An all-inversion-region MOST design methodology

applied to a ratioless differential LC-VCO

Rafaella Fiorelli1 , Fernando Silveira2 and Eduardo Peralı́as1
1
IMSE-CNM (CSIC) and Universidad de Sevilla, Seville, Spain.
2
Facultad de Ingenierı́a, Universidad de la República, Montevideo, Uruguay,
e-mail: [email protected]

Abstract—This paper presents a general optimization method- information provided by the foundry. As a hypothesis,
ology for analog blocks in RF applications, with CMOS nanome- MOST is considered to be working quasistatically, so its
ter technologies, based on the complete exploration of all-in- working frequency f0 is at least one tenth of its transition
version regions of MOS transistor (MOST). The fundamental
tool is the systematic use of the MOST gm /ID technique and frequency fT [3].
the description of the real behavior of all devices by means of 2) Passive semi-empirical modeling : Parasitic parameters
semi-empirical models. To exemplify this technique, the differen- extraction of passive components (inductors, capacitors,
tial ratioless cross-coupled LC-tank voltage controlled oscillator varactors and resistors) are expressed in LUTs, for the
(LC-VCO) circuit is studied. The implemented design flow working frequency f0 . Since for each nominal value of
minimizes the LC-VCO phase noise considering the constraints of
current consumption, output common-mode voltage and output the element, different geometries are possible, only the
amplitude. To verify the method, six LC-VCO were designed and best devices are included in the LUTs (e.g. devices with
validated by comparing them with the corresponding electrical the largest quality factor for each nominal value).
simulations. 3) Signal and noise analytical modeling : RF block core
Index Terms—Optimization, Low power, MOST all-inversion characteristics are modeled. When necessary, perform
regions, Design Methodology, LC-VCOs, RF
the equations modifications to link them with the device
characteristics described in steps 1) and 2).
I. I NTRODUCTION
4) Design Flow : Create a simple and systematic design
At present, the demands of low-cost, efficient and quick flow where the relations between block equations, ex-
time-to-market solutions oblige RF designers to use CMOS tracted parameters and necessary decisions are properly
nanometer technologies as well as accurate design methodolo- organized, all intended to fulfill the particular specifica-
gies applied prior to electrical simulations. It is particularly tions of the block and technological process constraints.
useful to observe the design’s trade-offs when low-power The paper is organized as follows. Section II presents the
constraints exist. This paper presents a general design method- way the CMOS process is modeled, dividing its study in
ology focused on nanometer technologies for analog RF the modeling of MOST and passive components. Section III
blocks that provides the electrical elements sizing as well as discuses the design flow of one particular RF circuit: the
the design compromises. The circuit used to exemplify the cross-coupled ratioless differential LC-VCO. Finally come the
technique is a cross-coupled differential LC-VCO in which Conclusions.
nMOS and pMOS transconductances can take different values
(ratioless LC-VCO). The design process is established over II. M ODELING OF NANOMETER CMOS PROCESSES
the exploration in all-inversion regions of the MOST, to find A good modeling of the process involved in the design
the best working zone. is necessary in order to correctly characterize its active and
We distinguish four main steps: passive devices. Not doing so would lead to substantial
1) MOST semi-empirical modeling : The MOST is char- mismatches between the circuit features observed at the de-
acterized as function of the gm /ID ratio, which defines sign level and after electrical simulation. MOST and passive
the MOST inversion region and has a biunivocal relation devices are modeled in this work using: a) semi-analytical
with the normalized current i = ID /(W/L) [1], [2], models whose parameters are in LUTs and depend on primary
with ID , W and L the MOST drain current, width and electrical magnitudes; and b) semi-empirical models whose
length, respectively. By measurements or simulations, data are in LUTs extracted from electrical simulations. These
the behavior of a small set of MOST is captured in models prove to be enough for RF applications at least until
look-up tables (LUTs). In them, gm /ID is related biuni- 5 GHz with our RF 1.2-V 90nm CMOS process.
vocally with basic MOST characteristics: transconduc-
tance gm , drain-source conductance gds , drain current A. MOS transistor model
0
ID , normalized intrinsic capacitances Cij , with ij = As a rule of thumb [4], for the 90nm CMOS technol-
{gs, gd, gb, bd, bs} and noise parameters. In this work, ogy used in this work, weak inversion (WI) is considered
these data are extracted via electrical simulation with the for gm /ID above 20 V −1 , strong inversion (SI) is below
 Figure 2. (a) Inductor parallel parasitic resistance Rp,ind versus inductance
Lind for a wide set of inductors’ sizes; and (b) capacitor series parasitic
resistance Rs,cap vs. capacitance Ccap for a wide set of capacitors’ size.

element, the associated parasitic and its physical size. Despite

this semi-empirical modeling is simple, it gives us good
Figure 1. MOST characteristics: (a) gm /ID vs. i; (b) gds /ID vs. gm /ID
0
and (c) Cij vs. gm /ID for a wide set of W .
results. The biunivocal relation between the best element’s
nominal value and its parasitic, e.g. between the inductor
inductance and its parasitic serial resistance, is very useful
gm /ID =10 V −1 and moderate inversion (MI) is in the midst of to generate a simple design flow.
them, as shown in Fig. 1. Our MOST semi-empirical model III. D ESIGN METHODOLOGY APPLIED TO AN LC-VCO
(semi-analytical for noise model) comprises LUTs with the The implementation of the two last steps of the general
following data: methodology of Section I are specific of each analog RF
1) gm /ID as function of the normalized current i, shown circuit. Here, we choose to study a cross-coupled differential
in Fig. 1.(a). The dependency of gm /ID with W , VDS LC-VCO, sketched in Fig. 3. Its special feature is that it
is slight and in a first approximation it can be neglected is a ratioless VCO, i.e. its nMOS and pMOS small-signal
if narrow devices with finger widths Wf <2 µm are transconductances gm,n and gm,p are not equal. Since both
discarded. transistors join the drain current ID , (gm /ID )n 6= (gm /ID )p .
2) gds /ID as function of gm /ID and VDS . The variation As gm /ID indicates the MOST inversion region, nMOS and
with W is very slight, as seen in Fig. 1.(b), and it is not pMOS transistors are in different inversion regions.
considered here. The design methodology here presented extends the work
0
3) Normalized capacitances Cij versus gm /ID , as seen in of the authors in [2], where these transconductances were
Fig. 1.(c). The spread with W and VDS is reasonably considered identical (ratioed LC-VCO). The removal of this
small, hence it is not considered in our approximation. bound permits to adjust the output amplitude voltage Aout ,
4) Noise parameters: a) thermal noise parameters γ/α [3], common-mode output voltage Vo,cm and phase noise play-
as function of gm /ID and VDS (variation with W can ing with nMOS and pMOS coupled-pairs (gm /ID )n and
be neglected in a first approximation); b) flicker noise (gm /ID )p ratios. To implement this idea, we use an analytical
parameter KF versus gm /ID , at f0 (dependency with LC-VCO small-signal modeling, resumed next.
W and VDS is very low and not considered here).
5) Overdrive voltage VOD = VGS − VT versus gm /ID (the A. LC-VCO signal modeling
spread of VOD with W and VDS is very low and it is Oscillation frequency and oscillation condition are
not included in our LUTs). 1
f0 = √
2π Lind Ctank
B. Passives model
gtank =(gm,n + gm,p )/(2 kosc ) (1)
The semi-empirical passive components’ models are ob-
tained via AC electrical simulations. The extraction of these with kosc the oscillation safety factor. Assuming that the
models depends on the topological location of the component; inductor parasitic conductance gind is much higher than the
for example, when the device has an AC grounded terminal varactor one (as the varactor parallel parasitic resistance is
or when it is fully differential. In Fig. 2, the plots of parallel around 20 kΩ), the tank capacitance and tank conductance are
parasitic resistance of inductance Lind and series parasitic CM OS,n + CM OS,p
resistance of capacitance Ccap are shown for f0 =2.45 GHz. Ctank =Cvar + + Cload (2)
2
The best devices are marked with a black thick line. The gds,p gds,n
gtank =gind + + (3)
LUT includes, for each best device, the nominal value of the 2 2
 when the phase noise is minimized, we consider (gm /ID )p
a thirty percent away from (gm /ID )n , that is (gm /ID )p ∈
(gm /ID )n · [0.7, 1.3] = Ψn,30% .
The corresponding design flow is organized as follows:
1) Start fixing a set of initial parameters: minimum tran-
sistor channel length Lmin , kosc , maximum equivalent
inductance Lind,max , minimum varactor capacitance
Cvar,min , Cload , and grids of Ψn,30% , ΦgmID,n and
ΦLind . Next, set the VCO specifications: f0 , maximum
current ID,max , maximum phase noise Lmax at an
offset ∆f , minimum output amplitude Aout,min and
Vo,cm ∈ [Vo,cm,min , Vo,cm,max ] [6].
2) Pick Lind,i and (gm ID )n,k from ΦLind and ΦgmID,n .
Figure 3. VCO (a) schematic and (b) small-signal equivalent circuit. 3) From the inductor LUT, derive gind of Lind,i .
0
Obtain in , (gds /ID )n and Cij,n from the picked
(gm /ID )n,k and the nMOS transistor LUTs.
with CM OS,n(p) the cross-coupled nMOS (pMOS) effective For each (gm /ID )p,j of Ψn,30% calculate the drain
capacitance (see Fig. 3), and Cvar and Cload the varactor and current ID,j from (4). Obtain ip,j and compute Wn,j and
load capacitances. The drain current is Wp,j from in , ip,j and ID,j . Compute gds,n(p) from the
2gind MOST LUTs. Finally, with (1) and (2) calculate Qtank
ID = 0 0 . (4) and Cvar .
(gm /ID )n 1/kosc,n + (gm /ID )p 1/kosc,p
0
Compute Vo,cm , Aout and L from [6], (5) and (6),
with kosc,n(p) = (1/kosc − gds,n(p) /gm,n(p) )−1 . The output respectively.
amplitude voltage is [5] If ID > ID,max , L > Lmax , Cvar < Cvar,min , Vo,cm ∈ /
8 2kosc [Vo,cm,min , Vo,cm,min ] or Aout < Aout,min discard this
Aout ∼
= , (5) (gm /ID )p and choose another j. If finishing covering
π (gm /ID )n + (gm /ID )p
all the elements of Ψn,30% , continue.
and Vo,cm , obtained using [6], depends on ID , Aout and the 4) From all the valid (gm /ID )p found in 3), find the
nMOS transistor aspect ratio. (gm /ID )p that minimizes the phase noise L.
Finally, the phase noise model of this structure in the white 5) If all points of ΦgmID,n are not covered return to 2)
noise zone when gm,n 6= gm,p is derived similarly as in [2], and increase k. Otherwise, find the k ∗ of ΦgmID,n that
and results in minimizes the phase noise Lik∗ . Then, if all points
!
π 2 Γ2rms   gm  g   f2
m 0
of ΦLind are not covered return to 2) and increase i,
L = 10log kB T ξn +ξp . otherwise the design is finished.
32 Q2tank ID ID n ID p ∆f 2
(6) The design flow is implemented in MATLAB rou-
where kB is the Boltzmann constant, T is the absolute tines, with f0 =2.45 GHz, ∆f =400 kHz, ID,max =0.9 mA,
temperature, Qtank the tank quality factor (with Qtank = Cvar,min =40 fF, Aout,min =0.4 V and Vo,cm =[0.2, 0.6] V. The
(ω0 Lind , gtank )−1 ), Γ is the Impulse Sensitive Function [7], family of curves of phase noise and power consumption,
f0 is the oscillation

frequency,  ∆f is the offset frequency and shown in Figure 4, are obtained for ratioed and ratioless
1 γ 1 VCOs. It is observed that lowest phase noise values are
ξn(p) = 2 α n(p) + kosc . The ratio γ/α is the thermal
noise parameter which depends on gm /ID , as we stated in reached in SI, and highest ones in WI; the contrary happens
Section II-A. for power consumption. It is also gathered that lower phase
noise and higher current are obtained when nMOS and pMOS
B. Design methodology flow transconductances are not equal.
This subsection details the proposed design flow developed Figure 6 presents the (gm /ID )p color plot versus (gm /ID )n
here to implement the last step of the methodology introduced and Lind . As expected, due to (6), the routine chooses the
in Section I. This design flow systematically obtains the minimum available (gm /ID )p for each (gm /ID )n , except
set of LC-VCOs that minimizes the phase noise for each when the constraints are not met (for low inductor values).
(gm /ID )n , with constraints in current consumption, output Figure 5 represents the minimum phase noise value achieved
common-mode voltage Vo,cm and output amplitude Aout . For for each feasible inductor. For small inductors, some imposed
the sake of simplifying the explanation, the optimization pro- restrictions are reached and the minimum valid (gm /ID )n
cess is implemented exhaustively in the whole design domain, raises, increasing the chosen (gm /ID )p and, from (6), the
being it all the feasible inductors Lind ∈ ΦLind and all the corresponding phase noise, as gathered in the inset of Fig. 5.
nMOS transistor inversion levels (gm /ID )n ∈ ΦgmID,n . From Table I lists six LC-VCOs in the three inversion regions (SI,
(4) and (6), to limit the increment of current consumption MI and WI) for various tank inductors values. The computed
 Table I
M ETHOD VALIDATION : COMPARISON BETWEEN RESULTS FROM M ATLAB AND S PECTRE RF SIMULATIONS .

(gm /ID )n (gm /ID )p Aout (V) Vo,cm (V) L@400kHz (dBc/Hz) Lind Rind ID Wn Wp Cvar
Design
(1/V) (1/V) Calc. Sim. Calc. Sim. Calc. Sim. (nH) (kΩ) (mA) (µm) (µm) (pF)
PSI1 10 7 0.9 1.16 0.51 0.54 -119.2 -118.2 2.6 0.64 0.73 15.1 25.9 1.36
PSI1 10 7 0.9 1.16 0.51 0.54 -110.6 -111.3 8.7 1.6 0.29 6.0 10.2 0.26
PMI1 16 11.3 0.56 0.72 0.39 0.37 -115.5 -115.3 2.6 0.64 0.45 44.8 41.9 1.27
PMI2 16 11.3 0.56 0.72 0.39 0.37 -113.3 -112.2 5.1 1.12 0.25 25.4 24.0 0.54
PWI1 20 14 0.45 0.58 0.28 0.29 -110.2 -109 5.1 1.12 0.20 115.3 36.0 0.38
PWI2 20 14 0.45 0.58 0.28 0.29 -113.6 -112.6 2.6 0.64 0.35 181 63.3 0.98

Figure 6. Color plot of (gm /ID )p versus (gm /ID )n and Lind . Zones
where constraints are not met are shadowed.

considering power, output amplitude and output common-

mode voltages constraints is developed and implemented in
Figure 4. Comparison of (a) phase noise and (b) drain current for three
real inductors considering ratioless(continuous line) and ratioed (broken line) MATLAB routines. Trade-offs between designing ratioed and
VCOs. ratioless LC-VCOs are given. Six LC-VCO designs were
simulated, whose characteristics match, with an acceptable
error, with the computed data.
V. ACKNOWLEDGMENTS
This work has been financed in part by the Junta de An-
daluca project P09-TIC-5386 and the Ministerio de Economia
y Competitividad project TEC2011-28302, both of them co-
financed by the FEDER program.
Figure 5. Minimum phase noise obtained from the design flow. The inset R EFERENCES
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