VIRTUAL MEMORY (REVISED VERSION)

Computer Operating Systems

Virtual Memory:
Virtual memory is a memory management capability of an OS that uses
hardware and software to allow a computer to compensate for physical memory
shortages by temporarily transferring data from random access memory (RAM)
to disk storage.
Virtual memory is the use of space on a hard disk drive (HDD) to simulate
additional main memory.
Memory is used to hold portions of the operating system, programs and data that
are currently in use or that are frequently used. Physically, main memory (also
referred to as primary memory) consists of random access memory (RAM) chips
that are combined into modules which, in turn, are inserted into slots on the
motherboard (i.e., the main circuit board) on a computer. The times required to
access different addresses (i.e., locations) in RAM are extremely short and nearly
equal, in contrast to the varying delay times for accessing locations on the HDD
and other storage devices.
In order to free up space in memory, an operating system with a virtual memory
capability transfers data that is not immediately needed from memory to the
HDD; when that data is needed again, it is copied back into memory. That is,
when all of the RAM is being used (e.g., if there are many programs open
simultaneously or if one very large program is in use), a computer with virtual
memory enabled will swap data to the HDD and back to memory as needed, thus,
in effect, increasing the total system memory.
Virtual memory permits software to run in a memory space (i.e., a logical
memory) whose size is greater than the computer's RAM. Most personal
computers sold today contain from 256MB to 1024MB of RAM. While this is
huge in comparison to what was common just a few years ago, it is still often
insufficient to simultaneously run all of the programs that users attempt to run.
The reason is that the size of many programs has continued to increase
accompanying the growth in memory sizes and HDD capacities, largely in order
to add more features (including fancier graphics).
Application programs cannot distinguish between primary memory and virtual
memory, and thus they run as if all the data is in primary memory. Virtual
memory is likewise usually invisible to the user. However, its existence can
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become apparent in the form of degraded performance if it is used too heavily,

because the CPU (central processing unit) will spend more of its time copying
data back and forth to the HDD and less of its time doing useful work. This is
termed thrashing. The reduced efficiency is also a result of the facts that HDDs
are far slower than RAM and that they are not designed for accessing small pieces
of data (e.g., single bytes) one at a time.
Virtual memory has become a standard feature of most operating systems on
desktop and notebook computers. This is because it provides a large benefit to
users at a very low cost. That is, the cost of hard disk space is only a small fraction
of that of an equal amount of RAM, and thus it pays to install, and use, more of
the former and less of the latter.
The space on a HDD that is used to store the overflow from memory is called
swap space. On Linux it is a separate partition (i.e., a logically independent
section of a HDD) that is set up during installation of the operating system and
which is referred to as the swap partition. It is generally recommended that the
size of the swap partition be about twice the amount of system RAM.
The swap space is divided into segments called pages, each of which is associated
with a specific address in memory. When an address is referenced, the page is
swapped into memory. It is returned to the disk when no longer needed and other
pages are called. This management of virtual memory is performed by a type of
hardware circuitry called a memory management unit (MMU).
Most CPUs now include built-in MMU circuitry, which improves performance
as compared with separate MMU chips. In order to facilitate this switching, CPUs
also maintain a table of recently used main-to-virtual memory translations, called
a translation lookaside buffer (TLB).
The origin of virtual memory is not entirely clear. It was apparently first
employed at the University of Manchester in the UK for the Atlas Computer,
which was completed in 1962. However, Fritz-Rudolf Güntsch, a German
computer scientist who developed the Telefunken TR 440 mainframe, claims to
have first proposed the concept in his doctoral dissertation in 1957. Virtual
memory was incorporated into the UNIX kernel (i.e., the core of the operating
system) in the 1970s as part of the Berkeley Extensions, which were developed at
the University of California at Berkeley (UCB).

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Virtual memory is so important that its acronym, i.e., vm, was incorporated into
the name of the Linux kernel as it is used on most systems, i.e., vmlinux for the
non-compressed version and vmlinuz for the compressed, bootable (i.e., runnable)
version.
 Recall: memory allocation with variable partitions requires mapping
logical addresses to physical addresses
 Virtual memory achieves a complete separation of logical and physical
address-spaces
 Today, typically a virtual address is 32 bits, this allows a process to have
4GB of virtual memory
 Physical memory is much smaller than this, and varies from machine to
machine
 Virtual address spaces of different processes are distinct
 Structuring of virtual memory
 Paging: Divide the address space into fixed-size pages
 Segmentation: Divide the address space into variable-size segments
(corresponding to logical units)
Memory paging is a memory management technique for controlling how a
computer or virtual machine's (VM's) memory resources are shared. A computer
can address memory beyond the amount physically installed on the system. ...
The portion of the hard disk that acts as physical memory is called a page file.

Paging (1)

The position and function of the MMU

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Paging
 Physical memory is divided into chunks called page-frames (on Pentium,
each page-frame is 4KB).
 Virtual memory is divided into chunks called pages; size of a page is equal
to size of a page frame
 So typically, 220 pages (a little over a million) in virtual memory
 OS keeps track of mapping of pages to page-frames
 Some calculations:
1. 10-bit address : 1KB of memory; 1024 addresses
2. 20-bit address : 1MB of memory; about a million addresses
3. 30-bit address : 1 GB of memory; about a billion addresses
Paging (2):
The Relation between virtual addresses and physical memory addresses given by
page Table:

Virtual Memory in UNIX:

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It allows us to run more applications on the system than we have enough physical
memory to support. Virtual memory is simulated memory that is written to a
file on the hard drive. That file is often called page file or swap file. It's used by
operating systems to simulate physical RAM by using hard disk space.

 A virtual address is considered as a pair (p,o)

1. Low-order bits give an offset o within the page
2. High-order bits specify the page p
 E.g. If each page is 1KB and virtual address is 16 bits, then low-order 10
bits give the offset and high-order 6 bits give the page number
 The job of the Memory Management Unit (MMU) is to translate the page
number p to a frame number f
** The physical address is then (f,o), and this is what goes on the memory
bus
 For every process, there is a page-table (basically, an array), and page-
number p is used as an index into this array for the translation

Page Table Entry:

1. Validity bit: Set to 0 if the corresponding page is not in memory

2. Frame number
o Number of bits required depends on size of physical memory
3. Protection bits:
o Read, write, execute accesses

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4. Referenced bit is set to 1 by hardware when the page is accessed:

used by page replacement policy
5. Modified bit (dirty bit) set to 1 by hardware on write-access: used to
avoid writing when swapped out
Internal Operation of MMU with 16 4KB Pages.

Design Issues:
In a operating systems that use paging for memory management, page
replacement algorithm are needed to decide which page needed to be replaced
when new page comes in. Whenever a new page is referred and not present in
memory, page fault occurs and Operating System replaces one of the existing
pages with newly needed page. Different page replacement algorithms suggest
different ways to decide which page to replace. The target for all algorithms is to
reduce number of page faults.
1. What is the “optimal” size of a page frame ?

Typically 1KB – 4KB, but more on this later

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2. How to save space required to store the page table

With 20-bit page address, there are over a million pages, so the page-table
is an array with over million entries
Solns: Two-level page tables, TLBs (Translation Look a side Beffers),
Inverted page tables
3. What if the desired page is not currently in memory?
This is called a page fault, and it traps to kernel
Page daemon runs periodically to ensure that there is enough free memory
so that a page can be loaded from disk upon a page fault
A page fault is a type of interrupt, raised by the hardware when a running
program accesses a memory page that is mapped into the virtual address space,
but not loaded in physical memory.
4. Page replacement policy: how to free memory?
Whenever a new page is referred and not present in memory, page fault
occurs and Operating System replaces one of the existing pages with newly
needed page. Different page replacement algorithms suggest different ways to
decide which page to replace. The target for all algorithms is to reduce number
of page faults.
When should page replacement policy be invoked:
• on a page fault
• independent of page faults (a paging daemon)
Page Replacement Algorithms :
 First In First Out (FIFO) –
This is the simplest page replacement algorithm. In this algorithm,
operating system keeps track of all pages in the memory in a queue, oldest
page is in the front of the queue. When a page needs to be replaced page in
the front of the queue is selected for removal.
For example-1, consider page reference string 1, 3, 0, 3, 5, 6 and 3 page slots.
Initially all slots are empty, so when 1, 3, 0 came they are allocated to the empty
slots —> 3 Page Faults.

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when 3 comes, it is already in memory so —> 0 Page Faults.

Then 5 comes, it is not available in memory so it replaces the oldest page slot
i.e 1. —>1 Page Fault.
Finally 6 comes, it is also not available in memory so it replaces the oldest page
slot i.e 3 —>1 Page Fault.
Example-2, Let’s have a reference string: a, b, c, d, c, a, d, b, e, b, a, b, c, d and
the size of the frame be 4.

There are 9 page faults using FIFO algorithm.

Belady’s anomaly – Belady’s anomaly proves that it is possible to have more
page faults when increasing the number of page frames while using the First in
First Out (FIFO) page replacement algorithm. For example, if we consider
reference string 3, 2, 1, 0, 3, 2, 4, 3, 2, 1, 0, 4 and 3 slots, we get 9 total page
faults, but if we increase slots to 4, we get 10 page faults.
 Optimal Page replacement –
In this algorithm, pages are replaced which are not used for the longest
duration of time in the future.
Let us consider page reference string 7 0 1 2 0 3 0 4 2 3 0 3 2 and 4 page slots.
Initially all slots are empty, so when 7 0 1 2 are allocated to the empty slots —>
4 Page faults
0 is already there so —> 0 Page fault.
when 3 came it will take the place of 7 because it is not used for the longest
duration of time in the future.—>1 Page fault.
0 is already there so —> 0 Page fault..
4 will takes place of 1 —> 1 Page Fault.

Now for the further page reference string —> 0 Page fault because they are
already available in the memory.
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Example-2, Let’s have a reference string: a, b, c, d, c, a, d, b, e, b, a, b, c, d and

the size of the frame be 4.

There are 6 page faults using optimal algorithm.

Optimal page replacement is perfect, but not possible in practice as operating
system cannot know future requests. The use of Optimal Page replacement is to
set up a benchmark so that other replacement algorithms can be analyzed
against it.
 Least Recently Used –
In this algorithm page will be replaced which is least recently used.
Let say the page reference string 7 0 1 2 0 3 0 4 2 3 0 3 2 . Initially we have 4
page slots empty.
Initially all slots are empty, so when 7 0 1 2 are allocated to the empty slots —>
4 Page faults
0 is already their so —> 0 Page fault.
when 3 came it will take the place of 7 because it is least recently used —>1
Page fault
0 is already in memory so —> 0 Page fault.
4 will takes place of 1 —> 1 Page Fault
Now for the further page reference string —> 0 Page fault because they are
already available in the memory.
Example-2, Let’s have a reference string: a, b, c, d, c, a, d, b, e, b, a, b, c, d and
the size of the frame be 4.

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There are 7 page faults using LRU algorithm.

Multi Level Paging:
 Keeping a page-table with 220 entries in memory is not viable
 Solution: Make the page table hierarchical
 Pentium supports two-level paging
 Suppose first 10-bits index into a top-level page-entry table T1
(1024 or 1K entries)
 Each entry in T1 points to another, second-level, page table
with 1K entries (4 MB of memory since each page is 4KB)
 Next 10-bits of physical address index into the second-level
page-table selected by the first 10-bits
 Total of 1K potential second-level tables, but many are likely to be unused
 If a process uses 16 MB virtual memory then it will have only 4
entries in top-level table (rest will be marked unused) and only 4
second-level tables

Paging in LINUX:
Linux Uses 3 Level Page Tables. Figure.shows the model, which defines three
types of paging tables.
o Page Global Directory
o Page Middle Directory
o Page Table

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Linux uses demand paging to load executable images into a process's virtual
memory. Whenever a command is executed, the file containing it is opened and
its contents are mapped into the process's virtual memory.
The Page Global Directory includes the addresses of several Page Middle
Directories, which in turn include the addresses of several Page Tables. Each
Page Table entry points to a page frame. The linear address is thus split into four
parts. Figure.does not show the bit numbers because the size of each part depends
on the computer architecture.
Linux’s handling of processes relies heavily on paging. In fact, the automatic
translation of linear addresses into physical ones makes the following design
objectives feasible:
o Assign a different physical address space to each process, ensuring an
efficient protection against addressing errors.
o Distinguish pages (groups of data) from page frames (physical addresses
in main memory). This allows the same page to be stored in a page frame,
then saved to disk and later reloaded in a different page frame. This is the
basic ingredient of the virtual memory mechanism

Translation Lookaside Buffer (TLB)

A translation lookaside buffer (TLB) is a memory cache that stores recent
translations of virtual memory to physical addresses for faster retrieval.
When a virtual memory address is referenced by a program, the search starts in
the CPU. First, instruction caches are checked. If the required memory is not in
these very fast caches, the system has to look up the memory’s physical address.

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At this point, TLB is checked for a quick reference to the location in physical
memory.
When an address is searched in the TLB and not found, the physical memory
must be searched with a memory page crawl operation. As virtual memory
addresses are translated, values referenced are added to TLB. When a value can
be retrieved from TLB, speed is enhanced because the memory address is stored
in the TLB on processor. Most processors include TLBs to increase the speed of
virtual memory operations through the inherent latency-reducing proximity as
well as the high-running frequencies of current CPU’s.
TLBs also add the support required for multi-user computers to keep memory
separate, by having a user and a supervisor mode as well as using permissions on
read and write bits to enable sharing.
TLBs can suffer performance issues from multitasking and code errors. This
performance degradation is called a cache thrash. Cache thrash is caused by an
ongoing computer activity that fails to progress due to excessive use of resources
or conflicts in the caching system.
 Page-tables are in main memory
 Access to main memory is slow compared to clock cycle on CPU (10ns
vs 1 ns)
 An instruction such as MOVE REG, ADDR has to decode ADDR
and thus go through page tables
 This is way too slow !!
 Standard practice: Use TLB stored on CPU to map pages to page-frames
 TLB stores small number (say, 64) of page-table entries to avoid the
usual page-table lookup
 TLB is associative memory and contains, basically, pairs of the form
(page-no, page-frame)
 Special hardware compares incoming page-no in parallel with all
entries in TLB to retrieve page-frame
If no match found in TLB, standard look-up invoked
 Key design issue: how to improve hit rate for TLB?
 Which pages should be in TLB: most recently accessed
 Who should update TLB?

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 Modern architectures provide sophisticated hardware support to

do this
 Alternative: TLB miss generates a fault and invokes OS, which
then decides how to use the TLB entries effectively.

Inverted Page Tables

 When virtual memory is much larger than physical memory,
overhead of storing page-table is high
 For example, in 64-bit machine with 4KB per page and 256 MB
memory, there are 64K page-frames but 252 pages !
 Solution: Inverted page tables that store entries of the form (page-frame,
process-id, page-no)
 At most 64K entries required!
 Given a page p of process x, how to find the corresponding page
frame?
 Linear search is too slow, so use hashing
 Note: issues like hash-collisions must be handled
 Used in some IBM and HP workstations; will be used more with 64-bit
machines

Steps in Paging:
 Today’s typical systems use TLBs and multi-level paging
 Paging requires special hardware support
 Overview of steps
1. Input to MMU: virtual address = (page p, offset o)
2. Check if there is a frame f with (p,f) in TLB

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3. If so, physical address is (f,o)

4. If not, lookup page-table in main memory ( a couple of accesses due to
multi-level paging)
5. If page is present, compute physical address
6. If not, trap to kernel to process page-fault
7. Update TLB/page-table entries (e.g. Modified bit)
Page Fault Handing:
 Hardware traps to kernel on page fault
 CPU registers of current process are saved
 OS determines which virtual page needed
 OS checks validity of address, protection status
 Check if there is a free frame, else invoke page replacement policy
to select a frame
 If selected frame is dirty, write it to disk
 When page frame is clean, schedule I/O to read in page
 Page table updated
 Process causing fault rescheduled
 Instruction causing fault reinstated (this may be tricky!)
 Registers restored, and program continues execution
Paging Summary:
 How long will access to a location in page p take?
 If the address of the corresponding frame is found in TLB?
 If the page-entry corresponding to the page is valid?
 Using two-level page table
 Using Inverted hashed page-table

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 If a page fault occurs?

 How to save space required to store a page table?
 Two-level page-tables exploit the fact only a small and contiguous
fraction of virtual space is used in practice
 Inverted page-tables exploit the fact that the number of valid page-table
entries is bounded by the available memory
 Note: Page-table for a process is stored in user space

Page Replacement Algorithm:

 When should a page be replaced
Upon a page fault if there are no page frames available
By pager daemon executed periodically
 Pager daemon needs to keep free page-frames
Executes periodically (e.g. every 250 msec in Unix)
If number of free page frames is below certain fraction (a settable
parameter), then decides to free space
 Modified pages must first be saved
unmodified just overwritten
 Better not to choose an often used page
will probably need to be brought back in soon
 Well-understood, practical algorithms
 Useful in other contexts also (e.g. web caching)

Reference String:
Def: The virtual space of a process consists of N = {1,2,…,n} pages.

A process reference string w is the sequence of pages referenced by a

process for a given input:

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w = r1 r2 … rk … rT
where rk ∈ N is the page referenced on the kth memory reference.

E.g., N = {0,...,5}.

w=003455522212221100

Given f page frames,

• warm-start behavior of the replacement policy

• cold-start behavior of the replacement policy

Forward and Backward Distances:

Def: The forward distance for page X at time t, denoted by dt(X), is

dt(X) = k if the first occurrence of X in rt+1 rt+2 …at rt+k.

dt(X) = ∞ if X does not appear in rt+1 rt+2 ….

Def: The backward distance for page X at time t, denoted by bt(X), is

bt(X) = k if rt-k was the last occurrence of X.
bt(X) = ∞ if X does not appear in r1 r2 … rt-1.

Paging Replacement Algorithms:

Random -- Worst implementable method, easy to implement.

2FIFO - Replace the longest resident page. Easy to implement since

control information is a FIFO list of pages.
Consider a program with 5 pages and reference string

w = 1 2 3 4 1 2 5 1 2 3 4 5 Suppose there are 3 page frames.

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Optimal Page Replacement Algorithm

 If we knew the precise sequence of requests for pages, we
can optimize for least number of faults

 Replace page needed at the farthest point in future

Optimal but unrealizable

 Off-line simulations can estimate the performance of this

algorithm, and be used to measure how well the chosen scheme
is doing
Competitive ratio of an algorithm = (page-faults generated by
optimal policy)/(actual page faults)
 Consider reference string: 1 2 3 4 1 2 5 1 2 3 2 5
 Consider a program with 5 pages and reference string
w = 1 2 3 4 1 2 5 1 2 3 4 5 Suppose there are 3 page frames.
w=123412512345
PF 1
PF 2
PF 3
victim
 Use reference bit and modified bit in page-table entry
Both bits are initially 0
Read sets reference to 1, write sets both bits to 1
Reference bit cleared on every clock interrupt (40ms)

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 Prefer to replace pages unused in last clock cycle

First, prefer to keep pages with reference bit set to 1
Then, prefer to keep pages with modified bit set to 1

 Easy to implement, but needs additional strategy to resolve ties

 Note: Upon a clock interrupt, OS updates CPU-usage

counters for scheduling in PCB as well as reference bits in page
tables

Queue Based Algorithm:

 FIFO
 Maintain a linked list of pages in memory in order of arrival
 Replace first page in queue
 Easy to implement, but access info not used at all
 Modifications
 Second-chance
 Clock algorithm

Second Chance Page Replacement:

 Pages ordered in a FIFO queue as before

 If the page at front of queue (i.e. oldest page) has Reference
bit set, then just put it at end of the queue with R=0, and try again
 Effectively, finds the oldest page with R=0, (or the first one
in the original queue if all have R=1)
 Easy to implement, but slow !!

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Clock Algorithm:
 Optimization of Second chance
 Keep a circular list with current pointer
 If current page has R=0 then replace, else set R to 0 and move current
pointer

Least Recently Used (LRU):

 Assume pages used recently will be used again soon
throw out page that has been unused for longest time
 Consider the following references assuming 3 frames
123412512325

 This is the best method that is implementable since the past

is usually a good indicator for the future.

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 It requires enormous hardware assistance: either a fine-grain

timestamp for each memory access placed in the page table, or a
sorted list of pages in the order of references.
How to Implement LRU?
 Main challenge: How to implement this?
Reference bit not enough
 Highly specialized hardware required
 Counter-based solution
Maintain a counter that gets incremented with each memory access,
Copy the counter in appropriate page table entry
On page-fault pick the page with lowest counter
 List based solution
Maintain a linked list of pages in memory
On every memory access, move the accessed page to end
Pick the front page on page fault

Approximating LRU: Aging

 Bookkeeping on every memory access is expensive
 Software solution: OS does this on every clock interrupt
 Every page-entry has an additional 8-bit counter
 Every clock cycle, for every page in memory, shift the
counter 1 bit to the right copying R bit into the high-order bit of
the counter, and clear R bit
 On page-fault, or when pager daemon wants to free up
space, pick the page with lowest counter value
 Intuition: High-order bits of recently accessed pages are set
to 1 (i-th high-order bit tells us if page was accessed during i-th
previous clock-cycle)
 Potential problem: Insufficient info to resolve ties
Only one bit info per clock cycle (typically 40ms)
Info about accesses more than 8 cycles ago lost

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Analysis of Paging Algorithm:

 Reference string r for a process is the sequence of pages
referenced by the process
 Suppose there are m frames available for the process, and
consider a page replacement algorithm A
We will assume demand paging, that is, a page is brought in only
upon fault
 Let F(r,m,A) be the faults generated by A
 Belady’s anomaly: allocating more frames may increase the
faults: F(r,m,A) may be smaller than F(r,m+1,A)

 Worth noting that in spite of decades of research

Worst-case performance of all algorithms is pretty bad
Increase m is a better way to reduce faults than improving A
(provided we are using a stack algorithm)

Effects of Replacement Policy:

 Evaluate a page replacement policy by observing how it behaves
on a given page-reference string.

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Belady’s Anomaly:
For FIFO algorithm, as the following counter-example shows,
increasing m from 3 to 4 increases faults

Stack Algorithms:

 For an algorithm A, reference string r, and page-frames m, let P(r,m,A) be

the set of pages that will be in memory if we run A on references r using m
frames

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 An algorithm A is called a stack algorithm if for all r and for all m,

P(r,m,A) is a subset of P(r,m+1,A)
 Intuitively, this means the set of pages that A considers relevant grows
monotonically as more memory becomes available
 For stack algorithms, for all r and for all m, F(r,m+1,A) cannot be more
than F(r,m,A) (so increasing memory can only reduce faults!)
 LRU is a stack algorithm: P(r,m,LRU) should be the last m pages in r,
so P(r,m,LRU) is a subset of P(r,m+1,LRU)

Thrashing:

Will the CPU Utilization increase monotonically as the degree

Of multiprogramming (number of processes in memory) increases?

Not really! It increases for a while, and then starts dropping again.

Reason: With many processes around, each one has only a few pages
in memory, so more frequent page faults, more I/O wait, less CPU
utilization

Locality Of Reference:

 To avoid thrashing (i.e. too many page faults), a process needs

“enough” pages in the memory

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 Memory accesses by a program are not spread all over its virtual
memory randomly, but show a pattern
E.g. while executing a procedure, a program is accessing the page that
contains the code of the procedure, the local variables, and global vars
 This is called locality of reference
 How to exploit locality?
Pre-paging: when a process is brought into memory by the swapper, a few
pages are loaded in a priori (note: demand paging means that a page is
brought in only when needed)
Working set: Try to keep currently used pages in memory

Locality:

 The phenomenon that programs actually use only a limited set

of pages during any particular time period of execution.
 This set of pages is called the locality of the program during that
time.
 Ex. Program phase diagram

 The working set of a process is the set of all pages accessed by the
process within some fixed time window.
Locality of reference means that a process's working set is usually small
compared to the total number of pages it possesses.

 A program's working set at the k-th reference with window size h is

defined to be
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W(k,h) = { i ∈ N | page i appears among rk-h+1 … rk }

 The working set at time t is

W(t,h) = W(k,h) where time(rk) ≤ t < t(rk+1)

 Ex. h=4

 Working set of a process at time t is the set of pages

referenced over last k accesses (here, k is a parameter)
 Goal of working set based algorithms: keep the working set
in memory, and replace pages not in the working set
 Maintaining the precise working set not feasible (since we
don’t want to update data structures upon every memory access)
 Compromise: Redefine working set to be the set of pages
referenced over last m clock cycles
 Recall: clock interrupt happens every 40 ms and OS can
check if the page has been referenced during the last cycle (R=1)
 Complication: what if a process hasn’t been scheduled for a
while? Shouldn’t “over last m clock cycles” mean “over last m
clock cycles allotted to this process”?

Virtual Time and Working Set:

 Each process maintains a virtual time in its PCB entry

** This counter should maintain the number of clock cycles that the
process has been scheduled
 Each page table entry maintains time of last use (wrt to the process’s
virtual time)
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 Upon every clock interrupt, if current process is P, then increment

virtual time of P, and for all pages of P in memory, if R = 1, update “time of
last use” field of the page to current virtual time of P
 Age of a page p of P = Current virtual time of P minus time of last use of
p
 If age is larger than some threshold, then the page is not in the working
set, and should be evicted

WSClock Replacement Algorithm:

 Combines working set with clock algorithm

 Each page table entry maintains modified bit M
 Each page table entry maintains reference bit R indicating
whether used in the current clock cycle
 Each PCB entry maintains virtual time of the process
 Each page table entry maintains time of last use
 List of active pages of a process are maintained in a ring with a
current pointer

WSClock Algorithm:

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Maintain reference bit R and dirty bit M for each page

Maintain process virtual time in each PCB entry

Maintain Time of last use for each page (age=virtual time – this field)

To free up a page-frame, do:

 Examine page pointed by Current pointer

 If R = 0 and Age > Working set window k and M = 0 then add this
page to

list of free frames

 If R = 0 and M = 1 and Age > k then schedule a disk write, advance

current,

and repeat

 If R = 1or Age <= k then clear R, advance current, and repeat

 If current makes a complete circle then

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 If some write has been scheduled then keep advancing current till
some

write is completed

 If no write has been scheduled then all pages are in working set so
pick a

page at random (or apply alternative strategies)

Page Replacement in UNIX:

 Unix uses a background process called paging daemon that tries to

maintain a pool of free clean page-frames

 Every 250ms it checks if at least 25% (a adjustable parameter) frames

are free

 selects pages to evict using the replacement algorithm

 Schedules disk writes for dirty pages

 Two-handed clock algorithm for page replacement

 Front hand clears R bits and schedules disk writes (if needed)

 Page pointed to by back hand replaced (if R=0 and M=0)

UNIX and Swapping:

 Under normal circumstances pager daemon keeps enough pages free

to avoid thrashing. However, when the page daemon is not keeping up
with the demand for free pages on the system, more drastic measures
need be taken: swapper swaps out entire processes

 The swapper typically swaps out large, sleeping processes in order to

free memory quickly. The choice of which process to swap out is a
function of process priority and how long process has been in main

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memory. Sometimes ready processes are swapped out (but not until
they've been in memory for at least 2 seconds).

 The swapper is also responsible for swapping in ready-to-run but

swapped-out processes (checked every few seconds)

Local Vs Global Policy:

Paging algorithm can be applied either

1. locally: the memory is partitioned into “workspace”, one for each

process.

(a) equal allocation: if m frames and n processes then m/n frames.

(b) proportional allocation: if m frames & n processes, let si be the size

of Pi.

2. globally: the algorithm is applied to the entire collection of running

programs. Susceptible to thrashing (a collapse of performance due to
excessive page faults).

Thrashing directly related to the degree of multiprogramming.

PFF (Page Fault Frequency):

 direct way to control page faults.

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 Program restructuring to improve locality at compile-time at run-time

(using information saved during exec)

Data Structure on Page Faults:

int a[128][128]

for (j=0, j<128, j++)

for (i=0, i<128, i++)

a[i,j]=0

for (i=0, i<128, i++)

for (j=0, j<128, j++)

a[i,j]=0

** C row first FORTRAN column first **

OS has to determine the size of a page:

 Does it have to be same as size of a page frame (which is determined

by hardware)? Not quite!

Arguments for smaller page size:

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 Less internal fragmentation (unused space within pages)

 Can match better with locality of reference

Arguments for larger page size

 Less number of pages, and hence, smaller page table

 Less page faults

 Less overhead in reading/writing of pages

Page Size:

1. (to reduce) table fragmentation ⇒ larger page

2. internal fragmentation ⇒ smaller page
3. read/write i/o overhead for pages ⇒ larger page
4. (to match) program locality (& therefore to reduce total i/o) ⇒
smaller page
5. number of page faults ⇒ larger page

THM. (Optimal Page Size)

 (wrt factors 1 & 2)

Let c1 = cost of losing a word to table fragmentation and c2 = cost of

losing a word to internal fragmentation.

Assume that each program begins on a page boundary.

If the avg program size s0 is much larger than the page size z, then the
optimal page size z0 is approximately √2cs0 where c = c1 /c2.

 Proof.

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Page Size Examples:

 c1=c2=1

Z S0 f=Z/S0× 100%
8 32 25
16 128 13
32 512 6
64 2K 3
128 8K 1.6
256 32K .8
512 128K .4
1024 512K .2

 c1 > c2⇒ larger page than above (need cache) c1 < c2 (unlikely)
⇒smaller

GE645 64 word & 1024-word pages

IBM/370 2K & 4K

VAX 512bytes

Berkeley Unix 2 x 512 = 1024

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Page Size: Trade Fault

Overhead due to Page table

Sharing of Pages:

 Can two processes share pages (e.g. for program text)

 Solution in PDP-11:

 Use separate address space and separate page table for

instructions (I space) and data (D space)
 Two programs can share same page tables in I space

 Alternative: different entries can point to the same page

 Careful management of access writes and page replacement

needed

 In most versions of Unix, upon fork, parent and child use same pages
but have different page table entries

 Pages initially are read-only

 When someone wants to write, traps to kernel, then OS copies the
page and changes it to read-write (copy on write)

Shared Pages with Separate Page Tables:

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Two Processes Sharing Same Pages with “Copy on Write”.

Segmentation:

Memory segmentation is the division of a computer's primary memory

into segments or sections. In a computer system using segmentation, a
reference to a memory location includes a value that identifies a
segment and an offset (memory location) within that segment.

 Recall: Paging allows mapping of virtual addresses to physical

addresses and is transparent to user or to processes

 Orthogonal concept: Logical address space is partitioned into

logically separate blocks (e.g. data vs code) by the process (or by the
compiler) itself

 Logical memory divided into segments, each segment has a size

(limit)

 Logical address is (segment number, offset within seg)

 Note: Segmentation can be with/without virtual memory and paging

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 Conceptual similarity to threads: threads is a logical organization

within a process for improving CPU usage, segments are for improving
memory usage

Implementation Without Paging:

Advantages:

 Address allocation is easy for compiler

 Different segments can grow/shrink independently

 Natural for linking separately compiled code without worrying about

relocation of virtual addresses

 Just allocate different segments to different packages

 Application specific

 Large arrays in scientific computing can be given their own

segment (array bounds checking redundant)

 Natural for sharing libraries

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 Different segments can have different access protections

 Code segment can be read-only

 Different segments can be managed differently

Segmentation without Paging:

 Address space within a segment can be virtual, and managed using

page tables

 Same reasons as we saw for non-segmented virtual memory

 Two examples

 Multics
 Pentium

 Steps in address translation

1. Check TLB for fast look-up

2. Consult segment table to locate segment descriptor for s

3. Page-table lookup to locate the page frame (or page fault)

Multics: Segmentation + Paging

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Multics Memory

 34-bit address split into 18-bit segment no, and 16 bit (virtual) address
within the segment

 Thus, each segment has 64K words of virtual memory

 Physical memory address is 24 bits, and each page frame is of size

1K

 Address within segment is divided into 6-bit page number and 10-bit
offset

 Segment table has potentially 256K entries

 Each segment entry points to page table that contains upto 64 entries

 Segment table entry is 36 bits consisting of

 main memory address of page table (but only 18 bits needed, last
6 bits assumed to be 0)
 Length of segment (in terms of number of pages, this can be used
for a limit check)
 Protection bits

 More details

 Different segments can have pages of different sizes

 Segment table itself can be in a segment itself (and can be paged!)

 Memory access first has to deal with segment table and then with
page table before getting the frame

 TLBs absolutely essential to make this work!

Pentium:

 16K segments divided into LDT and GDT (Local/Global Descriptor

Tables)

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 Segment selector: 16 bits

 1 bit saying local or global

 2 bits giving protection level
 13 bits giving segment number

 Special registers on CPU to select code segment, data segment etc

 Incoming address: (selector,offset)

 Selector is added to base address of segment table to locate segment

descriptor

 Phase 1: Use the descriptor to get a “linear” address

 Limit check
 Add Offset to base address of segment

Segmentation with paging: Pentium

In many ways, the virtual memory on the Pentium resembles that of MULTICS,
including the presence of both segmentation and paging. Whereas MULTICS has
256K independent segments, each up to 64K 36-bit words, the Pentium has 16K
independent segments, each holding up to 1 billion 32-bit words. Although there
are fewer segments, the larger segment size is far more important, as few
programs need more than 1000 segments, but many programs need large
segments.

The heart of the Pentium virtual memory consists of two tables, called the LDT
(Local Descriptor Table) and the GDT (Global Descriptor Table). Each program
has its own LDT, but there is a single GDT, shared by all the programs on the
computer. The LDT describes segments local to each program, including its code,
data, stack, and so on, whereas the GDT describes system segments, including
the operating system itself.

To access a segment, a Pentium program first loads a selector for that segment
into one of the machine's six segment registers. During execution, the CS register
holds the selector for the code segment and the DS register holds the selector for
the data segment. The other segment registers are less important. Each selector is

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a 16-bit number, as shown in Figure 1.

One of the selector bits tells whether the segment is local or global (i.e., whether
it is in the LDT or GDT). Thirteen other bits specify the LDT or GDT entry
number, so these tables are each restricted to holding 8K segment descriptors.
The other 2 bits relate to protection and will be explained later. Descriptor 0 is
forbidden. It may be safely loaded into a segment register to indicate that the
segment register is not currently available. It causes a trap if used.

At the time a selector is loaded into a segment register, the corresponding

descriptor is fetched from the LDT or GDT and stored in microprogram
registers, so it can be accessed quickly. As shown in Figure 2, a descriptor
consists of 8 bytes, including the segment's base address, size, and other
information.

The format of the selector has been cleverly chosen to make locating the
descriptor easy. First either the LDT or GDT is selected, based on selector bit 2.
Then the selector is copied to an internal scratch register, and the 3 low-order bits
set to 0. Finally, the address of either the LDT or GDT table is added to it, to give
a direct pointer to the descriptor. For example, selector 72 refers to entry 9 in the
GDT, which is located at address GDT + 72.

Let us trace the steps by which a (selector, offset) pair is converted to a physical
address. As soon as the microprogram knows which segment register is being
used, it can find the complete descriptor corresponding to that selector in its
internal registers. If the segment does not exist (selector 0), or is currently paged
out, a trap occurs.

The hardware then uses the Limit field to check if the offset is beyond the end of
the segment, in which case a trap also occurs. Logically, there should be a 32-bit

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field in the descriptor giving the size of the segment, but there are only 20 bits

available, so a different scheme is used. If the Gbit (Granularity) field is 0, the

Limit field is the exact segment size, up to 1 MB. If it is 1, the Limit field gives
the segment size in pages instead of bytes. The Pentium page size is fixed at 4
KB, so 20 bits are enough for segments up to 232 bytes.

Assuming that the segment is in memory and the offset is in range, the Pentium
then adds the 32-bit Base field in the descriptor to the offset to form what is called
a linear address, as shown in Figure 3. The Base field is broken up into three
pieces and spread all over the descriptor for compatibility with the 286, in which
the Base is only 24 bits. In effect, the Base field allows each segment to start at
an arbitrary place within the 32-bit linear address space.

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If paging is disabled (by a bit in a global control register), the linear address is
interpreted as the physical address and sent to the memory for the read or write.
Thus with paging disabled, we have a pure segmentation scheme, with each
segment's base address given in its descriptor. Segments are not prevented from
overlapping, probably because it would be too much trouble and take too much
time to verify that they were all disjoint.

On the other hand, if paging is enabled, the linear address is interpreted as a

virtual address and mapped onto the physical address using page tables, pretty
much as in our earlier examples. The only real complication is that with a 32-bit
virtual address and a 4-KB page, a segment might contain 1 million pages, so a
two-level mapping is used to reduce the page table size for small segments.

Each running program has a page directory consisting of 1024 32-bit entries. It is
located at an address pointed to by a global register. Each entry in this directory
points to a page table also containing 1024 32-bit entries. The page table entries
point to page frames. The scheme is shown in Figure 4.

In Figure 4(a) we see a linear address divided into three fields, Dir, Page, and
Offset. The Dir field is used to index into the page directory to locate a pointer to
the proper page table. Then the Page field is used as an index into the page table
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to find the physical address of the page frame. Finally, Offset is added to the
address of the page frame to get the physical address of the byte or word needed.

The page table entries are 32 bits each, 20 of which contain a page frame number.
The remaining bits contain access and dirty bits, set by the hardware for the
benefit of the operating system, protection bits, and other utility bits.

Each page table has entries for 1024 4-KB page frames, so a single page table
handles 4 megabytes of memory. A segment shorter than 4M will have a page
directory with a single entry, a pointer to its one and only page table. In this way,
the overhead for short segments is only two pages, instead of the million pages
that would be needed in a one-level page table.

To avoid making repeated references to memory, the Pentium, like MULTICS,

has a small TLB that directly maps the most recently used Dir-Page combinations
onto the physical address of the page frame. Only when the current combination
is not present in the TLB is the mechanism of Figure 4 actually carried out and
the TLB updated. As long as TLB misses are rare, performance is good.

It is also worth noting that if some application does not need segmentation but is
content with a single, paged, 32-bit address space, that model is possible. All the
segment registers can be set up with the same selector, whose descriptor has Base
= 0 and Limit set to the maximum. The instruction offset will then be the linear
address, with only a single address space used - in effect, normal paging. In fact,
all current operating systems for the Pentium work this way. OS/2 was the only
one that used the full power of the Intel MMU architecture.

All in all, one has to give credit to the Pentium designers. Given the conflicting
goals of implementing pure paging, pure segmentation, and paged segments,
while at the same time being compatible with the 286, and doing all of this
efficiently, the resulting design is surprisingly simple and clean.

Although we have covered the complete architecture of the Pentium virtual

memory, albeit briefly, it is worth saying a few words about protection, since this
subject is intimately related to the virtual memory. Just as the virtual memory
scheme is closely modeled on MUL TICS, so is the protection system. The
Pentium supports four protection levels, with level 0 being the most privileged
and level 3 the least. These are shown in Figure 5. At each instant, a running
program is at a certain level, indicated by a 2-bit field in its PSW. Each segment
in the system also has a level.
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As long as a program restricts itself to using segments at its own level, everything
works fine. Attempts to access data at a higher level are permitted. Attempts to
access data at a lower level are illegal and cause traps. Attempts to call procedures
at a different level (higher or lower) are allowed, but in a carefully controlled
way. To make an interlevel call, the CALL instruction must contain a selector
instead of an address. This selector designates a descriptor called a call gate,
which gives the address of the procedure to be called. Thus it is not possible to
jump into the middle of an arbitrary code segment at a different level. Only
official entry points may be used. The concepts of protection levels and call gates
were pioneered in MULTICS, where they were viewed as protection rings.

A typical use for this mechanism is suggested in Figure 5. At level 0, we find the
kernel of the operating system, which handles I/O, memory management, and
other critical matters. At level 1, the system call handler is present. User programs
may call procedures here to have system calls carried out, but only a specific and
protected list of procedures may be called. Level 2 contains library procedures,
possibly shared among many running programs. User programs may call these
procedures and read their data, but they may not modify them. Finally, user
programs run at level 3, which has the least protection.

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Traps and interrupts use a mechanism similar to the call gates. They, too,
reference descriptors, rather than absolute addresses, and these descriptors point
to specific procedures to be executed. The Type field in Figure 2 distinguishes
between
code segments, data segments, and the various kinds of gates.
Paging in Pentium:

 Paging can be disabled for a segment

 Linear virtual address is 32 bits, and each page is 4KB

 Offset within page is 12 bits, and page number is 20 bits. Thus, 220
pages, So use 2-level paging

 Each process has page directory with 1K entries

 Each page directory entry points to a second-level page table, in turn

with 1K entries (so one top-level entry can cover 4MB of memory)

 TLB used

 Many details are relevant to compatibility with earlier architectures

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