PLL Problems and Solutions (9/6/03) Page 1

PLL PROBLEMS AND SOLUTIONS

Problem 1
Solve for and evaluate the series Cs = 30fF Rs = 5.3Ω
and parallel resonance
Ls = 8.4mH
frequencies of the crystal whose
model is shown. It is Cp = 6pF
suggested to make appropriate
assumptions as the exact Crystal SU03H01P1
frequencies are difficult to
achieve.
Solution
Solving the exact frequencies for this problem is very challenging. It is better to assume that
series resonance (minimum impedance) will occur approximately when the impedance of Cs
cancels the impedance of Ls. This gives series resonance as
1 1
ω s2 = L C → fs = ≈ 10.026MHz
s s 2π LsCs
The parallel resonance can be approximated by assuming that it will occur close to the frequency
when the impedance of the series branch equals the negative impedance of the parallel branch.
This condition is given as,
1 1 1 1 1 1 11 1
= ωLs + → ωp2 = L  C + C  → fp = Ls Cs + Cp
ωCp ωCs s  s p 2π

fp ≈ 10.051MHz
SPICE Simulation:
Homework H01P1 - Crystal Impedance
IIN 0 1 AC 1.0
CP 1 0 6PF
CS 1 2 30FF
LS 2 3 8.4MH
RS 3 0 5.3OHM
RBIG 1 0 1GOHM
.AC LIN 101 9.5MEG 10.5MEG
.PRINT AC V(1)
.PROBE
.END

100kΩ
Impedance

10kΩ

1kΩ

100Ω
9.6 9.8 10 10.2 10.4
Frequency (MHz) SU03H01S1
PLL Problems and Solutions (9/6/03) Page 2

Problem 2
A simple, doubly balanced passive CMOS mixer is shown along with the local oscillator
waveform, vOL(t). Assume that vRF(t) = ARFcos(ωRFt) and vLO(t) is the waveform shown
below. (a.) Find the mixer gain, Gc, in dB if the switches are ideal. (b.) Find the mixer gain in
dB if the switches have an ON resistance of Rs/2.
vLO(t)
Rs vLO(t) vLO(t) Switch
2 ON

vRF(t) +vIF(t) -
0 t
Rs
vLO(t) vLO(t)
Rs Switch
2 OFF 1
fLO F99E2P1

Solution
Assume the switches have an ON resistance of RON and work both parts (a) and (b)
simultaneously. Also, The equation for vIF(t) can be written as,

 Rs 
vIF(t) =  2R +2R  vRF(t) · sgn[vLO(t)]
 s ON

 Rs  4 4
VIF(jω) =  2R +2R  ARFcos(ωRFt) ·  cos( ω LO t) + cos (3 ω LO t) + ···
 s ON  π 3π 

 Rs  4ARF
∴ VIF(jω) ≈  2R +2R  cos(ωRFt) · cos(ωLOt)
 s ON π

 Rs  2ARF
=  2R +2R  cos[ωRF -ωLO)t]
 s ON π
The conversion gain in general is written as
|VIF|  Rs 2
Gc = |V | =  2R +2R 
RF  s ON π

1 1
(a.) For RON = 0, Gc = → Gc = = -9.943dB
π π

2 2
(b.) For RON = 0.5Rs, G c = → Gc = = -13.465dB
3π 3π
PLL Problems and Solutions (9/6/03) Page 3

Problem 3
Use SPICE to demonstrate that the
following circuit is a frequency doubler. 2V
If vin(t) is a sinusoid of 10kHz and 1.5V M1 M2
peak, show vin(t) and vout(t) as a 10µm
function of time. The model parameters 1µm
of the MOSFETS are K N ’ = 110µA/V2, vin(t) vin(t)
vout(t)
VTN = 0.7V, and λN = 0.04V-1.
Solution 100kΩ
The results of this problem are below. -2V SU03H01P3
SPICE Input File:
Homework H01P3 - Frequency Doubler
VIN 1 0 DC 0.0 SIN(0 1.5 10KHz)
EVIN 0 2 1 0 1.0
VDD 4 0 DC 2.0
VSS 5 0 DC -2.0
M1 4 1 3 3 NMOS1 W=10U L=1U
M2 4 2 3 3 NMOS1 W=10U L=1U
RTAIL 3 5 100K
.MODEL NMOS1 NMOS VTO=0.7 KP=110U LAMBDA=0.04
.OP
.TRAN (10U 1000U)
.PRINT TRAN V(1) V(2) V(3)
.PROBE
.END
Output Plots:
1.5V
vin(t)
1.0V
vout(t)
0.5V

-0.5V

-1.0V

-1.5V
0 200 400 600 800 1000
SU03H01S3
Time (µsec.)
PLL Problems and Solutions (9/6/03) Page 4

Problem 4
An 10nH inductor has a Q of 5 and is used to create a tank circuit with a 10pF capacitor.
Assume the capacitor is ideal. (a.) What is the resonant frequency of this circuit? (b.) What
value of parallel negative resistance should be used to create an oscillator? (c.) If C is changed
to 20 pF, what is the new value of the parallel negative resistance?
Solution
C = 10pF:
1 26
Lp =  1+ 2 = 25 ·10nH = 10.4nH
 Q
1 1
ωo = = = 3.1623x109 radians/sec.
L pC 10.4nH·10pF
ωoLs ω oL s
Q= R → Rs = Q = 6.201Ω
s
∴ Rp = (1+Q2)Rs = 26·6.201Ω = 161.245Ω
C = 20pF:
1 1
ωo = = = 2.1926x109 radians/sec.
L pC 10.4nH·20pF
ωoLs ω oL s
Q= R → Rs = Q = 4.3853Ω
s
∴ Rp = (1+Q2)Rs = 26·4.3853Ω = 114.017Ω

Problem 5
Give a block diagram of simple brute-force coherent direct synthesizer that will generate 1.75f
from f. The input frequency f is to vary from 12 MHz to 15MHz. Since f is variable, you
cannot use frequency multipliers (integer frequency dividers and mixers are allowed) in your
design. A simple design will receive more credit. What other frequencies will be present at the
output?
Solution
Approach: fout = fxf – f/4 = 1.75f

f 2f

2f±0.25f
f
f/4
÷ 4
S03H01S5
The frequency 2.25f will also be present at the output.
PLL Problems and Solutions (9/6/03) Page 5

Problem 6
A phase-locked loop has a center frequency of 105 rads/s, a Ko of 103 rad/V-s, and a Kd of 1
V/rad. Assume there is no other gain in the loop. Determine the loop bandwidth in the first-
order loop configuration. Determine the single-pole, loop-filter pole location to give the closed-
loop poles located on 45° radials from the origin of the complex frequency plane.
Solution
103
The loop bandwidth = Kv = KoKp = s

In order to produce poles at 45° to the axis, we add a loop filter pole at ω1 where
ω1 = 2Kv = 2000 rads/sec.
The filter transfer function becomes,
ω1 2000
F(s) = = s+2000
s+ω1
Problem 7
For the same PLL of the previous problem, design a loop filter with a zero that gives a crossover
frequency for the loop gain of 100 rads/sec. The loop phase shift at the loop crossover
frequency should be –135°.
Solution
A plot of the desired loop gain is shown below.

-20dB/dec.
Loop Gain (dB)

40dB

20dB
-40dB/dec.
0dB ω1 = ω(rads/sec)
ω2 = Kv = 1000
10 100 SU03H02S2

If ω2 (the zero frequency) is at the unity gain point, then the loop phase shift will be
–135° at this point. Therefore, we require that ω2 = 100 radians/sec.. If ω1 = 10 radians/sec.,
the requirement will be satisfied as shown in the above plot.
The design of the filter becomes, R1
1 1
ω2 = R C and ω1 = (R +R )C
2 1 2 C
ω2 R1 R2
∴ = 1 + R = 10 → R1 = 9R2
ω1 2

Now appropriate values of R1 , R2, and C can be chosen. Fig. SU03H02S2A

PLL Problems and Solutions (9/6/03) Page 6

Problem 8
Estimate the capture range of the PLL of the previous problem assuming that it is not artificially
limited by the VCO frequency range.
Solution
For capture we need
π
|(ωi - ωo)| < 2 Kv|F(j(ωi - ωo)|
If we assume that
π
|(ωi - ωo)| = 2 Kv|F(j(ωi - ωo)|

then with ωo = 105 rads/sec and Kv = 1000 rads/sec. we get,

|(ωi - ωo)| = 1570|F(j(ωi - ωo)|

Now from the previous problem, we know that |F(jω)| is given as

|F(jω)|
1 10 100
1 ω

0.1
SU03H02S3
From this figure we can solve the above equation to find that
(ωi - ωo) = 157 rads/sec.
which is the capture range.
PLL Problems and Solutions (9/6/03) Page 7

Problem 9
A filter for a phase locked loop is specified as C=10pF
10ω1 1,000,000 R R
|F(s)| = = s+100,000 R = 10kΩ
s+ω1
R2 Vout
and must be implemented on a CMOS chip using Vin R R
resistors no larger than 10kΩ and capacitors no larger _
than 10pF. Using the circuit shown, find the values R1
of R1 and R2 that will satisfy the component value +
constraints. SU03H02P4
Solution
Find the currents i1 and i2, C=10pF
v in R R 1 vi n v in R R
i1 = = = R = 10kΩ
RR 1 R+R 1 2RR + R 2 R T1
R + R+R 1 i2
1 R2 Vout
and Vin R R
vout R _
i2 = RR 1 R+R 1 + sCvout R1 i1
R + R+R +
1
R 2 v out vout SU03H02S4
= + sCv out R T2 + sCvout
=
2RR + R 2
2
Solving for the sum of the currents flow toward the minus op amp input terminal gives,
v in vout vout RT2 1 1
+
R T1 R T2 + sCv out = 0 → v in = -R T1 sCRT2+1 = -10 s
+1
105
10-5
∴ CRT2 = 10-5 → RT2 = -11 = 106
10
2RR 2 + R 2 R2 6
R T2 = = 2R + = 20x10 3 + 100x10 = 106
R2 R2 R2
100x106
∴ R2 = = 100Ω
106-20x103
R T2 R2 100x106
R T1 = 10 = 105 → 2R + R = 20x103 + R = 105
1 1
100x106
∴ R1 = = 1000Ω
105-20x103
This problem shows how a clever circuit technique can make a filter suitable for integrated circuit
implementation.
PLL Problems and Solutions (9/6/03) Page 8

Problem 10
This homework is designed to provide practical inductor design experience for students. Use
ASITIC for the design and analysis. However, other tools are acceptable if they give all the
results including layout.
A 5GHz LC tank will be designed as a part of LC oscillator. C value is given as 1pF.
(a) Find L value. (b) Design and simulate a spiral inductor with this L value (± 5% range).
Optimize design parameters, W, S, D and N to get a high Q (Qmin = 5). Show L, Q, fSR value
obtained from simulation. (c) Show the layout. (d) Give a lumped circuit model with component
values.
Solution
(a) LC tank oscillation frequency is given as 5GHz.
1 1
L= 2 = 9 -12 = 1.01x10-9
ωosc ·C (2π·5x10 )(1x10 )
(b) One possible solution is
ƒ Parameters: W = 16um, S = 2um, D = 150um, N =2.5
ƒ Resulting inductor: L = 0.952nH, Q = 8.54, fSR = 19.35GHz @ 5GHz
(c) Layout

(d) Pi model from ASITIC is shown below. This is the analysis result from ‘pix’
command.
0.952nH 3.27

71.1fF 65.1fF

-1.3
3.03
PLL Problems and Solutions (9/6/03) Page 9

Problem 11
Assume an LPLL has F(s) =1 and the PLL parameters are Kd = 0.8V/radians, Ko = 100 MHz/V,
and the oscillation frequency, fosc = 500MHz. Sketch the average control voltage at the output of
the phase detector if the input frequency jumps from 500MHz to 550MHz.
Solution
Find the transfer function from the input frequency, fin, to the
output of the phase detector, vd. ω1 vd
K d
K dK o
Vd = Kd(θ1-θ2) = Kdθ1- s Vd ω2 Ko
s
 ω1 SU03H03S1A
 K dK o
Vd1+ s  = Kdθ1 = Kd s 

Vd Kd Kd Kd ∆ω1 k1 k2
∴ = s+K K → Vd(s) = s+K K ω1(s) = s+K K s = s + s+K K
ω1 d o d o d o d o
Kd∆ω1 Kd∆ω1
By partial fraction expansion we can show that k1 = - k2 = K K = K = 0.4V
d o v
Kd∆ω1 (V/rad)(rad/sec)
Note the units of K are 1/sec =V
v
and Kv = (2π·100MHz/V)(0.8V/rad.) = 502.65x106 (1/sec.)
Kd∆ω1
∴ vd(t) = K (1-e-Kvt) = 0.4(1-e-502.65x106t)
v
A plot of vd(t) is shown below.
0.400V

0.267V
vd(t)
0.133V

0V
0 2 4 6 8 10
Time (ns) Fig. SU03H03S1B
PLL Problems and Solutions (9/6/03) Page 10

Problem 12
A Type I PLL incorporates a VCO with Ko = 100MHz/V, a phase detector with Kd = 1V/rad,
and a first-order, lowpass filter with ωLPF = 2π x106 radians/s shown below. A divider of 100
has been placed in the feedback path to implement a frequency synthesizer. (a.) Find the value
of the natural damping frequency, ωn, and the damping factor, ζ, for the transfer function
φout(s)/φin(s), for this PLL. (b.) If a step input of ∆φin is applied at t = 0, what is the steady-
state phase error at the output of the phase detector, φe? The steady-state error is evaluated by
multiplying the desired phase by s and letting s→0.

Phase Detector Filter VCO

φin + φe 1 Vc Ko φout
Kd s
ωLPF +1 s
-
Divider
1/100
F02E2P3

Solution
Ko  1  K  φ - φ out → φ  1+ K o  Kd   K o  Kd 
(a.) φout = s  s  d in N  out sN  s  = s  s  φin
ω + 1  1 +   + 1
 LPF    ωLPF  ωLPF 
φout(s) K oK d KoKdωLPF ωn2
∴ = s  K oK d = =
φin(s) K o K d ω L P F s 2 + 2 ζω n s + ω n 2
s  1 + + 2
 ωLPF N s + ω LPF s + N
KoKdωLPF 2πx106·2πx108
Thus, ωn2 = N = 100 = 4π2x1012 → ωn = 2πx106

ωLPF ωLPF 1 NωLPF 1 100·2πx106

ζ= = =2 K oK d = 2 = 0.5
2ωn KoKdωLPF 1·2πx108
2 N
∴ ω n = 2 π x10 6 and ζ = 0.5

(b.) First we must solve for φe(s) which is found as

s  s 
s 1 +  s 1 +
 ωLPF  ωLPF KoKdωLPF
φe(s) = Ko φout(s) = Ko φ (s)
K o K d ω L P F in
s2+
ω LPF s + N
∆φin K d(s2+ ω LPF s)∆φ in
If φin(s) = s , then we can write sφe(s) =
K oK dω L P F
s 2 + ω LPF s + N

Therefore, we see that the steady-state error is φ (t= ∞ ) = 0.

PLL Problems and Solutions (9/6/03) Page 11

Problem 13
Modify the active filter shown of Problem 9 to C2
design the lag-lead loop filter shown below. The
capacitors can be no larger than 10pF. Give the R R
values of R1, R2, C1 and C2. R = 10kΩ
|F(jω)| dB R2 Vout
Vin R R
10K 100K
0dB _
ω(rads/sec.) R1
+
SU03H03P3A
-20dB
S03H03P3
Solution
The transfer function corresponding to the above Bode plot is,
s
+1
105
F(s) = 1
+1
104 C1 C2
The modification of the filter is vd R R vc
shown where from Prob. 9,
2RR i+ R 2 - -
R Ti = RT1 RT2
Ri + +
The transfer function of this Loop Filter
filter is found as, SU03H03S2A
Vc(s)
F(s) = V (s) =
d
 R T2  sR T1 C 1 +1
⇒ RT2 = RT1 = RT , RTC1 = 10-5 and RTC2 = 10-4
 R T1 sRT2C2+1
We see if RT2 = RT1, then C2 = 10C1. Choosing C2 = 10pF gives C1 = 1pF. This gives

10-4 10-4
RT = C = -11 = 107
2 10
2RR i+ R 2 R2 100x106 100x106
RT = 3
= 2R + R = 20x10 + R 7
= 10 ⇒ R1 = 7 = 10.02Ω
Ri 1 1 10 -20x103
Therefore, R1 = R2 = 10.02Ω, C1 = 1pF and C2 = 10pF
The realization is completed by replacing each of the RT resistors with the following equivalent:

RT1 10kΩ 10kΩ

10.02Ω
SU03H03S3B
PLL Problems and Solutions (9/6/03) Page 12

Problem 14
Using the filter of Problem 13, find the value of ωn and ζ of the PLL if Kd = 1V/radians, K o =
2Mradians/V·sec. What is the steady state phase error in degrees if a frequency ramp of 109
radians/sec.2 is applied to the PLL?
Solution
Using the definition give in the notes for the time constants of the passive lag-lead filter we get,
s
+1
105 sτ2 + 1
F(s) = 1 = ⇒ τ2 = 10-5 sec. and τ1 = 9x10-5 sec.
+1 s( τ +
1 2τ ) + 1
104

K oK d 2x106
∴ ωn = = = 2 x105 = 141.4x103 radians/sec.
τ1+τ2 10-4
ωn 1  2x105 -5 1  1 1
ζ = 2 τ2 + K K = 2 10 + = 1 + 20  = 0.742
 o d  2x106 2
Assuming the PLL has a high loop gain, then the steady-state phase error can be found as
∆ω· 109 1
θe(∞) = 2 = = 20 radians = 2.86°
ω n 2x1010
PLL Problems and Solutions (9/6/03) Page 13

Problem 15
Solve for the crossover frequency of the PLL of Problems 13 and 14 and find the phase margin.
Use SPICE to find the open-loop frequency response of the PLL and from your plot determine
the crossover frequency and phase margin and compare with your calculated values.
Solution
The crossover frequency can be found as,

ωc = ωn 2ζ2 + 4ζ4+1 = 2 x105 2·0.742 2 + 4·0.7424+1

= 2 x105(1.6089) = 2.275x105 radians/sec. = 36.208kHz

The open loop transfer function is given as
Kv 1+sτ1 2x105 1+s10-5
LG(s) = s  = s  1+s10-4
 1+sτ2
The phase margin can be written as,
 ωc   ωc 
PM = 180° - 90° +tan-1 5 - tan-1 4 = 90° + 66.27° - 87.48° = 68.79°
10  10 
SPICE Results:
Problem H3P5-Open Loop Response of an LPLL with Lead-Lag Filter
VS 1 0 AC 1.0
R1 1 0 10K
* Loop bandwidth = Kv =2xE+6 Tau1=1E-4 Tau2=1E-5
ELPLL 2 0 LAPLACE {V(1)}=
+{(2E+6/(S+0.001))*((1+1E-5*S)/(1+1E-4*S))}
* Note: The 0.001 added to “S” in the denominator is to prevent
* blowup of the problem at low frequencies.
R2 2 0 10K
*Steady state AC analysis
.AC DEC 20 10 100K
.PRINT AC VDB(2) VP(2)
.PROBE
.END
100
Phase + 180°
80
dB or Degrees

60
|F(jω)| Phase
40 Margin
≈ 69°
20

0
-20
10 100 1000 104 105
SU03H03S5 Frequency (Hz) ωc ≈ 36kHz
The simulation results agree well with the calculated results.
PLL Problems and Solutions (9/6/03) Page 14

Problem 16
For the DPLL shown assume that N = 1000 and the –3dB bandwidth is 1000 Hz. (a.) Assume
that ζ = 0.2 and solve for the natural pole frequency, ωn, the filter time constant, τ = RC, and the
phase margin. (b.) Repeat part (a.) if ζ = 0.7. (c.) Repeat part (a.) if ζ = 1. Verify your
answers with PSPICE.
VDD

I1
v1(t) QA
S1 v2(t)
PFD VCO
v2'(t) QB
S2 C
R
I2

1/N
SU03H04P1
Solution
The filter output can be written as,
Kd Kd  θ2
Vf(s) = s (sτ +1)(θ1-θ2’) = s (sτ +1)θ 1 + N  where τ = RC

Ko K oK d  θ 2  K v (s τ +1) K v (s τ +1)
θ2(s) = s Vf(s) = 2 (sτ +1)θ 1 + N  = θ 1 (s) + θ2(s)
s s2 Ns 2
The closed-loop response is given as,
θ2(s) K v (s τ +1) K v (s τ +1)
= = 2
θ1(s) K vτ K v s + 2ω nζs + ω n2
2
s + N s + N
Kv 2ζ
∴ ωn = N and τ=
ωn
We know that the loop bandwidth, ω-3dB, can be expressed as
ω-3dB
ω-3dB = ωn 2 ζ 2 +1+ (2ζ2+1)2 +1 → ωn =
2 ζ 2 +1+ (2ζ 2+1)2 +1
ζ = 0.2:
ωn = 3933 rads/sec., τ = 102µs and PM = 0°+tan-1(2000π·102µs) = 32.6°
ζ = 0.7:
ωn = 3066 rads/sec., τ = 457µs and PM = 0°+tan-1(2000π·457µs) = 70.8°
ζ = 1:
ωn = 2531 rads/sec., τ = 790µs and PM = 0°+tan-1(2000π·790µs) = 78.6°
PLL Problems and Solutions (9/6/03) Page 15

Problem 16 – Continued
PSPICE Input File:
Homework4, Problem 1
VS 1 0 AC 1.0
R1 1 0 10K
ELPLL1 2 0 LAPLACE {V(1)}= {5044*5044*(1+102E-6*S)/(S+0.01)/(S+0.01)}
R2 2 0 10K
ELPLL2 3 0 LAPLACE {V(1)}= {3513*3513*(1+457E-6*S)/(S+0.01)/(S+0.01)}
R3 3 0 10K
ELPLL3 4 0 LAPLACE {V(1)}= {2531*2531*(1+790E-6*S)/(S+0.01)/(S+0.01)}
R4 4 0 10K
*Steady state AC analysis
.AC DEC 20 1 100K
.PRINT AC VDB(2) VP(2) VDB(3) VP(3) VDB(4) VP(4)
.PROBE
.END

Plot of Results:
100
ζ = 0.2 ζ=1

ζ = 0.7 ζ = 0.2
dB or Degrees

50
PM PM
ζ=1 = 72° = 79°
PM
= 32°
0

ωc

-50
1 10 100 1000 10 4 10 5
Frequency (Hz) SU03H04S1
PLL Problems and Solutions (9/6/03) Page 16

Problem 17
A type-I, second-order DPLL synthesizer is to be made with components having the following
values:
Ko = 4x108 rads/sec./V fref = 12.5 kHz Kd = 0.15 V/rad β = 2π
Design a type-I, second-order synthesizer having the following specifications:
1.) Output frequency range = 50MHz
2.) Lock range = 10MHz at the output
3.) Damping factor = 0.75.
Determine the components for the loop filter. Let C = 0.5µF. Make a sketch of your filter with
all components carefully labeled. Once your design is complete, determine the pull-in range in
Hz (at the output) and the lock time of your loop.
Solution
fout 50MHz K oK d 4x108·0.15
N = f = 12.5kHz = 4000 and Kv = N = 4000 = 15,000 sec.-1
r
∆ωH = βKvN = 2π·15x103·4000 = 377x106 rads/sec.
τ2 τ2 τ2 ∆ωL 62.8Mrads/sec 1
∆ωL = ∆ωH = 377 Mrads/sec. → = = =
τ1 τ1 τ1 ∆ωH 377Mrads/sec 6
∴ τ1 = 6τ2
1 1 1
ζ = 0.5 (1+τ2Kv) → 1.5 = (1+τ2Kv) → 2.25 = (1+τ2Kv)2
K vτ1 K vτ1 K vτ1
2.25·Kv(6τ2) = 13.5 Kvτ2 = 1 +2 Kvτ2 + (Kvτ2)2 → 0 = 1 – 11.5x + x2
11.5 1
where x = Kvτ2. Solving for x gives x = Kvτ2 = 2 ±2 11.5 2 - 4 = 0.0876
0.0876 5.84
∴ τ2 = 15,000 = 5.84µs = R2C = R2(0.5µF) → R2 = 0.5µF = 11.7Ω
35
τ1 = 6τ2 = 35µs = (R1+R2)C → R1+R2 = 0.5µF = 70.08Ω → R1 = 58.4Ω
Filter schematic:
R1 = 58.4Ω

R2 =
11.7Ω
C=
0.5µF
SU03H04S2
Kv
∆ωP = Nβ 2 2ζωnKvF(0) -ωn2 and ωn = = 20,702 rads/sec
τ1
∴ ∆ωP = 4000·2π 2 2·0.75·20,702·15,000 - (20,702)2 = 216.85 Mrads/sec.
∆ fP = 34.51 MHz
2π 6.283
TL = = 20,702 = 303.5µs
ωn
PLL Problems and Solutions (9/6/03) Page 17

Problem 18
Given the DPLL described by
1+5x10-6s
1+τ2s
Kd = 2.2 V/rad F(s) = =
1+τ1s 1+2x10-5s
fref = 12 kHz Ko = 25 MHz/V β = 2π Ν = 15,000
Determine the type number and order of the system and then find:
(a.) The output frequency in Hz.
(b.) The crossover frequency in Hz.
(c.) The noise bandwidth (Hz).
(d.) The closed-loop phase –3dB bandwidth in Hz
(e.) The steady-state phase error in response to a phase step of 0.1 radian.
(f.) The hold range (±Hz at the output).
(g.) The lock range (±Hz at the output).
(h.) The lock time.
(i.) The pull-in range (±Hz at the output)
(j.) The steady-state phase error in radians in response to a frequency step equal to the lock
range.
Solution
This is a type-I, second-order system. The closed loop transfer function is,
 1+τ2s
K v 
KvF(s) θ2 θ2 K vF(s)  1+τ1s Kv(1+τ2s)
θ2 = s  θ 1 - N  → = K v F(s) = =
θ1  1+τ2s K v (1+ τ 2 s)
s+ N s(1+ τ s) +
Kv  1 N
 1+τ1s
s + N
Kv
(1+τ2s)
θ2 τ1 Kv(1+τ2s)
= Kv  =
K v s2+2ζω s+ω 2
θ1 s
s 2 +  1 + N τ2 + n n
τ1 τ1N
Kv 2π·25x106·2.2
∴ ωn = = = 33.94 Krads/sec
N τ1 2x10-5·15,000

N  τ2Kv 15,000  2 π ·25x10 6 ·2.2·5x10 -6

ζ = 0.5 1+ N  = 0.5 1 + 
K vτ1  2π ·25x10 6·2.2·2x10-5 15,000 
= (0.5)(1.4732)(1.115) = 0.821
(a.) fo = Nfr = 15,000·12kHz = 180MHz
ωn 33,940
(b.) fc = 2 ζ 2 + + 4ζ4+1 = 2(0.821)2+ 4(0.821)4+1 = 9,397 Hz
2π 2π
PLL Problems and Solutions (9/6/03) Page 18

Problem 18 - Continued
ωn 1 33,940 1 
(c.) Bn = 2  ζ +  = 2  0.821 + = 19.1kHz
 4ζ   4·0.821
Nωn  N ω n
(d.) ω-3dB = ωn b + b2+1 where b = 2ζ2 + 1 - K  4 ζ - K 
v  v 
33,940·15,000  33,940·15,000
b = 2(0.821)2 + 1 -  4·0.821 - = -0.320
2π·25x106·2.2  2π·25x106·2.2

ω-3dB = 33,940 -0.320 + (-0.320)2+1 = 29,003 rads/sec. → f-3dB = 4615Hz

(e.) Because this is a Type-I, second-order system, the phase error in response to a phase step is
zero provided that ∆θ < β.
βKv
(f.) ∆ω H = β NK = β K v → ∆ fH = = (2π·25x106·2.2) = ±345.6MHz
2π
τ2  5x10-6
(g.) ∆ωL = ∆ωH → ∆fL = ±345.6MHz   = ±86.39MHz
τ1 2x10-5
2π 2π
(h.) Lock time = TL = = 33,940 =185µs
ωn
(i.) Pull-in range.
2ζωnKvF(0)
∆ωP = Nβ 2 N - ωn2 where F(0) = 1 for the filter selected.

15,000·2π 2 2·0.821·33,940·2π ·25x106·2.2

∴ ∆ fP = 15,000 - (33,940 2 ) = 243.7MHz
2π
Note that,
∆ fL < ∆ fP < ∆ fH
∆ωosc 2π·86.39x106
(j.) εss = K = = 1.57 rads < β as required
v 2π·25x106·2.2
PLL Problems and Solutions (9/6/03) Page 19

Problem 19
Construct an accurate Bode plot of the synthesizer in Problem 18. Use this Bode plot to
determine the phase margin.
Solution
PSPICE was used to solve this problem. The input file and the results are shown below.

Problem H4P4-Open Loop Response of an DPLL with Lead-Lag Filter

VS 1 0 AC 1.0
R1 1 0 10K
ELPLL 2 0 LAPLACE {V(1)}= {23.04E+3*(1+5E-6*S)/(1+2E-
5*S)/(S+0.001)}
R2 2 0 10K
*Steady state AC analysis
.AC DEC 20 10 100K
.PRINT AC VDB(2) VP(2)
.PROBE
.END

100
dB or Degrees

50 Phase
Margin
= 72°

-50
10 100 1000 10 4 10 5
Frequency (Hz) SU03H04S4
PLL Problems and Solutions (9/6/03) Page 20

Problem 20
Write the transfer functions giving: (1) The VCO phase noise in the output, (2) the reference
oscillator phase noise in the output. Use the literal form of the equations. The phase noise of the
VCO used in the synthesizer of Problem 3 is shown below. Make an accurate plot of the VCO
phase noise in the output of the synthesizer.
-50
SSB Phase Noise (dBc/Hz)

-100

-150

-200
10 100 1000 10 4 10 5 10 6 10 7
Frequency Offset from Carrier (Hz) SU03H04P6
Solution
The following block diagram will be Phase Detector
used to find the phase noise in the +
output due to the VCO phase noise. θr θe ωo
K d F(s) Ko
 K v F(s) θ o  -
θo = θ o,n - sN 
 θo' θo,n

1 θo + + 1
θo s s
= N
θ o,n K vF(s) SU03H04P5
s+ N

θo s s(1+τ1s)
= =
θ o,n K v  1+τ2s  K vτ2 K v
s+ N   s 2 τ 1 + s  1+ N  + N
 1+τ1s
From Problem 3 of this assignment we get,
Kv
(1+τ2s)
θo 1 τ1
= N Kv  Kv
θr,n s
s 2 +  1 + N τ2 +
τ1 τ1N
PLL Problems and Solutions (9/6/03) Page 21

Problem 20 – Continued
The following PSPICE input file gives the results plotted below.
Homework 4, Problem 5 -In/Out VCO Phase Noise, Transfer Function
.PARAM N=15000, KVCO=157.1E6, T1=2E-5, T2=5E-6, KD=2.2, E=0.001
*Input Phase Noise
vphasenoise 1 0 ac 1.0
R1 1 0 10k
EPN 2 0 freq {v(1)} = (1,-40,0) (10,-70,0) (100,-100,0)
+(1E5,-160,0) (1E6,-160,0)
RPN 2 0 10k
*VCO Noise Transfer Function
EDPLL1 3 0 LAPLACE {V(1)}=
+{S*(T1*S+1)/(S*S*T1+KD*KVCO*T2/N*S+S+KD*KVCO/N)}
RDPLL1 3 0 10K
*VCO Noise at the Output
EDPLL2 4 0 LAPLACE {V(2)}=
+{S*(T1*S+1)/(S*S*T1+KD*KVCO*T2/N*S+S+KD*KVCO/N)}
RDPLL2 4 0 10K
*Reference Noise Transfer Function
EDPLL3 5 0 LAPLACE {V(1)}=
+{KD*KVCO*(1+T2*S)/(S*S*T1+S+KD*KVCO/N*S+KD*KVCO/N)/N}
RDPLL3 5 0 10K
*Reference Noise at the Output
EDPLL4 6 0 LAPLACE {V(2)}=
+{KD*KVCO*(1+T2*S)/(S*S*T1+S+KD*KVCO/N*S+KD*KVCO/N)/N}
RDPLL4 6 0 10K
*Steady state AC analysis
.AC DEC 20 1 1000K
.PRINT AC VDB(2) VDB(3) VDB(4) VDB(5) VDB(6)
.PROBE
.END
VCO Output Noise (and Reference Output Noise):

50
Reference Transfer Function VCO Transfer Function
0

-50
dB or dBc

VCO Phase Noise and Output Reference Noise

-100 VCO Input and
Ouput Phase Noise
-150
VCO Output Phase Noise
-200
Output Reference Noise
-250
1 10 100 1000 10 4 10 5 10 6
Frequency (Hz) SU03H04S5B
PLL Problems and Solutions (9/6/03) Page 22

Problem 21
Sketch the time variation and frequency spectrum of an RF signal with 75 percent amplitude
modulation. Show several cycles of the modulated wave. Make the modulation frequency 1/10
of the carrier frequency. The unmodulated carrier has a peak amplitude of 1.0V.
Solution
The expression for the general form of amplitude modulation is,
  ωct 
v(t) = 1.01 + m a cos  10   cos(ωct) = [1 + 0.75cos(0.1ωct)]cosωct

1.5
1

0.5

v(t) 0
-0.5

-1

-1.5

-2
0 π 2π 3π 4π 5π 6π 7π 8π
ωct Fig. SU03H05S1

vmax. = 1.75V and vmin. = 0.25V

Problem 22
The level of an SSB AM spur is observed to be –75 dBc. If the carrier has a peak amplitude of
1V, what is the variation of the carrier in ±V needed to produce the observed spur?
Solution
Vc = 0dBc
The observed spectrum is

Vc
 ma m = -75dBc
SSB = 20 log10 2  → ma = 2·10SSB/20 2 a
f
fc SU03H05S2
∴ ma = 2·10-75/20 = 335.6x10-6
∆v
If Vpeak = 1V, then ma = V → ∆ v = 3.35.6µV
p
PLL Problems and Solutions (9/6/03) Page 23

Problem 23
A pair of 5 kHz PM/FM spurs appear on a 10 MHz carrier. The level of each spur is –50dBc.
(a.) What phase deviation in ±degrees is need to produce the spurs? (b.) What frequency
deviation in ±Hz is needed to produce the spurs?
Solution
(a.) The single sideband spurs can be expressed as,
 θd β
SSB = 20 log10 2  = 20 log102 

Solving for θd gives,

θd = 2·10SSB/20 = 2·10-50/20 = 2·0.003162 = 6.325 milliradians = ±0.3624°

∆ fc
(b.) We know that θd = β = f which gives
m

∆fc = βfm = θdfm = 6.325x10-3·5x10+3 = ±31.6 Hz

Problem 24
The carrier and spurs of Problem 3 above are passed through a frequency tripler. Make a sketch
of the output spectrum of the tripler. Label and show all important features of the spectrum.
Solution
After passing through a tripler, the SSB spur is increased by 20log10(3) or +9.54dB.
The resulting spectrum is shown as,

0dBc 0dBc
-50dBc+20log10(3) = -40.5dBc
5kHz -50dBc 5kHz
10MHz-5kHz x3 30MHz-5kHz
Frequency Frequency
-40.5dBc 10MHz 10MHz+5kHz 10MHz 30MHz+5kHz
-40.5dBc SU03H05S4
PLL Problems and Solutions (9/6/03) Page 24

Problem 25
A 100 MHz carrier having a –40 dBc upper sideband at 100.002 MHz and a –47 dBc lower
sideband at 99.998 MHz is passed through an ideal limiter followed by a bandpass filter centered
at 100 MHz with a 10 kHz total bandwidth. Make a sketch of the spectrum at the output of the
filter. Label all frequencies and amplitudes.
Bandpass
Ideal Limiter Filter
10kHz

100MHz
SU03H05P5
Solution
Asymmetrical sidebands imply the presence of both AM and FM as show below.
Carrier Carrier
AM FM
-40dBc
-47dBc SA SA SF
fc-fm
f f f f
fc-fm fc fc+fm fc fc-fm fc fc+fm fc fc+fm
SF SU03H05S5

-40dBc = 10-40/20 = 0.01 and -47dBc = 10-47/20 = 4.467x10-3

Solve for SA and SF as follows,
SA + SF = Upper sideband = 0.01

SA - SF = Lower sideband = 4.467x10-3

Upper sideband + Lower sideband
SA = 2 = 7.234x10-3
Upper sideband - Lower sideband
SF = 2 = 2.767x10-3
The limiter will remove all AM sidebands and the filter removes all products other than the
sidebands at ±2kHz. Therefore the output spectrum will appear as,

Carrier

-51.16dBc
fc-fm
f
fc fc+fm
-51.16dBc SU03H05S5A
where fc = 100MHz and fm = 2kHz.
PLL Problems and Solutions (9/6/03) Page 25

Problem 26
An LC oscillator is shown. The value of the inductors, L, are 5nH VDD
and the capacitor, C, is 5pF. If the Q of each inductor is 5, find (a.)
the frequency of oscillation, (b.) the value of negative resistance that L L
should be available from the cross-coupled, source-coupled pair (M1 C
and M2) for oscillation and (c.) design the W/L ratios of M1 and M2
to realize this negative resistance.
Solution M1 M2
(a.) The equivalent circuit seen by the negative resistance circuit is:
2L 2Rs The frequency of oscillation is given as
1/ 2LC or ωo = 2πx109 radians/sec. 2mA
C
Therefore the series resistance, R s , is found F00E2P2
as
ωL 2πx109·5x10-9
F00E2S2A Rs = Q = 5 = 2π Ω
Converting the series impedance of 2L and 2Rs into a parallel impedance gives,

1 0.5 Rs-jωL 0.5R s 0.5ωLs

Y= = · = 2 2 2-j 2 2 2
2Rs+jω2L R s +jω L R s -jω L Rs +ω L R s -ω L
The reciprocal of the conductance is the parallel resistance, Rp, given as
Rs2+ω2L2 4π 2 + 4π 2 ·25
Rp = 0.5R = = 4π(26) = 326.7Ω
s π
∴ R neg = -104π Ω = -326.7Ω
(b.) The negative resistance seen by the RLC circuit is found as follows.
iin iin = gm1vgs1 - gm2vgs2 = gm(vgs1 - vgs2) = - gmvin ∴
-1
Rin = g
m
vin
Assuming the 2mA splits evenly between M1 and M2 for the negative
resistance calculation gives,
M1 + + M2
vgs1 vgs2 1 W/L
- - Thus, gm = gm1 = gm2 = = 2mA·110x10-6 (W/L) = 2132
104π
2mA 2132  2
∴ W/L =  = 42.6 ⇒ W/L = 42.6
104π
F00E2S2B
PLL Problems and Solutions (9/6/03) Page 26

Problem 27
An LC oscillator is shown. Find an expression for the VDD
frequency of oscillation and the value of gmRL necessary for
oscillation. Assume that the output resistance of the FET, rds, RL
can be neglected. L Vout
Solution
An open-loop, small-signal model of this oscillator is shown M1 C1
below. C2

L F99E2P4

+ +
V' gmV' RL C2 Vo
- C2 -
F99P3S2
Writing a nodal equation at the output and input gives,
V o-V' Vo-V’
gm V’+G LV o+sC2V o+ sL = 0 and sL = sC2V’ → Vo = V’(1+s2LC2)

1 V’
∴ gmV’ + G L +sC 1 + sL (1+s2LC2)V’ - sL = 0

Assuming a non-zero value of V’ gives,

1 1 1 1
gm+G L +sC 1 + sL (1+s2LC2)- L = gm+GL+sC1+ sL +s2LC2GL+s3LC1C2+sC2 - sL = 0

or (gm+GL-ω2LGLC2) + jω[C1-ω2LC1+C2] = 0
Therefore, the frequency of oscillation is,

C1+C2 1
ω osc = LC1C2 = LC1C2
C1+C2

The value of gmRL necessary for oscillation is

 C 2 C2
gm+GL = LGLC2ωosc2 = GL 1 + C  → gmRL = C
 1 1
PLL Problems and Solutions (9/6/03) Page 27

Problem 28
A Clapp oscillator which is a version of the Colpitt’s
oscillator is shown. Find an expression for the VDD
frequency of oscillation and the value of gmRL necessary RLarge C1
for oscillation. Assume that the output resistance of the
FET, rds, and RLarge can be neglected (approach
C2
infinity). VBias
L
Solution
C3 RL
The small-signal model for this problem is IBias
shown below.
The loop gain will be defined as Vgs/Vgs’. C2 F02FEP5
C1
Therefore, - +
V gs = Vgs
gmVgs' RL C3 L
-g m V gs' RL||(1/sC 3)  1 
1 1 sC2
R L ||(1/sC 3 ) + sC + sC + s L F02FES5
1 2
RL(1/sC3) 1
-g m V gs ' R +(1/sC ) sC
L 3 2
= RL(1/sC3) 1 1
R L +(1/sC 3 ) + sC1+ sC2 + s L
-g m R L 1 -g m R L
Vgs sRLC3+1 sC2 sC2
T(s) = V = R 1 1 = 1 1
gs L
sR L C 3 + 1 + sC1+ sC2 + s L R L + (sR L C 3 +1)  sC + sC + s L
 1 2 
-g m R L
T(s) = C2
sC 2 R L + (sR L C 3 +1)(s 2 LC 2 + C + 1 )
1
-g m R L
T(s) = C 2C 3 C2
sC 2 R L +s 3 R L C 3 LC 2 + sR L C + sC 3 R L + s 2 L C 2 + C + 1
1 1
-g m R L
T(jω) = C2 C 2C 3 = 1 + j0
2 2
[1+ C - ω LC 2 ] + j ω [R L (C 2 +C 3 ) + R L C -ω R LC 3LC 2]
1 1
C2C3 1 1 1 1
∴ C2+C3 + C = ωosc2C3LC2 → ω osc = L C1 + C2 + C3
1

C2 1 1 1 C2 C2 C2
Also, gm RL = ωosc2LC2 –1 - C = C2 C + C + C  - C -1 = C → g m R L = C
1  1 2 3 1 3 3
PLL Problems and Solutions (9/6/03) Page 28

Problem 29
The objective of this problem is to use passive LC tank and negative feedback circuit to
design an LC oscillator that meets the GSM specification. At first, show the condition that the
1
ideal circuit oscillates at ωosc = and find quality factor, Q. The transistors should be
LC
modeled with the standard small-signal model using gm and rds or rout in this part of the problem.
Second, use SPICE to obtain a transient simulation. Third, simulate the oscillator that replaces
the ideal inductor with the lumped inductor model shown, and use the program referenced below
[1] to layout the inductor. Use the model parameters given in [2] for this problem.
Fig.1. Ideal LC VCO Fig.2. Lumped Inductor Model

GSM specifications:
Frequency range = 935 ~ 960MHz vc = 0.75 ~ 1.75V
Switching time = 800µsec VDD = 2.5V
Technology parameter:
Metal sheet resistance = 35 mΩ/sq.
Substrate layer resistivity = 0.015 Ω-cm
Metal to substrate capacitance = 5.91 aF/µm2
Metal to metal capacitance = 98.0 aF/µm
Csub, Rsub, Cp can be ignored
PLL Problems and Solutions (9/6/03) Page 29

Problem 29 - Continued
Solution

Av1 = Av2 = Gm * (rout || L || C/2)

1 1
Av1(s) = Av2(s) = Gm 1 1 C = Gm s L L C where Gm and rout are
2
rout + Ls + 2 s 1 + s rout + s L 2
the transconductance and the output resistance of M1 and M2 transistors respectively, C/2 is the
total output capacitance at the outputs Von and Vop. For this circuit to oscillate, the gain around the
loop must be equal to negative one; therefore, each cross coupled gain stage can be presented as
Av1(s)
shown below. Hence, the total gain equation around the loop is equal to H(s) = 1 - A .
v1 (s)
Substituting for Av1(s),
Gm s L
L C
1 + s r + s2 L 2 Gm s L
out
H(s) = Gm s L = C
1 - L C 1 - s L (G m - G o u t ) + s 2 L 2
1 + s r + s2 L 2
out
1
For this circuit to oscillate at ωosc = , it is necessary for the s term in the denominator to be
C
L2
1
equal to zero; hence, Gm = r = Gout
out
By forcing Gm greater than Gout a pair of complex poles are forced in the right side plane. This is
the condition to start oscillation. Once the oscillation starts, the Geff parameter (Geff = Gm – Gout)
C
L 2 C
approaches zero and the oscillation becomes sustaining, giving a Q = L G = 2L Reff
eff
PLL Problems and Solutions (9/6/03) Page 30

Problem 29 – Continued
Inductor Layout:
PLL Problems and Solutions (9/6/03) Page 31

Problem 30
A four-stage ring oscillator used as the VCO in a PLL is shown. Assume that M1 and M2 are
matched and M3 and M4 are matched. Also assume that
W
gm = 2 K' L ID where K’N = 100µA/V2 and K’P = 50µA/V2

and that rds = ∞. The parasitic capacitors to ground at the outputs are 0.1pF each.
(a.) If I =2mA, find the frequency of oscillation in Hertz. (b.) Find the W/L ratio of M1 (M2)
necessary for oscillation when I =2mA. (c.) If the current I is used to vary the frequency,
express the relationship between ωosc and I. In otherwords, find ωosc = f(I).
VDD

10µm 10µm
vi+ vo+ vi+ vo+ vi+ vo+ vi+ vo+ 1µm 1µm
vo- M3 M4 vo+

vi- vo- vi- vo- vi- vo- vi- vo- vi+ M1 M2 v -

i

F02E2P2
I

Solution
(a.) The small-signal transfer function of the stages can be written as,
Vout(s) gm1/gm3  Vout(jω)  ωC 
= → Arg   = -tan-1 
Vin(s) C gm3
s g +1  Vin(jω) 
m3
From the above, we see that each stage must contribute –45° of phase to oscillate. Therefore,
gm3 2K' 10·0.5I 2·50x10-610·10-3
ωosc = C = C = = 1010 rads/s → f osc = 1.59GHz
10-13
(b.) The gain of the 4-stage ring oscillator at ωosc should be equal to 1 so we can write,
4
 gm1/gm3 4 (gm1/gm3)
1=  = 4 → gm1 = 40.25 gm3 = 2 gm3 = 2 mS
 1+1 
2 mS = 2K' N (W/L)·1mA = 2·100x10-6 (W/L)·1mA
2mS
∴ (W/L)1 = 0.2mS = 10 → (W / L ) 1 = 1 0
(c.) From part (a.) we get,
gm3 2K' 10·0.5I 2·50x10-610·0.5I
ωosc = C = C = = 2.36x1011 I
10-13

ω osc =2.36x1011 I
PLL Problems and Solutions (9/6/03) Page 32

Problem 31
How does the oscillation VDD
frequency depend on I SS for a
ring oscillator using the stage - M3 M4
shown? Express your answer in W4
+ W3 L4
terms of VDD, V REF , I SS , the V vo1 vo2
REF M5 L3
simple large signal model
parameters of the MOSFETs (K’, VDD vi1 M1 W M2 v
1 W2 i2
VT, λ) and the W/L values of the 0.5ISS L1 L2
MOSFETs. ISS
M7 W7
Solution M6 ISS
W8 L7
This topology uses a replica L8 W5
biasing circuit to define the on- M8 L5
resistance of M3 and M4 based SU03H07P3
on the on-resistance of M5. The
on-resistance of M5 is
V DD -V REF
R on5 = 0.5I
SS
We can either assume that the W/Ls of M3, M4 and M5 are equal or since we know that Ron is
inversely proportional to the W/L ratio, we can write that,
W 5/L5
Ron3 = Ron4 = W /L Ron5
3 3
where W3/L3 = W4/L4.
Assuming a capacitance at each output of CL, allows us to write the transfer function of the ring
oscillator stage as,
Vo2-Vo1 gm1Ron3
=
V i1-V i2 sR on3 C L + 1
The phase shift due to a stage can be written as,
θi(jω) = -tan-1(ωRon3CL)
To oscillate, this phase shift needs to be equal to some value, say k (in degrees). Therefore we
can write that,
k 0.5I SS k
ωosc = R C = W /L
on3 L 5 5
W3/L3(V DD -V REF )C L
Therefore, the oscillation frequency varies linearly with ISS.
PLL Problems and Solutions (9/6/03) Page 33

Problem 32
In every practical oscillator, the LC tank is not the only source of phase shift. Hence, the actual
oscillation frequency may differ somewhat from the resonant frequency of the tank. Using the
time-varying model, explain why the oscillators’s phase noise can degrade if such off-frequency
oscillations occur.
Solution
If there is any off-frequency oscillations that are close to the actual oscillation frequency
or harmonics of it, we know from the LTV theory that these frequencies and their associated
noise will “fold” into the noise spectrum around the actual frequency and degrade the oscillator’s
phase noise. The following diagram illustrates the process.

in2
(ω) 1/f noise
∆f
∆ω ∆ω ∆ω

ω
∆ω ωo 2ωo 3ωo
Sφ(ω)
c0 c1 c2 c3

-∆ω ∆ω ω
Sv(ω)
Phase
Modulation
ωo 2ωo 3ωo ω
ωo-∆ω ωo+∆ω Fig. 3.4-32
PLL Problems and Solutions (9/6/03) Page 34

Problem 33
Assume that the steady-state output
amplitude of the following oscillator is 1V. k= M
L1L2 Comparator
Calculate the phase noise in dBc/Hz at an -
offset of 100kHz from the carrier from the vout
signal coming out of the ideal comparator. 2 +
Assume that L1 = 25nH, L2 = 100nH, M = in1 L1 L2 C
10nH, and C = 100pF. Further assume that
the noise current is SU03H07P4

2 = 4kTG ∆ f
in1 eff

where 1/Geff = 50Ω. The temperature of the circuit is 300°K.

Solution
First of all, several assumptions must be made to work this problem. They are:
1.) The load on the secondary of the transformer approximates a short.
2.) The output of the comparator is a square wave of amplitude 0.5V.
Our objective is to find the value of
 i 2 /∆ f Γ 2 
L{fm} = 10log10
 n2 rms

 2qmax2(fm) 2 
First, the influence of the transformer. The equations of a general transformer are,
V1 = sL1I1 + sMI2 and V2 = sMI1 + sL2I2
M
If we assume that V2 ≈ 0, then I2 ≈ L I1 = 0.1I1. Since we are looking at the square of the
2
current, we can write that the noise injected into the tank is
2
in2 2
in2
0.04(1.381x10-23)300
= 0.01 = 0.04kTGeff = 50 = 3.314x10-24 A2/Hz
∆f ∆f
Next, we will evaluate Γrms2. From the notes (page 160-21), we see that
∞
1
Γrms2 = 2 ∑cn2 where cn are the coefficients of the ISF represented by a Fourier series.
n=0
What are the cn? We shall assume that the ISF of the LC tank is a sinusoid of the same period.
Therefore, only the c1 coefficient is important. If the peak value of the ISF is 1V (a questionable
assumption) then the rms value is 0.707. Thus Γrms2 ≈ 0.25.
qmax = Cvmax = 100pF(1V) = 10-10 coulombs.
 3.314x10-24(0.25)
∴ L{fm} = 10log10 -20 5 2  = 10log10(4.14x10-13) = -123.82 dBc/Hz
 2·10 (10 ) 
L{fm} = -123.82 dBc/Hz
PLL Problems and Solutions (9/6/03) Page 35

Problem 34
A crystal reference oscillator and its associated transistor have the following specifications at
290°K.
Output frequency: 6.4MHz
Power output: +10 dBm
Noise figure: 2.0 dB
Flicker corner: 15 kHz
Loaded Q: 12x103
(a.) Determine and plot the SSB phase noise in dBc as a function of the frequency offset from the
carrier. Include the frequency range from 10Hz to 10MHz.
(b.) Suppose that this reference oscillator is used with a frequency synthesizer whose transfer
function from the reference to the output is
θn,o(s) N 2 ζω n s + ω n 2
=
θn,ref(s) Nref s 2 + 2 ζω n s + ω n 2

where N = 19,000, Nref = 256, ζ = 0.7, and ωn = 908 sec.-1. Make a plot of the SSB reference
noise in the output of the synthesizer.
Solution
(a.) NF = 2.0dB, F = 102.0/10 = 1.585, and Po = 10 dBm = 0.01W
 FkT 1  fo  2  fc  
L{fm} = 10 log  P  1 +  1 + fm 
 s  4Q2 f m    
 1.585·1.38x10-23·290 1  6.4x106 2  15kHz 
= 10 log     
0.01 1 +
4(12x103)2 f m   
1 + fm 
  
  71.11x10 3   1.5x10 4  
L{fm} = 10 log  6.348x10-19 1 + 2  1 + f m  
  f m  
-120

-130

-140

-150
dBc
-160

-170

-180

-190
10 100 1000 10 4 10 5 10 6 10 7
Offset from carrier, fm (Hz) SU03H07S5A
PLL Problems and Solutions (9/6/03) Page 36

Problem 34
(b.) The VCO phase noise transfer function is
θn,o(s) N 2 ζω n s + ω n 2 1271.2s 2 + 8.245x10 5
= Nref 2 = 74.219
θ (s)
n,ref s + 2 ζω s + ω 2
n n s 2 + 635.6s + 8.245x10 5
  θn,o(jω)  2 
θn,ref(dBc) = 10 log    L{fm }
θn,ref(jω) 
Below is a plot of the above equation as well as the transfer function, θn\,o(s)/θn\,ref(s), and the
input reference noise.
50
Transfer Function
0

-50
Input Reference Noise
-100
dBc Output Noise
-150
Noise Floor
-200
This region is not possible
-250
10 100 1000 10 4 10 5 10 6 10 7
fm SU03H07S5B
PLL Problems and Solutions (9/6/03) Page 37

Problem 35
Use the National Semiconductor website (www.national.com) to design a DPLL
frequency synthesizer for the GSM (935-960MHz) application. The channel spacing is 200kHz.
Choose an appropriate VCO from a manufacturer. Assume a 0.25µm CMOS process with a
3.3V power supply.
Your homework should show a block diagram for the resulting frequency synthesizer
with the blocks identified. Give the following parameters that you selected for your design:
1.) N, the divider ratio.
2.) ζ, the damping ratio
3.) The type of PD/PFD and the value of Kd.
4.) The type of VCO, Ko, and Vmin and Vmax.
5.) τL, the lock-in time or settling time and ωn, the natural frequency of the PLL
6.) Design of the loop filter including the time constants and component values.
Solution
The problem specifications call for the following:
• Standard : GSM
• Frequency band : 935 MHz ~ 960 MHz
• Channel spacing : 200 kHz
• Power supply : 3.3 V
• Technology : 0.25 µm CMOS
• Switching time : < 800 µs (by GSM standard)
Design
The block diagram for this design is as follows:

The central frequency to use is the geometric mean of the extreme frequencies (947 MHz).

The devices chosen for this design are:

1. A low phase noise PLL (PFD), (chip code LMX2346) from National Semiconductors.
This has a range of operation from 200 MHz to 2 GHz, so it is suitable here.
2. A VCO (chip code VCO191-947U) from Vari-L. Its frequency of operation is well-suited
for this GSM application: 934 MHz to 960 MHz.
3. A second-order loop filter. This will reduce the number of capacitors in contrast with a
higher order filter. And this can be done because the filter components are going to be
off-chip, so the needed capacitance values –relatively high– are realizable. This filter is
passive so as to avoid the non-idealities associated with an OPAMP (mainly, noise).
PLL Problems and Solutions (9/6/03) Page 38

Problem 35 - Continued
The comparison frequency at the input of the phase/frequency detector was chosen to be equal
to the channel spacing, i.e., 200 kHz. Therefore, the reference divider —ifusing a 10 MHz
crystal source at the input— and the feedback divider ratio can be found as:

f CRYSTAL 10 MHz
R= = = 50
f COMPARISON 200 kHz
f OUTPUT 947 MHz
N= = = 4735
f COMPARISON 200 kHz

Other parameters for this design are:

VCO
• K0 = 18 MHz/V
• Vmin = typ. 0.8 V @ 934 MHz (min. 0.4 V)
• Vmax = typ. 2.2 V @ 960 MHz (min. 2.6 V)

PFD
• Kφ (= Kd) = 4 mA ( or 4/2π [mA/rad] )

General
• Lock-in time = τL = 200 µs

The filter components were found to be (standard values given, ideal values in parenthesis):

C1 = 910 pF (943.6 pF)

C2 = 6.8 nF (6.6 nF)
R2 = 5.6 kΩ (5.7 kΩ)

Simulation Results

Simulation was performed using the computed standard values for the filter components
and are as follows:

Phase Noise performance:

• 0 dB bandwidth = 14.80 kHz
• Peak frequency = 7.40 kHz
• Phase noise peaking = 2.47 dB
• Phase noise @ 10 kHz offset = -90.56 dBc/Hz
• Phase noise @ 100 kHz offset = -118.86 dBc/Hz
• RMS phase error = 0.33°
PLL Problems and Solutions (9/6/03) Page 39

Problem 35 — Continued
Phase Noise

––– Total noise ––– PLL noise

––– VCO noise ––– TCXO noise
––– R 2 noise
Lock-in time performance for a frequency jump from 934 MHz to 960 MHz
(worst case) with a tolerance of 500 Hz:
• Lock-in time = τL = 215.31 µs
PLL Problems and Solutions (9/6/03) Page 40

Problem 35 - Continued
Frequency analysis (Bode plots):

• Natural frequency = ωn = 7.06 kHz

• Phase margin = 51.74°
• Spur gain at comparison frequency = 33.68 dB
• Loop bandwidth = 11.94 kHz
• Damping factor = ζ = 0.84

Spur level estimation

Spur Offset Description Spur Gain Leakage Component Pulse Component Spur Level
(kHz) (dB) (dBc) (dBc) (dBc)
200 1st Spur 33.7 -90.5 -76.3 -76.1
400 2nd Spur 21.7 -102.4 -81.2 -81.1
600 3rd Spur 14.7 -109.4 -84.2 -84.2

Therefore, this design is suitable for use in the proposed GSM application.
PLL Problems and Solutions (9/6/03) Page 41

Problem 36 – (10 points)

The phase noise of an oscillator is –40 dBc at 10 Hz offset and has a straight-line variation (on a
dBc vs. logf scale) variation to –85 dBc at 15 kHz offset. Determine the residual phase
modulation in the range of 300 Hz to 3 kHz.
Solution
We will solve this problem modeling the phase noise as a simple line on the dBc vs. log f
scale as y = mx + b where
y = dBc and x = logf
The slope of the curve on the dBc vs. log f scale is found as,
-85 - (-40)
m= = - 14.186 dB/dec.
log(15x103) - log(10)
The intercept, b, can be found as
-40 = (-14.186 dB/dec.)log(10) + b
b = -40 + (14.186 dB/dec)log(10) = -40 + 14.186 = -25.832 dBc
∴ y(dBc) = -14.186 dBc/dec (logf) – 25.832 dBc
Let y = L{f} dBc
We can write for both sidebands L{f} = 2(10-(25.832/10)) f -1.4186
Integrating from 300Hz to 3kHz, gives the residual PM,
3000
θrms = ⌠2[10-(25.832/10)] f -1.4186 df = 0.027 radians
⌡
300

Problem 37
On page 160-33 of the class lecture notes, the approximate rms value of the impulse sensitivity
function for single-ended ring oscillators is given as
2π2 1
Γrms ≈
3η3 N 1.5
Derive this approximate impulse sensitivity function.
Solution
This derivation follows that given in A. Hajimiri, et. al., “Jitter and Phase Noise in Ring
Oscillators,” IEEE J. of Solid-State Circuits, vol. 34, no. 6, June 1999, pp. 790-804.
The approximate waveform f(x)
and the ISF for a single-ended ring
oscillator is shown below and is 1 Slope
based on the assumptions that the
Slope = -fmax'
sensitivity during the transition is = fmax'
inversely proportional to the slope
and the rise and fall times are x
symmetrical. Γ(x) 2π
1 2
fmax' fmax'
x
2 1 2π
fmax' fmax'
SU03H08P3A
PLL Problems and Solutions (9/6/03) Page 42

Problem 37 - Continued
The Γrms can be estimated as,
2π 1/fmax '
1 ⌠ 2 1 ⌠ 2  1 3
Γrms2 ≈ ⌡Γ (x)dx = ⌡x2dx =
2π 0 4π 0 3π f max '
The normalized delay per stage is given as
η
^t =
D f max '
which is found from the following waveforms of the single-ended ring oscillator.
f(x) 1 1
fmax' fmax'
1 η
fmax'
η
fmax'
x
SU03H08P3B 2π
The period of the ring oscillator is 2N times larger than the normalized delay per stage and is
2Nη 1 π
2π = 2Nt^D = f ' → f max ' = N η
max

2  π  3 2π2 1
∴ Γrms2 ≈   =
3π N η  3η3 N 3
The result is obtained as,

2π2 1
Γrms ≈
3η3 N 1.5

Problem 38
A frequency synthesizer has a reference frequency of 5kHz and uses a 64/65 dual-modulus
prescaler. Determine the values of the A and M counters to give an output frequency of 555.015
MHz.
Solution
fo = Nfr
fo
N = f = 111003
r
N = MP+A
N  111003
M = Interger  P  = Interger  64  =1734, A = N –MP = 27
∴ A = 27 and M = 1734
PLL Problems and Solutions (9/6/03) Page 43

Problem 39 – (10 points)

When testing a frequency synthesizer, you observe the
frequency display shown above on a spectrum analyzer.
What important fact is obvious from the display?
Solution
Asymmetrical sidebands indicate the presence of f
fo SU03H09P2
both PM/FM and AM spurs.

Problem 40 – (10 points)

What is the main advantage of a fractional-N PLL synthesizer over an ordinary PLL synthesizer?
Explain.
Solution
A fractional-N PLL synthesizer gives much high frequency resolution than possible with
an ordinary PLL synthesizer having the same reference frequency.

Problem 41 – (10 points)

A 1600 MHz carrier together with a set of 20 kHz PM spurs are applied to a divide by 8
frequency divider. The power of the 200 MHz carrier frequency output of the divider is 0.2 mW
and the 20 kHz spurs have an amplitude of 20 µV. What is the phase deviation of the signal at
the input of the divider? All impedances are 50 ohms.
Solution
At the output,
Vs = 20x10-6 V and Po = 0.2x10-3 W
|Vs|2
∴ Ps = 50 = 8x10-12 W
Ps  8x10-12 
SSB = 10log10P  = 10log10  = -73.979 dB
o 0.2x10-3
At the input,
SSBinput = SSBoutput + 20log10(N) = -73.979 dB + 18.062 dB = -55.92 dB
 θd
SSBinput = 20log10 2 
  → θd = 2·10SSBinput/20 = 0.0032 radians
PLL Problems and Solutions (9/6/03) Page 44

Problem 42 – (10 points)

In the lecture notes, how a rotational frequency detector works is explained. Use explanation
and accompanying diagram to clearly explain how the rotational frequency detector works.
Solution
Rotational Frequency Detector
When referenceless frequency acquisition is desired for CDR applications, a frequency detector as
shown below can be used in a frequency locked loop for pulling the VCO frequency to the correct
data rate. Once, the VCO frequency is centered to corresponding data rate, the phase locking
loop takes over in order to sample the data at optimum sampling point.

DE-FF DE-FF up
A C
I-clk D Q D Q

data

B D down
Q-clk D Q D Q
DE-FF DE-FF

Figure 1: Rotational frequency detector. I and Q clocks come from the VCO. Data is the non-
return to zero (NRZ) data to be resampled by the clock and data recovery circuit (CDR).
The flip flops are double edge sampling FFs. States A and B hold the present sampled
I and Q clocks whereas the C and D hold the previously sampled inputs (A and B are
resampled) UP is 1 when AB CD = 00 10. DOWN is 1 when AB CD = 10 00.
A typical frequency detector waveform for data slower than VCO clock is shown below. Note that,
anytime when AB changes from 00 to 10 a DOWN pulse is generated. In this example, there is no
UP pulse since no 10 to 00 transition occurs.
data
I_clk
Q_clk
A
B
up 10 11 01 00 10 10 11 00 10 11 01 01 10 01 00 10 11 01 01 10 11 11 01 00 10
down

Figure 2: Typical FD waveform example.

In figure below, the I and Q VCO clocks are 12.5% faster than the incoming sampling clock. As a
result, the beat frequency (frequency offset between VCO and sampling clocks) vector shown,
takes 8 samples in counterclockwise direction to come to its initial position. Initially, the sampling
clock is sampling I and Q clocks when I is low and Q is high (01). Next time, it samples IQ=01 one
more time. Next two times, it samples 00. The next sampling result is 10. The decision point is 00
to 10 transition or 10 to 00 transition. In the former one, a DOWN signal is produced and in the
later case an UP pulse is produced. During the entire beat period (i.e., 8 samples) only one down
pulse is produced).

Q Q Q Q Q Q Q Q Q

01 11 01 11 01 11 01 11 01 11 01 11 01 11 01 11 01 11
I I I I I I I I I
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10

down
Figure 3: IQ clocks are 12.5% faster than sampling clock.
PLL Problems and Solutions (9/6/03) Page 45

Problem 42 - Continued
In the example below, VCO clock is 25% faster. Therefore, the beat frequency completes its full
rotation in 4 cycles. In 8 cycles there are two 00 to 10 transitions or equivalently two DOWN pulses
are produced by the frequency detector.

Q Q Q Q Q Q Q Q Q

01 11 01 11 01 11 01 11 01 11 01 11 01 11 01 11 01 11
I I I I I I I I I
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10

down down
Figure 4: IQ clocks are 25.0% faster than sampling clock.

Now, let s look at what happens if the VCO clock is 37.5% faster than the sampling clock. The beat
frequency rotation vector comes to its starting position in 8 cycles, and during which only one 00 to
10 transition is made. Note that from the 4th position to 5th position, the beat frequency vector, skip
the quadrant 00. Therefore, the past state of the sampling state CD and present sampling state
AB which goes to the four input AND signals are 01 and 10. As a result, both outputs remain at 0.
No UP and DOWN generated when one of the decision quadrants are skipped.

Q Q Q Q Q Q Q Q Q

01 11 01 11 01 11 01 11 01 11 01 11 01 11 01 11 01 11
I I I I I I I I I
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10

down
Figure 5: IQ clocks are 37.5% faster than sampling clock.

When the speed difference is 50%, there is no 00 to 10 transition. As a result no UP/DOWN pulses
generated.
Q Q Q Q Q Q Q Q Q

01 11 01 11 01 11 01 11 01 11 01 11 01 11 01 11 01 11
I I I I I I I I I
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10

Figure 6: IQ clocks are 50% faster (or slower) than sampling clock.

The case where VCO is 62.5% percent faster than the sampling clock: During the 8 sampling
period in which the beat frequency vector comes to its initial starting point, there is only one
transition between quadrants 3 and 4. This transition, however is on the reverse direction. That is
CD=10 to AB=00. The AND gates in this case generate an UP pulse. To the frequency detector,
VCO appears to be 37.5% slower instead of 62.5% faster. A wrong pulse is generated.
Q Q Q Q Q Q Q Q Q

01 11 01 11 01 11 01 11 01 11 01 11 01 11 01 11 01 11
I I I I I I I I I
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10

up
Figure 7: IQ clocks are 50% faster (frequency detector interprets this as VCO is 37.5% slower)
than sampling clock.

The above examples is for the case when VCO is faster. The case in which the VCO is slower can
be plotted similarly. When VCO is slow, the beat frequency vector traverses the IQ quadrant
planes in clockwise direction. In the light of above vector diagrams, the following frequency detector
output vs. frequency input waveform can be plotted.
PLL Problems and Solutions (9/6/03) Page 46

Problem 42 - Continued

Normalized frequncy
+1 detector gain

fc 3fc fc fc
4 2 4 frequency
0 fc fc 3fc fc error
4 2 4

-1
Figure 8: Frequency detector characteristics when the sampling input is clock instead of
NRZ data.

Note that, the pulling range of this frequency detector is +/-50% when a full rate clock signal is
rising (or falling) edge samples the I and Q VCO clocks, instead of data sampling the I and Q clocks
at both rising and falling edges. This case is explained below.

From Figure 8, the detector gain is maximum for +/-25% frequency offset. (Two DOWN pulses in
Figure 4 above). Above +/-50% frequency offset, the output changes polarity and VCO frequency
is pulled to the wrong direction. The useful range is, therefore only +/-50%.

The above phase diagram example is for the case if the frequency detector input is a full-rate clock
instead of NRZ data. We further assumed that, I and Q clocks are sampled only at one edge of
the clock (either rising or falling). A pseudo random NRZ data resembles to a clock with 1/4th of the
full speed clock as far as the transition density is concerned. If this fact is combined with the
double edge sampling nature of the actual frequency detector, the data sampling the I and Q
clocks can be assumed as half the full speed clock. That is, in above phasor diagrams, the IQ
clocks are effectively sampled every other time. In this case, the frequency detector characteristics,
changes polarity when VCO range exceeds +/-25% of the data rate. For actual data inputs,
therefore the frequency characteristics resembles to the following figure. The rounded edges of
the gain characteristics is due to the pseudo random nature of the input bit sequence (PRBS).

Normalized frequncy
+1 detector gain

f data fdata 3fdata f data

frequency
2 4 8 8 error
0 f data f data 3fdata f data
8 4 8 2

-1
Figure 10: Rotational frequency detector characteristics for PRBS NRZ data.