Control Design of PWM Converters: The User Friendly Approach

Control Design of PWM Converters:
The User Friendly Approach

Prof. Sam Ben-Yaakov
Email: [email protected];
Web: http://www.ee.bgu.ac.il/~pel/
Seminar material download: PET06
Power Electronics Technologies Conference
Long Beach CA, October 2006
 All rights reserved. Duplication or copying is not permitted

without written permission by author
Prof. S. Ben-Yaakov , Control Design of PWM Converters [2]
Motivation
Most switch mode systems need to operated

in closed loop
Performance largely dependent on the Compensator
(feedback) design
Loop control design is conceived as “black magic”
OR requiring tedious analytical derivations
Digital control is becoming relevant
1
Objective
To present a user friendly version of control

loop design including both analog and digital
control
Based on:
Intuition
Simulation
Simple calculations
Outline
1. Basics of feedback theory and graphical representation
2. Relationship between LoopGain and dynamic response
3. PWM converters as feedback systems
4. Voltage Mode (VM) control
5. Current Mode (dual loop) control
6. Simulation tools
7. Average models
8. Analog compensator networks
9. Digital control
10. Q&A
2
1. Basics of feedback theory and graphical

representation
Block diagram of a feedback systems

(one loop)
Sin + Sε Sout
A OL
- S
f
So A OL
A CL = = LG ≡ β A OL
Sin 1 + β ⋅ A OL
So 1 So
= = A OL
Sin β⋅ A β Sin β⋅ A
OL >>1 OL << 1
3
Block Diagram
Sin + Sε Sout
H1 P
- S
f
H2 K
HHHH HHHH L
PPPP1111 HHHH G
SSSS SSSS
AAAA
oooo
= =
C
L
1111
KKKK ffff
PPPP
+
i
n
1 2
142 4
3
(((( ))))
Effect of Feedback
Sin + Sε Sout
P
- S
f
H2 K
So P
A CL = = ACL =
1
Sin 1 + H2 P K LG( f )>>1
H2 K
123
LG(f )
4
PWM Converter
βm βe
Block diagram concepts

Vin H2
+ Sout
Sin + Sε +
H1 P
So H1 P
- S A CL = =
f
S in 1 + H 1 P K
K
123
LG ( f )
Power
Vin
Power Vo vo 1
stage A CL LG ( f ) >> 1
=
R1 K
C R3
-
MOD +
d D ve Ve Vref R2
βm βe
5
Audio susceptibility
Vin H2
+ Sout
Sin + Sε +
H1 P
- S
f
Vin + Sout
H2
- S
f
So H2
= P H1 K
Vin 1 + LG
Sin + Sε S out
H1 P
- S
f
S′in + S′ε Sout

P
- S′
f
H1 K
Sout H1 P 1 Sout P 1
A CL = = → ≠ A′CL = = →
Sin 1 + k H1 P k S′in 1 + H1 P H1 k
But loop gains are equal: LG(f ) = H1 K P
6
Block diagram division

B
S′in + S′ε A Sout
H1 P
- S′
f
LG(f ) = A B
A – known (power stage + divider)

B – unknown (have to be designed)
Graphical representation of BA
A [ dB] conventional method
A AB [ dB]
f [Hz ]
AB
B [dB ]
B
f [Hz ]
f1 f2 f3
f [Hz ]
f1 f2 f3
Tedious – need to re-plot BA

Analysis (not design) oriented
Requires iterations
7
Graphical Representation of BA
1
20log A − 20log = 20log(BA)
B
A [dB ] 1
A 20logA = 20log ⇒ B⋅ A = 1
40dB − 20 dB / dec B
LG( f ) = BA BA = 1
1
20dB
B
B
A
>1 BA < 1
fo [Hz ]
fo = 1kHz
10 kHz
Stability of Feedback System
bm sm + bm−1sm−1 + ... + 1
H(s) =
an sn + an−1sn−1 + ... + 1
jω
σ − Zero
− Pole
α
RHP solutions include the term sin(ωt) e αt
8
Stability Criterion
H1 K
A CL =
1 + LG(f )
The system is unstable if {1+LG(f)} has roots

in the right half of the complex plane.
Nyquist criterion is a test for location of
{1+LG(f)} roots.
Nyquist criterion is normally translated into
the Bode plane (frequency domain)
Nyquist
Im[LG(f )]
unit circle
-1 f=0 Re[LG(f )]
Φm |LG|
Stable
9
Nyquist
Im[LG(f )]
Φm unit circle
-1
Re[LG(f )]
f=0
Oscillatory
Nyquist
Im[LG(f )]
Φm unit circle
-1 f=0 Re[LG(f )]
Phase Lead
Φm
Unstable
Phase Lag
The culprit: Phase Lag
Phase Lead in LG can help stabilize a system
10
Bode plane
BA
BA = 1
φo
ϕm
ϕm = ϕ|BA|=1 − (−180o ) = ϕ|BA|=1 + 180o
Bode plane
BA
BA = 1
φo
ϕm
ϕm = ϕ|BA|=1 − (−180o ) = ϕ|BA|=1 + 180o
11
Minimum Phase Systems

no Right Half Plane Zero (RHPZ)
A [dB]
− 20db / dec
− 40db / dec
f1 f2
f [Hz ]
phase
0 f [Hz ]
− 45 o
− 90o
− 135 o
− 180 o
Rate of closure (ROC)

(minimum phase systems)
BA dB
− 20 db
dec
− 40 db
+ 20 db dec
dec
− 20 db
dec
 f  f  f
 1 + j  ⋅  1 + j  ⋅  1 + j  ⋅ ⋅ ⋅ ⋅ ⋅
f f f
BA =  1  2   3  k
⋅ ⋅⋅ =
 f  f  f  f
 1 + j  ⋅  1 + j  ⋅  1 + j  ⋅ ⋅ ⋅ ⋅ ⋅ 1+ j 
 f1   f2   f3   fp 

12
Application of the 1/B curve

Rate of closure
dB rate of closure
A
− 20 dB / dec
1
B
− 40 dB / dec
f [Hz ]
f1 f2
Rate of closure of BA is the difference

between the A and B slopes
No need to re-plot BA
Design oriented approach
Stability Criterion
0 db dec
− 20 db dec
A db s u
s − 40 db dec
+ 20 db dec 0 db u
dec
− 20 db dec s − 60 db dec
s f
1 − 40 db dec
B db
If rate of closure − 20 db dec system is stable
13
Phase Margin Examples
dB A 20 dB / dec
20 dB / dec
ϕ m = 90 o 0 dB / dec
1 ϕ m = 90 o
ϕ m = 45 o
0 dB / dec
B − 20 dB / dec
ϕ m = 45 o
− 20 dB / dec
ϕ m = 90 o
− 40 dB / dec
− 20 dB / dec
ϕ m = 45 o
− 60 dB / dec
f
Phase Margin Calculation

A[dB]
− 20 dB / dec
p − 40 dB / dec
p
z − 20 dB / dec
p
1 p − 40 dB / dec
z
B
f [Hz ]
fO
For minimum phase systems history is not important
14
Approximate Phase Margin Calculation

A[dB]
− 20 dB / dec
p − 40 dB / dec
p
z − 20 dB / dec
p − 40 dB / dec
1 Phase lag in A
z f [Hz]
B p
fO
Phase lead in B
Get the accurate phase at intersection by simulation
Design Steps
A
| BA |
1/B
Draw A
Select cross point of BA (<< than fs/2, for PWM)
Select B shape
15
Stability of a Source-Load System

Front ZS
End POL
Converter ZL
POL
BUS
POL
ZL → negative resistance
System stability
V Vex + 1
ZS O
IO - ZS
IO
Vex Z
L
V
O Z
L
1
LoopGain = ZL
ZS
Convenient way to examine the LG stability is the Nyquist
stability test
16
2. Relationship between Loop Gain

and dynamic response
Response in Closed Loop

Sin S Sout
ε
H1 A
Sf
K
1
Desired : ACL =
K
1 1
What we get : ACL = ⋅ for ϕm ≤ 50o
K s2 s
+ +1
ω02 ω0 Q
1 1
ACL = ⋅ for ϕm ≥ 50o
K s +1
ω0 For small ϕm, ACL behaves
1
ACL (0 ) = as a second order system
K
17
Overshoot and Q in Closed Loop

in Response to step in Sin
cosϕ m
Q≅ for ϕm < 50o
sinϕm
Design target ϕm ≥ 45o
Load-Step Response
∆I
Zo
Sin S Sout
ε
H1 A
Sf
K
∆I Sout
Zo
A H1 K
Sout Zo
=
∆I 1 + A ⋅ H1 ⋅ K
1424 3 Small-signal output impedance
LG
18
Load-Step Response
Zof
Affected by:
Output impedance
ESR of output
capacitor
Slew rate of inductor
Output Impedance
(Immunity to load changes)
40 0
ZOf
0
ZO -100
-200
-40
1.0Hz 1.0KHz 1.0MHz
1.0Hz 1.0KHz 1.0MHz
db( V(OUT_S)/ i(V5))
0 db( V(OUT_S)/i(V5)) Frequency
Frequency
A
-50 v Zo
Z of = out =
1/B ∆io 1+ A
{B
-100 LG
1.0Hz 1.0KHz 1.0MHz
db(v(out)/V(LG_IN))
db( V(OUT)/ V(LG_OUT)) Buck converter – small signal
Frequency
19
Audio-Susceptibility (Line Regulation)

(Immunity to input voltage changes)
Vin
H2
+ Vout
Vref
Comp PS
+
-
Sf
K
Vout H2
=
Vin 1 + LG(f )
Large LG reduces susceptibility
Steady-state (DC) Error

Power
Vin
Power Vo vo
stage Sin + Sε Sout
R1 H1 P
C R3
- S
- f
MOD +
d D ve Ve Vref R2
K
βm βe
Sin
Sε =
1 + LG
Sε is the offset between the
sampled output and reference
Small DC error for large LG(0)
20
Dynamic Response
Summary
Systems that have a slope of –20 db/dec are easy to control
Response is largely determined by LG(f)
Desired LG:
LG as large as possible at low frequencies
(small DC errors)
LG of large BW - intersection point of A and 1/B
(quick response, fast recovery, rejection of Vin changes)
Phase margin > 450
(reasonable overshoot)
The culprit: Phase delay in LG
Nyquist
Im[LG(f )]
Φm unit circle
-1 f=0 Re[LG(f )]
Φm
Design target ϕm ≥ 45o
21
3. PWM converters as feedback systems
Issues:
Stability
Rejection of input voltage variations (audio
susceptibility)
Immunity to load changes
Quick response to reference change - good
tracking.
PWM converter in closed loop

Power
Vin
Power Vo vo
stage
R1
C R3
-
MOD +
d D ve Ve Vref R2
βm βe
Small signal responses

Linearization around operating point
22
Type of Blocks
Small Signals (Perturbation) Responses
Power
Vin
Power Vo vo
stage
R1
C R3
-
MOD +
d D ve Ve Vref R2
βm βe
Power stage is a Switching System (may be non linear)

Feedback is an analog or digital controller
Modulator: mixed mode
Linear control theory based design → small signal response
Small-Signals (Perturbation) Responses
Analytical solutions
Simulation
Injection of sinusoidal perturbation
AC analysis of behavioral average model
This seminar promotes the simulation approach
23
Small signal response of the modular

Power
Vin
Power Vo vo
stage
R1
C R3
-
MOD +
d D ve Ve Vref R2
βm βe
Relationship between ve and d (Km =d/ve)
Ve Small d
t
D Zoom
d
D
d is the AC component of D
24
Modulator
(Vp − Vv )t
Vt = + Vv
Ts
(Vp − Vv )ton
Vt = Ve = + Vv
Oscillator Ts
t on (V − Vv )
= Don = e
Ts Vp − Vv
ve v
d= = e
Vp − Vv Va
d 1
Km = =
ve Va
THE CONTROL DESIGN PROBLEM
KNOWN CONTROL
DESIGN
βm βe
vo
(f ) − Ana log Function βm = d
ve ve
A → Power Stage ; B → compensator
25
4. Voltage mode (one loop) control
Block diagram
Vin
(power ) Vo , v o
(power )
The power conversion system
Vref Controller
26
Buck small-signal frequency response

(CCM)
L Io i Vo
S o
vo
C RL
D
ESR
D d
MOD
vex
VD
Buck frequency response (CCM)

vo
, dB
d
3 -40dB/dec
20
0
1
Unstable -20dB/dec
-20
2
-40 f, Hz
100 1k 10k 100k
Second order plus zero due to ESR of CO
27
d
ve Dependence on Vin
Vin 40
0
Vin:
5V
Magnitude
-40
10V
-80
db(V(a))
15V
0d
Phase
-100d
SEL>>
-200d
10Hz 100Hz 1.0KHz 10KHz 100KHz 1.0MHz
p(V(a))
Frequency
d
Effect of Load
ve 40
RL=
0
10Ω - CCM
-40 50 Ω - DCM
Magnitude
100 Ω - DCM
-80
db(V(a))
0d
-100d
Phase
SEL>>
-200d
p(V(a))
Frequency
28
Buck Derived Converters
Forward
Half bridge (HB)
Full Bridge (FB)
Simulation is the simplest way to

obtain the transfer functions
Boost Power Stage

Small signal response
50
0 Magnitude
-50
DB(V(OUT)/V(DON))
0d
Phase
-200d
SEL>>
-400d
10Hz 100Hz 10KHz 1.0MHz
p(V(OUT)/V(DON))
Frequency
RHPZ – non minimum-phase system
29
CM Boost
40
SEL>>
-40
DB(V(OUT)/V(verror))
0d
-100d
-200d
p(V(OUT)/V(verror))
Frequency
Buck-Boost (Flyback) Power Stage

0d
-100d
SEL>>
-200d
p(V(OUT)/V(don))
40
-40
DB(V(OUT)/V(don))
Frequency
RHPZ – non minimum-phase system
30
5. Current Mode (dual loop) control
Current Feedback
The problem of voltage mode control:

Transfer function is second order
Solution: Add current Feedback
System order is reduced for each state

variable (inner loop) feedback
31
The effect of current feedback

L Io i Vo v
S o o
Vin C
D RL
N
D d AMP
MOD Vε
Ve v
e
io 1
= For ‘strong’ feedback
ve N
LG >> 1 vε → 0
1
io = ve
N
Transfer function with closed Current Loop

L Io i Vo v
S o o
Vin C
D RL
vo
N
D d AMP
ve
RL
MOD Vε
Ve v N
e
ve
N
Co
1
RL
2π ⋅ CoRL
First order system !
32
Current Mode
L io vo
S Co RL
inner
loop
K
d AMP
MOD Vε
ve AMP vref
outer
loop
Flat First order
The advantages of current feedback
vo
vo ve
ve − 20 db dec
− 40 db dec − 40 db dec
− 20 db dec
Typical power stage Same power stage

VM (outer loop) with
CM
33
7. Peak Current Mode (PCM) control
PCM Modulator
D
d
Ve , v e
Vo
= f (Don ) is the same !
Vin
34
Implementation CM Boost
L
Driver
Rf
R
FF
comp Cf RS
S
Clock
Error AMP Vref
Some controllers have amplifiers for sensed current
The nature of Subharmonic Oscillations

IL
Ve
The geometric explanation
∆I1 D<0.5 ∆I2<∆I1

∆I2
t
TS
IL Ve
∆I1
∆I2 D>0.5 ∆I2>∆I1
t
For D>0.5 need slope compensation
35
Extra delay in PCM (Ridley)
PCM is a current sampling process

Subject to sampling delay
Delay was derived by Ray Ridley
Important for frequencies above fs/10
Mostly of theoretical importance
Average Current Mode (ACM)

Block diagram
Vo
PWM mod
Z fv Zinv
Z fi
+
-
-
+
Vref
Current sample is filtered first attenuate high frequency (fS)
36
PCM and ACM
Both are current feedbacks

Both reduce the order of system
The difference is in BW of the
current feedback loop
Both increase the output impedance
Advantages of peak CM (PCM)

∗ Cycle by cycle protection
∗ Better dynamics
Disadvantages
∗ Leading edge spike
∗ Subharmonic oscillations
37
6. Simulation tools
General purpose simulators

Dedicated simulators
PC and web based simulators
This seminar promotes PC based general

purpose simulators
Why Simulation
• Most control design methods apply graphical

representations of transfer functions
• One can get the plots from analytical
expressions or by simulation
• Simulation is the easiest way to get “A” (the
small signal response of the power stage)
38
Computer Simulation of Power Conversion Systems
Desired Simulator’s Features

for Power Electronics Systems
• Convergence
• Physical models
• Small signal analysis
• Interfaces
• Run time
• Behavioral models
• Statistical and optimization analysis
• Discrete domain simulation capabilities
39
Some Popular Modern Simulators

SPICE Based (Berkeley)
• PSPICE – MicroSim - Orcad - Cadence
• ICAP/4 – Intusoft
• MICROCAP - Spectrum
Others
• PSIM - Powersim
• Simplorer -Ansoft
• PLECS -Plexim
Power IC Models Library
• AEi – Design Automation
PSPICE – The Physical Simulator

• Most popular
• SPICE based simulator (Berkley)
• Used extensively for circuit simulation
• Extensive physical models libraries
• Behavioral models (ABM)
• AC analysis
• Statistical analysis
• Optimization tool
• Some PWM models
• MATLAB/Simulink interface
40
Working with PSPICE
PSPICE Convergence Problems
• Very common in switched circuits simulation
41
AEi Power IC Library

• PWM controllers are not included in PSPICE libraries
• AEi’s library supports Power Electronics
150 SPICE Models for Popular Power ICs
Regulators, Controllers, Switchers
FET Drivers
Support for Capture and Schematics
Symbols
Example Applications schematics/simulations
Documentation
PSIM -The Switching Circuit Simulator

• Disregards switching instances
• Fast and effective time domain algorithm
• Constant time step approach
• Transient (time domain) based AC analysis
• User friendly intuitive interface
• Generic models: passive, switchers, motors
• Analog Behavior Models library
• Simulink interface
• Interface to magnetics program
• Prone to errors in simulation results

• Simple output graphics utility
42
PSIM AC Model
Excitation
source
• Multiple time-domain runs are used to obtain AC

response
PLECS – The MATLAB Plug-In
• Power tool-kit for SIMULINK

• Allows the simulation of power stage as integrated
part of MATLAB (SIMULINK) simulation without
introducing extra delays
• Ideal for investigating digital control loops in power
systems
• Only generic models

• Simulink interface for both schematic and
graphics
43
PLECS Circuit as a Simulink Block

PLECS Circuit
Ground
C2 R3 Mutual
I II
C: 10e-9 R: 10e3 Ind. 2
C1 R1
Vm1 V 1
C: 22e-6 R: 23
Vout
Am2 A 3
Llkg D1
I_L2
V_dc
V: 300
Am1 A 2
I_L1
D2
Output
Voltage
Vout
I_L1
PLECS Primary
m s Gate I_L2
MOSFET1 1 Circui t Current
4 V Vm2
Gate Sawtooth PWM
Saturati on D
D
0.724 Constant1 GateOut1
5
Secondary
GateOut1 Circui t
Current
Ground1
num(s)
-K-
s+2.564e5
Saturation1 Transfer Fcn Gain Drain
Voltage
5 Constant
PSPICE cycle-by-cycle model

PWM V(%IN+, %IN-)*100k Vin Snubber secondary
D3
out
IN- OUT-
IN+ OUT+ MBR360
E1 ETABLE R3 C3 2 1
4.3105Vdc (0,0) (15,15) 10k
10n L1 L2
V6 R7
0.5m 0.5m 10m
R14
23
2 IC = 48
D5 1 2
10
MUR160 L3 R2
V1 = 0 C2
0.002m
V4 22u
V2 = 5 V7
1
TD = 0
300Vdc Vd
TR = 9.999u
M3 0
TF = 0.0009u gate
PW = 0.1n IRF830
PER = 10u K K1
0 K_Linear
COUPLING = 1
L1 = L1
L2 = L2 R11
0
10k
C5 R6 R9
eaout
10n 20K C4 10k
3.9n
ETABLE
R13
OUT- IN-
80
OUT+ IN+
E2 Vref R12
V(%IN+, %IN-)*100k V5
5Vdc 1.2k
(4.36,4.36) (9.2,9.2)
EA 0
0
0
• Uses physical level models of “real” devices
44
PSIM Flyback cycle-by-cycle model

(Time Domain)
Demo
Real time: 3 ms
PSIM
DCM cycle-by-cycle simulation results
Rload=220Ω
• Textbook waveforms
45
PSPICE vs. PSIM Flyback

cycle-by-cycle simulation results
PSPICE vs. PSIM Flyback

cycle-by-cycle simulation results
Primary current
4.0A
2.0A
0A
-2.0A
Secondary current
4.0A
2.0A
0A
-2.0A
Output voltage
47.8V
47.7V
47.6V
47.5V
2.95 2.96 2.97 2.98 2.99 3.00
PSPICE PSIM Time, [ms]
46
Small Signal (AC) Analysis

(Needed for Control Design)
Two Alternatives:
1. Full switched circuit:

Injection of a sinusoidal perturbations
PSPICE manually
PSIM automatic
2. Average Model
PSPICE AC analysis
(linearization by simulator)
PSIM automatic transient injection
Small signal response by injection of

sinusoidal perturbations ( time domain)
L Io i Vo
S o
vo
C RL
D
ESR
D d
MOD
vex
VD
Transient simulation – any simulator
47
PSIM Realization (Buck)
Power-Stage small signal transfer function

By injection of sinusoidal perturbation - PSIM & PSPICE
60
50 3V
dB
40
20mV Boost
Gain, [dB]
30
20
10
PSPICE
0 PSIM 50.0 Output voltage
-10 47.5
[V]
45.0
-20 Vpk-pk: 3V
100 1K 10K 40K 257µS
20
Sinus excitation
Frequency, [Hz]
[mV]
0
0 Vpk-pk: 20mV
-20
3.61 4.00 5.00 6.00 6.75
-50
Phase, [deg]
Time, [ms]
-100 257µS*1.5kHz*360 0
-150 PSPICE PSPICE

-200 PSIM
-250
100 1K 10K 40K
Frequency, [Hz]
48
The Behavioral Approach

Average Model of Flyback - PSPICE
R3
out
47.99V
10m
0.001 47.99V R4
in E1
IN+ OUT+
1 G1
R2
300.0V IN- OUT- L1 IN- OUT-
EVALUE IN+ OUT+ 22u
47.99V
{Vin} {Lmain} C1 23
V4 GVALUE
2
0V 0V
{Vin*V(d)-V(out)*V(doff)/n} {I(L1)*V(doff)/n} 0
137.9mV d PARAMETERS:
V5 n=1
ETABLE Vin = 300V
0.01Vac E2
doff862.1mV fs = 100kHz
IN+ OUT+ Lmain = 0.5m
IN- OUT-
V2
min(1-V(d),(2*{Lmain*fs}*I(L1)/(V(in)*V(d))-V(d)))
0.1379
0 0 Duty cycle generator
• Average models can be applied to obtain frequency

response – AC analysis (to be discussed later)
Signal injection versus Average model
Signalinjection
Applies the switching schematics as is
Takes a long time to run
Noisy at high frequency
Average model
Runs very fast
Need to built a behavioral equivalent
Some topologies/controllers are not easy to
convert to average circuits
49
PSIM vs. PSPICE AC Comparison

50
40
30
Gain, [dB]
20
10
0
PSPICE
vout -10
-20
PSIM
-30
d 100 1k 10k
Frequency, [Hz]
100k
-50
Phase, [deg]
-100
-150
PSPICE
-200 PSIM
-250
100 1k 10k 100k
Frequency, [Hz]
Behavioral average modeling

of switch mode systems
Applications:
• DC transfer functions
• Transient (large signal, time domain) phenomena
• Small signal (AC, time domain) transfer functions
Not applicable to:

• Switching details, rise and fall times, spikes
• Device characteristics and losses
• Subharmonic oscillations
• Conduction losses can be accounted for

• HF ripple can be estimated
50
7. Average Models
The Switched Inductor Model (SIM) Strategy
Identify the switched assembly
Replace the switching part by a continuous
behavioral (analog) equivalent circuit
Leave the analog part as-is
Run the combined circuit on a general purpose
simulator
The modeling methodology presented in this seminar is

highly ‘portable’, independent of simulator
Demonstration by PSPICE Ver. 10.5 (Demo Edition)
The switched inductor model

Switched
Assembly Vo
Vin +
−
D VE
Modulator Control
• The problematic part : Switched Assembly

• Rest of the circuit continuous - SPICE compatible
• The objective : translate the Switched Assembly
into an equivalent circuit which is SPICE
compatible
51
Average Simulation of PWM Converters

t on L Vout L Vout
b d a d c
+
Ib IL + IL IC
− RLoad − Ib RLoad
Vin IC Cf Vin Cf
c b
Buck Boost
t on Vout
b d c
+ Ib IC
Vin − RLoad
IL L Cf
a
Buck − Boost
Possible switch modes

b L a b TON L a
TDCM
TOFF
c c
TON - switch conduction time

TOFF - diode conduction time
TDCM - no current time (in DCM)
52
The Switched Inductor Model (SIM) (CCM)

The concept of average signals
TON b Ib
Ia a L
TOFF c Ic
Ia Ia
t
Ib Ib
t
Ic Ic
t
Objective : To replace the switched part

by a continuous network
TON b Ib
Ia a L
TOFF c Ic
⇓
b Ib
Ia a
?
c Ic
53
Average current
IL TON
TON b Ib Ib = = ILDon
Ia a L TS
IL c Ic TON
Don =
TS
I a = IL
I Ib
IL
Similarly :
Ib
IL TOFF
Ic = = ILDoff TON
TS
TS
Toward a continuous model

b I b = I L ⋅ D on
I a = IL a
c I c = I L ⋅ D off
⇓
Ga, Gb,Cc - current
dependent sources
Gb b Ib
Ga Ga ≡ IL
Ia a
G b ≡ IL ⋅ Don
Gc Ic Gc ≡ IL ⋅ Doff
c
54
IL derivation
dIL V d IL V
= ⇒ =
dt L dt L
X = X = Average value
VL IL
IL
VL V
VL
IL t
Average inductor voltage

VL
V (a,b )
V(a, b )
b
a L
c
V (a, c )
V(a, c )
Ton Toff
Ts
V(a, b) ⋅ Ton + V(a, c ) ⋅ Toff

V L= =
TS
= V(a, b) ⋅ Don + V(a, c ) ⋅ Doff
55
The Generalized Switched Inductor Model

(GSIM) Model
b IL
Gb
b Ga L
L
a a EL
c
Gc c rL
Ga = IL
Gb = IL ⋅ Don
Gc = IL ⋅ Doff Topology independent !
V L = V(a, b) ⋅ Don + V(a, c ) ⋅ Doff
Example: Implementation in Buck Topology

1. The formal approach b S L a
Vin c Co Ro
V(a, b) a Vo
IL
Ga
Gb EL
b Co Ro L
Vin Gc
c V(a, c ) rL
Ga = I(L) Gb = I(L) ⋅ Don Gc = I(L) ⋅ Doff
E L = [ V0 − Vin ] ⋅ Don + [ V0 − 0 ] ⋅ Doff
56
Implementation in Buck Topology

2. The intuitive approach - by inspection
S L Vo
Vin D C Ro
o
Ein = Vin ⋅ Don L Vo

Gb Co
Gb = IL ⋅ Don V IL
in Ro
Ein
Ein + Vo → VL
Polarity: (voltage and current sources) selected by inspection
Boost
L D Vo
Vin S Co Ro
L IL ⋅ Doff Vo
Co
Vin Ro
Doff ⋅ Vo
• Emulate average voltage on inductor

• Create IL dependent current sources
57
Making the model SPICE compatible
IL Don Ll
Gb
IL and DON are time dependent Variables {IL(t), DON (t) }

DON is not an electrical variable
In SPICE environment
⇓
Gvalue
V(Don ) ∗ I(Ll ) Ll
Don
+ Name of node : " Don "
−
Source
Don is coded into voltage
58
Running SPICE simulation
DC (steady state points) - as is
TRAN (time domain) - as is
AC ( small signal) - as is
• Linearization is carried out by simulator !
Discontinuous Model (DCM)

TON b
a L
IL TOFF c
IL
Ipk
T'off = Ts − Ton
t Ts − TN
Ton Toff D'off = = 1− Don
Ts
Toff
Ts
Doff ≠ 1 - Don
59
The combined DCM / CCM model
Gb b
IL
b Ga
L L
a a
c
Gc c
rL
Ga ≡ IL
IL Don IL Doff
Gb ≡ Gc ≡
Don + Doff Don + Doff
VL = V(a, b) Don + V(a, c) Doff
  2ILLfs 
Doff = min(1 − Don ),  − Don  
  V(a, b)Don 
Synchronous Power Stages

(diode replaced by switch)
Only two stated for switched inductor:

open and closed
No third state as in DCM
Use CCM model
60
Example: Buck Converter

L out
Vo
Vin puls R esr

D1 RL
Vin Cout
D
PWM
MOD
Vex
VD on
File: Buck_cy_by_cy.OPJ
Cycle by Cycle simulation

of PWM Buck converter buck_cy_by_cy.sch
PARAMETERS:
VIN = 10v
PARAMETERS:
Sbreak-X LOUT = 75u
Rinductor Lout COUT = 220u
S1 out
a RLOAD = 10
{Rinductor} {Lout} Cout
-
+
Vin Dbreak {Cout}

+
+
-
{Vin} in RLoad PARAMETERS:

- D1 Resr RESR = 0.07
{RLoad} RINDUCTOR = 0.1
+- {Resr}
VD
0 PW = 5u PARAMETERS:
PER = 10u FS = 100k
TS = {1/fs}
61
Power Start-Up at Constant Don
10V
0V
V(out)
10A DCM to CCM
0A
-10A
0s 2.0ms 4.0ms 6.0ms
-I(Lout)
Time
Zooming up
500mA
250mA
0A
1.535ms 1.625ms 1.750ms 1.862ms
-I(Lout)
Time
62
Average model
SIM
R dson L rL a Vo
b c Co
Vin Ro
rc
a
Ga IL
Rdson b Gb Co L
Ro
Gc rc EL rL
Vin c
File: Buck.OPJ
Average simulation by SIM-Model buck.sch
of PWM Buck converter
V(Don)*I(Lout)/(V(Don)+V(Doff))
b a NODESET= 5
PARAMETERS:
+
b Rinductor a
VIN = 10v
GVALUE c c
GVALUE
EL
{Rinductor}
Lout Ga
Cout
{Cout}
VDON = 0.5
Dbreak RLoad
Vin IN-
OUT- IN-
OUT- IN+
OUT+ {Lout} GVALUE
+ IC = 0 Resr PARAMETERS:
{Vin} D1 IN+
OUT+ IN+
OUT+ IN-
OUT- OUT+
IN+ {RLoad} LOUT = 75u
- EVALUE OUT-
IN- {Resr}
Gc COUT = 220u
Gb
RLOAD = 10
V(Don)*V(a,b)+V(Doff)*V(a,c) I(Lout) PARAMETERS:
0
V(Doff)*I(Lout)/(V(Don)+V(Doff))
RESR = 0.07
RINDUCTOR = 0.1
1V
Don Doff
- + EDoff
+ IN+
OUT+
VDon Vexcitation PARAMETERS:
- IN-
OUT-
FS = 100k
{VDon} etable TS = {1/fs}
0 min(2*abs(I(Lout))*Lout/(Ts*(vin-V(a))*V(Don))-V(Don),1-V(Don))
• Don coded into voltage

• Doff for CCM/DCM
63
Inductor
Rinductor
{Rinductor}
EL Lout
IN+
OUT+ {Lout}
IN-
OUT-
EVALUE
V(Don)*V(a,b)+V(Doff)*V(a,c)
Input side
V(Don)*I(Lout)/(V(Don)+V(Doff))
b
GVALUE GVALUE
c
Dbreak
Vin IN-
OUT- IN-
OUT-
+ D1 IN+
OUT+ IN+
OUT+
{Vin}
-
Gc Gb
0
V(Doff)*I(Lout)/(V(Don)+V(Doff))
64
Output side
NODESET= 5
+
a
Cout
Ga {Cout}
GVALUE RLoad
Resr
OUT+
IN+ {RLoad}
OUT-
IN- {Resr}
I(Lout)
DC Sweep plus Parametric (on Rload)
65
Sweeping Rload Constant Don

10V
8V
Diode losses
DCM
6V
CCM
4V
1.0 10 100 1.0K
V(out)
RLoad
Transient Analysis –Power Turn-On
66
Power Start-Up at Constant Don

10V
5V
0V
V(out)
10A
5A
SEL>>
0A
0s 2.0ms 4.0ms 6.0ms
-I(Lout)
Time
Comparing Cycle-by-Cycle to Average Simulation

766mA
400mA
0A
-268mA
1.625ms 1.750ms 1.875ms
-I(Lout)
Time
67
AC Analysis
The Real Strength of Average Simulation
Linearization
• The circuit is linearized by simulator (elements,
devices and expressions)
• Numerical linearization !
e.g. a source f(x,y,z) is replaced by:
f ( X + ∆X , Y , Z ) − f ( X , Y , Z )
x
∆X
f ( X, Y + ∆Y, Z) − f ( X, Y, Z)
+ y
∆Y
f ( X, Y, Z + ∆Z) − f ( X, Y, Z)
+ z
∆Z
• Transparent to user
68
PSpice simulations examples
Buck Average Buck Cy by Cy
Boost
a L main D1
c Vo
Vin puls R esr

RL
Vin Cout
b
D
PWM
MOD
Vex
VD on
69
Boost Simulation
SIM-Model under CCM & DCM
for PWM Boost converter Boost.sch
{Rinductor} Dmain
a b c out
Vin_pulse
PARAMETERS:
GVALUE Rinductor 1 Cout
+- Dbreak VIN_DC = 10v
I(Lmain) Gb {Cout}
EL Lmain Gc VDON = 0.5
Rsw RLoad
IN+
OUT+ IN+
OUT+ IN-
OUT- IN-
OUT-
Vin_DC + {Lmain} {Rsw} Resr {RLoad}
IN-
OUT- IN-
OUT- IN+
OUT+ IN+
OUT+
EVALUE GVALUE {Resr}
{Vin_DC} - Ga GVALUE PARAMETERS:
LMAIN = 75u
(V(Don)*V(a,b)+V(Doff)*V(a,c)) COUT = 220u
0 V(Don)*I(Lmain)/(V(Don)+V(Doff)) RLOAD = 10
V(Doff)*I(Lmain)/(V(Don)+V(Doff)) PARAMETERS:
1V Don
Doff RESR = 0.07
EDoff RINDUCTOR = 0.1
- +
+ IN+
OUT+
RSW = 0.1
VDon Vexcitation
- IN-
OUT-
{VDon} etable PARAMETERS:
FS = 100k
0 min(2*I(Lmain)*Lmain/(Ts*v(a,b)*V(Don))-V(Don),1-V(Don)) TS = {1/fs}
100V
ESR of Cout
1.0V 100mΩ
10 mΩ
1mΩ
10mV
V(out)
0d
-200d
SEL>>
-400d
1.0Hz 100Hz 10KHz 1.0MHz
P(V(out))
Frequency
RLoad= 10Ω
70
DCM
1.0V
DCM
V(out)
0d
SEL>>
-100d
1.0Hz 1.0KHz 1.0MHz
P(V(out))
Frequency
RLoad = 1000Ohm
PSpice simulation example
Boost simulation
71
Modulators – The Duty Cycle Generators

POWER STAGE
V in V out
Power
Input
D ON VL
Duty Cycle IL
'D'
Generator
V
E
Error Ampl.
Vref
ref
• General representation of a switch mode
DC-DC converter
PWM MODULATOR - Voltage Mode

D V − VM
= K M (voltage mode) = E
Ve VP − VM
d ve
=
Ve VP ⋅ VM
72
Coding
Vo
Vin +
−
D Modulator
KM Control
VE − VM
K M (voltage mod e ) =
Vp − VM
D coded into voltage
0 ≤ VD ≤ 1
Duty Cycle Limiter

• Behavioral dependent source ETABLE
E1
IN+
OUT+
IN-
OUT-
ETABLE
V(%IN+, %IN-)
TABLE = (0.1,0.1) (0.9,0.9)
Out
0.9
0.1
0.1 0.9 In
73
Average Current Mode

Vo
Vin +
−
D Modulator VE
KM Control
• VE is a function of Vo and IL
• ‘Control’ is the original analog circuit
• Same modulator as in voltage mode
Peak Current Mode Control

L=195 µ D
C=2000 µ
28v + R o =11.2 Ω R1
Rs
R c =0.012 Ω 47.5 Ω
25m Ω
R 2 =2.5k Ω
V p =0.25v
+
++
3.25
C f =0.23 µ R f =72.2k Ω
FF
+
+ 2.8v
74
Current Mode CCM

I(L)
V ( Ve ) − KS
V (Don) + V (Doff )
EDon =
 V ( a, b ) 
TS MC + KS 
 2L 
V(V)
KS = Current Loop Gain
MC = Slope Compensation
TS = Switching Period
L = Inductance of main inductor
|I(L)| = Average inductor current
If your can write an expression, it can be modeled !
SIM-Model under CCM & DCM

for Current-Mode PWM Boost converter
File: CM-Boost.opj
Schematic file name: CM-Boost\CM-Boost.sch
in
Power stage
a out
lin rind v(doff)*i(vl)/(V(Don)+V(Doff))
Vin_pulse +
{lin} 1m 0V {resr}
+- -
Ed_c ELs Gdoff resr RL
d_c vl
IN+
OUT+ IN+
OUT+ OUT-
IN-
Vin_DC + cout {RL}
IN-
OUT- Red_c IN-
OUT- OUT+
IN+
etable - evalue gvalue {cout}
1k {Vin_DC}
1/(v(don)+v(doff)) v(sw)*v(don)+(v(c)+v(out))*v(doff)+v(in)*(1-v(don)-v(doff)) PARAMETERS:

KS = 81.25m
Vexatation TS = 40u
1 MC = 6250
min(abs((2*i(vl)*lin/(ts*v(don)*(v(in)-v(sw))))-v(don)),1-v(don))
Verror + -
Edoff V13 PARAMETERS:
+
doff LIN = 195u
IN+
OUT+ -
IN-
OUT- Redoff RSEN = 0.025
1.09 FS = {1/ts}
etable 1k
DCG - CM PARAMETERS:
RSON = 1m
RSW = {rson+rsen}
RL = 11.2
Edon Gsw Gd
don sw c PARAMETERS:
IN+
OUT+ OUT-
IN- OUT-
IN-
IN-
OUT- rsw OUT+
IN+ OUT+
IN+
RESR = 0.012
1k d1 COUT = 2m
etable Redon {rsw} gvalue gvalue
Dbreak VIN_DC = 28
fs*(v(Verror)-ks*i(vl)*v(d_c))/(mc+ks*(v(in)-v(sw))/(2*lin)) i(vl)*v(d_c) i(vl)*v(d_c)
Doff CCM/DCM
75
Inductor
a
in
lin rind
Vin_pulse 27.99V
+
{lin} 1m 0V
+- -
ELs vl
IN+
OUT+
Vin_DC + IN-
OUT-
- evalue
{Vin_DC}
0V
v(sw)*v(don)+(v(c)+v(out))*v(doff)+v(in)*(1-v(don)-v(doff))
Duty Cycle Generator

min(abs((2*i(vl)*lin/(ts*v(don)*(v(in)-v(sw))))-v(don)),1-v(don))
Edoff
doff
IN+
OUT+
IN-
OUT- Redoff
etable 1k
0V
Edon
don
IN+
OUT+
IN-
OUT- 1k
etable Redon
fs*(v(Verror)-ks*i(vl)*v(d_c))/(mc+ks*(v(in)-v(sw))/(2*lin))
76
50
vo
d
0
vo
SEL>> ve
-50
db(V(OUT)) db(V(OUT)/ V(DON))
0d vo
ve
-200d vo
d
-400d
p(V(OUT)) p(V(OUT)/ V(DON))
Frequency
V(out)/V(Don) as normal
V(out)/V(Verror) lower order
PSpice simulation example
CM-Boost
77
Models of IC Controllers
Vendors do not supply simulation models of IC

controllers
Large signal controllers’ models are supplied with
some simulators (e.g. PSIM)
Average models ( applicable for small signal
analysis) are available from AEi
It is easy to build your own behavioral average
models (for control)
The Power Stage small-signal response
A prerequisite for control design

Can be obtained by analytical derivations/expressions
By Simulation
– On switched model (cycle by Cycle)
– Average models
78
Feedback Loop Design

of PWM Converters
AOL
1. Find A(f) of Power Close loop
stage Bandwith f o
2. Decide on f0 |βA|
3. Choose type of
1/β
compensating
network Break frequency not
4. Calculate feedback important,
network as low as possible
Make βA as large as possible
The Relationship to PID
vcomp K
H(s ) = = Kp + I + s ⋅ K d =
ve s
K d ⋅ s2 + K p ⋅ s + K I K d (s + ωz1) ⋅ (s + ω z2 )
= =
s KI s
ω z1,2 =
− Kp ± (Kp )2 − 4KdKI
2K d
79

K d ⋅ s2 + Kp ⋅ s + K I K d (s + ω z1) ⋅ (s + ω z2 )
= =
s KI s
Vcomp
Ve
[dB]
f1 f2
Vcomp
f1 f2
Ve
[dB]
1
B
80

Vo
d
[dB] dB
- 40
dec
dB
- 20
dec
BW Limitations
(of LG, crossing of A and B)
PWM is a smapled data sysyem .

Nyquist sampling theorem applies
Cross over frequency fo (A, B, LG ) < fs/2
In practice fo < 10 fs/2
81
8. Analog compensator networks
Possible phase compensation schemes

Lag (A)
Rf
Ao =
Rin
1
fp =
2πC f R f
82
Lag (B)
40
R2 0
out1
0V C1
100k
0V -40
10n
R1 E1 db(V(out1))
0d
IN+ OUT+
V10V 1k
1Vac IN- OUT-
EVALUE
0Vdc V(%IN+, %IN-)*1E6 -50d
SEL>>
-100d
p(-V(out1))
Frequency
Lag – Lead (B)

1
β
f
A o = A OL (ampl.)
β
1 20 db dec
fL =
2πC f R f A0
f2
f
R f1 A2
A2 = f
Rin
83
Lag-Lead (B)
100
R9
0V 0V
1g
50
R3 C2
out2
10k 10n
0
db(V(out2))
R4 E3 0d
IN+ OUT+
V20V 1k
1Vac IN- OUT-
EVALUE
0Vdc V(%IN+, %IN-)*1E6 -50d
SEL>>
-100d
p(-V(out2))
Frequency
Double zero compensation scheme

R3
A OL R1
C 2 > C3 R3
1 R2 β
R1< R 2
2 π f ⋅ R 2C3
64748 64748 6474 8 64748

1 1 1 1
< < <
2π ⋅ R 3C2 2π ⋅ R 2C1 2π ⋅ R1C1 2π ⋅ R 3C3
14243 1424 3 1424 3 14243
1
2 π f ⋅ R 2C3
1
dB
β
− 20
dec
84
Double Zero (B)
1g 40
R8
C4
0V
100p
20
R7 C3
100k 10n
out3
C5 R5 E2 0
db(V(out3))
0V IN+ OUT+
V3 0V 10n 1k 100d
1Vac R6 IN- OUT-
EVALUE
0Vdc V(%IN+, %IN-)*1E6
100k
0d
SEL>>
-100d
0 10Hz 100Hz 10KHz 1.0MHz
p(-V(out3))
Frequency
Double Zero- Alternative
C4
100p
C3 R4
C2
10n 22k
1n
R9 R8
out1 EVALUE
1k 100k IN- OUT- Don
IN+ OUT+
V2
R10 2.5 E2
1k
V(%IN+, %IN-)*1000k
85
Application of Double Zero Compensator
A
-20db/drc
-40db/dec
1/β
Rate of closure
20 db/dec
Phase advance by compensator
Voltage Mode Control

Compensator Design Example
VM Regulator
86
Obtaining the Loop Gain by Simulation
Sin + Sε Sout
H PS
- S
f
Sf
LG =
Sε
Loop Gain by Simulation
SS
Sin + Sε S′f + Sout
COMP H PS
- S
+ S′ε
f
S′
LG = f
S′ε
87
Loop Gain by Simulation
Sin + Sε Sout
H PS
-
Sf
S ′ε + S ′f
K
+
SS
S′f
LG =
S′ε
Loop-Gain
Getting Loop-Gain under closed loop response {A(f)*B(f)}
Vin=0
LG(f) = V1/V2
88
Rules for Getting Loop-Gain by Simulation

The relevant analysis is .AC
• Locate the AC source at the output of a low impedance

device (could be real or behavioral)
• Set the AC value to any value (1 V is fine)
• Make sure that there are no other AC sources in the

system
• Check bias point (.OUT file)
• Remember that the classical stability criteria take into

account the phase reversal (1800)
PSpice Simulation
VM Regulator
89
PSIM Demonstration
Large signal Small signal
Schematic Schematic
LoopGain TF
Probe
Probe Probe
Peak and Average Current Mode
IL
Vo
IL/Ve flat
inner loop
D
MOD
Vref
Ve
outer loop
Two step design: inner loop and outer loop
90
The advantages of current feedback

(PCM or ACM)
 Vo 
 
 Ve  − 20 db dec
 Vo 
− 40 db dec  
 Ve  − 40 db dec
− 20 db dec
Typical power stage VM Same power stage

(outer loop) with CM
With closed inner-loop
Inner Loop design

Average Current Mode
µ Ω
Vac = 1V ; Vc =Constant (operating point) ; KS= 1/20
91
out
L1 R1
in Co
0.1 GVALUE {Co}
{Lin} E1 Ro
IN- OUT-
OUT+IN+ IN+ OUT+ Resr {Ro}
OUT- IN- G1
Inductor EVALUE
0
.02
V1 Section V(Doff)*V(out)+V(in)*(1-V(Don)-V(Doff)) V(Doff)*I(L1)/(V(Don)+V(Doff))

100Vdc
0
0
Output
Section
0 E4
Don
IN+ OUT+
IN- OUT-
ETABLE
V(Ve)
0 Duty Cycle
Generator
E5
Doff
IN+ OUT+
IN- OUT-
ETABLE
Ve
0
min(2*i(L1)*{Lin}/({Ts}*V(Don)*V(in)+0.1m)-V(Don),1-V(Don))
PARAMETERS: V3
Lin = 1m 1Vac
Co = 450u
Ts = 10u DC = 0.74Vdc
Ro = 610
The response for inner loop design

80
I(L1)/V(Ve)
40
(13.154K,13.335)
0
1/β
-40
DB(I(L1)/(V(Ve)))
Frequency
F=13kHz; Gain= -13.3db=0.22
92
E2 Rin Rf Cf
ks
IN+ OUT+
IN- OUT- 15k 68k 820p Ve_out
EVALUE
I(L1)/20 Cfh 62p V2
Ve
1Vac
0Vdc
0 0
E3
Vc
Error IN+ OUT+
IN- OUT-
Amplifier EVALUE
1E6*V(%IN+, %IN-)
0
PARAMETERS: V3
Lin = 1m 0Vac
Co = 450u
Ts = 10u DC = 0.12Vdc
Ro = 610
• The error amplifier (For KS =1/20)
80
I(L1)/V(Ve)
40
(12.761K,13.564)
0
1/β
(2.9126K,10.624)
-40
DB( I(L1)/V(Ve)) -DB( V(VE_OUT)/I(L1))
Frequency
93
40
I(L1)/V(Vc)
0
-40
DB( I(L1)/V(Vc))
Frequency
Closed inner Loop
V in L VO
1m H D
CO RO
4 70 µ F 1 60 Ω
R in
C fh
Rf Cf
V E _O U T
D
KM
VE
VC
Vac = 1V ; Vc =Constant (operating point) ; KS= 1/20
94
LoopGain
100
(12.467K,72.211m)
-100
DB(V(VE_OUT)/V(Ve))
180d
(12.467K,60.107)
90d
SEL>>
0d
p(V(VE_OUT)/V(Ve))
Frequency
Phase margin 600
Nyquist Plot
20K
-20K
-40K
-20K 0 20K 40K
IMG(-V(VE_OUT)/V(Ve))
R(-V(VE_OUT)/V(Ve))
Imaginary(LG) versus Real(LG)
95
Nichols Plot
100
Phase margin
0
-100
-200d -150d -100d -50d -0d
db(V(VE_OUT)/V(Ve))
p(-V(VE_OUT)/V(Ve))
|LG| versus Phase(LG)
Closed Inner Loop

(Tracing)
40
I(L1)/V(Vc)
-40
DB( I(L1)/V(Vc))
Frequency
96
in
L1 R1
Closed Inner Loop
{Lin} 0.1
E1
OUT+ IN+
OUT- IN-
EVALUE
Rect. line V(Doff)*V(out)+V(in)*(1-V(Don)-V(Doff))
Abs(310*Sin(6.28*50*time))+0.01
Rin Rf Cf
E2 0
Inductor IN+ OUT+
IN- OUT-
ks
15k 68k 820p
Ve_out
Section EVALUE
I(L1)/20 Cfh 62p
IC = -1v
V2
Ve
1Vac
0Vdc
0 0
E3
Vc
Error IN+ OUT+
IN- OUT-
Amplifier EVALUE
1E6*V(%IN+, %IN-)
0
PARAMETERS:
Lin = 1m
Co = 450u Abs(2.4*Sin(6.28*50*time)/20)+0.01
Ts = 10u
Ro = 610
• Toward Power factor Correction (open loop)
Transient Simulation -CCM

4.0A
0A
I(L1)
-4.0A
I(L1)
1.0V
0.5V
Don
0V
V(Don)
1.0V
SEL>>
Don +Doff
0V
10ms 20ms 30ms 40ms 50ms
V(Doff)+ V(Don)
Time
In CCM: Don+Doff = 1
97
Transient Simulation - CCM/DCM

4.0A
0A
-4.0A I(L1)
I(L1)
1.0V
0.5V Don
0V
V(Don)
1.0V
SEL>> Don +Doff

0V
10ms 20ms 30ms 40ms 50ms
V(Doff)+ V(Don)
Time
After changing Lm to 300µH
Three Loops Feedback PFC System

(Conventional CCM)
RECTIFIER
Lin Dout
+-
AC PWM Cout Rload

R1
RS R3
+ -
R4
R2 M
Ref
98
UC3854 Based Average Model

POWER STAGE FILTER & LOAD
AC in rec out
sw Vout
Lbst
t R0 C0
line +
i L(t) Esw - Gsw
Vline ret Rs
Rci Rcz Vout

lineret Ccz
Rm Rvf
AC in pci
cai caout
Rff1 _ Ccp vaout
Cvf Rvi
Rff2 f cap D _ van
+
f1
Gm + + + vap Rvd
C
ff1 Cff 2 R
ff3 Eca - - + Vref
Eva -
E ff Rff
C. ERR. AMP
FF. LPF SQR-DIV-MUL PWM V. ERR. AMP
CCM - Based on UC3854

out
L1
sw
Gsw
line {Lin}
+ OUT-
IN- R18 {2*Ro}
Ro
rec 0V - OUT+
IN+
V1 E1 {Ro*2} Co
V_Iac Gvalue {Co} V4
+- IN+
OUT+
IN-
OUT- +-
IC = 390
Evalue V(Doff)*I(L1)/(V(Don)+V(Doff))
Racl Esw
abs(V(line))
{Rac} IN+
OUT+
Rs IN-
OUT-
ret
Evalue out
{Rs}
V(Doff)*V(out)+V(rec)*(1-V(Don)-V(Doff))
gvalue V_Iin
IN-
OUT- + Rci Rvi
IN+
OUT+ Rvf 180k
-
0V 4k 511k
Rcz Ccz
G3 Rm
vaout van
4k 24k 620p
caout Eva
cai Cvf 47n
I(L1)*V(Line)/abs(v(line)) Ccp OUT+
IN+
Rvd
OUT-
IN-
10k
62p
Riv
Eca Evalue vap
Gm
IN-
OUT-
cap 1000*V(%IN+, %IN-) +
IN-
OUT- IN+
OUT+
IN+
OUT+ Evalue Vref - 7.5V 1Meg
rec Gvalue 1E6*V(%IN+, %IN-)
E6 Doff
I(V_Iac)*(V(vaout)-1)/(pwr(V(f),2)) Don EDoff
IN+
OUT+
IN-
OUT- IN+
OUT+
Rff1 etable IN-
OUT-
Etable
910k
Rff2 f (V(caout)-1.1)/5.4
f1 min(2*I(L1)*{Lin}/({Ts}*v(rec)*V(Don)+0.1m)-V(Don),1-V(Don))
91k
Cff1 Cff2 Rff3

0.1u PARAMETERS: PARAMETERS:
0.5u 20k
Vrms = 230V RS = 0.25
RO = 610
CO = 450uF
RAC = 910k Av_Model_UC.opj
Lin = 1m
TS = 10uF
99
Voltage Control Loop

out
390.0V
R3
Gsw
{ESR}
Output Section
OUT-
IN-
Ro 390.0V
OUT+
IN+
{Ro}
0V
Gvalue Co
{Co}
0V IC = 390
out
V(Doff)*I(L1)/(V(Don)+V(Doff))
Rvi
Rvf 180k 511k
Excitation van
7.614V
V13 Cvf {Fed_Cap}
Eva
vaout ba_out Rvd
OUT+
IN+
7.614V 10k
1Vac OUT-
IN- 7.500V
7.492VR2
0V
0Vdc vap 0V
Evalue
Error Amplifier and 1000*V(%IN+, %IN-)
+
7.5V
1Meg
Vref -
Compensation Network
Input Voltage Step Response:

115Vrms to 230Vrms
400V
0V
SEL>> Input Voltage

-400V
v(line)
10A
Input Current
0A
-10A
400ms 450ms 500ms 550ms 600ms 650ms 700ms
i(V_Iin)
Time
Pout=250W, Slew Rate=160V/mS
100
Input Voltage Step Response:

115Vrms to 230Vrms
400V
0V
Input Voltage
-400V
v(line)
425.0V
412.5V Output Voltage

400.0V
SEL>>
375.0V
400ms 450ms 500ms 550ms 600ms 650ms 700ms
v(out)
Time
Pout=250W, Slew Rate=160V/mS
Current Loop Gain at Different Input Voltages

200
SEL>>
-200
db(v(ba_out)/v(Don))
0d
-100d
-200d
p(v(ba_out)/v(Don))-180
Frequency
Vin=50V, 100V, 200V, 300V
101
Loop Gain of Voltage Control Loop

0
-100
SEL>>
-200
db(v(ba_out)/v(vaout))
0d
Φm=650
-200d
-400d
100mHz 1.0Hz 10Hz 100Hz 1.0KHz 10KHz
p(v(ba_out)/v(vaout))-180
Frequency
PSpice simulation
PFC-AC PFC-TRAN
102
CCM Control Concept with no Sensing

of Input Voltage
I in L D Vo
IL
Vac Co Ro
Vin SW
Low Pass Doff

Filter
KM PWM
I L (av) Ve
Vref
M E/A
Average Model
L1 R1 0.1
in Out
{Lin}
G1
Vrms*1.414*abs(sin(6.28*50*time)) GVALUE
R6
OUT-
IN- C1 {res}
OUT+
IN+
Iin
THD meter
V(OUT)*V(doff)+V(in)*(1-V(Don)-V(Doff)) 1mF
IC = 390
i(l1)*(sin(6.28*50*time)/abs(sin(6.28*50*time))) i(L1)*v(Doff)/(v(don)+v(doff))
0.99 0.99
don Ipk doff
1-I(L1)*v(k)
0 0
v(in)*v(don)*{Ts}/{Lin} min(1-v(don),2*I(L1)/(v(Ipk)+1u)-v(Don))
Out
R3
V(%IN+, %IN-)*100k
770k
14 V1 E1
k eao ba_in ba_out
OUT+
IN+
1 1Vac OUT-
IN-
(14-V(%IN))*14m 0Vdc
EVALUE
+
-
V2
PARAMETERS: C2 R4 5
Lin = 1m 10k
res = {380*380/P} 3.3u
Ts = {1/100k}
Vrms = 220
P = 1kW
0
103
Input Behavior at Different Line Voltages

300V Rectified Input Voltage
200V
100V
SEL>>
0V
v(in)
20A
Inductor Current
10A
0A
730ms 740ms 760ms 780ms 800ms
I(L1)
Time
Pout=1kW, Vin=80Vrms, 230Vrms, 265Vrms
Loop Gain of Current Control Loop

100
SEL>>
-100
db(v(ba_out)/v(Don))
100d
0d
Φm=900
-100d
1.0Hz 10Hz 100Hz 1.0KHz 10KHz 100KHz
p(v(ba_out)/v(Don))+180
Frequency
104
Current Loop Transfer Function

-30
-40
iL/vin=const
-60
30Hz 100Hz 1.0KHz 10KHz 100KHz
db(i(l1)/v(in))
Frequency
PSpice simulation
PFC_no_sens-AC PFC_no_sens-TRAN
105
Conventional Border Line Control Method

L D
Vac DRIVER
Cout Rload
R1
Zero
QS Detector
-
R
R2
Ref
MC33261 Based Average Model
106

Out
1.414*{Vrms}*abs(sin(6.28*50*time))
L1 R1 iload
in
{Lin}
0.1 PARAMETERS:
0Vdc
Lin = 0.87m
R10
G1 {nom_load} Vrms = 220
THD P = 175W
THD meter
GVALUE Nom_load = {Vo*Vo/P}
OUT-
IN- C1 Rsense = 0.1
i(l1)*(sin(6.28*50*time)/abs(sin(6.28*50*time))) OUT+
IN+ Cout = 180u
{Cout}
Vo = 400
V(OUT)*V(doff)+V(in)*(1-V(Don)-V(Doff)) IC = 400
i(l1)*v(Doff)/(v(don)+v(doff))
1 1
Doff 1-v(Doff) Don
0 0
2*i(L1)*{Rsense}*V(in)/(v(Curr_tresh)*v(out))
2
Curr_tresh Out
in 10n
I1 R3
Error Amplifier
1.6meg
0.5m
R2 V(%IN2)*0.62* 0
1.3meg (V(%IN1) -2.5) R6 E1
Q2 inv
OUT+ IN+
1k OUT- IN-
5.7 Q2N2222
2 1 ea Q1 C2 EVALUE
0
2.1 Q2N2222 1.59u V(%IN+, %IN-)*17783 ref
0 0 +
C3 R4 R5
-
V2 10k
10n 2.5
12k C5
0.68u
0
PSpice simulation
PFC_bord-AC PFC_bord-TRAN
107
Border Line Control Concept with no

Sensing of Input Voltage
Principle of Operation
Vin
Iin
Ipk(t)
Iav(t)
V Vin ( t )
Ipk ( t ) = 2Iav ( t ) = in Ton = const. if Ton = const.
L Iav ( t )
108
Io = f(Vout)
T Toff
E = on EDoff =
Don T +T Ton + Toff
on off

Out
L1 R1
in
{Lin} iload
IC = 0.1
1.4*{Vrms}*abs(sin(6.28*50*time))
0Vdc
R10
G1 {nom_load}
GVALUE
THD
THD meter V(OUT)*V(doff)+V(in)*(1-V(Don)-V(Doff)) OUT-
IN- C1
OUT+
IN+
{Cout}
i(l1)*(sin(6.28*50*time)/abs(sin(6.28*50*time)))
IC = 400
i(l1)*v(Doff)/(v(don)+v(doff))
1 PARAMETERS:
Don Ton
Lin = 320u
0 CT = 2.7n
Vrms = 220
v(Ton)/(V(Ton)+V(Toff)) v(Vcontrol)*200u*{Cch}/(2*i(V_Io)*i(V_Io)+10n) P = 80
Nom_load = {Vo*Vo/P}
Rsense = 1
1 Toff Cout = 47u
Doff Vo = 400
Cch = {15p+CT}
0
v(Toff)/(V(Ton)+V(Toff)) 2*i(L1)*{Lin}/(v(out)-v(in))
Out
R3
ABM3 1meg
TABLE1 R6
i(V_Io) Vreg
300k R5
In Out Vcontrol 1meg
0 1.5v
194u 1.5v V_Io
C3 2.6V +
200u 0v 680n -
0 0
109
Combined Stage
(Boost-Flyback)
ON:
OFF:
• CB serves as output capacitor for Boost Section and as

input voltage source for Flyback section.
110
Average Model
Boost Inductor Section
R1 L1
in 1 2
{L1}
0.1
310*abs(sin(6.28*50*time)) V(Vc)*V(Doff1)+V(in)*(1-V(Don)-V(Doff1))
Boost Output Section Flyback Input

NODESET= 500 PARAMETERS:
+ Voltage Section
Vc L1 = 50u
n=7
I(L2)*V(Don)/(V(Don)+V(Doff2)) L2 = 100u
R4 Ts = {1/100kHz}
C1
I(L1)*V(Doff1)/(V(Don)+V(Doff1)) 1meg
50u
IC =
Flyback Inductor Section out

I(L2)*{n}*V(Doff2)/(V(Don)+V(Doff2))
V(Vc)*V(Don) V(out)*{n}*V(Doff2)
L2 R2
1 2 C2 R3
{L2} 0.01 100u 50
IC = 50
Load Section 0
min((2*I(L1)/(V(pk1)+0.1m)-V(Don)),1-V(Don))
V(in)*V(Don)*v(Ts)/{L1}
1
pk1 Doff1
0 1 0.2/5 E1
Boost Doff Generator Don R6 v(out)*5/50
OUT+ IN+
0 OUT- IN-
1k
0 EVALUE
min((2*I(L2)/(V(pk2)+0.1m)-V(Don)),1-V(Don)) V(%IN+, %IN-)*1e5
V(Vc)*V(Don)*{Ts}/{L2} R5 V2
1 5
Doff2 pk2
330k
C3
0
1u 0
Flyback Doff Generator
Feedback and Don Generator
V(in)*V(Don)*v(Ts)/{L1}
1 Doff Generator
pk1 Doff1
for Boost Section
0
Boost Doff Generator
V(Vc)*V(Don)*{Ts}/{L2}
1
Doff2 pk2 Doff Generator for
0 Flyback Section
Flyback Doff Generator
1 0.2/5 E1
Don R6 v(out)*5/50
OUT+ IN+
0 OUT- IN-
1k
0 EVALUE
Error Amplifier V(%IN+, %IN-)*1e5
R5 V2
and Don 5
Voltage
generator 330k
C3 Divider
1u 0
Feedback and Don Generator
111
Behavior at Different Power Levels

62.5V
Output Voltage
50.0V
37.5V
v(out)
1.0A
Inductor Current
0.5A
SEL>>
0A
671.4ms 680.0ms 690.0ms 700.0ms 710.0ms 721.4ms
I(L1)
Time
Vin=230V, Pout=100W, 50W
Combined Stage
(SEPIC with Transformer)
D in LB Df
LF
C out R load
SW
n:1
Vac
CB
PWM
+ -
E/A
Ref
112
ON:
OFF:
Vout (ILB +ILF)⋅n2
n
Average Model
Vc
R1 L1 I(L2)*V(Don)/(v(doff2)+v(don))
in 1 2 140u
R4 C1
0.0001 {L1} IC =
0 1meg
{Vrms}*1.414*abs(sin(6.28*50*time)) V(in)*(v(Don)+V(Doff1))-(V(out)*{n}+v(Vc))*V(Doff1)
I(L1)*V(Doff1)/(v(doff1)+v(don))
0
out
V(Vc)*V(Don)-V(out)*{n}*max(V(Doff2),V(Doff1))
L2 R2
1 2 PARAMETERS:
C2 R3
{L2} L1 = 90u
0.5 0 10m {load} n=6
IC = 19
L2 = 225u
Vrms = 265
Load = 5
0 Ts = {1/90kHz}
I(L1)*V(Doff1)*{n}/(v(doff1)+v(don))+I(L2)*V(Doff2)*{n}/(v(doff2)+v(don))
1 V6 0.495/5 E1
Don ba_in ba_out R6 v(out)*5/19
OUT+ IN+
0 1Vac OUT- IN-
10k
0Vdc EVALUE
V(%IN+, %IN-)*1e5
0
C4
V2
5
1u
R5
900k 0
V(in)*V(Don)*{Ts}/{L1} min((2*I(L2)/(V(pk2)+0.1m)-V(Don)),1-V(Don))
1 V(Vc)*V(Don)*{Ts}/{L2}
pk1 Doff1 1
pk2 doff2
0
0
113
Behavior at Different Power Levels

500mA
Inductor Current
250mA
0A
I(L1)
25V
Output Voltage
20V
15V
SEL>>
10V
640.0ms 650.0ms 660.0ms 670.0ms 679.7ms
v(out)
Time
Vin=230V, Pout=70W, 50W
PSpice simulation
PFC_DCM - avg PFC_DCM - CBC
114
9. Digital Control
Analog/continuous control
LG(s ) = K tKMPS(s )B(s )
115
Digital/discrete control
1
2NPWM
2NA/D
VA/D
e - s∆T ⇔
1
LG = K tKMK A/D e- s∆TPS(s )B(z ) z
• Sampling and computation delay

• Additional gain – KA/D
Sampling Issues
ZOH
Time
∆T
116
ZOH fs=10KHz
500Hz
1.5KHz
2.5KHz
Sampling Delays
1
TS =
fS
D (n) D (n+1)
Time
output
A/D computation PWM (n+1)
sample (n+2)
sample (n) sample (n+1) (result of sample (n))
Sampling rate = fs
117
Slow Sampling Rate
1
TS =
fS
D (n) D (n) D (n+1) Time
output
PWM (n+1)
A/D computation
sample (n+1)
sample (n) (result of sample (n-1))
fs
Sampling rate =
2
Compensation network, continuous

R1
Ve(t) R2 R1
- Vc(t) K=
R2 Ve (t ) dV (t ) V (t )
+
= −C c − c
R2 dt R1
τ = R1C
dVc (t )
Differential equation: − KVe (t ) = τ + Vc (t )
dt
Integral equation: − K ∫ Ve (t )dt = τ ∫ dVc (t ) + ∫ Vc (t )dt
K 1
− Ve (s ) = τVc (s ) + Vc (s )
Laplace transform: s s
Vc (s ) K
Transfer function: =−
Ve (s ) sτ + 1
118
Discretization rules
Differential equations transforms to difference equations

dV (t ) V [n] − V [n − 1]
⇒
dt ∆T
Integral equations transforms to summations
n-1
∫ V (t )dt ⇒ ∆T ∑ V[k ]
k = -∞
Z-transform is the discrete time dual of the Laplace transform
∞ ∞
− st dt ⇔ V (z ) =
V (s ) = ∫ V (t )e ∑ V[k]z −k
-∞ k =-∞
Transfer functions are represented in Z
jω Im[ z ] 1 unstable
S plane Z plane
stable
-1 Re[ z ]
σ 1
stable unstable -1
−1
vo 1 z
= =
v e z + a 1 + az −1
v o (1 + az −1 ) = v e z −1
v o = v o (n − 1) ⋅ a + v e (n − 1)
Unstable if a>1
119
The intuitive meaning of the z operator

s ⇒ derivative operator; z ⇒ Delay operator
vo z
(z) = 2
vin z −1
vo z−1
(z) =
vin 1 − z −2
vo (1− z−2 ) = vin z−1
vo = vo z−2 + vin z−1
vo = vo (n − 2) + vin (n − 1)
Continuous to discrete transformation
• Pole-Zero matching
• Zero Order Hold (ZOH)
• Trapezoid (bilinear) transformation
120
Pole-Zero matching
• Map discrete poles/zeros by zi = e si∆ T
• For complex s-domain roots si = ai + jbi → zi = e ai∆ T e jbi∆ T
• Maintain same DC gain G(s ) s=0 = G(z ) z =1
Vc (s ) K Z KP  1 
= →  ai = ; bi = 0 
Ve (s ) sτ + 1 z − e − ∆T τ  τ 
Vc (s ) V (z )
= c → P = 1 − e − ∆T τ
Ve (s )|s =0 Ve (z )| z =1
=
(
Vc (z ) K 1 − e − ∆T τ
=
m ) m, n - constants
Ve (z ) z−e − ∆T τ z −n
Zero Order Hold (ZOH)

Hold equivalent = sampled area
Vc (s ) K
z −1 =
s⇔ Ve (s ) sτ + 1
∆T
Vc (z ) K
=
Transfer function: Ve (z ) z − 1
τ +1
  ∆T
Vc (z ) K ∆T  1  m
=  =
Ve (z ) ∆T + τ  z − τ  z −n
 
 ∆T + τ 
K ∆T
τ + ∆T
τ
τ + ∆T
121
Trapezoid (bilinear) transformation

Hold equivalent = sampled area
Vc (s ) K 2 z −1
= s⇔
Ve (s ) sτ + 1 ∆T z + 1
K ∆T 2
Transfer function: τ + ∆T 2
Vc (z ) K
=
Ve (z ) 2τ z − 1 + 1
∆T z + 1
Vc (z ) K ∆T 2  z + 1 
=  
Ve (z ) τ + ∆T 2  z − 1 
Comparison of hold types
fs=50KHz
Vc (s ) 10
=
Ve (s ) 0.1s + 1
122
Effects of sampling rate
Hold Type: ZOH

Discretization:
Inherent Phase-lag
A/D and PWM Resolution

The Limit Cycle Problem
duty/Vc
Oscillatory output Stable output

[mV/bit]
123
No Limit cycle rules

One bit of the DPWM should change Vo
by less than 1 bit of the A/D
Taking into account the system gains

KPSK t qDPWM < q A/D
Compensator must include integral action
(included in PID)
System must satisfy Nyquist criterion

1 + A(s)B(s) > 0 1 + A(s)B(s) ≠ 0
Stability Oscillations
Digital Compensator Design Methods
Frequency domain based

Pole location in z plane
Time domain design
124
Frequency domain design
1. Design a frequency domain controller (Bode,

Nichols, etc.)
2. Refinement: take into account the sampling and
computational delays
3. Translate the analog controller into a Z equivalent
4. Simulate by numerical simulator (e. g. MATLAB)
Frequency domain design

References
[1] V. Yousefzadeh, W. Narisi, Z. Popovic, and D.
Maksimovic, “A digitally controlled DC/DC converter
for an RF power amplifier”, IEEE Trans. on PE, Vol.
21, 1, 164-172, 2006.
[2] G. F. Franklin, J. D. Powell, M. L. Workman, Digital
control of dynamic systems, 3rd edition, Prentice Hall,
1998.
[3] B. J. Patella, A. Prodic, A. Zirger, and D. Maksimovic,
“High-frequency digital PWM controller IC for DC-DC
converters”, IEEE Trans. on PE, Vol. 18, 1, 2, 438-
446, 2003.
125
Z Plane Design
Using the MATLAB SISO tool
1. Define the system structure
2. Define the Plant response
3. Define the compensator template
4. Select the analysis view (Root Locus, Bode, Nichols)
5. Insert design constraints (gain, BW, PM, settling time,
Natural frequency, etc.)
6. You can use the GUI to change pole/zero locations
(either in S or Z and observe the resulting closed loop
response
• Trial and error procedure
MATLAB SISO tool

References
[1] O. Garcia, A. de Castro, A. Soto, J. A. Oliver, J. A.
Cobos, J Cezon, “Digital control for power supply of a
transmitter with variable reference”, IEEE Applied
Power Electronics conference APEC-2006, 1411-
1416, Dallas, 2006.
[2] The Mathworks, Matlab control toolbox user guide,
available at www.mathworks.com.
126
Time domain Discrete Controller Design

● Digital compensator operates in the sampled-data domain
● Direct controller design - does not involve errors related to
approximations (s to z)
● When working in the time domain, system attributes such
as bandwidth and phase margin seem artificial
● Relevant parameters are: rise time, overshoot etc.
● Improved performance of the closed loop system
compared to other discrete design approaches
● Does not involve trial and error procedure

References
[1] G. F. Franklin, J. D. Powell, M. L. Workman, Digital control of
dynamic systems, 3rd edition, Prentice Hall, 1998.
[2] J. R. Ragazzini and G. F. Franklin, Sampled-data control
systems, McGraw-Hill, 1958.
[3] J. G. Truxal, Automatic feedback control systems synthesis,
McGraw-Hill, 1955.
[4] B. Miao, R. Zane, and D. Maksimovic, “Automated Digital
Controller
[5] Design for Switching Converters”, IEEE Power Electronics
Specialists Conference, PESC-2005, 2729-2735, Recife,
2005.
NEW [6] M. M. Peretz and S. Ben-Yaakov, Time domain design of
digital compensators for PWM DC-DC converters, IEEE
Applied Power Electronics conference APEC-2007, In
Press.
127

• Plant transfer function (continuous): A(s)
• S to Z transformation: A(s) -> A(z)
• Defining the desired closed loop response: ACL(s)
• S to Z transformation: ACL(s) -> ACL(z)
• Ideal controller:
A (z )B (z ) A CL (z ) 1
A CL (z ) = → B (z ) =
1 + A (z )B (z ) 1 − A CL (z ) A (z )
Closed-loop response
45o < ϕm < 90o
2nd order system Design constraint:

1
System will have the
s2 s characteristic equation
+ +1
ωn 2 ωnQ
128
Describing the closed-loop response by

time domain characteristics Step Response
1.6
2nd order system 1.4
Vo (s )
1.2
1
= 1
d (s ) s 2 s
+ +1
0.8
ωn2 ω nQ 0.6
0.4
0.2
1.8 1.8
Rise time: tr ≈ ⇒ ωn ≈ 0
0 5 10 15 20 25 30 35
ωn tr Time (sec)
π 1
 ln Mp
1+ 
( ) 2
− 1− 
2Q 4Q2  π 
Overshoot Mp = e ⇒ Q= −
2
ln Mp ( )
π
Describing the desired ACL in Z

• Second order characteristic equation sets the ACL(z)
denominator (a0, a1, a2)
2
Z b z + b1z + b 2
→ 0
s2 s a 0 z 2 + a1z + a 2
+ +1
ωn 2 ωn Q
• To derive the complete ACL equation (i. e. numerator)

additional constraints are to be satisfied:
• Stability at infinity (bounded system) ACL(z)|z=∞ = 0
• Steady state error to step ACL(z)|z=1 = 1
• Response to ramp (velocity constant) dACL(z) 1

=
dz |z=1 K V
129
Template-oriented controller
•Ideal controller to satisfy the design constraints
ACL (z ) 1
B(z )ideal =
1 − A CL (z ) A (z )
This design method suffers from:

• controller implementation on digital platform vary by
design (plant, ACL, etc.)
• High order - too many parameters – long computation
time
Template-based controller
● In each computational event, only data points
around the sampling instant are considered
● The controller uses only information that is in the
vicinity of the sampling instant and is blind to all
other information
● The implemented finite difference equation can be
based on a short-term time response of the
system rather than on the full response
130
A look at the step response of B(z)ideal
Objective:
• Find a compensator template that will match (or will be
close to) the the ideal response – at least at the first few
samples
• The compensator should have fewer computation cycles
The answer - PID controller

PID template: continuous
s2 s
+ +1
Vc (s ) ωc 2 ωc Q
=
Ve (s ) s
PID template: discrete p-z matching

Vc (z ) a + bz −1 + cz −2
=
Ve (z ) z −1 − z −2
Taking into account the sampling delay (A/D)

Vc (z ) a + bz − 1 + cz − 2
=
Ve (z ) 1 − z −1
131
PID controller
Difference Equation (will be implemented on the
digital platform)
Vc [n] = Vc [n - 1] + aVe [n] + bVe [n - 1] + cVe [n - 2]
Only 3 samples!!!
Only 4 computations!!!
Extracting PID coefficients (a, b, c)
Ideal
Amplitude
PID
132
PID coefficients extraction procedure

Vc [n] = Vc [n - 1] + aVe [n] + bVe [n - 1] + cVe [n - 2]
n=0 Vc [0] = Vc [- 1] + aVe [0] + bVe [- 1] + cVe [- 2]


n=1 Vc [1] = Vc [0] + aVe [1] + bVe [0] + cVe [- 1]
n=2 V [2] = V [0] + aV [2] + bV [1] + cV [0]
 c c e e e
Design example
Vo = 5V Switching frequency=sampling rate= 50KHz

Tr=100u 0.5044 z + 0.4123
A CL (z) =
z 2 − 1.403z + 0.4956
Mp=10%
133
Plant response
Amplitude
3.333 ⋅ 108 0.06548 z + 0.06459
PS(s) = ZOH PS(z) =
2 8
s + 2500 s + 1.333 ⋅ 10 z 2 + 1.908z + 0.96
Ideal controller response
0.5044z3 - 1.375 z 2 + 1.271z - 0.3958

B(z) =
0.06548 z3 - 0.1249 z 2 + 0.05945 z
134
Extracting PID coefficients (a, b, c)
3.4 − 6.15z −1 + 2.93z −2

B(z )F =
1 − z −1
Closed loop response

St ep Response
1. 4
1. 2 Ideal
1
0. 8 PID
Amplitude
0. 6
0. 4
0. 2
0
0 0. 5 1 1.5 2 2.5 3
Time (sec) -3
x 10
135
Closed loop step response - results
Reference is stepped from 5V to 6V
A look at the frequency domain

Magnitude (dB)
PM=40
BW=4KHz
Phase (deg)
136
Experimental
PM=33
BW=3.2KHz
Load step
PID coefficients
a=3.4
b=-6.15
c=2.93 Vout
137
Slower Response
Switching frequency=sampling rate= 50KHz
Vo = 5V
Tr=500u
Mp=0% No over shoot
Controller response
1.52 − 2.81z −1 + 1.38z −2

Derived PID: B(z )S =
1 − z −1
138
Closed loop
St ep Response
1. 4
1. 2
0. 8
A mplitude
0. 6
0. 4
0. 2
0
0 0. 5 1 1.5 2 2.5 3
-3
Time (sec) x 10
Closed loop step response - results
Reference is stepped from 5V to 6V
139
A look at the frequency domain
PM=80
BW=800Hz
Experimental
PM=80
BW=1.5KHz
140
Load step
PID coefficients
a=1.52
b=-2.81
c=1.38
Comparison to analog design
The analog controller was set to have the same

bandwidth as the digital design
Load step applied: 1A to 1.5A
141
Load step - analog (Spice simulation)
Load step - analog
142
Load step digital
Thank you for Your Attention
Thanks to the Israeli Science Foundation for

supporting our research
143
10. Q&A
Sort Biography of Presenter

Prof. Shmuel (Sam) Ben-Yaakov
BSc degree in Electrical Engineering from the Technion, Haifa Israel, in 1961
MS and PhD degrees in Engineering from the UCLA, in 1967 and 1970
respectively.
Full Professor at the Department of Electrical and Computer Engineering, Ben-
Gurion University of the Negev, Beer-Sheva, Israel,
Heads the Power Electronics Group of BG University
Published over 250 scientific and technical papers in leading journals and
conferences
Holds about 20 patents (as an inventor)
Consultant to companies worldwide on design-oriented theoretical issues in
the areas of analog and power electronics as well as on product development.
Founder and CTO of Green Power Technologies Ltd. (http://www.g-p-t.com)
Present research interests include: power electronics aspects of piezoelectric
elements, analog and digital control, power factor correction, lighting
electronics, soft switching and active thermal cooling.
144
Primary to secondary isolation
The problem :
Converter Filter RO VO
Isolation
barrier
Alternative
Pin
A C
Power Vo Power Vo
stage stage
isolation
feedback
- Gain
-
feedback
+ +
Vref isolation
Vref
B Vo
D
D Power D Power Vo
stage stage
D Gain +
feedback - feedback -
+
isolation +
Vref isolation
Vref
145

Control Design of PWM Converters: The User Friendly Approach

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Control Design of PWM Converters:

The User Friendly Approach

 All rights reserved. Duplication or copying is not permitted

Prof. S. Ben-Yaakov , Control Design of PWM Converters [2]

Most switch mode systems need to operated

To present a user friendly version of control

Prof. S. Ben-Yaakov , Control Design of PWM Converters [4]

1. Basics of feedback theory and graphical

Prof. S. Ben-Yaakov , Control Design of PWM Converters [6]

Block diagram of a feedback systems

Prof. S. Ben-Yaakov , Control Design of PWM Converters [8]

Prof. S. Ben-Yaakov , Control Design of PWM Converters [10]

Block diagram concepts

Prof. S. Ben-Yaakov , Control Design of PWM Converters [12]

S′in + S′ε Sout

But loop gains are equal: LG(f ) = H1 K P

Block diagram division

A – known (power stage + divider)

Prof. S. Ben-Yaakov , Control Design of PWM Converters [14]

Tedious – need to re-plot BA

Prof. S. Ben-Yaakov , Control Design of PWM Converters [16]

Stability of Feedback System

RHP solutions include the term sin(ωt) e αt

The system is unstable if {1+LG(f)} has roots

Prof. S. Ben-Yaakov , Control Design of PWM Converters [18]

Prof. S. Ben-Yaakov , Control Design of PWM Converters [20]

ϕm = ϕ|BA|=1 − (−180o ) = ϕ|BA|=1 + 180o

Prof. S. Ben-Yaakov , Control Design of PWM Converters [22]

ϕm = ϕ|BA|=1 − (−180o ) = ϕ|BA|=1 + 180o

Minimum Phase Systems

Prof. S. Ben-Yaakov , Control Design of PWM Converters [24]

Rate of closure (ROC)

Application of the 1/B curve

Rate of closure of BA is the difference

Prof. S. Ben-Yaakov , Control Design of PWM Converters [26]

If rate of closure − 20 db dec system is stable

Phase Margin Examples

Prof. S. Ben-Yaakov , Control Design of PWM Converters [28]

Phase Margin Calculation

For minimum phase systems history is not important

Approximate Phase Margin Calculation

Get the accurate phase at intersection by simulation

Prof. S. Ben-Yaakov , Control Design of PWM Converters [30]

Stability of a Source-Load System

Prof. S. Ben-Yaakov , Control Design of PWM Converters [32]

2. Relationship between Loop Gain

Prof. S. Ben-Yaakov , Control Design of PWM Converters [34]

Response in Closed Loop

Overshoot and Q in Closed Loop

Design target ϕm ≥ 45o

Prof. S. Ben-Yaakov , Control Design of PWM Converters [36]

Prof. S. Ben-Yaakov , Control Design of PWM Converters [38]

Audio-Susceptibility (Line Regulation)

Large LG reduces susceptibility

Prof. S. Ben-Yaakov , Control Design of PWM Converters [40]

Steady-state (DC) Error

The culprit: Phase delay in LG

Prof. S. Ben-Yaakov , Control Design of PWM Converters [42]

Design target ϕm ≥ 45o