670 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO.

5, MAY 1999

A CMOS Bandgap Reference

Circuit with Sub-1-V Operation
Hironori Banba, Hitoshi Shiga, Akira Umezawa, Takeshi Miyaba,
Toru Tanzawa, Shigeru Atsumi, and Koji Sakui, Member, IEEE

Abstract— This paper proposes a CMOS bandgap reference

(BGR) circuit, which can successfully operate with sub-1-V sup-
ply. In the conventional BGR circuit, the output voltage Vref is the
sum of the built-in voltage of the diode Vf and the thermal voltage
VT of kT=q multiplied by a constant. Therefore, Vref is about
1.25 V, which limits a low supply-voltage operation below 1 V.
Conversely, in the proposed BGR circuit, Vref has been converted
from the sum of two currents; one is proportional to Vf and the
other is proportional to VT . An experimental BGR circuit, which
is simply composed of a CMOS op-amp, diodes, and resistors, has
been fabricated in a conventional 0.4-m flash memory process.
Measured Vref is 518 6 15 mV (3 ) for 23 samples on the same
wafer at 27–125 C.
Index Terms—Bandgap reference, CMOS, low voltage. Fig. 1. Conventional BGR circuit, which is composed of a CMOS op-amp,
diodes, and resistors.

I. INTRODUCTION is expressed as

R EFERENCE voltage generators are used in DRAM’s,

flash memories, and analog devices. The generators are
required to be stabilized over process, voltage, and temperature
variations, and also to be implemented without modification (1)
of fabrication process. The bandgap reference (BGR) is one of
the most popular reference voltage generators that successfully (2)
achieve the requirements [1]. Regarding the generators, the de-
mand for the low-power and low-voltage operation is strongly
increasing the spread of battery-operated portable applications. where is Boltzmann’s constant (1.38 10 J/K) and is
The output voltage of the conventional BGR is 1.25 V, which electronic charge (1.6 10 C).
is nearly the same voltage as the bandgap of silicon. This In the conventional circuit, a pair of input voltages for the
fixed output voltage of 1.25 V limits the low operation. op-amp, and , are controlled to be the same voltage.
This work proposes a BGR that can successfully operate with is the forward voltage difference between one diode and
sub-1-V supply. diodes

II. CONVENTIONAL BGR CIRCUIT (3)

Fig. 1 shows the conventional BGR circuit, which is com-
posed of a CMOS op-amp, diodes, and resistors. It is essential The BGR output voltage then becomes
that the BGR circuit be designed without bipolar transistors
because most semiconductor memories are fabricated in the
CMOS process. A general diode current versus voltage relation conv (4)

where is the built-in voltage of the diode and is

proportional to the thermal voltage . Here, has a nega-
Manuscript received November 15, 1998; revised December 23, 1998.
H. Banba, H. Shiga, A. Umezawa, T. Tanzawa, S. Atsumi, and K. Sakui are tive temperature coefficient of 2 mV/ C, whereas has a
with the Microelectronics Engineering Laboratory, Toshiba Corp., Sakae-ku, positive temperature coefficient of 0.086 mV/ C, so that
Yokohama 247-8585 Japan (e-mail: [email protected]). is determined by the resistance ratio, being little influenced by
T. Miyaba is with Toshiba Microelectronics Corp., Sakae-ku, Yokohama
247-8585 Japan. the absolute value of the resistance. Thus, is controlled to
Publisher Item Identifier S 0018-9200(99)03678-1. be about 1.25 V where temperature dependence becomes
0018–9200/99$10.00  1999 IEEE

Authorized licensed use limited to: Aldo Bottelli. Downloaded on February 23,2010 at 16:27:53 EST from IEEE Xplore. Restrictions apply.
BANBA et al.: CMOS BANDGAP REFERENCE CIRCUIT 671

Fig. 2. Proposed BGR circuit.

negligibly small. As a result, the operational voltage cannot

be lowered below than 1.25 V, which limits the low-voltage
Fig. 3. Simulated Vref characteristics of the conventional and proposed
design for the CMOS circuits. BGR’s. The CMOS threshold voltages are optimized for the low-voltage
operation, such as PMOS Vth =0
0:3 V and NMOS Vth = 0:4 V.

III. PROPOSED BGR CIRCUIT

The concept of the proposed BGR is that two currents,
which are proportional to and , are generated by only
one feedback loop. Fig. 2 presents the proposed BGR circuit.
The PMOS transistor dimensions of , , and are the Fig. 4. Test-chip microphotograph. The size without the pads is 0.1 mm2 .
same, and the resistance of and is the same
If the resistor and diode parameters for the proposed BGR
(5) are the same as those for the conventional BGR, prop is
simplified as
The op-amp is so controlled that the voltages of and
are equalized prop conv (13)

(6) Therefore, prop can be freely changed from conv

of 1.25 V. for the proposed BGR is determined by the
Therefore, the gates of , , and are connected to a resistance ratio of , , and and little influenced by the
common node so that the current , , and becomes the absolute value of the resistance. The transistors , , and
same value due to the current mirror are required to operate in the saturation region, so that their
drain-to-source voltages can be small when the drain-to-source
(7) currents are reduced. Therefore, for the proposed BGR can
be theoretically lowered to if is set below .
In this case, and
IV. SIMULATED RESULTS
(8)
The minimum for the proposed BGR can be successfully
is proportional to lowered by the SPICE simulation when the threshold voltages
are optimized for a low-voltage operation. Fig. 3 presents the
simulated when the threshold voltages are optimized to
(9) ensure low-voltage operation of the op-amp, such as PMOS
V and NMOS V, which can definitely
is proportional to be realized for a low-voltage design. Here, in the conventional
BGR, is 1.25 V, and the minimum is 1.3 V. In the
(10) proposed BGR, however, the operational voltage is simply
limited by so that the minimum varies with the
Here, is the sum of and , and is mirrored to temperature. Even in the worst case of 10 C, the simulated
minimum for the proposed BGR is 0.84 V, which is lower
(11) than that for the conventional BGR by 0.46 V.

Therefore, the output voltage of the proposed BGR, , V. EXPERIMENT RESULTS AND DISCUSSION
becomes Fig. 4 shows a chip microphotograph of the proposed
BGR test chip, which has been fabricated in a conventional
prop (12) 0.4- m flash memory process with P-substrate CMOS, single
polysilicon, single silicide, and double metal. The test chip

Authorized licensed use limited to: Aldo Bottelli. Downloaded on February 23,2010 at 16:27:53 EST from IEEE Xplore. Restrictions apply.
672 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 5, MAY 1999

TABLE I
PROCESS PARAMETERS

Fig. 7. Measured Vref characteristics of the proposed BGR.

Fig. 5. Schematic of the proposed BGR test chip.

Fig. 8. Simulated results of the BGR implemented in the test chip.

515 mV 3 mV from 27 to 125 C for the whole voltage

region, where the voltage resolution in the measurement is
1 mV. The operation current is 2.2 A. Unfortunately, the
transistors were not designed for low-voltage operation of the
0.4- m flash memory, and their threshold voltages were high,
so we utilized the native transistors. As a result, the op-amp
operation was limited by a of 2.1 V. Fig. 8 shows the
simulated results of the BGR implemented in the test chip.
and , as shown in Fig. 5, are respectively given by

Fig. 6. Structure of the diode, which is easily fabricated by CMOS process. (14)
(15)
is composed of four pads; some transistors, resistors, and
capacitors; and 101 diodes. The size without the pads is where ( 1 V) is the threshold voltage of PMOS field-
about 0.1 mm . The process parameters for the test chip are effect transistors (FET’s) and ( 0.2 V) is that of native
summarized in Table I. The transistors were not designed NMOS FET’s. The minimum of the BGR is determined
for low-voltage operation, and their threshold voltages were as follows. In accordance with the decrease in with
high. The PMOS threshold voltage is 1 V, and the NMOS lowering, is equal to . This defines the minimum ,
threshold is 0.7 V. Fig. 5 shows the circuit schematic of the , which is given by
proposed BGR test chip. An N-type diffusion layer is used
for the resistors. Fig. 6 illustrates the structure of the diode, (16)
which is easily fabricated by CMOS process. The transistors,
with and applied to the gates, are native NMOS Fig. 9 compares the measured distribution of the con-
transistors ( V) because the threshold voltages ventional and proposed BGR’s. Supply-voltage, temperature,
of the enhancement-mode NMOS transistors exceed in the and process variations are included. There are four condi-
standard 0.4- m flash memory process. The control signal tions and three temperature conditions. Thus, there are twelve
PONRST is used to initialize the BGR circuit when the power matrix measurement conditions: , , , and
is turned on. The capacitors and stabilize the circuit. V; and temp , , and C. The number of samples
Fig. 7 shows the measured characteristics of the proposed is 34 for the conventional BGR and 23 for the proposed BGR.
BGR. is 515 mV 1 mV from 2.2 to 4 V at 27 C; and In the upper graph, 408 (4 3 34) points are plotted, and in

Authorized licensed use limited to: Aldo Bottelli. Downloaded on February 23,2010 at 16:27:53 EST from IEEE Xplore. Restrictions apply.
BANBA et al.: CMOS BANDGAP REFERENCE CIRCUIT 673

Hironori Banba was born in Niigata, Japan, on

August 8, 1970. He graduated from the Technical
High School of Niigata in 1989.
In 1989, he joined Toshiba Corp., Kawasaki,
Japan. From 1989 to 1990, he attended a one-year
technical training program at the Toshiba Computer
School, Kawasaki, Japan. From 1990 to 1997, he
was engaged in the research and development of
EPROM’s and flash EEPROM’s. Since 1997, he has
been designing embedded DRAM’s at the Micro-
electronics Engineering Laboratory, Toshiba Corp.,
Yokohama, Japan.

Fig. 9. Measured Vref distributions of the conventional BGR and the pro- Hitoshi Shiga was born in Matsuyama, Japan, on
posed BGR. The temperature and voltages are varied in the measurement: February 9, 1971. He received the B.S. and M.S.
Temp(27, 85, 125 C) 2Vcc (2.4, 2.7, 3.3, 3.9 V). degrees in physics from Kyoto University, Kyoto,
Japan, in 1994 and 1996, respectively.
In 1996, he joined the Microelectronics Engineer-
the lower graph, 276 (4 3 23) points are plotted. The ing Laboratory, Toshiba Corp., Yokohama, Japan,
where he has been engaged in the research and
of for the proposed BGR is 15.3 mV, which is about one- development of flash EEPROM’s.
third that for the conventional BGR of 44.5 mV. As a result,
the normalized dispersion, mean , for the proposed
BGR is 2.9%, which is similar to that for the conventional
BGR, 3.5%. The variation of for the proposed BGR
mainly originates from an offset voltage of the op-amp, as it
does for the conventional BGR. Considering the offset voltage
of , the BGR operates under the condition of Akira Umezawa was born in Tokyo, Japan, on
September 15, 1965. He received the B.S. degree
in metallurgical engineering from the University of
(17) Tokyo, Tokyo, Japan, in 1989.
In 1989, he joined the Toshiba Semiconductor
The total , including the effect of , is given by Device Engineering Laboratory, Toshiba Corp.,
Kawasaki, Japan, where he has been engaged
(18) in the research and development of EPROM’s
and flash EEPROM’s. He is now working on
the circuit design of nonvolatile memories at the
for the conventional BGR and Microelectronics Engineering Laboratory, Toshiba
Corp., Yokohama, Japan.
(19)

for the proposed BGR. The ratio of the effect of on

for the proposed BGR is the same as that for the conventional Takeshi Miyaba was born in Shizuoka, Japan,
BGR. To reduce the effect of on , it is effective to on April 19, 1969. He received the B.S. degree
decrease the ratio of , i.e., to increase . in electrical engineering from the University of
Ibaraki, Hitachi, Japan, in 1993.
In 1993, he joined the Toshiba Microelectronics
VI. CONCLUSIONS Corp., Kawasaki, Japan, where he has been engaged
in the research and development of flash EEP-
A CMOS BGR, which can operate with sub-1-V supply, ROM’s. He is now working on the circuit design
has been proposed and verified. is generated by the sum of low-voltage, low-power flash memories.
of two currents with one feedback loop. can be set at any
level between 0 V and . The simulated minimum of
0.84 V has been achieved. The measured is 518 15 mV
for 3 . The proposed BGR may therefore be a key technology
for low-voltage CMOS circuit design.
Toru Tanzawa received the B.S. degree in physics
from Saitama University, Japan, in 1990 and the
ACKNOWLEDGMENT M.S. degree in physics from Tohoku University,
Sendai, Japan, in 1992.
The authors wish to thank Dr. J. Miyamoto, M. Asano, K. In 1992, he joined the Research and Devel-
Numata, H. Kato, and S. Miyano for their encouragement. opment Center, Toshiba Corp., Kawasaki, Japan.
Since then, he has been working on the circuit
design of high-density flash memories. In 1996,
REFERENCES he transferred to the Microelectronics Engineering
Laboratory, Toshiba Corp., Yokohama, Japan. He is
[1] K. E. Kuijk, “A precision reference voltage source,” IEEE J. Solid-State now working on the circuit design of low-voltage,
Circuits, vol. SC-8, pp. 222–226, June 1973. low-power flash memories.

Authorized licensed use limited to: Aldo Bottelli. Downloaded on February 23,2010 at 16:27:53 EST from IEEE Xplore. Restrictions apply.
674 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 5, MAY 1999

Shigeru Atsumi was born in Tokyo, Japan, on Koji Sakui (M’92) was born in Tokyo, Japan, on
August 27, 1957. He received the B.S. degree April 29, 1956. He received the B.E. and M.E.
in applied physics from the University of Tokyo, degrees in instrumental engineering from Keio Uni-
Tokyo, Japan, in 1981. versity, Tokyo, Japan, in 1979 and 1981, respec-
In 1981, he joined the Semiconductor Device tively, and the Ph.D. degree from Tohoku Univer-
Engineering Laboratory, Toshiba Corp., Kawasaki, sity, Sendai, Japan, in 1995.
Japan, where he has been engaged in the research In 1981, he joined the Research and Development
and development of EPROM’s and flash EEP- Center, Toshiba Corp., Kawasaki, Japan, where he
ROM’s. He is now working on the circuit design was engaged in the circuit design of DRAM’s. Since
of nonvolatile memories at the Microelectronics 1990, he has been engaged in the development of
Engineering Laboratory, Toshiba Corp., Yokohama, high-density EEPROM’s. From 1991 through 1993,
Japan. he was a Visiting Scholar at Stanford University, Stanford, CA, doing research
in the field of multichip module and BiCMOS technologies. Currently, he is
managing both NAND- and NOR-type flash memory development.
Dr. Sakui is a member of the IEEE Electron Device Society.

Authorized licensed use limited to: Aldo Bottelli. Downloaded on February 23,2010 at 16:27:53 EST from IEEE Xplore. Restrictions apply.