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PLD 8

The document contains examples of blocking, non-blocking, case, and loop statements in Verilog. It includes code snippets for blocking and non-blocking assignments, a case statement to select between two inputs, and examples of forever and repeat loops. Test benches are provided to simulate each code example.

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Fahad Salman
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20 views2 pages

PLD 8

The document contains examples of blocking, non-blocking, case, and loop statements in Verilog. It includes code snippets for blocking and non-blocking assignments, a case statement to select between two inputs, and examples of forever and repeat loops. Test benches are provided to simulate each code example.

Uploaded by

Fahad Salman
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Blocking Statement

module blocking (input a, clk,


output reg b, c);
always @ (posedge clk) begin
b=a;
c=b;
end
endmodule
Test bench:
module blocking_test;
reg a, clk;
wire b, c;
blocking uut (. a (a),. clk (clk),. b(b), .c(c));
initial begin
a = 0; clk = 0;
#100; a = 0; clk = 1;
#100; a = 1; clk = 0;
#100; a = 1; clk = 1;
end
endmodule
Non_blocking Statement
module non_blocking (input a, clk,
output reg b, c);
always @ (posedge clk) begin
b<=a;
c<=b;
end
endmodule
Test bench:
module blocking_test;
reg a, clk;
wire b, c;
blocking uut (. a (a),. clk (clk),. b(b), .c(c));
initial begin
a = 0; clk = 0;
#100; a = 0; clk = 1;
#100; a = 1; clk = 0;
#100; a = 1; clk = 1;
end
endmodule

module case_1(input in0, in1, s,


output reg out);
always @ (*) begin
case (s)
1'b0: out = in0;
1'b1: out = in1;
default: out = 1'bx;
endcase
end
endmodule
Test bench:
module case_test;
reg in0, in1, s;
wire out;
case_1 uut (.in0(in0), .in1(in1),. s(s), .out(out));
initial begin
in0 = 0; in1 = 0; s = 0;
#100; in0 = 0; in1 = 1; s = 0;
#100; in0 = 1; in1 = 0; s = 0;
#100; in0 = 1; in1 = 1; s = 0;
#100; in0 = 0; in1 = 1; s = 1;
#100; in0 = 1; in1 = 0; s = 1;
#100; in0 = 1; in1 = 1; s = 1;
end
endmodule
Loop Statement
Forever Loop
module loop_forever (
input a, output reg b);
initial
b=0;
always @ (a)
forever #4 b=~a;
endmodule
Repeat Loop
module repeat_loop();
//input wire a,
//output reg out);
reg r_Clock = 1'b0;
initial begin
repeat (10)
r_Clock = !r_Clock;
end
endmodule

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