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Basic Concept: Multiplier

The document describes the design of a binary multiplier circuit using a hardwired control approach. It includes: 1) An explanation of the basic multiplier concept and an example multiplication of 1101 * 1011 shown in binary. 2) A state diagram and state table for a 3-state finite state machine that implements the multiplier using microoperations like shift, decrement, load, and clear. 3) Details of the control signals and sequencing needed to implement the multiplier circuit using either a sequence register and decoder, or a flip-flop per state.

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Florin Ungureanu
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113 views9 pages

Basic Concept: Multiplier

The document describes the design of a binary multiplier circuit using a hardwired control approach. It includes: 1) An explanation of the basic multiplier concept and an example multiplication of 1101 * 1011 shown in binary. 2) A state diagram and state table for a 3-state finite state machine that implements the multiplier using microoperations like shift, decrement, load, and clear. 3) Details of the control signals and sequencing needed to implement the multiplier circuit using either a sequence register and decoder, or a flip-flop per state.

Uploaded by

Florin Ungureanu
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Multiplier

Basic Concept
Multiplicand 1101* (13)
Multiplier 1011 (11)
1101
1101
0000
1101
10001111 (143)

Alternative method
1101* (13)
1011 (11)
0000 initial partial product
1101+ Multiplier MR0=1; ADD multiplicand
1101 partial product
01011 shift to the right
1101+ MR0=1; ADD multiplicand
100111 partial product
0100111 shift to the right
00100111 MR0=0; shift, no ADD
1101+ MR0=1; ADD multiplicand
10001111 final shift
010001111 (143) product
Binary Multiplier Block diagram
Initial state; 1101*1011

Final state
ASM for the Multiplier
WE assume, that the Multiplicand (B) and Multiplier (Q) registers have been loaded
already. P is the counter’s name. The C, A and Q registers are concatenated. IDLE,
MUL0 and MUL1 represent the 3 states necessary to implement this multiplier.

Hardwired control
• The ASM chart provides information about
– Control of the microoperations (control word)
– Sequencing of these operations
• The design can be split up in two parts:
– Control signals
– Sequencing

The control signals for the multiplier


The 4 output signals from the Control Unit are: Initialize, Shift/Decrement, LDA and
ClearC. The Shift and Decrement operations have a single common control signal. LDB
and LDQ assure the initial loading of the Multiplicand and Multiplier, they was not
included in the presented ASM.

Hardwired control
• The ASM chart provides information about
– Control of the microoperations (control word)
– Sequencing of these operations
• The design can be split up in tow parts:
– Control signals
– Sequencing

Control signals for binary multiplier


Module Microoperation Control signal name
Register A AÅ0; Initialize A,P
AÅA+B; Load A,C
C||A||QÅsrC||A||Q; Shift/Decrement C||A||Q,P
Register B BÅIN; Load B
Register C CÅ0; Clear C
CÅCout; Load A,C
Register Q QÅIN; Load Q
C||A||QÅsrC||A||Q; Shift/Decrement C||A||Q
Counter P PÅn-1; Initialize A,P
PÅP-1; Shift/Decrement C||A||Q,P

• Note: LoadB and LoadQ is supplied externally to the control unit.


Control Signal Expressions
Initialize= IDLE.G
Clear_C= IDLE.G + MUL1
Load= MUL0.Qo
Shift_Dec = MUL1

Sequencing
• The ASM chart give the sequence of microoperations
• Outputs can be removed: simplified ASM chart
– Conditional output boxes and any condition that does not affect the next state can be
removed
– The simplified ASM only contains information about the sequence
Simplified ASM

Similar to a State Diagram without outputs specified

State Table
3 states: IDLE (00), MUL0 (01) and MUL1 (10)
2 inputs: G and Z
Present State Inputs Next State
Name M1 M0 G Z M1 M0
Idle 0 0 0 X 0 0
0 0 1 X 0 1
MUL0 0 1 X X 1 0
MUL1 1 0 X 0 0 1
1 0 X 1 0 0
- 1 1 X X X X

Design
• Select Flip-flop types
• From the State Table we can find the input to the Flip Flops (for D FF)
• However, for complex circuits with many states this method can get difficult
• We’ll introduce two other methods that are simpler:
– Use of a Sequence Register and Decoder
– One Flip-flop per state
Sequence Register and Decoder
• We’ll use a register to represent the states with a decoder to generate an output signal
corresponding to each state.

•Use the State Table to find the input logic


•With D flip-flops: Di=Mi+ (next state)

State Table with Decoder outputs


Present State Inputs Next State Decoder Outputs
Name M1 M0 G Z M1 M0 Idle MUL0 MUL1
Idle 0 0 0 X 0 0 1 0 0
0 0 1 X 0 1 1 0 0
MUL0 0 1 X X 1 0 0 1 0
MUL1 1 0 X 0 0 1 0 0 1
1 0 X 1 0 0 0 0 1
- 1 1 X X X X X X X
D1 D0

Input Logic
• One can now use the Decoder outputs (instead of the flip-flop outputs) to generate
the input logic! This makes the design considerably simpler
• The expressions for the input logic can usually be written by inspection of the state
table: DM1 and DM0
DM0 = IDLE.G + MUL1.Z’;
DM1 = MUL0;
Schematic

Method2: One Flip-flop per State


• Very simple design
• More flip-flops needed than in previous method
• The ASM chart can be used to derive the logic circuit:
– Direct relationship between the ASM elements and the hardware
Correspondence ASM elements and Hardware
State Box

Decision Box
Junction

Conditional output box: use the output of the decision box as control signal

We assume that G is active for only one clock period.

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