Voltage-Tolerant Monolithic L-Band Gaas SPDT Switch: 1989 Ieee 1989 Ieee MTT-S Digest

00-3
Voltage-Tolerant Monolithic L-Band GaAs SPDT Switch

Steven W. Cooper and G. Austin Truitt
Texas Instruments Incorporated

P.O. Box 655474 MIS 255
Dallas, Texas 75265
ABSTRACT Drain
A monolithic GaAs L-band single-pole double-
t h r o w nonreflective (SPDTNR) FET switch has been
developed. The switch has shown t o be significantly
less sensitive t o DC r i p p l e w h e n compared t o
conventional FET switches. Also, the switch has the
advantage o f o p e r a t i n g w i t h either positive or
negative control voltages. Small-signal insertion loss
is less than 1.3 dB over a 1 t o 2 GHz bandwidth with
less than 1.3:l VSWR in all states Isolation exceeds 35 R
dB, w i t h a switching current requirement of less than
10 uA. The chip size is 0.97 mm x 1.75 mm x 0.1 5 mm
which permits more than 2100 monolithic switches t o
be fabricated on a 3-inch GaAs wafer.
Gate 4
INTRODUCTION
Series-shunt FET switches are often used for low

frequency applications (DC t o 6 GHz) when t h e rf
power handling requirements are small (typically
under 33 dBm) FET switches have an advantage over
PIN diode switches since FET current requirements are
on the order of microamperes and d o n o t require Source
external current drivers For a conventional series-
shunt FET switch, the bias voltages must be negative Figure 1. Lumped Element FET Schematic.
This paper describes a new switch topology which can
operate w i t h either positive or negative bias making source (8 ohms) When the gate is reversed biased
it TTL a n d CMOS compatible w h i l e m i n i m i z i n g w i t h respect t o the drain and source, Rgd and Rds
sensitivity t o DC bias ripple become very large while Cgd and Cds are quite small
The model thereby reduces t o an a p p r o x i m a t e
FET MODEL equivalent o f 4 ohms in serieswith a 0.45 pF capacitor
from drain t o source
To obtain the FET models for the switch design,
600 urn gatewidth FET's were rf characterized as MONOLITHIC CIRCUIT DESIGN
three-port devices. A model was then f i t t o t h e
resulting S-parameters. The gate of a FET creates a A novel approach t o reducing bias voltage
Schottky diode which can be modeled as a variable sensitivity is t o DC isolate t h e switch except f o r
capacitor Cgd in parallel w i t h a variable resistor control bias (Figure 2) The shunt FETs are DC
Rgd (Figure 1). The resistance of the gate finger is blocked, allowing their source potential t o float The
modeled as a lumped resistor Rg. Rc is the contact 44 pF blocking capacitors are large enough such that
resistance o f the drain and source pads. Rds and Cds their reactance i s negligible f o r the r f frequencies
are the variable drain-to-source channel resistance being considered The size o f t h e capacitors i s
and capacitance. When the gate is forward biased irrelevant t o switching speed since the rise t i m e i s
w i t h respect t o the drain and source, Rds, Rgd, Cds, determined by FET capacitance and bias resistance
and Cgd take on l o w resistive and capacitive values, By applying 4 5 V at VC1, and 0 5 V at VC2, the series
respectively. The value o f each element is difficult t o FETs in the RF1 path, and the shunt FETs in the RF2
determine. However, the n e t result i s t h a t t h e p a t h are f o r w a r d biased Their gates create a
channel is predominately resistive f r o m d r a i n t o Schottky barrier so that there is a 0 6 V diode drop
1113
CH2725-0189/0000-1113$01.OO 0 1989 IEEE 1989 IEEE MTT-S Digest
0.7
/
CONVENTIONAL TOPOLOGY
Vref
1 vc2 I
U- -
T NEW TOPOLOGZ
Figure 2. Switch Circuit Schematic.

from gate t o drain/source. Thus the voltage potential -0.1 f I I I I I
at Vref is approximately 3.9 V. The shunt FETs in the
R F l path, and the series FETs in t h e RF2 path are 0.00 -0.25 -0.50 -0.75 -1.00 -1.25
therefore reversed biased by 3.4 V and turned o f f .
The RF1 path is a l o w insertion loss path, while t h e Figure 3. Increasing Insertion Loss As A Function Of
RF2 path is isolated. The switch will work equally well Decreasing VC1 Voltage For The RF1 Path
w i t h negative bias voltage provided t h e potential (VC2 = -4.5V)
difference is greater than 2.5 V. Nominally the FET
drain-source spacing is 0.15 mils. By increasing the
drain-source spacing t o 0.55 mils in the first shunt
FETs, the FET channel on-resistance is approximately
50 o h m s a n d t h e s w i t c h i s t h e r e b y m a d e
nonreflective.
PERFORMANCE
m i i i
The advantage o f t h i s t o p o l o g y over t h e
conventional topology is best seen when comparing
insertion loss as a function of VC1 voltage. In the
conventional case, as VC1 oes negative the series FET
channels become d e p l e t e j o f charge carriers, causing a) c o n v e n t i o n a l topology b ) new topology
an increase in insertion loss. In the new topology, the
series FETs are f o r w a r d biased so t h e r e i s n o Figure 4. Comparison of the A M Modulation for the
substantial increase i n insertion loss until the shunt Detected RF Signal in the N e w and Old
FETs begin t o turn on. The t u r n o n p o i n t can be Topology.
expressed as follows:
VC2 - Vref = - I Vp 1 Table 1. Switch Performance.

where Vref = VC1 - 0.6 V
I I n s e r t i o n loss I < 1.3 dB ~
and Vp is the pinchoff voltage of the shunt FETs As > 35 dB

an example, w i t h VC2 = 4 5 V, Vp = 1 8 V, n o
substantial degradation i n insertion loss w i l l be
detected for the new topology until VC1 becomes less
than -2 1 V Figure 3 shows almost no increase i n
insertion loss for the new topology for VC1 = -1 25 V
whereas in the conventional case, insertion loss
increases rapidly
CONCLUSION
By holding VC2 constant a t -4 5 V a n d
modulating VC1 (at -0 5 V) w i t h a 2 V p-p 125 KHz An L-band monolithic FET switch has been
sinusoidal signal there is a significant reduction in A M demonstrated By placing DC blocking capacitors in
modulation of the RF signal for the new topology the source o f t h e shunt FETs the switch became
(Figure 4) In both (a), and (b) the t o p trace is the -0 5 significantly less sensitive t o DC bias r i p p l e t h a n
V a t VC1 modulated w i t h a 125 KHz sinusoid The conventional switch topologies A 1 2 1 VSWR in the
bottom trace (a) shows a 0 5 dB p-p excursion in the off state was achieved by taking advantage o f the on
detected rf The bottom trace (b) shows a 0 1 dB p-p channel resistance of the first shunt FETs The switch
excursion in the detected rf The r f performance o f uses only microamperes of current and is compatible
the switch is summarized in Table 1 with TTL or CMOS logic levels
1114

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00-3

Voltage-Tolerant Monolithic L-Band GaAs SPDT Switch

Texas Instruments Incorporated

Series-shunt FET switches are often used for low

Figure 2. Switch Circuit Schematic.

VC2 - Vref = - I Vp 1 Table 1. Switch Performance.

and Vp is the pinchoff voltage of the shunt FETs As > 35 dB

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