CS 19 Circuits
CS 19 Circuits
S E D G E W I C K / W A Y N E
PA R T I I : A L G O R I T H M S , M A C H I N E S , a n d T H E O R Y
Computer Science
19. Combinational
Computer Circuits
Science An Interdisciplinary Approach
ROBERT SEDGEWICK
K E V I N WAY N E
Section 6.1
http://introcs.cs.princeton.edu
COMPUTER SCIENCE
S E D G E W I C K / W A Y N E
PA R T I I : A L G O R I T H M S , M A C H I N E S , a n d T H E O R Y
CS.19.A.Circuits.Basics
Context
Basic abstractions
• On and off.
• Wire: propagates on/off value.
• Switch: controls propagation of on/off values through wires.
1
power
connection
0
thin wires are OFF
4
Controlled Switch
5
Controlled Switch
data input OFF output OFF data input OFF output OFF
magnet on
magnet pulls
(off ) contact up
connection
contact broken
spring
7
First level of abstraction
8
Switches and wires: a first level of abstraction
technology switch
water transistor
fluid
pressure
“pass transistor” in
integrated circuit
relay electric
(now) potential
atom-thick
transistor
Amusing attempts that do not
scale but prove the point Real-world examples that prove the point
9
Switches and wires: a first level of abstraction
Technology
Deposit materials on substrate.
Key properties
Lines are wires.
Certain crossing lines are controlled switches.
10
Circuit anatomy
11
COMPUTER SCIENCE
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Image sources
http://upload.wikimedia.org/wikipedia/commons/f/f4/1965_c1960s_vacuum_tube%2C_7025A-12AX7A%2C_QC%2C_Philips%2C_Great_Britain.jpg
http://electronics.howstuffworks.com/relay.htm
CS.19.A.Circuits.Basics
COMPUTER SCIENCE
S E D G E W I C K / W A Y N E
PA R T I I : A L G O R I T H M S , M A C H I N E S , a n d T H E O R Y
CS.19.B.Circuits.Algebra
Boolean algebra
George Boole
circuit design 1815−1864
operation Java notation logic notation
(this lecture)
AND x && y x⋀y xy
various notations
OR x || y x⋁y x + y in common use
NOT !x ¬x x'
DeMorgan's Laws
(xy)' = (x' + y' )
Example: (stay tuned for proof )
(x + y)' = x'y'
Relevance to circuits. Basis for next level of abstraction. Copyright 2004, Sidney Harris
http://www.sciencecartoonsplus.com
14
Truth tables
0 1 0 0 0 0 0 0 0 0 1 0 0 0
1 0 0 1 0 0 1 1 0 1 0 0 1 1
NOT 1 0 0 1 0 1 1 0 0 1 0 1
1 1 1 1 1 1 1 1 0 1 1 0
15
Truth table proofs
0 1 0 1 0 1 1 0 1 0 1 1 0 0 1 1 0 0
1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 0 1 0
1 1 1 0 1 1 0 0 0 1 1 1 0 1 1 0 0 0
16
All Boolean functions of two variables
0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
17
Functions of three and more variables
A. 256 (all possibilities for the 8 bits in the truth table column).
0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0
Image sources
http://en.wikipedia.org/wiki/George_Boole#/media/File:George_Boole_color.jpg
CS.19.B.Circuits.Algebra
COMPUTER SCIENCE
S E D G E W I C K / W A Y N E
PA R T I I : A L G O R I T H M S , M A C H I N E S , a n d T H E O R Y
CS.19.C.Circuits.Digital
A basis for digital devices
Claude Shannon
“ Possibly the most important, and also the 1916−2001
most famous, master's thesis of the [20th]
− Howard Gardner
22
A second level of abstraction: logic gates
x x'
x x'
NOT x' 0
1
1
0
x ¬ x' 1 iff x is 0
x y NOR x y x y
0 0 1
(x + y )' (x + y )' 1 iff x and y
NOR (x + y )' 0 1 0 (x + y )' NOR
1 0 0 are both 0
1 1 0
x y OR x y x y
0 0 0
x+y x+y NOR ¬
OR x + y 0 1 1
OR
1 0 1
x + y = ((x + y )')'
1 1 1
x y AND x y x y
0 0 0
¬ ¬
AND xy 0 1 0 AND xy xy NOR
1 0 0
1 1 1 x y = (x ' + y ')'
23
Multiway OR gates
examples
0 1 1 0 0 0
1
Multiway OR gates are oriented vertically
in our circuits. Learn to recognize them! 0 0 0 0 0 1
1
0 0 0 0 0 0
0
24
Multiway generalized AND gates
AND uvwxyz 1 0
0 1 1 0 0 1 0 1 1 0 0 0
u v w x y z
generalized u'vwx'y'z 1 0
u v w x y z 0 0 0 0 0 0 0 1 0 1 0 0
NOR
u'v'w'x'y'z' 1 0
same as (u + v + w + x + y + z)'
Might also call these "generalized NOR gates"; we consistently use AND. 25
Pop quiz on generalized AND gates
x y z
Q. Give the Boolean function computed by these gates.
x y z
Q. Also give the inputs for which the output is 1.
u v w x y z x y z
x y z
u v w x y z
x y z
x y z
x y z
x y z
26
Pop quiz on generalized AND gates
x y z
Q. Give the Boolean function computed by these gates.
x'y'z' 000
x y z
Q. Also give the inputs for which the output is 1.
x'y'z 001
u v w x y z x y z
x'yz' 010
uv'wxy'z 101101 x y z
x'yz 011
u v w x y z
x y z
xy'z 101
x y z
Get the idea? If not, replay this slide, like flash cards.
xyz' 110
x y z
Note. From now on, we will not label these gates.
xyz 111
27
A useful combinational circuit: decoder
110 = 6
Decoder
Example: 3-to-8 decoder
• n input lines (address).
• 2n outputs. 0
• Addressed output is 1.
• All other outputs are 0. 1
3
outputs 0-5
and 7 are 0
4
output 6
6 is 1
28
A useful combinational circuit: decoder
110 = 6
Decoder
Example: 3-to-8 decoder
• n input lines (address).
• 2n outputs.
• Addressed output is 1.
• All other outputs are 0.
Implementation
• Use all 2n generalized AND gates with n inputs. outputs 0-5
and 7 are 0
• Only one of them matches the input address.
• 2n outputs.
• Addressed output has value x. 1
3
outputs 0-4
and 6-7 are 0
4
output 5
5 has value x
30
Another useful combinational circuit: demultiplexer (demux)
101 = 5 x
Demultiplexer
Example: 3-to-8 demux
• n address inputs.
0
• 1 data input with value x.
• 2n outputs. 1
• Addressed output has value x.
• All other outputs are 0. 2
Implementation 3
5 output 5
has value x
31
Decoder/demux
101 = 5 x
Decoder/demux
Example: 3-to-8 decoder/demux
• n address inputs.
• 1 data input with value x. 0
• 2n output pairs.
• Addressed output pair has 1
value (1, x ).
2
• All other outputs are 0.
3
output pairs 0-4
and 6-7 are (0, 0)
4
5 output pair 5
has value (1, x)
32
Decoder/demux
101 = 5 x
Decoder/demux
Example: 3-to-8 decoder/demux
• n address inputs.
• 1 data input with value x.
• 2n output pairs.
• Addressed output pair has
value (1, x ).
• All other outputs are 0.
x y z MAJ MAJ
0 0 0 0
0 0 1 0
term gate
0 1 0 0
0 1 1 1 x'yz
1 0 0 0
1 0 1 1 xy'z
1 1 0 1 xyz'
1 1 1 1 xyz
MAJ MAJ is 1
MAJ = x'yz + xy'z + xyz' + xyz majority circuit example 34
Creating a digital circuit that computes a boolean function: odd parity
x y z ODD ODD
0 0 0 0 term gate
0 0 1 1 x'y'z
0 1 0 1 x'yz'
0 1 1 0
1 0 0 1 xy'z'
1 0 1 0
1 1 0 0
1 1 1 1 xyz
ODD ODD is 0
ODD = x'y'z + x'yz' + xy'z' + xyz example
odd parity circuit 35
Combinational circuit design: Summary
x y z MAJ x y z ODD
Problem: Design a circuit that computes a given boolean function.
0 0 0 0 0 0 0 0
0 0 1 0 0 0 1 1
Ingredients 0 1 0 0 0 1 0 1
• OR gates. 0 1 1 1 0 1 1 0
1 0 0 0 1 0 0 1
• NOT gates. 1 0 1 1 1 0 1 0
• NOR gates. use to make generalized AND gates
1 1 0 1 1 1 0 0
• Wire. 1 1 1 1 1 1 1 1
37
Pop quiz on combinational circuit design
0 0 0 term gate
0 1 1 x'y
1 0 1
xy'
1 1 0
XOR
XOR = x'y + xy' XOR
38
Encapsulation
NOT
DECODER/DEMUX
DEMULTIPLEXER
DECODER
AND
ODD
MAJ
OR
XOR 39
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Image sources
http://en.wikipedia.org/wiki/Claude_Shannon#/media/File:Claude_Elwood_Shannon_(1916-2001).jpg
CS.19.C.Circuits.Digital
COMPUTER SCIENCE
S E D G E W I C K / W A Y N E
PA R T I I : A L G O R I T H M S , M A C H I N E S , a n d T H E O R Y
CS.19.D.Circuits.Adder
Let's make an adder circuit!
Adder
• Compute z = x + y for
n-bit binary integers.
• 2n inputs. 0 0 0 1 0 1 1 23
• n outputs. 0 0 1 1 0 0 0 + 49
carry
out
0 0 1 1 0 1 1 1 0
0 0 0 1 0 1 1 1
+ 0 0 1 1 0 0 0 1
0 1 0 0 1 0 0 0
0 1 0 0 1 0 0 = 72
42
Let's make an adder circuit!
Adder
• Compute z = x + y for
n-bit binary integers.
• 2n inputs. x7 y7 x6 y6 x5 y5 x4 y4 x3 y3 x2 y2 x1 y1 x0 y0
• n outputs.
• Ignore overflow. ADD
carry
out
c8 c7 c6 c5 c4 c3 c2 c1 0
x7 x6 x5 x4 x3 x2 x1 x0
+ y7 y6 y5 y4 y3 y2 y1 y0
z7 z6 z5 z4 z3 z2 z1 z0
z7 z6 z5 z4 z3 z2 z1 z0
43
Let's make an adder circuit!
x7 x6 x5 x4 x3 x2 x1 x0 y7 y6 y5 y4 y3 y2 y1 y0 c4 z7 z6 z5 z4 z3 z2 z1 z0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0
8-bit adder
truth table 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 0 1 1 216 = 65536 rows!
... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 1 1 1 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 1 0 0 0 0 1 0 1 1
1 0 0 0 0 1 0 0 1 1
1 0 1 1 1 1 0 1 0 0
1 1 0 1 1 1 1 0 0 0
1 1 1 1 1 1 1 1 1 1
45
Let's make an adder circuit!
x7 y7 x6 y6 x5 y5 x4 y4 x3 y3 x2 y2 x1 y1 x0 y0
c7 c6 c5 c4 c3 c2 c1 c0
c8 c7 c6 c5 c4 c3 c2 c1 0
x7 x6 x5 x4 x3 x2 x1 x0
+ y7 y6 y5 y4 y3 y2 y1 y0
z7 z6 z5 z4 z3 z2 z1 z0
z7 z6 z5 z4 z3 z2 z1 z0
46
An 8-bit adder circuit
47
Layers of abstraction
MAJ ODD
Vastly simplifies design of complex systems and enables use of new technology at any layer
48
COMPUTER SCIENCE
S E D G E W I C K / W A Y N E
CS.19.D.Circuits.Adder
COMPUTER SCIENCE
S E D G E W I C K / W A Y N E
PA R T I I : A L G O R I T H M S , M A C H I N E S , a n d T H E O R Y
CS.19.E.Circuits.ALU
Next layer of abstraction: modules, busses, and control lines
Conventions input
• Bus inputs are at the top,
busses
51
Arithmetic and logic unit (ALU) module
ADD
control
lines XOR
AND
output
bus
52
Arithmetic and logic unit (ALU) module
Implementation
• One circuit for each function.
• Compute all values in parallel. ADD
✓
output
"Calculator" at the heart of your computer. bus
53
A simple and useful combinational circuit: one-hot multiplexer
2
output
3 is 0
data
4
inputs
data
input 3
is 1
output
output
is 1
54
A simple and useful combinational circuit: one-hot multiplexer
multiway
OR gate
One-hot multiplexer
• m selection lines 0
2
output
Implementation 3 is 0
4
Applications
• Arithmetic-logic unit (previous slide). data
• Main memory (next lecture). input 3
is 1
Important to note. No direct connection from input to output. a virtual selection switch output
is 1
55
Summary: Useful combinational circuit modules
ALU
DECODER/DEMUX
DEMUX
CS.19.D.Circuits.Adder
COMPUTER SCIENCE
S E D G E W I C K / W A Y N E
PA R T I I : A L G O R I T H M S , M A C H I N E S , a n d T H E O R Y
Computer Science
19. Combinational
Computer Circuits
ScienceAn Interdisciplinary Approach
ROBERT SEDGEWICK
K E V I N WAY N E
Section 6.1−2
http://introcs.cs.princeton.edu