A Low-Cost Hardware-In-The-Loop Real Time

Simulation of Control Systems

Diego Rosas Velasquez, Victor Tomanguilla Collazos and Jose Machuca Mines
National University of Engineering, Lima, Peru
[email protected], [email protected] and [email protected]

Abstract—When learning different control related concepts

and methods, simulation is often used as a training tool; but,
it does not have some real time characteristics of implemen-
tation like dealing with coding and PC resources, supervision,
and communications. In some cases, implementation cannot be
carried away, since it involves hardware design and is expensive.
The proposed solution in this paper involves low-cost Hardware-
in-the-Loop for the Real Time Simulation of the plant or process
to be controlled, a PC acting as a controller and a supervisor,
and communications via Ethernet between the elements. It has Fig. 1. Network Topology.
the following advantages: new processes can be controlled by
the PC without having to change the topology of the system;
modifications on the plant or controller only require software
changes; and has the potential of being extensible to a real system
if the simulator software is changed to work as an Ethernet to
analog decoder/transducer.
Index Terms—Control Systems, Real Time, Hardware in the
Loop, FPGA, Simulation.

I. I NTRODUCTION
Our proposal (Fig. 1) was created with the purpose of
exploring some characteristics of control-supervision via PC:
resource sharing between both roles, constraints on sampling Fig. 2. Simulated System.
time, delay on communications, and coding for implementa-
tion; while avoiding hardware related complexities.
This platform is divided in the following modules: Where:
   
• Supervisor: Module in which the variables related to the ẋ1 x2
dynamics and the controller are displayed. ẋ2  = − M sin(x1 ) − B x2 + Km x3  (2)
J J J
Kω Rm KC
• Controller: Module in which the communications with the ẋ3 − nL m
x 2 − Lm x 3 + Lm u(t)
Dynamic Simulator are done, and control algorithms are
executed. This role, and the Supervisor one, are carried The numerical values of the coefficients are the following:
by a PC. M B Km
• Dynamic Simulator: Module in which the Real Time
= 1.4149030; = 0.587740053; = 0.94903793
J J J
Simulation of the Plant/Process behavior is executed. This
Kω Rm KC
role is fulfilled by an ARM ($55), and a SoC-FPGA = 11.2; = 128.0; = 120.0
($100). nLm Lm Lm
• Communications: The protocol used is TCP/IP over an The implemented controllers using this platform are: a lead
Ethernet layer. With this, multiple simulators can be con- compensator, a PID controller, and a pole placement by
trolled with a PC, without need for additional hardware. state feedback controller, all of them applied to a feedback
The simulated system corresponds to a nonlinear control linearized plant; and, a sliding mode controller (SMC) that
system for the angular position of a rod, mounted on a system exploits the structure of the normal form derived by feedback
of gears and shafts, rotated by the action of a DC motor (Fig. linearization.
2).
II. S IMULATION OF P LANT /P ROCESS DYNAMICS
The equations describing the plant dynamics can be reduced
to the following ones: Real Time Simulation needs a platform with dynamics as

T
T close as possible to the simulated model or system. This
x = x1 x2 x3 = θ ω im (1) platform can be analog-based, digital-based or mixed. The
978-1-5090-6363-5/17/$31.00
c 2017 IEEE proposed system on this paper involves only digital platforms.
 Fig. 4. Control-Supervision GUIs acting over two simulators (FPGA at left,
Fig. 3. FPGA Design. ARM at right). 1Hz plotting frequency.

The state evolution problem is solved using 4th Order Runge- to the parallel processing on FPGA and the independence
Kutta Method on the dynamics differential equations. between the Dynamic Simulator and communications. Also,
Two platforms were used to implement the Dynamic Simu- changes on the plant only involve changes on the Black Box.
lator: an FPGA was chosen to explore the performance of a The main constraints on the step size involve the following
highly customizable processor, and an ARM to explore the characteristics of the simulation problem:
performance of a programmer-friendly processor. Their step
• Calculation Complexity: Non-parallelizable calculations
sizes for the state evolution problem were 10us and 1ms,
constrain the minimum hardware-related step size. This
respectively.
kind of calculations come from sequential behavior and
A. ARM (Beaglebone Black Rev C) from limits on logic usage (only 40% was used on this
project, so, this is not a common issue).
On this platform, the implementation consists on making • Underflow and Slow Dynamics: Slow dynamics or small
software that fulfills the following functions: step sizes produce a small state displacement, which can
• Setup the TCP/IP Socket and the Initial States. cause underflow and drive off the dynamics from the
• Check if any incoming connections are waiting. If they desired system.
are, send the states and wait for the control action.
• Make the states of the Dynamic Simulator evolve. III. PC BASED C ONTROL AND S UPERVISION
The main constraint on the step size of this Dynamic Simulator A. PC Based Control-Supervision
is the time that the processor takes to verify if the TCP/IP
Socket has any incoming connections. Also, when TCP/IP The controller requirements are related to sampling time:
requests are attended, additional delay is introduced in the having one as small as possible (analog design), and also as
program, and the step size has to be changed during those stable as possible (digital design). The supervisor must show
cycles. the usual waveforms (states, tracking error and control action)
and track the sampling time characteristics.
B. SoC FPGA (DE0-NANO-SoC Module) The Controller-Supervisor program (Fig. 4) is based on
Python, with the GUI framework Qt GraphicView, over a
On this platform, the implementation consists on using the
Linux OS (Fedora 24). This GUI has the following features:
FPGA to create a processor which solves the dynamics of the
plant/process, while the HPS (ARM) of the SoC attends the • A main plot (upper) showing the reference signal and

Ethernet requests (for design simplicity, since that could be angular position; and a secondary one in which tracking
done on the FPGA). The AXI Bridge [1] connects the FPGA error, control action, states, or a loop time histogram can
fabric to the HPS of the SoC. The FPGA part of the design be plotted.
is shown on Figure 3. • Selection of control method, reference signal frequency,

The HPS-FPGA Interface executes instructions coming from plotting frequency, and the secondary plot signal.
the HPS (reset, measures, and control action update). The • A text box in which loop time statistics are printed.

Black Box module takes as input the current states and the 1) Loop Time Statistical Analysis: The analysis involve
control action, and calculates the evolved states after a defined recursive calculations of the mean and variance [2], maxi-
time step. This architecture is designed to simulate third order mum/minimum values, and a histogram of the loop time. Since
systems, but it can be extended to higher order ones by adding the histogram involves only discrete values on the horizontal
registers to store the additional states. axis, while the loop time has a continuous range; a convex
This implementation has the advantage of having a much sum between two neighbors was used to determine the how
smaller and stable time step on the Dynamic Simulator, due the histogram is updated with the new loop time measures.
 2) Decimation: Continuous update of the plots slow down
the system, and this speed is not needed due to the limits on
visual perception; so, the graphs are updated with a reduced
frequency with respect to the sampling frequency.
B. Design and Implementation of Controllers
1) Feedback Linearization: It can be shown that the simu-
lated plant is feedback linearizable (for theory, see [3]). The
PID was designed by computerized optimization; while the (a) (b)
compensator and the state feedback were designed by defining
poles explicitly. To avoid derivative kick, the derivative term
of the PID was filtered by a first order LPF.
The normal form of the simulated plant can be obtained by
the transformation:
   
z1 x1
z2  =  x2  (3)
M B Km
z3 − J sin(x1 ) − J x2 + J x3
And its dynamics are expressed by the following equation: (c) (d)
    Fig. 5. Histograms vs. plotting frequency: a) 0.1Hz, b) 1Hz, c) 10Hz, d) 1Hz
ż1 z2 Double Simulation.
ż2  =  z3  (4)
ż3 −a1 z3 − a2 z2 − β(z) + αu(t)
IV. S YSTEM T ESTS
Where:
Tests on how the sampling period and the controller effi-
B Rm Km Kω + nBRm ciency change with different design parameters are essential
a1 = + ; a2 =
J Lm nJLm to understand the system behavior. The variable parameters on
Km KC M M Rm the test were the plotting frequency, the Dynamic Simulator
α= ; β(z) = cos(z1 )z2 + sin(z1 ) platform, and the execution of control-supervision programs
JLm J JLm
for both Dynamic Simulators. The default values on the test
The transformation between the linear control v(t) and the are:
nonlinear controller u(t) can be expressed by the equation: The default values on the test are:
1 • Sampling period: 5 ms
u(t) = [v(t) + β(z)] (5)
α • Reference signal: 0.1Hz, 2 rad

The transfer function of the PID and Lead Compensator are: • Plotting frequency: 1Hz

544.293 1.00106s A. Sampling Period

GP ID (s) = + 1.47631 + (6)
s 0.0678085s + 1 Figures 5(a) to 5(c) show the effect of increasing plotting
4214.75s + 3630.06 frequency: the additional delay produced by cycles in which
GCompensator (s) = (7) plotting is done explains the accumulation of values around
s + 11.2397
14ms. Figures 5(b) and 5(d) show the differences between
As for the Pole Relocation by State Feedback controller, the
controlling one and two simulators: the conflict in Ethernet
control action can be expressed as:
and processor resource sharing explain the small decaying
v(t) = −124.219(z1 − r) + 24.2974z2 + 115.088z3 (8) deviation around the sampling period, while plotting and
interaction between both programs explain the accumulation
2) Sliding Mode Control (SMC): Using the normal form of values around 19ms.
previously obtained, the following controller was designed:
  B. Controller Performance
S
u(t) = ηSat For the lead compensator (LC) and the state feedback
φ (9) controller (SF), the error signal form is a sinusoid produced by
1 ... ¨ 2˙

+ r − 2λze − λ ze + β(z) + a1 z3 + a2 z2 tracking delay, since the magnitude of the sinusoid was tracked
α correctly. Small deformations on the error signal were formed
Where: when the plotting frequency was increased or an ARM was
ze(t) = z1 (t) − r(t); S = z¨e + 2λze˙ + λ2 ze used instead of an FPGA. The differences between computer
and real time simulation were minimal.
The value of the parameters φ, λ, η are 4, 5 and 10, respec- For the PID controller, the error signal form is sinusoid-like
tively. and a product of bad tracking, since no phase delay was
 During long simulation times, small oscillations on the track-
ing error were generated. For the ARM, those disturbances
had unstable behavior. The evolution of those disturbances to
unstability was very dependent on plotting frequency: around
20 minutes for 1Hz, but less than 10 minutes for 10Hz. To
erase this behavior, the control had to be turned off during a
(a) small time to stop feeding the oscillation.
V. C ONCLUSIONS AND F UTURE W ORK
A. Conclusions
The focus of our work was educational, and was successful
to show some effects of resource sharing between controller
and supervisor, and some random effects of communications
in the system. Different applications of Real Time Simulation
(b) have been mentioned in previous works [4]; this system can
be used for some of them if the ARM is used. The source of
the unbounded disturbance when using the FPGA is unknown;
but, from its behavior with respect to plotting and the platform,
increasing the step size on the ODE solver and making the
system more deterministic should reduce or erase it. To do
this last, some changes are needed: communications [5], RTOS
on simulators [6], and separating the supervisor (PC) and the
(c)
controller (another platform, e.g. ARM).
Fig. 6. Tracking Error vs. Plot Frequencies (FPGA based Simulator, SMC):
(a) 0.1Hz, (b) 1Hz, (c) 10Hz. B. Future Work
Previous works [7] have shown that if real data is available,
TABLE I a model could be identified by training the Dynamic Simulator
M AXIMUM T RACKING E RROR V S P LATFORM A ND P LOTTING
F REQUENCY
with that data. This emulator can be used on fast design
of controllers when experiments with the plant/process are
SS LC PID SMC expensive or unavailable. Our future work involves solving
Simulation 0.65 0.35 0.1 0.03 the problems found on our proposed system, and using it for
FPGA 0.6 0.4 0.1 0.02 fast design of controllers.
Single, 1Hz
ARM 0.6 0.4 0.12 0.03
ACKNOWLEDGMENT
FPGA 0.6 0.4 0.1 0.02
Single, 0.1Hz
ARM 0.6 0.4 0.1 0.03 This work was funded by the Research Institute of the
FPGA 0.6 0.35 0.14 0.06 School of Electrical and Electronic Engineering (IIFIEE -
Single, 10Hz
ARM 0.6 0.35 0.12 0.05 UNI). The authors gratefully acknowledge the support of
FPGA 0.65 0.4 0.1 0.02 National University of Engineering, Lima, Peru, especially
Double, 1Hz
ARM 0.65 0.4 0.12 0.04 to our school FIEE-UNI. Also, the authors give their thanks
to Edson Ticona Zegarra, for his valuable advice during the
edition of this paper.
present. Small deformations were formed when plotting fre- R EFERENCES
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