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VHDL Code:: Structural Modeling

The document provides VHDL code for implementing a 4x1 multiplexer (MUX) using different modeling approaches - structural, dataflow and behavioral. The structural model uses AND3, OR4 and NOT1 components. The dataflow model assigns signals for the logic functions. The behavioral models use if-else and case statements to assign the output based on the input select lines and vector. Waveform diagrams are also provided for each implementation.

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Juhi Choudhary
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727 views6 pages

VHDL Code:: Structural Modeling

The document provides VHDL code for implementing a 4x1 multiplexer (MUX) using different modeling approaches - structural, dataflow and behavioral. The structural model uses AND3, OR4 and NOT1 components. The dataflow model assigns signals for the logic functions. The behavioral models use if-else and case statements to assign the output based on the input select lines and vector. Waveform diagrams are also provided for each implementation.

Uploaded by

Juhi Choudhary
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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Que:1 Write the VHDL Code for 4x1 MUX .

Answer:

VHDL CODE:

Structural Modeling:

library ieee;
use ieee.std_logic_1164.all;

entity mux_4X1 is
port(c:in std_logic_vector(3 downto 0);
a,b:in std_logic;
f:out std_logic);
end mux_4X1;

architecture SM_mux_4X1 of mux_4X1 is


component and3
port(x1,x2,x3:in std_logic;
o1:out std_logic);
end component;

component or4
port(y1,y2,y3,y4:in std_logic;
o2: out std_logic);
end component;

component not1
port(z1:in std_logic;
o3:out std_logic);
end component;
signal t1,t2:std_logic;
signal s1,s2,s3,s4:std_logic;

begin
U1:and3 port map(t1,t2,c(0),s1);
U2:and3 port map(t1,b,c(1),s2);
U3:and3 port map(a,t2,c(2),s3);
U4:and3 port map(a,b,c(3),s4);
U5:not1 port map(a,t1);
U6:not1 port map(b,t2);
U7:or4 port map(s1,s2,s3,s4,f);
end ;

-------------------------------
--and3
-------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity and3 is
port(x1,x2,x3:in std_logic;
o1:out std_logic);
end and3;
architecture DF_and3 of and3 is
begin
o1<=((x1 and x2) and x3);
end;
--------------------------------
--OR4
--------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity or4 is
port(y1,y2,y3,y4:in std_logic;
o2: out std_logic);
end or4;
architecture DF_or4 of or4 is
begin
o2<= (((y1 or y2)or y3) or y4);
end;

--------------------------------
--NOT1
--------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity not1 is
port(z1:in std_logic;
o3:out std_logic);
end not1;

architecture DF_not1 of not1 is


begin
o3<= (not z1);
end;

WAVE FORM:

DATAFLOW :

library ieee;
use ieee.std_logic_1164.all;
entity MUX4X1 is
port(c:in std_logic_vector(3 downto 0);
a,b:in std_logic;
f:out std_logic);
end MUX4X1;

architecture DM_MUX4X1 of MUX4X1 is


signal t1,t2: std_logic;
signal s1,s2,s3,s4: std_logic;
begin
t1<=(not a);
t2<=(not b);
s1<=((t1 and t2) and c(0));
s2<=((t1 and b) and c(1));
s3<=((a and t2) and c(2));
s4<=((a and b) and c(3));
f<=(((s1 or s2) or s3) or s4);
end;

WAVE FORM:

BEHAVIORAL:

(IF THEN ELSE)

library ieee;
use ieee.std_logic_1164.all;

entity BH_MUX4X1 is
port(c:in std_logic_vector(3 downto 0);
a,b:in std_logic;
f:out std_logic);
end BH_MUX4X1;
architecture BH_MUX4X1 of BH_MUX4X1 is
begin
process(a,b,c)
begin
if a='0' and b='0' then
f<=c(0);
elsif a='0' and b='1' then
f<=c(1);
elsif a='1' and b='0' then
f<=c(2);
elsif a='1' and b='1' then
f<=c(3);
end if;
end process;
end;

WAVEFORM:

(CASE)

library ieee;
use ieee.std_logic_1164.all;

entity BH_MUX4X1_case is
port(c:in std_logic_vector(3 downto 0);
a,b:in std_logic;
f:out std_logic);
end BH_MUX4X1_case;

architecture BH_MUX4X1_case of BH_MUX4X1_case is


begin
process( a,b)
variable w:std_logic_vector(1 downto 0);
begin
w:=a & b;
case w is
when "00" => f<=c(0);
when "01" => f<=c(1);
when "10" => f<=c(2);
when "11" => f<=c(3);
when others => f<='0';
end case;
end process;
end;

WAVEFORM:

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