8. Programmable Logic Devices 8.1.

Read Only Memories

o Objectives o A Read Only Memory (ROM) is a matrix of data that is
accessed one row at a time.
n This chapter deals with devices that can be programmed to
realize a specified logical functions. It has the following A0
A1
ROM

objectives: Ak-1
u Introduce ROMs and show how they can be used as a universal
logic device. Dn-1 D1 D0
u Show how simple programmable logic devices can be derived from
ROMs. n The A inputs are address lines used to select one row (called a word) of
the matrix for access. If A=i, then row i is selected and its data appears
u Give an overview of Complex Programmable Logic Devices on the output terminals D. In this case we say that the contents of row i
(CPLDs) and Field Programmable Gate Arrays (FPGAs) are read from the memory.
n Reading Assignment n If there are k address lines, then there are 2 k words in the ROM and the
number of bits per word is called the word size
u Chapter 3, Sections 3.6, 3.7 and 3.10 and Appendix E in Brown
and Vranesic. n The data values of the words are called the contents of the memory and
are said to be stored in the memory.
n The term read only refers to the property that once data is stored in a
ROM, either it can not be changed, or it is not changed very often.

Elec 326 8.1 Programmable Logic Devices Elec 326 8.2 Programmable Logic Devices

o Internally a ROM contains a o The type of ROM is determined by the way the
decoder and a storage array switches are set or reset (i.e., programmed).
DECODER m0
as shown to the right. A0 m1 0 1 1
A1 1 1 0 n Mask programmed ROMs: The switch is realized at the time the
n When the address is i, the i-th m2k-1 ROM is manufactured. Either a connection is made by putting in
Ak-1
output of the decoder mi is 0 0 1
a wire, or the connection is left open by not putting in a wire.
activated selecting row i of the
data array. Dn-1 D1D0 n Field programmable ROMs (PROMs): The switch is realized by
a fuse. When the ROM is manufactured all switches are closed
since all the fuses are intact. To open a switch the fuse is blown
o Functionally the data array m0
0
by sending a larger than usual current through it. Once a fuse is
can be viewed as a blown, it can not be reinstalled.
programmable OR array m1
n Erasable ROMs (EPROMs): The switch is realized by a special
n Each column acts as a stack of kind of fuse that can be restored to its usual closed state, usually
OR gates as shown to the right. by the insertion of extra energy (e.g., shining ultraviolet light on
If a 0 is stored in a row, the the fuse. All fuses are reset when this is done.
switch is open and if a 1 is m2k-1 n Electrically Programmable ROMs (EPROMs): The fuses are
stored, the switch is closed. reset by the application of larger than usual currents. Sometimes
subsections of the ROM can be reset without resetting all fuses.

Elec 326 8.3 Programmable Logic Devices Elec 326 8.4 Programmable Logic Devices

1
 8.2. Programmable Logic Arrays
o Realizing logical functions with ROMs
n ROMs with k address lines and n data terminals can be o Programmable Logic Arrays (PLAs) have the same
used to realize any n logical functions of k variables. programmable OR array as a ROM, but also have a
u Simply store the truth table for each function in a column of the
ROM data array programmable AND array instead of the decoder.
A2 A1 A0 D3 D2 D1 D0 n Where the decoder produces all minterms of k variables,
0
0
0
0
0
1
1
1
1
1
1
0
0
1 the programmable AND array can be used to produce
0
0
1
1
0
1
1
0
0
1
1
1
1
1 arbitrary product terms, not just minterms.
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0 p0
1 1 1 1 0 0 0
p1
AND OR
n The most serious disadvantage of using large ROMs to ARRAY
pm
ARRAY
realize logical functions is the ROMs are much slower than
gate realizations of the functions. Yn-1 Y1 Y0
n If some form of programmable ROM is used, we have the
possibility of reconfigurable logic. That is, the same n The number of possible product terms m is much less than
hardware being reprogrammed to realize different logic at the number of possible minterms 2k, so some functions may
different times. not be realizable.

Elec 326 8.5 Programmable Logic Devices Elec 326 8.6 Programmable Logic Devices

n A typical row of the programmable AND array has the

following structure: n Example:
Xk X1 X0
P1 = A' • C' X= P3 = A • B'
1 pi P2 = A' • C Y = P2 + P4 = A' • C + A • B • C
P3 = A • B' Z = P1 + P3 = A' • C' + A • B'
P4 = A • B • C
o PLA Notation

n A dot is placed at an intersection if the variable is to be

included in the product term or to sum term.
Elec 326 8.7 Programmable Logic Devices Elec 326 8.8 Programmable Logic Devices

2
 9.3. Programmable Array Logic (PAL) 8.5. Complex Programmable Logic Devices (CPLD)
o While the ROM has a fixed AND array and a programmable o How could we make PLD’s more complex in order to
OR array, the PAL has a programmable AND array and a
fixed OR array. take advantage of the rapidly improving
n The main advantage of the PAL over the PLA and the ROM is that it is semiconductor technology?
faster and easier to fabricate. n Put extra features in the PAL (e.g., configurable outputs)
u The options here are limited and have mostly been used to develop
GALs from PALs
n Increase the size of a conventional PAL or GAL
n Put several PAL’s or GAL on the same chip along with
some way to interconnect them inside the chip.
o Increasing the size of a conventional PAL or GAL is
not an effective way to increase complexity
n It significantly slows the chip down due to long rows of
AND gates.
n It wastes space on the chip

Elec 326 8.9 Programmable Logic Devices Elec 326 8.10 Programmable Logic Devices

o The third option of putting several PALs on one chip n Structure of the PAL-like blocks
works best. These chips are called Complex PLDs or
CPLDs.

Elec 326 8.11 Programmable Logic Devices Elec 326 8.12 Programmable Logic Devices

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 8.6. Field-Programmable Gate Arrays (FPGA) o The Structure of Logic Blocks
n The circuits used to implement combinational logic in logic
o Differences between FPGAs and CPLDs: blocks are called lookup table (LUT)
n CPLD’s PLDs replaced with a much smaller logic block. n LUT in the Xilinx XC4000
n FPGAs use a more flexible and faster interconnection u Use three ROMs to realize the LUTs and generate the following
structure than the CPLDs. classes of logical funtctions:
u The logic blocks are embedded in a mesh or wires that have l Any two different functions of 4 variables each plus any other function of 3
programmable interconnect points that can be used to connect two variables.
wires together or a wire to a logic block. l Any function of 5 variables. How?
l Any function of 4 variables, plus some (but not all) functions of 6 variables
l Some (but not all) functions of up to 9 variables

l The boxes G and H are ROMs with 16 1-bit words and H is a ROM with 8 1-
bit words.

Elec 326 8.13 Programmable Logic Devices Elec 326 8.14 Programmable Logic Devices

n Example of programmed FPGA

o LUTs in Altera FPGAs

Elec 326 8.15 Programmable Logic Devices Elec 326 8.16 Programmable Logic Devices

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 8.7. Tips & Tricks
o Use external inverters instead of two-pass PALs
when speed is critical. Better yet, use GALs.
8.8. Pitfalls
o Using SSI and MSI chips when PLDs would reduce
the chip count.

8.9. Review Questions

o The differences between ROMs, PLAs and PALs.
o The structure of CPLDs and FPGAs

Elec 326 8.17 Programmable Logic Devices