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Mips Instructions

The document discusses branch instructions in computer architecture. It describes conditional branches that transfer program control based on a condition, and unconditional branches that transfer control without checking conditions. Specific branch instructions covered include beq (branch equal), bne (branch not equal), and other branches like bgtz (branch greater than zero). The target of branches is a label that will be replaced with an address. Converting conditions from high-level languages to assembly instructions using these branch instructions is also discussed.

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90 views30 pages

Mips Instructions

The document discusses branch instructions in computer architecture. It describes conditional branches that transfer program control based on a condition, and unconditional branches that transfer control without checking conditions. Specific branch instructions covered include beq (branch equal), bne (branch not equal), and other branches like bgtz (branch greater than zero). The target of branches is a label that will be replaced with an address. Converting conditions from high-level languages to assembly instructions using these branch instructions is also discussed.

Uploaded by

Mohamaad Sihatth
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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IT403

Introduction to computer
architecture
Branch instructios
● Conditional branches
– Execute if some condition holds
– Transfer the program control to a different point
based on a condition
● Unconditional branch
– Take the branch without checking any condtion
– Transfer the program flow to a different point
– Also called as jumps
Branch equal
● Syntax: beq r1, r2, <target>
● Sematics:
– Transfer the program control to the given target address of r1
== r2
– Target is a label in the code (which will later be replaced with
an address)
● Examples
beq r1, r2, if
…..
if:
Branch NOT equal
● Syntax: bne r1, r2, <target>
● Sematics:
– Transfer the program control to the given target address of r1
!= r2
– Target is a label in the code (which will later be replaced with
an address)
● Examples
bne r1, r2, if
…..
if:
Other banch instructions
● branch greater than zero
– Syntax: bgtz r1, <target>
– Sematics: take the branch if r1 > 0
● Branch greater than or equal to zero
– Syntax: bgez r1, <target>
– Sematics: take the branch if r1 >= 0
Other banch instructions ...
● branch less than zero
– Syntax: bltz r1, <target>
– Sematics: take the branch if r1 < 0
● Branch less than or equal to zero
– Syntax: blez r1, <target>
– Sematics: take the branch if r1 <= 0
Converting to instructions
● Some of the conditions provided by the higher
level language are much more expressive than
this
● Compiler will convert then to suitable
operations and use these hardware instructions
to implement them.
● Example: if(x + 1 > y)
Thinking time …
● How to convert the following C-code into
assembly
if(x+1 < y && y > 10)
z ++;
else
z –;
Note on the target
● The taget given in the assembly code in encoded using
16bits
– The address field in the j-type instructions
● There is a limit to the target address
– It should be within the 216 byte limit
● If the actual function is outside of this limit another
instruction will be placed there to make the real branch.
● The label will be replaced with the actual address at the link
time
– Assembel → link → final executable
Address encoding
● Size aligned address:
– Almost all computers requires you to align data to its size
– That is, if the data item is 4bytes its address should be divisible
by 4 (or 2 LSBs should be zero)
● Since all instructions are 32bit and they are stored aligned
to the size the last two bits of any instruction should be
zero
– So, we do not include the last 2bits in the encoding (or divide the
address by 4)
– When taking the branch, recompute the address by adding
2more bits (or multiply with 4)
Jump instruction
● In addition to conditional branches MIPS also provide
jump which transfer the control always
● Two type of jump
– Syntax: j <taget address>
– Sematics: jump to the given address. Address has a limited
range (you cannot go to any place in the address space)

– Synaxt: jr r1
– Sematics: jump to the address given in the register. No limit on
the range. However, need to use an additional register for this.
Thinking time …
● Are these enogh?
– Can we implement all branches provided in a
typical programming language

● How about function calls?


What is special about function calls?
● Function calls are esentially transfer of control (with few
other things)
– Go and execute the called function
● Additional feature
1)Need to pass arguments
2)Need to get a result back
3)Need to come back to where we were
● The 1,2 above are handled by the calling convention (which
I will not cover this completely in this course)
● Need some hardware support for the 3 point above
The jump and link instruction
● The jump and link instruction provide the means for function
calls
● It is essentialy a unconditional branch, but the returnn address
will be saved in a given register
● Synax: jal <function>
● Sematics: jump to the function, load PC+4 to r31
● Idea: so I know where to get back
● Once the function finishes execution it can jump register to r31
● jalr jump and link register is also available
A typical function
foo:
save callee saved register (ones you would use)
do the operation
restore the callee saved register (ones you messed up fix
them with original values)
jr r31
● Notes:
– Registers will be saved on the stack
– Not all registers need to be saved
Calling convention
● It is a convention developed by compiler
designers for a given programming language
and architecture, which says
– How to pass the arguments
– How to get the results back
– What registers needs to be preserved
– What registers can be trashed
MIPS calling convention for C
● R0 → always contains 0
● R1 → reserved for the assemble (not used by C code) (called at)
● R2 – R3 → used to return values from a subrotine. If return value
takes one register only R2 is used (V0 – V1)
● R4 – R7 → used to pass arguments to function (A0 – A4)
● R8 – R15, R24, R25 → no need to preserve
● R16 – R23, R28 – R30→need to be preserved (R29 = Stack
Pointer)
● R31 → contains the return address
● R27 – R18 → reserved for the operating system
Excercise
● Conver the following C-code to assembly
int main() int main()
{ {
int a = add(1, 2); int a[10];
return 0; addone(a, 10);
} return 0;
}
int add(int i, int j)
{
return i+j;
void addone(int *a, int limit)
} {
for(int i=0; i<limit; i++)
a[i] += 1;
}
Load instructions
● Loading a word is simple
– What you load from the memory will fit into the register
– Example: on a 32bit maching the registers will be 32bits
and lw/sw will take 32bits from/to memory
● Some data types takes less than 32 bits
– Example: from c: shorts, bytes …
● How to deal with these ones
– Issue: read 16bits from memory and put to a 32bit
register
Signed and unsigned loads
● MIPS provides two types of loads (applicable
when loading sub-word)
● Signed load:
– Basic idea: reapeat the signed bit to fill the MSBs
as requred
– Example: when loading two bytes (16bits) from
memory to a four byte (32bit) register repeat the
MSB from what is loaded to fill the additional 16bits
Effect of signed load
● Find the 8bit 2's complement of -9
● Do a signed load of this number to a 16bit
register
● What is the 16bit value (using 16bit 2's
complement)?
When to use what
● If your data type uses 2's complement then
loads should be signed
– Example: from C, short, byte …
● If your data type is not 2's complement then
loads should be unsigned
– Example: from unsigned short, …
Unsigned loads
● Unsigned loads will fill the additional bits with 0
● Example: if you load 16bits from memory to a
32bit register
– Bottom 16bits (LSB) will be filled with what is
loaded from memory
– Top 16bits (MSB) will be filled with zeros
– So that the unsigned value will be the same
Loading sub-words
● Load half signed → lh
● Load half unsigned → lhu
● Load byte signed → lb
● Load byte unsigned → lbu
● Exercise: Convert the following C-code to
assembly
short a[10];
for(int i=0; i<10; i++) a[i] = a[i] + 10;
Loading immediate values
● MIPS provide instructions to load immediate values
● The rules on signed and unsigned loads will be
applicable here as well
● Value is limited by the 16bits in the I-type
instructions
● Instruction
– li → load the immediate value, signed
– liu → load immediate unsigned
Storing subwords
● Storing subwords is simpler that loading them
● You simply select a suitable number of LSBs
– Exampe: sh (store half) will store the 16LSB bits
– Top 16bits will be lost
Operations with immediate values
● MIPS ISA provide operations with immediate values
– That is values in the instruction itself
● addi → addi r1, r2, 8 (add 8 to r2 and store in r1)
● addiu → addiu r1, r2, 8 (do an unsigned addition of
r2 and 8 and store in r1)
● Other instructions: ori, andi, xori
– These do not have the u variant (they are anyway
bitwise operations)
Shift instructions
● MIPS provides instructions to shift values
● Synatax: sll r1, r1, 3 (shift logically left)
● Semantics: shitf the value in r1 by 3 possitions to the left
and store in r1
● Can be used for multipication by powers of two

● Syntax: sllv r1, r1, r2 (shift logically left value)


● Smantics: shift the value in r1 by given value in r2 and
store in r1
Other instructions
● We will not discuss about them
● They are there to handle exceptions
– Exception → something that should not have happen,
something unexpected by the code
– Example: a packet can through the network, someone
pulled put the USB stick ….
● ISA provides instructions to handling these conditions
● They are, in most cases privilleged → that is to say
not all applications can execute them.
Summary
● There are lots of instructions
– Would vary depending on the architecture
– No one will be able to remember all of them
● However the concepts would be the same
– Examlpe: jal in MIPS vs call in x86
● Use the given MIPS instruction sheet when you
need to refer to any instruction

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