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The Fan-Out Technology On The Advanced Packaging

The document discusses fan-out technology and advanced packaging. It defines fan-out as the maximum number of digital inputs that the output of a logic gate can feed. TTL gates typically have a fan-out of 2-10, while CMOS gates can be up to 50. Higher fan-out reduces the need for additional gates but increases switching delay. Fan-out wafer-level packaging is discussed as enabling more interconnects at smaller wafer sizes. References analyze fan-out packaging's ability to integrate dies vertically/horizontally, reduce warpage, and enable multi-chip modules.

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30 views2 pages

The Fan-Out Technology On The Advanced Packaging

The document discusses fan-out technology and advanced packaging. It defines fan-out as the maximum number of digital inputs that the output of a logic gate can feed. TTL gates typically have a fan-out of 2-10, while CMOS gates can be up to 50. Higher fan-out reduces the need for additional gates but increases switching delay. Fan-out wafer-level packaging is discussed as enabling more interconnects at smaller wafer sizes. References analyze fan-out packaging's ability to integrate dies vertically/horizontally, reduce warpage, and enable multi-chip modules.

Uploaded by

peterchondro
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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1st Report of MOS Devices Couse (ET6306701 – Spring 106) – Professor Pao-Hung Lin

NAME: PETER CHONDRO STUDENT ID: D10502803 CREATED ON: 03.22.2017

The Fan-Out Technology on the Advanced Packaging


Introduction
In the digital circuit design, various parameters and conditions need to be taken into the
account of the circuit designer. For instance, in an ideal design, a logic gate is theoretically required
to have infinite input impedance (thus receiving input signal with extremely low current demand)
and zero output impedance (thus transmitting output signal with extremely low current loss).
Nevertheless, the aforementioned conditions are practically impossible to realize, which results in
a certain limitation for an output of the logic gate to be connected with the logic gates properly
without the possibility of voltage drop due to insufficient current outcome. Based on this type of
limitation, the fan-out character is observed as one of the essential parameter to design the digital
circuit design. The fan-out is defined as the maximum number of digital inputs that the output of
a single logic gate can feed. The fan-out rating depends mainly on the fundamental of the design
of the corresponding logic gate. For the transistor-transistor logic (TTL) based logic gates, the fan-
out rating is specified from 2-10 connections depending on exact design, which is stated in the
datasheet; while for the complementary metal oxide semiconductor (CMOS) based logic gates, the
fan-out rating is specified as significantly higher number of possible connections per logic gate
compared to the TTL logic gates. For instance, most CMOS logic gates have fan-out rating at up
to 50 possible connections, or 5 times higher than what the TTL-based logic gates can deliver.
Ideally, the high rating of fan-out is more preferable option to minimize the requirement for
additional logic gates or buffers, thus reducing the packaging dimensions. However, since each
logic gate yields an input impedance that incorporates a stray capacitance; therefore, with higher
rating of fan-out, higher capacitance is expected and this shall result in the increased switching
delay. This is the reason why most CMOS logic gates have slower switching speed than the TTL.
References
In the application stage, the fan-out technology is a powerful technique that helps to
significantly manage the digital circuit design; thus fabricating the concept of advanced packaging,
including the fan-out wafer-level-packaging (FO-WLP). The FO-WLP technology has been
widely observed in different studies [1], [2], [3] with different perspective of advantages that
mainly focuses on improving the form factor of the digital circuit and the packaging; therefore, the
fabrication cost can be further conserved. The development of FO-WLP contributes in realizing as
many number of interconnects at any shrink stage of the wafer node technology. The
aforementioned outline of research is observed and characterized in [1] by integrating multiple
dies both vertically and horizontally (high density 3D design) in single package without using any
substrate that results in a miniaturized and fine pitch advanced silicon packaging solution. Chan et
al. introduces another challenge in reducing the wafer warpage as a measure to address the
subsequent wafer process by identifying different parameters through the finite element analysis
and therefore optimizing the ratio between the die and the compound [2]. To improve the
innovation in [2], Jin et al. developed a next generation of the advanced packaging that enables
RDL scaling, overcomes the die shift, die protrusion, and warpage challenges of the FO-WLP in
[2] as well as to extend the FO-WLP technology for multi-chip package and high I/O count
package applications [3]. With the gradual development of the FO-WLP technology, advanced
packaging would be able to achieve a design that minimizes the trade-off between the package
dimensions and the electrical to thermal performances.

1
1st Report of MOS Devices Couse (ET6306701 – Spring 106) – Professor Pao-Hung Lin
NAME: PETER CHONDRO STUDENT ID: D10502803 CREATED ON: 03.22.2017

Commentary
As it has been stated in the Introduction, the fan-out rating corresponds to the number of
inputs that are connected to the output of the corresponding logic gate and since the fabrication of
logic gates may not be idealized to zero input impedance and infinite output impedance, the
propagation delay will be introduced in the system. The propagation delay is contributed from the
stray capacitance that is apparent in both input and output of the logic gates.

Figure 1. An illustration

Suppose
d
List of References
[1] Y.-G. Jin, J. Tysseyre, X. Baraton, S.W. Yoon, Y.-J. Lin, and P.C. Marimuthu, “Development
of advanced fan-out wafer level package (embedded wafer level BGA) packaging,”
International Conference on Electronic Packaging Technology and High Density Packaging,
Guilin, 2012, pp. 151-156.
[2] V.S. Rao, C.T. Chon, D. Ho, D.M. Zhi, C.S. Choong, S. Lim, D. Ismael, and Y.Y. Liang,
“Development of high density fan out wafer level package (HD FOWLP) with multi-layer
fine pitch RDL for mobile applications,” IEEE 66th Electronic Components and Technology
Conference, Las Vegas, 2016, pp. 1522-1529.
[3] M.-H. Chan, Y.-P. Wang, I. Chang, J. Chiang, G. Pan, N. Kao, and D. Wang, “Development
and challenges of warpage for fan-out wafer-level package technology,” International
Symposium on Microelectronics, vol. 2016, no. 1, pp. 524-528.

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