RF Amplifier
RF Amplifier
RF Amplifier
1
Low Frequency Amplifier
• Transistor is an voltage controlled current source
• Device capacitances are negligible
• High Zin , rO are desirable for high voltage gain
• Amplifier gain drops as frequency increases due to internal and
external capacitances → Low pass type amplifier
RS Transistor model
iL
+ +
Z in vin g mvin rO VL RL
vS
-
−
Z in
VL = ⋅ vS ⋅ (− g m ) ⋅ ( RL || rO )
Z S + Z in 2
Tuned Amplifier
• Gain over a narrow frequency range centered about some high
frequency
• If feedback by Cgd is negligible
VL = vin ⋅ (− g m ) ⋅ ( RL || rO ) at f = 1/(2π LC )
yin yout
RS
+ Cgd +
vS C gs vin g mvin rO RL C L VL
- −
3
Tuned Amplifier
• When the internal capacitances cannot be ignored, yin and yout depend
on the load and the source impedances respectively (Miller Effects)
yout ≈ jω Cgd (1 + g m RS ) = jω Ceq if jω (Cgd + Cgs ) << g m
yin ≈ jω Cgs + jω Cgd (1 + g m / yL ) = jω Cin if jω Cgd << yL
• Additional capacitive loading at the output by Ceq=Cgd[1+gmRs]
• Resonance frequency shifts downward due to Ceq→ difficult to
control the resonance frequency→ need relatively large C
• If yL is inductive (below resonance frequency), yin shows negative
resistance →may oscillate
• Cgd loads the output tank, decreases gain, detunes the resonance, and
most importantly causes instability
– Minimizing feedback due to Cgd → Cascode topology
– Bilateral design using S parameters
4
S Parameters of FET
Lg Rg Cgd Rd Ld
Ri
C gs + g me − jωτ vi rds Cds
vi Csub
−
Intrinsics
Rs
Rsub
Ls
ECP for RF CMOS with simple substrate model when body is grounded
In general, the substrate model is more complicated
5
Bias Independent Parameters of FET
• Bias independence: assumption for convenience
• Lg, Ls, Ld: parasitic inductances mainly due to electrodes. several
tens of pH, usually ignored for a few GHz application, but important
for mm application
• Rg: due to gate poly resistance, reduce the power gain, increase device
noise
• Rs: due to ohmic resistance, reduce gm, effective gme = gm/(1+gmRs)
• Rd:due to ohmic resistance, affects the device power gain
6
Bias Dependent Parameters of FET
Ri : effective charging path resistance for Cgs , ≈ Rc / 3, Rc channel resistance at DC
For simple channel model(short channel device)
assume uniform sheet charge, and velocity saturated channel
id = −eWvs ns (vgs ), Qn = qWLns (vgs )
∂Qn ∂n ∂i ∂n
C gs = = qWL s , g m = d = qWvs s
∂vgs ∂vgs ∂vgs ∂vgs
∂id
g m / Cgs = vs / L = = 1/ τ (τ : charging time)
∂Qn
3L
⇒ more accurately, τ = (transit time),g m ∝ 1/ L
4 vs
∂Qn
C gd = : parasitic, cause nonunilaterality
∂vgd
−1
∂i
rds = d cause ouput power loss
∂vds
Rsub , Csub less dependent on Vgs, but sensitive to Vds, cause output power loss and cross talk
7
fT of FET
ig id
• Assume unilateral, ignore Cgd
• Short circuit current gain, h21=ig/id C gd
C gs + gm
vi
id g m vgs gm −
h21 = ≈ =
ig ω Cgs vgs ω Cgs
⇒ h 21 drops by 6dB/octave
gm
h21 ω =ω = 1 ⇒ ωT = , 2π fT = ωT
T
Cgs
f T is a figure of merit for switching speed
8
fmax of FET
• Assume unilateral
• Gp : Power gain under matched condition
G p = PL / Pg = Re(Vd I d* ) / Re(Vg I g* )
Re( Z L ) 2 R
ig id = Id / I g
2
= Id / I g ds
Re( Z g ) Rg
Rg (← I d = g m v gs / 2, v gs = I g / jωC gs )
+ + +
Rds 2
Z g vg Cgs vi gm Z L vd 1 gm Rds 1 fT
2
Rds
− − − = =
4 C gs Rg 4 f Rg
G p = 1 at f = f max
fT
f max =
4 Rg / Rds
9
Accurate fT and fmax
• Nonunilateral
• Includes all parasitic resistances
• For CMOS, junction capacitance should be merged to Cgs, Cgd
• Substrate parasitics are not included
gm
fT =
2π [C gs + C gd ][1 + ( Rs + Rd ) / Rds ] + g mC gd ( Rs + Rd )
fT
f max =
1 g m ( Rs + Rg ) 4 C gd 3C gd
4 g m Ri + + 1 + (1 + g m Rs ) 2
Rds g m (1 + g m Rs ) 5 C gs 2C
gs
10
Low Frequency Approximation of S11, S22
Lg, Ls, Ld, Rd, Rs, Ri, τ are ignored
Z in − Z 0
S11 = Series R-C
S(1,1)
Z in + Z 0 m5
Z in = Rg + 1/ jω Cin m6
Z out − Z 0
S22 =
freq (50.00MHz to 10.00GHz)
Z out + Z 0
Z out = (ro ||1/ jω Ceq )
S(2,2)
Parallel R-C
L18 CMOS S-parameter
m7
(2.15GHz & 5.25GHz) m8
for Finger=32 (width=160um)
11
Low Frequency Approximation of S21,S12
−2 g m Z 0
S 21 = when Rg are ignored
1 + jω Cin Z 0
Cin = Cgs + Cgd (1 + g m Z 0 )
jω Cgd Z 0
S12 = when Z0 << 1/ jω Cgs
1 + jω Cgd Z 0
m2 m4
m1 m3
S(1,2)
S(2,1)
13
Small Signal High Frequency Amplifier
Γa Γb
(VSWR)in ΓS (Z S ) Γ in ( Z in ) Γ out ( Z out ) Γ L ( Z L ) (VSWR)out
• Recall!
Z in − Z o
Γin =
Z in + Z o
14
Small Signal High Frequency Amplifier
• For Re(Zi)>0, always |Γi|≤1
• VSWR
1 + Γa Γin − ΓS* 1 + Γb Γout − ΓL*
(VSWR) in = = (VSWR) out = =
1 − Γa 1 − Γin ΓS 1 − Γb 1 − Γout ΓL
• All networks are specified by S parameters and reflection coefficient
Γ instead of impedance
– practically Γ , S parameters are based on the same normalizing impedance 50 Ω
– merely an alias of impedance or admittance
– Γin is equivalent to Zin, Γout is equivalent to Zout
• Amplifier Specification
– Linear spec :Gain, Bandwidth, VSWR, Noise Figure
– Nonlinear spec: P1dB, IIP3 etc.
15
Input, Output Reflection Coefficients
S12 S 21ΓL S11 − ∆ΓL
Γin = S11 + =
1 − S 22 ΓL 1 − S 22 ΓL ∆ = S11S 22 − S12 S 21
S12 S 21ΓS S 22 − ∆ΓS
Γout = S 22 + =
1 − S11ΓS 1 − S11ΓS
16
Simplified Amplifier Network
ZS
Transistor ZL
[S]
Vs
17
Amplifier Gain in Terms of S Parameters
• Power
– Pavs : power available from source, function of source impedance
– Pin : power delivered to transistor VS2
Pavs = , function of ZS
– Pavn: power available from transistor output 8Re(ZS )
– PL:power delivered to load, function of load impedance
• Transducer power gain GT =PL/Pavs (function of ΓS , ΓL)
• Available power gain GA=Pavn/Pavs (function of ΓS)
• Operating power gain GP= PL/Pin (function of ΓL)
• Measurements
– usual power measurement setup gives GT since signal source indicates Pavs,
power meter reads PL
– VNA |S21|2 corresponds to GT for ΓS= ΓL=0
18
Derivation of Transducer Power Gain
a1 a2
ZS b1 b2
[S ] ZL
19
Transducer Power Gain GT
(1− | Γ S |2 ) | S 21 |2 (1− | Γ L |2 )
GT =
| (1 − S11Γ S )(1 − S 22 Γ L ) − S12 S 21Γ S Γ L |2
1− | Γ S |2 1− | Γ |2
= | S |2 L
|1 − Γin Γ S |2 |1 − S 22 Γ L |2
21
1− | Γ S |2 1 − | Γ |2
= | S |2 L
|1 − S11Γ S |2 |1 − Γ L Γ out |2
21
20
Available Power Gain GA, Operating Power Gain GT
1− | Γ S |2 1
GA = GT |Γ =Γ* = | S 21 |2
L out |1 − S11Γ S |2
1− | Γ out |2
Function of source impedance
GA Conjugately matched output
Useful for LNA design
1 1− | Γ |2
GP = GT |Γ =Γ* = | S |2 L
1− | Γin | |1 − S22 Γ L |2
S 2 21
in
Amplifier
ZL=73Ω
S11 S12
S S
21 22
22
Stability
• Unconditional Stability
– for any |ΓS|, |ΓL|≤1 ⇒ |Γin|, |Γout|≤1
• Simple measure of stability →Roulette Stability Factor K
1− | S11 |2 − | S 22 |2 + | ∆ |2
K= > 1, | ∆ |< 1, where ∆ = S11S 22 − S12 S 21
2 | S12 S 21 |
23
Simultaneous Conjugate Matching
• Only if unconditionally stable, simultaneous conjugate matching
yields maximum gain
– ΓS* =Γin(ΓL), ΓL* =Γout(ΓS)
– Solution ΓMS, ΓML are little bit complicated. CAD will help you.
S11 − ∆Γ L
Γ s = Γ1 =
*
1 − S22 Γ L
S 22 − ∆Γ s
ΓL = Γ2 =
*
1 − S11Γ s
• Under simultaneous conjugate matching condition
– GTmax = GPmax = GAmax
| S 21 |
GTmax = ( K − K 2 − 1)
| S12 |
24
Stability Circles
• Potentially Unstable(Conditional Stability)
– find stable ZS and ZL using stability circle
• Input (Source) Stability Circle
– locus of ΓS on Smith chart producing |Γout|=1
– if |S11|<1, ZS in the region including origin(ZS=Z0) is stable source impedance
• Output (Load) Stability Circle
– locus of ΓL on Smith chart producing |Γin|=1
– if |S22|<1, ZL in the region including origin(ZS=Z0) is stable load impedance
• You can easily draw stability circle using CAD
25
Load Stability Circle(LSC)
From ΓL plane
Im
S12 S 21ΓL
S11 + =1
1 − S 22 ΓL
⇒ ΓL −
(S 22 − DS11**
) =
S12 S 21
(2)
RL
2 2 2 2
S 22 − D S 22 − D CL
Re
0
26
Source Stability Circle(SSC)
From Γ S plane
Im
S12 S 21Γs
S 22 + =1
1 − S 22Γs
⇒Γ −
(
s
S 11 − DS 22
**
) =
S12 S 21
(3)
Rs
2 2 2 2 Cs
S11 − D S11 − D 0
Re
27
Stability Regions
• The source and load stability circles only indicate the value
of Γs and ΓL where |Γ2 | = 1 and |Γ1 | = 1. We need more
information to show the stability regions for Γ s andΓL.
• For example for LSC, when ΓL =0, |Γ1 | = |S11|.
• Let the LSC does not encircle S11=0 point. If |S11| < 1 then
ΓL =0 is a stable point, else if |S11| > 1 then ΓL=0 is an
unstable point.
Stable
LSC
Region LSC
|S11|<1
|S11|>128
Stability Region Cont...
Stable
Region
LSC
LSC
|S11|<1
|S11|>1
29
Summary for Stability Region
LSC or SSC
LSC or SSC
LSC or SSC
LSC or SSC
• There are times when the amplifier is stable for all passive
source and load impedance.
• In this case the amplifier is said to be unconditionally
stable.
• Assuming |S11| > 1 and |S22| < 1, the stability region would
look like this:
Γs can
ΓL can
occupy any
occupy any
point in the SSC
point in the
LSC Smith chart
Smith chart
|S11|>1
|S22|<131
Problem 2
• Use the s-parameters of the amplifier in Problem 1, draw the load and
source stability circles and find the stability region.
SSC LSC
32
Summary for Stability Check
Start
Draw SSC and LSC
No Amplifier is conditionally
K factor > 1
and |∆| < 1 ? stable, find stability
regions
Yes
Amplifier Unconditionally
Stable End
33
Stabilization Methods
• |Γin | > 1 and |Γout | > 1 can be written in terms of input and
output impedances:
Z in − Z o Z out − Z o
Γin = > 1 and Γ out = >1
Z in + Z o Z out + Z o
34
Stabilization Methods Cont...
R1’ R2’
2 - port
Network
Source Load
Network S 11 S 12 Network
S
21 S 22
Z1
Z2
Z1+R1’ Z1+R1’
2 - port
G1’ Network G2’
Source Load
Network S 11 S 12 Network
S
21 S 22
Y1+G1’ Y1 Y2 Y2+G2’ 35
Example - S-parameters measurement and stability
analysis
S-PARAMETERS DC
R
Rb1 L
Lc S_Param DC
R=10.0 kOhm
L=330.0 nH SP1 DC1
V_DC Start=50.0 MHz
SRC1 R=
Stop=1.0 GHz
Vdc=5.0 V
Step=1.0 MHz
L
Lb1
L=330.0 nH C
R= Cc2 Term
C=470.0 pF Term2
pb_phl_BFR92A_19921214 Num=2
Q1 Z=50 Ohm
C L
Cc1 Lb2
Term C=470.0 pF L=330.0 nH
Term1 R=
Num=1
Z=50 Ohm R R C
Rb2 Re Ce
R=4.7 kOhm R=100 Ohm C=470.0 pF
36
Example Cont...
Amplifier is
Plotting K and ∆ versus frequency m1
freq=600.0MHz conditionally
(from 50MHz to 1.0GHz): K=0.956
stable
1.2
m1
1.0
0.8
0.6
0.4
0.2
D
K
0.0
-0.2
-0.4
-0.6
-0.8
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
freq, GHz
38
Example Cont...
SSC
LSC
39
Example
40
Transistor Power Gain
• Used as a figure of merit for transistor
• Independent of source and load impedance
• Classification | S 21 |
– K>1, MAG(Maximum Available Gain) MAG = ( k − k 2 − 1)
| S12 |
|S |
– K<1, MSG(Maximum Stable Gain) MSG = 21
| S12 |
[dB] | S 21 / S12 − 1 |2
U=
2k | S 21 / S12 | −2 Re( S 21 / S12 )
K
MSG
3dB/oct MAG(6dB/octave)
41
f [log]
Narrow Band Amplifier Design
• Unilateral Design
– assume S12=0
– approximate design
– use unilateral transducer power gain GTU=GT|S12=0
– detailed design procedure (Refer to Gonzales)
– not practical, just shows attainable variable range of GT
• Bilateral Design(if S12 is not negligible)
– Simultaneous conjugate matching design
• valid for k>1(unconditionally stable), fixed gain GTMAX
– GP or GA design
• if unconditionally stable(k>1) and for gain other than GTMAX
• if potentially unstable(k<1)
42
Operating Power Gain Design
• Mismatched output, matched input
• (VSWR)in=1, (VSWR)out>1,
• Constant GP circle on ΓL plane
– locus of ΓL(ZL) that yields constant GP at a frequency
– GP is only a function of ΓL(ZL)
• Unconditionally stable case
GPMAX =| S 21 / S12 | ( K − K 2 − 1)
– GPMAX exists at a single point of ΓL(ZL)
– Design procedure for a gain less than GPMAX
① Determine GP
② Draw GP circle and select the desired ΓL
③ Matched source impedance is ΓS= Γin*
43
Design Procedure Using GP (potentially unstable)
① Determine GP(Gp<MSG)
② Draw GP circle
③ Draw load stability circle(Γin stability)
④ Select ΓL on the GP circle far from stability circle
⑤ Matched source impedance is ΓS= Γin*
⑥ Draw input stability circle(Γout stability)
– Check if ΓS placed in the stable region
– If stable, design completed
– If unstable. go to step 4 and select new ΓL
⑦ If input match is made, GP becomes GT
44
GP circle when K<1
45
Available Power Gain Design
• Mismatched input, matched output
• (VSWR)in>1, (VSWR)out=1
• Constant GA circle on Γ S plane
• Design procedures are equivalent to that of using GP gain except that
Γs replaces ΓL
• If output match is made, GA becomes GT
46
Noise
• Random variation of current or voltage
t +T
lim ∫ [V (t )] dt = constant
t +T
Vn = lim ∫ Vn (t ) dt = 0 vn2 =
t
n
2
vn, rms = vn2
t T →∞
T →∞
47
Noise
• Flicker noise
– PSD=Γ/fα, Γ: proportional constant, α≅1 Other noise source
• Lorentz noise
– PSD=kτ/(1+(ωτ)2)
48
Thermal noise of Resistance
• Available thermal noise power Pn=kTB
• Equivalent circuit of noisy R
– can deliver the same available noise power to matched load R
– Pn = v2n,rms/4R=i2n,rmsG/4
Noiseless R in,rms
G=1/R
Noisy R at T
Vn,rms
Noisy R at Te
Networks
Pa=kTe
50
Noise Factor
G1
G2 No
Ni F1
F2
N o / G1G2
F = 1+ , N o = N1G1G2 + N 2 G2 = N i ( F1 − 1)G1G2 + N i ( F2 − 1)G2
Ni
F2 − 1 G1, G2 available gain of each stage
F = F1 + N1, N2 input referred added noise power of each stage
G1
en
+-
YS Noisy 2 port → YS Noiseless 2 port
is is in
is2 + in + Ys en
2
F= 2
, in = ic + iu , ic = Yc en
is
is2 + iu + (Yc + Ys ) en
2
iu2 + Yc + Ys en2
2
F= = 1+
is2 is2
en2 iu2 is2
Rn ≡ , Gu ≡ , Gs ≡
4kT ∆f 4kT ∆f 4kT ∆f
+ ( + ) + ( + ) Rn
2 2
Gu + Yc + Ys Rn
2
G G G B B
F = 1+ = 1+
u c s c s
Gs Gs 53
CLASSICAL TWO-PORT NOISE THEORY
Gu
Bs = − Bc = Bopt , Gs = + Gc2 = Gopt
Rn
Gu
Fmin = 1 + 2 Rn Gopt + Gc = 1 + 2 Rn + Gc + Gc
2
Rn
Rn
( opt ) ( opt )
2 2
F = Fmin + G − G + B − B
Gs s s
54
Noise Figure of 2 Port Network
Rn
F = Fmin + [(Gs − Gopt ) 2 + ( Bs − Bopt ) 2 ]
Gs
Fmin minimum noise factor in,rms Noisy
Ys 2 Port
Ys=Gs+jBs source admittance Network
Yopt=Gopt+jBopt source admittance at Fmin
Rn equivalent input noise resistance of 2 port network
Noise 4 parameters : Fmin, Yopt, Rn
• Noise factor of 2 port network is dependent on the source admittance
• Noise 4 parameters are dependent on frequency and bias conditions
• Manufacturer provides noise 4 parameters
55
Noise Circle
4rn | Γs − Γopt | 2
F = Fmin +
(1− | Γs |2 ) | 1 + Γopt |2
rn = Rn / Z o
• Rn, Γopt, Fmin are device parameters and constants if bias and frequency
are fixed
• Locus of Γs on the Smith chart for a given noise figure Fi is a circle→
Constant Noise Figure Circle
Γopt ( 1-|Γ opt|2 )N i + N i2 Fi − Fmin
Center C Fi = Radius RFi = , where N i = | 1 + Γopt |2
1 + Ni 1+ Ni 4rn
56
LNA Design
• Impossible to achieve maximum gain and minimum noise figure
simultaneously
• Compromise between Gain, NF, and VSWR
• Potentially unstable bilateral design
① Determine GA(<MSG)
② Draw source stability circle, GA circle, NF circle on Γs plane
③ Select Γs.. close to Γopt and far from source stability circle
④ ΓL= Γ*out, automatically VSWRout=1
⑤ Output stability check (|Γin| <1)
⑥ Input is always mismatched. Therefore always (VSWR)in>1
57
•S parameters
Output stability circle S11=0.641/-171 °
S21=5.89/9.6 °
S12=0.057/163 °
S22=0.572/-95.7 °
2dB noise circle
•Stability
k=0.617
MSG=20.1dB
20dB GA circle potentially unstable
58