1984 Harris CMOS

Digital Data Book

Harris Semiconductor CMOS Digital Products Division's
products represent state-of-the-art in density and high
performance. The HAR RIS expertise in CMOS design
and processing offers the user the most rei iable product
available in a wide choice of formats, options, and
package types. With continuing research and develop-
ment and the introduction of new products, Harris
will provide its customers with the most advanced
CMOS technology.

This book describes Harris Semiconductor CMOS

Digital Products Division's complete line of digital
products and includes a complete set of product speci-
fications and data sheets. Also included are sections
on reliaiblity, programming, and packaging.

Please fill out the registration card at the back of th is

book and return it to us so we may keep you informed
of our latest new product developments over the next
year.

If you need more information on these and other

HARRIS products, please contact the nearest HARRIS
sales office listed in the back of this data book.

Harris Semiconductor's products are sold by description only.

HARRIS reserves the right to make changes in circuit design,
specifications and other information at any time without prior
notice. Accordingly, the reader is cautioned to verify that data
sheets and other information in this publication are current
before placing orders. Information contained in application notes
is intended soley for general guidance; use of the information for
user's specific application is at user's risk. Reference to products
of other manufacturers are solely for convenience of comparison
and do not imply total equivalency of design, performance,
or otherwise.

quan'um electro
Box. 391162
rarnley.
9J8.
 General Information II
CMOS Memory •

CMOS SOCS6 Family II

CMOS 12-Bit Microprocessors & Peripherals II
CMOS Data Communication II
Harris Reliability and Quality II
Hi-Reliability & Military Products II
Article Reprints II
Custom - Semi-Custom CMOS IC Information II
Ordering and Packaging II
DICE Information III
Appendices lEI
 GENERAL INFORMATION
Sector Capabilities
CMOS Alpha-Numeric Index
CMOS Devices by Families
Classification of Literature
Symbols and Abbrevations
CMOS MEMORY
CMOS Memory Product Index 2-2
Low Voltage Data Retention 2-3
Industry CMOS RAM Cross-Reference 2--4
1K CMOS RAM Data Sheets 2-5
4K CMOS RAM Data Sheets 2-29
16K CMOS RAM Data Sheets 2-51
CMOS RAM Module Data Sheets 2-85
CMOS PROM Data Sheets 2-113
Preview of CMOS PROM Products 2-126
Programming Format for Harris PROMs 2-127
Preview of Future CMOS HPL Circuits 2-130
CMOS 80C86 FAMILY
CMOS 80C86 Family Product Index 3-2
CMOS 80C86 Family Cross Reference 3-3
Harris 80C86 Family Data Sheets 3-4
Preview of Future Harris 80C86 Family Products 3-96
CMOS 12 BIT MICROPROCESSORS AND PERIPHERALS
CMOS 12 Bit Microprocessor and Peripheral Product Index 4-2
CMOS Microprocessor Data Sheets 4-3
CMOS Peripheral Data Sheets 4-59
CMOS DATA COMMUNICATIONS
CMOS Data Communications Product Index
CMOS Data Communications Data Sheets
HARRIS RELIABILITY AND QUALITY
Harris Reliability and Quality Table of Contents

HARRIS HI-REL AND MILITARY PRODUCTS

Harris Hi-Rei and Military Products Table of Contents
ARTICLE REPRINTS
Article Reprints Table of Contents
CUSTOM - SEMI-CUSTOM CMOS IC INFORMATION
Custom - Semi-Custom CMOS IC Information Table of Contents 9-1
SECTION 10 ORDERING AND PACKAGING
Ordering and Packaging Information
SECTION 11 DICE INFORMATION
Dice Information
SECTION 12 APPENDICES
Sector Alpha-Numeric Product Index 12-3
Harris Sales Locations 12-8
1-2

1-3

1-4

1-6

1-6
 Harris Semiconductor
Sector Capabilities
Harris Semiconductor is one of the five management groups of Harris Cor-
poration, a producer of high-technology communication and information
processing systems sold in over 160 countries. Five main operations of
Harris Semiconductor produce standard and custom semiconductor devices.
These operations are:

ANALOG PRODUCTS DIVISION

Harris is a major force in analog integrated circuitry, offering a broad
line of products including: analog-to-digital converters, digital-to-
analog converters, switches, multiplexers, voltage references, opera-
tional amplifiers, telecommunications and speech processing products.

BIPOLAR DIGITAL PRODUCTS DIVISION

Harris introduced the industry's first bipolar programmable read only
memory in 1970 and has continued as a leader in the field of bipolar
PROMs. Harris offers a complete spectrum of bipolar PROMs from
256 bits to 64K bits, Also, offered is a new family of programmable
logic products featuring on-chip testability.

CMOS DIGITAL PRODUCTS DIVISION

Harris is a pioneer in developing and producing digital CMOS products
including: CMOS RAMs, CMOS PROMs, CMOS microprocessors, CMOS
peripherals, CMOS data communications products, and this year intro-
ducing a full line of SOCS6microprocessors and peripherals.

CUSTOM INTEGRATED CIRCUITS DIVISION

Harris designs, develops and manufactlJ'l'escustom analog, digital bipolar,
radiation-hardened, and CMOS circuits for specialized military and
commercial applications.

MICROWAVE SEMICONDUCTOR, INC.

Harris Microwave Semiconductor, Inc. develops and manufactures
gallium arsenide transistors, integrated circuits and microwave amplifiers.
 PAGE
..-.lliL..
HD-15530 Manchester Encoder-Decoder 5-3
HD-15531 Manchester Encoder-Decoder 5-10
HD-4702 Programmable Bit Rate Generator 5-56
HD-6101 Parallel Interface Element 4-51
HD-6120 12 Bit High Performance Microprocessor 4-3
HD-6121 I/O Controller 4-22
HD-6402 LSI Universal Asynchronous Receiver Transmitter 5-51
HD-6406 Programmable Asynchronous Communication Interface 5-39
HD-6408 Asynchronous Manchester Adapter 5-25
HD-6409 Manchester Encoder-Decoder 5-30
HD-6431 Hex Latching Bus Driver 4-59
HD-6432 Hex Bi-directional Bus Driver 4-62
HD-6433 Quad Bus Separator/Driver 4-65
HD-6434 Octal Resettable Latch 4-68
HD-6436 Octal Bus Buffer/Driver 4-71
HD-6440 Latch Decoder/Driver 4-74
HD-6495 Hex Bus Driver 4-78
HM-6100 12 Bit Static Microprocessor 4-30
HM-6504 4K X 1 Synchronous RAM 2-29
HM-6508 1K X 1 Synchronous RAM 2-5
HM-6514 1K X 4 Synchronous RAM 2-40
HM-6516 2K X 8 Synchronous RAM 2-51
HM-65162 2K X 8 Asynchronous RAM 2-57
HM-65172 2K X 8 Asynchronous RAM 2-70
HM-6518 1K X 1 Synchronous RAM 2-11
HM-65262 16K X 1 Asynchronous RAM 2-83
HM-6551 256 X 4 Synchronous RAM 2-17
HM-6561 256 X 4 Synchronous RAM 2-23
HM-6564 64K Synchronous RAM Module 2-85
HM-6616 2K X 8 Fuse Link PROM 2-118
HM-6641 512 X 8 PROM 2-113
HM-6664 8K X 8 Fuse Link PROM 2-126
HM-92560 256K Synchronous RAM Module 2-96
HM-92570 256K Synchronous RAM Module 2-104
HPL-16LC8 Programmable Logic 2-130
HPL-16RC4 Programmable Logic 2-132
HPL-16RC6 Programmable Logic 2-132
HPL-16RC8 Programmable Logic 2-132
8UC86 16 Bit Microprocessor 3-4
80C88 8 Bit Microprocessor 3-96
82C37A High Performance Programmable DMA Controller 3-97
82C52 Full Duplex UART 3-27
82C54 Programmable Interval Timer 3-28
82C55A Programmable Peripheral Interface 3-43
82C59A Priority Interrupt Controller 3-62
82C82 Octal Latch 3-77
82C83 Octal Latching Inverting Bus Driver 3-98
82C84A Clock Generator/Driver 3-82
82C84B Clock Generator Driver 3-99
82C86 Octal Bus Transceiver 3-100
82C87 Octal Bus Transceiver 3-101
82C88 Bus Controller 3-89
82C89 Bus Arbiter 3-102
CMOS Microprocessor and Support Circuits

8/16 BIT MICROPROCESSORS

80C86 16 Bit CMOS Microprocessor 3-4

80C88 8 Bit CMOS Microprocessor 3-96

82C37A CMOS DMA Controller 3-97

82C52 CMOS Serial Communication Interface 3-27
82C54 CMOS Programmable I nterval Timer 3-28
82C55A CMOS Programmable Peripheral Interface 3-43
82C59A CMOS Priority Interrupt Controller 3-62

82C82 CMOS Octal Latching Bus Driver 3-77

82C83 CMOS Octal Latching Inverting Bus Driver 3-98
82C84A CMOS Clock Generator Driver 3-82
82C84B CMOS Clock Generator Driver 3-99
82C86 CMOS Octal Bus Transceiver 3-100
82C87 CMOS Octal Inverting Bus Transceiver 3-101
82C88 CMOS Bus Controller 3-89
82C89 CMOS Bus Arbiter 3-102

HM-6100 CMOS 12 Bit Microprocessor 4-30

HD-6120 CMOS High Performance 12 Bit Microprocessor 4-3

HD-6101 CMOS Parallel Interface Element (PIE) 4-51

HD-6121 CMOS I/O Controller (IOC) 4-22

HD-6431 CMOS Hex Latching Bus Driver 4-59

HD-6432 CMOS Hex Bi-directional Bus Driver 4-62
HD-6433 CMOS Quad Bus Separator/Driver 4-65
HD-6434 CMOS Octal Bus Driver W/Reset 4-68
HD-6436 CMOS Octal Bus Buffer/Driver 4-71
HD-6440 CMOS Latched 3 to 8 Line Decoder/Driver 4-74
HD-6495 CMOS Hex Bus Driver 4-78

HD-4702 CMOS Bit Rate Generator 5-56

HD-6402 CMOS UART 5-51
HD-6406 CMOS Prog. Async. Communication Interface 5-39
HD-6408 CMOS Async. Serial Manchester Adapter (ASMA) 5-25
HD-6409 CMOS Manchester Encoder-Decoder 5-30
HD-15530 CMOS Manchester Encoder-Decoder 5-3
HD-15531 CMOS Manchester Encoder-Decoder 5-10
 CMOS Devices by Families
(continued)

HM-6508 1 K Xl 2-5
HM-6518 1 K Xl 2-11
HM-6551 256 X 4 2-17
HM-6561 256 X 4 2-25

HM-6504 4K Xl 2-29
HM-6514 1K X 4 2-40

16K-ASYNCHRONOUS
HM-65162 2K X 8 2-57
HM-65172 2K X 8 2-70
HM-65262 16K X 1 2-83
CMOS RAM MODULES
HM-6564 64K 2-85
HM-92560 256K 2-96
HM-92570 Buffered 256K 2-104
CMOS RADIATION HARDENED RAMS

HS-6504RH 4K Xl 9-18
HS-6508RH 1K X 1 9-19
HS-6514RH 1K X 4 9-20
HS-6551 RH 256 X 4 9-21
HS-6564R H 16K X 4 or 8K X 8 9-2

HM-6641 512 X 8 2-113

HM-6616 2K X 8 2-118
HM-6664 8KX8 2-126

CMOS Programmable Logic

HPL-16LC8 ProgrammableLogic 2-130
HPL-16RC4 ProgrammableLogic 2-132
HPL-16RC6 Programmable Logic 2-132
HPL-16RC8 ProgrammableLogic 2-132
CLASSIFICATION PRODUCT STAGE DISCLAIMERS

Preview Formative or This document contains the design specifications

DATA Design for product under development. Specifications
SHEET may be changed in any manner without notice.

Advance Sampling or This is advanced information, and specifications

Information Pre-Production are subject to change without notice.
DATA SHEET

Preliminary First Production Supplementary data may be published at a

DATA SHEET later date.
Harris reserves the right to make changes at any-
time without notice, in order to improve design
and supply the best product possible.

This data book utilizes a new set of specification nomenclature. This new format is an IEEE and JEDEC supported standard
for semiconductor memories. It is intended to clarify the symbols, abbreviations and definitions, and to make all memory
data sheets consistent. We believe that, once acclimated, you will find this standardized format easy to read and use.

CHIP
ENABLE E _ ~

v (Voltage) LEH
I (Current)
WRITE
P (Power) I;NABLE iN ~
C (Capacitance)

The second letter specifies input (I) or output (0), and the
third letter indicates the high (Hl. low (Ll or off (Zl state
of the pin during measurements. Examples:

The table of timing values shows either a minimum or a

maximum limit for each parameter. Input requirements
are specified from the external system point of view.
Thus, address set-up time is shown as a minimum since
the system must supply at least that much time (even
All timing abbreviations use upper case characters with no though most devices do not require it). On the other hand,
subscripts. The initial ch,facter is always T and is followed responses from the memory are specified from the device
by four descriptors. These characters specify twO signal point of view. Thus, the access time is shown as a maxi-
points arranged in a "from-to" seQuence that define a mum since the device never provides data later than that
timing interval. The two descriptors for each signal point time.
specify the signal name and the signal transitions. Thus
the format is:

TXXXX

-.J i I)
WAVEFORM INPUT OUTPUT
SYMBOL
S;,n.1 n.m, f,om wh;,h In•• ,..1 j, d,fin,d
Transition direction for first signal =-.J MUST
VAllO
BE WilL
VAllO
BE
Signal name to which interval is defined
Transition direction for second signal
CHANGE WILL CHANGE
~ FROM H TO L FROMHTOL

A· Address CHANGE WILL CHANGE

D· Data In ~ FROMLTOH FROM L TOH

Q. Data Out
DON'T CARE
W • Write Enable CHANGING
E • Chip Enable ~ ANY CHANGE
PERMITTED
STATE UNKNOWN

S" Chip Select

G •• Output Enable
:::::>- HIGH
IMPEDANCE

H •• Tnnsition to High
L" Transition to Low
V" Transition to Valid
X" Transition to Invalid or Don't Care
Z •• Transition to Off (High Impedance)
 2-2

Low Voltage Data Retention 2-3

Industry CMOS RAM
Cross-Reference 2-4
Product Information 2-5
1K CMOS RAM DATA SHEETS
HM-6508 1K x 1 Synchronous RAM 2-5
HM-6518 1K x 1 Synchronous RAM 2-11
HM-6551 256 x 4 Synchronous RAM 2-17
HM-6561 256 x 4 Synchronous RAM 2-23

4K CMOS RAM DATA SHEETS

HM-6504 4K x 1 Synchronous RAM 2-29
HM-6514 1K x 4 Synchronous RAM 2-40

16K CMOS RAM DATA SHEETS

HM-6516 2K x 8 Synchronous RAM 2-51
HM-65162 2K x 8 Asynchronous RAM 2-57
HM-65172 2K x 8 Asynchronous RAM 2-70

PREVIEW OF FUTURE CMOS RAM PRODUCTS

HM-65262 16K x 1 Asynchronous RAM

CMOS RAM MODULE DATA SHEETS

HM-6564 64K Synchronous RAM Module 2-85
HM-92560 256K Synchronous RAM Module 2-96
HM-92570 256K Synchronous RAM Module 2-104

CMOS PROM DATA SHEETS

HM-6641 512 x 8 Fuse Link PROM 2-113
HM-6616 2K x 8 Fuse Link PROM 2-118

PREVIEW OF FUTURE CMOS PROM PRODUCTS

HM-6664 8K x 8 Fuse Link PROM 2-126

2-128

PREVIEW OF FUTURE CMOS HPL CIRCUITS

HPL-16LC8 Programmable Logic 2-130
HPL-16RC4 Programmable Logic 2-132
HPL-16RC6 Programmable Logic 2-132
HPL-16RC8 Programmable Logic 2-132
HARRIS CMOS RAMs are designed with battery backup in mind. Data retention voltage and supply current are
guaranteed over temperature. The following rules insure data retention:

2. On RAMs which have selects or output enables (e.g. S, G), one of the selects or output enables should be
held in the deselected state to keep the RAM outputs high impedance, minimizing power dissipation.

4. Inputs which are to be held high (e.g. E) must be kept between VCC + 0.3V and 70% of VCC during the
power up and power down transitions.

5. The RAM can begin operation one TEHEL (for synchronous RAMs) and> 55ns (for asynchronous RAMs)
after VCC reaches the minimum operating voltage (4.5 voltsl.
 os ~
~
~ ~ ~ t.J:.,f ~
~.;:r
0 ~v
"Y

~
~:--..

~~
CMOS RAMs
<:; ~ ,p 0«; §' 8" ° ~ "0$
FEATURES

1K CMOS RAMs
HM-6508 -lK x 1 16 PIN 6508 8401 6508 6508 6508 6508 443 6508 5508 2125
SYNCH 74C929 1821 4015

HM-6518 - lK x 1 18PIN 6518 6518 6518 6518 6518

SYNCH 74C930

HM-6561 - 256 x 4 22 PIN 6551 6551 1822 5101 2101

SYNCH 74C920

HM-6561 - 256 x 4 18 PIN 6561 2111

SYNCH

4K CMOS RAMs
HM-6504 - 4K x 1 18PIN 6504 8404 4315 6504 6504 6504 6504 5104 5504 2141/47
SYNCH 6147 3150
4104
4404

HM-6514-1Kx4 18PIN 6514 8414 4334 6514 6514 58981 6514 6514 444 5114 5114 5514 2114
SYNCH 6148 5115 2148/49
4045
314A

16K CMOS RAMs

HM-6516 - 2K x 8 24 PIN 6516 6516
.,
SYNCH

HM-65162 - 2K x 8 24PIN 8416 6116 6116 5117 65116 6116 446 5128 6116 5517 4802
ASYNCH 2116
2016
4016

HM-65172 - 2K x 8 24 PIN 8418 6117 5116 449 5516

ASYNCH

HM-65262 - 16K x 1 20 PIN

ASYNCH
6167 6167 I 2167
8167
m HARRIS HM-6508

Pinout
TOP VIEW
• LOW STANDBY POWER 50J.l.WMAX
• LOW OPERATING POWER 20mW/MHz MAX
• FAST ACCESS TIME 180n58c MAX r vcc
• DATA RETENTION VOLTAGE 2.0 VOL TS MIN AO D
• TTL COMPATIBLE IN/OUT
Al W
• HIGH OUTPUT DRIVE - 2 TTL LOADS
• HIGH NOISE IMMUNITY A2 A9

• ON CHIP ADDRESS REGISTER A3 Ae

• MILITARY TEMPERATURE RANGE
A4 A7
• INDUSTRIAL TEMPERATURE RANGE
• THREE-STATE OUTPUTS a A6

• 16 PIN PACKAGE FOR HIGH DENSITY GND AS

A - Address' nput
E- Chip Enable
W- Write Enable
The HM-6508 is a 1024 by 1 static CMOS RAM fabricated using self-
aligned silicon gate technology. Synchronous circuit design techniques are
employed to achieve high performance and low power operation.

On chip latches are provided for address allowing efficient interfacing with
microprocessor systems. The data output buffers can be forced to a high
impedance state for use in expanded memory arrays.

The HM-6508 is a fully static RAM and may be maintained in any state
for an indefinite period of time. Data retention supply voltage and supply
current are guaranteed over temperature.

ALL LINES POSITIVE LOGIC - ACTIVE HIGH

THREE STATE BUFFERS,

A HIGH -OUTPUT ACTIVE

ADDRESS REGISTER AND DECODERS,

LATCHED LATCH ON FALLING EDGE OF E
AODRESS GATE ON FALLING EDGE OF E
REGISTER

CAUTION: These devices are sensitive to electronic discharge. Proper I.C. handling procedures should be followed.

2-5
 Operating Supply Voltage -VCC
Military (-2) 4.5V to 5.5V
Input or Output Voltage Applied (GND -O.3V) Industrial (-9) 4.5V to 5.5V
to (VCC +O.3Vl
Operating Temperature
Military (-2) -550C to +1250C
Industrial (-9) -4QOC to +850C

TEMP.S. VCC =
OPERATING TEMP. - 250CG)
RANGE VCC -5.0V
TEST
SYMBOL PARAMETER MIN MAX TYPICAL UNITS CONDITIONS

ICCSS Standby Supply Current 10 0.1 JlA 10 = 0

VI = VCC or GND
ICCOP Operating Supply Current@ 4 1.5 mA f=lMHz,IO=O
VI ~ VCC or GND
ICCDR Data Retention Supply Current 5 0.01 JlA VCC = 2.0, 10 = 0
VI = VCC or GND
VCCDR Data Retention Supply Voltage 2.0 1.4 V E = VCC
II Input Leakage Current -1.0 +1.0 0.0 JlA GND ~ VI ~ VCC
10Z Output Leakage Current -1.0 +1.0 0.0 JlA GND~VO~ VCC
VIL Input Low Voltage -0.3 0.8 2.0 V
VIH Input High Voltage VCC -2.0 VCC +0.3 2.0 V
VOL Output Low Voltage 0.4 0.2 V 10 = 3.2mA
VOH Output High Voltage 2.4 4.5 V 10 = -0.4mA
CI Input Capacitance ® 6 4 pF VI = VCC or GND
f: lMHz
CO Output Capacitance@ 10 6 pF VO = VCC or GND
f ~ lMHz

TELQV Chip Enable Access Time 180 100 ns @

TAVQV Address Access Time 180 90 ns @
TELQX Chip Enable Output Enable Time 20 120 40 ns @
TWLQZ Write Enable Output Disable Time 120 40 ns @
TEHQZ Chip Enable Output Disable Time 120 40 ns @
TELEH Chip Enable Pulse Negative Width 180 100 ns @
TEHEL Chip Enable Pulse Positive Width 100 50 ns @
TAVEL Address Setup Time 0 -10 ns @
TELAX Address Hold Time 40 20 ns @
TDVWH Data Setup Time 80 40 ns @
TWHDX Data Hold Time 0 0 ns @
TWLEH Chip Enable Write Pulse Setup Time 100 50 ns @
TELWH Chip Enable Write Pulse Hold Time 100 50 ns @
TWLWH Write Enable Pulse Width 100 50 ns @
TELEL Read or Write Cycle Time 280 150 ns @

NOTES: 1. All devices tested at worst case limits. Room temp .• 5 volt data provided for information - not guaranteed.
2. Operating Supply Current (ICCOP) is proportional to Operating Frequency. Example: Typical ICCOP = 1.5mA/MHz.
3. Capacitance sampled and guaranteed - not 100% tested.
4. AC Test Conditions: Inputs - TR ISE : TFALL ~ 20nsec; Outputs - CLOAD = 50pF. All timing
measurements at 1.5V reference level.
 Operating Supply Voltage -VCC
Military (-2) 4.5V to 5.5V
Input or Output Voltage Applied (GND -O.3Vl Industrial (-9) 4.5V to 5.5V
to (GND +O.3V)
Operating Temperature
Military (-2) -550C to +1250C
Industrial (-9) -400C to +850C

TEMP. & VCC =

OPERATING TEMP. = 250C CD
RANGE VCC = 5.0V
TEST
SYMBOL PARAMETER MIN MAX TYPICAL UNITS CONDITIONS

ICCSS Standby Supply Current 10 0.1 f..LA 10 = a

VI = VCC or GND
ICCOP Operating Supply Current @ 4 1.5 mA f = 1 MHz. 10 = a
VI = VCC or GND
ICCDR Data Retention Supply Current 10 0.01 f..LA VCC=2.0.10=0
VI = VCC or GND
VCCDR Data Retention Supply Voltage 2.0 1.4 V E= VCC

II Input Leakage Current -1.0 +1.0 0.0 f..LA

GND" VI " VCC
10Z Output Leakage Current -1.0 +1.0 0.0 f..LA
GND " VO" VCC
VIL Input Low Voltage -0.3 0.8 2.0 V
VIH Input High Voltage VCC -2.0 VCC +0.3 2.0 V
VOL Output Low Voltage 0.4 0.2 V 10 = 3.2mA
VOH Output High Voltage 2.4 4.5 V 10 = -O.4mA
CI Input Capacitance@ 6 4 pF VI = VCC or GND
f = lMHz
CO Output Capacitance ® 10 6 pF VO=VCC or GND
f = lMHz

TELQV Chip Enable Access Time 250 110 ns @

TAVQV Address Access Time 250 100 ns @
TELQX Chip Enable Output Enable Time 20 160 60 ns @
TWLQZ Write Enable Output Disable Time 160 60 ns @
TEHQZ Chip Enable Output Disable Time 160 60 ns @
TELEH Chip Enable Pulse Negative Width 250 110 ns @
TEHEL Chip Enable Pulse Positive Width 100 50 ns @
TAVEL Address Setup Time a -10 ns @
TELAX Address Hold Time 50 30 ns @)
TDVWH Data Setup Time 110 50 ns @)
TWHDX Data Hold Time a a ns @)
TWLEH Chip Enable Write Pulse Setup Time 130 60 ns @)
TELWH Chip Enable Write Pulse Hold Time 130 60 ns @
TWLWH Write Enable Pulse Width 130 60 ns @)
TELEL Read or Write Cycle Time 350 160 ns @)

NOTES: 1. All devices tested at worst case limits. Room temp., 5 volt data provided for information - not guaranteed.
2. Operating Supply Current (lCCOP) is proportional to Operating Frequency. Example: TypicaliCCOP = 1.5mA/MHz.
3. Capacitance sampled and guaranteed - not 100% tested.
4. AC Test Conditions: Inputs - TRISE = TFALL = 20nsec; Outputs - CLOAD = 50pF. All timing
measurements at 1.5V reference level.
 Operating Supply Voltage -VCC
Commercial
(GND -O.3Vl
to (VCC +{).3V)
Operating Temperature
Commercial

TEMP.& VCC z

OPERATING TEMP. = 250C G)

RANGE VCC = 5.0V
TEST
SYMBOL PARAMETER MIN MAX TYPICAL UNITS CONDITIONS

ICCSB Standby Supply Current 100 10 J.lA 10 = 0

VI = VCC or GND
ICCOP Operating Supply Current ® 4 1.5 mA f=IMHz.IO=O
VI = VCC or GND

ICCDR Oat8 Retention Supply Current 100 1.0 IlA VCC = 2.0. 10 z 0
VI z VCC or GND
E = VCC
VCCDR Data Retention Supply Voltage 2.0 V

II Input Leakage Current -1.0 +1.0 0.0 J.lA GND'" VI'" VCC
10Z Output Leakage Current -1.0 +1.0 0.0 J.lA GND"'VO~ VCC
VIL Input Low Voltage -0.3 O.B 2.0 V
VIH Input High Voltage VCC -2.0 VCC +0.3 2.0 V
VOL Output Low Voltage 0.4 0.2 V 10 =1.6mA
VOH Output High Voltage 2.4 4.5 V 10 =-Q.2mA
CI Input Capacitance@ 6 4 pF VI = VCC or GND
f = lMHz
CO Output Capacitance ® 10 6 pF VO = VCC or GND
f = lMHz

TELQV Chip Enable Access Time 300 160 ns ®

TAVQV Address Access"Time 310 160 ns ®
TELQX Chip Enable Output Enable Time 20 200 60 ns ®
TWLQZ Write Enable Output Disable Time 200 60 ns ®
TEHQZ Chip Enable Output Disable Time 200 60 ns ®
TELEH Chip Enable Pulse Negative Width 300 160 ns ®
TEHEL Chip Enable Pulse Positive Width 150 90 ns @
TAVEL Address Setup Time 10 a ns @
TELAX Address Hold Time 70 40 ns ®
TDVWH Data Setup Time 130 BO ns ®
TWHDX Data Hold Time a 0 ns ®
TWLEH Chip Enable Write Pulse Setup Time 160 100 ns ®
TELWH Chip Enable Write Pulse Hold Time 160 100 ns ®
TWLWH Write Enable Pulse Width 160 100 ns ®
TELEL Read or Write Cycle Time 450 250 ns ®

NOTES: 1. All devices tested at worst case limits. Room temp., 5 volt data provided for information - not guaranteed.
2. Opereting Supply Current IiCCOP) is proportional to Operating Frequency. Exemple: Typical ICCOP = 1.5mA/MHz.
3. Capacitance sampled and guaranteed - not 100% tested.
4. AC Test Conditions: Inputs - TRISE = TFALL = 20nsec; Outputs - CLOAD = 50pF. All timing
measurements at 1.5V reference level.
 TAVEL~ m.•x-l TAVEL~ I-
VAllO NUT
nUL

_ nHEL TEHEL_
nUH

---' ~
HIGH

o5-=Q
nHOZ
_nLQV

_TELQX - TEHQZ

TOM' __ I I_~I t_~ __ 1 1

REFERENCE r--1 r-----1 I"l
·1 0 , 2 4 5

TIME INPUTS OUTPUTS

REFERENCE E Vii A 0 Q FUNCTION

-1 H X X X Z MEMORY DISABLED
0
1 "'-
L
H
H
V
X
X
X
Z
X
CYCLE
OUTPUT
BEGINS.
ENABLED
ADDRESSES ARE LATCHED

2 L H X X V OUTPUT VALID
3
..r H X X V READ ACCOMPLISHED
4 H X X X Z PREPARE FOR NEXT CYCLE (SAME AS -1)
5
"'- H V X Z CYCLE ENDS. NEXT CYCLE BEGINS (SAME AS 0)

In the HM-6508 Read Cycle, the address information is (T = 2). W must remain high for the read cycle. After the
latched into the on chip registers on the falling edge of output data has been read, E may return high (T = 3).
E (T = 0). Minimum address setup and hold time require- This will disable the chip and force the output buffer to
ments must be met. After the required hold time, the a high impedance state. After the required E high time
addresses may change state without affecting device opera- (TEHEL) the RAM is ready for the next memory cycle
tion. During time (T = 1) the data output becomes en- (T= 4).
abled; however, the data is not valid until during time

TIME INPUTS OUTPUTS

REFERENCE E Vii A D Q FUNCTION

-1 H X X X Z MEMORY DISABLED
0
1
'- L
X

'-
V
X
X
X
Z
Z
CYCLE
WRITE
BEGINS.
PERIOD
ADDRESSES
BEGINS
ARE LJ'.TCHED

2 L
..r x V Z DATA IS WRITTEN
3 ..r H x X Z WRITE COMPLETED
4 H X X X Z PREPARE FOR NEXT CYCLE (SAME AS -1)
5
"'- X V X Z CYCLE END5. NEXT CYCLE BEGINS (SAME AS 01
The write cycle is initiated by the falling edge of E which posItioning the W pulse at different times within the E
latches the address information into the on chip registers. low time (TELEH). various types of write cycles may be
The write portion of the cycle is defined as both E and IN performed.
being low simultaneously. IN may go low anytime during
the cycle provided that the write enable pulse setup time If the E low time (TELEH) is greater than the W pulse
(TWLEH) is met. The write portion of the cycle is term- (TWLWHI plus an output enable time (TELOX) , a comb-
inated by the first rising edge of either E or IN. Data ination read write cycle is executed. Data may be modified
setup and hold times must be referenced to the terminating an indefinite number of times during any write cycle
signal. (TELEHI. The data input and data output pins may be tied
together for use with a common I/O data bus structure.
If a series of consecutive write cycles are to be performed, When using the RAM in this method allow a minimum of
the IN line may remain low until all desired locations have one output disable time (TWLOZ) after W goes low before
been written. When this method is used, data setup and applying input data to the bus. This will insure that the
hold times must be referenced to the rising edge of E. By output buffers are not active.
m HARRIS HM-6518

Features
• HM-6100COMPATIBLE
• LOW STANDBY POWER 50llW MAX
20mW/MHz MAX
51 vcc
• LOW OPERATING POWER
• FAST ACCESS TIME 180058C MAX E 52
• DATA RETENTION VOLTAGE 2.0 VOLTS MIN AO 0
• TTL COMPATIBLE IN/OUT
A1 W
• HIGH OUTPUT DRIVE - 2 TTL LOADS
A2 A9
• HIGH NOISE IMMUNITY
• ON CHIP ADDRESS REGISTER A3 AS

• TWO CHIP SELECTS FOR EASY ARRAY EXPANSION A4 A7

• THREE STATE OUTPUTS a A6

• MILITARY TEMPERATURE RANGE
GND A5
• INDUSTRIAL TEMPERATURE RANGE
A -ADDRESS INPUT Vi -WRITE ENABLE
E- CH IP ENABLE D -DATA INPUT
S -CHIP SELECT Q -DATA OUTPUT

The HM-6518 is a 1024 by 1 static CMOS RAM fabricated using self-

aligned silicon gate technology. Synchronous circuit design techniques are
employed to achieve high performance and low power operation.

On chip latches are provided for address and data outputs allowing ef-
ficient interfacing with microprocessor systems. The data output buffers
can be forced to a high impedance state for use in expanded memory
arrays.

The HM-6518 is a fully static RAM and may be maintained in any state
for an indefinite period of time. Data retention supply voltage and supply
current are guaranteed over temperature.

All LINES POSITIVE LOGIC - ACTIVE HIGH

THREE STATE BUFFERS,

A HIGH - OUTPUT ACTIVE

DATA LATCH:
LHIGH -Q.,o
a LATCHES ON RISING EDGE OF L

ADDRESS REGISTERS AND DECODERS:

LATCH ON FALLING EDGE OF E
GA.TE ON 'FA.LLING EDGE Of E
 Operating Supply Voltage -vee
Military (-2) 4.5V to 5.5V
Input or Output Voltage Applied (GND -O.3V) Industrial (-9) 4.5V to 5.5V
to (Vee +O.3V)
Operating Temperature
Military (-2) -550e to +1250e
Industrial (-9) -4QOe to +850e

TEMP. & VCC =

OPERATING TEMP. = 250C <D
RANGE VCC = 5.0V
TEST
SYMBOL PARAMETER MIN MAX TYPICAL UNITS CONDITIONS

ICCSB Standby Supply Current 10 0.1 IJ.A 10 = 0

VI = VCC or GND

ICCOP Operating Supply Current ® 4 1.5 mA f = 1MHz, 10 = a

VI = VCC or GND
ICCDR Data Retention Supply Current 5 0.01 IJ.A VCC =2.0,10 = 0
VI = VCC or GND
VCCDR Data Retention Supply Voltage 2.0 1.4 V
E = VCC
II Input Leakage Current -1.0 +1.0 0.0 IJ.A GND ~ VI ~ VCC
10Z Output Leakage Current -1.0 +1.0 0.0 IJ.A GND ~VO~ VCC
VIL Input Low Voltage -0.3 0.8 2.0 V
VIH Input High Voltage VCC -2.0 VCC +0.3 2.0 V
VOL Output Low Voltage 0.4 0.2 V 10 = 3.2mA
VOH Output High Voltage 2.4 4.5 V 10 = -0.4mA
CI Input Capacitance ® 6 4 pF VI = VCC or GND
f = lMHz
CO Output Capacitance ® 10 6 pF VO= VCC or GND
f = lMHz

TELOV Chip Enable Access Time 180 100 ns @

TAVOV Address Access Time 180 90 ns @
TSLOX Chip Select Output Enable Time 20 120 40 ns @)
TWLOX Write Enable Output Disable Time 120 40 ns @
TSHOX Chip Select Output Disable Time 120 40 ns @
TELEH Chip Enable Pulse Negative Width 180 100 ns @
TEHEL Chip Enable Pulse Positive Width 100 50 ns @
TAVEL Address Setup Time 0 -10 ns @
TELAX Address Hold Time 40 20 ns @
TDVWH Data Setup Time 80 30 ns @
TWHDX Oata Hold Time 0 a ns @
TWLSH Chip Select Write Pulse Setup Time 100 50 ns @)
TWLEH Chip Enable Write Pulse Setup Time 100 50 ns @
TSLWH Chip Select Write Pulse Hold Time 100 50 ns
TELWH Chip Enable Write Pulse Hold Time 100 50 ns ~
TWLWH Write Enable Pulse Width 100 50 ns @)
TELEL Read or Write Cycle Time 280 150 ns @

All devices tested at worst case limits. Room temp., 5 volt data provided for information - not guaranteed.
Operating Supply Current (ICCOPl is proportional to Operating Frequency. Example: Typical ICCOP = 1.5mAIMHz.
Capacitance sampled and guaranteed - not 100% tested.
AC Test Conditions: Inputs - TRISE = TFALL = 20nsec; Outputs - CLOAD = 50pF. All timing
measurements at 1 .5V refere~ce level.
 Operating Supply Voltage -VCC
Military (-2) 4.5V to 5.5V
Input or Output Voltage Applied (GND -O.3V) Industrial (-9) 4.5V to 5.5V
to (GND +O.3V)
Operating Temperature
Military (-2) -550C to +1250C
Industrial (-9) -400C to +850C

TEMP. & VCC =

OPERATING TEMP. = 250C <D
RANGE VCC= 5.0V
TEST
SYMBOL PARAMETER MIN MAX TYPICAL UNITS CONDITIONS

ICCSB Standby Supply Current 10 0.1 /.LA 10 = a

VI = VCC or GND
ICCOP Operating Supply Current@ 4 1.5 mA f=1MHz,10=0
VI = VCC or GND
ICCDR Data Retention Supply Current 10 am /.LA VCC = 2.0. 10 = 0
VI = VCC or GND
VCCDR Data Retention Supply Voltage 2.0 1.4 V E= VCC

II Input Leakage Current -1.0 +1.0 0.0 /.LA GND ~ VI ~ VCC

10Z Output Leakage Current -1.0 +1.0 0.0 /.LA GND ~ VO~ VCC
VIL Input Low Voltage -0.3 0.8 2.0 V
VIH Input High Voltage VCC -2.0 VCC +0.3 2.0 V
VOL Output Low Voltage 0.4 0.2 V 10 = 3.2mA
VOH Output High Voltage 2.4 4.5 V 10 = ..(l.4mA

CI Input Capacitance ® 6 4 pF VI = VCC or GND

f = 1MHz
CO Output Capacitance ® 10 6 pF VO= VCC or GND
f = 1MHz

TELQV Chip Enable Access Time 250 110 ns @)

TAVQV Address Access Time 250 100 ns @)
TSLQX Chip Select Output Enable Time 20 160 60 ns @)
TWLQX Write Enable Output Disable Time 160 60 ns @)
TSHQX Chip Select Output Disable Time 160 60 ns @)
TELEH Chip Enable Pulse Negative Width 250 110 ns @)
TEHEL Chip Enable Pulse Positive Width 100 50 ns @)
TAVEL Address Setup Time 0 -10 ns @)
TELAX Address Hold Time 50 30 ns @)
TDVWH Data Setup Time 110 50 ns @)
TWHDX Data Hold Time 0 0 ns @)
TWLSH Chip Select Write Pulse Setup Time 130 60 ns @)
TWLEH Chip Enable Write Pulse Setup Time 130 60 ns @)
TSLWH Chip Select Write Pulse Hold Time 130 60 ns @)
TELWH Chip Enable Write Pulse Hold Time 130 60 ns @)
TWLWH Write Enable Pulse Width 130 60 ns @)
TELEL Read or Write Cycle Time 350 160 ns @)

NOTES: ffi All devices tested at worst case limits.

Operating Supply Current
Room temp., 5 volt data provided
(ICCOP) is proportional to Operating Frequency.
for information
Example:
- i".~t guaranteed.
Typical ICCOP = 1.5mA/MHz.
@ Capacitance sampled and guaranteed - not 100% tested.
@ AC Test Conditions: Inputs - TRISE = TFALL = 20nsec; Outputs - CLOAD = 50pF. All timing
measurements at 1.5V reference level.
 Operating Supply Voltage -VCC
Commercial
(GND -O.3Vl
to (VCC +O.3Vl
Operating Temperature
Commercial

TEMP. & VCC =

OPERATING TEMP. = 250C <D
RANGE VCC = 5.0V
TEST
SYMBOL PARAMETER MIN MAX TYPICAL UNITS CONDITIONS

ICCSB Standby Supply Current 100 10 JJ.A 10 = 0

VI = VCC or GND
ICCOP Operating Supply Current@ 4 1.5 mA f= 1MHz,10=0
VI = VCC or GND

ICCDR Data Retention Supply Current 100 1.0 JJ.A VCC = 2.0, 10 = 0
VI = VCC or GND
E= VCC
VCCDR Data Retention Supply Voltage 2.0 V
II Input Leakage Current -1.0 +1.0 0.0 JJ.A GND ~ VI ~ VCC
10Z Output Leakage Current -1.0 +1.0 0.0 JJ.A GND ~VO~ VCC
VIL Input Low Voltage -0.3 0.8 2.0 V
VIH Input High Voltage VCC -2.0 VCC +0.3 2.0 V
VOL Output Low Voltage 0.4 0.2 V 10 = 1.6mA
VOH Output High Voltage 2.4 4.5 V 10 = -0.2mA
CI Input Capacitance Q) 6 4 pF VI = VCC or GND
f = lMHz
CO Output Capacitance Q) 10 6 pF VO= VCC or GND
f = lMHz

TELQV Chip Enable Access Time 300 160 ns

TAVQV Address Access Time 310 160 ns
~
@)
TSLQX Chip Select Output Enable Time 20 200 60 ns @)
TWLQX Write Enable Output Disable Time 200 60 ns @)
TSHQX Chip Select Output Disable Time 200 60 ns @)
TELEH Chip Enable Pulse Negative Width 300 160 ns @)
TEHEL Chip Enable Pulse Positive Width 150 90 ns @)
TAVEL Address Setup Time 10 0 ns @)
TELAX Address Hold Time 50 30 ns @)
TDVWH Data Setup Time 130 80 ns @)
TWHDX Data Hold Time 0 0 ns @)
TWLSH Chip Select Write Pulse Setup Time 160 100 ns @)
TWLEH Chip Enable Write Pulse Setup Time 160 100 ns @)
TSLWH Chip Select Write Pulse Hold Time 160 100 ns @)
TELWH Chip Enable Write Pulse Hold Time 160 100 ns @)
TWLWH Write Enable Pulse Width 160 100 ns @)
TELEL Read or Write Cycle Time 450 250 ns @)

NOTES, ~ All devices tested at worst case limits. Room temp., 5 volt data provided for information - not guaranteed.
Operating Supply Current (ICCOP) is proportional to Operating Frequency. Example: TypicaliCCOP =- 1.5mA/MHz.
Capacitance sampled and guaranteed - not 100% tested.
@) AC Test Conditions: Inputs - TRISE = TFALL = 20nsec; Outputs - CLOAD = 50pF. All timing
measurements at 1.5V reference level.
 ~----~
I
,
I I
• 5

TIME INPUTS OUTPUT

REFERENCE E §Qlw A D Q FUNCTION

-1 H H X X X Z MEMORY DISABLED
0
1
'- L
X
L
H
H
V
X
X
X
Z
X
CYCLE
OUTPUT
BEGINS,
ENABLED
ADDRESSES ARE LATCHED

2 L L H X X V OUTPUT VALID
3 ..r L H X X V OUTPUT LATCHED
4 H H X X X Z DEVICE DISABLED, PREPARE FOR NEXT CYCLE (SAME AS -1)
5 '- X H V X Z CYCLE ENDS, NEXT CYCLE BEGINS (SAME AS 01

In the HM-6518 read cycle the address information is must be low, W must be high, When E goes high the out-
latched into the on chip registers on the falling edge of E put data is latched into an on chip register. Taking either
(T = 0), Minimum address setup and hold time require- or both 51 or 52 high forces the output buffer to a high
ments must be met, After the required hold time the impedance state. The output data may be re-enabled
addresses may change state without affecting device oper- at any time by taking 51 and 52 low. On the falling edge
ation. In order for the output to be read 51, 52, and E of E the data will be unlatched.

TAVIEL---l TElAX...J

VALID
T"'VEL~
-
NEXT

TElEL TEHEl-=':"':"":;:
I---TEHEL TELEH

Y
TWLEH
'--
TElWH
TWlWH

I----TOVWH_ t---TWHOX
VAllO DATA

HIGHZ

TSLWH
I rwLSH

TIME INPUTS OUTPUT

REFERENCE E W §Ql A D Q FUNCTION

-1 H X X X X Z MEMORY DISABLED
0
1
'- L
X
L
X
L
V
X
X
V
Z
Z
CYCLE
WRITE
BEGINS, ADDRESSES
MODE HAS BEGUN
ARE LATCHED

2 L..r L X V Z DATA IS WRITTEN

3 ..r X X X X Z WAITE COMPLETED
4 H X X X X Z PREPARE FOR NEXT CYCLE (SAME AS-1)
5 ,-X X V X Z CYCLE ENDS. NEXT CYCLE BEGINS (SAME AS 01
The write cycle is initiated by the falling edge of E which By positioning the W pulse at different times within the E
latches the address information into the on chip registers. low time (TELEHl. various types of write cycles may be
The write portion of the cycle is defined as E, W, 51, and performed. If the E low time (TELEH) is greater than the
52 being low simultaneously. W may go low anytime W pulse (TWLWH) plus an output enable time (T5LOXl.
during the cycle provided that the write enable pulse set- a combination read-write cycle is executed. Data may be
up time (TWLEH) is met. The write portion of the cycle modified an indefinite number of times during any write
is terminated by the first rising edge of either E, W, 51 or cycle (TELEH).
52. Data setup and hold times must be referenced to the
terminating signal. The data input and data output pins may be tied together
for use with a common I/O data bus structure. When us-
If a series of consecutive write cycles are to be performed, ing the RAM in this method allow a minimum of one out-
the W line may remain low until all desired locations have put disable time (TWLOZ) after W goes low before apply-
been written. When this method is used data setup and ing input data to the bus. This will insure that the output
hold times must be referenced to the rising edge of E. buffers are not active.
;m HARRIS HM-6551

LOW STANDBY POWER 60/..LWMAX

LOW OPERATING POWER 20mW/MHz MAX
FAST ACCESS TIME 220nNCMAX
DATA RETENTION VOLTAGE 2.0 VOL TS MIN
TTL COMPATIBLE IN/OUT
HIGH OUTPUT DRVIE - 1 TTL LOAD
INTERNAL LATCHED CHIP SELECT
HIGH NOISE IMMUNITY
ON CHIP ADDRESS REGISTERS
LATCHED OUTPUTS
THREE STATE OUTPUTS
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
A - Addre •• Input iN -Write Eneble
E - Chip Eneble D - oete Input
5 - Chip Select a - oete Output
The HM-6551 is a 256 by 4 static CMOS RAM fabricated using self-
aligned silicon gate technology. Synchronous circuit design techniques are
employed to achieve high performance and low power operation.

On chip iatches are provided for addresses and data outputs allowing
efficient interfacing with microprocessor systems. The data output
buffers can be forced to a high impedance state for use in expanded
memory arrays.

The HM-6551 is a fully static RAM and may be maintained in any state
for an indefinite period of time. Data retention supply voltage and supply
current are guaranteed over temperature.

ALL. LINES 'OI111VI LOGIC. ACTIVI HIGH

GATID THfiln ITATlIUP'EfIIl:

.••HIGH _OUTPUT ..,CfIYI
.ow
DICDDIA DATA LATCHES:
LHIQH_a_o
QLATCHEI ON PALLIHG 1001 OF L

GATED

COLUMN DATA

DECCOUI OUf1IUT
AND DATA L.\TCHES
INPUT/OU'f1l'UT

SELECT L.ATCH:
LLow-a-o
Q LATCHES ON RISINQ EDGE OF L

ADDRESS LATCHES AND GATED DECODERS:

LATCH ON FALLING EDGE OF E
OATE ON FALLING EDGE OF E

CAUTION: The •• devices ere •• nsitive to electronic discherge. Proper I.C. hendling procedures should be followed.
2-17
ABSOLUTE MAXIMUM RATINGS
Supply Voltage -(VCC -GNDl -O.3V to +8.0V Operating Supply Voltage -VCC
Military (-2) 4.5V to 5.5V
Applied Input or Output Voltage (GND -O.3V) Industrial (-9) 4.5V to 5.5V
to (GND +O.3V)
Operating Temperature
Military (-2) -550C to +1250C
Industrial (-9) -400C to +850C

TEMP. & VCC~

OPERATING TEMP. = 250C CD
RANGE VCC =5.0V
TEST
SYMBOL PARAMETER MIN MAX TYPICAL UNITS CONDITIONS

ICCSB Standby Supply Current 10 0.1 f.LA 10 = 0

VI ~ VCC or GND
ICCOP Operating Supply Current <6> 4 1.5 mA f=1MHz,10~0
VI = VCC or GND
W= GND
ICCDR Data Retention Supply Current 10 0,01 f.LA VCC ~ 2.0. 10 = 0
VI = VCC or GND
VCCDR Data Retention Supply Voltage 2.0 1.4 V E VCC =
II Input Leakage Current -1.0 +1.0 0.0 f.LA GND~ VI ~ VCC
10Z Output Leakage Current -1.0 +1.0 0.0 f.LA GND~ VO~VCC
VIL Input Low Voltage -0.3 0.8 2.0 V
VIH Input High Voltage VCC -2.0 VCC +0.3 2.0 V
VOL Output Low Voltage 0.4 0.2 V 10 ~ 1.6mA
VOH Output High Voltage 2.4 4.5 V 10 ~ -O.4mA
CI I nput Capacitance@ 6 4 pF VI ~ VCC or GND
f =1MHz
CO Output Capacitance@ 10 6 pF VO= VCC or GND
f ~ 1MHz

TELQV Chip Enable Access Time 220 120 ns ®

TAVQV Address Access Time 220 110 ns ®
TS1LQX Chip Select 1 Output Enable Time 20 130 50 ns ®
TWLQZ Write Enable Output Disable Time 130 50 ns ®
TS1HQZ Chip Select 1 Output Disable Time 130 50 ns ®
TELEH Chip Enable Pulse Negative Width 220 120 ns ®
TEHEL Chip Enable Pulse Positive Width 100 50 ns ®
TAVEL Address Setup Time 0 -10 ns ®
TS2LEL Chip Select 2 Setup Time 0 -10 ns ®
TELAX Address Hold Time 40 20 ns ®
TELS2X Chip Select 2 Hold Time 40 20 ns ®
TDVWH Data Setup Time 100 50 ns ®
TWHDX Data Hold Time 0 0 ns ®
TWLS1H Ch ip Select 1 Write Pu Ise Setup Time 120 60 ns ®
TWLEH Chip Enable Write Pulse Setup Time 120 60 ns ®
TS1LWH Chip Select 1 Write Pulse Hold Time 120 60 ns ®
TELWH Chip Enable Write Pulse Hold Time 120 60 ns ®
TWLWH Write Enable Pulse Width 120 60 ns ®
TELEL Read or Write Cycle Time 320 170 ns ®

NOTES: CD All devices tested at worst case limits. Room temp., 5 volt data provided for information - not guaranteed.
® Operating Supply Current (ICCOP) is proportional to Operating Frequency. Example: Typical lCCOP = 1.5mA/MHz.
@ Capacitance sampled and guaranteed - not 100% tested.
@) AC Test Conditions: Inputs - TRISE ~ TFALL = 20nsec; Outputs - CLOAD ~ 50pF. All timing
measurements at 1.5V reference level.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage -(VCC - GND) -O.3V to +8.0V Operating Supply Voltage -VCC
Military (-2) 4.5V to 5.5V
Applied Input or Output Voltage (GND -O.3V) Industrial (-9) 4.5V to 5.5V
to (VCC +O.3V)
Operating Temperature
Military (-2) -550C to +1250C
Industrial (-9) -400C to +850C

TEMP. & VCC ~

OPERATING TEMP. = 250C CD
RANGE VCC = 5.OV
TEST
SYMBOL PARAMETER MIN MAX TYPICAL UNITS CONDITIONS

ICCSB Standby Supply Current 10 0.1 J.lA 10 ~ 0

VI ~ VCC or GND
ICCOP Operating Supply Current@ 4 1.5 mA f = 1 MHz. 10 ~ 0
..\0 ~ VCC or GND
W = GND
ICCDR Data Retention Supply Current 10 0.Q1 J.lA VCC = 2.0. 10 = 0
VI ~ VCC or GND
VCCDR Data Retention Supply Voltage 2.0 1.4 V E = VCC
II I nput Leakage Current -1.0 +1.0 0.0 J.lA GND~ VI ~ VCC
10Z Output Leakage Current -1.0 +1.0 0.0 J.lA GND~ VO~ VCC
VIL Input Low Voltage -0.3 0.8 2.0 V
VIH Input High Voltage VCC -2.0 VCC +0.3 2.0 V
VOL Output Low Voltage 0.4 0.2 V 10 = 1.6mA
VOH Output High Voltage 2.4 4.5 V 10 ~ -0.4mA
CI I "put Capacitance @ 6 4 pF VI ~ VCC or GND
f = lMHz
CO Output Capacitance @ 10 6 pF VO= VCC or GND
f = 1MHz

TELQV Chip Enable Access Time 300 160 ns @

TAVQV Address Access Time 300 150 ns @
TS1LQX Chip Select 1 Output Enable Time 20 150 60 ns @
TWLQZ Write Enable Output Disable Time 150 60 ns @
TS1HQZ Chip Select 1 Output Disable Time 150 60 ns @
TELEH Chip Enable Pulse Negative Width 300 160 ns @
TEHEL Chip Enable Pulse Positive Width 100 50 ns @
TAVEL Address Setup Time 0 -10 ns @
TS2LEL Chip Select 2 Setup Time 0 -10 ns @
TELAX Address Hold Time 50 30 ns @
TELS2X Chip Select 2 Hold Time 50 30 ns @
TDVWH Data Setup Time 150 100 ns @
TWHDX Data Hold Time 0 0 ns @
TWLS1H Chip Select 1 Write Pulse Setup Time 180 120 ns @
TWLEH Chip Enable Write Pulse Setup Time 180 120 ns @
TS1LWH Chip Select 1 Write Pulse Hold Time 180 120 ns @
TELWH Chip Enable Write Pulse Hold Time 180 120 ns @
TWLWH Write Enable Pulse Width 180 120 ns @
TELEL Read or Write Cycle Time 400 170 ns @

All devices tested at worst case limits. Room temp., 5 volt data provided for information - not guaranteed.
Operating Supply Current OCCOP) is proportional to Operating Frequency. Example: Typical ICCOP =:: 1.5mA/MHz.
Capacitance sampled and guaranteed - not 100% tested.
AC Test Conditions: Inputs - TRISE ~ TFALL ~ 20nsec; Outputs - CLOAD ~ 50pF. All timing
measurements at 1.5V reference level.
 Operating Supply Voltage -VCC
Commercial
(GND -O.3V)
to (GND +O.3VI
Operating Temperature
Commercial

TEMP.& VCC·
OPERATING TEMP.· 260C G)
RANGE VCC·5.0V
TEST
SYMBOL PARAMETER MIN MAX TYPICAL UNITS CONDITIONS

ICCSB Standby Supply Currant 100 10 !J.A 10·0

VI • VCC or GND
ICCOP Oparating Supply Currant @ 4 1.5 mA f· 1MHz. 10·0
VI· VCC or GND
ViI· GND
ICCDR Data Ratantlon Supply Currant 100 1.0 !J.A VCC· 2.0,10·0
VI· VCC or GND
VCCDR Data Retantion Supply Voltage 2.0 1.4 V !. VCC
II Input Leakege Currant -1.0 +1.0 0.0 /-.A GND( VI (VCC
10Z Output Laakaga Currant -1.0 +1.0 0.0 !J.A GND(VO( VCC
VIL Input Low Voltaga -0.3 O.B 2.0 V
VIH Input High Voltege VCC -2.0 VCC +0.3 2.0 V
VOL Output Low Voltaga 0.4 0.2 V 10 ·1.6mA
VoH Output High Voltaga 2.4 4.5 V 10 • -0.2mA
CI Input Capacitence ® 6 4 pF VI· VCC or GND
f·1MHz
CO Output Cepecitenca ® 10 6 pF VO· VCC or GND
f·1MHz

TELQV Chip Enable Acce •• Tima 350 200 ns @

TAVQV Address Access Time 360 200 ns @
TS1LQX Chip Selact 1 Output Enable 1ime 20 180 80 ns @
TWLQZ Writa Enable Output oiseble Time 180 80 ns @
TS1HQZ Chip Select 1 Output Diseble Time 1BO 80 ns @
TELEH Chip Eneble Pulse Negetiva Width 350 200 ns @
TEHEL Chip Enable Pulse Positive Width 150 90 ns @
TAVEL Addre •• Setup Time 10 0 ns @
TS2LEL Chip Salect 2 Setup Tima 10 0 ns @
TELAX Addre •• Hold Time 70 40 ns @
TELS2X Chip Select 2 Hold Tima 70 40 ns @
TDVWH Data Setup Time 170 120 ns @
TWHDX Date Hold Time 0 0 ns @
TWLS1H Chip Salect 1 Write Pulse Setup Time 210 150 ns @
TWLEH Chip Eneble Write Pulse Setup Time 210 150 ns @
TS1 LWH Chip Select 1 Write Pulse Hold Time 210 150 ns @
TELWH Chip Eneble Write Pulse Hold Time 210 150 ns @
TWLWH Write Eneble Pulse Width 210 150 ns @
TELEL Read or Write Cycle Time 500 290 ns @

NOTES: CD All devices tested at worst case limits. Room temp" 5 volt data provided for information - not guaranteed.
Operating Supply Current (ICCOP) is proportional to Operating Frequency. Fxample: Typical ICCOP = 1.5mA/MHz.

~ Capacitance sampled and guaranteed - not 100% tested.

@ AC Test Conditions: Inputs - TRISE ~ TFALL ~ 20nsec; Outputs - CLOAD ~ 50pF. All timing
measurements at 1.5V reference level.
 TlLQ~
TAVQV

a TS1Lax~~ ----------t,---1:::TS1HOz
ii 7ZZ/ZZT~~---------_47/Z§W

TIME INPUTS OUTPUTS

REFERENCE E 51 52 Vii A 0 Q FUNCTION

-1 H H X X X X Z MEMORY DISABLED
0 ",-X L H V X Z ADDRESSES AND 52 ARE LATCHED, CYCLE BEGINS
1 L L X H X X X OUTPUT ENABLED BUT UNDEFINED
2 L L X H X X V DATA OUTPUT VALID
3 fL X H X X V OUTPUTS LATCHED, VALID DATA,52 UNLATCHES
4 H H X X X X Z PREPARE FOR NEXT CYCLE (SAME AS -1)
5 "'-X L H V X Z CYCLE ENDS, NEXT CYCLE BEGINS (SAME AS 0)

The HM-6551 Read Cycle is initiated by the falling edge The HM-6551 has output data latches that are controlled
ofE. This signal latches the input address word and 52 into by E. On the rising edge of E the present data is latched
on chip registers providing that minimum setup and hold and remains in that state until E falls. Also on the rising
times are met. After the required hold time, these inputs edge of E, 52 unlatches and controls the outputs along
may change state without affecting device operation. with ST. Either or both ST or 52 may be used to force the
52 acts as a high order address and simplifies decoding. output buffers into a high impedance state.
For the output to be read, E, 51 must be low and W must
be high. 52 must have been latched low on the falling
edge of E. The output data will be valid at access time
(TELOV).
 TIME INPUTS OUTPUTS
REFERENCE E S1 S2 W A 0 Q FUNCTION

-1 H H X X X X Z MEMORY DISABLED
0 '-X L X V X Z CYCLE BEGINS, ADDRESSES AND S2 ARE LATCHED
1
2
L
L
L
L
X
X
'-
J
X
X
X
V
Z
Z
WRITE
DATA
PERIOD
IN
BEGINS
IS WRITTEN
3 Jx X H X X Z WRITE IS COMPLETED
4 H H X X X X Z PREPARE FOR NEXT CYCLE (SAME AS -1)
5 '-X L X V X Z CYCLE ENDS, NEXT CYCLE BEGINS (SAME AS 0)

In the Write Cycle the falling edge of E latches the ad- times within the E and 51 low time (TELEH) various types
dresses and 52 into on chip registers. S2 must be latched of write cycles may be performed. If the $1 low time
in the low state to enable the device. The write portion of (TS1 LS1 H) is greater than the W pulse plus an output
the cycle is defined as E, W, $1 being low and 52 being enable time (TS1 LOX), a combination read-write cycle
latched low simultaneously. The W line may go low at any is executed. Data may be modified an indefinite number
time during the cycle providing that the write pulse setup of times during any write cycle (TELEH).
times (TWLEH and TWLS1H) are met. The write portion
of the cycle is terminated on the first rising edge of either The HM-6551 may be used on a common I/O bus struct-
E, W, or $1. ure by tying the input and output pins together. The
multiplexing is accomplished internally by the W line.
If a series of consecutive write cycles are to be executed, In the write cycle, when IN goes low, the output buffers
the W line may be held low until all desired locations are forced to a high impedance state. One output disable
have been written. If this method is used, data setup and time delay (TWLOZ) must be allowed before applying
hold times must be referenced to the first rising edge input data to the bus.
of E or 51. By positioning the write pulse at different
 m HARRIS HM-6561

Features
• HM-6100 COMPATIBLE
• LOW STANDBY POWER 50J.lWMAX
• LOW OPERATING POWER 20 mW/MHz MAX
• FAST ACCESS TIME 220nsec MAX
• DATA RETENTION VOLTAGE 2.0 VOL TS MIN
• TTL COMPATIBLE IN/OUT
• HIGH OUTPUT DRIVE - 1 TTL LOAD
• ON CHIP ADDRESS REGISTERS
• COMMON DATA IN/OUT
• THREE STATE OUTPUTS
• EASY MICROPROCESSOR INTERFACING
• MILITARY TEMPERATURE RANGE
• INDUSTRIAL TEMPERATURE RANGE

A - Address Input W- Writa Enable

E- Chip Enable DQ - Data In/Out
S- Chip Select
The HM-6561 is a 256 by 4 static CMOS RAM fabricated using self-
aligned silicon gate technology. Synchronous circuit design techniques are
employed to achieve high performance and low power operation.
On chip latches are provided for address and data outputs allowing ef-
ficient interfacing with microprocessor systems. The data output buffers
can be forced to a high impedance state for use in expanded memory
arrays. The data inputs and outputs are multiplexed internally for com-
mon I/O bus compatibility.
The HM-6561 is a fully static RAM and may be maintained in any state
for an indefinite period of time. Data retention supply voltage and supply
current are guaranteed over temperature.

GAUD
COLU'"
DECODlR
'.0
DATA INfOUT

CAUTION: The •• devices are sensitive to electronic discharge. Proper I.C. handling procedure. should be followed.
2-23
 Operating Supply Voltage -VCC
Military (-2) 4.5V to 5.5V
Input or Output Voltage Applied (GND -O.3V) Industrial (-9) 4.5V to 5.5V
to (VCC +O.3V)
Operating Temperature
Military (-2) -550C to +1250C
Industrial (-9) -400C to +850C

TEMP. & VCC =

OPERATING TEMP. = 25°C <D
RANGE VCC = 5.0V
TEST
SYMBOL PARAMETER MIN MAX TYPICAL UNITS CONDITIONS

ICCSB Standby Supply Current 10 0.1 J.lA 10 = 0

VI = VCC or GND
ICCOP Operating Supply Current@ 4 1.5 mA f = 1MHz, 10 = 0
VI = VCC or GND
W = GND
ICCDR Data Retention Supply Current 10 0.01 J.lA VCC = 2.0, 10 = 0
VI = VCC or GND
VCCDR Data Retention Supply Voltage 2.0 1.4 V E = VCC
II Input Leakage Current -1.0 +1.0 0.0 J.lA GND ~ VI ~VCC
IIOZ Input/Output Leakage Current -1.0 +1.0 0.0 J.lA GND ~VIO~VCC
VIL Input Low Voltage -0.3 0.8 2.0 V
VIH I nput High Voltage VCC -2.0 VCC +0.3 2.0 V
VOL Output Low Voltage 0.4 0.2 V 10 = 1.6mA

VOH Output High Voltage 2.4 4.5 V 10 = -O.4mA

CI Input Capacitance@ 6 4 pF VI = VCC or GND

f = 1MHz
CIO Input/Output Capacitance@ 10 6 pF VIO = VCC or GND
f = 1MHz

TELQV Chip Enable Access Time 220 120 ns @

TAVQV Address Access Time 220 110 ns @
TSLQX Chip Select Output Enable Time 20 120 50 ns @
TWLQZ Write Enable Output Disable Time 120 50 ns @
TSHQZ Chip Select Output Disable Time 120 50 ns @
TELEH Chip Enable Pulse Negative Width 220 120 ns @
TEHEL Chip Enable Pulse Positive Width 100 50 ns @
TAVEL Address Setup Time 0 -10 ns @
TELAX Address Hold Time 40 20 ns @
TDVWH Data Setup Time 100 50 ns @
TWHDX Data Hold Time 0 0 ns @
TWLDV Write Data Delay Time 120 50 ns @
TWLSH Chip Select Write Pulse Setup Time 120 60 ns @
TWLEH Chip Enable Write Pulse Setup Time 120 60 ns @
TSLWH Chip Select Write Pulse Hold Time 120 60 ns @
TELWH Chip Enable Write Pulse Hold Time 120 60 ns @
TWLWH Write Enable Pulse Width 120 60 ns @
TWLSL Early Output High Z Time 0 -10 ns @
TSHWH Late Output High Z Time 0 -10 ns @
TELEL Read or Write Cycle Time 320 170 ns @

NOTES: ~ All devices tested at worst case limits. Room temp., 5 volt data provided for information - not guaranteed.
Operating Supply Current (ICCOPl is proportional to Operating Frequency. Example: TypicaliCCOP = 1.5mA/MHz.
Capacitance sampled and guaranteed - not 100% tested.
@) AC Test Conditions: Inputs - TRISE = TFALL = 20nsec; Outputs - CLOAD = 50pF. All timing
measurements at 1 ,5V reference level.
 Operating Supply Voltage -VCC
Military (-2) 4.5V to 5.5V
Input or Output Voltage Applied (GND -O.3Vl Industrial (-9) 4.5V to 5.5V
to (VCC +O.3Vl
Operating Temperature
Military (-2) -550C to +1250C
Industrial (-9) -400C to +850C

TEMP. & VCC ~

OPERATING TEMP.· 250C CD
RANGE VCC·5.0V
TEST
SYMBOL PARAMETER MIN MAX TYPICAL UNITS CONDITIONS

ICCSB Standby Supply Cu~rant 10 0.1 IJ.A 10 ~ 0

VI· VCC or GND
ICCOP Oparating Supply Currant@ 4 1.5 mA f· 1 MHz. 10·0
Y.I • VCC or GND
W· GND
ICCDR Data Ratantion Supply Currant 10 0.Q1 IJ.A VCC ~2.0, 10 ~ 0
VI • VCC or GND
VCCDR Data Ratantion Supply Voltaga 2.0 1.4 V E· VCC

II ~ Input Leakage Current -1.0 +1.0 0.0 IJA GND ~VI ~ VCC
1I0Z Input/Output Laakaga Currant -1.0 +1.0 0.0 IJ.A GND ~ VIO ~ VCC
VIL I nput Low Voltaga -0.3 0.8 2.0 V
VIH Input High Voltaga VCC -2.0 VCC +0.3 2.0 V
VOL Output Low Voltaga 0.4 0.2 V 10 ·'.SmA
VOH Output High Voltaga 2.4 4.5 V 10 • -0.4mA
CI Input Capacitanca @ 6 4 pF VI • VCC or GND
f - 1MHz
CIO I nput/Output Capacitance@ 10 6 pF VIO- VCC or GND
f = 1MHz

TELQV Chip Enabia Access Time 300 160 ns @

TAVQV Address Access Time 300 150 ns @
TSLQX Chip Select Output Enable Time 20 150 60 ns @
TWLQZ Write Enable Output Disabla Time 150 60 ns @)
TSHQZ Chip Select Output Disabla Time 150 60 ns @
TELEH Chip Enable Pulsa Negative Width 300 160 ns @
TEHEL Chip Enable Pulse Positive Width 100 50 ns @)
TAVEL Address Setup Time 0 -10 ns @
TELAX Address Hold Time 50 30 ns @
TDVWH Data Setup Time 150 100 ns @
TWHDX Data Hold Time 0 0 ns @
TWLDV Write Data Delay Time 150 60 ns @
TWLSH Chip Selact Write Pulse Setup Time 180 120 ns @
TWLEH Chip Enable Write Pulse Setup Time 180 120 os @
TSLWH Chip Select Write Pulse Hold Time 180 120 ns @
TELWH Chip Enable Write Pulse Hold Time 180 120 ns @
TWLWH Write Enable Pulse Width 180 120 ns @
TWLSL Early Output High Z Time 0 -10 ns @
TSHWH Late Output High Z Time 0 -10 ns @
TELEL Read or Write Cycle Time 400 210 ns @

All devices tested at worst case limits. Room temp., 5 vOlt data provided for information - not guaranteed.
Operating Supply Current (ICCOP) is proportional to Operating Frequency. Example: TypicalICCOP: '.5mA/MHz.
Capacitance sampled and guaranteed - not 100% tested.
AC Test Conditions: Inputs - TRISE: TFALL: 20nsec; Outputs - CLOAD: 50pF. All timing
measurements at 1.5V reference level.
 Operating Supply Voltage -VCC
Commercial
(GND ·O.3V)
to (VCC +O.3V)
Operating Temperature
Commercial

TEMP. & VCC=

OPERATING TEMP. = 250C <D
RANGE VCC= 5.0V
TEST
SYMBOL PARAMETER MIN MAX TYPICAL UNITS CONDITIONS

ICCSB Standby Supply Current 100 10 J.l.A 10 = 0

VI = VCC or GND
ICCOP Operating Supply Current@ 4 1.5 mA f= 1 MHz, 10 = 0
yl = VCC or GND
W = GND
ICCDR Data Retention Supply Current 100 1 J.l.A VCC =
2.0, 10 0 =
VI = VCC or GND

VCCDR Data Retention Supply Voltage 2.0 V

E= VCC

II Input Leakage Current -1.0 +1.0 0.0 J.l.A GND ~VI ~VCC
1I0Z Input/Output Leakage Current -1.0 +1.0 0.0 J.l.A GND ~VIO~ VCC
VIL Input Low Voltage -0.3 O.B 2.0 V
VIH I nput High Voltage VCC -2.0 VCC +0.3 2.0 V
VOL Output Low Voltage 0.4 0.2 V 10 = 1.6mA
VOH Output High Voltage 2.4 4.5 V 10 = -0.2mA
CI Input Capacitance@ 6 4 pF VI =
VCC or GND
f= 1MHz
CIO Input/Output Capacitance@ 10 6 pF VIO = VCC or GND
f = 1MHz

TELOV Chip Enable Access Time 350 200 ns @

TAVOV Address Access Time 360 200 ns
TSLOX Chip Select Output Enable Time 20 180 80 ns ~
TWLOZ Write Enable Output Disable Time 1BO 80 ns @)
TSHOZ Chip Select Output Disable Time 180 80 ns @)
TELEH Chip Enable Pulse Negative Width 350 200 ns @
TEHEL Chip Enable Pulse Positive Width 150 90 ns @)
TAVEL Address Setup Time 10 0 ns @)
TELAX Address Hold Time 70 40 ns @
TDVWH Data Setup Time 170 120 ns @
TWHDX Data Hold Time 0 0 ns @)
TWLDV Write Data Delay Time 200 60 ns
TWLSH Chip Select Write Pulse Setup Time 210 150 ns ~
TWLEH Chip Enable Write Pulse Setup Time 210 150 ns @)
TSLWH Chip Select Write Pulse Hold Time 210 150 ns @)
TELWH Chip Enable Write Pulse Hold Time 210 150 ns @)
TWLWH Write Enable Pulse Width 210 150 ns @)
TWLSL Early Output High Z Time 0 -10 ns @
TSHWH Late Output High Z Time 0 -10 ns @)
TELEL Read or Write Cycle Time 500 290 ns @)

NOTES: ~ All devices tested at worst case limits. Room temp .. 5 volt data provided for information - not guaranteed.
Operating Supply Current (ICCOP) is proportional to Operating Frequency. Example: Typical ICCOP = 1.5mA/MHz.
Capacitance sampled and guaranteed - not 100% tested.
@) AC Test Conditions: Inputs - TRISE = TFALL = 20nsec; Outputs - CLOAD = 50pF. All timing
measurements at 1.5V reference level.
 --j TS"QZ

---------4ZT~
t
J
t t
.,

TIME INPUTS OUTPUT

REFERENCE E 51 IN A DO FUNCTION

-1 H H X X Z MEMORY DISABLED
0
1
"'-
L
X
L
H
H
V
X
Z
X
CYCLE
OUTPUT
BEGINS,
ENABLED
ADDRESSES ARE LATCHED

2 L L H X V OUTPUT VALID
3 ..r L H X V OUTPUT LATCHED
4 H H X X Z DEVICE DISABLED, PREPARE FOR NEXT CYCLE (SAME AS -1)
5
"'- X H V Z CYCLE ENDS. NEXT CYCLE BEGINS (SAME AS 0)

The HM-6561 Read Cycle is initiated on the falling edge The HM-6561 has output data latches that are controlled
of E. This signal latches the input address word into on by E. On the rising edge of E the present data is latched
chip registers. Minimum address setup and hold times and remains latched until E falls. Either or both 51 or 52
must be met. After the required hold time, the address may be used to force the output buffers into a high im-
lines may change state without affecting device operation. pedance state.
In order to read the output data E,51 and 52 must be low
and W must be high. The output data will be valid at access
time (TELQV).

TSLWH [TSHWH

TWl$H

&/i///////A\\\\.'\\\\\\

TIME INPUTS
REFERENCE E 51 W A DO FUNCTION

-1 H H X X X MEMORY DISABLED
0
1
"'-L
X
L
X
L
V
X
X
X
CYCLE
WRITE
BEGINS,
PERIOD
ADDRESSES
BEGINS
ARE LATCHED

2 L L ..r X v DATA IN IS WRITTEN

3
..r X H X X WRITE IS COMPLETED
4 H H X X X PREPARE FOR NEXT CYCLE (SAME AS -1)
5
"'- X X V X CYCLE ENDS, NEXT CYCLE BEGINS (SAME AS 0)

NOTES: 1) Device selected only If both S1 and 52 are low. and deselected if either 51 or 52 are high.

2-27
The write cycle begins with the E falling edge latching the guaranteed not to enable at the beginning of the cycle. This
address. The write portion of the cycle is defined by~,"ST, eliminates the concern for data bus conflicts and simplifies
S2 and Vi all being low simultaneously. The write portion data input timing. Data input may be applied as early as
of the cycle is terminated by the first rising edge of any convenient, and TWLDV is ignored. Since W is not used
control line, E, ST, S2 or W. The data setup and data to disable the outputs it can be shorter than in case 1;
hold times (TDVWH and TWHDX) must be referenced to TWLWH is the minimum write pulse. At the end of the
the terminating signal. For eXample, if S2 rises first, data write period, if W rises before either select the outputs will
setup and hold times become TDVS2H and TS2HDX; and enable, reading the data just written. They will not disable
are numerically equal to TDVWH and TWHDX. until either select goes high (TSHQZ).

Data input/output multiplexing is controlled by Vii. Care IF OBSERVE IGNORE

must be taken to avoid data bus conflicts, where the RAM
outputs become enabled when another device is driving Case 1 Both.S1 and S2 = low TWLQZ TWLWH
the data inputs. The following two examples illustrate the before Vi = low TWLDV TWLSL
timing required to avoid bus conflicts. TDVWH TSHWH

Case 2 W = low before both TWLWH TWLQZ

Case 1: Both 51 and 52 fall before W falls. S1 and S2 = low TDVWH TWLDV
If both selects fall before W falls, the RAM outputs will TWLSL
become enabled. Vii is used to disable the outputs, so a TSHWH
disable time (TWLQZ = TWLDV) must pass before any
other device can begin to drive the data inputs. This method If a series of consecutive write cycles are to be performed,
of operation requires a wider write pulse, because TWLDV Viimay remain low until all desired locations are written.
+ TDVWH is greater than TWLWH. In this case TWLSL This is an extension of Case 2.
and TSHWH are meaningless and can be ignored.
Read-Modify-Write cycles and Read-Write-Read cycles
Case 2: Vii falls before both ST and 52 fall. can be performed (extension of Case 1). In fact, data may
be modified as many times as desired with E remaining low.
If one or both selects are high until W falls the outputs are
m HARRIS HM-6504

Pinouts
• LOW POWER STANDBY 125 J.i.W MAX. TOPVIEW

• LOW POWER OPERATION 35mW/MHz MAX.

AO VCC
• EXTREMELY LOW SPEED-POWER PRODUCT
At A6
• DATA RETENTION
A2 A7
• TTL COMPATIBLE INPUT/OUTPUT
A3 AS
• THREE-STATE OUTPUT
A4 A9
• STANDARD JEDEC PINOUT AtO
A5
• FAST ACCESS TIME All
• MILITARY TEMPERATURE RANGE 0

• INDUSTRIAL TEMPERATURE RANGE E

• 18 PIN PACKAGE FOR HIGH DENSITY
TOP VIEW
• ON CHIP ADDRESS REGISTER

• GATED INPUTS-NO PULL UP OR PULL DOWN RESISTORS

REQUIRED

Description
The HM-6504 is a 4096 x 1 static CMOS RAM fabricated using self-
aligned silicon gate technology. The device utilizes synchronous circuitry
to achieve high performance and low power operation.

On chip latches are provided for addresses, data input and data output
allowing efficient interfacing with microprocessor systems. The data
output can be forced to a high impedance for use in expanded memory
arrays. Gated inputs allow lower operating current and also eliminates
the need for pull-up or pull-down resistors. The HM-6504 is a fully A - Addr.ss Input
static RAM and may be maintained in any state for an indefinite period E- Ch ip Enable
of time. W- Write Enable
o- Data Input
Data retention supply voltage and supply current are guaranteed over Q - Data Output
temperature.

LSB,A8
A7

A'
AO
Al
A2

All LINES ACTIVE HIGH - POSITIVE lOGIC

THREE STATE BUfFERS:

A HIGH--OUTPUT ACTIVE

CONTROL AND DATA LATCHES:

lLDW--O-O
Q LATCHES ON RISING EDGe Of L

ADDRESS LATCHES: _
LATCH ON FALLING EDGE OF E

GATED DECODERS:
GATE ON RISING EDGE OF G
Supply Voltage - (VCC -GND) -O.3V to +8.0V Operating Supply Voltage
Input or Output Voltage Applied (GND -O.3V) Military (-2)
to (VCC +O.3V)
Operating Temperature
-650C to +150oC
Military (-2)

• CAUTION: Stresses above those listed under "Absolute Maximum Rati"gI" mey catne permBnent
damage to the device. This is a stress only rating and functiona' operation of the device at these or at any
other conditions above those indicated in the operational sections of this specificlltion is not implied.

TEMP. & VCC· TEMp· 250 cCD

OPERATING VCC·5.0V
RANGE
TEST
SYMBOL PARAMETER MIN MAX TYPICAL UNITS CONDITIONS

50 10 =0
ICCSB Standby Supply Current 5.0 ~A
~. VCC -0.3V

ICCOP Operating Supply Current® 7 5 mA E· 1MHz. 10 = 0

VI' GND

ICCDR Data Retention Supply Current 25 3.0 10 O. VCC·

0
2.0V
~A
~. VCC
VCCDR Data Retention Supply Voltage 2.0 1.4 V
II Input Leakage Current -1.0 +1.0 0.0 ~A GND~VI~VCC
102 Output Leakage Current -1.0 +1.0 0.0 ~A GNO~VO~VCC
VIL Input Low Voltage -0.3 0.8 1.2 V
VIH Input High Voltage VCC VCC 2.2 V
-2.0 +0.3
VOL Output Low Voltage 0.4 0.25 V 10:: 2.0mA

VOH Output High Voltage 2.4 4.0 V 10'" -1.0mA

CI Input Capacitance@) B.O 5.0 pF f'" lMHz

VI '" VCC or GND
CO Output CapacitanceG) 10.0 5.0 pF f'" lMHz
VO'" VCC or GND

TELOV Chip Enable Access Time 120 ns

®
TAVOV Address Access Time 120 ns ®
TELQX Chip Enable Output Enable
Time
10 ns
®
TEHOZ Chip Enable Output Disable
Time
50 n. ®®
TELEH Chip Enable Pulse Negative
Width
120 n. ®
TEHEL Chip Enable Pulse POSitive
Width
50 n. ®
TAVEL Address Setup Time 0 ns ®
TELAX Address Hold Time 40 n. ®
TWLWH Write Enable Pulse Width 20 ns ®
TWLEH Write Enable Pulse Setup Time 70 n. ®
TWLEL Early Write Pulse Setup Time 0 ns ®
TWHEL Write Enable Read Mode
Setup Time
0 n.
®
TELWH Early Write Pulse Hold Time 40 ns ®
TDVWL Data Setup Time 0 n.
®
TDVEL Early Write Data Setup Time 0 ns ®
TWLDX Data Hold Time 25 ns
®
TELDX Earlv Write Data Hold Time 25 n.
®
TOVWL Data Valid to Write Time 0 n. ®
TELEL Read or Write Cycle Time 170 n. ®
All devices tested at worst case limits. Room temp., 5 volt data provided for information - not guaranteed
Operating Supply Current (ICCOP) is proportional to Operating Fraquancy. Example: Typical ICCOP' 5mA/MHz.
Capec;tance samplad and guarantaed - not 100% listed.
AC Test Conditions: Inputs - TRISE· TFALL· 5 nsec; Outputs - CLOAD = 50pF. All timing
measurements at 1 ,5V reference level.
This parameter is guaranteed and not tested. 2-30
Supply Voltage - (VCC -GND) -O.3V to +8.0V Operating Supply Voltage
Input or Output Voltage Applied (GND -O.3V) Industrial (-9)
to (VCC +O.3V)
-650C to +1500C Operating Temperature
Industrial (-9)

* CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress onlv rating and functional operation of the device at these or at any
other conditions above those indicated in the operational sections of this specification is not implied.

TEMP. & VCC· TEMP' 250 CG)

OPERATING VCC· 5.0V
RANGE
TEST
SYMBOL PARAMETER MIN MAX TYPICAL UNITS CONOITIONS

ICCSB 25 3.0 10· 0

Standby Supply Current ~A
E= vcc -0.3V
ICCOP Operating Supply Current0 7 5 mA E' 1MHz, 10 = 0
VI = GNO

ICCDR 15 2.0 VCC· 2.0V 10 = 0

Data Retention Supply Current ~A
~. VCC
VCCDR Data Retention Supply Voltage 2.0 1.4 V
II Input Leakage Current -1.0 +1.0 0.0 ~A GND~VI~VCC
10Z Output leakage Current -1.0 +1.0 0.0 ~A GND~VO~VCC
VIL Input Low Voltage -0.3 0.8 1.2 V
VIH Input High Voltage VCC VCC 2.2 V
-2.0 +0.3
VOL Output Low Voltage 0.4 0.25 V 10;:: 2.0mA

VOH Output High Voltage 2.4 4.0 V IO==-l.OmA

CI Input Capacitance® 8.0 5.0 pF f: 1MHz

VI: VCC or GND

CO Output Capacitance0 10.0 6.0 pF f: 1MHz

VO=- VCC or GND

TELOV Chip Enable Access Time 120 n. CD

TAVOV Address Access Time 120 n. CD
TELQX Chip Enable Output
Time
Enable 10 n. CD
TEHOZ Chip Enable Output
Time
Disable 50 n. CD®
TELEH Chip Enable Pulse Negative
Width
120 n. ®
TEHEL Chip Enable Pulse Positive
Width
50 n. ®
TAVEL Address Setup Time 0 n. CD
TELAX Address Hold Time 40 n. CD
TWLWH Write Enable Pulse Width 20 n. CD
TWLEH Write Enable Pulse Setup Time 70 n. CD
TWLEL Early Write Pulse Setup Time 0 n. CD
TWHEL Write Enable Read Mode
Setup Time
0 n. CD
TELWH Early Write Pulse Hold Time 40 n. CD
TDVWL Data Setup Time 0 n. CD
TDVEL Early Write Data Setup Time 0 n. CD
TWLDX Data Hold Time 25 n.
CD
TELDX Early Write Data Hold Time 25 n. CD
TOVWL Data Valid to Write Time 0 n. CD
TELEL Read or Write Cycle Time 170 n. CD
All devices tested at worst case limits. Room temp., 5 volt data provided for information.- not guaranteed
Operating Supply Current (ICCOP) is proportional to Operating Frequency. Example: Typical ICCOP = 5mA/MHz.
Capacitance sampled and guaranteed - not 100% tested.
AC Test Conditions: Inputs - TRISE = TFALL = 5 nsec; Outputs - CLOAD • 50pF. All timing
measurements at 1.5V reference level.
This parameter is guaranteed and not tested.
Supply Voltage - (VCC -GND) -O.3V to +8.0V Operating Supply Voltage
Input or Output Voltage Applied (GND -O.3V) Military (-2)
to (VCC +O.3V)
-650C to +1500C Operating Temperature
Military (-2)

• CAUTION: Stresses above those listed under uAbsolute Maximum Ratings" may cause permanent
damage to the device. This is a stress only rating and functional operation of the device at these or at any
other conditions above those indicated in the operational sections of this specifjc~tion is not implied.

TEMP. & VCC- TEMP - 250cCD

OPERATING VCC- 5.0V
RANGE
TEST
SYMBOL PARAMETER MIN MAX TYPICAL UNITS CONDITIONS

ICCSB 10-0
Standby Supply Current 50 5.0 ~A ~ = VCC -0.3V

Iceop Operating Supply Current® 7 5 mA E = 1MHz. 10 = 0

VI - GND
VCC • 2.0 V. 10 • 0
ICeDR Data Retention Supply Current 25 3.0 ~A
E- VCC
VCCDR Data Retention Supply Voltage 2.0 1.4 V
Input Leakage Current -1.0 +1.0 0.0 ~A GND~VI~VCC
"
10Z Output Leakage Current -1.0 +1.0 0.0 ~A GND~VO~Vee
VIL Input Low Voltage -0.3 0.8 1.2 V
VIH Input High Voltage vee vec 2.2 V
-2.0 +0.3
VOL Output Low Voltage 0.4 0.25 V 10 = 2.0mA

VOH Output High Voltage 2.4 4.0 V 10 =: -1.0mA

CI Input Capacitance@) 8.0 5.0 pF f'" lMHz

VI:: VCC or GND

CO Output Capacitance@) 10.0 6.0 pF f'" lMHz

VO'" VCC or GND

TELOV Chip Enable Access TIme 200 ns

®
TAVOV Address Access Time 220 ns ®
TELOX Chip Enable Output
Time
Enable 20 ns ®
TEHOZ Chip Enable Output
Time
Disable 80 ns ®®
TELEH Chip Enable Pulse Negative
Width
200 ns ®
TEHEL Chip Enable Pulse Positive
Width
90 ns ®
TAVEL Address Setup Time 20 ns
®
TELAX Address Hold Time 50 ns
®
TWLWH Write Enable Pulse Width 60 ns ®
TWLEH Write Enable Pulse Setup Time 150 ns ®
TWLEL Early Write Pulse Setup Time 0 ns CD
TWHEL Write Enable
Setup Time
Read Mode 0 ns CD
TELWH Early'Write Pulse Hold Time 60 ns ®
TDVWL Data Setup Time 0 ns
®
TDVEL Early Write Data Setup Time 0 ns
®
TWLDX Oata Hold Time 60 ns
®
TELDX Early Write Data Hold Time 60 ns
®
TOVWL Data Valid to Write Time 0 ns ®
TELEL Read or Write Cycle Time 290 ns ®
NOTES: CD All devices tested at worst case limits. Room temp., 5 volt data provided for information.- not guaranteed
Operating Supply Current (ICCOP) is proportional to Operating Frequency. Example: Typical ICCOP = 5mA/MHz.
ffi Capacitance sampled and guaranteed - not 100% tested.

® AC Test Conditions: Inputs - TRISE - TFALL

measurements at 1.5V reference level.
= 10ns; Outputs - CLOAO = 50pF. All timing

® This parameter is guaranteed and not tested. 2-32

Supply Voltage - (VCC -GND) -O.3V to +8.0V Operating Supply Voltage
Input or Output Voltage Applied (GND -O.3V) Industrial (-9)
to (VCC +O.3V)
Operating Temperature
-650C to +150oC
Industrial (-9)

• CAUTION: Stresses above those listed under uAbsolure Maximum Ratings" may cause permanent
damage to the device. This;$ a stress only rating and functional operation of the device at these or at any
other conditions above those indicated in the operational sections of this specification is not implied.

TEMP. 8<vee- TEMP - 250e (j)

OPERATING VCC- 5.0V
RANGE
TEST
SYMBOL PARAMETER MIN MAX TYPICAL UNITS CONDITIONS

ICCSB Standby Supply Current 25 3.0 ~A 10-0

~ - VCC -0.3V
ICCOP Operating Supply Current ® 7 5 mA ~ - 1MHz. 10 c 0
VI- GND
ICCDR Oat8 Retention Supply Current 15 2.0 ~A vce • 2.0V, 10 • 0
~- vec
VeeDR Data Retention Supply Voltage 2.0 1.4 V
Input Leakage Current -1.0 +1.0 0.0 ~A GND~VI ~vec
"
102 Output Leakage Current -1.0 +1.0 0.0 ~A GND~VO~VCe
VIL Input Low Voltage -0.3 0.8 1.2 V
VIH Input High Voltage vee vee 2.2 V
-2.0 +0.3
VOL Output Low Voltage 0.4 0.25 V 10 - 2.0mA
VOH Output High Voltage 2.4 4.0 V 10 - -LOrnA
CI Input Capacitance0 8.0 5.0 pF f; lMHz
VI = VCC or GNO
CO Output Capacitance® 10.0 6.0 pF f= 1MHz
VO • vee or GND

TELOV Chip Enable Access Time 200 ns @

TAVOV Address Access Time 220 ns @
TELOX Chip Enable Output Enable 20 ns @
Time

TEHQ2 Chip Enable Output Disable 80 n. @@

Time

TELEH Chip Enable Pulse Negative 200 n. @

Width

TEHEL Chip Enable Pulse Positive 90 n. @

Width

TAVEL Address Setup Time 20 ns @

TELAX Address Hold Time 50 n. @
TWLWH Write Enable Pulse Width 60 ns 0
TWLEH Write Enable Pulse Setup Time 150 ns 0
TWLEL Earlv Write Pulse Setup Time 0 n. 0
TWHEL Write Enable Read Mode 0 n. @
Setup Time

TELWH Early Write Pulse Hold Time 60 ns 0

TDVWL Data Setup Time 0 ns 0
TDVEL Early Write Data Setup Time 0 n. 0
TWLOX Data Hold Time 60 ns @
TELDX Early Write Data Hold Time 60 ns @
TOVWL Data Valid to Write Time 0 ns ®
TELEL Read or Write Cycle Time 29D n. ®
All devices tested at worst case limits. Room temp., 5 volt data provided for information.- not guaranteed
Operating Supply Current (ICCOP) is proportional to Operating Frequency. Example: Typical ICCOP = SmA/MHz.
Capacitance sampled and guaranteed - not 100% tested.
AC Test Conditions: Inputs - TR ISE = TFALL = 10nsec; Outputs - CLOAD = 50pF. All timing
measurements at 1.5V reference level.

This parameter is guaranteed and not tested. 2-33

Supply Voltage - (VCC -GND) -O.3V to +8.0V Operating Supply Voltage
Input or Output Voltage Applied (GND -O.3V) Military (-2)
to (VCC +O.3V)
Operating Temperature
Storage Temperature -650C to +1500C
Military (-2)

• CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress only rating and functional operation of the device at these or at any
other conditions above those indicated in the operational sections of this specification is not implied.

TEMP. & VCC = TEMp::c250CG)

OPERATING VCC= 5.0V
RANGE
TEST
SYMBOL PARAMETER MIN MAX TYPICAL UNITS CONDITIONS

10' 0
ICCSB Standby Supply Current 50 5.0 pA
E= VCC-O.3V

E= lMHz, 10 ""0
ICCOP Operating Supply Current(3) 7 5 mA
VI"" GND

VCC ""2.QV, 10 = 0
ICCDR Data Retention Supply Current 25 3.0 pA
~>VCC
VCCDR Data Retention Supply Voltage 2.0 1.4 V

II Input Leakage Current -1.0 +1.0 0.0 pA GND:SVI~VCC

10Z Output Leakage Current -1.0 +1.0 0.0 pA GND:5VO:5VCC

VIL Input Low Voltage -0.3 08 1.2 V

Input High Voltage VCC VCC 2.2 V

VIH
-2.0 +03
VOL Output Low Voltage 04 0.25 V 10'" 2.0mA

VOH Output High Voltage 2.4 4.0 V 10'" -1.0mA

CI Input Capacitance® 8.0 5.0 pF f'" lMHz

VI '" VCC or GND

CO Output Capacitance0 10.0 6.0 pF f= lMHz

VO '" VCC or GND

TELQV Chip Enable Access Time 300 ns

CD
TAVQV Address Access Time 320 ns CD
TELQX Chip Enable Output
Time
Enable 20 ns CD
TEHQZ Chip Enable Output
Time
Disable 100 ns
CD®
TELEH ChIp Enable Pulse Negative
Width
300 ns CD
TEHEL Chip Enable Pulse Positive
Width
120 ns CD
TAVEL Address Setup Time 20 ns CD
TELAX Address Hold Time 50 ns CD
TWLWH Write Enable Pulse Width 80 ns CD
TWLEH Write Enable Pulse Setup Time 200 ns CD
TWLEL Early Write Pulse Setup Time 0 ns CD
TWHEL Write Enable
Setup Time
Read Mode 0 ns CD
TELWH Early Write Pulse Hold Time 80 ns
CD
TDVWL Data Setup Time 0 ns
CD
TDVEL Early Write Data Setup Time 0 ns
CD
TWLDX Data Hold Time 80 ns
CD
TELDX Early Write Data Hold Time 80 ns
CD
TQVWL Data Valid to Write Time 0 ns 0
TELEL Read or Write Cycle Time 420 ns CD
NOTES: <D All devices tested at worst case limits. Room temp., 5 volt data provided for information.- not guaranteed
Operating Supply Current (ICCOP) is proportional to Operating Frequency. Example: Typical ICCOP = 5mA/MHz.

~ Capacitance sampled and guaranteed - not 100% tested.

@) AC Test Conditions: Inputs - TRISE = TFALL = 10nsec; Outputs - CLOAD = 50pF. All timing
measurements at 1.5V reference level.

® This parameter is guaranteed and not tested.

Supply Voltage - (VCC -GND) -O.3V to +8.0V Operating Supply Voltage
Industrial (-9)
Input or Output Voltage Applied (GND -O.3V)
to (VCC +O.3V)
Operating Temperature
Storage Temperature -650C to +150oC
Industrial (-9)

• CAUTION: Stresses above those listed under NAbso/ute Maximum Ratings" may cause permanent
damage to the device. This is a stress only rating and functional operation of the device at these or at any
other conditions above those indicated in the operational sections of this specification is not implied.

TEMP. & VCC: TEMP = 250CG)

OPERATING VCC = 5.0V
RANGE
TEST
SYMBOL PARAMETER MIN MAX TYPICAL UNITS CONDITIONS

25
10'" 0, F. =: VCC-O.3V
ICCSB Standby Supply Current 3.0 ~A

E'" lMHz, 10 =: 0
ICCOP Operating Supply Current0 7 5 mA
VI "'GND

V_CC = 2.0V, 10 = 0
ICCDR Data Retention Supply Current 15 2.0 ~A
E = VCC
VCCDR Data Retention Supply Voltage 2.0 1.4 V

Input Leakage Current -1.0 +1.0 GND~VI~VCC

"
10Z Output Leakage Current -1.0 +1.0
0.0

0.0
~A

~A GND~VO~VCC

VIL Input Low Voltage -0.3 0.8 1.2 V

VIH Input High Voltage VCC VCC 2.2 V

-2.0 +0.3
VOL Output Low Voltage 04 0.25 V 10'" 2.0mA

VOH Output High Voltage 2.4 4.0 V 10'" -1.0mA

CI Input Capacitance® B.O 5.0 pF f'" lMHz

VI '" VCC or GND

CO Output Capacitance0 10.0 6.0 pF f'" lMHz

va", VCC or GND

TELQV Chip Enable Access Time 300 ns

®
TAVQV Address Access Time 320 ns @
TELQX Chip Enable Output
Time
Enable 20 ns
®
TEHQZ Chip Enable Output Disable 100 ns @®
Time

TELEH Chip Enable Pulse Negative 300 ns @

Width

TEHEL Chip Enable Pulse Positive 120 ns @

Width

TAVEL Address Setup Time 20 ns @

TELAX Address Hold Time 50 ns @
TWLWH Write Enable Pulse Width BO ns
®
TWLEH Write Enable Pulse Setup Time 200 ns @
TWLEL Early Write Pulse Setup Time 0 ns ®
TWHEL Write Enable
Setup Time
Read Mode 0 ns
®
TELWH Early Write Pulse Hold Time 80 ns
®
TDVWL Data Setup Time 0 ns @
TDVEL Early Write Data Setup Time 0 ns @
TWLDX Data Hold Time 80 ns @
TELDX Early Write Data Hold Time BO ns
®
TQVWL Data Valid to Write Time 0 ns ®
TELEL Read or Write Cycle Time 420 ns ®
NOTES: <D All devices tested at worst case Iimits. Room temp., 5 volt data provided for information.- not guaranteed
Operating Supply Current (lCCOP) is proportional to Operating Frequency. Example: Typical ICCOP::: 5mA/MHz.

~ Capacitance sampled and guaranteed - not 100% tested.

@) AC Test Conditions: Inputs - TRISE::: TFALL::: 10nsec; Outputs - CLOAD::: 50pF. All timing
measurements at 1.5V reference level.

® This parameter is guaranteed and not tested.

Supply Voltage - (VCC -GND) -O.3V to +8.0V Operating Supply Voltage
Input or Output Voltage Applied (GND -O.3V) Industrial (-9)
to (VCC +O.3V)
Operating Temperature
Storage Temperature -650C to +1500C
Industrial (-9)
• CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may CBUse permanent
damage to the device. This is a stress only fsting and functional operation of the device at these or at any
other conditions above those indicated in the operational sections of this specification is not implied.

TEMP. & VCC' TEMP· 25o CG)

OPERATING VCCa 5.0V
RANGE
TEST
SYMBOL PARAMETER MIN MAX TYPICAL UNITS CONDITIONS

10 = 0 E= VCC-0.3v
ICCS8 Standby Supply Current 100 20 ~A

ICCOP Operating Supply Current® 7 5 mA

En lMHz, JO;; 0
VI = GND
VCC • 2.0\$10 = 0
ICCDR Data Retention Supply Current 50 12 ~A
E' VCC
VCCDR Data Retention Supply Voltage 2.0 1.4 V
II Input Leakage Current -1.0 +1.0 0.0 ~A GND~VI~VCC
10Z Output Leakage Current -1.0 +1.0 0.0 ~A GND~VO~VCC
Vil Input Low Voltage -0.3 0.8 1.2 V
VIH Input High Voltage VCC vcc 2.2 V
-2.0 +0.3
VOL Output Low Voltage 0.4 0.25 V 10 = 2.0mA
VOH Output High Voltage 2.4 4.0 V 10'" -1.0mA

CI Input Capacitance® 8.0 5.0 pF f'" lMHz

VI •• VCC or GND

CO Output Capacitance® 10.0 6.0 pF f'" lMHz

va = VCC 0' GND

TElaV Chip Enable Access Time 300 ns

0
TAVOV Address Access Time 320 ns
0
TElOX Chip Enable Output
Time
Enable 20 ns CD
TEHOZ Chip Enable Output
Time
Disable 100 ns 0®
TElEH Chip Enable Pulse Negative
Width
300 ns 0
TEHEl Chip Enable Pulse Positive
Width
120 ns 0
TAVEL Address Setup Time 20 ns
0
TElAX Address Hold Time 50 ns
0
TWlWH Write Enable Pulse Width 80 ns 0
TWlEH Write Enable Pulse Setup Time 200 ns 0
TWlEl Early Write Pulse Setup Time 0 ns 0
TWHEl Write Enable
Setup Time
Read Mode 0 ns
0
TELWH Early Write Pulse Hold Time 80 ns CD
TDVWL Data Setup Time 0 ns
0
TDVEl Early Write Data Setup Time 0 ns
0
TWlDX Data Hold Time 80 ns
0
TElDX Early Write Data Hold Time 80 ns
0
TaVWl Data Valid to Write Time 0 ns 0
TELEl Read or Write Cycle Time 420 ns 0
NOTES; <D All devices tested at worst case limits. Room temp., 5 volt data provided for information.- not guaranteed
Operating Supply Current (ICCOP) is proportional to Operating Frequency. Example: Typical ICCOP = SmA/MHz.

~ Capacitance samplad and guaranteed - not 100% tested.

@ AC Test Conditions: Inputs - TRISE = TFALL = 10nsec; Outputs - CLOAD = SOpF. All timing
measurements at 1.5V reference level.

® This parameter is guaranteed and not tested.

Supply Voltage - (VCC -GND) -O.3V to +8.0V Operating Supply Voltage
Commercial
Input or Output Voltage Applied (GND -O.3V)
to (VCC +O.3Vl
Storage Temperature -650C to +1500C

• CAUTION: Stresses above those listed under uAbsolute Maximum Ratings U

may cause permanent

damage to the device. This is a stress only rating and functional operation of the device at these or at any
other conditions above those indicated in the operational sections of this specification is not implied.

TEMP. & VCC· TEMP:: 250cCD

OPERATING VCC= 5.0V
RANGE
TEST
SYMBOL PARAMETER MIN MAX TYPICAL UNITS CONDITIONS

ICCSB Standby Supply Current 350 50 ~A

10' O.E· VCC-0.3V

ICCOP Operating Supply Current(3) 7 5 mA

E"" lMHz, 10 '" 0
VI", GND

VCC • 2.0V. 10 • 0
ICCoR Data Retention Supply Current 200 30 ~A
E= VCC
VCCoR Data Retention Supply Voltage 2.0 1.4 V

II Input Leakage Current -10.0 +10.0 ±O.S ~A GND~VI~VCC

10Z Output Leakage Current -10.0 +10.0 iO.S ~A GND~VO~VCC

VIL Input Low Voltage -0.3 08 1.2 V

VCC VeL 2.2 V
VIH Input High Voltage
-2.0 +0.3
VOL Output Low Voltage 04 0.25 V 10 = 2.0mA

VOH Output High Voltage 2.4 4.0 V 10 = -1.0mA

CI Input Capacitance® 80 5.0 pF f = lMHz

VI = VCC or GND

CO Output Capacitance0 10.0 6.0 pF f = lMHz

VO'" VCC or GND

TELOV Chip Enable Access Time 350 ns

0
TAVOV Address Access Time 370 ns 0
TELQX Chip Enable Output
Time
Enable 20 ns 0
TEHOZ Chip Enable Output
Time
Disable 100 ns 0®
TELEH Chip Enable Pulse Negative
Width
350 ns 0
TEHEL Chip Enable Pulse Positive
Width
150 ns 0
TAVEL Address Setup Time 20 ns
0
TELAX Address Hold Time 50 ns ®
TWLWH Write Enable Pulse Width 100 ns 0
TWLEH Write Enable Pulse Setup Time 250 ns
0
TWLEL Early Write Pulse Setup Time 0 ns ®
TWHEL Write Enable
Setup Time
Read Mode 0 ns
®
TELWH Early Write Pulse Hold Time 100 ns
0
TDVWL Data Setup Time 30 ns
0
TDVEL Early Write Data Setup Time 30 ns
0
TWLDX Data Hold Time 100 ns
0
TELoX Early Write Data Hold Time 100 ns
0
TOVWL Data Valid to Write Time 0 ns 0
TELEL Read or Write Cycle Time 500 ns 0
NOTES: CD All devices tested at worst case limits. Room temp., 5 volt data provided for information - not guaranteed
Operating Supply Current OCCOP) is proportional to Operating Frequency. Example: Typical ICCOP = 5mA/MHz.
ffi@) Capacitance sampled and guaranteed - not 100% tested.
AC Test Conditions: Inputs - TRISE = TFALL;;:; 10nsec; Outputs - CLOAD = 50pF. All timing
measurements at 1.5V reference level.

® This parameter is guaranteed and not tested.

 TIME INPUTS OUTPUT FUNCTION
REFERENCE E W A a
-1 H X X Z MEMORY DISABLEO
a H V Z CYCLE BEGINS. ADDRESSES ARE LATCHED'
1 L H X X OUTPUT ENABLED
Z ""-L H X V OUTPUT VALID
3 .r H x V READ ACCOMPLISHED
4 H X X Z PREPARE FOR NEXT CYCLE ISAME AS-1I
5 '- H V Z CYCLE ENDS. NEXT CYCLE BEGINS (SAME AS 01

The address information is latched in the on chip registers becomes enabled but data is not valid until during time
on the falling edge of E (T = 0). Minimum address set up (T = 2). W must remain high until after time (T = 2).
and hold time requirements must be met. After the requir- After the output data has been read, E may return high
ed hold time, the addresses may change state without (T = 3). This will disable the output buffer and all inputs
affecting device operation. During time (T = 1) the output and ready the RAM for the next memory cycle (T = 4).

;;

~DV'"T'"DX~
o DATA VALID IIXT DATA

TIME INPUTS OUTPUT FUNCTION

REFERENCE E W A 0 0

-1 H X X X Z MEMORY DISABLED
0
1
'-L L
X
V
X
V
X
Z
Z
CYCLE BEGINS. ADDRESSES ARE LATCHED
WRITE IN PROGRESS INTERNALLY
2 .r X X X Z WRITE COMPLETED
3 H X X X Z PREPARE FOR NEXT CYCLE (SAME AS-1I
4 '- L V V Z CYCLE ENDS. NEXT CYCLE BEGINS {SAME AS 0'

The early write cycle is the only cycle where the output is will remain in that state until E returns high (T = 2). For
guaranteed not to become active. On the falling edge of this cycle, the data input is latched by E going low; there-
r (T = 0), the addresses, the write signal, and the data fore data set up and hold times should be referenced to E.
input are latched in on chip registers. The logic value of Vii When E (T = 2) returns to the high state the output buffer
at the time E falls determines the state of the output buffer and all inputs are disabled and all signals are unlatched. The
for that cycle, Since W is low when r
falls, the out- device is now ready for the next cycle.
put buffer is latched into the high impedance state and

2-38
 TIME INPUTS OUTPUT FUNCTION
REFERENCE "[ Vi A 0 0

, H X X X Z MEMORY DISABLE D

,
0
'- H V X Z CYCLE BEGINS, ADDRESS ARE LATCHED

, l

l
H

H
X

X
X

X
X

V
OUTPUT ENABLED
OUTPUT VALID. READ AND MODIFY TIME

,
3 l

l
'-X
X

X
V

X
V

V
WRITE BEGINS. DATA IS LATCHED
WRI!E IN PROGRESS INTERNALL Y
5 of X X X V WRITE COMPLETED
6 H X X X Z PREPARE FOR NEXT CYCLE (SAME AS -11
7 '- H V X Z CYCLE ENOS, NEXT CYCLE BEGINS (SAME AS OJ

The read modify write cycle begins as all other cycles on IN signal also latches itself on its low going edge. All input
the falling edge of E (T ; 0). The IN line should be high at signals excluding E have been latched and have no further
(T ; 0) in order to latch the output buffers in the active effect on the RAM. The rising edge of E (T ; 5) completes
state. During (T ; 11 the output will be active but not the write portion of the cycle and unlatches and disables all
valid until (T ; 21. On the falling edge of the IN (T ; 3) inputs and output. The output goes to a high impedance
the data present at the output and input are latched. The and the RAM is ready for the next cycle.

TIME INPUTS OUTPUT

REFERENCE r Vi A 0 0 j:UNCTION

.' H
"\.
X X X Z MEMORY DISABLED
0 H V X Z CYCLE BEGINS ADDRESSES ARE LATCHED

,
I l "\. X V X WRITE BEGINS DATA IS LATCHF.O
l H X X X WRITE IN PROGRESS INTERNALL Y
3 .f H X X x WRITE COMPLETED
, H X X X Z PREPARE j:QR NEXT CYCLE ISAME AS ~1f
"\.
5 H V X Z CYCLE ENDS. NEXT CYCLE BEGINS lSAME AS Ol

The late write cycle is a cross between the early write write is between these two cases. With this cycle the
cycle and the read-modify-write cycle. output may become active, and may become valid data, or
may remain active but undefined. Valid data is written
Recall that in the early write the output is guaranteed to into the RAM if data setup, data hold, write setup and
remain high impedance, and in the read-modify-write write pulse widths are observed.
the output is guaranteed valid at access time. The late
m HARRIS
HM-6514
1024 x 4 CMOS RAM
Pinouts
TOPVIEW
• LOW POWER STANDBY 12&JlWMAX.
• LOW POWER OPERATION 35mW/MHz MAX. A6 vcc
• DATA RETENTION @2.0VMIN. A7

• TTL COMPATIBLE INPUT/OUTPUT A' A8

• COMMON DATA IN/OUT A3 A9

• THREE-STATE OUTPUTS AD DOO

• STANDARD JEOEC PINOUT
Al DOl
• FAST ACCESS TIME
D02
• MILITARY TEMPERATURE RANGE
E D03
• INDUSTRIAL TEMPERATURE RANGE
Vi
• 18 PIN PACKAGE FOR HIGH DENSITY
• ON-CHIP ADDRESS REGISTER TOP VIEW
• GATED INPUTS-NO PULL UP OR PULL DOWN RESISTORS REQUI RED
A7
D.escription
The HM-6514 is a 1024 x 4 static CMOS RAM fabricated using self A4 A8
aligned silicon gate technology. The device utilizes synchronous circuitry
to achieve high performance and low power operation. A3 A9

AO 000
On-chip latches are provided for the addresses allowing efficient inter-
facing with microprocessor systems. The data output can be forced to Al DOl
a high impedance state for use in expanded memory systems. Gated
A2 DQ2
inputs allow low operating current and also eliminates the need for pull-
up or pulldown resistors.

The HM-6514 is a fully static RAM and may be maintained in any state
E GND W 003
for an indefinite period of time. Data retention supply voltage and supply A - Address Input
current are guaranteed over temperature. E.. -Chip Enable
W - Write Enable
DO - Data In/Out

LSB 11.9

A'
A1

A6

A5

A'

GATED COLUMN
DECOOER
AND
DATA
INPUT/OUTPUT

ALL liNes ACTIVE HIGH - POSITIVE LOGIC

THREE STAT( BUFFERS:

A HIGH--OUTPUT ACTIVE

ADDRESS lATCHES:
LATCH ON FALLING EDGE OFE

GATED DECODERS:
GATE ON RISING EDGE OF G
Supply Voltage - (VCC - GND) -O.3V to +8.0V Operating Supply Voltage
Military (-2)
Input or Output Voltage Applied (GND -O.3V)
to (VCC +O.3V) Operating Temperature
Storage Temperature -65°C to +1500C Military (-2)

* CAUTION: Stresses above those listed under "Absolute Maximum Ratin{}$" msy CBUse permanent
damage to the device. This;s a stress only rating and functional operation of the device at these or at any
other conditions above those indicated in the operational sections of this specification ;s not implied.

TEMP. 8<VCC' TEMP' 250CG)

OPERATING VCC· 5.0V
RANGE
TEST
SYMBOL PARAMETER MIN MAX TYPICAL UNITS CONDITIONS

ICCSB Standby Supply Current 50 5.0 IJA 10-0

E' VCC-0.3V
ICCOP Operating Supply Current ® 7 5 mA E' lMHz.IO =0
VI' GNO
ICCDR Data Retention Supply Current 25 3.0 IJA VCC· 2.0V.10 = 0
£. VCC
VCCDR Data Retention Supply Voltage 2.0 1.4 V
II Input Leakage Current -1.0 +1.0 0.0 IJA GND ~ VI ~VCC
1I0Z Input/Output Leakage Current -1.0 +1.0 0.0 IJA GND~VIO~VCC
VIL Input Low Voltage -0.3 O.B 1.2 V
VIH Input High Voltage VCC VCC 2.2 V
-2.0 +0.3
VOL Output Low Voltage 0.4 0.25 V 10 = 2.0mA
VOH Output High Voltage 2.4 4.0 V 10' -1.0mA
CI Input Capacitance® B.O 5.0 pF VI • VCC or GND
f· lMHz
CIO Input/Output Capacitance@) 10.0 6.0 pF VIO' VCC or GND
f· lMHz

TELQV Chip Enable AccessTime 120 ns 0

TAVQV AddressAccessTime 120 n. 0
TELQX Chip Enable Output Enable
Time
10 n. 0
lWLQZ Write Enable Output Disable
Time
50 n. 0®
TEHQZ Chip Enable Output Disable
Time
50 n. 0®
TELEH Chip Enable PulseNegative
Width
120 n. 0
TEHEL Chip Enable PulsePositive
Width
50 n. 0
TAVEL AddressSetup Time 0 n. 0
TELAX AddressHold Time 40 no 0
lWLWH Write Enable PulseWidth 120 n. 0
TWLEH Write Enable PulseSetup Time 120 no 0
TELWH Write Enable Pulse Hold Time 120 n. 0
TDVWH Data Setup Time 50 n. 0
lWHDX Data Hold Time 0 n.
lWLDV Write Data Delay Time 70 n. ffi
lWLEL Early Output High-Z Time 0 n. 0
TEHWH Late Output High-Z Time 0 n. 0
TELEL Read or Write Cycle Time 170 n. 0
All devices tested at worst case limits. Room Temp., 5V data provided for information - not guaranteed
Operating Supply Current lICCOPI is proportional to Operating Frequency. Ex: TypicaliCCOP = SmA/MHz.
Capacitance sampled and guaranteed - not 100% tested.
AC test conditions: Inputs - TRISE = TFALL = 5ns; Output - CLOAO = 50pF. All timing measured at
1 .5 V reference level.
This parameter is guaranteed and not tested.
Supply Voltage - (VCC - GND) -O.3V to +8.0V Operating Supply Voltage
Industrial (-9)
Input or Output Voltage Applied (GND -O.3V)
to (VCC +O.3V)

Operating Temperature
Industrial (-9)

* CAUTION: Stresses above those listed under uAbsolute Maximum Ratings" may cause permanent
damage to the device. This is a stress only rating and functional operation of the device at these or at any
other conditions above those indicated in the operational s3ct;ons of this specification is not implied.

TEMP. & VCC- TEMP = 250CG)

OPERATING VCC- 5.0V
RANGE
TEST
SYMBOL PARAMETER MIN MAX TYPICAL UNITS CONDITIONS

ICCSB Standby Supply Current 25 3.0 ~A 10- 0

E = VCC -0.3V
ICCOP Operating Supply Current 0 7 5 mA E - lMHz. 10 = 0
VI = GND
ICCDR Data Retention Supply Current 15 2.0 ~A VCC = 2.0V.10 =0
E = VCC
VCCDR Data Retention Supply Voltage 2.0 1.4 V
II Input Leakage Current -1.0 +1.0 0.0 ~A GNDS VI SVCC
IIOZ Input/Output Leakage Current -1.0 +1.0 0.0 ~A GNDSVIOSVCC
VIL Input Low Voltage -0.3 O.B 1.2 V
VIH Input High Voltage VCC VCC 2.2 V
-2.0 +0.3
VOL Output Low Voltage 0.4 0.25 V 10 = 2.0mA
VOH Output High Voltage 2.4 4.0 V 10 = -1.0mA
CI Input Capacitance® 8.0 5.0 pF VI = VCC or GND
f'" 1MHz
CIO Input/Output Capacitance@) 10.0 6.0 pF VIO = VCC or GND
f = lMHz

TELOV Chip Enable Access Time 120 ns 0

TAVOV Address Access Time 120 ns 0
TELOX Chip Enable
Time
Output Enable 10 ns 0
TWLOZ Write
Time
Enable Output Disable 50 ns 0®
TEHOZ Chip Enable
Time
Output Disable 50 ns 0®
TELEH Chip Enable
Width
Pulse Negative 120 ns 0
TEHEL Chip Enable
Width
Pulse Positive 50 ns 0
TAVEL Address Setup Time 0 ns 0
TELAX Address Hold Time 40 ns 0
TWLWH Write Enable Pulse Width 120 ns 0
TWLEH Write Enable Pulse Setup Time 120 ns 0
TELWH Write Enable Pulse Hold Time 120 ns 0
TDVWH Data Setup Time 50 ns 0
TWHDX Data Hold Time 0 ns
TWLDV Write Data Delay Time 70 ns ffi
TWLEL Early Output H igh-Z Time 0 ns 0
TEHWH Late Output High-Z Time 0 ns 0
TELEL Read or Write Cycle Time 170 ns 0
All devices tested at worst case limits. Room Temp., 5V data provided for information - not guaranteed
Operating Supply Current (ICCOP) is proportional to Operating Frequency. Ex: Typical ICCOP = SmA/MHz.
Capacitance sampled and guaranteed - not 100% tested.
AC test conditions: Inputs - TRISE = TFALL = 5ns; Output - CLOAD = 50pF. All timing measured at
1.5V reference level.
This parameter is guaranteed and not tested.
2-42
Supply Voltage - (VCC -GND) -O.3V to +8.0V Operating Supply Voltage
Military (-2)
Input or Output Voltage Applied (GND -O.3V)
to (VCC +O.3V)
Operating Temperature
-650C to + 1500C
Military (-2)

• CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This;s a stress only rating and functional operation of the device at these or at any
other conditions above those indicated in the operational sections of this specification ;s not implied.

TEMP. & VCC = TEMP = 250 cCD

OPERATING VCC· 5.0V
RANGE
TEST
SYMBOL PARAMETER MIN MAX TYPICAL UNITS CONDITIONS

ICCSB Standby Supply Current 50 5.0 IJA 10= 0

E = VCC -0.3V
ICCOP Operating Supply Current 0 7 5 mA E=lMHz, 10=0
VI = GND
ICCDR Data Retention Supply Current 25 3.0 IJA VCC = 2.0V.10 = 0
E = VCC
VCCDR Data Retention Supply Voltage 2.0 1.4 V
II Input Leakage Current -1.0 +1.0 0.0 IJA GNDSVISVCC
IIOZ Input/Output Leakage Current -1.0 +1.0 0.0 IJA GNDSVIOSVCC
VIL Input low Voltage -0.3 0.8 1.2 V
VIH Input High Voltage VCC VCC 2.2 V
-2.0 +0.3
VOL Output Low Voltage 0.4 0.25 V 10 = 2.0mA
VOH Output High Voltage 2.4 4.0 V 10' -LOrnA
CI Input Capacitance® 8.0 5.0 pF VI = VCC or GND
f= lMHz
CIO Input/Output Capacitance@ 10.0 6.0 pF VIO = VCC or GND
f = lMHz

TELOV Chip Enable Access Time 200 ns 0

TAVOV Address Access Time 220 ns 0
TELOX Chip Enable
Time
Output Enable 20 ns 0
TWLOZ Write
Time
Enable Output Disable 80 ns ®@
TEHOZ Chip Enable
Time
Output Disable BO ns ®@
TELEH Chip Enable
Width
Pulse Negative 200 ns 0
TEHEL Chip Enable
Width
Pulse Positive 90 ns 0
TAVEL Address Setup Time 20 ns 0
TELAX Address Hold Time 50 ns
0
TWLWH Write Enable Pulse Width 200 ns
0
TWLEH Write Enable Pulse Setup Time 200 ns 0
TELWH Write Enable Pulse Hold Time 200 ns 0
TDVWH
TWHDX
Data Setup

Data Hold
Time

Time
120 ns 0
0 ns
TWLDV Write Data Delay Time BO ns ffi
TWLEL Early Output High-Z Time 0 ns 0
TEHWH Late Output High-Z Time 0 ns 0
TELEL Read or Write Cycle Time 290 ns 0
All devices tested at worst case limits. Room Temp., 5V data provided for information - not guaranteed
Operating Supply Current (ICCOP) is proportional to Operating Frequency. Ex: Typical ICCOP = 5mA/MHz.
Capacitance sampled and guaranteed - not 100% tested.
AC test conditions: Inputs - TRISE =: TFALL = 10ns; Output - CLOAD = 50pF. All timing measured at
1.5V reference level.
This parameter is guaranteed and not tested.
Supply Voltage - (VCC -GND) -O.3V to +8.0V Operating Supply Voltage
Input or Output Voltage Applied (GND -O.3V) Industrial (-9)
to (VCC +O.3V)
-650C to +1500C Operating Temperature
Industrial (-9)

* CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may CBUse permanent
damage to the device. This is a stress only fating and functional operation of the device at these or at any
other conditions above those indicated in the operational sections of this specification ;s not implied.

TEMP. & VCC- TEMP - 250cCD

OPERATING VCC- 5.0V
RANGE
TEST
SYMBOL PARAMETER MIN MAX TYPICAL UNITS CONDITIONS

ICCSB Standby Supply Current 25 3.0 IJ.A 10 - 0

~ - VCC -0.3V
Iceop Operating Supply Current ® 7 5 mA ~-lMHz, 10=0
VI- GND
leeDR Data Retention Supply Current 15 2.0 IJ.A vee - 2.0V,J0 = 0
~- vee
VeeOR Data Retention Supply Voltage 2.0 1.4 V
II 1 nput Leakage Current -1.0 +1.0 0.0 IJ.A GNOSVISVee
1I0Z Input/Output Leakage Current -1.0 +1.0 0.0 IJ.A GNOSVIOSVee
VIL Input Low Voltage -0.3 O.B 1.2 V
VIH Input High Voltage vee vee 2.2 V
-2.0 +0.3
VOL Output Low Voltage 0.4 0.25 V 10 - 2.0mA
VOH Output High Voltage 2.4 4.0 V 10 - -LOrnA
el Input Capacitance@) B.O 5.0 pF VI - vee or GND
f -lMHz
elo Input/Output CIP8citance® 10.0 6.0 pF VIO - vee or GND
f -lMHz

TELOV Chip Enable Access Time 200 ns 0

TAVOV Address Access Time 220 ns
0
TELOX Chip Enable Output Enable
Time
20 ns 0
TWLOZ Write Enable Output Disable
Time
BO ns 0®
TEHOZ Chip Enable Output Disable
Time
BO ns 0®
TELEH Chip Enable Pulse Negative
Width
200 ns 0
TEHEL Chip Enable Pulse Positive
Width
90 ns 0
TAVEL Address Setup Time 20 ns 0
TELAX Address Hold Time 50 ns 0
TWLWH Write Enable Pulse Width 200 ns
0
TWLEH Write Enable Pulse Setup Time 200 ns 0
TELWH Write Enable Pulse Hold Time 200 ns 0
TOVWH
TWHOX
Data Setup Time 120 ns 0
Data Hold Time 0 ns
TWLOV Write Data Delay Time BO ns ffi
TWlEL Early Output High-Z Time 0 ns 0
TEHWH Late Output High-Z Time 0 ns 0
TELEL Read or Write Cycle Time 290 ns 0
All devices tested at worst case limits. Room Temp,. 5V data provided for information - not guaranteed
Operating Supply Current (ICCO?) is proportional to Operating Frequency. Ex: TypicaliCCOP = 5mA/MHz.
Capacitance sampled and guaranteed - not 100% tested.
AC test conditions: Inputs - TRISE = TFALL = 10ns; Output - CLOAD = 50pF. All timing measured at
1 .5 V reference level.
This parameter is guaranteed and not tested. 2-44
Supply Voltage - (VCC - GND) -O.3V to +8.0V Operating Supply Voltage
Military (-2)
Input or Output Voltage Applied (GND -O.3V)
to (VCC +O.3V)
Operating Temperature
Military (-2)

• CAUTION: Stresses above those listed under "Absolute Maximum Ratings" mllY cause permanent
damage to the device. This is II stress only 'llting and functional operation of the device at these or at any
other conditions above those indicated in the operational 16Ctions of this specification is not implied.

TEMP. & VCC- TEMP -:ZSOCCD

OPERATING VCC- 5.0V
RANGE
TEST
SYMBOL PARAMETER MIN MAX TYPICAL UNITS CONDITIONS

ICCSB Standby Supply Current 50 5.0 p.A 10= 0

10· VCC-0.3V
ICCOP Operating Supply Current ® 7 5 mA E-1MHz, 10 = 0
VI = GND
ICCDR Data Retention Supply Current 25 3.0 p.A VCC = 2.0V.10 = 0
E"- VCC
VCCDR Data Retention Supply Voltage 2.0 1.4 V
II Input Leakage Current -1.0 +1.0 0.0 p.A GND S VI S VCC
1I0Z Input/Output Leakage Current -1.0 +1.0 0.0 p.A GNDSVIOSVCC
VIL Input Low Voltage -0.3 0.8 1.2 V
VIH Input High Voltage VCC VCC 2.2 V
-2.0 +0.3
VOL Output Low Voltage 0.45 0.25 V 10 - 2.0mA
VOH Output High Voltage 2.4 4.0 V 10' -1.0mA
CI Input Capacitance® 8.0 5.0 pF VI' VCC 0' GND
f= lMHz
CIO Input/Output C8pacitance® 10.0 6.0 pF VIO = VCC or GND
fz lMHz

TELOV Chip Enable Access Time 300 ns 0

TAVOV Address Access Time 320 ns 0
TELOX Chip Enable
Time
Output Enable 20 ns 0
TWLOZ Write
Time
Enable Output Disable 100 ns
0®
TEHOZ Chip Enable
Time
Output Disable 100 ns
0®
TELEH Chip Enable
Width
Pulse Negative 300 ns 0
TEHEL Chip Enable
Width
Pulse Positive 120 ns 0
TAVEL Address Setup Time 20 ns 0
TELAX Address Hold Time 50 ns 0
TWLWH Write Enable Pulse Width 300 ns 0
TWLEH Write Enable Pulse Setup Time 300 ns 0
TELWH Write Enable Pulse Hold Time 300 ns 0
TDVWH Data Setup Time 200 ns 0
TWHDZ Data Hold Time 0 ns
TWLDV Write Data Delay Time 100 ns ~
TWLEL Early Output High-Z Time 0 ns 0
TEHWH Late Output High-Z Time 0 ns 0
TELEL Read or Write Cycle Time 420 ns 0
All devices tested at worst case limits. Room temp., 5 volt data provided for information - not guaranteed
Operating Supply Current (ICCOPl is proportional to Operating Frequency. Example: Typical ICCOP = 5mA/MHz.
Capacitance sampled and guaranteed - not 100% tested.
AC Test Conditions: Inputs - TRISE TFALL = 10n5Oc; = Outputs - CLOAD = 50pF. All timing
measurements at 1.5V reference level.
This value is guaranteed and tested at 25°C.
Supply Voltage - (VCC -GND) -O.3V to +8.0V Operating Supply Voltage
Input or Output Voltage Applied (GND -O.3V) Industrial (-9)
to (VCC +O.3Vl
-650C to +1500C
Operating Temperature
Industrial (-9)

• CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may causa permanant
damage to the device. This is a stress only rating and functional operation of the device at these or at any
other conditions above those indicated in the operational sections of this specification is not implied.

TEMP. & VCC- TEMP - 250 cCD

OPERATING VCC- 5.0V
RANGE
TEST
SYMBOL PARAMETER MIN MAX TYPICAL UNITS CONDITIONS

ICCSB Standby Supply Current 25 3.0 jJ.A 10=0

~- VCC -0.3V
ICCOP Operating Supply Current CD 7 5 mA ~·lMHz. 10 = 0
VI- GND
ICCDR Data Retention Supply Current 15 2.0 jJ.A VCC - 2.0V. 10 - 0
~= VCC
VCCDR Data Retention Supply Voltage 2.0 1.4 V
II Input Leakage Current -1.0 +1.0 0.0 jJ.A GND:SVI:SVCC
IIOZ Input/Output Leakage Current -1.0 +1.0 0.0 jJ.A GND:S VIO:S VCC
VIL Input Low Voltage -0.3 O.B 1.2 V
VIH Input High Voltage VCC VCC 2.2 V
-2.0 +0.3
VOL Output Low Voltage 0.45 0.25 V 10' 2.0mA
VOH Output High Voltage 2.4 4.0 V 10' -LamA
CI Input Capacitance0 B.O 5.0 pF VI = VCC or GND
f -lMHz
CIO Input/Output Capacitance® 10.0 6.0 pF VIO· VCC or GND
f 'lMHz

TELOV Chip Enable Access Time 300 ns 0

TAVOV Address Access Time 320 ns
0
TELOX Chip Enable
Time
Output Enable 20 ns 0
TWLOZ Write
Time
Enable Output Disable 100 ns 0®
TEHOZ Chip Enable
Time
Output Disable 100 ns 0®
TELEH Chip Enable
Width
Pulse Negative 300 ns 0
TEHEL Chip Enable
Width
Pulse Positive 120 ns 0
TAVEL Address Setup Time 20 ns
0
TELAX Address Hold Time 50 ns 0
TWLWH Write Enable Pulse Width 300 ns 0
TWLEH Write Enable Pulse Setup Time 300 ns 0
TELWH Write Enable Pulse Hold Time 300 ns 0
TDVWH
TWHDX
Data Setup

Data Hold
Time

Time
200 ns 0
a ns
TWLDV Write Data Delay Time 100 ns ffi
TWLEL Early Output High-Z Time 0 ns 0
TEHWH Late Output High-Z Time 0 ns 0
TELEL Read or Write Cycle Time 420 ns 0
All devices tested at worst case limits. Room temp., 5 volt data provided for information - not guaranteed
Operating Supply Current (ICCOP) is proportional to Operating Frequency. Example: Typical ICCOP = 5mA/MHz.
Capacitance sampled and guaranteed - not 100% tested.
AC Test Conditions: Inputs - TRISE = TFALL: 10nsec; Outputs - CLOAD· 50pF. All timing
measurements at 1.5V reference level.
Supply Voltage - (VCC -GNDI -O.3V to +8.0V Operating Supply Voltage
(GND -O.3V) Industrial (-9)
Input or Output Voltage Applied
to (VCC +O.3V)
Operating Temperature
-650C to +150oC
Industrial (-9)

* CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This;s a stress only rating and functional operation of the device at these or at any
other conditions above those indicated in the operational sections of this specification is not implied.

TEMP. & VCC- TEMP - 250 cCD

OPERATING VCC - 5.0V
RANGE
TEST
SYMBOL PARAMETER MIN MAX TYPICAL UNITS CONDITIONS

ICCSB Standby Supply Current 100 20 ~A 10-0

£'- VCC -0.3V
ICCOP Operating Supply Current 0 7 5 mA £'-lMHz. 10' a
VI- GND
ICCDR Data Retention Supply Current 50 12 ~A VCC - 2.0V. 10 - a
£'- VCC
VCCDR Data Retention Supply Voltage 2.0 1.4 V
II Input Leakage Current -1.0 +1.0 0.0 ~A GND~VI~VCC
1I0Z Input/Output Leakage Current -1.0 +1.0 0.0 ~A GND~VIO~VCC
VIL Input Low Voltage -0.3 O.B 1.2 V
VIH Input High Voltage VCC VCC 2.2 V
-2.0 +0.3
VOL Output Low Voltage 0.4 0.25 V 10 - 2.0mA
VOH Output High Voltage 2.4 4.0 V 10 - -LamA
CI Input Capacitance® B.O 5.0 pF VI - VCC or GNO
f-1MHz
CIO Input/Output Capacitance@) 10.0 6.0 pF VIO - VCC or GND
f -lMHz

TELOV Chip Enable Access Time 300 ns @

TAVOV Address Access Time 320 ns @
TELOX Chip Enable Output Enable 20 ns @
Time

TWLOZ Write Enable Output Disable 100 ns @®

Time

TEHOZ Chip Enable Output Disable 100 ns @(5)

Time

TELEH Chip Enable Pulse Negative 300 ns @

Width

TEHEL Chip Enable Pulse Positive 120 ns @

Width

TAVEL Address Setup Time 20 ns @

TELAX Address Hold Time 50 ns @
TWLWH Write Enable Pulse Width 300 ns @
TWLEH Write Enable Pulse Setup Time 300 ns @
TELWH Write Enable Pulse Hold Time 300 ns @
TDVWH Data Setup Time 200 ns @
TWHDX Data Hold Time a ns
TWLDV
TWLEL
Write

Early
Data

Output
Delay

High-Z
Time

Time
100
a
ns
ns
ffi@
TEHWH Late Output High-Z Time a ns @
TELEL Read or Write Cycle Time 420 ns @

NOTES: ~ All devices tested at worst case limits. Room temp., 5 volt data provided for information - not guaranteed
Operating Supply Current (ICCOP) is proportional to Operating Frequency. Example: Typical ICCOP = 5mA/MHz.
Capacitance sampled and guaranteed - not 100% tested,
@ AC Test Conditions: Inputs - TRISE - TFALL· 10nsec; Outputs - CLOAD - 50pF. All timing
measurements at 1 ,5V reference level.

® This perameter is guarenteed and not tested. 2-47

Supply Voltage - (VCC - GND) -O.3V to +8.0V Operating Supply Voltage
Input or Output Voltage Applied (GND -O.3VI Commercial
to (VCC +O.3VI
-650C to +150oC

* CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress only rating and functional operation of the device at these or at any
other conditions above those indicated in the operatiunal sections of this specification is not implied.

TEMP. & vec' TEMP - 25OCQ)

OPERATING vec- 5.0V
RANGE
TEST
SYMBOL PARAMETER MIN MAX TYPICAL UNITS CONDITIONS

leCSB Standby Supply Current 350 50 JJA E = vee -Q.3V

10= 0
leeop Operating Supply Current ® 7 5 mA ~ - 1MHz. 10 = 0
VI- GND

ICCDR Data Retention Supply Current 200 30 JJA VCC= 2.0V,10 = 0

e=vce
VCCDR Data Retention Supply Voltage 2.0 1.4 V
II Input Leakage Current -10.0 +10.0 iO.5 uA GND S VI S VCC
IIOZ Input/Output Leakage Current -10.0 +10.0 iO.5 JJA VCC $ Via S GND
VIL Input Low Voltage -0.3 0.8 1.2 V
VIH Input High Voltage VCC VCC 2.2 V
-2.0 +0.3
VOL Output Low Votta~ 0.4 0.25 V 10 = 1.6mA
VOH Output High Voltage 2.4 4.0 V 10 = -0.4mA
CI Input Capacitance@ 8.0 5.0 pF VI = VCC 0' GND
f= lMHz
cia Input/Output Capacitance@) 10.0 6.0 pF VI = VCC 0' GND
f= lMHz

TELQV Chip Enable Access Time 350 ns 0

TAVQV Address Access Ti me 370 ns 0
TELQX Chip Enable Output Enable
Time
20 ns
0
TWLQZ Write
Time
Enable Output Disable 100 ns 0®
TEHQZ Chip Enable Output Disable
Time
100 ns 0®
TELEH Chip Enable
Width
Pulse Negative 350 ns 0
TEHEL Chip Enable
Width
Pulse Positive 150 ns 0
TAVEL Address Setup Time 20 ns 0
TELAX Address Hold Time 50 ns 0
TWLWH Write Enable Pulse Width 350 ns
0
TWLEH Write Enable Pulse Setup Time 350 ns 0
TELWH Write Enable Pulse Hold Time 350 ns 0
TDVWH Data Setup Time 250 ns
0
TWHDX Data Hold Time 0 ns 0
TWLDV Write Data Delay Time 100 ns
0
TWLEL Early Output High-Z Time 0 ns
0
TEHWH Late Output High-Z Time 0 ns
0
TELEL Read or Write Cycle Time 500 ns
0
All devices tested at worst case limits. Room temp., 5 volt data provided for information - not guaranteed
Operating Supply Current (ICCOP) is proportional to Operating Frequency. Example: Typical ICeD? = 5mA/MHz.
Capacitance sampled and guaranteed - not 100% tested.
AC Test Conditions: Inputs - TR ISE = TFALL = lOnsec; Outputs - CLOAD = 50pF. All timing
measurements at 1.5V reference level.
This parameter is guaranteed and not tested.
 TIME INPUTS 0 .•••T .•••1I0

REFERENCE E W A 00 FUNCTION

, , , MEMORY DISABLED

'-," " ,
2

,
0 V
,
2 CYCLE BEGINS. ADDRESSES ARE LATCHeD

, ," , OUTPUT ENABLED

.,
J .r "

'-" "
,
, ,
H

V
V
V
2
2
OUTPUT

PREPARE
CYCLE
VALID
RE .•••O ACCOMPLISHED
FOR NEXT CYCLE
ENDS NEXT CYCLE
ISAME AS-ll
BEGINS ISAIAE .•••S 0)

The address information is latched in the on chip registers enabled but data is not valid until time (T = 2). Vi must
on the falling edge of ~ (T = 0). Minimum address setup remain hig!l throughout the read cycle. After the data has
and hold time requirements must be met. After the required been read E may return high (T = 3). This will force the out-
hold time the addresses may change state without affecting put buffers and all inputs to a disabled state at time (T = 4).
device operation. During time (T = 1) the outputs become The memory is now ready for the next cycla.

TIME INPUTS
REFERENCE E W A 00 FUNCTION

, , ,
" ,
2 MEMORY DISABLED

,
0 '-, , , V 2 CYCLE BEGINS. ADDRESSES ARE LATCHED

, , .r , 2 WRiTe ~eRIOD BEGINS

.
J

,
.r
"
'\.
,
,
", ,
V
V
2
2
2
DATA

PREPARE
IN IS WRITTEN
WRITE CO",PLETED

CYCLE ENDS
FOR NEXT CYCLE
NEXT CYCLE
ISAME AS-II
BEGINS fS.•••ME AS 0)

The write cycle is initiated by the falling edge of E (T = 0), This E and W control timing will guarantee that the data
which latches the address information in the on-ehip outputs will stay disabled throughout the cycle, thus sim-
registers. There are two basic types of write cycles, which plyifying the data input timing. TWLEL and TEHWH must
differ in the control of the common data-in/data-out bus. be met but TWLDV becomes meaningless and can be ig-
nored. In this cycle TDVWH and TWHDX become TDVEH
and TEHDX. In other words, reference data setup and
hold times to the ~ rising edge.
The output ..Euffers !:!lay become enabled (reading) if E
falls before W falls. W is used to disable (three-state) the IF OBSERVE IGNORE
outputs so input data can be applied. TWLDV must be met
to allow the ijj signal time to disable the outputs before Case 1 E falls before W TWLDV TWLEL
applying input data. Also, at the end of the cycle the out- Case 2 ~ falls after W & TWLEL TWLDV
puts may become active if W rises before E. The RAM E rises before W TEHWH TWHDX
outputs and all inputs will-state) after E rises (TEHQZ).
In this type of write cycle TWLEL and TEHWH may be
ignored. If a series of consecutive write cycles are to be performed,
Vi may be held low until all desired locations have been
Case 2: E falls equal to or afterW falls, and E rises written (an extension of Case 2).
before or equal to W rising
 TIME INPUTS DATAIIO
REFERENCE E W A 00 FUNCTION

, ,
H
'-
X
H
X
V , MEMORY
CYCLE
DISABLED
BEGINS. ADDRESSES ARE LATCHED
0
,
, ,
C H X X READ MODE. OUTPUT ENABLED

.
l

,
,
,,
,
J
J
H

H
X
X
X
X
,
V

,
V

,
READ MODE. OUTPUT
WRITE
WRITE
WRITE
MODE. OUTPUT
MODE DATA
COMPLETED
VALID
HIGH Z
IS WRITTEN

, H

'-
X
H
X
V , PREPARE FOR NEXT CYCLE
CYCLE ENDS. NEXT CYCLE
(SAME AS·1I
BEGINS [SAME AS 01

If the pulse width of W is relatively short in relation to that information just written may now be read or E may return
of E a combination read-write cycle may be performed. If high, disabling the output buffers and all inputs and pre-
W remains high for the first part of the cycle, the outputs paring the device for the next cycle. Any number or
will become active during time (T: 1). Data out will be sequence of read-write operation may be performed
valid during time (T : 2). After the data is read, W can go while E is low providing all timing requirements are met.
low. After minimum TWLWH, W may return high. The

":~~-----A-O-O'-~:-:-"-"-O------bw
6514 - Requires Valid Address for Only a Small
Portion of the Cycle, but Requires E te
Fall to Initiate Eact'l Cycle.
;II HARRIS HM-6516

• LOW POWER STANDBY 275 J.l.W MAX

• LOW POWER OPERATION 55mW/MHz MAX TOP VIEW

• FAST ACCESS 120/200 ns MAX A7 VCC
A6 A8
• INDUSTRY STANDARD PINOUT
AS A9 PIN NAMES
• SINGLE SUPPLY A4 W Address Input
A3 if Data InpuUDutput
• TTL COMPATIBLE A2 A1D
Chip Enable
• STATIC MEMORY CELLS Al E
Output Enable
AD 007
• HIGH OUTPUT DRIVE 000 006
Write Enable
001 DOS No Connect
• ON CHIP ADDRESS LATCHES
002 004
• EASY MICROPROCESSOR INTERFACING OND 003

• WIDE TEMPERATURE RANGE

The HM-6516 is a CMOS 2048 x 8 Static Random Access Memory. Ex-

tremely low power operation is achieved by the use of complementary MaS
design techniques. This low power is further enhanced by the use of synch-
ronous circuit techniques that keep the active (operating) power low, and
also give fast access times. The pinout of the HM-6516 is the popular 24 pin,
8 bit wide JEDEC standard which allows easy memory board layouts, flexible
enough to accomodate a variety of PROMs, RAMs, EPROMs, and ROMs.
The HM-6516 is ideally suited for use in microprocessor based systems.
The byte wide organization simplifies the memory array design,and keeps
operating power down to a minimum because only one device is enabled at
a time. The address latches allow very simple interfacing to recent genera-
tion microprocessors which employ a multiplexed address/data bus. The con-
venient output enable control also simplifies multiplexed bus interfacing by
allowing the data outputs to be controlled independent of the chip enable.

ALL LINES POSITIVE LOG1C-

ACTIVE HIGH

THREE STATE BUFFERS:

A HIGH - OUTPUT ACTIVE

ADORESS LA."TCHES AN.D GATED

DECODERS:
LATCH ON FALLING EDGE OFE
GATE ON FALLING EDGE OF E
ABSOLUTE MAXIMUM RATINGS· OPERATING RANGE
Operating Supply Voltage
Supply Voltage (VCC - GND) -0.3 to 8.0V Military (B-2) 4.5V to 5.5V
Input or Output Voltage Applied (GND -0.3V) Industrial (B-9) 4.5V to 5.5V
to (VCC +0.3V) Operating Temperature
-65°C to 150°C Military (B-2) -550C to +1250C
Industrial (B-9) -400C to +850C
• CAUTION: Str••• tn above thoSBIi.tad under "Abso/ute Maximum Ratings" may cau.e permanent
damsgs to the device. Thi. i. a .tress only rating and functional operation of the deviceat the.e or at any
other condition. above those indicated in the operational ssction. of this specification i. not implied.

TEMP.&VCC -
OPERATING
RANGE G) TEST
SYMBOL PARAMETER MIN MAX UNITS CONDITIONS

ICCSS Standby Supply Currant 50 IJA 10 -0

VI - VCC or GND
ICCOP Operating Supply Current ® 10 mA f-1 MHz,IO=O,G'-VCC
VI - VCC or GND
ICCDR Data Retention Supply Current 25 !JA 10 - O. VCC • 2.0,
VI· VCC or GND,
VCCDR Data Retention Supply Voltage 2.0 V E = VCC
II Input Leakage Current -1.0 +1.0 IJA GNDS VIS VCC
1I0Z Input/Output LeakageCurrent -1.0 +1.0 IJA GND:S; VIO:S; VCC
VIL Input Low Voltage -0.3 0.8 V
VIH Input High Voltage 2.4 VCC V
+0.3
VOL Output Low Voltage 0.4 V 10 -3.2mA
VDH Output High Voltage 2.4 V 10 - -1.0mA
CI Input Capacitance ® 8.0 pF VI • VCC or GND,
f-1MHz
CIO Input/Output Capacitance ® 10.0 pF VIO • VCC or GND,
f ·1MHz

TELOV Chip Enable Acce •• Time 120 ns @

TAVOV Addre •• Acce•• Time 120 ns @
TELOX Chip Enable Output Enable Time 10 ns @
TWLOZ Writa Enable Output Disable Time 50 ns @
TEHOZ Chip Enable Output Disable Time 50 ns @
TGLOV Output Enable Output Valid Time 80 ns 0
TGLOX Output EnablaOutput E"ableTime 10 ns @
TGHOZ Output EnableOutput DisableTime 50 nl @
TELEH Chip Enable Pulse Nagative Width 120 nl @
TEHEL Chip Enable Pulse POlitiva Width 50 nl @
TAVEL Addre •• Setup Time 0 ns
TELAX Addre •• Hold Time 30 nl ~
TWLWH Write Enable PulseWidth 120 ns @
TWLEH Write Enable PulseSetup Time 120 ns @
TELWH Write Enable Pulse Hold Time 120 ns @
TDVWH Data Setup Time 50 ns @
TWHDX Data Hold Time 10 ns @
TWLDV Write Data Delay Time 50 ns @
TELEL Read or Write Cycle Tima 170 ns @

NOTES:
All devices tested at worst case limits.
~ Operating Supply Current (ICCOP) is proportional to Operating Frequency.
Example: TypicallCCOP = 5mA/MHz. This parameter is sampled and guaranteed - Not 100% tested.
® Capacitance sampled and guaranteed· not 100% tested.
@ AC test conditions: Inputs - TRISE - TFALL = 5ns; Output - CLOAD - 5OpF. All timing
measured at 1.5V reference level. Input pulse levels: OV to 3V.
2-52
ABSOLUTE MAXIMUM RATINGS· OPERATING RANGE
Supply Voltage (VCC - GND) -0.3 to 8.0V Operating Supply Voltage
Military (-2) 4.5V to 5.5V
Input or Output Voltage Applied (GND -0.3V) 4.5V to 5.5V
Industrial (-9)
to (VCC +O.3V) Operating Temperature
-650C to 150°C Military (-2) -55°C to +1250C
Industrial (-9) -400C to +850C
• CAUTION: Stres.es abova thOlB li.tad under "Abloluta Maximum Ratinfll" may cau'a parmanant
damagato tha devica. Thi. i. a Itre•• only rating and functional oparation of tha davicaat the.e or et any
other condition. abovtJthOlB indicated in the operational IBerion. of this spocification i. not implied.

TEMl!&VCC·
OPERATING
RANGE G)
TEST
SYMBOL PARAMETER MIN MAX UNITS CONDITIONS

ICCSB Standby Supply Current 100 IJA 10 -0

VI - VCC or GND
ICCOP Oparating Supply Current @ 10 mA f-l MHz.IO=O,G-vcC
VI - VCC or GND
ICCDR Data Retention Supply Current 50 IJA 10·0, VCC· 2.0,
VI - VCC or GND.
VCCDR Data Retention Supply Voltage 2.0 V E - VCC
II Input Leakage Current -1.0 +1.0 IJA GND.:'> VI.:'> VCC
IIOZ Input/Output Leakage Current -1.0 +1.0 IJA GND .:'>VIO .:'>VCC
VIL Input Low Voltage -0.3 0.8 V
VIH Input High Voltage 2.4 VCC V
+0.3
VOL Output Low Voltage 0.4 V 10 -3.2mA
VOH Output High Voltage 2.4 V 10 --1.0mA
CI Input Capacitance ® 8.0 pF VI - VCC or GND,
f-1MHz
CIO Input/Output Copacitance ® 10.0 pF VIO - VCC or GND,
f -lMHz

TELQV Chip Enable Access Time 200 ns @

TAVQV Address Access Time 200 ns @
TELQX Chip Enable Output Enable Time 10 ns @
TWLQZ Write Enable Output Disable Time 80 ns @
TEHQZ Chip Enable Output Disable Time 80 ns @)
TGLQV Output Enable Output Valid Time 80 ns @
TGLQX Output Enable Output Enable Time 10 ns @
TGHQZ Output EnableOutputDisableTime 80 ns @
TELEH Chip Enable Pulse Negative Width 200 ns @)
TEHEL Chip Enable Pulse Positiva Width 80 ns @
TAVEL Address Setup Time 0 ns
TELAX Address Hold Time 50 ns ~
TWLWH Write Enable Pulse Width 200 ns @
TWLEH Write Enable Pulse Setup Time 200 ns @
TELWH Write Enable Pulse Hold Time 200 ns @
TDVWH Data Setup Time 80 ns @
TWHDX Data Hold Time 10 ns @
TWLDV Write Data Delay Time 80 ns @
TELEL Read or Write Cycle Time 280 ns @

NOTES:
All devices tested at worst case limits.
~ Operating Supply
Exemple: Typical
Current lICCOp) is proportional
ICCOP - SmA/MHz.
to Operating Frequency.
This parameter is sampled and guaranteed - Not 100% tested.
® Capacitance sampled and guaranteed· not 100% tested.
@ AC test conditions: Inputs - TRISE - TFALL -IOns; Output - CLOAD • 100pF All timing
measured at 1.5V reference level. Input pulse levels: OV to 3V.
2-53
ABSOLUTE MAXIMUM RATINGS· OPERATING RANGE
Supply Voltage (VCC - GND) -0.3 to B.OV Operating Supply Voltage
Input or Output Voltage Applied (GND -0.3V) Commercial (-5)
to (VCC +0.3V) Operating Temperature
-65°C to 150°C Commercial (-5)

• CAUTION: Stre•••• ebove those Ii.ted under "Absolute Meximum Ratingr" may cau'e permanent
damaf/8to the device. Thi. i. a .tress only rating and functional operation of the deviceat the.e or at any
other condition. above those indicated in the operational section. of this .pecification i. not implied.

TEMP.&VCC·
OPERATING
RANGE G) TEST
SYMBOL PARAMETER MIN MAX UNITS CONOITIONS

ICCSB Standby Supply Currant 500 IJ.A 10 -a

VI = VCC or GND
ICCOP Oparating Supply Currant ® 10 mA f=1 MHz,IO=O,G=VCC
VI - VCC or GND
ICCDR Data Retention Supply Current 250 JJ.A 10 = 0, VCC - 2.0.
VI = VCC or GND,
VCCDR Data Retention Supply Voltage 2.0 V E= VCC

II Input Leakage Current -5.0 +5.0 IJ.A GND~ VI ~ VCC

IIOZ Input/Output Leakaga Current -5.0 +5.0 IJ.A GND :5: VIO :5: VCC
VIL Input Low Voltage -0.3 0.8 V
VIH Input High Voltage 2.4 VCC V
+0.3
VOL Output Low Voltage 0.4 V 10 - 3.2mA
VOH Output High Voltage 2.4 V 10 = -1.0mA
CI I nput Capacitance ® 8.0 pF VI • VCC or GNO,
f = lMHz
CIO I nput/Output Capacitance ® 10.0 pF VIO - VCC or GND,
f = lMHz

TELQV Chip Enable Access Time 200 ns @

TAVQV Address Access Time 200 ns @
TELQX Chip Enable Output Enable Time 10 ns ®
TWLQZ Write Enable Output Disable Time 80 ns ®
TEHQZ Chip Enable Output Disable Time 80 ns ®
TGLQV Output Enable Output Valid Time 80 ns @
TGLQX Output Enable Output EnableTime 10 ns ®
TGHQZ Output Enable Output DisablaTime 80 n. @
TELEH Chip Enable Pulse Nagative Width 200 ns @
TEHEL Chip Enable Pulse Positive Width 80 n. ®
TAVEL Address Satup Time a ns
TELAX Address Hold Time 50 ns ~
TWLWH Write Enable Pulse Width 200 ns ®
TWLEH Write Enable Pulse Setup Time 200 ns ®
TELWH Write Enable Pulse Hold Time 200 ns ®
TDVWH Data Setup Time 80 ns ®
TWHDX Data Hold Tima 10 ns ®
TWLDV Write Data Delay Time 80 ns ®
TELEL Read or Write Cycle Time 280 ns ®

NOTES:
All devices tested at worst case limits.
~ Operating Supply Current (ICCOP) is proportional to Operating Frequency.
Exampla: Typical ICCOP· SmA/MHz. This paramater is sampled and guaranteed - Not 100% tested.
® Capacitanca sampled and guarantaed • not 100% tested.

® AC test conditions: Inputs - TRISE - TFALL -IOns; Output - CLOAD , 100pF.AII timing
measurad at 1.5V referance level. Input pulse lavels: OV to 3V.
2-54
 TEHQZ

VALID DATA OUT

TI ••••E INPUTS
REFERENCE T Vi G A DO FUNCTION

-, H X X X Z MEMORY DISABLED

0 '- H X V Z CYCLE BEGINS ADDRESSES ARE LATCHED

1 L H L X X OUTPUT ENABLED

2 L H L X V OUTPUT VALtD

3 ./ H X X V READ ACCOMPLISHED
4 H X X X Z PREPARE FOR NEXT CYCLE (SAME AS-lI

5 '- H X V Z CYCLE ENDS. NEXT CYCLE BEGINS (SAME AS 0)

The address information is latched in the on chip registers cycle. After the data has been read, E may return high
on the falling edge of E (T = 0). minimum address setup (T = 3). This will force the output buffers into a high
and hold time requirements must be met. After the impedance mode at time (T = 4). G is used to disable the
required hold time, the addresses may change state output buffers when in a logical "1" state (T = -1, 0,
without affecting device operation. During time (T = 1). 3,4, 5). After (T = 4) time, the memory is ready for the
the outputs become enabled but data is not valid until next cycle.
time (T = 2). IN must remain high throughout the read

E f I

TWLWH TWLEH-

D:~'~
G HIGH
~

TIME INPUTS
REFERENCE E Vi 1l" A DO FUNCTION

-1 H X H X X MEMORY DISABLED
0 '- X H V X CYCLE BEGINS. ADDRESSES ARE LATCHED
1 L L H X X WRITE PEAIOD BEGINS
2 L ./ H X V DATA IN IS WRITTEN
3 ./ H H X X WAITE COMPLETED
4 H X H X X PREPARE FOR NEXT CYCLE (SAME AS-l)
5 '- X H V X CYCLE ENDS, NEXT CYCLE BEGINS (SAME AS 0)

The write cycle is initiated on the falling edge ofE (T = 0), to the E rising edge. The write operation is terminated by
which latches the address information in the on chip the first rising edge ofW (T = 2) or E(T = 3). After the
registers. If a write cycle is to be performed where the minimum E high time (TEHEL). the next cycle may
output is not to become active, G can be held high (in- begin. If a series of consecutive write cycles are to be
active). TDVWH and TWHDX must be met for proper performed, the W line may be held low unit! all desired
device operation regardless of G. If E and "IT fall before W locations have been written. In this case, data setup
falls (read mode), a possible bus conflict may exist. If and hold times must be referenced to the rising edge ofE.
E rises before IN rises, reference data setup and hold times
 TIME INPUTS DATA 1/0
REFERENCE r Vi 1r A 00 FUNCTION

_1 H X H X Z MEMORY DISABLED
0 "\ H H V Z CYCLE BEGINS. ADDRESSES AAE LATCHED
1 L H L X X READ MODE. OUTPUT ENABLED I Vii· HIGH, G· LOWl
2 L H L X V READ MODE, OUTPUT VALID
3 L L H X Z WAITE MODE, OUTPUT HIGH Z
4 L f H X V WRITE MODE, DATA IS WRITTEN
5 f H H X Z WRITE COMPLETED

•
7
H
"\
X
H
H
H
X
V
Z
Z
PREPARE
CYCLE
FOR
ENDS,
NEXT
NEXT
CYCLE
CYCLE
(SAME
BEGINS
AS-ll
(SAME AS OJ

If the pulse width of W is relatively short in relation to TWLWH, Iii may return high. The information just written
that of E, a combination read write cycle may be perform- may now be read or E may return high, disabling the out-
ed. If W remains high for the first part of the cycle, the put buffer and preparing the device for the next cycle.
output will become active during time (T = 1) provided Any number or sequence of read-write operations may be
G is low. Data out will be valid during time (T = 2). performed while E is low providing all timing requirements
After the data is read, Iii can go low. After minimum are met.

NOTES:
In the above descriptions, the numbers in parentheses (T = n), refer to the respective timing diagrams. The numbers
are located on the time reference line below each diagram. The timing diagrams shown are only examples and are
not the only valid method of operation.
m HARRIS HM-65162
2048 x 8 Asynchronous
CMOS Static RAM

Pinouts
• FASTACCESSTIME n. MAX
551701901120 TOP VIEW
• Law STANDBYCURRENT 50"A MAX 1
• Law OPERATINGCURRENT A7 24 VCC
70 mA MAX A6 2 23 A8
• DATARETENTION@ 2.0 VOLTS 20"A MAX 3 PIN NAMES
• TIL CoMPI\TIBLEINPUTSANDOUTPUTS A5 22 A9
A4 4 21 Vi A Address Input
• JEoECAPPROVEDPINOUT(2716, 6116 TYPE)
• NOCLOCKSDRSTROBESREQUIRED A3 5 20 if DO Data InpuVOutput
• WIDETEMPERATURERANGE A2 6 19 AID E Chip Enable
Al 7 18 f
• EOUALCYCLEANDACCESSTIME
AD 8 17 007 G Output Enable
• SINGLE5 VOLTSUPPLY W Write Enable
000 9 16 006
• GATEDINPUTS- NOPULL-UPDR PULL-DOWN 10 15 NC No Connect
RESISTORSAREREOUIREo oQl OQ5
oQ2 11 14 oQ4
GNO 12 13 003

Description
The HM-65162 is a CMOS 2048 x 8 Static Random Access Memory manufactured
using the HARRIS advanced SAJI V process. The device utilizes asynchronous circuit
design f~r fast cycle time and ease of use. The pinout is the JEDEC 24 pin, 8 bit wide
standard which allows easy memory board layouts flexible to accommodate a variety of
industry standard PROMs, RAMs, ROMs and EPROMs. The HM-65162 is ideally suited
for use in microprocessor based systems with its 8 bit word length organization. The
convenient output enable also simplifies the bus interface by allowing the data outputs
to be controlled independent of the chip enable. Gated inputs lower operating current
and also eliminate the need for pull-up or pull-down resistors.

Functional Diagram
A1
A2--
A3-- ROW
oE- /- 128 x 128
A4--
A5-- CODER 28 MEMORY ARRAY
A6--
A7
DaD
/-8THRU
I Da7
I
I
 ABSOLUTE MAXIMUM RATINGS· OPERATING RANGE
Supply Voltage (Vee - GNO) -0.3 to 8.0V Operating Supply Voltage
Input or Output Voltage Applied (GNO -0.3V) Military (-2)
to (Vee +0.3V) Operating Temperature
-we to 150 e 0
Military (-2)
•. CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
only rating and functional operation of the device at these or at any other conditions above those indicated in the operational sections of
this specification is not implied.

TEMP. &. VCC =

OPERATING
RANGE CD TEST
SYMBOL PARAMETER MIN MAX UNITS CONDITIONS

ICCSB1 Standby Supply Current 50 ",A 10 ~ 0, E = VCC-0.3V

ICCSB Standby Supply Current 8 mA E= VIH, 10 ~ 0
ICC Enabled Supply Current 70 mA E~ VIL, 10 ~ 0
ICCOP Operating Supply Current ® 70 mA E= VIL, 10 = 0
t~ 1 MHz
ICCOR Oata Retention Supp~ Current 20 p.A 10 ~ 0, VCC ~ 2.0
E~VCC-0.3V
VCCOR Oata Retention Supply Voltage 2.0 V
II Input Leakage Current -1.0 +1.0 p.A GNO"VI"VCC
IIOZ InpuVOutput Leakage Current -1.0 +1.0 ",A GNO"VIO"VCC
VIL Input Low Voltage -0.3 0.8 V
VIH Input High Voltage 2.2 vcc V
+0.3V
VOL Output Low Voltage 0.4 V 10 ~ 4.0mA
VOH Output High Voltage 2.4 V 10 ~ -1.0mA
CI Input Capacitance ® 8 pF VI = VCC or GNO.
f ~ 1 MHz
CIO InpuVOutput Capacttance ® 10 pF VIO ~ VCC or GND,
f ~ 1 MHz

TAVAV Read Cycle Time 70 ns @)

TAVaV Address Access Time 70 ns @)
TELOV Chip Enable Access Time 70 ns @)
TELOX Chip Enable Output Enable Time 5 ns @)
READ TGLOV Output Enable Output Enable Time 50 ns @)
CYCLE TGLOX Output Enable Output Enable Time 5 ns @)
TEHOZ Chip Enable Output Disable Time 35 ns @)
TGHOZ Output Enable Output Disable Time 35 ns @)
TAVOX Output Hold trom Address Change 5 ns @)
TAVAV Write Cycle Time 70 ns @)
TELWH Chip Selection to End of Write 45 ns @)
TAVWL Address Setup Time 10 ns @)
WRITE TWLWH Write Enable Pulse Width 40 ns @)
CYCLE TWHAV Write Enable Read Setup Time 10 ns @)
TGHOZ Output Enable Output Disable Time 35 ns @)
TWLOZ Write Enable Output Disable Time 40 ns @)
TDVWH Data Setup Time 30 ns @)
TWHDX Data Hold Time 10 ns @)
TWHOX Write Enable Output Enable Time 0 ns @)
TWLEH Write Enable Pulse Setup Time 40 ns @)
TDVEH Chip Enable Data Setup Time 30 ns @)
TAVWH Address Valid to End of Write 65 ns @)
All devices tested at worst case limits.
Typical derating ~ 5mAlMHz increase in ICCOP: VI = VCC or GND.
capacitance sampled and guaranteed - not 100% tested.
Input pulse levels: OV to 3.0V Input and Output timing reference levels: 1.5V
Input rise and fall times: 5 ns Output load: lTTL Gate and 3t =
100pF (Including scope and jig)
 ABSOLUTE MAXIMUM RATINGS· OPERATING RANGE
Supply Voltage (VCC - GNO) -0.3 to 8.0V Operating Supply Voltage
Input or Output Voltage Applied (GNO -0.3V) Military (-2)
to (VCC +0.3V) Operating Temperature
- 65°C to 150°C Military (-2)
• CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
only rating and functional operation of the device at these or at any other conditions above those indicated in the operational sections of
this specification is not implied.

TEMP. & VCC =

OPERATING
RANGE <D TEST
SYMBOL PARAMETER MIN MAX UNITS CONDITIONS
ICCSB1 Standby Supply Current 100 p.A 10 ~ 0, E = VCC-0.3V
ICCSB Standby Supply Current 8 mA E ~ VIH, 10 ~ 0
ICC Enabled Supply Current 70 mA E = VIL, 10 ~ 0
ICCOP Operating Supply Current ® 70 mA [ ~ VIL, iO ~ 0
f~ 1 MHz
ICCDR Data Retention Supply Current 40 p.A 10 ~ 0, VCC =
2.0
[ ~ VCC-0.3V
VCCDR Data Retention Supply Voltage 2.0 V
II Input Leakage Current -1.0 +1.0 I'A GND",VI",VCC
1I0Z InpuUOutput Leakage Current -1.0 +1.0 I'A GND",VIO"'VCC
VIL Input Low Voltage -0.3 0.8 V
VIH Input High Voltage 2.2 VCC V
+0.3V
VOL Output Low Voltage 0.4 V 10 = 4.0mA
VOH Output High Voltage 2.4 V 10 ~ -1.0mA
CI Input Capacitance ® 8 pF VI ~ VCC or GND,
f ~ 1 MHz
cia InpuUOutput Capacitance ® 10 pF via ~ VCC or GND,
f ~ 1 MHz

TAVAV Read Cycle Time 90 ns @)

TAVQV Address Access Time 90 ns @)
TELQV Chip Enable Access Time 90 ns @)
TELQX Chip Enable Output Enable Time 5 ns @)
READ TGLQV Output Enable Output Enable Time 65 ns @)
CYCLE TGLQX Output Enable Output Enable Time 5 ns @)
TEHQZ Chip Enable Output Disable Time 50 ns @)
TGHQZ Output Enable Output Disable Time 40 ns @)
TAVQX Output Hold from Address Change 5 ns @)
TAVAV Write Cycle Time 90 ns @)
A.C. TELWH Chip Selection to End of Wrrte 55 ns @)
TAVWL Address Setup Time 10 ns @)
WRITE TWLWH Write Enable Pulse Width 55 ns @)
CYCLE TWHAV Write Enable Read Setup Time 10 ns @)
TGHQZ Output Enabie Output Disable Time 40 ns @)
TWLQZ Write Enable Output Disable Time 50 ns @)
TDVWH Data Setup Time 30 ns @)
TWHDX Data Hold Time 15 ns @)
TWHQX Write Enable Output Enable Time 0 ns @)
TWLEH Write Enable Pulse Setup Time 55 ns @)
TDVEH Chip Enable Data Setup Time 30 ns @)
TAVWH Address Valid to End of Write 80 ns @)
All devices tested at worst case limits.
Typical derating = 5mA/MHz increase in ICCOP; VI ~ VCC or GND.
Capacitance sampled and guaranteed - not 100% tested.
Input pulse levels: OV to 3.0V Input and Output timing reference levels: 1.5V
Input rise and fall times: 5 ns Output load: lTTL Gate and Cl ~ 100pF (including scope and jig)
 ABSOLUTE MAXIMUM RATINGS· OPERATING RANGE
Supply Voltage (Vee - GND) -0.3 to B.OV Operating Supply Voltage
Input or Output Voltage Applied (GND -0.3V) Military (- 2) 4.5V to 5.5V
to (Vee +0.3V) Operating Temperature
-we to 1500e Military (-2) - ssoe to + 125°e
• CAUTION:Stresses above/hose listed under "Absolute Maximum Ratings" may cause permanent damage/a the device. This Is a stress
only rating and lunctlonal operation 01 the device at these or at any other condlllons above/hose Indicated In the operational sections 01
/hls specification Is no/lmptled.

TEMP. & VCC =

OPERATING
RANGE <D TEST
SYMBOL PARAMETER MIN MAX UNITS CONOITIONS

ICCSS1 Standby Supply Current 1000 ".A 10 = O. r = VCC-0.3V

ICCSS Standby Supply Current 8 mA r= VIH.IO = 0
ICC Enabled Supply Current 70 mA E= VIL, 10 = 0
ICCOP Operating Supply Current ® 70 mA r = VIL, 10 = 0
1=1 MHz
ICCOR Oata Retention Supply Current 400 p.A 10 = 0, VCC = 2.0
E= VCC-0.3V
VCCOR Oata Retention Supply Voltage 2.0 V
II input Leakage Currenl -5.0 +5.0 ".A GNO",VI",VCC
IIOZ InpuVOutput Leakage Current -5.0 +5.0 ".A GNO",VIO"VCC
VIL Input Low Voltage -0.3 0.8 V
VIH Input High Voltage 2.2 VCC V
+0.3V
VOL Output Low Voltage 0.4 V 10 = 4.0mA
VOH Output High Voltage 2.4 V 10 = -1.0mA
CI Input Capacitance lID 8 pF VI = VCC or GNO,
f = 1 MHz
CIO InpUVOutput Capacitance lID 10 pF VIO = VCC or GNO,
f = 1 MHz

TAVAV Read Cycle Time 120 ns lD

TAVQV Address Access Time 120 ns lD
TELQV Chip Enable Access Time 120 ns lD
TELQX Chip Enable Output Enable Time 5 ns lD
READ TGLQV Oulput Enable Output Enable Time 80 ns lD
CYCLE TGLQX Output Enable Output Enabie Time 5 ns lD
TEHOZ Chip Enable Oulput Oisable Time 50 ns lD
TGHOZ Output Enable Output Oisable Time 40 ns lD
TAVax Output Hoid from Address Change 5 ns lD
TAVAV Write Cycle Time 120 ns lD
A.C. TELWH Chip Selection to End of Write 70 ns lD
TAVWL Address Setup Time 10 ns lD
WRITE TWLWH Write Enable Pulse Width 70 ns lD
CYCLE TWHAV Write Enable Read Setup Time 10 ns lD
TGHQZ Output Enable Output Oisable Time 40 ns lD
TWLOZ Write Enable Outpul Oisable Time 50 ns lD
TOVWH Oala Selup Time 35 ns lD
TWHOX Oata Hold Time 15 ns lD
TWHQX Write Enable Output Enable Time 0 ns lD
TWLEH Write Enable Pulse Selup Time 70 ns lD
TOVEH Chip Enable Oata Setup Time 35 ns lD
TAVWH Address Valid to End of Write 105 ns lD
All devices tested at worst case limits.
Typical derating = SmA/MHz increase in ICCOP; VI = VCC or GNO.
Capacitance sampled and guaranteed - not 100% tested.
Input pulse leveis: OV to 3.0V Input and Output timing reference levels: 1.5V
Input rise and fall times: 5 ns Output load: lTIL Gale and Cl = 100pF (including scope and jig)
 ABSOLUTE MAXIMUM RATINGS· OPERATING RANGE
Supply Voltage (VCC - GND) -0.3 to 8.0V Operating Supply Voltage
Input or Output Voltage Applied (GND -0.3V) Industrial (- 9)
to (VCC +0.3V) Operating Temperature
- 65°C to 150°C Industrial (-9)
* CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
only rating and functional operation of the device at these or at any other conditions above those indicated in the operational sections of
this specification is not implied.

TEMP. &0 VCC =

OPERATING
RANGE<D TEST
SYMBOL PARAMETER MIN MAX UNITS CONDITIONS

ICCSS1 Standby Supply Current 100 p.A 10 = 0, E = VCC-0.3V

ICCSS Standby Supply Current 8 mA r = VIH, 10 = 0

ICC Enabled Supply Current 70 mA r = VIL, 10 = 0

ICCOP Operating Supply Current ® 70 mA r= VIL, 10 0=
1=1 MHz

ICCOR Oata Retention Supply Current 40 p.A 10 = 0, VCC = 2.0

f = VCC-0.3V
VCCOR Oata Retention Supply Voltage 2.0 V
II Input Leakage Current -1.0 +1.0 p.A GND"VI"VCC
1I0Z InpuUOutput Leakage Current -1.0 +1.0 p.A GND"VIO"VCC
VIL Input Low Voltage -03 0.8 V
VIH Input High Voltage 2.4 VCC V
+0.3V
VOL Output Low Voltage 0.4 V 10 = 4.0mA
VOH Output High Voltage 2.4 V 10 = -1.0mA

CI Input Capacitance ® 8 pF VI = VCC or GND,

f =,MHz
CID InpuUDutput Capacitance ® 10 pF VIO = VCC or GND,
f = 1 MHz

TAVAV Read Cycle Time 55 ns @)

TAVQV Address Access Time 55 ns @)
TELQV Chip Enable Access Time 5S ns @)
TELQX Chip Enable Output Enable Time 5 ns @)
READ TGLQV Output Enable Output Enable Time 35 ns @)
CYCLE TGLQX Output Enable Output Enable Time 5 ns @)
TEHQZ Chip Enable Output Disable Time 30 ns @)
TGHQZ Output Enable Output Disable Time 25 ns @)
TAVQX Output Hold from Address Change 5 ns @)

TAVAV Write Cycle Time 55 ns @)

TELWH Chip Selection to End of Write 45 ns @)
TAVWL Address Setup Time 5 ns @)
WRITE TWLWH Write Enable Pulse Width 35 ns @)
CYCLE TWHAV Write Enable Read Setup Time 10 ns @)
TGHQZ Output Enable Output Disable Time 25 ns @)
TWLQZ Write Enable Output Disable Time 25 ns @)
TDVWH Data Setup Time 25 ns @)
TWHDX Data Hold Time 10 ns @)
TWHQX Write Enable Output Enable Time 0 ns @)
TWLEH Write Enable Pulse Setup Time 50 ns @)
TDVEH Chip Enable Data Setup Time 25 ns @)
TAVWH Address Valid to End of Write 50 ns @)

All devices tested at worst case limits.

Typical derating = 5mA/MHz increase in ICCOP; VI ~ VCC or GND.
Capacitance sampled and guaranteed - not 100% tested.
Input pulse levels: OV to 3.0V Input and Output timing reference levels: 1.5V
Input llse and fall times: 5 ns Output load: lTTL Gate and CL = 100pF (including scope and jig)
 (GND -O.3V) I-ridustrial (-gi .
to (VCC +O.3V) Operating Temperature
-65°C to 150°C Industrial (-9)
* CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
only rating and funcI'onal operation of the device at these or at any other conditions above those indicated in the operational sections of
this specification is not implied.

TEMP. & VCC =

OPERATING
RANGE<D TEST
SYMBOL PARAMETER MIN MAX UNITS CONOITIONS

ICCSB1 Standby Supply Current 50 !,-A 10 = 0, E = VCC-0.3V

ICCSB Standby Supply Current 8 mA I = VIH, 10 = 0
ICC Enabled Supply Current 70 mA f ~VIL, 10 = 0
ICCOP Operating Supply Current ® 70 mA f = VIL, 10 = 0
f = 1 MHz
ICCOR Data Retention Supply Current 20 !,-A 10 = 0, VCC = 2.0
f= VCC-0.3V
VCCOR Oata Retention Supply Voltage 2.0 V
II Input Leakage Current -1.0 +1.0 !,-A GNO"VI"VCC
IIOZ InpuUOutput Leakage Current -1.0 +1.0 !,-A GNO"VIO"VCC
VIL Input Low Voltage -0.3 O.B V
VIH Input High Voltage 2.2 VCC V
+0.3V
VOL Output Low Voltage 0.4 V 10 = 4.0mA
VOH Output High Voltage 2.4 V 10 = -1.0mA
CI Input Capacitance ® B pF VI = VCC or GNO,
f = 1 MHz
CIO InpuUOutput Capacitance ® 10 pF VIO = VCC or GNO,
t = 1 MHz

TAVAV Read Cycle Time 70 ns @)

TAVOV Address Access Time 70 ns @)
TELQV Chi~ Enable Access Time 70 ns @)
TELQX Chip Enable Output Enable Time 5 ns @)
READ TGLQV Output Enable Output Enable Time 50 ns @)
CYCLE TGLQX Output Enable Output Enable Time 5 ns @)
TEHQZ Chip Enable Output Disable Timn 35 ns @)
TGHQZ Output Enable Output Disable Time 35 ns @)
TAVQX Output Hold from Address Change 5 ns @)
TAVAV Write Cycle Time 70 ns @)
A.C. TELWH Chip Selection to End of Write 45 ns @)
TAVWL Address Setup Time 10 ns @)
WRITE TWLWH Write Enable Pulse Width 40 ns @)
CYCLE TWHAV Write Enable Read Setup Time 10 ns @)
TGHOZ Output Enable Output Disable Time 35 ns @)
TWLQZ Write Enable Output Oisable Time 40 ns @)
TDVWH Oata Setup Time 30 ns @)
TWHOX Data Hold Time 10 ns @)
TWHQX Write Enable Output Enable Time 0 ns @)
TWLEH Write Enable Pulse Setup Time 40 ns @)
TDVEH Chip Enable Data Setup Time 30 ns @)
TAVWH Address Valid to End ot Write 65 ns @)
All devices tested at worst case limits.
Typical derating = 5mA/MHz increase in ICCOP; VI = VCC or GND.
Capacitance sampled and guaranteed - not 100% tested.
Input pulse levels: OV to 3.0V Input and Output timing reference levels: 1.5V
Input rise and fall times: 5 ns Output load: lTTL Gate and Cl =
100pF (including scope and iig)
 ABSOLUTE MAXIMUM RATINGS' OPERATING RANGE
Supply Voltage (VCC - GND) -0.3 to 8.0V Operating Supply Voltage
Input or Output Voltage Applied (GND -0.3V) Industrial (-9)
to (VCC +0.3V) Operating Temperature
- 65°C to 150°C Industrial (-9)

• CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
only rating and functional operation of the device at these or at any other conditions above those indicated ;n the operational sections of
this specification is not implied.

TEMP. & VCC ~

OPERATING
RANGE TEST
SYMBOL PARAMETER MIN MAX UNITS CONDITIONS

ICCSSl Standby Supply Current 100 IJ.A 10 = 0, E = VCC-0.3V

Icess Standby Supply Current S mA I= VIH, 10 = 0
ICC Enabled Supply Current 70 mA I= VIL, 10 = 0
ICCOP Operating Supply Current 70 mA E= VIL, 10 = 0
f = 1 MHz
ICCOR Data Retention Supply Current 40 IJ.A 10 = 0, VCC = 2.0
I= VCC-0.3V
VCCDR Data Retention Supply Voltage 2.0 V
II Input Leakage Current -1.0 +1.0 IJ.A GND"VI"VCC
1I0Z Input/Output Leakage Current -10 +1.0 IJ.A GND"VIO"VCC
VIL Input Low Voltage -03 08 V
VIH Input High Voltage 2.2 VCC V
+0.3V
VOL Output Low Voltage 0.4 V 10 = 4.0mA
VOH Output High Voltage 2.4 V 10 = -1.0mA
CI Input Capacitance 8 pF VI = VCC or GND,
f= 1 MHz
CIO InpuVOutput Capacitance 10 pF VIO = VCC or GND,
f = 1 MHz

TAVAV Read Cycle Time 90 ns @)

TAVOV Address Access Time 90 ns @)
TELOV Chip Enable Access Time 90 ns @)
TELOX Chip Enable Output Enable Time 5 ns @)
REAO TGLOV Output Enable Output Enable Time 65 ns @)
CYCLE TGLOX Output Enable Output Enable Time 5 ns @)
TEHOZ Chip Enable Output Disable Time 50 ns @)
TGHOZ Output Enable Output Disable Time 40 ns @)
TAVOX Output Hold from Address Change 5 ns @)
TAVAV Write Cycle Time 90 ns @)
TELWH Chip Selection to End of Write 55 ns @)
TAVWL Address Setup Time 10 ns @)
WRITE TWLWH Write Enable Pulse Width 55 ns @)
CYCLE TWHAV Write Enable Read Setup Time 10 ns @)
TGHOZ Output Enable Output Disable Time 40 ns @)
TWLOZ Write Enable Output Disable Time 50 ns @)
TDVWH Data Setup Time 30 ns @)
TWHDX Data Hold Time 15 ns @)
TWHOX Write Enable Output Enable Time 0 ns @)
TWLEH Write Enable Pulse Setup Time 55 ns @)
TDVEH Chip Enable Data Setup Time 30 ns @)
TAVWH Address Valid to End of Write 80 ns @)
All devices tested at worst case limits.
Typical derating = SmA/MHz increase in Iceop; VI = VCC or GND.
Capacitance sampled and guaranteed - not 100% tested.
Input pulse levels: OV to 3.0V Input and Output timing reference levels: 1.5V
Input rise and fall times: 5 ns Output load: lTTL Gate and Cl ~ 100pF (including scope and jig)
 ABSOLUTE MAXIMUM RATINGS' OPERATING RANGE
Supply Voltage (Vee - GNO) -0.3 to 8.0V Operating Supply Voltage
Input or Output Voltage Applied (GNO -0.3V) Industrial (-9)
to (Vee +0.3V) Operating Temperature
-we to 1500e Industrial (-9)
• CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
only rating and functional operation of the device at these or at any other conditions above those indicated in the operational sections at
this specification is not implied.

TEMP. & VCC =

OPERATING
RANGE <D TEST
SYMBOL PARAMETER MIN MAX UNITS CONOITIONS

ICCSB1 Standby Supply Current 1000 !LA 10 = o. I ~ VCC-0.3V

ICCSB Standby Supply Current 8 mA I ~ VIH, 10 = 0
ICC Enabled Supply Current 70 mA f ~VIL, 10 = 0
ICCO? Operating Supply Current ® 70 mA f ~VIL, 10 = 0
, ~ 1 MHz

ICCOR Data Retention Supply Current 400 }LA 10 ~ 0, VCC = 2.0

E= VCC-0.3V
VCCOR Data Retention Supply Voltage 2.0 V
Ii Input Leakage Current -5.0 +5.0 !LA GNO",VI",VCC
1t0Z InpuVOutput Leakage Current -5.0 +5.0 }LA GNO",VIO",VCC
VIL Input Low Voltage -0.3 0.8 V
VIH Input High Voltage 2.2 VCC V
+0.3V
VOL Output Low Voltage 0.4 V 10 ~ 4.0mA
VOH Output High Voltage 2.4 V 10 ~ -1.0mA

CI Input Capacitance ® 8 pF VI ~ VCC or GNO,

t ~ 1 MHz
CIO InpuVOutput Capacitance ® 10 pF VIO ~ VCC or GNO,
t~1MHz

TAVAV Read Cycle Time 90 ns @)

TAVQV Address Access Time 90 ns @)
TELQV Chip Enable Access Time 90 ns @)
TELQX Chip Enable Output Enable Time 5 ns @)
READ TGLQV Output Enable Output Enable Time 65 ns @)
CYCLE TGLQX Output Enable Output Enable Time 5 ns @)
TEHOZ Chip Enable Output Disable Time 50 ns @)
TGHOZ Output Enable Output Disable Time 40 ns @)
TAVQX Output Hold from Address Change 5 ns @)

TAVAV Write Cycle Time 90 ns @)

A.C. TELWH Chip Selection to End of Write 55 ns @)
TAVWL Address Setup Time 10 ns @)
WRITE TWLWH Write Enable Pulse Width 55 ns @)
CYCLE TWHAV Write Enable Read Setup Time 10 ns @)
TGHQZ Output Enable Output Disable Time 40 ns @)
TWLQZ Write Enable Output Disable Time 50 ns @)
TOVWH Data Setup Time 30 ns @)
TWHOX Data Hold Time 10 ns @)
TWHQX Write Enable Output Enable Time 0 ns @)
TWLEH Write Enable purse Setup Time 55 ns @)
TOVEH Chip Enable Data Setup Time 30 ns @)
TAVWH Address Valid to End of Write 80 ns @)
All devices tested at worst case limits.
Typical derating ~ 5mA/MHz increase in ICCOP: VI = VCC or GNO.
Capacitance sampled and guaranteed - not 100% tested.
Input pulse levels: OV to 3.0V Input and Output timing reference levels: 1.5V
Input rise and lalltimes: 5 ns Output load: nTL Gate and CL ~ 1OOpF (including scope and iig)
 ABSOLUTE MAXIMUM RATINGS· OPERATING RANGE
Supply Voltage (VCC • GND) -0.3 to B.OV Operating Supply Voltage
Input or Output Voltage Applied (GND -0.3V) Commercial (-5) 4.5V to 5.5V
to (VCC +0.3V) Operating Temperature
- SSOCto 150°C Commercial (-5) O°Cto + 70°C
• CAUTION:Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This Is a stress
only rating and functional operation of the device at these or at any other conditions above those Indicated In the operational sections of
this specillcatlon Is not Implied.

TEMP. & vee =

OPERATING
RANGE Q) TEST
SYMBOL Pl\RAMETER MIN MAX UNITS eONDInONS

ICCSS1 Standby Supply Current 100 p.A 10 = 0, r. VCC-0.3V

ICCSS Standby Supply Current 8 mA T. VIH, 10·0
ICC Enabled Supply Current 70 mA E. VIL, 10.0
ICCOP Operating Supply Current <D 70 mA r= VIL, 10·0
f = 1 MHz
ICCOR Oata Retention Supply Current 40 p.A 10 • 0, VCC = 2.0
T = VCC-0.3V
VCCOR Oata Retention Supply Voltage 2.0 V
II Input Leakage Current -1.0 +1.0 p.A GND",VI",VCC
1I0Z Input/Output Leakage Current -1.0 +1.0 p.A GND",VIO"'VCC
VIL Input Low Voltage -0.3 0.8 V
VIH Input High Voltage 2.4 vcc V
+0.3V
VOL Output Low Voltage 0.4 V 10·4.0mA
VOH Output High Voltage 2.4 V = -1.0mA
10
CI Input Capacitance lID 8 pF = VCC or GND,
VI
f = 1 MHz
CIO Input/Output Capacitance lID 10 pF VIO = VCC or GND,
f = 1 MHz

TAVAV Read Cycle Time 55 ns CD

TAVOV Address Access Time 55 ns CD
TELOV Chip Enable Access Time 55 ns CD
TELOX Chip Enable Output Enable Time 5 ns CD
READ TGLOV Output Enable Output Enable Time 35 ns CD
CYCLE TGLOX Output Enable Output Enable Time 5 ns CD
TEHOZ Chip Enable Output Disable Time 30 ns CD
TGHOZ Output Enable Output Disable Time 25 ns CD
TAVax Output Hold from Address Change 5 ns CD
TAVAV Write Cycle Time 55 ns CD
TELWH Chip Selection to End of Write 45 ns eD
TAVWL Address Setup Time 5 ns eD
WRITE TWLWH Write Enable Pulse Width 35 ns CD
CYCLE TWHAV Write Enable Read Setup Time 10 ns CD
TGHOZ Output Enable Output Disable Time 25 ns eD
TWLOZ Write Enable Output Disable Time 25 ns eD
TDVWH Data Setup Time 25 ns eD
TWHDX Data Hold Time 10 ns eD
TWHOX Write Enable Output Enable Time 0 ns eD
TWLEH Write Enable Pulse Setup Time 50 ns CD
TDVEH Chip Enable Data Setup Time 25 ns CD
TAVWH Address valid to End of Write 50 ns eD
All devices tested at worst case limits.
Typical deraling = SmA/MHz increase in ICCOP; VI ~ VCC or GND.
Capacitance sampled and guaranteed - not 100% tested.
Input pulse levels: OV to 3.0V Input and Output timing reference levels: 1.5V
Input rise and fall times: 5 ns Output load: 1nL Gate and Cl =
100pF (inclUding scope and jig)
 ABSOLUTE MAXIMUM RATINGS' OPERATING RANGE
Supply Voltage (VCC - GND) -0.3 to 8.0V Operating Supply Voltage
Input or Output Voltage Applied (GND -O.3V) Commercial (-5) 4.5V to 5.5V
to (VCC +O.3V) Operating Temperature
- WC to 150°C Commercial (-5) O°Cto +70°C
• CAlfT/ON: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
only rating and functional operation of the device at these or at any other conditions above those indicated in the operational sections of
this specification is not implied.

TEMP. & VCC =

OPERATING
RANGE <D TEST
SYMBOL PARAMETER MIN MAX UNITS CONOITIONS

ICCSBl Standby Supply Current 50 I'A 10 ~ 0, E ~ VCC-0.3V

ICCSB Standby Supply Current 8 mA E ~ VIH.IO ~ 0
ICC Enabled Supply Current 70 mA E = VIL, 10 ~ 0
ICCOP Operating Supply Current ® 70 mA E~ VIL, 10 ~ 0
f ~ 1 MHz
ICCOR Oata Retention Supply Current 20 ~ 10 ~ 0, VCC ~ 2.0
E~ VCC-0.3V
VCCOR Oata Retention Supply Voltage 2.0 V
II Input Leakage Current -1.0 +1.0 I'A GND"VI"VCC
IIOZ InpuUOutput Leakage Current -1.0 +1.0 I'A GND"VIO"VCC
VIL Input Low Voltage -0.3 0.8 V
VIH Input High Voltage 2.2 VCC V
+0.3V
VOL Output Low Vollage 0.4 V 10 ~ 4.0mA
VOH Output High Voltage 2.4 V 10 = -1.0mA
CI Input Capacitance ® 8 pF VI ~ VCC or GND,
f = 1 MHz
CIO InpuUOutput Capacitance ® 10 pF VIO ~ VCC or GND,
f ~ 1 MHz

TAVAV Read Cycle Time 70 ns @)

TAVOV Address Access Time 70 ns @)
TELQV Chip Enable Access Time 70 ns @)
TELQX Chip Enable Output Enable Time 5 ns @)
REAO TGLQV Output Enable Output Enable Time 50 ns @)
CYCLE TGLQX Output Enable Output Enable Time 5 ns @)
TEHQZ Chip Enable Output Disable Time 35 ns @)
TGHQZ Output Enable Output Disable Time 35 ns @)
TAVQX Output Hold from Address Change 5 ns @)

TAVAV Write Cycle Time 70 ns @)

A.C. TELWH Chip Selection fa End of Write 45 ns @)
TAVWL Address Setup Time 10 ns @)
WRITE TWLWH Write Enable Pulse Width 40 ns @)
CYCLE TWHAV Write Enable Read Setup Time 10 ns @)
TGHQZ Output Enable Output Disable Time 35 ns @)
TWLQZ Write Enable Output Disable Time 40 ns @)
TDVWH Data Setup Time 30 ns @)
TWHDX Data Hold Time 10 ns @)
TWHQX Write Enable Output Enable Time 0 ns @)
TWLEH Write Enable Pulse Setup Time 40 ns @)
TDVEH Chip Enable Data Setup Time 30 ns @)
TAVWH Address Valid to End of Write 65 ns @)

All devices tested at worst case limits.

Typical derating = 5mA/MHz increase in ICCOP; VI = VCC or GND.
Capacitance sampled and guaranteed - not 100% tested.
Input pulse levels: OV to 3.0V Input and Output timing reference levels: 1.5V
Input rise and fall times: 5 ns Output load: lTTL Gate and CL = 100pF (including scope and jig)
 ABSOLUTE MAXIMUM RATINGS· OPERATING RANGE
Supply Voltage (VCC - GND) -0.3 to 8.0V Operating Supply Voltage
Input or Output Voltage Applied (GND -0.3V) Commercial (-5) 4.5V to 5.5V
to (VCC +0.3V) Operating Temperature
- 65°C to 150°C Commercial (-5) O°Cto + lO°C
• CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanenl damage to the device. This is a slress
only rating and functional operation of the device at these or at any other conditions above those indicated in the operational sections of
this specification is not implied.

TEMP. & VCC =

OPERATING
RANGE <D TEST
SYMBOL PARAMETER MIN MAX UNITS CONOITIONS

ICCSSl Standby Supply Current 100 j.A 10 ~ 0, E ~ VCC-0.3V

ICCSS Standby Supply Current 8 mA E ~ VIH, 10 = 0
ICC Enabled Supply Current 70 mA E~ VIL,IO ~ 0
ICCOP Operating Supply Current ® 70 mA E ~ VIL,IO ~ 0
f = 1 MHz
ICCDR Data Retention Supply Current 40 I'A 10 ~ 0, VCC ~ 2.0
E= VCC-0.3V
VCCDR Data Retention Supply Vollage 2.0 V
II Input Leakage Current -1.0 +1.0 j.A GND",VI",VCC
1I0Z InpuVOutput Leakage Current -1.0 +1.0 I'A GNO",VIQ",VCC
VIL Input Low Voltage -0.3 0.8 V
VIH Input High Vollage 2.2 VCC V
+0.3V
VOL Output Low Voltage 0.4 V 10 ~ 4.0mA
VOH Outpul High Voltage 2.4 V 10 = -1.0mA
CI Input Capacitance ® 8 pF VI ~ VCC or GNO,
f ~ 1 MHz
CIO InpuVDutput Capacilance ® 10 pF VIO ~ VCC or GND,
1 = 1 MHz
TAVAV Read Cycle Time 90 ns @)
TAVOV Address Access Time 90 ns @)
TELOV Chip Enable Access Time 90 ns @)
TELOX Chip Enable Output Enable Time 5 ns @)
READ TGLOV Output Enable Output Enable Time 65 ns @)
CYCLE TGLOX Output Enable Output Enable Time 5 ns @)
TEHOZ Chip Enable Output Disable Time 50 ns @)
TGHOZ Outpul Enable Outpul Disable Time 40 ns @)
TAVOX Outpul Hold from Address Change 5 ns @)
TAVAV Write Cycle Time 90 ns @)
TELWH Chip Selection 10 End 01 Write 55 ns @)
TAVWL Address Setup Time 10 ns @)
WRITE TWLWH Write Enable Pulse Width 55 ns @)
CYCLE TWHAV Write Enable Read Setup Time 10 ns @)
TGHOZ Oulput Enable Output Disable Time 40 ns @)
TWLOZ Write Enable Oulput Disable Time 50 ns @)
TDVWH Data Setup Time 30 ns @)
TWHDX Data Hold Time 15 ns @)
TWHOX Wrile Enable Oulput Enable Time 0 ns @)
TWLEH Write Enable Pulse Setup Time 55 ns @)
TDVEH Chip Enable Data Setup Time 30 ns @)
TAVWH Address Valid to End 01 Write 80 ns @)
All devices tested at worst case limits.
Typical deraling ~ 5mNMHz increase in ICCOP; VI ~ VCC or GND.
Capacitance sampled and guaranteed - not 100% tested.
Input pulse levels: OV to 3.0V Input and Output timing reference levels: 1.5V
Inpul rise and fall times: 5 ns Dulpulload: lTTL Gate and Cl ~ 100pF (including scope and iig)
Addresses must remain stable for the duration of the read cycle. To read cycles, t may be tied low continuously until all desired locations
read,G andE must be", VILandW;o. VIH. The output buffers can be are accessed. When tis low. addresses must be driven by stable logic
controlled independently by G while Eis low. To execute consecutive levels and must not be in the high impedance state.

TDVWH
TAVWH

To write. addresses must be stable. E low and W falling low for a the outputs must not be apl1.!!ed.(Bus contention). If Etransitions lo~
period n..Q..shorterthan TWLWH. Data in is referenced with the risi~ simultaneously with the W line transitionlng low or after the W
edge of W. (TDVWH and TWHDX). While addresses are changing, W transition, the output will remain in a high impedance state. G is held
must be high. When W falls low, the \/0 pins are still in the output continuously low.
state for a period of TWLQZ and input data of the opposite phase to
 Write Cycle /I

TAVAV

In this write cycle G has control of the output after a period, TGHQZ.
G switching the output to a high impedance state allows data in to be
applied without bus contention after TGHQZ. When W transitions
high, the data in can change afterTWHDX to complete the write cycle.
 Pinouts
• FAST ACCESS TIME 55170/90/120 ns MAX TOP VIEW
• LOW STANOBY CURRENT 50~A MAX
1 24 VCC
• LOW OPERATING CURRENT 70 mA MAX
2 23 A8
• OATA [email protected] 20~A MAX PIN NAMES
3 22 A9
• TTL COMPATIBLE INPUTS ANO OUTPUTS
• TOSHIBA 5516/HITACHI 6117 PINOUT - TWO CHIP ENABLE INPUTS
4 21 iN A Address Input
• NO CLOCKS OR STROBES REQUIREO
5 20E; DO Data Input/Output
• WIDE TEMPERATURE RANGE 6
7
19
18
A10
f,
['E; Chip Enable
• EQUAL CYCLE ANO ACCESS TIME
• SINGLE 5 VOLT SUPPLY
8 17 OQ7 Vi Write Enable
• GATEO INPUTS - NO PULL·UP OR PULL·OOWN
9 16 OQ6 NC No Connect
10 15 DQ5
RESISTORS ARE REQUIREO
11 14 OQ4
12 13 OQ3

Description
The HM-65172 is a CMOS 2048 x 8 Static Random Access Memory manufac-
tured using the HARRIS advanced SAJI V process. The device utilizes asyn-
chronous circuit design for fast cycle time and ease of use. The pinout Is a
24-pin, industry standard which ailows easy memory board layouts flexible to
accommodate a variety of industry standard PROMs, RAMs, ROMs and EPROMs.
The HM-65172 is ideally suited for use in microprocessor based systems with its
8 bit word iength organization. Gated inputs lower operating current and also
eliminate the need for puli-up or pull-down resistors. The HM-65172 features two
chip enables; E, for fast memory access and E; for low power applications where
battery operation or battery back-up for nonvolatility are required.

Functional Diagram
A1
AI-
A2-- ROW
A3-- ADD- 7 ROW
RESS DE- 128 X 128
A4--
A5-- BUFFER CODER ~8 MEMORY ARRAY
A6-- AI-
A7 7
DOD
1- THRU
I 8007
I
I
 ABSOLUTE MAXIMUM RATINGS· OPERATING RANGE
Supply Voltage (VCC - GND) - 0.3 to 8.0V Operating Supply Voltage
Input or Output Voltage Applied (GND -0.3V) Military (-2)
to (VCC + O.3V) Operating Temperature
Storage Temperature - 65°C to 150°C Military (- 2) - 55°Cto + 125°C
'CAUTlON: Stresses above those listed under "Absolute Maximum Ralings" may cause permanent damage to the device.
This is a stress only rating and functional operation of the device at these or at any other conditions above those indicated in the
operational sections of this specification is not implied.

TEMP. & VCC =

OPERATING
RANGE(j)
TEST
SYMBOL PARAMETER MIN MAX UNITS CONDITIONS

ICCSS1 Standby Supply Current 50 pA Ez = VCC-0.2V

OTHER INPUTS =
0.2V or VCC-0.2V
ICC Enabled Supply Current 70 mA E" E; = VIL. 10 = 0
ICCOP Operating Supply Current ® 70 mA E" E; = VIL, 10 = 0
f = 1 MHz
ICCDR Data Retention Supply Current 20 pA 10 = 0, VCC = 2.0
E,. E; = VCC-03V
VCCDR Data Retention Supply Voltage 2.0 V
II Input Leakage Current -1.0 +1.0 pA GNDsVlsVCC
1I0Z Input/Output Leakage Current -1.0 +1.0 pA GNDsVIOsVCC
VIL Input Low Voltage -0.3 +0.8 V
VIH Input High Voltage 2.2 VCC V
+0.3 V
VOL Output Low Voltage 0.4 V 10 = 4.0mA
VOH Output High Voltage 2.4 V 10 = -1.0mA
CI Input Capacitance ill 8 pF VI = VCC or GND,
f = 1 MHz
CIO Input/Output Capacitance ill 10 pF via = VCC or GNO,
f = 1 MHz

TAVAV Read Cycle Time 70 ns 0

TAVQV Address Access Time 70 ns 0
TE1LQV E, to Output Valid 40 ns 0
TE2LQV E; to Output Valid 70 ns 0
READ TE1LQX E, to Output in Low Z 0 ns 0
CYCLE TE2LQX E; to Output in Low Z 0 ns 0
TE1HQZ E, Disable to Output in High Z 35 ns 0
TE2HQZ E; Disable to Output in High Z 40 ns 0
TAVQX Output Hold from Address Change 5 ns 0
TAVAV Write Cycle Time 70 ns 0
TE1LWH E, to End of Write 45 ns 0
TE2LWH E; to End of Write 50 ns 0
WRITE TAVWL Address Setup Time 10 ns 0
CYCLE TAVWH Address Valid to End of Write 65 ns 0
TWLWH Write Pulse Width 40 ns 0
TWHAV Write Recovery Time 10 ns 0
TWLQZ Write to Output in High Z 40 ns 0
TDVWH Data to Write Time Overlap 30 ns 0
TWHDX Data Hold from Write Time 15 ns 0
TWHQX Output Active from End of Write 0 ns 0
(j) All devices tested at worst case limits.
® Typical derating = 5mA/MHz increase in ICCOP; VI = VCC or GND.
® Capacitance sampled and guaranteed - not 100% tested.
o Input pulse levels: OV to 3.0V Input and Output timing reference levels: 1.5V
Input rise and fall times: 5 ns Qutput load: 1TTL Gate and Cl = 100pF (Including scope and jig)
 ABSOLUTE MAXIMUM RATINGS· OPERATING RANGE
Supply Voltage (VCC· GND) -0.3 to 8.0V Operating Supply Voltage
Input or Output Voltage Applied (GND -0.3V) Military (-2)
to (VCC + 0.3V) Operating Temperature
Storage Temperature -65°C to 150°C Military (- 2) - 55°C to + 125°C
·CAUTlON: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress only rating and functional operation of the device at these or at any other conditions above those indicated in the
operational sections of this specification is not implied.

TEMP. & VCC =

OPERATING
RANGE CD
TEST
SYMBOL PARAMETER MIN MAX UNITS CONDITIONS

ICCSBl Standby Supply Current 100 pA Ez = VCC-0.2V

OTHER INPUTS =
0.2V or VCC-0.2V
ICC Enabled Supply Current 70 mA E" E2 = VIL. 10 = 0
ICCOP Operating Supply Current ® 70 mA E" E2 = VIL, 10 = a
f = 1 MHz
ICCDR Data Retention Supply Current 40 pA 10 = 0, VCC = 2.0
E" E2 = VCC-0.3V
VCCDR Data Retention Supply Voltage 2.0 V
II Input Leakage Current -1.0 +1.0 pA GNDsVlsVCC
1I0Z Input/Output Leakage Current -1.0 +1.0 pA GNDsVIOsVCC
VIL Input Low Voltage -0.3 +0.8 V
VIH Input High Voltage 2.2 VCC V
+0.3 V
VOL Output Low Voltage 0.4 V 10 = 4.0mA
VOH Output High Voltage 2.4 V 10= -1.0mA
CI Input Capacitance ® 8 pF VI = VCC or GND,
f = 1 MHz
cia Input/Output Capacitance ® 10 pF via = VCC or GND,
f = 1 MHz

TAVAV Read Cycle Time 90 ns @

TAVQV Address Access Time 90 ns @
TE1LQV E, to Output Valid 70 ns @
TE2LQV E2 to Output Valid 90 ns @
READ TE1LQX E, to Output in Low Z 0 ns @
CYCLE TE2LQX E2 to Output in Low Z 0 ns @
TE1HQZ E, Disable to Output in High Z 45 ns @
TE2HQZ E2 Disable to Output in High Z 50 ns @
TAVQX Output Hold from Address Change 5 ns @
TAVAV Write Cycle Time 90 ns @
TE1LWH E, to End of Write 55 ns @
TE2LWH E2 to End of Write 60 ns @
WRITE TAVWL Address Setup Time 10 ns @
CYCLE TAVWH Address Valid to End of Write 80 ns @
TWLWH Write Pulse Width 55 ns @
TWHAV Write Recovery Time 10 ns @
TWLQZ Write to Output in High Z 50 ns @
TDVWH Data to Write Time Overlap 30 ns @
TWHDX Data Hold from Write Time 15 ns @
TWHQX Output Active from End of Write 0 ns @

CD All devices tested at worst case limits.

® Typical derating = 5mA/MHz increase in ICCOP; VI = VCC or GND.
® Capacitance sampled and guaranteed· not 100% tested.
@ Input pulse levels: OV to 3.0V Input and Output timing reference levels: 1.5V
Input rise and fall times: 5 ns Output load: lTTL Gate and Cl = 100pF (including scope and jig)
 ABSOLUTE MAXIMUM RATINGS· OPERATING RANGE
Supply Voltage (VCC· GND) -O.3t08.0V Operating Supply Voltage
Input or Output VoltageApplied (GNO -O.3V) Military (-2)
to (VCC + O.3V) Operating Temperature
Storage Temperature - 65°C to 150°C Military (- 2) - 55°C to + 125°C
'CAUTlON: Stresses above those listed under' 'Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress only rating and functional operation of the device at these or at any other conditions above those indicated in the
operalional sections of this specification is not Implied.

TEMP. & VCC s

OPERATING
RANGEG)
TEST
SYMBOL PARAMETER MIN MAX UNITS CONDITIONS

ICCSBl Standby Supply Current 1000 p.A E2 • VCC-0.2V

OTHER INPUTS.
0.2V or VCC-0.2V
ICC Enabled Supply Current 70 mA E" Ei • Vil. 10 = 0
ICCOP Operating Supply Current ® 70 mA E" Ei = Vll, 10 = 0
f = 1 MHz
ICCOR Data Retention Supply Current 400 p.A 10 = 0, VCC = 2.0
E" Ei = VCC-0.3V
VCCDR Data Retention Supply Voltage 2.0 V
II Input leakage Current -5.0 +5.0 p.A GND s VI s VCC
1I0Z Input/Output leakage Current -5.0 +5.0 p.A GNDsVIOsVCC
Vil Input low Voltage -0.3 +O.B V
VIH Input High Voltage 2.2 VCC V
+0.3 V
VOL Output low Voltage
0.4 V 10 = 4.0mA
VOH Output High Voltage 2.4 V 10 = -1.0mA
CI Input Capacitance ® 8 pF VI = VCC or GND,
f = 1 MHz
CIO Input/Output Capacitance ® 10 pF VIO = VCC or GND,
f = 1 MHz

TAVAV Read Cycle Time 120 ns ®

TAVOV Address Access Time 120 ns ®
TEll0V E, to Output Valid 100 ns ®
TE2l0V Ei to Output Valid 120 ns ®
READ TEll0X E, to Output In low Z 0 ns ®
CYCLE TE2l0X Ei to Output In low Z 0 ns ®
TE1HOZ E, Olsable to Output In High Z 45 ns ®
TE2HOZ Ei Disable to Output In High Z 50 ns ®
TAVOX Output Hold from Address Change 5 ns ®
TAVAV Write Cycle Time 120 ns ®
TE1LWH E, to End of Write 65 ns ®
TE2lWH Ei to End of Write 70 ns ®
WRITE TAVWL Address Setup Time 10 ns ®
CYCLE TAVWH Address Valid to End of Write 105 ns ®
TWlWH Write Pulse Width 70 ns ®
TWHAV Write Recovery Time 10 ns ®
TWlOZ Write to Output In High Z 50 ns ®
TOVWH Data to Write Time Overlap 35 ns ®
TWHDX Data Hold from Write Time 15 ns ®
TWHOX Output Active from End of Write 0 ns ®
NOTES: G) All devices tested at worst case limits.
® Typical derating = 5mA/MHz Increase In ICCOP; VI = VCC or GND.
@ Capacitance sampled and guaranteed - not 100% tested.
® Input pulse levels: OV to 3.0V Input and Output timing reference levels: 1.5V
Input rise and fall times: 5 ns Output load: 1TTl Gate and CL = 100pF (Including scope and jig)
 ABSOLUTE MAXIMUM RATINGS· OPERATING RANGE
Supply Voltage (VCC - GND) -0.3 to 8.0V Operating Supply Voltage
Input or Output Voltage Applied (GND -O.3V) Industrial (-9)
to (VCC + O.3V) Operating Temperature
Storage Temperature -65°Cto 150°C Industrial (-9) -40°Cto +85°C
·CAUTlON: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress only raling and functional operalion of the device at these or at any other conditions above those indicated in the
operational sections of this specification is not implied.

TEMP. & VCC =

OPERATING
RANGE(1)
TEST
SYMBOL PARAMETER MIN MAX UNITS CONOITIONS

ICCSS1 Standby Supply Current 100 J1A E2 = VCC-0.2V

OTHER INPUTS =
0.2Vor VCC-0.2V
ICC Enabled Supply Current 70 mA E" E; = VIL. 10 = 0
ICCOP Operating Supply Current ® 70 mA E" E; = VIL, 10 = 0
f = I MHz
ICCOR Data Retention Supply Current 40 J1A 10 = 0, VCC = 2.0
E" E;
= VCC-03V
VCCDR Data Retention Supply Voltage 2.0 V
II Input Leakage Current -1.0 +1.0 J1A GNDsVlsVCC
IIOZ Input/Output Leakage Current -1.0 +1.0 J1A GNDsVIOsVCC
VIL Input Low Voltage -0.3 +0.8 V
VIH Input High Voltage 2.4 VCC V
+0.3 V
0.4 V iO = 4.0mA
VOL Output Low Voltage
VOH Output High Voltage 2.4 V 10 = -1.0mA
CI Input Capacitance ® 8 pF VI = VCC or GND,
f = I MHz
CIO Input/Output Capacitance ® 10 pF VIO = VCC or GND,
t = 1 MHz

TAVAV Read Cycle Time 55 ns <D

TAVQV Address Access Time 55 ns <D
TEILQV E, to Output Valid 35 ns <D
TE2LQV E; to Output Valid 55 ns <D
READ TEILQX E, to Output in Low Z 0 ns <D
CYCLE TE2LQX E; to Output in Low Z 0 ns <D
TEIHQZ E, Disable to Output in High Z 30 ns <D
TE2HQZ E; Disable to Output in High Z 40 ns <D
TAVQX Output Hoid from Address Change 5 ns <D
TAVAV Write Cycle Time 55 ns <D
TEILWH E, to End of Write 40 ns <D
TE2LWH E; to End of Write 45 ns <D
WRITE TAVWL Address Setup Time 5 ns <D
CYCLE TAVWH Address Valid to End of Write 50 ns <D
TWLWH Write Pulse Width 35 ns <D
TWHAV Write Recovery Time 10 ns <D
TWLQZ Write to Output in High Z 25 ns <D
TDVWH Data to Write Time Overlap 25 ns <D
TWHDX Data Hold from Write Time 15 ns <D
TWHQX Output Active from End of Write 0 ns <D
(1) All devices tested at worst case limits.
® Typical derating = 5mA/MHz increase in ICCDP; VI = VCC or GND.
® Capacitance sampled and guaranteed - not 100% tested.
<D Input pulse levels: OV to 3.0V Input and Output timing reference levels: 1.5V
Input rise and fall times: 5 ns Output load: lTIL Gate and CL = 100pF (including scope and jig)
 ABSOLUTE MAXIMUM RATINGS· OPERATING RANGE
Supply Voltage (VCC - GND) -O.3t08.0V Operating Supply Voltage
Input or Output Voltage Applied (GND -O.3V) Industrial (-9)
to (VCC +O.3V) Operating Temperature
Storage Temperature - 65°C to 150°C Industrial ( - 9) - 40°C to + 85°C
·CAUTlON: Stresses above those listed under "Absolute Maximum Ralings" may cause permanent damage to the device.
This is a stress only rating and functional operation of the device at these or at any other conditions above those indicated in the
operational sections of this specification is not implied.

TEMP. & VCC =

OPERATING
RANGE(!)
TEST
SYMBOL PARAMETER MIN MAX UNITS CONDITIONS

ICCSSI Standby Supply Current 50 "A E2 = VCC-0.2V

OTHER INPUTS =
0.2Vor VCC-0.2V
ICC Enabled Supply Current 70 mA E;, E2 = VIL. 10 = 0
ICCOP Operating Supply Current ® 70 mA E;, E2 = VIL, 10 = 0
t = 1 MHz
ICCDR Data Retention Supply Current 20 "A 10 = 0, VCC = 2.0
E;, E2 = VCC-0.3V
VCCDR Data Retention Supply Voltage 2.0 V
II Input Leakage Current -1.0 +1.0 "A GNDsVlsVCC
IIOZ Input/Output Leakage Current -1.0 +1.0 "A GNDsVIO sVCC
VIL Input Low Voltage -0.3 +O.B V
VIH Input High Voltage 2.2 VCC V
+0.3 V
VOL Output Low Voltage 0.4 V 10 = 4.0mA
VOH Output High Voltage 2.4 V 10 = -1.0mA
CI Input Capacitance <D 8 pF VI = VCC or GND,
t = 1 MHz
CIO Input/Output Capacitance <D 10 pF VIO = VCC or GND,
f = 1 MHz

TAVAV Read Cycle Time 70 ns <D

TAVOV Address Access Time 70 ns <D
TE1LOV E;to Output Valid 40 ns <D
TE2LOV E2to Output Valid 70 ns <D
READ TE1LQX E;to Output in Low Z 0 ns <D
CYCLE TE2LQX E2to Output in Low Z 0 ns <D
TE1HQZ E;Disable to Output in High Z 35 ns <D
TE2HQZ E2Disable to Output in High Z 40 ns <D
TAVQX Output Hold trom Address Change 5 ns <D
TAVAV Write Cycle Time 70 ns <D
TE1LWH E; to End ot Write 45 ns <D
TE2LWH E2 to End of Write 50 ns <D
WRITE TAVWL Address Setup Time 10 ns <D
CYCLE TAVWH Address Valid to End of Write 65 ns <D
TWLWH Write Pulse Widfh 40 ns <D
TWHAV Write Recovery Time 10 ns <D
TWLQZ Write to Output in High Z 40 ns <D
TDVWH Data to Write Time Overlap 30 ns <D
TWHDX Data Hold from Write Time 15 ns <D
TWHQX Output Active from End ot Write 0 ns <D
(!) All devices tested at worst case limits.
® Typical derating = 5mA/MHz increase in ICCOP; VI = VCC or GND.
<D Capacitance sampled and guaranteed - not 100% tested.
<D input pulse levels: OV to 3.0V Input and Output timing reference levels: 1.5V
Input rise and tall limes: 5 ns Output load: 1TIL Gate and CL = 100pF (including scope and iig)
 ABSOLUTE MAXIMUM RATINGS· OPERATING RANGE
Supply Voltage (VCC· GND) -O.3t08.0V Operating Supply Voltage
Input or Output Voltage Applied (GND -O.3V) Industrial (- 9)
to (VCC +O.3V) Operating Temperature
Storaae Temperature - 65°C to 150°C industriai ( - 9)
'CAUTlON: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This Is a stress only rating' and functional operation of the device at these or at any other conditions above those Indicated in the
operational sections of this specification Is not implied.

TEMP. '" VCC =

OPERATING
RANGE CD
TEST
SYMBOL PARAMETER MIN MAX UNITS CONOITIONS

ICCSSl Standby Supply Current 100 ~ E2 = VCC-0.2V

OTHER INPUTS =
0.2V or VCC-0.2V
ICC Enabled Supply Current 70 mA Ei, Ei = VIL. 10 = a
ICCOP Operating Supply Current CD 70 mA Ei, Ei = VIL, 10 = a
f = 1 MHz
ICCPR Data Retention Supply Current 40 ~ 10 = 0, VCC = 2.0
Ei, Ei = VCC-0.3V
VCCoR Data Retention Supply Voltage 2.0 V
II Input Leakage Current -1.0 +1.0 ~ GNDsVlsVCC
lIoZ Input/Output Leakage Current -1.0 +1.0 ~ GNosVIOsVCC
VIL Input Low Voltage -0.3 +0.8 V
VIH Input High Voltage 2.2 VCC V
+0.3 V
Val Output Low Voltage 0.4 V 10 - 4.0mA
VOH Output High Voltage 2.4 V 10 = -1.0mA
CI Input Capacitance ® 8 pF VI = VCC or GND,
f = 1 MHz
cia Input/Output Capacitance ® 10 pF via = VCC or GND,
f = 1 MHz

TAVAV Read Cycle Time 90 ns CD

TAvav Address Access Time 90 ns CD
TE1Lav Ei to Output Valid 70 ns CD
TE2LaV Ei to Output Valid 90 ns CD
READ TEl LOX Ei to Output In Low Z 0 ns CD
CYCLE TE2LOX Ei to Output In Low Z 0 ns CD
TE1HOZ Ei Disable to Output In High Z 45 ns CD
TE2HOZ Ei Disable to Output In High Z 50 ns CD
TAVOX Output Hold from Address Change 5 ns CD
TAVAV Write Cycle Time 90 ns CD
TE1LWH Ei to End of Write 55 ns CD
TE2LWH Ei to End of Write 6D ns CD
WRITE TAVWL Address Setup Time 10 ns CD
CYCLE TAVWH Address Valid to End of Write 80 ns CD
TWLWH Write Pulse Width 55 ns CD
TWHAV Write Recovery Time 10 ns CD
TWLOZ Write to Output In High Z 50 ns CD
TDVWH Data to Write Time Overlap 30 ns CD
TWHoX Data Hold from Write Time 15 ns CD
TWHOX Output Active from End of Write a ns CD
NOTES: CD All devices tested at worst case limits.
CD Typical derating = 5mA/MHz Increase In ICCOP; VI = VCC or GND.
® Capacitance sampled and guaranteed - not 100% tested.
CD Input pulse levels: OV to 3.0V Input and Output liming reference levels: 1.5V
Input rise and fall limes: 5 ns Output load: lTTL Gate and CL = 100pF (Including scope and Jig)
 ABSOLUTE MAXIMUM RATINGS· OPERATING RANGE
Supply Voltage (VCC - GND) -O.3t08.0V Operating Supply Voltage
Input or Output Voltage Applied (GND -O.3V) Industrial (-9)
to (VCC + O.3V) Operating Temperature
Storage Temperature - 65°C to 150°C Industrial (-9) -40°Cto + 85°C
·CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress only rating and functional operation of the device at these or at any other conditions above those indicated in the
operational sections of this specification is not implied.

TEMP. & VCC =

OPERATING
RANGEG)
TEST
SYMBOL PARAMETER MIN MAX UNITS CONDITIONS

ICCSB1 Standby Supply Current 1000 ~ E2 = VCC-0.2V

OTHER INPUTS =
0.2V or VCC-0.2V
ICC Enabled Supply Current 70 mA E;, E; = VIL. 10 = 0
ICCOP Operating Supply Current ® 70 mA E;, E; = VIL, 10 = 0
f = 1 MHz
ICCOR Oata Retention Supply Current 400 ~ 10 = 0, VCC = 2.0
E;, E; = VCC-0.3V
VCCOR Oata Retention Supply Voltage 2.0 V
II Input Leakage Current -5.0 +5.0 ~ GNOsVlsVCC
IIOl Input/Output Leakage Current -5.0 +5.0 ~ GNOsVIOsVCC
VIL Input Low Voltage -0.3 +0.8 V
VIH Input High Voltage 2.2 VCC V
+0.3 V
VOL Output Low Voltage 0.4 V 10 = 4.0mA
VOH Output High Voltage 2.4 V 10 = -1.0mA
CI Input Capacitance ® 8 pF VI = VCC or GNO,
f = 1 MHz
CIO Input/Output Capacitance (!) 10 pF VIO = VCC or GND,
f = 1 MHz

TAVAV Read Cycle Time 90 ns 0

TAVQV Address Access Time 90 ns 0
TE1LQV E;to Output Valid 70 ns 0
TE2LQV E;to Output Valid 90 ns 0
READ TE1LQX E;to Output in Low l 0 ns 0
CYCLE TE2LQX E;to Output in Low l 0 ns 0
TE1HQl E;Disable to Output in High l 45 ns 0
TE2HQl E;Disable to Output in High l 50 ns 0
TAVQX Output Hold from Address Change 5 ns 0
TAVAV Write Cycle Time 90 ns 0
TEILWH E; to End of Write 55 ns 0
TE2LWH E; to End of Write 60 ns 0
WRITE TAVWL Address Setup Time 10 ns 0
CYCLE TAVWH Address Valid to End of Write 80 ns 0
TWLWH Write Pulse Width 55 ns 0
TWHAV Write Recovery Time 10 ns 0
TWLQl Write to Output in High l 50 ns 0
TDVWH Data to Write Time Overlap 30 ns 0
TWHDX Data Hold from Write Time 15 ns 0
TWHQX Output Active from End of Write 0 ns 0
G) All devices tested at worst case limits.
® Typical derating = 5mA/MHz increase in ICCOP; VI = VCC or GND.
(!) Capacitance sampled and guaranteed - not 100% tested.
o Input pulse levels: OV to 3.0V Input and Output timing reference levels: 1.5V
Input rise and talt times: 5 ns Output load: lTIL Gate and Cl = 100pF (including scope and jig)
 ABSOLUTE MAXIMUM RATINGS· OPERATING RANGE
Supply Voltage (VCC - GN D) -O.3t08.0V Operating Supply Voltage
Input or Output Voltage Applied (GND -O.3V) Commercial (- 5)
to (VCC + O.3V) Operating Temperature
Storage Temperature - 65°C to 150°C Commercial (- 5) O°C to + 70°C
'CAUTlON: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress only rating and functional operation of the device at these or at any other conditions above those indicated in the
operalional sections of this specification is not implied.

TEMP. & VCC =

OPERATING
RANGE CD
TEST
SYMBOL PARAMETER MIN MAX UNITS CONOITIONS

ICCSS1 Standby Supply Current 100 "A Ez = VCC-0.2V

OTHER INPUTS =
0.2V or VCC-0.2V
ICC Enabled Supply Current 70 mA r" E2 = VIL. iO = 0
ICCOP Operating Supply Current <D 70 mA r" E2 = VIL, 10 = 0
f = 1 MHz
ICCOR Oata Retention Supply Current 40 "A 10 = 0, VCC = 2.0
r" E2 = VCC-0.3V
VCCOR Oata Retention Supply Voltage 2.0 V
II Input Leakage Current -1.0 +1.0 "A GNOsVlsVCC
1I0Z Input/Output Leakage Current -1.0 +1.0 "A GNOs VIO s VCC
VIL Input Low Voltage -0.3 +0.8 V
VIH Input High Voltage 2.4 VCC V
+0.3 V
0.4 V 10 = 4.0mA
VOL Output Low Voltage
VOH Output High Voltage 2.4 V 10 = -1.0mA
CI Input Capacitance ® 8 pF VI = VCC or GND,
f = 1 MHz
CIO Input/Output Capacitance ® 10 pF VIO = VCC or GND,
t = 1 MHz

TAVAV Read Cycle Time 55 ns <D

TAVQV Address Access Time 55 ns <D
TE1LQV r, to Output Valid 35 ns <D
TE2LQV E2 to Output Valid 55 ns <D
READ TE1LQX r, to Output in Low Z 0 ns <D
CYCLE TE2LQX E2 to Output in Low Z 0 ns <D
TE1HQZ r, Disable to Output in High Z 30 ns <D
TE2HQZ E2 Disable to Output In High Z 40 ns <D
TAVQX Output Hold from Address Change 5 ns <D
TAVAV Write Cycle Time 55 ns <D
TE1LWH r, to End of Write 4D ns <D
TE2LWH E2 to End of Write 45 ns <D
WRITE TAVWL Address Setup Time 5 ns <D
CYCLE TAVWH Address Valid to End of Write 50 ns <D
TWLWH Write Pulse Width 35 ns <D
TWHAV Write Recovery Time 10 ns <D
TWLQZ Write to Output in High Z 25 ns <D
TOVWH Oata to Write Time Overlap 25 ns <D
TWHOX Data Hold from Write Time 15 ns <D
TWHQX Output Active from End of Write 0 ns <D
CD All devices tested at worst case limits.
<D Typical derating = 5mA/MHz increase in ICCOP; VI = VCC or GNO.
® Capacitance sampled and guaranteed - not 100% tested.
<D Input pulse levels: OV to 3.0V input and Output timing reference levels: 1.5V
Input rise and fall limes: 5 ns Output ioad: 1TTL Gate and CL = 100pF (including scope and jig)
 ABSOLUTE MAXIMUM RATINGS· OPERATING RANGE
Supply Voltage (VCC - GND) -0,3 to 8,OV Operating Supply Voltage
Input or Output Voltage Applied (GND -0,3V) Commerciai(-5)
to (VCC +0,3V) Operating Temperature
Storage Temperature - 65°C to 150°C Commercial (- 5) O°C to + 70°C
·CAUTlON: Stresses above those fisted under "Absolute Maximum Ratings" may cause permanent damage to the device,
This is a stress onfy rating and functional operation of the device at these or at any other conaitions above those indicated in the
operational sections of this specification is not implied,

TEMP, & VCC =

OPERATING
RANGE CD
TEST
SYMBOL PARAMETER MIN MAX UNITS CONOITIONS

ICCS81 Standby Supply Current 50 ~ E2 = VCC-0,2V

OTHER INPUTS =
0,2Vor VCC-O,2V
ICC Enabled Supply Current 70 mA E;, E; = VIL. 10 = 0
ICCOP Operating Supply Current CD 70 mA E;, E; = VIL, 10 = 0
f = 1 MHz
ICCDR Data Retention Supply Current 20 pA ID = 0, VCC = 2,0
E;, E; = VCC-03V
VCCDR Data Retention Suppiy Voltage 2,0 V
II Input Leakage Current -1,0 +1.0 pA GNDsVlsVCC
1I0Z Input/Output Leakage Current -1.0 +1.0 pA GNDsVIOsVCC
VIL Input Low Voltage -0.3 +0.8 V
VIH Input High Voltage 2.2 VCC V
+0.3 V
VOL Output Low Voltage 0.4 V 10 = 4,OmA
VOH Output High Voltage 2.4 V 10 = -1,OmA
CI Input Capacitance CD 8 pF VI = VCC or GND,
f = 1 MHz
CIO Input/Output Capacitance CD 10 pF VIO = VCC or GND,
f = 1 MHz

TAVAV Read Cycle Time 70 ns 0

TAVQV Address Access Time 70 ns 0
TE1LQV E;to Output Valid 4D ns 0
TE2LQV E;to Output Valid 70 ns 0
READ TElLQX E;to Output in Low Z 0 ns 0
CYCLE TE2LQX E;to Output in Low Z 0 ns 0
TE1HQZ E; Disable to Output in High Z 35 ns 0
TE2HQZ E; Disable to Dutput in High Z 40 ns 0
TAVQX Output Hoid from Address Change 5 ns 0
TAVAV Write Cycle Time 70 ns 0
TEILWH E; to End of Write 45 ns 0
TE2LWH E; to End of Write 50 ns 0
WRITE TAVWL Address Setup Time 10 ns 0
CYCLE TAVWH Address Valid to End of Write 65 ns 0
TWLWH Write Puise Width 40 ns 0
TWHAV Write Recovery Time 10 ns 0
TWLQZ Write to Output in High Z 40 ns 0
TDVWH Data to Write Time Overlap 30 ns 0
TWHDX Data Hold from Write Time 15 ns 0
TWHQX Output Active trom End of Write D ns 0
Alt devices tested at worst case limits,
Typical derating = 5mA/MHz Increase in ICCOP; VI = VCC or GND.
Capacitance sampled and guaranteed - not 100% tested,
Input pulse levels: OV to 3,OV Input and Output timing reference ievels: 1.5V
Input rise and fali times: 5 ns Output load: HTL Gate and Cl = 100pF (Including scope and Jig)
 ABSOLUTE MAXIMUM RATINGS· OPERATING RANGE
Supply Voltage (VCC - GND) -O.3t08.0V Operating Supply Voltage
Input or Output Voltage Applied (GND -O.3V) Commercial ( - 5)
to (VCC +O.3V) Operating Temperature
- 65°C to 150°C Commercial ( - 5)
·CAUTlON: Stresses above those listed under "Absolute Maximum Ralings" may cause permanent damage to the device.
This is a stress only raling and funclional operalion of the device at these or at any other conditions above those indicated in the
operational sections of this specification is not implied.

TEMP. & VCC =

OPERATING
RANGE CD
TEST
SYMBOL PARAMETER MIN MAX UNITS CONOITIONS

ICCSS1 Standby Supply Current 100 "Po E2 = VCC-O.2V

OTHER INPUTS =
O.2Vor VCC-O.2V
ICC Enabled Supply Current 70 mA E" E2 = Vilo 10 = a
ICCOP Operating Supply Current CD 70 mA E" E2 = Vll, 10 = 0
f = I MHz
ICCDR Data Retention Supply Current 40 "Po 10 = 0, VCC = 2.0
E" E2 = VCC-0.3V
VCCDR Data Retention Supply Voltage 2.0 V
II Input leakage Current -1.0 +1.0 "Po GND",VI ",VCC
IIOZ Input/Output leakage Current -1.0 +1.0 "Po GND",VIO",VCC
VIL Input Low Voltage -0.3 +0.8 V
VIH Input High Voltage 2.2 VCC V
+0.3 V
VOL Output Low Voltage 0.4 V 10 = 4.0mA
VOH Output High Voltage 2.4 V 10 = -1.0mA
CI Input Capacitance ® 8 pF VI = VCC or GND,
t = 1 MHz
cia Input/Output Capacitance ® 10 pF via = VCC or GND,
f = 1 MHz

TAVAV Read Cycle Time 90 ns CD

TAVOV Address Access Time 90 ns CD
TE1LOV E, to Output Valid 70 ns CD
TE2LOV E2 to Output Valid 90 ns CD
READ TElLOX E, to Output in Low Z 0 ns CD
CYCLE TE2LOX E2 to Output in Low Z 0 ns CD
TE1HOZ E, Disable to Output In High Z 45 ns CD
TE2HOZ E2 Disable to Output in High Z 50 ns CD
TAVOX Output Hoid from Address Change 5 ns CD
TAVAV Write Cycle Time 90 ns CD
TE1LWH E, to End of Write 55 ns CD
TE2LWH E2 to End of Write 60 ns CD
WRITE TAVWL Address Setup Time 10 ns CD
CYCLE TAVWH Address Valid to End of Write 80 ns CD
TWLWH Write Pulse Width 55 ns CD
TWHAV Write Recovery Time 10 ns CD
TWLOZ Write to Output in High Z 50 ns CD
TDVWH Data to Write Time Overlap 30 ns CD
TWHDX Data Hold from Write Time 15 ns CD
TWHOX Output Active from End of Write 0 ns CD
CD All devices tested at worst case limits.
CD Typical derating = 5mA/MHz increase in ICCOP; VI = VCC or GND.
® Capacitance sampled and guaranteed - not 100% tested.
CD Input pulse levels: OV to 3.0V Input and Output timing reference levels: 1.5V
Input rise and fall times: 5 ns Dutput load: HTL Gate and Cl = 100pF (including scope and jig)
 HM-65172
Read Cycle

NOTES: 1. Wts high, "1", lor READ Cycle

2. When f1 and E2 are low, "0", address Inputs must nol be In high Impedance
5lale.
3. E2-"l" deselects the part and gales the InpUlS 011. The HM-65172 will con-
sume ICCSB1 regardless of Inpul conditions wllhln lhe absolute maximum
rallngs.

'!'{riti~ data into the memory requires an ove!:@pof E" E; and W. Wh~ state. Care must be taken when applying data input at this time. Data of
E or E2 transition low simultaneously with the W low transition, or after W
j opposite phase must not be applied when the DO lines are in the output
transitions low, the outputs will remain in a high impedance state. After state. Also, during TWLOZ, the DOpins are in the output state and data of
W transitions high and if E, and E; are low, the DOpins are in the output opposite phase must not be applied.
 E2 E1 W D Q Ice MODE

H X X Z Z IS8 E; = VI H; Deselect

H X X Z Z IS81 E; ~ VCC = 0.3;

Deselect

L L H Z VALID ICC Read

L L L VALID Z ICC Write

X H X Z Z ICC Deselect

Low Voltage Data Retention

Harris CMOS RAMs are designed with battery backup in mind. Data
retention voltage and supply current are guaranteed over tem-
perature. The following rules insure data retention:

1. Chip Enable (E;) must be held high during data retention; 3. Inputs which are to be held high, must be kept between
within VCC to VCC + 0.3V. VCC + 0.3V and 70% of VCC during the power up and
2. On RAMs which have two chip enables, one of the enables power down transitions.
should be held in the deselected state to keep the RAM 4. The RAM can begin operation> 55ns after VCC reaches
outputs high impedance, minimizing power dissipation. the minimum operating voltage (4.5 volts).

DATA RETENTION MODE

vee;;. 2.0V
m HARRIS HM-65262
16K x 1 Asynchronous
CMOS Static RAM

• lOW STANDBY CURRENT 50~A

• lOW OPERATING CURRENT 60mA

• FAST ADDRESS ACCESS TIME 45/55170 ns

• lOW VOLTAGE DATA RETENTION @ 2.0V

• CMOS/TTl COMPATIBLE INPUTS AND OUTPUTS

• JEDEC APPROVED PINOUT

• EQUAL CYCLE AND ACCESS TIMES

• NO CLOCKS OR STROBES REQUIRED

• SINGLE 5 VOLT SUPPLY

• GATED INPUTS-NO PUll·UP OR PUll-DOWN

RESISTORS REQUIRED

• WIDE TEMPERATURE RANGE AO

A1
• EASY MICROPROCESSOR INTERFACING A2
A3
A4
A5
Description A6
A7
The HM-65262 is a CMOS 16384 x 1 Static Random Access Memory manufac- AB
A9
tured using Harris' advanced SAJI-VI process. The device utilizes asynchronous A10
circuit design for fast cycle time and ease of use. The pinout is the JEOEC 20-pin, A11
O.300-inch wide standard, providing high board-level packing density. Gated in- A12
A13
puts lower operating current and also eliminate the need for pull-up or pull-down
resistors. A- Address Input D- Oata Input
l- Chip Enable Q- Data Output
W- Wrtte Enable

ROW ROW
ADDRESS DECODER
BUFFERS (101128)

A7 I A~ I ~4 I A6
A8 A10 A5

CAUTION: These devices are sensitIve to electronic discharge. Proper I.e. handling procedures should be followed.

Copynght © Hams Corporation 1983

mHARRIS
HM-6564

LOW POWER STANDBY 4mWMAX

LOW POWER OPERATION 280mW/MHz MAX
2.0V MIN *GNO VCC
DATA RETENTION
Q4 QO
TTL COMPATIBLE IN/OUT
04 00
THREE STATE OUTPUTS
Q5 Ql
FAST ACCESS TIME 350nsMAX 01
05
FULL MILITARY TEMPERATURE AVAILABLE -550C to 1250C All
AO
INDUSTRIAL TEMPERATURE STANDARD -400C to 850C Al0
Al
COMMERCIAL TEMPERATURE AVAILABLE OOC to 750C A2 A9
ON CHIP ADDRESS REGISTERS E3 El
ORGANIZABLE 8K x 8 or 16K x 4 *W2 W1
W2 Wl*
40 PIN DIP PINOUT - 2.000" x 0.900"
E4 E2
A6 A5
Description A7 A4
The HM-6564 is a 64K bit CMOS RAM. It consists of 16 HM4-6504 4K x 1 A8 A3
CMOS RAMs, in leadless carriers, mounted on a ceramic substrate. The HM- 06 02
Q6 Q2
6564 is configured as an extra wide, standard length 40 pin DIP. The memory
07 03
appears to the system as an array of 16 4K x 1 static RAMs. The array is or-
Q7 Q3
ganized as two 8K by 4 blocks of RAM sharing only the address bus. The data
*VCC GNO*
inputs, data outputs, chip enables and write enables are separate for each
block of RAM. This allows the user to organize the HM-6564 RAM as either
an 8K by 8 or a 16K by 4 array. The HM-6564 also contains decoupling
capacitors to reduce noise and to minimize the need for additional external *NOTES:
decoupling. Pins 20 and 40 (VCC) are internally connected.
This 64K memory provides a unique blend of low power CMOS semiconductor Similarly pins 1 and 21 (Ground) are connected.
technology and advanced packaging techniques. The HM-6564 is intended for The user is advised to connect all fourvec pins
use in any application where a
large amount of RAM is needed, and where and Ground pins to his board busses. This will
improve power distribution across the array and
power consumption and board space are prime concerns. The guaranteed low
will enhance decoupling.
voltage data retention characteristics allow easy implementation of non-
Pin 10 is internally ~onnected to pin 11, and
volatile read/write memory by using very small batteries mounted directly on
pin 30 is connected to pin 31.
the memory circuit board. Example applications include digital avionic in-
strumentation, remote data acquisition, and portable or hand held digital com-
munications devices.

.,
A
W,
'2
To Organize 8K x 8: To Organize 16K x 4:
Connect: E1 with E3 (Pins 9 + 32) Connect: 00 with 04 (Pins 2 + 39)
E2 with E4 (Pins 12 + 29) DO with D4 (Pins 3 + 38)
W1 withW2 (Pins 11 +31) 01 with 05 (Pins 4 + 37)
D1 with D5 (Pins 5 + 36)
02 with D6 (Pins 16 +25)
02 with 06 (Pins 17 + 24)
D3 with D7 (Pins 18 + 23)
03 with 07 (Pins 19 + 22)
Optional W1 may be common with W2 (Pins 11 + 31)
Concerns for Proper Operation of Chip Enables:
The transition between blocks of RAM requires a change in the chip enable being used. When operating in the 8K x 8 mode,
use the chip enables as if there were only two, E1 and E2. In the 16K x 4 mode, all chip enables must be treated separately.
Transitions between chip enables must be treated with the same timing constraints that apply to anyone chip enable. All
chip enables must be high at least one chip enable high time (TEHEL) before any chip enable can fall. More than one chip
enable low simultaneously, for devices whose outputs are tied common either internally or externally, is an illegal input con-
dition and must be avoided.
Printed Circuit Board Mounting:
The leadless chip carrier packages used in the HM-6564 have conductive lids. These lids are electrically floating, not connect-
ed to VCC or GND. The designer should be aware of the possibility that the carriers on the bottom side could short conduc-
tors below if pressed completely down against the surface of the circuit board. The pins on the package are designed with a
standoff feature to help prevent the leadless carriers from touching the circuit board surface.
Printed circuit board real estate is a costly commodity. The following table compares board space for 16 standard
Actual board costs depend on layout tolerances, density, DIP 4K RAMs to the HM-6564 RAM arrey. Both fine
complexity, number of layers, choice of board material, line, close tolerance layout and standard "easy" layout
and other factors. board sizes are shown in the comparison.

PACKAGE CIRCUIT SUBSTRATE SIZE

18 Pin DIP Standard 12 to 15 sq. in.

Two Sided PCB

18 Pin DIP Fine line or 9 to 11 sq. in.

Multilayer PCB

18 Pin Multilayer 3 to 5 sq. in.

Leadless Carrier Alumina Substrate

HM5-6564 Two Sided Mounting 2 sq. in.

Multilayer
Alumina Substrate

The cost of semiconductor circuits decline with time. If the advantages of a lighter, smaller overall package for your
actual costs were included, they would be out of date in system. Consider how much more valuable your system
a very short time. We urge you to contact your local Harris will be when the memory array size is decreased to about
office or sales representative for accurate pricing allowing 1/6 of normal size.
cost tradeoff analysis. In your cost analysis, also consider
 OPERATING RANGE
Supply Voltage - (VCC - GND) -O.3V to +8.0V Operating Supply Voltage
Military (-2)flndustrial (-9)
Input or Output Voltage Applied (GND -O.3V)
Operating Temperature
to (VCC +O.3Vl
Military (-2)
-650C to +1500C

* CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress only rating and functional operation of the device at these or at any
other conditions above those indiCBted in the operational sections of this specification is not implied.

TEMP. & VCC =

OPERATING TEMP. = 25°C <D
RANGE VCC = 5.0V
TEST
SYMBOL PARAMETER MIN MAX MAX UNITS CONDITIONS

ICCSS Standby Supply Current 800 100 IJA 10 =0

VI = VCC or GND
ICCOPl Operating Supply 56 mA E=lMHz,IO=O
Current (8K x 8) ~ VI = VCC or GND
ICCOP2 Operating Supply 28 mA E= lMHz, 10 = 0
Current (16K x 41 ~ VI = VCC or GND
ICCDR Data Retention 400 48 /lA 10 ~ 0, VCC ~ 2.0,
Supply Current VI = VCC or GND
VCCDR Data Retention 2.0 V
Supply Voltage
IIA Address Input Leakage -20 +20 /lA GND~VI~VCC
IIDl Data I nput Leakage -3 +3 /lA GND~VI~VCC
18K x 8)
IID2 Data Input Leakage -5 +5 /lA GND~VI~VCC
116K x 4)
IIEl Enable Input Leakage -10 +10 /lA GND~VI~VCC
18K x 8)
IIE2 Enable Input Leakage -5 +5 /lA GND~VI~VCC
(16K x 4)
IIW Write Enable Input -10 +10 /lA GND~VI~VCC
Leakage (Each I
1021 Output Leakage 18K x 8) -5 +5 /lA GND~VO~VCC
1022 Output Leakage (16K x 4) -10 +10 /lA GND~VO~VCC
VIL Input Low Voltage -0.3 0.8 V
VIH Input High Voltage VCC-2.0 VCC+0.3 V
VOL Output Low Voltage 0.4 V 10 ~ 2.0mA
VOH Output High Voltage 2.4 V 10 =-1.0mA
CIA Address Input 200 pF f ~ lMHz,
Capacitance @ VI =
VCC or GND
CIDl Data Input 50 pF f = lMHz,
Capacitance 18K x 8) @ VI = VCC or GND
CID2 Data Input 100 pF f~ lMHz,
Capacitance (16K x 4) @ VI = VCC or GND
CIEl Enable Input 160 pF f ~ lMHz,
Capacitance (8K x 8) Q) VI ~ VCC or GND
CIE2 Enable Input 80 pF f ~ lMHz,
Capacitance (16K x 4) @ VI =
VCC or GND
CIW Write Enable Input 100 pF f =lMHz,
Capacitance I Each I @ VI = VCC or GND
C01 Output Ca&Citance 50 pF f=1MHz,
(8K x 8) 3 VO ~ VCC or GND
CO2 Output Capacitance 100 pF f ~ lMHz,
(16Kx4) @ VO = VCC or GND
CVCC Decoupling Capacitance .25 /IF f ~ lMHz

CD This valu,:, is guaranteed and tested at 250C.

a> Operating supply current is proportional to operating fre-

quency. ICCo? is specified at an operating frequency of
1 MHz, indicating repetitive accessing at a 1J.ls rate. Operation
at slower rates will decrease ICCo? proportionally.
 OPERATING RANGE
Supply Voltage - (VCC - GND) -O.3V to +8.0V Operating Supply Voltage
Industrial (-9)
Input or Output Voltage Applied (GND -O.3Vl
to (VCC +O.3V)
Operating Temperature
-650C to +1500C Industrial (-9)

* CAUTION: Strssss. sbovs tho.s lI.tsd undsr "Ab.olute Msltimum Rstings" msy csu.s psrmsnsnr
dsmsgs to ths dsvlcs. Thi. i. s strsssonly rsting snd functionsl opsrstion of ths dsvicsst ths.s or st sny
othsr condition. sbovs tho.s indicsted in ths opsrstlonsl .sction. of this .pscificstion i. not impllsd.

TEMP. & VCC-

OPERATING TEMP. - 250C<D
RANGE VCC - 5.0V TEST
SYMBOL PARAMETER MIN MAX MAX UNITS CONDITIONS

ICCSB Standby Supply Currsnt BOO 48 IJ.A 10 -0

VI - VCC or GNo
ICCOPl Oparating Supply 56 mA 'E'-lMHz, 10 - 0
Current IBK x BI (%) VI - VCC or GNo
ICCOP2 Operating Supply 2B mA E'-lMHz,IO - 0
Current 116K x 41 (%) VI - VCC or GNo
ICCoR Data Retention 400 32 IJ.A 10 - 0, VCC - 2.0,
Sup~ly Current VI - VCC or GNo
VCCoR Data Retention 2.0 V
Supply Voltage
IIA Addre •• Input Leakage -20 +20 IJA GNo~VI~VCC
1101 Data Input Leakage -3 +3 IJ.A GNo~VI~VCC
IBK x 81
1102 Data Input Leakage -5 +5 IJA GNo~VI~VCC
(16K x 41
IIE1 Enable Input Leakage -10 +10 IJA GNo~VI~VCC
IBK x BI
IIE2 Enable Input Laakage -5 +5 IJ.A GND~VI~VCC
116K x 4)
IIW Write Enable Input -10 +10 IJA GNo~VI~VCC
Leakage (Each)
10Zl Output Leakage (8K x BI -5 +5 IJA GND~VO~VCC
IOZ2 Output Leakage (16K x 4) -10 +10 IJA GNo~VO~VCC
VIL Input Low Voltage -0.3 0.8 V
VIH Input High Voltaga VCC-2.0 VCC+0.3 V
VOL Output Low Voltage 0.4 V 10·2.0mA
VOH Output High Voltage 2.4 V 10· -1.0mA
CIA Addre •• Input 200 pF f-1MHz,
Capacitance ~ VI • VCC or GNo
CI01 Data Input 50 pF f - lMHz,
Capacitance IBK x BI ~ VI • VCC or GNo
CID2 Data Input 100 pF f·1MHz,
Capacitance (16K x 4) ~ VI - VCC or GNo
CIE1 Enable Input 160 pF f·1MHz,
Capacitance (8K x B) ~ VI - VCC or GNo
CIE2 Enable Input 80 pF f·1MHz,
Capacitance (16K x 4) ~ VI • VCC or GND
CIW Writa Enable Input 100 pF f = lMHz,
Capacitance (Each) ~ VI - VCC or GNo
COl Output CaO)'cltance 50 pF f = lMHz,
IBK x BI VO - VCC or GND
CO2 Output Capacitance 100 pF f = lMHz,
(16Kx41 ~ VO = VCC or GNo
CVCC Decoupling Capacitance .25 IJ.F f -lMHz

G) This value is guaranteed and tested at 250C.

l2> Operating supply current is proportional to operating fre-

quency, ICCOP is specified at an operating frequency of
1MHz, indicating repetitive accessing at a 1jJs rate. Operation
at slower rates will decrease ICCOP proportionally,
 TEMP& VCC-
OPERATING
RANGE
TEST
SYMBOL PARAMETER MIN MAX UNITS CONDITIONS

TELQV Chip Enable Access 350 ns @

TAVQV Address Access 400 ns @
ITAVQV=TELQV+TAVEL)

TELQX Output Enable 20 120 ns @

TEHQZ Output Oisable 120 ns @
TELEL Read or Write Cycle 480 ns @
TELEH Chip Enable Low 350 ns @
TEHEL Chip Enable High 130 ns @
TAVEL Address Setup 50 ns @
TELAX Address Hold 50 ns @
TWLWH Write Enable Low 150 ns @
TWLEH Write Enable Setup 250 ns @
TWLEL Early Write Setup 10 ns @
(Write Mode)

TWHEL Write Enable Read Setup 10 ns @

TELWH Early Write Hold 100 ns @
(Write Mode)

TOVWL Data Setup 10 ns @

TOVEL Early Write Data Setup 10 ns @
TWLDX Data Hold 100 ns @
Early Write Data Hold
TELDX 100 ns ®
TQVWL Data Valid to Write 0 ns @
(Read-Modify-Write)

Inputs - Trise = Tlall ~ 20ns.

Outputs - CLOAD· 100pF
Timing measured at 1.5V reference level.
 Supply Voltage - (VCC - GND) -O.3V to +8.0V Operating Supplv Voltage
Commercial (-5)
Input or Output Voltage Applied (GND -O.3V)
to (VCC +O.3Vl Operating Temperature
Commercial (-5)
-650C to + 1500C

• CAUTION: Stresses above those listed under '~bsolute Maximum Ratings" may cause permanent
damage to the device. This is a stress only rating and functional operation of the device at these or at any
other conditions above those indicated in the operational sections of this specification is not implied.

TEMP. & VCC =

OPERATING TEMP. = 25°C
RANGE VCC= 5.oV G) TEST
SYMBOL PARAMETER MIN MAX MAX UNITS CONDITIONS

ICCSS Standby Supply Current 5.6 o.Bo mA 10 -0.

VI = VCC or GND
ICCOPl Operating Supply 60 mA E=1MHz.10=0
Current 18K x 8) <6> VI = VCC or GND
ICCOP2 Operating Supply 30 mA E=lMHz.IO=O
Current (16K x 4) Q) VI = VCC or GND
ICCDR Data Retention Supply Curro 3.2 0.48 mA VCC - 2.0,10 - 0
VI - VCC or GND
VCCDR Data Retention Supply V. 2.0 V
IIA Address Input Leakage -20 +20 J.lA GND~VI~VCC
1101 Data Input Leakage -3 +3 J.lA GND~VI~VCC
(8K x 8)
1102 Data Input Leakage -5 +5 J.lA GND~VI~VCC
(16K x 4)
IIE1 Enable Input Leakage -10 +10 J.lA GND~VI~VCC
(8K x 8)
IIE2 Enable Input Leakage -5 +5 J.lA GND~VI~VCC
(16K x 4) .
IIW Write Enable Input -10 +10 J.lA GND~VI~VCC
Leakage lEach)
1021 Output Leakage (8K x 8) -5 +5 J.lA GND~VO~VCC
1022 Output Leakage 116K x 4) -10 +10 J.lA GND~VO~VCC
VIL Input Low Voltage -0.3 0.8 V
VIH Input High Voltage VCC -2.0 VCC+0.3 V
VOL Output Low Voltage 0.4 V 10 = 1.6mA
VOH Output High Voltage 2.4 V 10 = -OAmA
CIA Address Input 200 pF f = 1MHz,
Capacitance (:l) VI = VCC or GND
CIDl Data Input 50 pF f = 1MHz,
Capacitance 18K x 8) @ VI = VCC or GND
CID2 Data Input 100 pF f= 1MHz,
Capacitance (16K x 4) @ VI = VCC or GND
CIE1 Enable Input 160 pF f= 1MHz,
Capacitance 18K x 8) ® VI = VCC or GND
CIE2 Enable Input 80 pF f = 1MHz,
Capacitance (16K x 4) ® VI = VCC or GND
CIW Write Input 100 pF f = 1MHz,
Capacitance (Each) @ VI = VCC or GND
C01 Output Capacitance 50 pF f = 1MHz,
(8K x 8) ® VO= VCC or GND
CO2 Output Capacitance 100 pF f = 1MHz,
(16K x4) (j) VO = VCC or GND
CVCC Decoupllng Capacitance .25 J.lF f = 1MHz

CD This value is guaranteed and tested at 250C.

(2) Operating supply current is proportional to operating fre-

quency. ICCOP is specified at an operating frequency of
1 MHz, indicating repetitive accessing at a 1ps rate. Operation
at slower rates will decrease ICCOP proportionally.
 TEMP. a. VCC·
OPERATING
RANGE
TEST
SYMBOL PARAMETER MIN MAX UNITS CONDTIONS

TELOV Chip Enabla Acca•• 450 ns lID

TAVOV Addre •• Acce•• 600 ns @
(TAVOV-TELOV+TAVEL)

TELOX Output Enable 20 150 ns lID

TEHOZ Output 0 isabla 150 ns @
TELEL Raad or Write Cycle 600 ns @
TELEH Chip Enabla Low 450 ns @
TEHEL Chip Enable High 150 ns lID
TAVEL Addre •• Setup 60 ns @
TELAX Addra •• Hold 60 ns @
TWLWH Writa Enabla Low 160 ns lID
TWLEH Write Enable Setup 260 ns lID
TWLEL Early Write Setup 10 ns @
(Write Mode)
TWHEL Write Enable Reed Setup 10 ns lID
TELWH Early Writa Hold 100 ns lID
(Write Modal

TOVWL Data Setup 10 ns @

TOVEL Early Wrlta Oeta Sotup 10 ns lID
TWLOX Data Hold 100 ns lID
TELOX Early Wrlta Data Hold 100 ns @
TOVWL Oato Valid to Wrlta 0 ns lID
(Raady-Modify-Wrlta)

NOTES:
@) AC TlSt Conditions:
Inputs - Tris. - nail ~ 20ns.
Outputs - CLOAO - 100pF.
Timing measured at 1.5V reference level.
 TIME INPUTS OUTPUT FUNCTION
REFERENCE E Vi A a
-, H X X Z MEMORY DISABLED
0 ~ H V Z CYCLE BEGINS. ADDRESSES ARE LATCHED
1 l H X X OUTPUT ENABLED
2 l H X V OUTPUT VALID
3 .r H x V READ ACCOMPLISHED
4 H X X Z PREPARE FOR NEXT CYCLE (SAME AS ·11
5 '- H V Z CYCLE ENDS. NEXT CYCLE BEGINS (SAME AS 0)

The address information is latched in the an chip registers becomes enabled but data is not valid until during time
on the falling edge of E (T = 0). Minimum address set up (T = 2). Vi must remain high until after time (T = 2).
and hold time requirements must be met. After the requir- After the output data has been read, E may return high
ed hold time, the addresses may change state without (T = 3). This will disable the output buffer and ready the
affecting device operation. During time (T = 1) the output RAM for the next memory cycle (T = 4).

TIME INPUTS OUTPUT FUNCTION

REFERENCE E Vi A 0 0

-1 H X X X Z MEMORY DISABLED
0 '- l V V Z CYCLE BEGINS. ADDRESSES ARE LATCHED
1 l X X X Z WRITE IN PROGRESS INTERNALL Y
2 .r x x x Z WRITE COMPLETED
3 H X X X Z PREPARE FOR NEXT CYCLE (SAME AS -1 t
4 '- l V V Z CYCLE ENDS. NEXT CYCLE BEGINS (SAME AS 01

The early write cycle is the only cycle where the output is will remain in that state until E returns high (T = 2). For
guaranteed not to become active. On the falling edge of this cycle, the data input 's latched by E going low; there-
E (T = 0). the addresses, the write signal, and the data fore data set up and hold times should be referenced to E.
input are latched in on chip registers. The logic value of Vii When E (T = 2) returns to the high state the output buffer
at the time E falls determines the state of the output buffer disables and all signals are unlatched. The device is now
for that cycle. Since W is low when E falls, the out- ready for the next cycle.
put buffer is latched into the high impedance state and
 TIME INPUTS OUTPUT FUNCTION
REFERENCE E W A 0 Q

-1 H X X X Z MEMORY DISABLED
0 "\. H V X Z CYCLE BEGINS. ADDRESS ARE LATCHED
1 L H X X X OUTPUT ENABLED
2 L H X X V OUTPUT VALID. READ AND MODIFY TIME
3 L "\. X V V WRITE BEGIN~,DATA IS LATCHED
4 L X X X V WRITE IN PROGRESS INTERNALL Y

, of
5 X X X V WRITE COMPLETED
H X X X Z PREPARE FOR NEXT CYCLE (SAME AS -1)
"\.
7 H V X Z CYCLE ENOS. NEXT CYCLE BEGINS (SAME AS 0)

The read modify write cycle begins as all other cycles W signal also latches itself on its low going edge. All input
on the falling edge of E (T= 0). The W line should be signals excluding E have been latched and have no further
high at (T = 0) in order to latch the output buffers in the effect on the RAM. The rising edge of E (T = 5) completes
active state. During (T = 1) the output will be active but the write portion of the cycle and unlatches all inputs and
not valid until (T = 2). On the falling edge of the W (T = 3) the output. The output goes to a high impedance and the
the data present at the output and input are latched. The RAM is ready for the next cycle.

T'LOX~ _

TIME INPUTS OUTPUT

REFERENCE "E W A 0 a FUNCTION

-I H X X X Z MEMORY DISABLED
"\.
0 H V X Z CYCLE BEGINS. ADDRESSES ARE LATCHED
I L "\. X V X WRITE eEGINS, DATA IS LATCHED
2 L H X X X WRITE IN PROGRESS INTERNALLY
3 of H X X X WRITE COMPLETED
4 H X X X Z PREPARE FOR NEXT CYCLE (SAME AS-lI
5 "\. H V X Z CYCLE ENDS, NEXT CYCLE BEGINS (SAME AS 0)

The late write cycle is a cross between the early write write is between these two cases. With this cycle the output
cycle and the read-modify-write cycle. may become active, and may become valid data, or may
Recall that in the early write the output is guaranteed to remain active but undefined. Valid data is written into the
remain high impedance, and in the read-modify-write RAM if data set up, data hold, write setup and write pulse
the outout is auaranteed valid at access time. The late widths are observed.

NOTES: In the above descriptions the numbers in parenthesis (T • nl refer to the respective timing diagrams.
The numbers are tocated on the time reference line below each diagram. The timing diagrams shown
are only examples and are not the only valid method of operation,

2-94
ADDRESS LATCHES AND GATED
DECODERS:
LATCH ON FALLING EDGE OF E
GATE ON FALLING EDGE OF E
m HARRIS HM-92560
256K SYNCHRONOUS
CMOS RAM MODULE

• LOW STANDBY CURRENT 500IJA

• FAST ADDRESS ACCESS TIME 170 ns
• DATA RETENTION 2.0V minVCC
GND vcc
• THREE STATE OUTPUTS A7 A.
• ORGANIZABLE AS 32K x 8 or 16K x 16 ARRAY AS Al
• ON CHIP ADDRESS REGISTERS A9 A2
• 48 PIN DIP PINOUT - 2.53" x 1.30" x 0.29" AI. " A'
Ei
• SYNCHRONOUS
• LOW OPERATING
OPERATION
POWER
YIELDS
Ei ., A'
AS

• WIDE TEMPERATURE RANGE

5
EO ..,. Ati
m
m
Description 'S
Eo E14
The HM-92560 is a high density 256K bit CMOS RAM module. Sixteen synchronous
HM-6516 2K x 8 CMOS RAMs in lead less chip carriers are mounted on a multilayer
"
GA
e;
" "
16
W
Go
m
ceramic substrate. The HM-92560RAM module is organized as two 16K by 8 CMOS e; ,. ill
RAM arrays sharing a common address bus. Separate data inpuVoutput buses and 000
chip enables allow the user to format the HM-92560 as either a 16Kx 16 or 32Kx8
" DO'

array. Ceramic capacitors are included on the substrate to reduce noise and to
001
002 " 009

" DOlO

minimize the need for additional external decoupling.

The synchronous design of the HM-92560 provides low operating power along with
DO'
DO'
DOS
,.
28
DOll
OQ12

0013
OOti OQ14
address latches for ease of interface to multiplexed address/data bus microproces-
007 0015
sors.
ill m
The HM-92560 is physically constructed as an extra wide 48 pin dual-in-line
package with standard 0.1" centers between pins. This packaging technique
combines the high packing density of CMOS and lead less chip carriers with the
ease of use of DIP packaging.

Functional Diagram

w
AO-Al0

AO-l0 _ AO-l0
W W
E E
000-7 G G 000-7
El E9
···
·
E8 E16
AO-10 _ AO-10
W
E E
G
HM-6516

000-7 GA GB 008-15
 CONNECT: PIN 16 (000) to PIN 33 (008)
PIN 17 (001) to PIN 32 (009)
PIN 18 (002) to PIN 31 (0010)
PIN 19 (003) to PIN 30 (0011)
PIN 20 (004) to PIN 29 (0012)
PIN 21 (005) to PIN 28 (0013)
PIN 22 (006) to PIN 27 (0014)
PIN 23 (007) to PIN 26 (0015)

CONNECT: PIN 6 (E1) to PIN 15 (E9)

PIN 7 (E2) to PIN 24 (E10)
PIN 8 (E3) to PIN 25 (E11)
PIN 9 (E4) to PIN 34 (E12)
PIN 10 (E5) to PIN 35 (E13)
PIN 11 (E6) to PIN 38 (E14)
PIN 12 (E7) to PIN 39 (E15)
PIN 14 (E8) to PIN 40 (E16)
PIN 13 (GA) to PIN 36 (GB)

The transition between blocks of RAM requires a chip enable high time (TEHEL) before any chip
change in the chip enable being used. When operating enable can fall. As the HM-92560 is a synchrounous
in the 16K x 16 mode use the chip enables as if there memory every address transition must be accomp-
were only eight, E1 thru E8. In the 32K x 8 mode, anied by a chip enable transition ( see timing dia-
all chip enables must be treated separately. Transi- grams). More than one chip enable low simultan-
tions between chip enables must be treated with the eously, for devices whose outputs are tied common
same timing constraints that apply to anyone chip either internally or externally, is an illegal input con-
enable. All chip enables must be high at least one dition and must be avoided.

The leadless chip carrier packages used in the HM- completely down against the surface of the circuit
92560 have conductive lids. These lids are elec- board. The pins on the package are designed with a
trically connected to GNO. The designer should standoff feature to help prevent the leadless carriers.
be aware of the possibil ity that the carriers on the from touching the circuit board surface.
bottom side could short conductors below if pressed
 Operating Supply Voltage
Supply Voltage (VCC - GND) -0.3 to 8.0V
Military (-2, -8) 4.5V to 5.5V
Input or Output Voltage Applied (GND -0.3Vl
Industrial (-9) 4.5V to 5.5V
to (VCC +0.3V)
Operating Temperature
-650C to 1500C
Military (-2, -8) -550C to +1250C
Industrial (-9) -400C to +850C

CAUTION: Stresses above those listed under ;'Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress only rating and functional operation of the device at these or at any
other conditions above those indicated in the operational sections of this specification is not implied.

TEMP. & VCC·

OPERATING
RANGE <D
TEST
SYMBOL PARAMETER MIN MAX UNITS CONOITIONS

ICCSB Standby Supply Current 500 IJ.A 10 =0

VI = VCC or GNO
ICCOP Operating Supply Current @ 30 mA E=lMHz,IO=O
16K x 16 VI = VCC or GNO. G = VCC
ICCOP Operating Supply Current @ 15 mA E = 1MHz, 10 = 0
32K x 8 VI = VCC or GNO, G = VCC
ICCOR Data Retention Supply Current 350 IJ.A 10 = 0, VCC = 2.0,
VI = VCC or GNO, E= VCC
VCCOR Data Retention Supply Voltage 2.0 V
II Input Leakage Current -5 +5 IJ.A GNO~VI~VCC
1I0Z I nput/Output Leakage Current -5 +5 J1A GNO~VIO~VCC
VIL Input Low Voltage -0.3 .8 V
VIH Input High Voltage VCC VCC V
-2.0 +0.3
VOL Output Low Voltage 0.4 V 10 = 3.2mA
VOH Output High Voltage 2.4 V 10 =-1.0mA
CIA Address Input ® 200 pF VI = VCC or GNO
Capacitance 1= lMHz
CIE1 Enable Input ® 100 pF VI = VCC or GNO
Capacitance (16K x 16) f = lMHz
CIE2 Enable Input ® 50 pF VI = VCC or GNO
Capacitance (32K x 8) 1= lMHz
CIG 1 Output Enable Input ® 150 pF VI = VCC or GNO
Capacitance (16K x 16) 1= lMHz
CIG 2 Output Enable Input ® 100 pF VI = VCC or GNO
Capacitance 132K x 8) 1= 1MHz
CIOl Input/Output ® 150 pF VI/O = VCC or GNO
Capacitance (16K x 16) 1= 1MHz
CI02 Input/Output ® 250 pF VI/O = VCC or GNO
Capacitance (32 x 8) 1= lMHz
CIW Write Input ® 200 pF VI = VCC or GNO
Capacitance 1= lMHz
CVcc DecQupling .5 pI 1= lMHz
Capacitance
 OPERATING RANGE
Operating Supply Voltage
Supply Voltage (VCC - GND) -0.3 to 8.0V
Military (-2, -8) 4.5V to 5.5V
Input or Output Voltage Applied (GND -0.3V)
Industrial (-9) 4.5V to 5.5V
to (VCC +0.3V)
Operating Temperature
-650C to 1500C
Military (-2, -8) -550C to +1250C
Industrial (-9) -400C to +850C

* CAUTION: Stresses above those listed under UAbsolute Maximum Ratings" may cause permanent
damage to the device. This is a stress only rating and functional operation of the device at these or at any
other conditions above those indicated in the operational sections of this specification is not implied.

TEMP. & VCC'

OPERATING
RANGE CD
TEST
SYMBOL PARAMETER MIN MAX UNITS CONDITIONS

TELQV Chip Enable Access Time 150 ns @

TAVQV Address Access Time 170 ns @
TELQX Chip Enable Output Enable Time 10 ns @)
TWLQZ Write Enable Output Disable Time 70 ns @)
TEHQZ Chip Enable Output Disable Time 70 ns @)
TGLQX Output Enable Output Enable Time 10 ns @)
TGLQV Output Enable Output Valid Time 70 ns @)
TGHQZ Output Enable Output Disable Time 70 ns @)
TELEH Chip Enable Pulse Negative Width 150 ns @)
TEHEL Chip Enable Pulse Positive Width 80 ns
TAVEL Address Setup Time 20 ns ~
TELAX Address Hold Time 50 ns @)
TWLWH Write Enable Pulse Width 150 ns @)
TWLEH Write Enable Pulse Setup Time 150 ns
TELWH Write Enable Pulse Hold Time 150 ns ~
TDVWH Data Setup Time 80 ns
TWHDX Data Hold Time 20 ns ~
TWLDV Write Data Delay Time 70 ns
TELEL Read or Write Cycle Time 230 ns ~

NOTES:
All devices tested at worst case limits.
Operating Supply Current IICCOP) is proportional to Operating Frequency.

~ Capacitance sampled and guaranteed - not 100% tested.

@) AC test conditions:
Input Puise Levels: OV to 3.0V
Input Rise Time: 10ns
 OPERATING RANGE
Operating Supply Voltage
Supply Voltage (VCC - GND) -0.3 to B.OV
Commercial (-5)
Input or Output Voltage Applied (GND -0.3V)
to (VCC +0.3V)
Operating Temperature
-650C to 1500C
Commercial (-5)

• CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is B stress only rating and functional operation of the device at these or at any
other conditions above those indicated in the operational sections of this specification is not implied.

TEMP. & VCC'

OPERATING
RANGE <D
TEST
SYMBOL PARAMETER MIN MAX UNITS CONDITIONS

ICCSS Standby Supply Current 3.5 mA 10 = 0

VI = VCC or GND
ICCOP Operating Supply Current @ 35 mA E= 1MHz, 10= 0
16K x 16 VI = VCC or GND, G = VCC
ICCOP Operating Supply Current @ 20 mA E= lMHz, 10=0
32K x 8 VI = VCC or GND, G = VCC
ICCDR Data Retention Supply Current 2.5 mA 10 = 0, VCC = 2.0,
VI = VCC or GND, E = VCC
VCCDR Data Retention Supply Voltage 2.0 V
II Input Leakage Current -10 +10 /lA GND$.VI$.VCC
IIOZ I nput/Output Leakage Current -10 +10 /lA GND$.VIO$.VCC
VIL Input Low Voltage -0.3 .8 V
VIH Input High Voltage VCC VCC V
-2.0 +0.3
VOL Output Low Voltage 0.4 V 10 = 3.2mA
VOH Output High Voltage 2.4 V 10 = -1.0mA
CIA Address Input @.> 200 pF VI = VCC or GND
Capacitance f = lMHz
CIE1 Enable Input ® 100 pF VI = VCC or GND
Capacitance (16K x 161 f = 1MHz
CIE2 Enable Input ® 50 pF VI = VCC or GND
Capacitance (32K x 81 f = 1MHz
CIG 1 Output Enable Input ® 150 pF VI =VCC or GND
Capacitance 06K x 16) f = 1MHz
CIG 2 Output Enable Input ® 100 pF VI = VCC or GND
Capacitance (32K x 81 f = lMHz
CI01 Input/Output ® 150 pF VI/O = VCC or GND
Capacitance (16K x 161 f = 1MHz
CI02 Input/Output ® 250 pF VI/O = VCC or GND
Capacitance (32 x 81 f = 1MHz
CIW Write Input ® 200 pF VI = VCC or GND
Capacitance f = lMHz
CVee Decoupling .5 IJf f = 1MHz
Capacitance
 OPERATING RANGE
Operating Supply Voltage
Supply Voltage (VCC - GND) -0.3 to 8.0V
Commercial (-5)
Input or Output Voltage Applied (GND -0.3V)
to (VCC +0.3V)
Operating Temperature
-650C to 1500C
Commercial (-5)

CAUTION: Stresses above those listed under nAbsolute Maximum Ratings" may cause permanent
damage to the device. This is a stress only rating and functional operation of the device at these or at any
other conditions above those indicated in the operational sections of this specification is not implied.

TEMP. & VCC·

OPERATING
RANGE <D
TEST
SYMBOL PARAMETER MIN MAX UNITS CONDITIONS

TELQV Chip Enable Access Time 250 ns @

TAVQV Address Access Time 270 ns @)
TELQX Ch ip Enable Output Enable Time 10 ns @)
TWLQZ Write Enable Output Disable Time 80 ns @)
TEHQZ Chip Enable Output Disable Time 80 ns @
TGLQX Output Enable Output Enable Time 10 ns @
TGLQV Output Enable Output Valid Time 70 ns @
TGHQZ Output Enable Output Disable Time 80 ns @)
TELEH Chip Enable Pulse Negative Width 250 ns @)
TEHEL Chip Enable Pulse Positive Width 100 ns
TAVEL Address Setup Time 20 ns ~
TELAX Address Hold Time 50 ns @
TWLWH Write Enable Pulse Width 250 ns @)
TWLEH Write Enable Pulse Setup Time 250 ns
TELWH Write Enable Pulse Hold Time 250 ns ~
TDVWH Data Setup Time 100 ns
TWHDX Data Hold Time 20 ns ~
TWLDV Write Data Delay Time 150 ns
TELEL Read or Write Cycle Time 350 ns ~

NOTES:
All devices tested at worst case limits.
Operating Supply Current (ICCOP) is proportional to Operating Frequency.

~ Capacitance sampled and guaranteed - not 100% tested.

(4) AC test conditions:
Input Pulse Levels: OV to 3.0V
Input Rise Time: 10ns
 T!ME INPUTS
REFERENCE T W G A DC FUNCTION

-1 H X X X Z MEMORV DISABLED
D "\ H X V Z CYCLE BEGINS, ADDRESSES ARC: LATCHED

,
1 L
L
H
H
L
L
X
X V
X OUTPUT ENABLED
OUTPUT VALID
3 f H X X V READ ACCOMPLISHED
4 H X X X Z PREPARE FOR NEXT CYCLE ISAME AS-ll
S "\ H X V Z CYCLE ENOS. NEXT CYCLE BEGINS (SAME AS 01

The address information is latched in the on chip registers cycle. After the data has been read, E may return high
on the falling edge of E (T = 0). minimum address setup (T = 3). This will force the output buffers into a high
and hold time requirements must be met. After the impedance mode at time (T = 4). G is used to disable the
required hold time, the addresses may change state output buffers when in a logical "1" state (T = -I, 0,
without affecting device operation. During time (T = 1). 3,4,5). After (T = 4) time, the memory is ready for the
the outputs become enabled but data is not valid until next cycle.
time (T = 2). Vi must remain high throughout the read

TIME INPUTS
REFERENCE ~ Vi G A DC FUNCTION

-1 H X H X X MEMORY DISABLED
0 \ X H V X CYCLE BEGINS. ADoREsses ARE LATCHED

,
1 l
L
L
f
H
H
X
X
X
V
WRITE PERIOD BEGINS
DATA IN IS WRITTEN
3 f H H X X WRITE COMPLETED
4 H X H X X PREPARE FOR NEXT CYCLE (SAME AS-I)
S "\ x H V X CYCLE ENDS, NEXT CYCLE BEGINS ISAME AS 0)

The write cycle is initiated on the falling edge ofE (T = 0). to the E rising edge. The write operation is terminated by
which latches the address information in the on chip the first rising edge ofW (T = 2) or E(T = 3). After the
registers. If a write cycle is to be performed where the minimum E high time (TEHEL). the next cycle may
output is not to become active, G can be held high (in- begin. If a series of consecutive write cycles are to be
active). TDVWH and TWHDX must be met for proper performed, the Vi line may be held low unitl all desired
device operation regardless of G. If E and ~ fall before TN locations have been written. In this case, data setup
falls (read mode). a possible bus conflict may exist. If and hold times must be referenced to the rising edge of E.
E rises before Vi rises, reference data setup and hold times
 TIME INPUTS DATA 1/0
REFERENCE "!'" W "1l A DO FUNCTION

-, H X H X Z MEMORY DISABLED

,,
0 >- H H V Z CYCLE BEGINS, ADDRESSES ARE LATCHED
L H L X X READ MODe, OUTPUT ENABLED (W· HIGH,G~ LOW)
L H L X V READ MODE, OUTPUT VALID
3 L L H X Z WRITE MODE, OUTPUT HIGH Z
4 L f H X V WRITE MODE, DATA IS WRITTEN
S f H H X Z WRITE COMPLETED
6 H X H X Z PREPARE FOR NEXT CYCLE ISAME AS -11
7 >- H H V Z CYCLE ENOS, NEXT CYCLE BEGINS ISAME AS 0)
--
If the pulse width of W is relatively short in relation to TWLWH,IN may return high. The information just written
that of E, a combination read write cycle may be perform- may now be read or Emay return high, disabling the out-
ed. If W remains high for the first part of the cycle, the put buffer and preparing the device for the next cycle.
output will become active during time (T = 1) provided Any number or sequence of read-write operations may be
G is low. Data out will be valid during time (T = 2). performed while E is low providing all timing requirements
After the data is read, IN can go low. After minimum are met.

NOTES:
In the above descriptions, the numbers in parentheses (T = nl, refer to the respective timing diagrams. The numbers
are located on the time reference line below each diagram. The timing diagrams shown are only examples and are
not the only valid method of operation.
m HARRIS
256K BUFFERED SYNCHRONOUS
HM-92570
Advanced Information CMOS RAM MODULE

• LOW STANDBY CURRENT 600J.lA/3.5rnA

• FAST ACCESS TIME 250no GND C 1 4B ::J VCC
• DATA RETENTION 2.0V rnin
A7 2 47 AO
A8 3 46 Al
• THREE STATE OUTPUTS A9 4 45 A2
• ORGANIZABLE AS 32K x 8 or 16K x 16 ARRAY Al0 5 A3
44
• BUFFERED ADDRESS AND CONTROL LINES All 6 43 A4
• ON CHIP ADDRESS REGISTERS A12 7 42 A5
• 48 PIN DIP PINOUT - 2.66" x 1.30" x 0.29" A13 8 41 A6
E1A 9 40 E1B
• WIDE TEMPERATURE RANGE
E2A 10 39 E2B
Description E3A 11 38 E3B
NC 12 37 W
The HM-92570 is a fully buffered 256K bit CMOS RAM module consisting of GA 13 36 GB
sixteen HM-6516 2K x 8 CMOS RAMs, two HD-6495 CMOS hex buffers, and NC 14 35 NC
two HD-6440 CMOS 3:8 line decoders in leadless chip carriers mounted on a NC 15 34 NC
000 16 33 DQ8
multilayer ceramic substrate. The HM-92570 RAM module is organized as two
001 17 32 009
16K by 8 CMOS RAM arrays sharing a common address bus. Separate data 002 18 31 0010
input/output buses allow the user to format the HM-92570 as either a 16K x 16 003 19 30 0011
or 32K x 8 array. 004 20 29 0012
DOS 21 28 0013
On-board CMOS buffers and decoders reduce external package count require- 006 22 27 0014
ments. Write enable and chip enable control signals are buffered along with 007 23 26 0015
address inputs. Ceramic capacitors are included on the substrate to reduce noise VCC 24 25 GND
and to minimize the need for additional external decoupling.

The synchronous design of the HM-92570 provides low operating power along
with address latches for ease of interface to multiplexed address/data bus A - Address Input
microprocessor. DO - Data Input/Output
GX - Output Enable
The HM-92570 is physically constructed as an extra wide 48 pin dual-in-line
EXX - Chip Enable
package with standard 0.1" centers between pins. This packaging technique W - Write Enable
combines the high packing density of CMOS and leadless chip carriers with the NC - No Connection
ease of use of DIP packaging.

W
G 000-7

All AO All
A12 Al A12
A13 A2 A13

E1A err G1 E1B

E2A G2 G2 E2B
Y7
E3A G3 G3 E3B

L2
-=
TI IT L2

DQO-7 GA GB 008-15
 CONNECT: PIN 16 (DOO) to PIN 33 (D08)
PIN 17 (001) to PIN 32 (D09)
PIN 18 (D02) to PIN 31 (0010)
PIN 19 (D03) to PIN 30 (D011)
PIN 20 (004) to PIN 29 (0012)
PIN 21 (005) to PIN 28 (D013)
PIN 22 (006) to PIN 27 (D014)
PIN 23 (007) to PIN 26 (D015)

CONNECT: PIN 9 (E1A) to PIN 40 (EiB)

PIN 10 (E2A) to PIN 39 (E2B)
PIN 11 (E3A) to PIN 38 (E3B)
PIN 13 (GA) to PIN 36 (GB)

The transition between blocks of RAM requires a As the HM-92570 is a synchroul1ous memory, every
change in the chip enable being used. When operating address transition must be accompanied by a chip
in the 16K x 16 mode use the chip enables as if there enable transition (see timing diagrams). More than
were only three, E1 thru E3. In the 32K x 8 mode all one chip enable low simultaneously, for devices
chip enables must be treated separately. Transitions whose outputs are tied common either internally or
between chip enables must be treated with the same externally, is an illegal input condition and must be
timing constraints that apply to anyone chip enable. avoided. To properly decode the chip enables,
All chip enables must be high at least one chip enable addresses A 11, A 12, and A 13 must be valid for the
high time (TEHEL) before any chip enable can fall. duration of TAVAV.

The lead less chip carrier packages used in the HM- completely down against the surface of the circuit
92570 have conductive lids. These lids are elec- board. The pins on the package are designed with a
trically connected to GND. The designer should standoff feature to help prevent the leadless carriers
be aware of the possibility that the carriers on the from touching the circuit board surface.
bottom side could short conductors below if pressed
 OPERATING RANGE
Operating Supply Voltage
Supply Voltage (VCC - GND) -0.3 to 8.0V
Military (-2, -8) 4.5V to 5.5V
Input or Output Voltage Applied (GND -0.3V)
Industrial (-9) 4.5V to 5.5V
to (VCC +0.3V)
Operating Temperature
-650C to 1500C
Military (-2, -8) -550C to +1250C
Industrial (-9) -400C to +850C

• CAUTION: Stresses above those listed under uAbsolute Maximum Ratings" may cause permanent
damage to the device. This is a stress only rating and functional operation of the device at these or at any
other conditions above those indicated in the operational sections of this specification is not implied.

TEMP. & VCC'

OPERATING
RANGE <D
TEST
SYMBOL PARAMETER MIN MAX UNITS CONDITIONS

ICCSB Standby Supply Current 600 IlA 10 =0

VI = VCC or GND
ICCOP Operating Supply Current @ 30 mA E= 1MHz, 10 = 0
16K x 16 VI = VCC or GND, G = VCC
ICCOP Operating Supply Current @ 15 mA E = 1MHz, 10 = 0
32K x 8 VI=VCCorGND,G=VCC
ICCDR Data Retention Supply Current 450 IlA 10 = 0, VCC = 2.0,
VI = VCC or GND, E= VCC
VCCDR Data Retention Supply Voltage 2.0 V
II Input Leakage Current -1.0 +1.0 IlA GND~VI~VCC
IIG Output Enable Leakage Current -5.0 +5.0 IlA GND ~ VI 5; VCC
IIOZ Input/Output Leakage Current -5.0 +5.0 IlA GND~VIO~VCC
VIL Input Low Voltage -0.3 0.8 V
VIH Input High Voltage 3.5 VCC V
+0.3
VOL Output Low Voltage 0.4 V 10 = 3.2mA
VOH Output High Voltage 2.4 V 10=-1.0mA
CIA Address Input @ 25 pF VI = VCC or GND
Capacitance 1= 1MHz
CIE1 Decoder Enable Input ® 50 pF VI = VCC or GND
Capacitance 116K x 161 1= 1MHz
CIE2 Decoder Enable Input ® 25 pF VI = VCC or GND
Capacitance (32K x 81 1= 1MHz
CIG 1 Output Enable Input ® 150 pF VI = VCC or GND
Capacitance (16K x 161 f = 1MHz
CIG 2 Output Enable Input ® 100 pF VI = VCC or GND
Capacitance 132K x 81 f = 1MHz
CI01 Input/Output @ 150 pF VI/O = VCC or GND
Capacitance (16K x 16) f = 1MHz
CI02 Input/Output ® 250 pF VI/O = VCC or GND
Capacitance 132 x 8) 1= 1MHz
CIW Write Input ® 25 pF VI = VCC or GND
Capacitance 1= 1MHz
CVcc Decoupling Capacitance .5 IJI 1= 1MHz
 OPERATING RANGE
Operating Supply Voltage
Supply Voltage (VCC - GND) -0.3 to 8.0V
Military (-2, -8) 4.5V to 5.5V
Input or Output Voltage Applied (GND -0.3V)
Industrial (-9) 4.5V to 5.5V
to (VCC +0.3V)
Operating Temperature
-650C to 1500C
Military (-2, -8) -550C to +1250C
Industrial (-9) -400C to +850C

CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress only rating and functional operation of the device at these or at any
other conditions above those indicated in the operational sections of this specification is not implied.

TEMP. & VCC'

OPERATING
RANGE CD
TEST
SYMBOL PARAMETER MIN MAX UNITS CONDITIONS

TELQV Chip Enable Access Time 250 ns @

TAVQV Address Access Time 270 ns @
TELQX Chip Enable Output Enable Time 10 ns @
TWLQZ Write Enable Output Disable Time 120 ns @)
TEHQZ Chip Enable Output Disable Time 150 ns @)@
TGLQX Output Enable Output Enable Time 10 ns @)
TGLQV Output Enable Output Valid Time 70 ns @)
TGHQZ Output Enable Output Disable Time 100 ns @)@
TELEH Chip Enable Pulse Negative Width 250 ns @)
TEHEL Chip Enable Pulse Positive Width 100 ns
TAVEL
TELAX
Address Setup Time
Address Hold Time
20
120
ns ~®
@)
ns
TWLWH Write Enable Pulse Width 140 ns @)
TWLEH Write Enable Pulse Setup Time 140 ns
TELWH Write Enable Pulse Hold Time 250 ns ~
TDVWH Data Setup Time 20 ns
TWHDX Data Hold Time 70 ns ~
TWLDV Write Data Delay Time 120 ns
TELEL
TAVAV
Read or Write Cycle Time
Enable Decoder Address Valid Time
350
270
ns
ns Applies
~
Only to A1 1, A12, A13

NOTES:
All devices tested at worst case limits.
Operating Supply Current (ICCOPI is proportional to Operating Frequency.
Capacitance sampled and guaranteed - not 100% tested.
~ AC test conditions:
Input Pulse Levels: OV to 3.5V
Input Rise Time: 10ns
Includes A 11, A 12, A 13
Output Disable Time is faster when using GA or GB to Disable the Outputs.
See Note 1 in Read Cycle Timing Diagram.
 OPERATING RANGE
Operating Supply Voltage
Supply Voltage (VCC - GND) -0.3 to 8.0V
Commercial (-5)
Input or Output Voltage Applied (GND -0.3VI
to (VCC +0.3V)
Operating Temperature
-650C to 1500C
Commercial (-5)

CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress only rating and functional operation of the device at these or at any
other conditions above those indicated in the operational sections of this specification is not implied.

TEMP. & VCC'

OPERATING
RANGE <D
TEST
SYMBOL PARAMETER MIN MAX UNITS CONDITIONS

ICCSB Standby Supply Current 3.5 mA 10 = 0

VI = VCC or GND
ICCOP Operating Supply Current ® 35 mA E= 1MHz, 10 = 0
16K x 16 VI = VCC or GND, G = VCC
ICCOP Operating Supply Current ® 20 mA E = 1MHz, 10 = 0
32K x 8 VI = VCC or GND. IT = VCC
ICCDR Data Retention Supply Current 2.5 mA 10 = 0, VCC = 2.0,
VI = VCC or GND, E= VCC
VCCDR Data Retention Supply Voltage 2.0 V
II Input Leakage Current -10.0 +10.0 IJA GND~VI~VCC
IIG Output Enable Leakage Current -10.0 +10.0 IJA GND~VI~VCC
1I0Z Input/Output Leakage Current -10.0 +10.0 IJA GND~VIO~VCC
VIL Input Low Voltage -0.3 0.8 V
VIH Input High Voltage 3.5 VCC V
+0.3
VOL Output Low Voltage 0.4 V 10 = 3.2mA
VOH Output High Voltage 2.4 V 10=-1.0mA
CIA Address Input 0) 25
pF VI = VCC or GND
Capacitance t = lMHz
CIE1 Decoder Enable Input @ 50
pF VI = VCC or GND
Capacitance (16K x 16) 1= 1MHz
CIE2 Decoder Enable Input ® 25
pF VI = VCC or GND
Capacitance 132K x 81 1= lMHz
CIG 1 Output Enable Input ® 150 pF VI =VCC or GND
Capacitance (16K x 16) 1= 1MHz
CIG 2 Output Enable Input ® 100
pF VI : VCC or GND
Capacitance (32K x 8) t = 1MHz
CI01 Input/Output ® 150 pF VI/O = VCC or GND
Capacitance (16K x 16l t: 1MHz
CI02 Input/Output ® 250 pF VitO = VCC or GND
Capacitance (32 x 8) 1= 1MHz
CIW Write Input ® 25 pF VI = VCC or GND
Capacitance 1= 1MHz
CVcc Decoupling Capacitance .5 pI t = 1MHz
 OPERATING RANGE
Operating Supply Voltage
Supply Voltage (VCC - GND) -0.3 to 8.0V
Commercial (-5)
Input or Output Voltage Applied (GND -0.3V)
to (VCC +0.3V)
Operating Temperature
-650C to 1500C
Commercial (-5)

CAUTION: Stresses above those listed under nAbsolute Maximum Ratings" may cause permanent
damage to the device. This is a stress only rating and functional operation of the device at these or at any
other conditions above those indicated in the operational sections of this specification ;s not implied.

TEMP. & VCC·

OPERATING
RANGE CD
TEST
SYMBOL PARAMETER MIN MAX UNITS CONDITIONS

TELQV Chip Enable Access Time 300 ns @

TAVQV Address Access Time 320 ns ®
TELQX Chip Enable Output Enable Time 10 ns ®
TWLQZ Write Enable Output Disable Time 120 ns ®
TEHQZ Chip Enable Output Disable Time 200 ns @@
TGLQX Output Enable Output Enable Time 10 ns @)
TGLQV Output Enable Output Valid Time 80 ns ®
TGHQZ Output Enable Output Disable Time 120 ns ®@
TELEH Chip Enable Pulse Negative Width 300 ns
TEHEL Chip Enable Pulse Positive Width 150 ns
TAVEL Address Setup Time 20 ns ~®
TELAX Address Hold Time 130 ns ®
TWLWH Write Enable Pulse Width 150 ns ®
TWLEH Write Enable Pulse Setup Time 150 ns
TELWH Write Enable Pulse Hold Time 300 ns ~
TDVWH Data Setup Time 30 ns
TWHDX Data Hold Time 80 ns ~
TWLDV Write Data Delay Time 120 ns
TELEL
TAVAV
Read or Write Cycle Time
Enable Decoder Address Valid Time
450
320
ns
ns
~
Applies Only to All, A12, A13

NOTES:
All devices tested at worst case limits.
Operating Supply Current (ICCOP) is proportional to Operating Frequency.

~ Capacitance sampled and guaranteed - not 100% tested.

® AC test conditions:
Input Pulse Levels: OV to 3.5V
Input Rise Time: 10ns
Includes All, A12, A13
Output Disable Tim.e is faster when using GA or GB to Disable the Outputs.
See Note 1 in Read Cycle Timing Diagram.
 m,m,E3A-
m,m,E3B
W

C!)TO I'fOIll bw __ •••• 1Il-nl-

~ __ omJ •••••••••• n•• I•••••, lJJ.
or lfI oIwtuW IftMh •••• Mill '"!tII
.n trW 01 tM , •••• _. " •••• 11011
fhIIotl I~'" tM Cllill ••••••• Cleco!Mt
'12
." _1'- OQ 11ft
0II1pU1 dill
•• 10 M 101M wltll
10""" II••,. TGMQZ
UllOf~'-bYt~_trJ,o'
TIME lII'lIl11lt't<\lhloll.
RfFERENCE

'n
TIME INPUTS "2 DATA I/O
REFERENCE ~ 1'1 ~ • .'3 DO FUNCTION

-1 H X X X X Z MEMORY DISABLED
,
0 '-
L
H
H
X
L
V
X
V
V
Z
X
CYCLE BEGINS, ADDRESSES ARE LATCHED
OUTPUT ENABLED
2 L H L X V V OUTPUT VALID
3 f H X X V V READ ACCOMPLISHED
4 H X X X X Z PREPARE FOR NEXT CYCLE (SAME AS-ll
5 '- H X V V Z CYCLE ENOS, NEXT CYCLE BEGINS (SAME AS 0)

The address information is latched in the on chip registers cycle. After the data has' been read, E may return high
on the failing edge of E(T = 0), minimum address setup (T = 3). This will force the output buffers into a high
and hold time requirements must be met. After the impedance mode at time (T = 4). G is used to disable the
required hold time, the addresses may change state output buffers when in a logical "1" state (T -1, 0, =
without affecting device operation. During time (T = 1). 3. 4, 5). After T = 4) time, the memory is ready for the
the outputs become enabled but data is not valid until next cycle. *E3A and E3B are opposite polarity of EIA.
time (T = 2). W must remain high throughout the read

An
A12
A,3
TIME t
REFERENCE -1

.n
TIME INPUTS "2 DATA 1/0
REFERENCE E Vi G • "3 DO FUNCTION

-, H X H X X X MEMORY DISABLED
0
, '-
L
X
L
H
H
V
X
V
V
X
X
CYCLE BEGINS, ADDRESSES ARE LATCHED
WRITE PERIOD BEGINS
2 L f H X V V DATA IN IS WRITTEN
3 f H H X V X WRITE COMPLETED

I 4
5
H
"'-
X
X
H
H
X
V
X
V
X
X
PREPARE FOR NEXT CYCLE (SAME AS-ll
CYCLE ENDS, NEXT CYCLE BEGINS (SAME AS 0)

The write cycle is initiated on the falling edge of E(T = 0). to the E rising edge. The write operation is terminated by
which latches the address information in the on chip the first rising edge of W (T = 2) or E(T =
3). After the
registers. If a write cycle is to be performed where the minimum E high time (TEHEL), the next cycle may
output is not to become active, 'IT
can be held high (in- begin. If a series of consecutive write cycles are to be
active). TDVWH and TWHDX must be met for proper performed. the W line may be held low until all desired
device operation regardless of G. If E and 'IT fall before W locations have been written. In this case, data setup
falls (read mode), a possible bus conflict may exist. If and hold times must be referenced to the rising edge of E.
E rises before W rises, reference data setup and hold times *E3A and E3B are opposite polarity of EIA.
 Rud Modify Writ, Cyel,
TELA X

All
A12
A13
TIME
REFERENCE

All
TIME INPUTS A12 DATA I/O
REFERENCE E Vi 13 A A13 DO FUNCTION

-1 H X H X X Z MEMORY DISABLED
0 \. H H V V Z CYCLE BEGINS, ADDRESSES ARE LATCHED
1 L H L X V X READ MODE, OUTPUT ENABLED (W· HIGH, G - LOW)
2 L H L X V V READ MODE, OUTPUT VALID
3 L L H X V Z WAITE MODE, OUTPUT HIGH Z
4 L f H X V V WRITE MODE, DATA IS WRITTEN
5 f H H X V Z WRITE COMPLETED
6 H X H X X Z PREPARE FOR NEXT CYCLE (SAME AS -1)
7 \. H H V V Z CYCLE ENDS, NEXT CYCLE BEGINS (SAME AS 0)

If the pulse width of W is relatively short in relation to written may now be read or E may return high, disabling
that of E, a combination read write cycle may be per- the output buffer and preparing the device for the next
formed. If W remains high for the first part of the cycie, cycle. Any number or sequence of read-write operations
the output will become active during time (T = 1) pro- may be performed while E is low providing all timing
vided G is low. Data out will be valid during time (T =2). requirement are met. *E3A and E3B are opposite polar-
After the data is read, W can go low. After minimum ity of E1A.
TWLWH, W may return high. The information just

NOTES:
In the above descriptions, the numbers in parentheses (T = 1), refer to the respective timing diagrams. The numbers
are located on the time reference line below each diagram. The timing diagrams shown are only examples and are
not the only valid method of operation.
;II HARRIS HM-6641

• LOW POWER STANDBY 600/JW MAX.

• LOW POWER OPERATION 60mW/MHz MAX.
A7 vcc
• FAST ACCESS TIME 260no MAX. AS AS

• FIELD PROGRAMMABLE AS Gl
• POLYSILICON FUSE LINKS A4 G2
• TTL COMPATIBLE IN/OUT A3 G3

A2
• POPULAR PINOUT LIKE BIPOLAR 7641
Al
• THREE STATE OUTPUTS
AO 07
• ADDRESS LATCHES INCLUDED ON CHIP
00 OS
• EASY MICROPROCESSOR INTERFACING
01 OS
• WIDE TEMPERATURE RANGES
02 04

GNO 03

PIN NAMES

A Address Input G Output Enable

The HM-6641 is a 512 x 8 CMOS polysilicon fusible link Programmable a Data Output P Program Enable
Read Only Memory in the popular 24 pin, byte wide pinout. Synchronous E Chip Enable (p. GNDexcept during
NC No Connect Programmingl
circuit design techniques combine with CMOS processingto give this device
high speed performance with very low power dissipation.

On chip address latches are provided, allowing easy interfacing with recent
generation microprocessorsthat use multiplexed address/data bus structures,
such as the 8085. The output enable controls, both active low and active
high, further simplify microprocessor system interfacing by allowing output
data bus control independent of the chip enable control. The data output
latches allow the use of the HM-6641 in high speed pipelined architecture
systems, and also in synchronous logic replacement functions.

Applications for the HM-6641 CMOS PROM include iow power handheld
microprocessor basedinstrumentation and communications systems, remote
data acquisition and processingsystems, processor control store, and synch-
ronous logic replacement.

AL.L. LINES POSITive LOGIC-

ACTive HIGH

THREE STATE BUFFERS:

A HIGH ••.•. OUTPUT ACTive

DATA LATCHES:
LHIGH-a-O
a LATCHES ON RISING EDGE OFt"
ADDRESS LATCHES AND GATED
DECODERS:
LATCH ON FALLING EDGE OF!'
GATE ON FALLING EDGE OF'r
 Operating Supply
Military (-2/-8) 4.5V to 5.5V
Input or Output Voltage Applied GND -O.3Vto Industrial (-9) 4.5V to 5.5V
VCC +O.3V
Operating Temperature
Military (-2/-8) -550C to +1250C
Industrial (-9) -400C to +850C

* CAUTION: Stresses above those listed under I~bsolute Maximum Ratings" may cause permanent
damage to the device. This is a stress only rating and functional operation of the device at these or at any
other conditions above those indicated in the operational sections of this specification is not implied.

TEMP & VCC =

OPERATING TEMP=25OC
RANGE VCC=5.0 Q) TEST

SYMBOL PARAMETER MIN MAX TYPICAL UNITS CONDITIONS

ICCSB Standby Supply Current 100 10 J.lA 10 =0

VI = GND OR VCC

ICCOP Operating Supply Current@ 10 5 mA f = lMHz, 10 =0

VI = VCC or GNO

II Input Leakage Current -1.0 +1.0 0.0 J.lA GNDSVISVCC

10Z Output Leakage Current -1.0 +1.0 :!:0.5 J.lA GNDSVOS,VCC

VIL Input Low Voltage -0.3 O.B 2.0 V

VIH Input High Voltage VCC-2.0 VCC+0.3 2.0 V

VOL Output Low Voltage 0.4 0.1 V 10L = 3.2mA

VOH Output High Voltage 2.4 4.25 V 10H = -1.0mA

CI I nput Capacitance ® 10.0 5.0 pF VI = VCC or GND

f= lMHz

CO Output Capacitance@ 12.0 8.0 pF VO = VCC OR GND

f= lMHz

TELQV Chip Enable Access Time 250 150 ns @)

TAVQV (TAVQV = TELQV + TAVEL)
Address Access Time 270 150 ns @)
TELQX Chip Enable Output Enable Time 20 150 70 ns @)
TGVQX Output Enable Output Enable Time 20 150 70 ns @)
TGXQZ Output Enable Output Disable Time 20 150 70 ns @)
TELEH Chip Enable Pulse Negative Width 250 150 ns @)
TELEL Read Cycle Time 400 230 ns @)
TEHEL Chip Enable Pulse Positive Width 150 80 ns @)
TAVEL Address Set-up Time 20 0 ns @)
TELAX Address Hold Time 60 40 ns @)

NOTES:

Q) All devices tested at worst case limits. Room temp., 5 volt data provided for information - not guaranteed.
Operating Supply Current (ICCOP) is proportional to Operating Frequency. Example: Typical ICCOP = SmA/MHz.
Capacitance sampled and guaranteed - not 100% tested.

~ AC Test Conditions: Inputs-TRISE = TFALL = 20nsec; Outputs -CLOAD = 50pF. All timing measurements
at 1.5V.
 TIME INPUTS OUTPUTS
REFERENCE E G A 0 FUNCTION

-1 H H X Z MEMORY DISABLED
0 "X. H V Z CYCLE BEGINS-ADDRESSES ARE LATCHED
1 L L X X OUTPUT ENABLED
2 L L X V OUTPUT VALID
of
3 L X V OUTPUT LATCHED
4 H H X Z READ ACCOMPLISHED AND OUTPUT DISABLED
5 H H X Z PREPARE FOR NEXT CYCLE (SAME AS -1)
6 "X. H X Z CYCLE ENDS, NEXT CYCLE BEGINS (SAME AS Ol

In the HM-6641 read cycle, the address information is the data outputs and begin TEHEL. Taking either or
latched into the on chip registers on the falling edge of both G1 or G2 high or G3 low will force the output buffers
E(T = 0). Minimum address setup and hold time require- to a high impedance state. The output data may be 're-
ments must be met. After the required hold time,the enabled at any time taking G1 and G2 low and G3 high.
addresses may change state without affecting device opera- On the falling edge of E the data will be unlatched. P
tion. To read data G1 and G2 must be low, and G3 must should be grounded except when in the programming mode.
be high. After access time, E may be taken high to latch

the PROM is inserted into the socket. VCC must be

applied to the PROM before any input or output pin
is allowed to rise'.
The HM-6641 is a 512 word, by 8 bit field programmable
read only memory utilizing polycrystalline silicon fusible
links as programmable memory elements. Selected mem-
ory locations are permanently changed from their manu-
factured state, of all low (VOL) to a logical high (VOH),
by the controlled application of programming potentials 1. The address of the first bit to be programmed is
and pulses. Careful adherence to the following program- presented, and latched by the chip enable (E""l falling
ming specifications will result in high programming yield. edge. The output is disabled by taking the output
80th high VCC (6.0 volts) and low VCC (4.0 volts) verify enable (G) high.
cycles are specified to assure the integrity of the pro-
grammed fuse. This programming specification, although 2. VCC is raised to the programming voltage level, 12.5V.
complete, does not preclude rapid programming. The worst
case programming time required is 37.4 seconds, and typ- 3. The data output pin corresponding to the bit to be
ical programming time can be approximately 4 seconds programmed is pulled low. All other bits in the
per device. word are pulled up to VCC (at the programming
level).
The chip (E'") and output enable (G) are used during the
programming procedure. On PROM's which have more 4. A 500 11 s pulse is applied to the programming con-
than one output enable control G1 is to be used. The trol pin (P).
other output enables must be held in the active, or enabled,
state throughout the entire programming sequence. The 5. The data output pin is returned to VCC, and the VCC
programmer designer is advised that all pins of the pro- pin is returned to 6.0 volts.
grammer's socket should be at ground potential when
6. The address of the bit is again presented, and latched 2. The address drivers must be able to maintain input
by a second chip enable falling edge. voltage levels ~70% VCC for VIH, and~20% VCC for
VI L. The programming system designer has a choice
7. The data outputs are enabled,and read, to verify that between buffers that will track VCC up and down
the bit was successfully programmed.. (e.g. open collector buffers with pUll up resistors)
a). If verified, two post programming pulses are or buffers used for VIH only at 4.0V and 6.0V and
applied (the bit is programmed twice more). returned to VI L when the system is at program-
Then the next bit to be programmed is ad- ing voltages.·
dressedand programmed .
3. The control input buffers have the same 70% and 20%
b). If not verified, the program/verify sequence is
VCC requirements as the address buffers. Notice that
repeated up to 8 times total, at the program-
chip enable (EI does not require a pull up to pro-
ming voltage level,12.5 volts.
gramming voltage levels, but that the output enable
c). If data is not verified, the programming voltage (GT must have a pull up to track VCC up and down.
is increased to +14.0 volts. The program/verify The program control (P) must switch from ground
sequence is then repeated up to 8 additional to programming VCC level.·
times.
4. The data input buffers must be able to sink up to 3mA
8. After all bits to be programmed have been
from the PROM's output pins without rising more than
verified at 6.0 volts, the VCC is lowered to
0.7 volts above ground, be able to hold the other
4.0 volts and all bits are verified.
outputs high with a current source capability of 0.5mA
a). If all bits verify, the device is properly programmed.
to 2.0mA, and not interfere with the reading and ver-
b). If any bit fails to verify, the device is rejected. ifying of the data output of the PROM. Notice that
a bit to be programmed is changed from a low state
(VOL) to high (VOH) by pulling low on the output
pin. A suggested implementation is open collector
1. The power supply for the device to be programmed TTL buffers (or inverters) with 4.7Kn pull up resis-
must be able to be set to four voltages; 4.0V, 6.0V, tors to VCC.·
12.5V,14.0V. This supply must be ableto supply500mA
average, and 1A dynamic, currents to the PROM ·Note: Never allow any input or output pin to rise more
during programming. The power supply rise fall than 0.3 volts above VCC, or fall more than
times when switching between voltages must be no 0.3 volts below ground.
quicker than 1/01
s.

PARAMET~ NAME MIN TARGET MAX UNITS

VCCN Normal VCC 5.76 6.0 6.26 volts

VCC POM Programming Voltage 12.0 12.6 14.0 volts
VCC LV Low Voltage Verifv VCC 3.76 4.0 4.26 volts
ICC Svstem ICC Capabllitv 500 mA
ICC Peak Transient ICC Capabilitv 1.0 A
For PROM Input Pins:
VOL Output Low Voltage
(to PROM) -0.3 OND 20% VCC volts
VOH Output High Voltage
(to PROM) 70% VCC VCC VCC +0.3 volts
IOL Output Sink Current
(at VOLl .01 mA
IOH Output Source Current
(AtVOH) .01 mA
For PROM Date Output Pins:
VOL Output Low Voltege
(to PROM) -0.3 OND 0.7 volts
VDH Output High Voltage
(to PROM) 70% VCC VCC VCC +0.3 volts
IOL Output Sink Current
(at VOL) 3.0 mA
IOH Output Source Current
(at VOH) 0.5 1.0 2.0 mA
 SYMBOLS PARAMETER MIN MAX UNITS

TAVEL Address Set-up Time 500 ns

TElAX Address Hold Time 500 ns
TEHEL Chip Enable High Time 500 ns
TELVP Chip Enable Low to VCC Rising Delay 500 ns
TGHVP Output Enable High to VCC Rising Delay 500 ns
TGHQZ Output Disable Time 150 ns
TRISE VCC Rise Time (to PGM Voltage) 1.0 IJ.s
TVPQl VCC High (PGM) to Output Low Delay 500 ns
TQLPH Programming Data Setup Time 500 ns
TPHPL Programming Pulse Width 450 550 IJ.s
TPLQH Programming Data Hold Time 500 ns
TQHVN Output High to VCC Normal Delay 500 ns
TFALL VCC Fall Time ( to Normal VCC) 1.0 IJ.s
TVNEH VCC Normal to Chip Enable High Delay 500 ns
TVNGL VCC Normal to Output Enable Low Delay 500 ns
TELQV Chip Enable Access Time 500 ns
TGLQV Output Enable Access Time 500 ns
TGLQX Output Enable Time 150 ns

A ...•
12.5

E ...•
G ...•
12.5

vee
...
12.5
TGHV

OUTPUT HIGH·
LEAVE BIT LOW
- - - -OUTPur-LOw-. - - - -
PROGRAM BIT HIGH

TOLPHlr---J" TPLOH

-------------~tl_TPHPLj----------------------
m HARRIS
HM-6616
2K X 8 CMOS PROM
Pinout
TOP VIEW
• LOW STANOBY ANO OPERATING POWER
• ICCSB • 50~All00""
A7 yee
• ICCOp· 13mA/MHz AI AI

• FAST ACCESSTIME A5 Ai

• INOUSTRY STANDARD PINOUT A4 P

SINGLE 5.0 VOLT SUPPLY A3 if
• TTL COMPATIBLE INPUTS A2 Al0
• HIGH OUTPUT DRIVE Al E
• SYNCHRONOUS OPERATION AD 07
• ON·CHIP ADDRESS LATCHES
00 01
• SEPARATE OUTPUT ENABLE
0' 05
• FULL INDUSTRIAL AND MILITARY TEMPERATURE RANGES
02 04
GNO 03

PIN NAMES
Description A Addrenlnpul If" Output Eneble
Q 0111 Output ,.. Progr.mEneble
The HM-6616 is a 16,384 bit fuse link CMOS PROM in a 2K word by 8 bit/word format
r ChIp Enlbll (,- • vec exclpt during
with' 'Three State" outputs. This PROM is available in the standard 0.600 inch wide Progrlmmlngj
24-Pin DIP, the 0.300 inch wide slimline DIP, and the JEDEC standard 32-Pin LCC.
The HM-6616 utilizes a synchronous design technique. This includes on-chip
address latches and a separate output enable control which makes this device ideal for
applications utilizing recent generation microprocessors. This design technique,
combined with the Harris advanced self-aligned silicon gate CMOS process
technology offers ultra-low standby current. Low ICCSB is ideal for battery applica-
tions or other systems with low power requirements.
The Harris polysilicon fuse link technology is utilized on this and all other Harris CMOS
PROMS. This gives the user a PROM with permanent, stable storage characteristics
over the full industrial and military temperature and voltage ranges. Polysilicon fuse
technology combined with the low power characteristics of CMOS provides an
excellent alternative to standard Bipolar PROMS or NMOS EPROMS.
All bits are manufactured storing a logical' '0" and can be selectively programmed for
a logical "1" at any bit location.

ALL LINES POSITIVE LOGIC:

ACTIVE HIGH
THREE STATE BUFFERS:
A HIGH OUTPUT ACTIVE
ADDRESS LATCHES AND GATED DECODERS:
LATCH ON FALLING EDGE OF E
GATE ON FALLING EDGE OF G
P = VCC EXCEPT DURING PROGRAMMING
 Supply Voltage + 7.0 Volts
Input/Output Voltage Applied GND-0.3V to VCC+0.3V
Storage Temperature Range - 65°C to + 150°C
Operating Temperature Range
Military - HM·6616·2/·8 - 55°C to + 125°C
Industrial - HM-6616-9 - 40°C to + 85°C
Operating Voltage Range +4Vto+7V

* CAUTION: Stresses ebove those fisted under the "ABSOLUTE MAXIMUM RATINGS" mey cause
permanent damaqe to the device. This is a stress only fetina and operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is nor implied

D.C. ELECTRICAL CHARACTERISTICS VCC = 5.0V ±10%; TA = Industrial -40°C to +85°C (HM-6616-9)
= Military -55°C to +125°C (HM-6616-2/-8)

TEST
SYMBOL PARAMETER MIN MAX UNITS CONDITIONS
VIH Logical One 2.4 V
Input Voltage
VIL Logical Zero 08 V
Input Voltage
VOH Logical One 2.4 V 10H = -2.0 mA
Output Voitage
VOL Logical Zero 0.4 V 10L = +4.8 mA
Output Voltage
II Input Leakage -1.0 1.0 p.A OV~VIN~VCC
10Z Output Leakage -1.0 1.0 p.A OV~VO~ VCC
G = HIGH
ICCSS Standby Power
Supply Current 100 p.A VIN = VCC or GND
VCC = 5.5 V
10 = 0
ICCOP Operating Power
Supply Current 15 mA f = 1 MHz
VCC = 5.5 V
10 = 0
VIN = VCC or GND
CIN Input 10 pF f = 1 MHz
Capacitance· VIN = VCC or GND
COUT Output 12 pF f = 1 MHz
Capactiance· VIN = VCC or GND
 Specifications HM·6616·9/·2/-B
A.C. ELECTRICAL CHARACTERISTICS VCC = 5.0V ± 10%; TA = Industrial -40°C to +B5°C (HM-6616-9)
= Military -55°C to + 125°C(HM-6616-2/-B)
TEST
SYMBOL PARAMETER MIN MAX UNITS CONOITIONS

TAVQV Address Access Time 140 ns see notes 1,2

TELQV Chip Enable Access Time 120 ns

TELQX Chip Enable Time 5 ns

TAVEL Address Setup Time 20 ns

TELAX Address Hold Time 25 ns

TELEH Chip Enable Low Width 120 ns
TEHEL Chip Enable High Width 40 ns
TELEL Cycle Time 160 ns
TGLQV Output Access Time 50 ns
TGLQX Output Enable Time 5 ns
TGHQZ Output Disable Time 50 ns
TEHQZ Chip Enable Disable Time 50 ns

Switching Waveforms
_______ TAVQV • I
I

I
I , •..•
•• ----<I---------TELEL- !------------.-.. I
••.
I t-+-
~TAVEL~ TELAX I I
2,.5V \!"' TELEH -V ~I 3.0V
l\.'5V I 1:, '.5V 1.5V
E~ I I· ov
I---TEHEL • I• TELQV • I --.lTEHQZI--
I I I
I I--TGLQV~ I
I 1.5v\ I f,·5V I
I I· 1'1 I
I -!TGLQXI-- I I I
I "..-.j TGHQZ ~

DATA
OUTPUT
I· TELQX--i<liX'
_ VALID
I
""__-------.
00-0, DATA /' T.S.

Figure 1 Read Cycle

50Pf•

I "Includlnq IIQ and probe capacitance

 Supply Voltage + 7,0 Volts
Input/Output Voltage Applied GND-0,3V to VCC+0,3V
Storage Temperature Range - 65'C to + 150'C
Operating Temperature Range
Military - HM-6616-2/-8 -55°C to +125°C
Industrial - HM-6616-9 - 40°C to + 85°C
Operating Voltage Range +4Vto +7V

* CAUTION' Stresses above those I,sted under the "ABSOLUTE MAXIMUM RATINGS" mey cause
permanent damaqe to the devIce. This is a stress only ratmq and operation of the device at these or any
other conditions above those indicated In the operatlonsl sectIons of this specIficatIOn IS not implied.

D.C. ELECTRICAL CHARACTERISTICS VCC = 5,OV ±10%; TA = Industrial -40°C to +85°C (HM-6616B-9)
= Military -55°C to + 125°C (HM-6616B-2/-8)

TEST
SYMBOL PARAMETER MIN MAX UNITS CONDITIONS
VIH Logical One 2.4 V
Input Voltage
VIL Logical Zero 0,8 V
Input Voltage
VOH Logical One 2.4 V 10H = -2.0 mA
Output Voltage
VOL Logical Zero 0.4 V 10L = +4,8 mA
Output Voltage
II Input Leakage -1,0 1,0 p.A OV:sVI N :s VCC
10Z Output Leakage -1.0 1,0 p.A OV:SVO:s VCC
G = HIGH
ICCSB Standby Power
Supply Current 50 p.A VIN = VCC or GND
VCC = 5.5 V
10 = a
ICCOP Operating Power
Supply Current 15 mA f = 1 MHz
VCC = 5,5 V
10 = a
VIN = VCC or GND
CIN Input 10 pF = 1 MHz
f
Capacitance· VIN = VCC or GND
COUT Output 12 pF f = 1 MHz
Capactiance· VIN = VCC or GND
 TEST
SYMBOL PARAMETER MIN MAX UNITS CONOITIONS

TAVQV Address Access Time 105 ns see notes 1.2

TElQV Chip Enable Access Time 90 ns
TElQX Chip Enable Time 5 ns

TAVEL Address Setup Time 15 ns

TELAX Address Hold Time 20 ns
TELEH Chip Enable Low Width 90 ns
TEHEL Chip Enable High Width 30 ns
TELEL Cycle Time 120 ns
TGLQV Output Access Time 40 ns
TGLQX Output Enable Time 5 ns
TGHQZ Output Disable Time 40 ns
TEHQZ Chip Enable Disable Time 45 ns

Switching Waveforms
_______ TAVQV " I
I

I I
I I•..•
-- ..•
I------TELEL-+I----------- ~I
•.••
I ~TAVEL~ TELAXt--- I 1
.11.5V {"-
~5V
TELEH
I
"/11.5V ~I
1.5V
3.0V
E-Ij 1- I·
1
ov
I---TEHEL .1 • TELQV " I ---+1TEHQZI---
1 I I
I I-+-- TGLQV ---1 I
I 15V\ I f15V I
1 I· I·' I
I -JTGLQXI-- I I I
I I 1 ---J TGHQZ ~
DATA
OUTPUT I" TELQX~ 6A_A~_\f ) ...••.•
I-------T.s.
Clo-Q,

Figure 1 Read Cycle

50P!"

I ·m •.•ludmQ 110 ilna O'uOe -:CloaCllance

The HM-6616 PROM is manufactured with all bits storing a logical 15) After a delay of td apply G = VIL Following a delay of td
"0" (output low). Any desired bit can be selectively examine the outputs for correct data.
programmed to a logical "1" (output high) by following the 16) If any location verifies incorrectly, repeat steps 4 through 15
procedure shown below. One may build their own programmer to (attempting to program only those bits in the word which
satisfy the specifications shown, or use any of the approved com- verified incorrectly) up to a maximum of eight attempts for any
mercially available programmers. given word. If a word does not program within eight attempts,
it should be considered a programming reject.
PROGRAM SEQUENCE OF EVENTS
17) Repeat steps 4 through 16 for all other words in the PROM.
1) Apply Vcdpin 24) = VCC1 to the PROM.
2) Read all fuse locations to verify (blank check) a 100% VOL POST PROGRAMMING VERIFICATION
(unprogrammed) condition. 18) Place the PROM in the post-programming verify mode. E=
3) Place the PROM in the initial state for programming. E= VIH, VIH, G = VIL, P = VIH. VCC(pin 24) = VCC1.
P = VIH, G = VIL 19) Apply the correct binary address of the word to be verified.
4) Apply the current binary address for the word to be pro- 20) After a delay of td, apply E= VIL
grammed. An open circuit should not be used to address the
PROM. 21) After a delay of td apply G = VIH to disable the outputs (out-
puts are tied to VCC through pull-up resistors Rn).
5) Apply E= VIL after a delay of td to access the addressed
word. 22) After a delay of td apply P = VIL
6) Address may be held throughout cycle, but must be held at 23) After '!Jlelay of td apply E= VIH for duration TEHEL, then
least time td (address hold time), after E = VIL apply E = VIL
7) After a delay of td tristate the outputs by applying G= VI H. 24) After a delay = TELPH2 apply P = VIH.
8) After a delay of td apply P= VIL. 25) After a delay of td apply G = VI L to enable the outputs. After a
delay of td examine the outputs for correct data.
9) After a delay of td raise VCC(pin 24) to VCCPROG with rise
time = tr. All signals at VIH should track VCC(pin 24) within 26) Repeat steps 19 through 25 for all possible address locations.
VCC-2V to VCC + 0.3V (including outputs - pull-up resistors
Rn to VCC would suffice). POST PROGRAMMING READ
10) After a delay of td pUll the output to be programmed to VIL 27) Apply VCC2 = 4.0V to VCC(pin 24).
After a duration tpw, allow the output to be pulled to VIH
through the pUll-up resistor Rn.
28) After a delay of td, apply E= VIH.
29) Apply the correct binary address of the word to be read.
11) Repeat step 10 for all other bits to be programmed in the
add res sed word. 30) After a delay of TAVEL, apply E= VIL
12) Lower Vcc(pin 24) to VCC1 with a fall time If. Signals at VIH 31) After a delay ofTELQV, examine the outputs for correct data. If
should track VCC (pin 24) in range VCC-2V to VCC+0.3V. any bit verifies incorrectly, the device is to be considered a
programming reject.
13) After a de@}' of td apply E= VIH for duration of TEHEL, and
the apply E = ViL 32) Repeat steps 28 thru 31 for all other words in the PROM.
14) After a delay = TELPH1, apply P = VIH. 33) Repeat steps 27 thru 32 for VCC2 = 6.0V applied to
VCC(pin 24)
 VCCPROG
VIH
-

AX VIL -J1'••
---,;:-----1
V.,A.L1
••
0
••-------
,,
•••
_
_

I I I TEHELI

fVIH
~ld.J
\.... -:~
I-I
r
VIL -
VCCPROG
- I I _------_ I I
ifVIH - II.td•• ~--_. 1 "• I
1 I
I
VIL ----1--.1 I
,
ld~
I
I
I
I I
I TELPHl '.ld.1
\
-----

PV'Hi
VIL -
I
1
t+ <I ••••• ll~F •••trJ-
:I :~1 II
I

-T\~,:::
VCCP~~~ - ! ~ld.V: ~~ I

•'.~~:~:
=---1~-;- ---
X VOL/VIL ._._. '
B=::~
ildt , •
m

'-! .
VALID I td I

VIH __ ••••••••••• -. __ ---_. __ ---

AX VIL ][ VALID ][ VALID , YALID

- VIH
EVIL
:"ld

I l I I.TEHEi I

H
I.• ld.t

..
'__
:......, TAVEL

p==t{~T_EH_E_L_ld_"_1MT_E_HE_L_
I I r-! TAVEL

I I I I: I
VIH I+td.j I I I I I

if VIL ------ ••1

r-td-+l+td+t
I : :TELPH21
'-t+td+l
~ :
I
I
I
~
I
- VIH - 1 I 11--1--- I I I
P VIL \ ••• " I i i I

VCC2•• 6.0V -
II
I I
lill~1
I I I \"
vcc VCC2••V4~~~- - - - - - - - - - - - - - - - - - - - - - i__
I
-~ I
:
~
I
TELQV- I '-

ax
VOH/VIH
VOLIVIL ---- ••
CD
-l
I
I ~
td~- I ,,)
R~ADDATA
TELQVI
m----P=I
READDATA
I

READDATA
POSTPROGRAM
READ
 SYMBOL PARAMETER MIN TYP. MAX. UNITS

VIL Input "0" 0.0 0.2 0.8 V

VIH (1) Voltage "1" VCC-2 VCC VCC+0.3 V

VCCPROG(2) Programming VCC 13.5 14.0 14.0 V

VCC1 Operating VCC 4.5 5.0 5.5 V
VCC2 (3) Special Verify VCC 4.0 ---- 6.0 V

td Delay Time 1.0 1,0 .--- us

tr Programming VCC 1.0 10.0 100 us

If Rise and Fall Times 1.0 10,0 10.0 us

TEHEL Chip Enable Pulse Width 50 ---- ---- ns

TAVEL Address valid to Chip 20 ---- ---- ns

Enable low time

TELQV Chip Enable low to ---- ---- 120 ns

Output Valid time

TELPH1 (4) E Low to 400 500 600 us

TELPH2 (5) PHigh Time 5,0 5,0 10.0 us
tpw (6) Programming Pulse Width 0.9 1.0 1.1 ms
liP Input Leakage at VCC = VCCPROG -10 +1.0 10 uA

lOP Data Output Current at ---- -5.0 -10 mA

VCC = VCCProg

Rn (7) Output pull-up 5 10 15 kohms

resistor
Ta Ambient Temperature ---- 25 ---- °C
Notes: 1) All inputs must track VCC(pin 24) within these limits
2) VCCPROG must be capable 01 supplying 500mA,
3) See steps 27 thru 3301 the programming algorithm.
4) See steps 13 & 1401 the programming algorithm.
5) See steps 23 & 24 01 the programming algorithm.
6) See step lOot the programming algorithm.
7) All outputs should be pulled up to VCC thru a resistor ot value Rn.
;II HARRIS HM-6664

Pinout
TOP VIEW DIP
• 175ns MAXIMUM ADDRESS ACCESS TIME

• LOW STANDBY CURRENT - 100/.1. MAXIMUM OVER THE

vpp vec
VOLTAGE AND TEMPERATURE RANGE .12 P
A7 NC
• LOW OPERATING CURRENT - 10m. AT lMHz AS A8
AI5 A9
• JEDEC STANDARD 28-PIN DIP
A4 All
• PIN COMPATIBLE WITH 2764 UV EPROM .3 a
A2 A10
• ASYNCHRONOUS OPERATION
Al E
• "THREE STATE" OUTPUT CONTROL WITH G, AND E AO 07
co Q6
• GATED INPUTS - REMOVING THE NEED FOR PULL-UP OR
al Q5
PULL-DOWN RESISTORS
Q2 Q4

• SELF-POWER DOWN IN THE READ MODE GND Q3

Description
The HM-6664 is a 65,536 bit fuse link CMOS PROM in an input Go The output enable input is used to "Three State"
8K word by 8 bit/word format with "Three State" outputs. the output buffers by bringing G high. Bringing the chip
This PROM is available in the JEDEC standard 28 pin 0.600" enable input E high will "Three State" the output buffers,
wide DIP. place the device in the standby power mode and gate the
input buffers. Gated input buffers allow the user to float
The HM-6664 utilizes advanced design techniques coupied the inputs after chip enable E has gone high without ex-
with the Harris advanced self-aligned silicon gate CMOS ceeding the ICCSB specification due to excessive current
process technology. This provides a high speed PROM with drain in the input buffers. This eliminates the need for
ultra-low standby current. Low ICCSB is ideal for battery pull-up or pull-down resistors.
applications or other systems with low power requirements.
In addition, there is an input edge activated, retriggerable
The Harris polysilicon fuse link technology is utilized on one-shot circuit internal to the HM-6664 which automatic-
this and all other Harris CMOS PROMS. This gives the user ally reduces the supply current to the power down standby
a PROM with permanent, stable storage characteristics over mode (ICCPD) after an address transition has been made
the full industrial and military temperature and voltage and no further input transitions are made for approximate-
ranges. Polysilicon fuse technology combined with the low ly , micro second. The device will stay in the power down
power characteristics of CMOS provides an excellent mode untii another input transition takes place.
alternative to standard Bipolar PROMS or NMOS EPROMS.
All bits are manufactured storing a logical "0" and can be
selectively programmed for a logical"'" at any bit location.

MSB
A12

..
All
A'
A'
,
A7
A'
A'
A'
LSB

MSB
AIO
A3
A'
A'
AO
LSB
 Data Entry Formats for
Harris Custom Programming*

For Harris to custom program to a user data pattern specification, the user must supply the
data in one of the following formats:
1. Master PROM of same organization and pinout as device ordered. Two pieces re-
quired, three preferred.
2. Paper tape in Binary or ASCII BPN F.

• A minimum of six inches of leader.

• A rubout (all eight locations punched).
• Data words beginning with the first word (word "O"l, proceeding sequentially, end-
ing with the last word (word "N"l, with no interruptions or extraneous characters
of any kind.
• Specify whether a punched hole is a VOH = "1" = logic high or is a VOL = "0" =
logic low.
• A minimum trailer of six inches of tape.

• A minimum leader of twenty rubouts (all eight locations punched).

• Any characters desired (none necessary) except "B".
• Data words beginning with the first word (word "O"l, proceeding sequentially, end-
ing with the last word (word "N").
• Data words consist of:
1. The character "B" denoting the beginning of a data word.
2. A sequence of characters, only "P" or "N", one character for each bit in
the word.
3. The character "F" denoting the finish of the data word.
• No extraneous characters of any kind may appear within a data word (between any
"B" and the next "F").
• Errors may be deleted by rubouts superimposed over the entire word including the
"B", and beginning the word again with a new "B".
• Any text of any kind (except the character "B") is allowed between data words
(between any "F" and the next "B"), including carriage return and line feed.
• A minimum trailer of twenty-five rubouts.
• Specify whether a "P" is a "1" = VOH = logic high or is a "0" = VOL = logic low.
• The use of even or odd parity is optional.

* Harris can not assume responsibility for PROMs programmed to data tapes or masters which contain errors.
The user must insure the accuracy of the data provided to Harris. Harris guarantees that the programmed
PROMs will contain the information provided if either of the following formats are followed.
 D;,ection t
t of Tape
Flow
Punched Hole = "0" = VOL = Logic Low

'" 0
o .• ,SP,OCk8t Word PROM Output Data eD
Holes
0
I
!••• .0o.• rr-
Channel 8 7 6 5 4 3 2 1
Channel 1
0 AX···A2 A1 AO Output 08 07 06 05 04 03 02 01
0 Channel 8
0 o .... 0 0 0 First 0 1 0 0 0 1 0 1
o .... 0

•• o. :.• •T';"'W~'
•••• '-- Rubout 0 1 Second 1 1 1 0 1 0 0 0
0 .... 0 1 0 Third 0 1 0 1 1 1 0 0
••• 0 o .... 0 1 1 Fourth 0 1 1 1 0 1 1 0
0 0 1 0 0 Fifth 1 0 0 1 0 0 0 1
• • .0
• •
•• 1 •••• 1 1 Last
T 0 0 0 0 1 0

A
• .0
0
•• .'" Last Word NOTES,

CD PROMs with 4 bit wide data outputs require punching only

first 4 channels on tape (Channels 1 thru 4).

0 On HARR IS PROMs Ox (Example: 0,) designates a respective

output pin on the device. 0, (Output 1) is always LSB.

91011012
6 7 8 0911121314

~ tJ- Output 8 (08)

Output 1 (01)
 FIRST WORD SECOND WORD LAST WORD
A A A
RUBOUTS /'---- ----~, /'---- ---- ••••
, /'---- ---- ••••
, RUBOUTS

1111 ~~~~~~r Ir I:I~~~ r IIr Ir III~ r Ir ~ ~ r ~ r ~ r ((( ((

........ ,
i' •••• •••••
Parity is optional.

•••••••••••••• ••••••••••• •••• • ••

•••• • ••••
••••
l •••• • • • ••• ••• • • • • •••••
1 o • ••• • •
0 00 0000000 • ••• o o• •• o • o • •••••
000000 000 0 00000 0 0 0 0 0 0 000000
•••• • ••• • • • • • •••••••
••• • •• • •••••••
~ •••••• ••• • • • • • .. •• •
••••••• <
j •••• • ••••• I!'

HM-6611 1211109 (MOS)

Truth Table
HM-7649 1413 1211 9 8 7 6 Character"0" = "1" = VOH = Logic High
Character"V" = "0" = VOL = Logic Low

0·····0 0 0 First 0 000 1 0 1

0·····0 0 1 Second 1 101 000
1 ·····0 1 0 Last
i 0 o 0 1 0 0

NOTES:
Q) In the ASCII BPNF format, MSB data is punched after "B". On
devices with 8 outputs, Os (Output 81 data is punched after "8".
On devices with 4 outputs. 04 (Output 4) data is punched
after "B".

CMOS
MEMORY
I
;II HARRIS HPL-16LC8

• PIN 8< FUNCTION COMPATIBLE WITH THE BIPOLAR l6L8 PAL™ • 20 PIN SLiMLINE DIP

• SCALED SAJI IV CMOS PROCESS • SECURITY FUSE FOR PATTERN PROTECTION

• FAST ACCESS (INPUT TO OUTPUT) • TTL/CMOS COMPATIBLE INPUTS/OUTPUTS FOR MIXED

SYSTEM COMPATIBILITY
• LOW STANDBY AND OPERATING POWER ICCSB l50/-lA
ICCOP lOrnA/MHz • RELIABLE POL YSILICON FUSE TECHNOLOGY

• INDUSTRIAL AND MILITARY TEMPERATURE RANGES • LOGIC PATHS TESTED TO INSURE FUNCTIONALITY

• RANDOM LOGIC REPLACEMENT

• CODE CONVERTORS

• ADDRESS DECODING

• FAULT DETECTORS

• BOOLEAN FUNCTION GENERATORS

• DIGITAL MULTIPLEXERS

• PARITY GENERATORS

• PATTERN RECOGNITION

• ROM PATCHING

The HPL-16LC8 is a programmable CMOS logic device which is Programmable Logic (HPLl, this device contains unique test
designed to provide a high performance, low power alternative circuitry developed by Harris which allows full AC, DC and
to the industry standard bipolar 16L8 programmable logic functional testing before programming.
device.
On-chip automatic power-down circuitry places internal cir-
The Harris polysilicon fuse link technology provides a perma- cuitry into an ultra-low ICCSB power mode after output data
nent fuse with stable storage characteristics over the full indus- becomes val id.
trial/military temperature and voltage ranges. Like all Harris

HPL is a trademark of Harris Corporation

PAL is a trademark of MMI
CAUTION: Electronic devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
1
o 1 2 3 4 5 6 7 891011 12131415 1617181920212223 2425262728293031

0
1

§~
2
3 19
4 -
5
6 r-
7 r-
2 ••
~
........•,
8
9

~EJi
10
11
12
13
14
---,
........•
3 ••. 15
.J>
16
17 ~
18 -
19
20
---. ~
-
21
22 '--
4 ••. 23 '--
.2 <;.
A~

24
25
26
27

5 ••.
•.. :>
28
29
30
31
§~ <.
....•
32
33
34
35
36
37
38
39
6 •.
.> ~
-

<;
A

,
40
41
42
43

E~
44
45 ~ V
46 }--
47
7 •. ....••
<;.
,
48
49 }--
50 r--
51
52
53
54
r--<

~
D- 13

55
8 •• A
.:>
~
56
57 f--
<
-
58 f...-
59 >---'
60
61
f...-
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62
9 ••. 63 ;---,
:> 11
< ,
m HARRIS

• 20 PIN SLIMLINE DIP

• SECURITY FUSE FOR PATTERN PROTECTION

• SCALED SAJI IV CMOS PROCESS
• TTL/CMOS COMPATIBLE INPUTS/OUTPUTS FOR MIXED
• FAST ACCESS (INPUT TO OUTPUT) SYSTEM COMPATIBILITY

• LOW STANDBY AND OPERATING POWER ICCSB l50/lA • RELIABLE POL YSILICON FUSE TECHNOLOGY
ICCOP lOrnA/MHz
• LOGIC PATHS TESTED TO INSURE FUNCTIONALITY
• INDUSTRIAL AND MILITARY TEMPERATURE RANGES

Pinout
Applications
1eRCS
• RANDOM LOGIC REPLACEMENT ~,eRce
r'8RC4
• CODE CONVERTORS vec vec
10 F7 Bt B3
• ADDRESS DECODING

I.
11 F5 B'
• CUSTOM SHIFT REGISTERS F5 F4 F3

13
• BOOLEAN FUNCTION GENERATORS F4 F3 F.

F' F1
• DIGITAL MULTIPLEXERS
•• F• F1 FO

• PARITY GENERATORS 18 F1 FO Bl

11 FO BO BO
• PATTERN RECOGNITION
aND l! l! l!
• STATE MACHINE DESIGN

The HPL-16RC4, 16RC6 and 16RCS are programmable CMOS Programmable Logic (HPL), these devices contain unique test
logic devices which are designed to provide a high performance, circuitry developed by Harris which allows full AC, DC and
low power alternative to the industry standard bipolar 16R4, functional testing before programming.
16R6 and 16RS programmable logic devices.
On-chip automatic power-down circuitry places internal cir-
The Harris polysilicon fuse link technology provides a perma- cuitry into an ultra-low ICCSB power mode after output data
nent fuse with stable storage characteristics over the full in- becomesvalid.
dustrial/military temperature and voltage ranges. Like all Harris

HPL is a trademark of Harris Corporation

PAL is a tradamark of MMI
CAUTION: Elactronic davicas ara sansitiv8 to electrostatic discharge. Propar I.e. handling proceduras should be followad.
 -
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CMOS 80C86 Family
Harris/Intel Cross-Reference 3-3

3-4
80C86 16 Bit Microprocessor 3-4
82C52 Full Duplex UART 3-27
82C54 Programmable Interval Timer 3-28
82C55A Programmable Peripheral Interface 3-43
82C59A Priority Interrupt Controller 3-62
HD-6406 Programmable Asynchronous Communications 3-76
Interface
82C82 Octal Latch 3-77
82C84A Clock Generator/Driver 3-82
82C88 Bus Controller 3-89

80C88 8 Bit Microprocessor 3-96

82C37A High Performance Programmable DMA 3-97
82C83 Octal Latching Inverting Bus Driver 3-98
82C84B Clock Generator/Driver 3-99
82C86 Octal Bus Transceiver 3-100
82C87 Octal Bus Transceiver 3-101
82C89 Bus Arbiter 3-102
 HARRIS CMOS 80C86 Family
Cross- Reference
INTEL DESCRIPTION HARRIS EQUIVALENT

80C86 CMOS 16 Bit Microprocessor

D8086 Commercial temp, ceramic or plastic pkg CD80C86or CP80C86

ID8086 Industrial temp, ceramic or plastic pkg I D80C86 or I P80C86
MD8086/B Military temp range, ceramic pkg
with DASH 8 processing MD80C86/B
without DASH 8 processing MD80C86

82C54 CMOS Programmable Timer

P8254 Commercial temp, plastic pkg CP82C54

D8254 Commercial temp, ceramic pkg CD82C54
MD8254/B Military temp, ceramic pkg
with DASH 8 processing MD82C54/B
without DASH 8 processing MD82C54

82C55A CMOS Programmable Peripheral Interface (PPI)

P8255A Commercial temp, plastic pkg, 2M Hz CP82C55A

D8255A Commercial temp, ceramic pkg, 2M Hz CD82C55A
P8255A-5 Commercial temp, plastic pkg, 3MHz CP82C55A
D8255A-5 Commercial temp, ceramic pkg, 3MHz CD82C55A
ID8255A Industrial temp, ceramic pkg, 2MHz I P82C55A or I D82C55A
MD8255A/B Military temp range, ceramic pkg
with DASH 8 processing MD82C55A/B
without DASH 8 processing MD82C55A

82C59A CMOS Interrupt Controller

D8259A Commercial temp range, ceramic pkg, 5MHz CD82C59A

P8259A Commercial temp range, plastic pkg, 5MHz CP82C59A
D8259A-2 Commercial temp range, ceramic pkg, 8MHz CD82C59A
P8259A-2 Commercial temp range, plastic pkg, 8MHz CP82C59A
D8259A-8 Commercial temp range, ceramic pkg, 2M Hz CD82C59A
P8259A-8 Commercial temp range, plastic pkg, 2M Hz CP82C59A
ID8259A I ndustrial temp range, ceramic or plastic pkg IP82C59A or I D82C59A
MD8259A Military temp, ceramic pkg
with DASH 8 processing MD82C59A/B
without DASH 8 processing MD82C59A

82C82 CMOS Octal Non-inverting Latching Bus Driver

D8282 Commercial temp range, ceramic pkg CD82C82

P8282 Commercial temp range, plastic pkg CP82C82
ID8282 I ndustrial temp range, ceramic pkg IP82C82 or ID82C82
MD8282/B Military temp range, ceramic pkg
with DASH 8 processing MD82C82/B
without DASH 8 processing MD82C82

82C84A CMOS Clock Generator Driver

P8284A Commercial temp, plastic pkg CP82C84A

D8284A Commercial temp, ceramic pkg CD82C84A
ID8284A Industrial temp, ceramic pkg I P82C84A or I D82C84A
MD8284A/B Military temp, ceramic pkg
with DASH 8 processing MD82C84A/B
without DASH 8 processing MD82C84A

82C8S CMOS Bus Controller

D8288 Commercial temp, ceramic or plastic pkg DP82C88 or CD82C88

ID8288 Industrial temp, ceramic pkg I P82C88 or I D82C88
MD8288/B Military temp, ceramic pkg
with DASH 8 processing MD82C88/B
without DASH 8 processing MD82C88
m HARRIS
CMOS
SOCS6
16 BIT MICROPROCESSOR

• COMPATIBLE WITH NMOS 8086

• COMPLETELY STATIC DESIGN
~ OPERATION FROM DC TO 5MHz GND VCC
• LOW POWER OPERATION
AD14 AD15
~ ICCSB = 500liA MAXIMUM
• AD13 A16/S3
~ ICCOP = lamA/MHz TYPICAL
• 1 MBYTE OF DIRECT MEMORY ADDRESSING CAPABILITY AD12 AI7/S4
• 24 OPERAND ADDRESSING MODES AD1! A1S/S5
• BIT, BYTE, WORD, AND BLOCK MOVE OPERATIONS AD10 A19/S6
.8 and 16 BIT SIGNED/UNSIGNED ARITHMETIC
AD9 SHE/57
~ BINARY or DECIMAL
~ MUL TIPL Y and DIVIDE ADS MNIMX
• BUS-HOLD CIRCUITRY ELIMINATES PULL-UP RESISTORS AD7 AD
• SCALED SAJI IV CMOS PROCESS AD6 AD/GTO (HOLD)
• SINGLE 5V POWER SUPPLY AD5 AD/GTI (HLDA)
• COMMERCIAL,INDUSTRIAL and MILITARY TEMPERATURE RANGES LOCK (\VAl
AD4
AD3 52 (M/iO)
Description AD2 51 IDT/R)

The Harris BOCB6high performance 16 bit CMOS CPU is manufactured using a ADI so 11m'll
ADO 050 IALE)
self-aligned silicon gate CMOS process (Scaled SAJI IVI.Two modes of oper-
NMI 051 IINTA)
ation, MINimum for small systems and MAXimum for larger applications such as
INTR TEST
multi-processing, allow user configuration to achieve the highest performance
CLK READY
level. Full TTL compatibility and industry standard operation allow use of exist-
GND RESET
ing NMOS BOB6hardware and software designs.

INSTRUCTION
iHllS7 STREAM BYTE
AlIlSe QUEUE
Alel13
,6,Clll-ADO
FLA13S
"
rm,IRl,Wft BUS

. DT/I(, 15TFl, ALI.M/io

INTERFACE
UNIT
SS

os
IP

A·BUS

LOCi( AH AL
BH BL
CH CL
, !2,r;, So
EXECUTION OH OL
UNIT SP
BP
ONO
SI
'cc
01 FLAGS
The following pin function de'!;criptions are for 80C86 interface connection to the 80C86 (without regard to
systems in either minimum or maximum mode. The "Local additional bus buffers).
Bus" in these descriptions is the direct multiplexed bus

PIN
SYMBOL NUMBER TYPE NAME AND FUNCTION

AD15-ADO 2-1S.39 110 ADDRESS DATA BUS: These lines constitute the time multiplexed memory/IO address (T1) and data
(T2. T3, TW, T4) bus. AO is analogous to BHE for the lower byte of the data bus, pins 07-00. It is
LOW during T 1 when a byte is to be transferred on the lower portion of the bus in memory or 110 opera-
tions. Eight-bit oriented devices tied to the lower half would normally use AO to condition chip select
functions (See SHE). These lines are active HIGH and float to 3-5tate OFF during interrupt acknowledge
and local bus "hold acknowledge."

A19/Ss 35-38 a ADDRESS/STATUS: During T 1, these are the four most significant address lines for memory operations.
A18/S5 During I/O operations these lines are LOW. During memory and 1/0 operations, status information is
An/S4 available on these lines during T2, T3, TW, and T4. The status of the interrupt enable FLAG bit 155) is
A1S/S3 updated at the beginning of each CLK cycle. An/S4 and A1S/S3 are encoded as shown in (Table 1).

This information indicates which relocation register is presently being used for data accessing.
These lines float to 3-state OFF during local bus "hold acknowledge."

BHE/S7 34 a BUS HIGH ENABLE/STATUS: During T1 the bus high enable signal (BHE) should be used to enable
data onto the most significant half of the data bus, pins 015-08. Eight bit oriented devices tied to the
upper half of the bus would normally use SHE to condition chip select functions. SHE is LOW during T1
for read, write, and interrupt acknowledge cycles when a byte is to be transferred on the high portion of
the bus. The 57 status information is available during T2' T3, and T4. The signal is active LOW, and
floats to 3-state OFF in "hold". It is LOW during THor the first interrupt acknowledge cycle.(See Table 2)
-
RD 32 a READ: Read st!:.9..beindicates that the processor is performing a memory of I/O read cycle, dependi!!i-0n
the state of the S2 pin. This signal is used to read devices which reside on the 80C86 local bus. RD is
active LOW during T2. T3. and TW of any read cycle, and is guaranteed to remain HIGH in T2 until the
80C8S local bus has floated.

This signal floats to 3-state OFF in "hold acknowledge,"

READY 22 I READY: is the acknowledgement from the addressed memory or I/O device that will complete the
data transfer. The ROY signal from memory/IO is synchronized by the 82C84A Clock Generator to
form READY. This signal is active HIGH. The 80C86 READY input is not synchronized. Correct
operation is not guaranteed if the setup and hold times are not met.

INTR 18 I INTERRUPT REQUEST: a level triggered input which is sampled during the last clock cycle of each
instruction to determine if the processor should enter into an interrupt acknowledge operation. A sub-
routine is vectored to via an interrupt vector lookup table located in system memory. It can be internally
masked by software resetting the interrupt enable bit. INTA is internally synchronized. This signal is
active HIGH.

TEST 23 I TEST: input is examined by the "Wait" instruction. If the TEST input is LOW execution continues,
otherwise the processor waits in an "Idle" state. This input is synchronized internally during each clock
cycle on the leading edge of CLK.

NMI 17 I NON-MASKABLE INTERRUPT: an edge triggered input which causes a tYpe 2 interrupt. A subroutine
is vectored to via an interrupt vector lookup table located in system memory. NMI is not maskable inter-
nally by software. A transition from a LOW to HIGH initiates the interrupt at the end of the current
instruction. This input is internally synchronized.

RESET 21 I RESET: causes the processor to immediately terminate its present activitY. The signal must be active
HIGH for at least four clock cycles. It restarts execution, as described in the Instruction Set description.
when RESET returns LOW. RESET is internally synchronized.

CLK 19 I CLOCK: provides the basic timing for the processor and bus controller. It is asymmetric with a 33%
duty cycle to provide OPtimized internal timing.

VCC 40 VCC: + 5V power supply pin.

GND 1,20 GND: Ground Note: both must be connected.

MN/MX 33 I MINIMUM/MAXIMUM: Indicates what mode the processor is to operate in. The two modes are discus-
sed in the following sections.
The following pin function descriptions are for the 80C861 mode are described; all other pin functions are as described
82C88 system in maximum mode (i.e., MN/MX = GND). above.
Only the pin functions which are unique to maximum

STATUS: active during T4, T 1, and T2 and I. returned to the passive state (1, 1, 1) during T3 or during
TW when READY is HIGH. This status Is usad by the B2CBB Bus Controllar to generate all mamory and
I/O access control signals. Any change by 52, 51, or Sa during T 4 Is used to Indicate the beginning of a
bus cycle, and the return to the passive stata In T3 or TW Is used to Indicate the end of a bus cycl •.
These signals float to 3-state OFF in "hold acknowladge. These status lines are encoded as shown
in Table 3.
REQUEST/GRANT: pins are used by other local bus masters to force the processor to release the local
bus at the end...2! t.!l!..Pro.£!!sor·s current bus cycle. Each pin is bidirectional with RQ/GTO having higher
prioritY than RQ/GT1. RQ/GT has an internal pull-up bus hold device so it may be left unconnected.
The request/grant sequence is as follows (see Waveform Section):

1. A pulse of 1 ClK wide from another local bus master Indicate. a local bus reque.t ("hold") to the
BOCB6 (pu Ise 1),

2. During a T 4 or TI clock cycle, a pulse 1 ClK wide from the BOCB6to tha requesting master (pulse 21,
Indlcatas that the BOCB6 has allowed the local bus to float and that It will enter the "hold acknow-
ledge" state at tha next ClK. The CPU's bus Interface unit Is dlsconnacted logically from the local bus
during "hold acknowledge."

3. A pulse 1 ClK wide from the requesting master indicates to tha BOCB6 (pulse 3) that tha "hold"
raquest is about to end and that the BOCB6 can reclaim the local bus at tha next ClK.
Each master-master exchange of the local bus is a sequence of 3 pulses. There must be one dead elK
cycle after each bus exchange. Pulses are active LOW.

If the request is made while the CPU Is performing a memory cycle, It will release the local bus during
T 4 of the cycle when all the follOWing conditions are met:
1. Request occurs on or before T2.
2. Current cycle is not the low byte of a word (on an odd addre •• ),
3. Current cycle is not the first acknowledge of an interrupt acknowledge sequence.
4. A locked instruction is not currently excutlng.

If the local bus is idle when the request Is made the two possible events will follow:
1. local bus will be released during the next clock.
2. A memory cycle will start within three clocks. Now the four rules for a currently active memory
cycle apply with condition number' already satisfied.

LOCK: output indicates that other system bus masters are not to gain control of the system bus while
I:'1iC'K is active lOW. The L'5C'K signal is activated by the "lOCK" prafix instruction and remains active
until the completion of the next instruction. This signal is active LOW. and floats to 3-state OFF in
"hold acknowledge." In MAX mode, LOCK Is automatically generated during T2 of the first INTA cycle
and removed during T2 of the second INTA cycle.

QUEUE STATUS: The queue status is valid during

the ClK cycle after which the queue operation
os, OSo

is performed.
o (lOW) 0 No Operation

os,. and asO

provide status to allow external
o 1 First Byte of Op Code from Queue
1 (HIGH) 0 EmptY the Queue
tracking of the internal 80C86 instruction queue.
1 1 Subsequent Byte from Oueue
Note that QS,. QSO never become high impedance,

52 s, 50 CHARACTERISTICS

",,&'53 CHARACTERISTICS
~ "'0 CHARACTERISTICS
Al11S4 o (LOW) 0 0 Interrupt
0 0 Whole word
o ILOW!
0 ,
0 Alternate Data
Stack
0 1 Upper byte froml 0
,
0 1
Acknowledge
Read 1/0 Pan

,
1 (HIGH)
,
0 Code or None
Data
, 0
to odd address
Lower byte from I
0
0 1
0
1
Write 1/0 Port
H.lt
S6 is a (LOW) , 1
to even address
None
llHIGHI
, 0
0
0
1
Code Access
Reed Memory
1
1 ,
1
,
0 Write Memory
Passive
The following pin function descriptions are for the SOCSS functions which are unique to minimum mode are de-
in minimum mode (i.e. MN/MX = VCC). Only the pin scribed; all other pin functions are as described above.

PIN
SYMBOL NUMBER TYPE NAME AND FUNCTION

M/iO 28 0 STATUS LINE: logically aqulval.nt to S2 In the maximum mod•. It I. u•• d to dl.tlngul.h • mamory
.cc ••• from an 1/0 ace.... M/iO b.com •• valid In the T4 pr.c.dlng • bu. cycl. and r.malns valid until
the fln.1 T4 of the cycl. (M HIGH. 10 c LOW). M/io floats to 3-stat. OFF In local bu. "hold acknow-
K

ledg•••.

WR 29 0 WRITE: Indlcat•• that the proc••• or Is p.rformlng. write m.mory or write I/O cycl., d.p.ndlng on the
stat. of the M/iO signal. WR Is actIv. for T2, T3, and TW of any write cycla. It Is .ctlv. LOW, and float.
to 3-stat. OFF In local bus "hold acknowledg•••.

INTA 24 0 INTER~UPT ACKNOWLEDGE: Is used as 8 reed strobe for interrupt acknowledge cycles. It is active
LOW during T2, T3, .nd TW of .ach Intarrupt acknowl.dge cycle. Note thet INTA i. nev.r flo.ted.

ALE 25 0 ADDRESS LATCH ENA8LE: provided by the proc••• or to latch the addrassInto the 82C82 addr.ss
latch. It I. a HIGH pulseactive during T1 of any bus cycl•• Not. that ALE Is n.v.r flo.t.d.

DT/R 27 0 DATA TRANSMIT/RECEIVE: n.eded In minimum sy.tem that d•• lr•• to usea data bu. tr.nsc.lver. It
Is usedto control the direction of data flow through the tran.celv.r. Logically, DT/A Is .qulvelent to 51
In maximum moda, and It. timing I. tha samea. for M/io (T c HIGH, R LOW). DT/A float. to 3-stata
K

OFF In local bus "hold acknowladge:'

DEN 26 0 DATA ENABLE: provided as an output enable for a bus transceiver in B minimum system which uses the
transceiver.DEN Is actlv. LOW during •• ch memory and 110 accessand for INTA eyeI••• For. r.ad or
INTA cycl. It Is active from the middle of T2 until the mlddla of T4, whll. for a writ. cycl. It I. active
from the b.glnning of T2 until the middle of T4. i5!N float. to 3-.tat. OFF In local bu. "hold acknow-
ledg.:'

HOLD 31, I HOLD: indicates that another master is requesting a local bus "hold". To b. a acknowl.dged, HOLD
HLDA 30 0 mu.t b. activ. HIGH. The processorrecalvingthe "hold" willlssu •• "hold acknowl.dg." (HLDA) In the
middla of a T4 or TI clock cycla. Simuitan.ou. with the Issuanceof HLDA, the processorwill float tha
local bu. and control line•. Aft.r HOLD i. detected a. being LOW, tha procassarwill LOWer HLDA, and
when the processor needs to run another cycle, it will again drive the local bus and control lines.

Th•• am. rule. a. for RQ/GT apply regardingwhen the local bus will be r.i.a.ad. HOLD I. not an asynch-
ronous Input. External synchronization should be provided if the systemcannot otherwl.e guaranteethe
setup time.

circuitry to provide critical information for bringing up

you r system.
All SOCSScircuitry is of static design. Internal registers,
counters and latches are static and require no refresh as Static design also allows very Ipw frequency operation
with dynamic circuit design. This eliminates the minimum (down to DC). In a power critical situation, this can provide
operating frequency restriction placed on other micropro- extremely low power operation since SOCSSpower dis-
cessors. The CMOS SOCSScan operate from DC to the sipation is directly related to operating frequency. As the
appropriate upper frequency limit. The processor clock system frequency is reduced, so is the operating power until,
may be stopped in either state (high/low) and held there ultimately, at a DC input frequency, the SOCBSpower
indefinitely. This type of operation is especially useful for requirement is the standby current. (SOOIlA maximum)
system debug or power critical applications.

The SOCSScan be single stepped using only the CPU clock.

This state can be maintained as long as is necessaryduring The internal functions of the BOCBSprocessor are parti-
debug. Single step clock operation allows simple interface tioned logically into two processing units. The first is the
Bus Interface Unit (BIU) and the second is the Execution
Unit (EU) as shown in the CPU functional diagram. ~FFFFFH

These units can interact directly but for the most part per-
form as separate asynchonous operational processors. The
bus interface unit provides the functions related to instruc-
..I..O} CODE SEGMENT

XXXXOH
tion fetching and queuing, operand fetch and store, and
address relocation. This unit also provides the basic bus
control. The overlap of instruction pre-fetching provided } STACK SEGMENT

by this unit serves to increase processor performance

through improved bus bandwidth utilization. Up to 6 bytes
of the instruction stream can be queued while waiting for
SEGMENT
decoding and execution. REGISTER FILE

CS
SS
The instruction stream queuing mechanism allows the BIU os
to keep the memory utilized very efficiently. Whenever ES

there is space for at least 2 bytes in the queue, the BIU will
attempt a word fetch memory cycle. Th is greatly reduces }EXTRA DATA SEGMENT
"dead time" on the memory bus. The queue acts as a
First-In-First-Out (FIFO) buffer, from which the EU
extracts instruction bytes as required. If the queue is
empty (following a branch instruction, for example), the
first byte into the queue immediately becomes available to
the EU.

The execution unit receives pre-fetched instructions from All memory references are made relative to base addresses
the BIU queue and provides un-relocated operand addresses contained in high speed segment registers. The segment
to the BIU. Memory operands are passed through the BIU types were chosen based on the addressing needs of pro-
for processing by the EU, which passes results to the BIU grams. The segment register to be selected is automatically
for storage. chosen according to specific rules of operation. All inform-
ation in one segment type share the same logical attributes
(e.g. code or data). By structuring memory into relocatable
areas of similar characteristics and by automatically select-
The processor provides a 20-bit address to memory, which ing segment registers, programs are shorter, faster, and more
locates the byte being referenced. The memory is organized structured. (See Table 4).
as a linear array of up to 1 million bytes, addressed as
OOOOO(H)to FFFFF(H). The memory is logically divided Word (16-bit) operands can be located on even or odd ad-
into code, data, extra data, and stack segments of up to dress boundaries and are thus not constrained to even
64K bytes each, with each segment falling on 16-byte boundaries as is the case in many 16-bit computers. For
boundaries. (See Figure 1). address and data operands, the least significant byte of the

DEFAULT ALTERNATE
TYPE OF MEMORY REFERENCE SEGMENT SEGMENT OFFSET
BASE BASE

Instruction Fetch CS NONE IP

Stack Operation SS NONE SP
Variable (except following) DS CS, ES,SS Effective Address
String Source DS CS, ES,SS SI
String Destination ES NONE DI
BP Used As Base Register SS CS,DS, ES Effective Address
word is stored in the lower valued address location and the through FFFFFH are reserved for operations including a
most significant byte in the next higher address location. jump to the initial program loading routine. Following
The BIU automatically performs the proper number of RESET, the CPU will always begin execution at location
memory accesses, one if the word operand is on an even FFFFOH where the jump must be. locations OOOOOH
byte boundary and two is it is on an odd byte boundary. through 003FFH are reserved for interrupt operations.
Except for the performance penalty, th is double access is Each of the 256 possible interrupt types has its service
transparent to the software. The performance penalty does routine pointed to be a 4-byte pointer element consisting
not occur for instruction fetches; only word operands. of a 16-bit segment address and a 16-bit offset address.
The pointer elements are assumed to have been stored at
Physically, the memory is organizlB as a high bank (D15- the respective places in reserved memory prior to occur-
DB) and a low bank '(D7-DO) of 512K B-bit bytes address- rence of interru pts.
ed in parallel by the processor's address lines.

Byte data with even addresses is transferred on the D7-DO

bus lines while odd addressed byte data (AO HIGH) is trans- The requirements for supporting minumum and maximum
ferred on the D15-DB bus lines. The processor provides BOCB6 systems are sufficiently different that they cannot
two enable signals. BHE and AO to selectively allow read- be met efficiently using 40 uniquely defined pins. Con-
ing from or writing into either an odd byte location, even sequently, the BOCB6 is equipped with a strap pin (MN/MX)
byte location, or both. The instruction stream is fetched which defines the system configuration. The definition of
from memory as words and is addressed internally by the a certain subset of the pins changes dependent on the con-
processor at the byte level as necessary. dition of the strap pin. When the MN/MX pin is strapped
to GND, the BOCB6 treats pins 24 through 31 in maximum
In referencing word data, the BIU requires one or two mode. An B2CBB bus controller interprets status inform-
memory cycles depending on whether the starting byte ation coded into So, 51,52 to generate bus timing and con-
of the word is on an even or odd address, respectively. trol signals compatible with the MUlTIBUS e architec-
Consequently, in referencing word operands performance ture. When the MN/MX pin is strapped to VCC, the BOCB6
can be optimized by locating data on even address bound- generates bus control signals itself on pins 24 through 31.
aries. This is an especially useful technique for using the
stack, since odd address references to the stack may adver-
sely affect the context switching time for interrupt pro-
cessing or task multiplexing. The BOCB6 has a combined address and data bus commonly
referred to as a time multiplexed bus. This technique pro-
Certain locations in memory are reserved for specific CPU vides the most efficient use of pins on the processor while
operations (See Figure 2). locations from address FFFFOH permitting the use of a standard 40-lead package. This
"local bus" can be buffered directly and used throughout
the system with address latching provided on memory and
I/O modules. In addition, the bus can also be demultiplex-
ed at the processor with a single set of B2CB2 address
latches if a standard non-multiplexed bus is desired for the
1II1.IT lOOTlTtllA' system.
"'OOlllA" JUM'

• Each processor bus cycle consists of at least four ClK

cycles. These are referred to as T 1, T2, T3 and T 4 (see
Figure 3). The address is emitted from the processor during
3
IHTEllIRUPT POINTE" T1 and data transfer occurs on the bus during T3 and T 4.
FOR TYPE 255
3 T2 is used primarily for changing the direction of the bus
during read operations. In the event that a "NOT READY"
indication is given by the addressed device, "Wait" states
7
tNTEllIRUPT POINTER (TW) are inserted between T3 and T 4. Each inserted
FOA TYPE t

INTERllIUPT POINTER
•
3
"Wait" state is of the same duration as a ClK cycle. Periods
FOR TYPE 0 between BOCB6 bus cycles are referred to as "idle" states
0
(TI) or inactive ClK cycles. The processor uses these
cycles for internal housekeeping and processing.

During T 1 of any bus cycle, the ALE (Address latch

Enable) signal is emitted (by either the processor or the
14 + "wAlT)-

~
Tcv -------t ..,
~IT ~ Tl ~
14 + Nw"'ITI - TCY

~ ~

\---

-----EX D_A_T_A_O_U_T_'D_"_-_DO_' )---CC

\_-_/
82C88 bus controller, depending on the MN/MX strap). At
the trailing edge of this pulse, a valid address and certain
status information for the cycle may be latched. In the 80C86, I/O operations can address up to a max-
imum of 64K I/O byte registers on 32K I/O word registers.
Status bits SO, S1, and S2 are used, in maximum mode, by The I/O address appears in the same format as the memory
the bus controller to identify the type of bus transaction address on bus lines A 15-AO. The address lines A 19-A 16
according to the following table: are zero in I/O operations. The variable I/O instructions
which use register OX as a pointer have full address capa-
bility while the direct I/O instructions directly address one
5-; S; So CHARACTERISTICS
or two of the 256 I/O byte locations in page 0 of the I/O
a (lOW) a a Interrupt Acknowledge
address space.
a a 1 Read 110
a 1 a Write 1/0
a 1 1 Halt I/O ports are addressed in the same manner as memory
1 (HIGH) a a Instruction Fetch locations. Even addressed bytes are transferred on the
1 a 1 Read Data from Memory 07-00 bus lines and odd addressed bytes on 015-08.
1 1 a Write Data to Memory Care must be taken to ensure that each register within an
1 1 1 Passive (no bus cycle)
8-bit peripheral located on the lower portion of the bus
be addressed as even.

Status bits S3 through S7 are time multiplexed with high

order address bits and the SHE signal, and are therefore
valid during T2 through T 4. S3 and S4 indicate which seg-
ment register (see Instruction Set description) was used for
Processor initialization or start up is accomplished with
this bus cycle in forming the address, according to the fol-
activation (HIGH) of the RESET pin. The 80C86 RESET is
lowing table:
required to be HIGH for greater than 4 ClK cycles. The
80C86 will terminate operations on the high-going edge of
54 53 CHARACTERISTICS RESET and will remain dormant as long as RESET is
a (lOW) a Alternate Data (extra segment) HIGH. The low-going transition of RESET triggers an
a 1 Stack internal reset sequence. After this interval, the 80C86
1 (HIGH) a Code or None
operates normally beginning with the instruction in abso-
1 } Data
lute location FFFFOH. The RESET input is internally
synchronized to the processor clock. At initialization, the
HIGH-to-lOW transition of RESET must occur no sooner
S5 is a reflection of the PSW interrupt enable bit. S6 is than 50 /lS (or 4 ClK cycles, whichever is greater) after
undefined and' S7 is a spare status bit. power-up, to allow complete initialization of the 80C86.

I T, T1 TJ T4 I T1 I T1 I

ALE~~_(J\~_
J I
( I
/
r l
~
1\
ADo·AD1" -.-J--------------~
\FLOAI
I
Ii
I

\ lYPE. \lECTOR
>-
NM I may not be asserted prior to the second CLK cycle multiply, divide, and variable shift instructions. There is
following the end of RESET. no specification on the occurrence of the low-going edge;
it may occur before, during, or after the servicing of NMI.
Another positive edge triggers another response if it occurs
after the start of the NMI procedure. The signal must be
To avoid high current conditions caused by floating inputs free of logical spikes in general and be free of bounces on
to CMOS devices, "bus-hold" circuitry has been used on the low-going edge to avoid triggering extraneous responses.
the SOCS6 pins 2-16, 26-32, and 34-39. These circuits will
maintain the last valid logic state if no driving source is pre-
sent (i.e. an unconnected pin or a driving source which goes
to a high impedance state). To overdrive the "bus hold" The SOCS6 provides a single interrupt request input (INTR)
circuits, an external driver must be capable of supplying which can be masked internally by software with the reset-
approximately 400 IJ.A minimum sink or source current at ting of the interrupt enable FLAG status bit. The inter-
valid input voltage levels. Since this "bus hold" circuitry is rupt request signal is level triggered. It is internally syn-
active and not a "resistive" type element, the associated chronized during each clock cycle on the high-going edge
power supply current is negligible and power dissipation is of CLK. To be responded to, INTR must be present
significantly reduced when compared to the use of passive (HIGH) during the clock period preceding the end of the
pull-up resistors. current instruction or the end of a whole move for a block-
type instruction. During the interrupt response sequence
further interrupts are disabled. The enable bit is reset as
part of the response to any interrupt (INTR, NMI, soft-
Interrupt operations fall into two classes; software or ware interrupt or single-step), although the FLAGS register
hardware initiated. The software initiated interrupts and which is automatically pushed onto the stack reflects the
software aspects of hardware interrupts are specified in the state of the processor prior to the interrupt. Until the old
Instruction Set description in the SOCS6 data sheet. Hard- FLAGS register is restored the enable bit will be zero unless
ware interrupts can be classified as non-maskable or mask- specifically set by an instruction.
able.
During the response sequence (Figure 4) the processor exe-
Interrupts result in a transfer of control to a new program cutes two successive (back-to-back) interrupt acknowledge
location. A 256-element table containing address pointers cycles. The SOCS6 emits the LOCK signal from T2 of the
to the interrupt service program locations resides in abso- first bus cycle until T2 of the second. A local bus "hold"
lute locations 0 through 3FFH, which are reserved for this request will not be honored until the end of the second bus
purpose. Each element in the table is 4 bytes in size and cycle. In the second bus cycle, a byte is supplied to the
corresponds to an interrupt "type". An interrupting device SOCS6 by the S2C59A Interrupt Controller, which identi-
supplies an S-bittype number during the interrupt acknow- fies the source (type) of the interrupt. This byte is multi-
ledge sequence, which is used to "vector" through the ap- plied by four and used as a pointer into the interrupt vector
propriate element to the new interrupt service program look-up table. An INTR signal left HIGH will be continually
location. All flags and both the Code Segment and Instruc- responded to within the limitations of the enable bit and
tion Pointer registers and saved as part of the INTA se- sample period. The INTERRUPT RETURN instruction
quence. These are restored upon execution of an Interrupt includes a FLAGS pop which returns the status of the orig-
Return (IRET) Instruction. inal interrupt enable bit when it restores the FLAGS.

The processor provides a single non-maskable interrupt pin When a software "HALT" instruction is executed the pro-
(NMI) which has higher priority than the maskable inter- cessor indicates that it is entering the "HAL T" stat~ in one
rupt request pin (INTR). A typical use would be to acti- of two ways depending upon which mode is strapped. In
vate a power failure routine. The NMI is edge-triggered on minimum mode, the processor issues one ALE with no
a LOW-to-H IGH transition. qualifying bus control signals. In maximum mode, the pro-
cessor issues appropriate HALT status on 52, 51, So and
NMI is required to have a duration in the HIGH state of the S2CSS bus controller issues one ALE. The SOCS6 will
greater than two CLK cycles, but is not required to be not leave the "HALT" state when a local bus "hold" is
synchronized to the clock. Any positive transition of NMI entered while in "HALT". In this case, the processor re-
is latched on-chip and will be serviced at the end of the issues the HALT indicator. An NMI or interrupt request
current instruction or between whole moves of a block- (when interrupts enabled) at the end of the bus hold period
type instruction. Worst case response to NMI would be for or RESET will force the SOCS6 out of the "HALT" state.
 AH Al ACCUMULATOR

BH Bl BASE

CH Cl COUNT
The LOCK status information is provided by the processor DH Dl DATA
when directly consecutive bus cycles are required during
the execution of an instruction. This gives the processor
the capability of performing read/modify/write operations
S: STACK POINTER

BASE POINTER

on memory (via the Exchange Register With Memory instr- SI SOURCE INDEX

uction, for example) without the possibility of another

system bus master receiving intervening memory cycles.
~ 01 DESTINATION INDEX

This is useful in multiprocessor system configurations to

accomplish "test and set lock" operations. The LOCK I FLAGS"
IP
FLAGSl,
I
signal is activated (forced LOW) in the clock cycle follow-
CODE SEGMENT
ing the one in which the software "LOCK" prefix instruc-
DATA SEGMENT
tion is decoded by the EU. It is deactivated at the end of STACK SEGMENT
the last bus cycle of the instruction following the "LOCK" EXTRA SEGMENT
prefix instruction. While LOCK is active a request on a
RQ/GT pin will be recorded and then honored at the end
of the LOCK.

As an alternative to the interrupts and general I/O capabili-

ties, the 80C86 provides a single software testable input The read cycle begins in T 1 with the assertion of the Ad-
known as the TEST signal. At any time the program may dress Latch Enable (ALE) signal. The trailing (low-going)
execute a WAIT instruction. If at that time the TEST signal edge of this signal is used to latch the address information,
is inactive (HIGH). program execution becomes suspended which is valid on the local bus at this time, into the 82C82
while the processor waits for TEST to become active. It latch. The BHE and AO signals address the low, high, or
must remain active for at least five CLK cycles. The WAIT both bytes. From T 1 to T4 the Milo' signal indicates a
instruction is re-executed repeatedly until that time. This memory or I/O operation. At T2, the address is removed
activity does not consume bus cycles. The processor re- from the local bus and the bus goes to a high impedance
mains in idle state while waiting. All 80C86 drivers go to state. The read control signal is also asserted at T2. The
3-state OFF if bus "Hold" is entered. If interrupts are read (RD) signal causes the addressed device to enable its
enabled, they may occur while the processor is waiting. data bus drivers to the local bus. Some time later, valid
When this occurs the processor fetches the WAIT instruc- data will be available on the bus and the addressed device
tion on extra time, processes the interupt, and then re- will drive the READY line HIGH. When the processor
fetches and re-executes the WAIT instruction upon return- returns the read signal to a HIGH level, the addressed device
ing from the interrupt. will again 3-state its bus drivers. If a transceiver is required
to buffer the 80C86 local bus, signals DT/R and DEN are
provided by the 80C86.

Typical system configurations for the processor operating A write cycle also begins with the assertion of ALE and the
in minimum mode and in maximum mode are shown in emission of the address. The M/Io signal is again asserted
Figures 5a and 5b, respectively. In minimum mode, the to indicate a memory or I/O write operation. In T2, im-
MN/MX pin is strapped to VCC and the processor emits mediately following the address emission, the processor
bus control signals (e.g. RD, WR, etc.) directly. In max- emits the data to be written into the addressed location.
imum mode, the MN/MX pin is strapped to GND and This data remains valid until the middle of T4. During T2,
the processor emits coded status information which the T3 and TW, the processor asserts the write control signal.
82C88 bus controller used to generate MULT1BUS8comp- The write (WR) signal becomes active a the beginning of
atible bus control signals. Figure 3 shows the signal timing T2 as opposed to the read which is delayed somewhat into
relationships. T2 to provide time for the bus to float.
I r-
aND
---.,
I WAIT
I ITATE
---, I
I I
----.,
I OENE~ATO~ I I I I
L ..J I
I
I

I I
I I J:---""
I L_rr---..,;
L - -JOE I I
TRA~~g~~VER I
121 I I
I I rn
L
OPTIONAL
f
El i RDW~
FO~ INCREASED
OArA IUS DRIVE HM~6'8 HM-6618 CMOS
CMOS RAM CMOS PROM (2) I2CXX
PERIPHERALS

Vcc

aND ClK IlIltie

IIN/
iO to iiWTC
i; S; AIIWC N.C.
i2 i2 .2C•• ~
1r-
aND
aoc ••
DEN
DTI~
C~~~" RSWC
A'DWe N.C.
C'V
ALE INTi
I WAIT I
I ITATE
I OENE~ATO~
I
I
~ N.C.
---:-,
L ___ -l I
I
I

EL W E
HM~6'82 HM-681S
CMOS RAM CMOS PROM (21
The BH E and AO signals are used to select the proper
byte(s) of the memory/IO word to be read or written ac-
cording to the following table: For medium size systems the MN/MX pin is connected to
GND and the 82C88 Bus Controller is added to the system
as well as an 82C82 latch for latching the system address,
and a transceiver to allow for bus loading greater than the
IHl AO CHARACTERISTICS 80C86 is capable of handling. ALE, DEN, and DT/R are
0 0 Whole word generated by the 82C88 instead of the processor in this
0 1 Upper byte froml configuration, although their timing remains relatively the
to odd address same. The 80C86 status outputs (52, 51, and SO) provide
1 0 Lower byte froml type-of-cycle information and become 82C88 inputs.
to even address This bus cycle information specifies read (code, data, or
1 1 None I/O). write (data or I/O). interrupt acknowledge, or soft-
ware halt. The 82C88 thus issues control signals specifying
memory read or write, I/O read or write, interrupt
acknowledge, or halt. The 82C88 provides two types of
write strobes, normal and advanced, to be applied as re-
I/O ports are addressed in the same manner as memory quired. The normal write strobes have data valid at the
location. Even addressed bytes are transferred on the D7- leading edge of write. The advanced write strobes have
DO bus lines and odd addressed bytes on D15-D8. the same timing of write. The transceiver receives the usual
T and 6E inputs from the 82C88 DT/R and DEN signals.
The basic difference between the interrupt acknowledge
cycle and a read cycle is that the interrupt acknowledge sig- The pointer into the interrupt vector table, which is passed
nal (INTA) is asserted in place of the read (RD) signal and during the second I NT A cycle, can be derived from an
the address bus is floated. (See Figure 4). In the second 82C59A located on either the local bus or the system bus.
of two successive INTA cycles, a byte of information is If the master 82C59A Priority Interrupt Controller is pos-
read from bus lines D7-DO as supplied by the interrupt itioned on the local bus, a TTL gate is required to disable
system logic (i.e., 82C59A Priority Interrupt Controller). the transceiver when reading from the master 82C59A
This byte identifies the source (type) of the interrupt. during the interrupt acknowledge sequence and software
It is multiplied by four and used as a pointer into an inter- "poll".
rupt vector lookup table, as described earlier.

Supply Voltage +8.0 Volts Operating Temperature Range

Operating Voltage Range +4V to +7V Commercial OOC to +700C
Input Voltage Applied GND -2.0V to 6.5V Industrial -400C to +850C
Output Voltage Applied GND -O.5V to VCC +O.5V Military -550C to +1250C
Storage Temperature Range -650C to +1500C Maximum Power Dissipation 1 Watt

CAUTlON: Strsssesabove those listed in the "ABSOLUTE MAXIMUM RA TINGS" may causepermanent damage
to the device. This is a stress only rating and operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
 Specifications (continued)
D.C. ELECTRICAL CHARACTERISTICS
VCC = 5.0V±10%; TA = OOC to +700C (C80C86); TA = -400C to +850C (180C86); TA = -550C to +1250C (M80C86)

SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS

VIH Logical One 2.0 V C80C86, 180C86

Input Voltage 2.2 V M80C86

VIL Logical Zero 0.8 V

Input Voltage

VIHC CLK Logical One VCC -0.8V V

Input Voltage

VILC CLK Logical Zero 0.8 V

Input Voltage

VOH Output High Voltage 3.0 V 10H = -2.5mA

VCC -0.4 V 10H = -tOOIJA

VOL Output Low Voltage 0.4 V IOL=+2.5mA

ilL Input Leakage -1.0 1.0

I fJ.A OV<VIN<VCC
Current -

18HH I nput Leakage -40 -400 fJ.A VIN = 3.0V

Current-Bus Hold High (see Note 1)

18HL Input Leakage 40 400 fJ.A V1N = 0.8V

Current-Bus Hold Low (see Note 2)

10 Output Leakage -10.0 10.0 fJ.A OV<VO~VCC

Current -
ICCS8 Standby Power Supply 500 IJA VCC = 5.5V
Current VIN = VCC or GND
Outputs unloaded

ICCOP Operating Power 10 mA/MHz TA = 250C

Supply Current VCC = 5V. TYPICAL

CAPACITANCE
TA = 250C; VCC = GND = OV; VIN = +5V or GND

SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS

CIN" Input Capacitance 5 pI FREQ = 1MHz

Unmeasured pins
returned to GND

COUTo Output Capacitance 15 pI

CliO" I/O Capacitance 20 pI
A.C. CHARACTERISTICS
VCC = +5V±10%. GND = OV: TA = OOCto +70oC (CBOCB6)
T A = -400C to +B50C (IBOCB6)
TA = -550C to +1250C (MBOCB6)
MINIMUM COMPLEXITY SYSTEM

SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS

TCLCL CLK Cycle Period 200 ns

TCLCH CLK Low Time 118 ns
TCHCL CLK High Time 69 ns
TCH1CH2 CLK Rise Time 10 ns From 1.0V to 3.5V
TCL2CL1 CLK Fall Time 10 ns From 3.5V to 1.0V
TDVCL Data in Setup Time 30 ns
TCLDX Data in Hold Time 10 ns
TR1VCL ROY Setup Time into 35 ns
82C84A Isee Note 1,2)
TCLR1X ROY Hold Time into 0
82C84A Isee Note 1.2)
TRYHCH READY Setup Time 11B ns
into BOCB6 CL = 20 -100pF
TCHRYX READY Hold Time 30 ns
into BOCB6
TRYLCL READY Inactive to -B ns
CLK Isee Note 3)
THVCH HOLD Setup Time 35 ns
TINVCH INTR, NMI, TEST 30 ns
Setup Time
(See Note 2)
TILIH Input Rise Time 15 ns
From O.BV to 2.0V
(Except CLK)
TIHIL Input Fall Time 15 ns From 2.0V to 0.8V
(Except CLK)

TIMING RESPONSES

TCLAV Address Valid Delay 10 110 ns CL = 20 -100pF

TCLAX Address Hold Time 10 ns
TCLAZ Address Float Delay TCLAX BO ns
TLHLL ALE Width TCLCH-20 ns
TCLLH ALE Active Delay BO ns
TCHLL ALE Inactive Delay B5 ns
TLLAX Address Hold Time TCHCL-10 ns
to ALE Inactive
TCLDV Data Valid Delay 10 110 ns
TCHDX Data Hold Time 10 ns
TWHDX Data Hold Time TCLCH-30 ns
AfterWR
TCVCTV Control Active 10 110 ns
Delay 1
TCHCTV Control Active 10 110 ns
Delay 2
TCVCTX Control Inactive 10 110 ns
Delay
TAZRL Address Float to 0 ns
READ Active
TCLRL RD Active Delay 10 165 ns
TCLRH RD Inactive Delay 10 150 ns
TRHAV AD Inactive to Next TCLCL-45 ns
Address Active
TCLHAV HLDA Valid Delay 10 160 ns
TRLRH RD Width 2TCLCL·75 ns
TWLWH WR Width 2TCLCL-60 ns
TAVAL Address Valid to TCLCH-60 ns
ALE Low
TOLOH Output Rise Time 15 ns From O.BV to 2.0V
TOHOL Output Fall Time 15 ns From 2.0V to 0.8V

NOTES: 1. Signal at B2CB4A shown for reference only.

2. Setup requirement for asynchronous signal only to guarantee recognition at next eLK.
3. Applies only to T2 state IB ns into T3).
 READ CYCLE

(NOTE 1)
(WIi,iNn. YON)
 WRITE CYCLE
O<OTE ,)

(iiii'iRTi'\
OTiR.voH)

INTA CYCLE OT/R

(NOTES l' 3)
All, WI\.VOH
IRl.Vod

SOFTWARE HALT-
AD, WA, iNTi • VOH
DT/R : IN~RMINATE

NOTES:
,. All signals switch between VOH and VOL unless otherwise specified.
2. ROY is sampled near the end of T2, T3, Tw to determine if Tw machines states are to be inserted.
3. Two INTA cycles run back-to-back. The 80e86 LOCAL AOORiOATA BUS is floating during both INTA cycles. Control signals shown
for second INTA cycle.
4. Signals at 82C84A are shown for reference only.
5. All timing measurements are made at , .5V unless otherwise noted.
 TA = OOC to +70oC (C80C86)
TA = -400C to +850C (I80C86)
TA = -550C to +1250C (M80C86)

TIMING REQUIREMENTS

SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS

TClCL ClK Cycle Period 200 ns

TClCH ClK low Time 118 ns
TCHCl ClK High Time 69 ns
TCH1CH2 ClK Rise Time 10 ns From ·1.0V to 3.5V
TCl2CL1 ClK Fall Time 10 ns From 3.5V to 1 nv
TDVCl Data in Setup Time 30 ns
TClDX Data in Hold Time 10 ns
TR1VCl ROY Setup Time 35 ns
into 82C84A
(see Notes 1,2)
TClR1X ROY Hold Time 0 ns
into 82C84A
Isee Notes 1,21
TRYHCH READY Setup Time 118 ns
into 80C86
TCHRYX READY Hold Time 30 ns Cl=20-100pF
into 80C86
TRYlCL READY inactive to -8 ns
ClK (see Note 4)
TINVCH Setup Time for 30 ns
Recognition IINTR,
NMI, TEST)
(see Note 2)
TGVCH RQ/GT Setup Time 30 ns
TCHGX RQ Hold Time 40 ns
into 80C86
TILIH Input Rise Time 15 ns From 0.8V to 2.0V
(Except ClK)
TIHll Input Fall Time 15 ns From 2.0V to 0.8V
(Except ClK)

TIMING RESPONSES

TClMl Command Active 5 35 ns

Delay (see Note 1)
TClMH Command 1nactive 5 35 ns
TRYHSH READY Active to 110 ns
Status Passive
(see Note 3)
TCHSV Status Active Delay 10 110 ns
TClSH Status Inactive Delay 10 130 ns
TClAV Address Valid Delay 10 110 ns
TClAX Address Hold Time 10 ns
TClAZ Address Float Delay TCLAX 80 ns
TSVlH Status Valid to ALE 20 ns
High (see Note 1)
TSVMCH Status Valid to MCE 30 ns Cl = 20 - 100 pf
High (see Note 1) for all80C86
TCLLH ClK low to ALE Valid 15 ns Outputs IIn eddition
TClMCH ClK low to MCE High 25 ns to 80C86 self-load)
Isee Note 11
TCHLL ALE Inactive Delay 4 18 ns
(see Note 11
TClMCL MC E I nactive Delay 15 ns
(see Note 11
TCLDV Data Valid Delay 10 110 ns
TCHDX Data Hold Time 10 ns
TCVNV Control Active 5 45 ns
Delay Isee Note 11
TCVNX Control Inactive 10 45 ns
Delay (see Note 1)
TAZRl Address Float to 0 ns
Read Active
TIMING RESPONSES (Continued)

SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS

TCLRL RD Active Delay 10 165 ns CL = 20 -100pF

TCLRH RD Inactive Delay 10 150 ns
TRHAV RD Inactive to Next TCLCL-45 ns
Address Active
TCHDTL Direction Control 50 ns
Active Delay
(see Note 1)
TCHDTH Direction Control 30 ns
J nactive Delay
(see Note 1)
TCLGL GT Active Delay 0 85 ns
TCLGH GT Inactive Delay 0 85 ns
TRLRH RD Width 2TCLCL-75 ns
TOLOH Output Rise Time 15 ns From 0.8V to 2.0V
TOHOL Output Fall Time 15 ns From 2.0V to 0.8V

NOTES: 1. Signal at 82C84A or 82C88 shown for reference only.

2. Setup requirement for asynchronous signal only to guarantee recognition at next eLK.
3. Applies only to T3 and wait states.
4. Applies only to T2 state (8 ns into T31.

V,

OUTPUT FROM
T'·7KO
~TESTPOINT
DEVICE UNDER TEST

CL*
I

VIH + O.4V _ • VOH

_
VIL- O.4V
___ ' •.5.V,X
. ....-----------*". X'·5V
,, VOL

A. C. Testing: All input signals (other than eLK) must switch between VILmax -O.4V and VIHmin +O.4V.
eLK must switch between OAV and 3.9V. TR and TF must be less than or equal to '5ns.
elK TR and TF must be less than or equal to 10ns.
 ALE CI2CII OUTPUT)

SEE NOTE 5
j IIDY (S2CS4A INPUT)
 MAXIMUM MODE (Continued) T, T, T, T.

T.

elK
vel

\
12.11.10 (EXCEPT HAL.n
\._---
WRITE CYCLE TCHDJ(-

"Ou-ADo DATA

TCYNX-
DEN

TeL.MH

12(11 OUI"PUTS
SEE NOTES 5,1 . AM we OR AiOWC
TClML. _TelMH

MWreOR~

",>
co:::!
INTACYCLE t.>::i:
g<
"0"-"00
(SEE NOTES 3 II 4,
FlOA
"-
FLOAT

TC OX

AOn-AOo POINTER
FLOAT

r--
I
MeEi
I'1llIl rCHDTH
OTlft

•..""" \'""
02C1Il 0lm'UTS

TCVNV

DEN
IOIJTW'RE HALT-
(DIN .Vo"IID._.~.IlWTC~.~.~.IIlTl •• VoHI

AO,,-ADo INVALID AODAESS

rCLAY

~ /
\ ,-------
i2,S;,iO \._-----
NOTES:
1. All signals switch between VOH and VOL unless otherwise specified.
2. ROY Is sampled near the end 01 T2. T3. Tw to determine II Tw machines states are to ba Insarted.
3. Cascade address Is valid batween Ilrst and second INTA cycle.
4. Two INTA cycles run back-to-back. The 6OC86 LOCAL ADDRIDATA BUS Is floating during both INTA cycles. Control lor pointer
address Is shown lor second INTA cycle.
5. Signals at 82C84A or 82088 are shown lor reference only.
6. The Issuance of tha 82C88 command and control signals (~. MWTC. AMWC. IORC. IOWC. AIOWC. INTA and DEN) lags the
active high 82088 CEN.
7. All timing meaSUremf.llts are made at 1.5V unless otherwise noted.
8. Status Inactive In state Just prior to T4.
 NOTE: 1 SETUP REQUIREMENTS FOR ASYNCHRO-
NOUS SIGNALS ONLY TO GUARANTEE RECOGNITION
AT NEXT elK

Q
"'CLKC""~
__

Cl,.k

TeLAV --

r-! 1 CLlt CYCLE_I r~-

I OR 2 CYCLES

m~~~

HOlO~

"~---
"
rTCLHAV
j I
TClHAV

Y'
-~ TClAl

COP.~ESSO.
 80C86

Instruction SIt Summery

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modO 0 0
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tut- •••
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modI 0 I alllll,. 01 I milS IAllrULATlON
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0 •••

Mnemonics ©Intel, 1978

 18543210
!llsp·PHgh JII/JAE Jump on not below/above o 11 1001 I dlsp
Dlreel wlth,n segment 11101000 dlsp·low Of equal
Indlfeet w,ll'lin segment 11111 t 11 mod 010 <1m JIIE/JA Jump on nol below or
equal/above
a 1 II 0 1 1 1 !lISP

olleel mlefsegment 10011010 ollset·low ollset·h'!lh JI'/J'O Jump on not par/par odd 101 " 101 1 I !lISp I
seo·low seo·hloh JIO Jump on nOI overllow 1011100011 dlsp I
11111111 mo!l 011 <1m JIS Jump on nol Sion 101 1 1\ 001 I !lISp I
LOa' Loop ex limes 11100010 !lISp
LOO'lILOO'E Loop while zero/equal 11 10000 I !lISp
011eel will'Hn segmenl 11110 1001 I d,sp·low lOO'llIlOO'IE Loop ••hiIe nOI
11100000 !lISP
le,o/equlli
Direct wlth,n seoment·shorl 1111010111 !lISP
JCIl Jump on GX ze'o 1 1 1000 11 !lISp
Indnecl within segment ~lllmodl00r/m
Dlrecl mlelseomenl 11 1 101010 I 011set· low liT Intetrupl
I seO·low Typespec,I1ed 11001101 type
111 I I 1 1 1 1 jmod 101 Type 3 11 0011 0 0
liTO Interlupt on ovtlllow 11 001 1 I 0
IIIET Intellupt relurn 11 001 1 I 1

!lata·low

dala-Iow
!lISP ClC Clea, cally 11111000
!lISP ClIIC Complement carry 11110101
!lISP STe Set carry 11 1 I 100 I
!lISP CLD Clurdorecllon 1 1 1 1 \I 00

d,sp $TD Set C1uecl,on 11111101

!lISp ell Clear ,ntellupt 111 1 11 0 1 0 I
JO<Jump onoverllow 1011100001 !l'SP STI Set ,nterrUPI
~iJ
JS·Jumponsl!ln 101 1 11 000 I !lISP HLT Hall 111 1 10 100 I
JIE/JIZ·Jump on not eQual/not zelO o 11 10 I 0 I !lISP WAIT Wa,t 110011 0" I
JIl/J6E'Jumpon not less/oreater
or equal 011 1 1 \ 0 I d,sp ESCEscapellot.'tlnaldtv,rel jIIOt\···Fo~lffl]
JIU/J6 Jump on not less 01 equal/
orealef 101 11 I 1 11 I dlsp
:J LOCI( Bus lOCk prel,. ~oYJ

Al = 8-bit accumulator il s:w:= 01 then 16 bits 01 Immediate data torm the operand.
AX = 16-bit accumulator II s·w:: 11 then an Immediate data byte IS sign extended to
CX '" Count register lorm the 16·M operand
as :: Data segment
If v = 0 then "count" = 1. II v =1 then "counr' In (Cl)
ES '" Extra segment
Above/below refers to unsigned value x::; don't care
Greater", more positive; Z IS used lor Siring primItives tor comparison WIth I.F FLAG
less = less positive (more negatIve) signed values
SEGMENT OVERRIDE PREFIX
,I d '" lthen"to" reg;lfd '" Othen "from" reg
II w = 1 then word instruction; " w s 0 lhtn bVlt InstruCllon 10 0 1 reg 1 1 01

If mod:: 11 then rim is treated as a REG held

if mod E 00 then OISP '" 0·, disp·low and disp-hlgh are absent
if mod'" 01 then DISP = dlsp-Iow sign-extended to 16-blls, dlsp-hlgh 1$ absent 16-8111··11 8-8111•• 01 Slgmlnt
if mod:: 10 then DISP '" disp-hlgh: dlsp-low 000 AX 000 AL 00 ES
001 CX 001 CL 01 CS
il rim· 000 Ihen EA • (BX) • (51) .0ISP
010- OX 010 OL 10 55
il rim· 00llhen EA • (BX) • (01) • OISP 011 BX 011 BL 11 OS
il rim· 010 Ihen EA • (BPI' (51) • OISP 100 SP 100 AH
II rim· 011 then EA • (BP) • (01) • OISP 101 BP 101 CH
il rim· 100 then EA • (51) • OISP 110 51 110 OH
il rim· 101 then EA • (Ol) .OISP 111 01 111 BH
il rim· 110 then EA • (BPI' OISP'
il rim· 111 then EA • (BX) .0ISP
DISP follows 2nd byte of instruction (before oata It required)
m HARRIS 82C52
CMOS Serial
Controller Interface

• SINGLE CHIP UART/BRG

• DC TO 16MHz OPERATION
• CRYSTAL OR EXTERNAL CLOCK INPUT
• ON CHIP BAUD RATE GENERATOR
... 72 SELECTABLE BAUD RATES cso
• INTERRUPT MODE WITH MASK CAPABILITY vcc
OR
• MICROPROCESSOR BUS ORIENTED INTERFACE
501
• 80C86 COMPATIBLE INTR
• SCALED SAJI IV CMOS PROCESS RST

• SINGLE 5V POWER SUPPLY TBRE

• LOW POWER -1mA/MHz TYPICAL

co
RTS
• MODEM INTERFACE DTR
• LINE BREAK GENERATION AND DETECTION DSR

• LOOPBACK AND ECHO MODES CTS

GND
SDO

The 82C52 is a high performance programmable Universal Asynchronous

Receiver/Transmitter (UART) and Baud Rate Generator (BRG) on a single
chip. Utilizing the Harris advanced Scaled SAJI IV CMOS process, the
82C52 will support data rates from D.C. to 1M baud asynchronously with a
16X clock (0-16 MHz clock frequency).

The on-chip Baud Rate Generator can be programmed for anyone of 72

different baud rates using a single industry standard crystal or external
frequency source. A unique pre-scale divide circuit has been designed to
provide standard RS-232-C baud rates when using anyone of three in-
dustry standard baud rate crystals (1.8432 MHz, 2.4576 MHz, or 3.072MHz).

A programmable buffered clock output (CO) is available and can be pro-

grammed to provide either a buffered oscillator or 16X baud rate clock for
general purpose system usage.

Inputs and outputs have been designed with full TTL/CMOS compatibility
in order to facilitate mixed TTL/NMOS/CMOS system design.

vCC - PIN 27
~ GND-PIN 16
IlTlI
lITO
m HARRIS
CMOS PROGRAMMABLE
82C54
INTERVAL TIMER

• COMPATIBLE WITH NMOS 8264

-ENHANCED VERSION OF NMOS 8263
• THREE INDEPENDENT 16 BIT COUNTERS D7 VCC
• SIX PROGRAMMABLE COUNTER MODES WR
D6
• STATUS READ-BACK COMMAND AD
05
• BINARY OR 8CD COUNTING
• FULLY TTL COMPATIBLE 04 CS
• SCALED SAJI IV CMOS PROCESS 03 Al

• LOWPOWER 02 AD
-ICCSB· 10/JA 0, CLK 2
-ICCOP· 10mAO 8MHz COUNT FREQUENCY
DO aUT2
• SINGLE 6V POWER SUPPLY
CLKO GATE 2
• COMMERCIAL,INDUSTRIAL AND MILITARY
TEMPERATURE RANGES aUTO CLK 1
GATE a GATE 1

GNO OUT 1

The Harris 82C54 is a high performance CMOS Programmable Interval Timer

manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI
IV). The 82C54 has three independently programmable and functional 16
bit counters, each capable of handling clock input frequencies of up to 8MHz.
The high speed and industry standard configuration of the 82C54 make it
compatible with many industry standard microprocessors.

Six programmable timer modes allow the 82C54 to be used as an event counter,
elapsed time indicator, programmable one-shot along with many other ap-
plications.

Static CMOS circuit design insures low operation power Harris advanced SAJI
process results in a significant reduction in power with performance equal to
or greater than existing equivalent products.

OUT 0

Il1l
eL.K 1
WIl
QATE 1

OUT 1

"
e-s
 PIN
SYMBOL NUMBER TYPE NAME AND FUNCTION

07-00 1-8 1/0 Data: Bi-directional three state data bus lines, connected to system data bus.

ClKO 9 I Clock 0: Clock input of Counter O.

OUTO 10 0 Output 0: Output of Counter O.

GATE 0 11 I Gate 0: Gate input of Counter O.

GNO 12 Ground: Power supply connection.

OUT 1 13 0 Out 1: Output of Counter 1.

GATE 1 14 I Gate 1; Gate input of Counter 1.

ClK 1 15 I Clock 1: Clock input of Counter 1.

GATE 2 16 I Gate 2: Gate input of Counter 2.

OUT2 17 0 Out 2: Output of Counter 2.

ClK 2 18 I Clock 2: Clock input of Counter 2.

AO.A1 19-20 I Address: Select inputs for one of the three counters or Control
Word Register for read/write operations. Normally connected to
the system address bus.
A1 AO Selects
0 0 Counter 0
0 1 Counter 1
1 0 Counter 2
1 1 Control Word Register

CS 21 I Chip Select: A Iowan this input enables the 82C54 to respond to

AD and WA signals. AD and WR are ignored otherwise.

RO 22 I Read: This input is low during CPU read operations.

WR 23 I Write: This input is low during CPU write operations.

VCC 24 Power: +5 V power supply con nection.

The 82C54 is a programmable interval timer/counter de- microcomputers which can be implemented with the 82C54
signed for use with microcomputer systems. It is a general are:
purpose, multi-timing element that can be treated as an
array of I/O ports in the system software. • Real time clock
• Event counter
The 82C54 solves one of the most common problems in • Digital one-shot
any microcomputer system, the generation of accurate • Programmable rate generator
time delays under software control. Instead of setting • Square wave generator
up timing loops in software, the programmer configures the • 8inary rate multiplier
82C54 to match his requirements and programs one of the • Complex waveform generator
counters for the desired delay. After the desired delay, • Complex motor controller
the 82C54 will interrupt the CPU. Software overhead
is minimal and variable length delays can easily be ac-
commodated.
This 3-state, bi-directional, 8-bit buffer is used to inter-
face the 82C54 to the system bus (see FiQure 1).
The ReadlWrite Logic accepts inputs from the system bus The Counters are fully independent. Each Counter may
and generates control signals for the other functional operate in a different Mode.
blocks of the 82C54. A 1 and AO select one of the three
counters or the Control Word Register to be read from/ The Control Word Register is shown in the figure; it
written into. A "low" on the RD input tells the 82C54 is not part of the Counter itself, but its contents determine
that the CPU is reading one of the counters. A "low" how the Counter operates.
on the WR input tells the 82C54 that the CPU is writing
either a Control Word or an initial count. Both RD and
WR are qualified by CS; RD and WR are ignored unless
the 82C54 has been selected by holding CS low.

The Control Word Register (Figure 2) is selected by the

ReadlWrite Logic when A 1, AO = 11. If the CPU then does
a write operation to the 82C54, the data is stored in the
Control Word Register and is interpreted as a Control Word
used to define the Counter operation.

The Control Word Register can only be written to; status

information is available with the Read-Back Command.

These three functional blocks are identical in operation,

so only a single Counter will be described. The internal
block diagram of a single counter is shown in Figure 3.
The status register, shown in the Figure, when latched, con-
tains the current contents of the Control Word Register
and status of the output and null count flag. (See detailed
explanation of the Read-Back command.)

The actual counter is labeled CE (for "Counting Element).

It is a 16-bit presettable synchronous down counter.

OlM and Oll are two a-bit latches. Ol stands for "Out-
put latch"; the subscripts M and l for "Most significant
byte" and "least significant byte" respectively. Both
are normally referred to as one unit and called just OL.
These latches normally "follow" the CE, but if a suitable
Counter latch Command is sent to the a2C54, the latches
"latch" the present count until read by the CPU and then
return to "following" the CEo One latch at a time is
enabled by the counter's Control logic to drive the internal
bus. This is how the 16-bit Counter communicated over
the a-bit internal bus. Note that the CE itself cannot
be read; whenever you read the count, it is the 0 l that
is bei ng read.

Similarly, there are two a-bit registers called CRM and CRl
(for "Count Register"). Both are normally referred to
as one unit and called just CR. When a new count is
written to the Counter, the count is stored in the CR and
later transferred to the CEo The Control logic allows After power-up, the state of the 82C54 is undefined.
one register at a time to be loaded from the internal bus. The Mode, count value, and output of all Counters are
Both bytes are transferred to the CE simultaneously. undefined.
CRM and CR l and cleared when the Counter is pro-
grammed for one byte counts (either most significant byte How each Counter operates is determined when it is pro-
only or least significant byte only) the other byte will be grammed. Each Counter must be programmed before it can
zero. Note that the CE cannot be written into; whenever be used. Unused counters need not be programmed.
a count is written, it is written into the CR.

The Control logic is also shown in the diagram. ClK n,

GATE n, and OUT n are all connected to the outside world Counters are programmed by writing a Control Word and
through the Control logic. then an initial count.

All Control Words are written into the Control Word

Register, which is selected when A 1, AD = 11. The Control
The a2C54 is treated by the system software as an array Word specifies which Counter is being programmed.
of peripheral I/O ports; three are counters and the fourth
is a control register for MODE programming. By contrast, initial counts are written into the Counters,
not the Control Word Register. The A1, AD inputs are
Basically, the select inputs AD, A1 connect to the AD, used to select the Counter to be written. The format of
A1 address bus signals of the CPU. The CS can be derived the initial count is determined by the Control Word used.
directly from the address bus using a linear select method
or it can be connected to the output of a decoder, such as
a Harris HD-644D for larger systems.
 82C54
Control Word Format
A1, AO = 11; CS = O;RD = l;WR =0

SC - select Counter: M - MODE:

SCl SCO M2 Ml
0 0 Select Counter a 0 0 0 Mode 0
0 1 Select Counter 1 0 0 1 Mode 1
1 0 Select Counter 2 X 1 0 Mode 2
Read-Back Command X 1 1 Mode 3
1 1
(See Read Operations)
1 0 0 Mode 4

RW - Re.dlWrlte: 1 0 1 Mode 5

RWl RWO

0 0 Counter Latch Command (see Read

Operations)

0 1 ReadlWrite least significant byte only. Binary Counter 16-bits

1 0 ReadIWrite most significant byte only. Binary Coded Decimal (BCD) Counter
1 1 AeadlWrite least significant byte first, (4 Decades)
then most significant byte.

The programming procedure for the 82C54 is very flexible. If a Counter is programmed to read/write two-byte counts,
Only two conventions need to be remembered: the following precaution applies: A program must not
transfer control between writing the first and second byte
1. For each Counter, the Control Word must be written to another routine which also writes into that same Coun-
before the initial count is written. ter. Otherwise, the Counter will be loaded with an in-
correct count.
2. The initial count must follow the count format specified
in the Control Word (least significant byte only, most
significant byte only, or least significant byte and then
most significant byte). It is often desirable to read the value of a Counter without
disturbing the count in progress. This is easily done in the
Since the Control Word Register and the three Counters 82C54.
have separate addresses (selected by the A 1, AO inputs),
and each Control Word specifies the Counter it applies to There are three possible methods for reading the Counters.
(SCO, SC1 bits), no special instruction sequence is required. The first is through the Read-Back command, which is
Any programming sequence that follows the conventions explained later. The second is a simple read operation
above is acceptable. of the Counter, which is selected with the A 1, AO inputs.
The only requirement is that the ClK input of the selected
A new initial count may be written to a Counter at any Counter must be inhibited by using either the GATE input
time without affecting the Counter's programmed Mode or external logic. Otherwise, the count may be in process
in any way. Counting will be affected as described in the of changing when it is read, giving an undefined result.
Mode definitions. The new count must follow the pro-
grammed count format.
 82C54

A, Ao A, Ao

Control Word - Counter 0 1 1 Control Word - Counter 2 1 1

LSB of count - Counter 0 0 0 Control Word - Counter 1 1 1
MSB of count - Counter 0 0 0 Control Word - Counter 0 1 1
Control Word - Counter 1 1 1 LSB of count - Counter 2 1 0
LSB of count - Counter 1 0 1 MSB of count - Counter 2 1 0
MSB of
Control
count
Word
-
-
Counter 1
Counter 2
0
1 ,
1 LSB of
MSB of
count
count
-
-
Counter 1
Counter 1
0
0
1
1
LSB of count - Counter 2 1 0 LSB of count - Counter 0 0 0
MSB of count - Counter 2 1 0 MSB of count - Counter 0 0 0

A, Ao A, Ao

Control Word - Counter 0 1 1 Control Word - Counter 1 1

Control Word - Counter 1 1 1 Control Word - Counter 0 1
Control
LSB of
Word
count
-
-
Counter
Counter
2
2
1
1
1
0
LSB of
Control
count
Word
-
-
Counter
Counter
1
2 ,
1

LSB of count - Counter 1 0 1 LSB of count - Counter 0 0

LSB of count - Counter 0 0 0 MSB of count - Counter 1 1
MSB of count - Counter 0 0 0 LSB of count - Counter 2 0
MSB of count - Counter 1 0 1 MSB of count - Counter 0 0
MSB of count - Counter 2 1 0 MSB of count - Counter 2 0

The selected Counter's output latch (aLl latches the count

when die Counter Latch Command is received. This count
The other method involves a special software command is held in the latch until it is read by the CPU (or until the
called the "Counter Latch Command". Like a Control Counter is reprogrammed). The count Is then unlatched
Word, th is command is written to the Control Word Reg- automatically and the OL returns to "following" reading
ister, which is selected when A 1, AO = 11. Also, like a the contents of the Counters "on the fly" without affecting
Control Word, the SCO, SC1 bits select one of the three counting in progress. Multiple Counter Latch Commands
Counters, but two other bits, 05 and 04, distinguish this may be used to latch more than one Counter. Each latched
command from a Control Word. Counter's OL holds its count until read. Counter Latch
Commands do not affect the programmed Mode of the
Counter in any way.

If a Counter is latched and then, some time later, latched

again before the count is read, the second Counter Latch
Command is ignored. The count read will be the count
at the time the first Counter Latch Command was issued.

With either method, the count must be read according to

SC1,SCO - specify counter to be latched the programmed format; specifically, if the Counter is pro-
grammed for two byte counts, two bytes must be read.
SC1 SCD Counter
The two bytes do not have to be read one right after the
0 0 0
other; read or write or programming operations of other
0 1 1
Counters may be inserted between them.
1 0 2
1 1 Read-Back Command
Another feature of the 82C54 is that reads and writes of
05,04 - 00 designates Counter Latch Command the same Counter may be interleaved; for example, if the
Counter is programmed for two byte counts, the following
X - don't care
sequence is valid.

1. Read least significant byte.

2. Write new least significant byte.
3. Read most significant byte.
4. Write new most significant byte.
If a Counter is programmed to read or write two-byte
counts, the following precaution applies: A program
MUST NOT transfer control between reading the first
and second byte to another routine which also reads from
that same Counter. Otherwise, an incorrect count will 0]1= OUT PIN IS 1
O=OUTPINISO
be read. 06 1 = NULL COUNT
0.: COUNT AVAILABLE FOR READING
0s-Do COUNTER PROGRAMMED MODE (SEE FIGURE 7)

The read-back command allows the user to check the

count value, programmed Mode, and current state of the
OUT pin and Null Count flag of the selected counter(s). NULL COUNT bit 06 indicates when the last count written
to the counter register (CR) has been loaded into the
The command is written into the Control Word Register counting element (CE). The exact time this happens
and has the format shown in Figure 8. The command depends on the Mode of the counter and is described in the
applies to the counters selected by setting their corres- Mode Oefinitions, but until the count is loaded into the
ponding bits 03, 02, 01 = 1. counting element (CEl, it can't be read from the counter.
If the count is latched or read before this time, the count
value will not reflect the new count just written. The op-
eration of Null Count is shown in Figure 10.

05: 0'" LATCH COUNT OF SELECTED COUNTER(S)

THIS ACTION: CAUSES:
04: 0 = LATCH STATUS OF SELECTED COUNTER(S)
A. WRITE TO 1l4E CONTROL WORO REGISTER,! 11 NULL COUNT=1
03: 1 SELECT COUNTER 2
02: 1 = SELECT COUNTER 1 B. WRITE TO 1l4E COUNT REGISTER ICR);12] NULL COUNT=l
01: 1 - SELECT COUNTER 0 C. NEW COUNT IS LOADED IHTO CE (CR_CE); NUll COUNT=O
Do: RESERVED FOR FUTURE EXPANSION; MUST BE 0
[1 J ONLY THE COUNTER SPECifIED BY THE CONTROL WORD WILL HAVE
ITS NULL COUNT SET TO 1. NULL COUNT BITS OF OTHER COUNTERS
ARE UNAFFECTED.

(2] ~J~~I~~~~T~~~
~~~R~~~Eg'~~~F~~TBr;frgo~~~E
~~~i
GOES TO 1 WHEN THE SECOND BYTE 1$ WRITIEN.

The read-back command may be used to latch multiple

counter output latches (OL) by setting the COUNT bit
05 = 0 and selecting the desired counter(s). This single
command is functionally equivalent to several counter latch
commands, one for each counter latches. Each counter's If multiple status latch operations of the counter(s) are
latched count is held until it is read (or the counter is performed without reading the status, all but the first are
reprogrammed). That counter is automatically unlatched ignored; i.e., the status that will be read is the status of the
when read, but other counters remain latched until they counter at the time the first status read-back command was
are read. If multiple count read-back commands are issued issued.
to the same counter without reading the count, all but the
first are ignored; i.e., the count which will be read is the Both count and status of the selected counter(s) may be
count at the time the first read-back command was issued. latched simultaneously by setting both COUNT and status
bits 05, 04 = O. This is functionally the same as issuing
The read-back command may also be used to latch status two separate read-back commands at once, and the above
information of selected counter(s) by setting STATUS discussions apply here also. Specifically, if multiple count
bit 04 = O. Status must be latched to be read; status of and/or status read-back commands are issued to the same
a counter is accessed by a read from that counter. counter(s) without any intervening reads, all but the first
are ignored. This is illustrated in Figure 11.
The counter status format is shown in Figure 9. Bits
05 through 00 contain the counter's programmed Mode If both count and status of a counter are latched, the first
exactly as written in the last Mode Control Word. OUT- read operation of that counter will return latched status,
PUT bit 07 contains the current state of the OUT pin. regardless of which was latched first. The next one or two
This allows the user to monitor the counter's output via reads (depending on whether the counter is programmed
software, possibly eliminating some' hardware from a for one or two type counts) return latched count. Subse-
system. quent reads return unlatched count.
 CS Ro WR A, Ao Control Word is written, OUT is initially low, and will
remain low until the Counter reaches zero. OUT then
0 1 0 0 0 Write into Counter 0
goes high and remains high until a new count or a new
0 1 0 0 1 Write into Counter 1 Mode 0 Control Word is written to the Counter.
0 1 0 1 0 Write into Counter 2
GATE = 1 enables counting; GATE = 0 disables counting.
0 1 0 1 1 Write Control Word
GATE has no effect on OUT.
0 0 1 0 0 Read from Counter 0

0 0 1 0 1 Read from Counter 1 After the Control Word and initial count are written to
a Counter, the initial count will be loaded on the next
0 0 1 1 0 Read from Counter 2
ClK pulse. This ClK pulse does not decrement the count,
0 0 1 1 1 No-Operation (3-State) so for an intial count of N, OUT does not go high until
1 X X X X No-Operation (3-State) N + 1 ClK pulses after the initial count is written.

0 1 1 X X No-Operation (3-State)
If a new count is written to the Counter it will be loaded
on the next ClK pulse and counting will continue from
the new count. If a two-byte count is written, the follow-
ing happens:

The following are defined for use in describing the opera- 1 - Writing the first byte disables counting. Out is set
tion of the 82C54. low immediately (no clock pulse required).

ClK PULSE: a rising edge, then a falling edge, 2 - Writing the second byte allows the new count to be
in that order, of a Counter's ClK input. loaded on next ClK pulse.

This allows the counting sequence to be synchronized by

COUNTER software. Again OUT does not go high until N + 1 ClK
lOADING: the transfer of a count from the CR to the pulses after the new count of N is written.
CE (See "Functional Description")
If an initial count is written while GATE = 0, it will still
be loaded on the next ClK pulse. When GATE goes high,
OUT will go high N ClK pulses later; no ClK pulse is
needed to load the Counter as this has already been done.

Command
07 06 05 04 03 O2 01 00

1 1 0 0 0 0 1 0 Read back count and status of Count and status latched

Counter 0 for Counter 0
1 1 1 0 0 1 0 0 Read back status of Counter 1 Status latched for Counter 1
1 1 1 0 1 1 0 0 Read back status of Counters 2, 1 Status latched for Counter
2, but not Counter 1
1 1 0 1 1 0 0 0 Read back count of Counter 2 Count latched for Counter 2
1 1 0 0 0 1 0 0 Read back count and status of Count latched for Counter 1,
Counter 1 but not status
1 1 1 0 0 0 1 0 Read back status of Counter 1 Command ignored, status
aireadv latched for Counter 1
 pulses after any trigger. The one-shot pulse can be repeated
without rewriting the same count into the counter. GATE
OUT will be initially high. OUT will go low on the CLK has no effect on OUT.
pulse following a trigger to begin the one-shot pulse, and
will remain low until the Counter reaches zero. OUT will If a new count is written to the Counter during a one-shot
then go high and remain high until the CLK pulse after the pulse, the current one-shot is not affected unless the
next trigger. Counter is retriggered, In that case, the Counter is loaded
with the new count and the one-shot pulse continues
After writing the Control Word and initial count, the until the new count expires.
Counter is armed. A trigger results in loading the Counter
and setting OUT low on the next CLK pulse, thus starting
the one-shot pulse N CLK cycles in duration. The one-
shot Is retriggerable, hence OUT will remain low for N ClK This Mode functions like a divide-by-N counter. It is
typicaily used to generate a Real Time Clock interrupt.
OUT will initially be high. When the initial count has
CW.10 LII.4
decremented to 1, OUT goes low for one CLK pulse. OUT
WIl l..JU then goes high again, the Counter reloads the initial count
and the process is repeated. Mode 2 is periodic; the same
ClK
sequence is repeated indefinitely. For an initial count
of N, the sequencerepeats every N ClK cycles.
OATE

OUT
::J
l.-.JU--------
CW.12 LSI.3
I N I N I N IN I WIl

CW.10 LSI.3

WIl l..JU
ClK

QATE

OUT =-=:J_____r-
I N IN IN IN I I ~I~I I g I ~~I WIl l....Il...-.J--------
CW.U LSI.3

WIl

ClK

GATE

______
r- OUT ~ \ r
OUT

=='
I N IN IN I N I I g I ~~I
ININININiN I~I Ig I

NOTE: THE FOLLOWING CONVENTIONS APPLY TO AU MODE TIMING DIAQRAMS:

1. COUNTERS ARE PROGRAMMED FOR BINARY (NOT ICD) COUNTING AND FOR
READING/WRITINQ LEAST SIGNIFICANT BYTE (tSS) ONLY.
2, THE COUNTER IS ALWAYS SELECTED (el ALWAYS lOW).
3. CW STANDS FOR "CONTROL WORD": CW .10 MEANS A CONTROL. WORD OF 10,
HEX 1$ WRITTEN TO THE COUNTER.
4. lSS STANDS FDA "LEAST SIGNIFICANT BYTE" OF COUNT,
5. NUMBERS BELOW DIAGRAMS ARE COUNT VALUES.
THE LOWER NUMBER IS THE LEAST SIGNIFICANT BYTE.
THE UPPER NUMBER 1$ THE MOST SIGNIFICANT BYTE. SINCE THE COUNTER
IS PROGRAMMED TO READ/WRITE lSS ONLY, THE MOST SIGNIFICANT BYTE
CANNOT 8E READ.
N STANDS FOR AN UNDEFINED COUNT.
VERTICAL LINES SHOW TRANSITIONS BETWEEN COUNT VALUES.
GATE = 1 enables counting; GATE = 0 disables counting.
If GATE goes low during an output pulse, OUT is set
high immediately. A trigger reloads the Counter with the Mode 3 is typically used for Baud rate generation. Mode
initial count on the next ClK pulse; OUT goes low N 3 is similar to Mode 2 except for the duty cycle of OUT.
ClK pulses after the trigger. Thus the GATE input can OUT will initially be high. When half the initial count
be used to synchronize the Counter. has expired, OUT goes low for the remainder fo the count.
Mode 3 is periodic; the sequence above is repeated indef-
After writing a Control Word and initial count, the Counter initely. An initial count of N results in a square wave
will be loaded on the next ClK pulse. OUT goes low N with a period of N ClK cycles.
ClK pulses after the initial count is written. This allows
the Counter to be synchronized by software also. GATE = 1 enables counting; GATE = 0 disables counting.
If GATE goes low while OUT is low, OUT is set high
Writing a new count while counting does not affect the immediately; no ClK pulse is required. A trigger reloads
current counting sequence. If a trigger is received after the Counter with the initial count on the next ClK pulse.
writing a new count but before the end of the current Thus the GATE input can be used to synchronize the
period, the Counter will be loaded with the new count Counter.
on the next ClK pulse and counting will continue form the
new count. Otherwise, the new count will be loaded at After writing a Control Word and initial count, the Counter
the end of the current counting cycle. will be loaded on the next ClK pulse. OUT goes low N
ClK pulses after the initial count is written. This allows
the Counter to be synchronized by software.

CW.1. lSB.3

WII """'"L.1l-J
C'K

GATE

OUT

I N I N I N I N I
CW.14 LSB.3

W1\ """'"L.1l-J
C'K

GATE

OUT
==.J LJ
I I I I I
N N N N I~I~I
CW_14 lSB_4
CW.1' lse ••
WII WIl 'Lfl.-J~------------
C'K

GATE

OUT
=.=J
I N I N I N I N I
current counting sequence. If a trigger is received after
CW.lI LSB.3
writing
half-cycle
a new count but before
of the square wave, the Counter
the end of the current
will be loaded
WI!
Ln-J~--------
with the new count on the next CLK pulse and counting
will continue from the new count. Otherwise, the new
count will be loaded at the end of the current half-cycle.
OATE

OUT~
u
o1 I I I I I
0
0
FF
FF
FF
FE
FF
FD
EVEN COUNTS: OUT is initially high. The initial count
is loaded on one CLK pulse and then is decremented by
CW.lI lS •• 3~ _
two
OUT
on succeeding CLK
changes value and the Counter
pulses. When the count
is reloaded
expires
with the
Wl!Ln-J
initial count. The above process is repeated indefinitely.

ODD COUNTS: OUT is initially high. The initial count

minus one (an even number) is loaded on one CLK pulse
and then is decremented by two on succeeding CLK pulses.
One CLK pulse after the count expires, OUT goes low and LJ
the Counter is reloaded with the initiai count minus one. o1 I I I
0
0
FF
FF
Succeeding CLK pulses decrement the count by two.
When the count expires, OUT goes high again and the
Counter is reloaded with the initial count minus one.
The above process is repeated indefinitely. So for odd
counts, OUT will be high for (N + 1)/2 counts and low for
(N-1 )/2 counts.
GATE

OUT~

OUT will be initially high. When the initial count expires, I I I I I

N N N N

OUT will go low for one CLK pulse and then go high
again. The counting sequence is "Triggered" by writing
the initial count.

GATE =
1 enables counting; GATE 0 disables counting. =
GATE going low freezes OUT in current logic state.

OUT will initially be high. Counting is triggered by a rising

After writing a Control Word and initial count, the Counter edge of GATE. When the initial count has expired, OUT
will be loaded on the next CLK pulse. This CLK pulse will go low for one CLK pulse and then go high again.
does not decrement the count, so for an initial count of
N, OUT does not strobe low until N + 1 CLK pulses after After writing the Control Word and initial count, the
the initial count is written. counter will not be loaded until the CLK pulse after a
trigger. This CLK pulse does not decrement the count,
If a new count is written during counting, it will be loaded so for an initial count of N, OUT does not strobe low until
on the next CLK pulse and counting will continue from the N+1 CLK pulses after trigger.
new count. If a two-byte count is written, the following
happens: A trigger results in the Counter being loaded with the
initial count on the next CLK pulse. The counting
1. Writing the first byte has no effect on counting. sequence is triggereble. OUT will not strobe low for
2. Writi ng the second byte allows the new cou nt to be N + 1 CLK pulses after any trigger. GATE has no effect
loaded on the next CLK pulse. on OUT.

This allows the sequence to be "retriggered" by software. If a new count is written during counting, the current
OUT strobes low N + 1 CLK pulses after the new count counting sequence will not be affected. If a trigger occurs
of N is written. after the new count is written but before the current count
expires, the Counter will be loaded with the new count diately after it is sampled. In this way, a trigger will be de-
on the next CLK pulse and counting will continue from tected no matter when it occurs - a high logic level does
there. not have to be maintained until the next rising edge of
CLK. Note that in Modes 2 and 3, the GATE input is both
edge- and level-sensitive.

When a Control Word is written to a Counter, all Control New counts are loaded and Counters are decremented on
Logic is immediately reset and OUT goesto a known in- the falling edgeof CLK.
itial state; no CLK pulsesare required for this.
The largest possible initial count is 0; this is equivalent
to 216 for binary counting and 104 for BCD counting.

The GATE input is always sampled on the rising edge of The Counter does not stop when it reacheszero. In Modes
CLK. In Modes 0,2, 3, and 4 the Gate input is level sensi- 0, 1, 4, and 5 the Counter "wraps around" to the highest
tive, and the logic level is sampled on the rising edge of count, either FFFF hex for binary counting or 9999 for
CLK. In Modes 1, 2, 3, and 5 the GATE input is rising- BCD counting, and continues counting. MOdes 2 and 3
edge sensitive. In these Modes, a rising edge of Gate (trig- are periodic; the Counter reloads itself with the initial
ger) sets an edge-sensitive flip-flop in the Counter. This count and continues counting from there.
flip-flop in the Counter. This flip-flop is reset imme-
5lgnll Low
5tltul Or Going Ailing High
Modll Low
CW.1A 1.511_:1
WIILJI......J------- 0 Disables -- Enables
counting counting

1 -- 1) Initiates
counting
--
2) Resets output
after next clock

2 1) Disables
counting Initiates Enables
2) Sets output counting counting
immediately
high

cw.,. L5B.3 3 1) Disables

WII
LJI......J----------- counting Initiates Enebles
2) Sets output counting q,ountlng
Immediately
high

4 Disables
counting
-- Enables
counting

-- --
OUT =:J 5 Initiates
counting

ININININININI:I

Mode
Mln Max 1
,
Count Count

0
, 1
0
0
2 2 0

OUT =.J 4
3 3
1
0
0
._-- ----
INININININI 5 1 0
 Supply Voltage +8.0 Volts Operating Temperature Range
Operating Voltage Range +4V to +7V Commercial OOCTO +700C
Input Voltage Applied GND-2.0V to +6.5V Industrial -400C to +850C
Output Voltage Applied GND-0.5V to VCC +O.5V Military -550C to + 1250C
Storage Temperature Range -650C to +1500C Maximum Power Dissipation 1 Watt

CAUTION: Stresses above those listed in the "ABSOLUTE MAXIMUM RA TINGS" may cause permanent damage
to the device. This is a stress only rating and operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.

D.C. ELECTRICAL CHARACTERISTICS

VCC = 5.0V±10%;TA = OOCto +700C (C82C54);TA =-400C to +850C (I82C54); TA = -550C to +1250C (M82C54)

SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS

VIH Logical One 2.0 V C82C54. 182C54

Input Voltage 2.2 V M82C54

Vil Logical Zero 0.8 V

Input Voltage

VOH Output High Voltage 3.0 V 10H= -2.5mA

VCC -0.4 V 10H= -1001JA

VOL Output Low Voltage 0.4 V 10l = +2.5mA

III Input Leakage Current -1.0 +1.0 IJA OV~VIN~VCC

10 Output Leakage Current -10.0 +10.0 IJA OV~voSVCC

ICCS8 Standby Power Supply Current 10 IJA VCC = 5.5V

VIN = VCC or GND
OUTPUTS OPEN
ICCOP Operating Power Supply Current 10 mA VCC = 5.5V
ClK FREQ = 8MHz
OUTPUTS OPEN

CAPACITANCE
TA = 250C; VCC = GND = OV; VIN = +5V or GND

SYM80l PARAMETER MIN MAX UNITS TEST CONDITIONS

CIN' Input Capacitance 5 pi FREQ= lMHz

Unmeasured pins
returned to GND

COUTo Output Capacitance 15 pi

CliO' I/O Capacitance 20 pi

 A.C. CHARACTERISTICS
VCC = +5V±10%:TA = OOCto +700C (C82C54);TA = -400C to +850C (I82C54); TA = -550C to +1250C (M82C54)

READ CYCLE

SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS

TAA Address Stable Before AD 45 ns

TSA CS Stable Before ~ 0 ns
TAA Address Hold Time After R15 0 ns
TAA A 0 Pulse Width 150 ns
TAD Data Delay from AD 120 ns
TAD Data Dalay from Address 220 ns
TDF A 0 to Data Floating 5 90 ns
TAV Command Recovery Time 200 ns

WRITE CYCLE

TAW Address Stable Before WA 0 ns

TSW CS Stable Before WR 0 ns
TWA Address Hold Time WR 0 ns
TWW WR Pulsa Width 150 ns
TOW Data Setup Time Before WR 140 ns
TWO Deta Hold Time After WR 10 ns
TAV Command Recovery Time 200 ns

CLOCK AND GATE

TClK Clock Period 125 DC ns

TPWH High Pulse Width 60 ns
TPWl low Pulse Width 60 ns
TA Clock Aise Time 100 ns
TF Clock Fall Time 100 ns
TGW Gate Width High 50 ns
TGl Gate Width low 50 ns
TGS Gate Satup Time to ClK 50 ns
TGH Gate Hold Time After ClK 50 ns
TOO Output Delay from ClK 150 ns
TODG Output Delay from Gate 120 ns

VI

OUTPUT FAOM
1
~TESTPOINT
1
TEST
CONDITION

2
VI

1.7V

5.0V
523

2K
AI A2

OPEN

UK
Cl

150pf

50pf
DEVICE UNDER TEST
3 1.5V 750 OPEN OPEN
Cl*

INPUT OUTPUT

VIH + OAV VOH

5V Xl.5V
1. X
Vll- 0.4V VOL

A. C. Testing: All input signals must switch between VIL -OAV and VIH +DAV
TR and TF must be less than or equal to 15ns.
3-41
 82C54

I RECOVERV

CLOCK AND GATE

m HARRIS CMOS PROGRAMMABLE
82C55A
PERIPHERAL INTERFACE

• PIN COMPATIBLE WITH NMOS B255A

• 24 PROGRAMMABLE I/O PINS
• FULLY TTL COMPATIBLE
• BUS-HOLD CIRCUITRY ON ALL 110 PORTS ELIMINATES PULL·UP RESISTORS
• HIGH SPEED. NO "WAIT STATE" OPERATION WITH sMHz SOCS6
• DIRECT BIT SET/RESET CAPABILITY
• ENHANCED CONTROL WORD READ CAPABILITY
• SCALED SAJIIV CMOS PROCESS
• SINGLE 5V POWER SUPPLY
.2.5 mA DRIVE CAPABILITY ON ALL 1/0 PORT OUTPUTS
• LOW STANDBY POWER - ICCSB = 10 !J.A
• COMMERCIAL. INDUSTRIAL AND MILITARY TEMPERATURE RANGES

Description
The Harris 82C55A is a high performance CMOS version of the industry standard
8255A and is manufactured using a self-aligned silicon gate CMOS process (Scaled
SAJI IV). It is a general purpose programmable I/O device which may be used with
many different microprocessors. There are 24 I/O pins which may be individually
programmed in 2 groups of 12 and used in 3 major modes of operation. The high
performance and industry standard configuration of the 82C55A make it compatible
with microprocessors such as the 80C86. 8048. 8051. and NSC800.

Static CMOS circuit design insures low operating power. TTL compatibility of VIH =
2.0 volts over the industrial temperature range and bus hold circuitry eliminate the
need for pull-up resistors. Harris's advanced SAJI process results in performance
equal to or greater than existing equivalent products at a fraction of the power.

POWER
{_.SV
SUPPLIES
_ONO

01-Dt DATA BUS (BI-DIRECTIDNAl)

RESET RESeT INPUT
CS CHIP SELECT
RD READ INPUT
WR WAITE INPUT
AO, A1 PORT ADDRESS
PA7-PAO PORT A(Bln
PB7·PBO PORT B (Bin
PC7-PCO PORTC(Bln
VCC +5 VOLTS
GND o VOLTS
REAO
WRITE
CQHTROl
lOGIC
Data Bus Buffer

This 3-state bidirectional 8-bit buffer is used to interface the

82C55A to the system data bus. Data is transmitted or
received by the buffer upon execution of input or output
instructions by the CPU. Control words and status information
are also transferred through the data bus buffer.

Read/Write and Control Logic

The function of this block is to manage all of the internal and

external transfers of both Data and Control or Status words. It
accepts inputs from the CPU Address and Control busses and
in turn, issues commands to both of the Control Groups.

(CS)

Chip Select. A "low" on this input pin enables the communica-

tion between the 82C55A and the CPU.

(RD) Figure'
82C55A Block Dlegrlm
Read. A "low" on this input pin enables the 82C55A to send the Dltl Bu. Buffer Ind Reid/Write
data or status information to the CPU on the data bus. In Control Logic Function.
essence, it allows the CPU to "read from" the 82C55A.
(RESET)
(WR) Reset. A "high" on this input clears the control register and all
Write. A "low" on this input pin enables the CPU to write data or ports (A, B, C) are set to the input mode. "Bus hold" devices
control words into the 82C55A. internal to the 82C55A will hold the I/O port inputs to a logic "1"
state with a maximum hold current of 300 p.A.

(Ao and A,) Group A and Group B Controls

Port Select 0 and ~rt Select 1. These input signals, in The functional configuration of each port is programmed by
conjunction with the RD and WR inputs, control the selection the systems software. In essence, the CPU "outputs" a control
of one of the three ports or the control word registers. They are word to the 82C55A. The control word contains information
normally connected to the least significant bits of the address such as "mode", "bit set", "bit reset", etc., that initializes the
bus (Ao and A,). functional configuration of the 82C55A.
Each of the Control blocks (Group A and Group B) accepts
"commands" from the Read/Write Control Logic, receives
"control words" from the internal data bus and issues the
proper commands to its associated ports.
Control Group A- Port A and Port C upper (C7-C4)

•..
A, RD WR
, CS INPUT OPERATION (READ) Control Group B - Port B and Port Clower (C3-CO)
0 0
, 0
, 0 PORT A~ DATA BUS

,
0 0
, 0 PORT EHoDATABUS
The control word register can be both written and read as
, , 0 0
0 , 0
0
PORT C-+DATA
CONTROL
BUS
WORO .• OATA BUS
shown in the "Basic Operation" table. Figure 4 shows the
OUTPUT OPERATION control word format for both Read and Write operations. When
, (WRITE) the control word is read, bit D7 will always be a logic "1", as this
0
, , 0 0 0 DATA 8US-tPORT A implies control word mode information.
,
0
, 0 0 DATA BUS •• PORT B
Ports A, Band C
, , , 0 0
0
0
0
DATA 8US-tPORT
DATA BUS .• CONTROL
C

The 82C55A contains three 8-bit ports (A, B, and C). All can be
X X X X , DISABLE FUNCTION
DATA BUS .• 3·STATE
configured to a wide variety of functional characteristics by the
X X , , 0 DATA BUS43-STATE
system software but each has its own special features or
"personality" to further enhance the power and flexibility olthe
82C55A.
Port A One 8-bit data output latch/buffer and one 8-bit data
input latch. Both "pull-up" and "pull-down" bus-hold
devices are present on Port A.
Port BOne 8-bit data input/output latch/buffer and one 8-bit
data input buffer.

Port COne 8-bit data output latch/buffer and one 8-bit data
input buffer (no latch for input). This port can be
divided into two 4-bit ports under the mode control.
Each 4-bit port contains a 4-bit latch and it can be
used for the control signal outputs and status signal
inputs in conjun<:tion with ports A and B.

MODE 1

~o
P8"PBo
!!lI
CONTROL
1111
CONTROL
~o
PA,·'Ao
OR I/O OR I/O

C
MODE 2

~o !! 1 ! 11 11 ~I'DIRECTIONAL

1'8,"80 110 L' -00-'-+"-' O-L~' PA,'PAo

Figure 3
Baalc Mode Dellnltlona
and Bus Interface

Figure 2
82C55A Block Diagram Showing Group A
and Group B Control Functions

Mode Selection
There are three basic modes of operation that can be selected
by the system software:
Mode 0 - Basic Input/Output
Mode 1 - Strobed Input/Output
Mode 2 - Bi-Directional Bus
When the reset input goes "high", all ports will be set to the
input mode with all 24 port lines held at a logic "one" level by
internal bus hold devices. After the reset is removed, the
82C55A can remain in the input mode with no additional
initialization required. This eliminates the need for pullup or
pulldown resistors in all-CMOS designs. During the execution
of the system program, any of the other modes may be
selected using a single output instruction. This allows a single
82C55A to service a variety of peripheral devices with a
simple software maintenance routine. MODE SELECTION
00- MODE 0
The modes for Port A and Port B can be separately defined, 01-MOO£ \
l)(-MOOE 2
while Port C is divided into two portions as required by the Port
A and Port B definitions. All of the output registers, including
the status flip-flops, will be reset whenever the mode is
changed. Modes may be combined so that their functional
definition can be "tailored" to almost any I/O structure. For
instance: Group B can be programmed in Mode 0 to monitor
simple switch closings or display computational results, Group
A could be programmed in Mode 1 to monitor a keyboard or
tape reader on an interrupt-driven basis.
The mode definitions and possible mode combinations may support almost any peripheral device with no external logic.
seem confusing at first but after a cursory review of the Such design represents the maximum use of the available
complete device operation a simple, logical I/O approach will pins.
surface. The design of the 82C55A has taken into account
fhings such as efficient PC board layout, control signal
Single Bit SetiReaet Feature
definition vs PC layout and complete functional flexibility to
Any of the eight bits of Port C can be Set or Reset using a
single OUTput instruction. This feature reduces software
requirements in control·based applications.
When Port C is being used as status/control for Port A or B,
these bits can be set or reset by using the Bit Set/Reset
operation just as if they were data output ports.

Interrupt Control Functions

When the 82C55A is programmed to operate in mode 1 or
mode 2, control signals are provided that can be used as
interrupt request inputs to the CPU. The interrupt request
BIT SELECT signals, generated from port C, can be inhibited or enabled by
012341517 setting or resetting the associated INTE f1ip·f1op, using the bit
o , 0 1 0 1 01
set/reset function of port C.
00,,00',B
Oooo""B This function allows the programmer to enable or disable a
CPU interrupt by a specific I/O device without affecting any
other device in the interrupt structure.

INTE fUp-flop definition:

(BIT·SET)-INTE is SET - Interrupt enable

(BIT·RESET)-INTE is RESET - Interrupt disable.
Note: All Mask f1ip·f1ops are automatically reset during mode
selection and device Reset.

Operating Modea Mode 0 Basic Functional Definitions:

Mode 0 (Basic Input/Output). This functional configuration • Two 8·bit ports and two 4·bit ports
provides simple input and output operations for each of the • Any port can be input or output
three ports. No handshaking is required, data is simply written • Outputs are latched
to or read from a specific port. • Inputs are not latched
• 16 different Input/Output configurations possible

,,,-R-,..-f
R=~~- .....
::\
"O'=c--"'--~ ~--'-5=
e1,A' .•.0

-----------------------
I ~ ._--\li.-
x_-
 A B GROUPA GROUP B
PORT C PORT C
04 03 0, 00 PORTA /; PORT B
(UPPER) (LOWER)

0 0 0 0 OUTPUT OUTPUT 0 OUTPUT OUTPUT

0 0 0 1 OUTPUT OUTPUT 1 OUTPUT INPUT
0 0 1 0 OUTPUT OUTPUT 2 INPUT OUTPUT
0 0 1 1 OUTPUT OUTPUT 3 INPUT INPUT
0 1 0 0 OUTPUT INPUT 4 OUTPUT OUTPUT
0 1 0 1 OUTPUT INPUT 6 OUTPUT INPUT
0 1 1 0 OUTPUT INPUT 8 INPUT OUTPUT
0 1 1 1 OUTPUT INPUT 7 INPUT INPUT
1 0 0 0 INPUT OUTPUT 8 OUTPUT OUTPUT
1 0 0 1 INPUT OUTPUT 9 OUTPUT INPUT
1 0 1 0 INPUT OUTPUT 10 INPUT OUTPUT
1 0 1 1 INPUT OUTPUT 11 INPUT INPUT
1 1 0 0 INPUT INPUT 12 OUTPUT OUTPUT
1 1 0 1 INPUT INPUT 13 OUTPUT INPUT
1 1 1 0 INPUT INPUT 14 INPUT OUTPUT
1 1 1 1 INPUT INPUT 16 INPUT INPUT

CONTROL WOAD.O CONTROL WOAD _2

~ D. D, D. DS 0, D, DO D, D, D, 0. DS 0, 0, DO

A PA,·pAo A •
82C55A 82C55A
,
c{
~1tC7·PC.

C,.CO
Pes·pea
0,.°0
~{ ,
"".'., I
I

CONTROL WORD ., CONTROL WOAD .,

D, D, D, D. DJ DJ 0, DO 0, D, D, C. Ds D, [), Co

CEEEEEEEl
I ,I
A A

82C55A
, , 82C55A
,
. c{ . c{
i" i "
I
I
I •
CONTROL WORD #4 CONTROL WORD .s
0, D. 0, D. 0, 0, 0, D. 0, D. D. D. 0, 0, 0, D.

• . '

.
A PA7,PAo A ; 'A,"Ag

82C55A 82C55A
• '

07-00
c{ (

(
•
pc'-Pee

PeJ-PeO
07-00
c{ • pc"Pee

PeJ-PeO

B (
• PS,-PBO B • PB,.'a,

CONTROL WORD .-s CONTROL WORD #9

0, D. 0, D. 0, 0, 0, D. 0, D. 0, D. 0, 0, 0, D.

A
B
PA7-PAo A
,.
; PA7.f1Ao

82C55A 82C55A
• •
07-00 •
c{ (

(
•
Pe7-Pee

PeJ-Peg
0,-00
c{ •
pc'-I'C.

PeJ,PeO

B • P87-PBg B • PB,.•••

CONTROL WORD #tj CONTROL WORD #10

0, D. 0, D. 0, 0, 0, D. 0; D. 0, D. 0, 0, 0, D.

A • PA,-'Ao A --f!-- PA7-PAc.

82C55A 82C55A
• •
0,-00
c{ •
Pe,-Pee

Pe)'PCO
0,-00
c{ •
Pe7-PC.•

PC3-PCO

B • ---;..L- Pa -PB
7 g B • PB,.'a,

CONTROL WORD 117 CONTROL WORD .11

0, D. 0, D. OJ 0, 0, D. 0, D. 0, D. 0, 0, 0, D.

A
B
PA7·'Ao A • 'A,"Ag

82C55A 82C55A
• •
°7,°0 c{ •
Pe7-Pee

pcJ.pc,
°7,00 c{ •
PC,-PCe

PC3·PCO

• • PB,.'a, B
•B
PB,.•••
 CONTtI'tOLWOtl'tO.12 CONTROL WORD llI:'4

0, 0, 0, 04 0, 02 0, DO 0, O. D, 04 0, O~ 0, 00

• •

, .
82C88A
A

c{
•
82CIIA

c{
A

i
( .
,• •
• ,• • •

CONTAOL WOAo'13 CONTROL WORO'"

o.,O.Dt°40JOaO,Oo 0, 0, 0, 04 0, 0, 0, 00

A • A •
82CIIA 82CIIA
• •
c{ •
c{ •
• • • •

Operating Model Mode 1 Basic Functional Definitions:

Mode 1 (Strobed InpuVOutput). This functional configuration • Two Groups (Group A and Group B)
provides a means for transferring I/O data to or from a • Each group contains one B-bit port and one 4-bit
specified port in conjunction with strobes or "handshaking" control/data port.
signals. In mode 1. port A and port B use the lines on port C to • The B-bit data port can be either input or output. Both
generate or accept these "handshaking" signals. inputs and outputs are latched.
• The 4-bit port is used for control and status of the S-bit
port.
Input Control Signal Definition
STB (Strobe Input)
A "low" on this input loads data into the input latch.

IBF (Input Buffer Full F/F)

A "high" on this output indicates that the data has been loaded
into the input latch; in essence, an acknowledgement. IBF is
~t by STB input being low and is reset by the rising edge of the
RD input.

INTR (Interrupt Request)

A "high"on this output can be used to interrupt the CPU when

an input device is requesting service. INTR is set by the condition;
STBis a "one", IBF is a "one" and INTE is a "one". It is reset
by the falling edge of RD. This procedure allows an input
device to request service from the CPU by simply strobing its
data into the port.
INTEA

Controlled by bit seVreset of PC,.

INTEB

Controlled by bit seVreset of PC2.

OUTPUT CONTROL SIGNAL DEFINITION
OBF (Output Buffer Full F/F). The OBF output will go "low" to
indicate that the CPU has written data out to the specified
port. The OBF F/F.:!!ill be set by the rising edge of the WR
input and reset by ACK Input being low.
ACK (Acknowledge Input). A "low" on this input informs the
82C55A that the data from port A or port B has been accepted.
In essence, a response from the peripheral device indicating
that it has received the data output by the CPU.
INTR (Interrupt Request). A "high" on this output can be used
to interruptthe CPU when an output device has accepted data
transmitted by the CPU. INTR is set when ACK is a "one", OBF
is a "one" and INTE is a "one". It is reset by the falling edge of
WR.

INTEA
Controlled by Bit Set/Reset of CS2.

INTEB
Controlled by Bit Set/Reset of PCB.
 Combinations of MODE 1: Port A and Port B can be individually defined as Input or output In Mode 1 to support a wide variety of
strobed I/O applications.

CONTIIIOL WOIIID CONTIIIOL WOIllD

0, 0, 0, 0. 0, 0, -0, Do 0, D, Dt at 0, 0, 0, 00

1'1 1,1,1':1,1 0
0 0 1,101, 101,[,1, D<I
LIlC,., 1IC4,1

l-INI'UT
1-IN"UT
O-OUT'UT O-OUT..uT

Operating Modes
MODE 2 (Strobed Bidirectional Bus I/O) Output Operations
The functional configuration provides a means for com- OBF (Output Buffer Full). The ~ output will go "low" to
municating with a peripheral device or structure on a single indicate that the CPU has written data out to port A.
8-bit bus for both transmitting and receiving data (bidirectional ACK (Acknowledge). A "low" on this Input enables the tri-state
bus I/O). "Handshaking" signals are provided to maintain output buffer of port A to send out the data. Otherwise, the
proper bus flow discipline similar to MODE 1. Interrupt
output buffer will be in the high Impedance state.
generation and enable/disable functions are also available.
INTE 1 (The INTE Flip-Flop Associated with OBF). Controlled
MODE 2 Basic Functional Definitions: by bit set/reset of pce.
• Used in Group A only. Input Operations
• One 8-blt, bi-directional bus Port (Port A) and as-bit
control Port (Port C). STB (Strobe Input). A "low" on this input loads data into the
• Both inputs and outputs are latched. input latch.
• The S-bit control port (Port C) is used for control and IBF (Input Buffer Full F/F). A "high" on this output indicates
status for the 8-bit, bi-directional bus port (Port A). that data has been loaded into the Input latch.
Bidirectional Bus I/O Control Signal Definition INTE 2 (The INTE Flip-Flop Associated with IBF). Controlled
by bit set/reset of PC4.
INTR (Interrupt Reguest). A high on this output can be used to
interrupt the CPU for both input or output operations.
A DATA FROM
CPU TO 82C55A
CONTIIOL WOIIO CQNTIIOL WORD

rXMXt: I:31
0, O. 0. D. OJ D. 0, DO

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 --
MOOE 0 MODE' MODE 2
IN OUT IN OUT OAOUPA ONLY

--
PAO IN OUT IN OUT

-
PAl IN OUT IN OUT
IN OUT IN

-
PA2 OUT

-
PA3 IN OUT IN OUT

-
PA4 IN OUT IN OUT
PAe IN OUT IN OUT
PAE IN OUT IN OUT
PA7 IN OUT IN OUT

--
l
PBO IN OUT IN OUT
PB, IN OUT IN OUT --
PB2 IN OUT IN OUT --
PB3 IN OUT IN OUT -- MODEO
--

J
PB4 IN OUT IN OUT OR MODE'
PBe IN OUT IN OUT -- ONLY
PBe IN OUT IN OUT --
PB7 I IN OUT IN OUT --
PCo IN OUT INTRB 1NTRe I/O
PC, IN OUT IBFB WB I/O
PC2 IN OUT mB ACKB I/O
PC3 IN OUT INTRA INTRA INTRA
PC4 IN OUT MA I/O mA
PCe IN OUT IBFA I/O IBFA
PCe IN OUT I/O ACKA ACKA
PC7 IN I OUT I/O 6iiF A OBFA

Special Mode Combination Considerations:

There are several combinations of modes possible. For any status. The remaining bits are either inputs or outputs as
combination, some or all of Port C lines are used for control or defined by a "Set Mode" command.

Duri~ read of Port C, the state of all the Port C lines, except
IN,.UT CONFIOUJlATlON the ACR and SfB lines, will be placed on the data bus. In place
OJ 0, 0, o~ 0, 01 0, Do of the ACK and STB line states, flag status will appear on the
data bus in the PC2, PC4, and PCG bit positions as illustrated
by Figure 17.
Through a "Write Port C" command, only the Port C pins
OUTPUT CONFIGURATION

0, ~ ~ ~ 0, 02 0, 00
programmed as outputs in a Mode 0 group can be written. No

EB Il~ 110 i'NTA~

other pins can be affected by a "Write Port Coocommand, nor
can the interrupt enable flags be accessed. To write to any Port
C output programmed as an output in a Mode 1 group or to
change an interrupt enable flag, the "Set/Reset Port C Bit"
command must be used.
With a "Set/Reset Port C Bit" command, any Port Cline
programmed as an output (including INTR, IBF and OBF) can
01 0, Os D. 0, 02 0, Do
be written, or an interrupt enable flag can be either set or
reset. Port C lines programmed as inputs, including ACK and
\----. _ _--'~ __ ---.-. _ ..J

GROUP A __ --- CiROUp B

STB lines, associated with Port C are not affected by a
"Set/Reset Port C Bit" command. Writln£i!Q.the corresponding
(OEFINEO B" MODE 0 OR MOOE 1 SELECTION}
Port C bit positions of the ACK and STB lines with the
"Set/Reset Port C Bit" command will affect the Group A and
Group B interrupt enable flags, as illustrated in Figure 17.
 Interrupt Enable Flag" Position Alternate Port C Pin Signal (Mode)

INTEB PC2 ACKB (Output Mode 1) or mB (Input Mode 1)

INTEA2 PC4 STBA (Input Mode 1 or Mode 2)

INTE A1 PC6 ACKA (Output Mode 1 or Mode 2)

device. When the 82C55A is programmed to function in

Current Drive Capability:
Modes 1 or 2, Port C generates or accepts "hand-shaking"
Any output on Port A, B or C can sink or source 2.5mA. This signals with the peripheral device. Reading the contents of
feature allows the 82C55A to directly drive Darlington type Port C allows the programmer to test or verify the "status" of
drivers and high-voltage displays that require such sink or each peripheral device and change the program flow accord-
source current. ingly.

Reading Port C Status There is no special instruction to read the status information
from Port C. A normal read operation of Port C is executed to
In Mode 0, Port C transfers data to or from the peripheral perform this function.

I'CJ ••••

",
APPLICATIONS OF THE 82C55A ",
",
...
M,
The 82C55AI is a very powerful tool for interfacing peripheral
equipment to the microcomputer system. It represents the
optimum use of available pins and is flexible enough to
I=~l'-" ",
interface almost any I/O device without the need for additional DATA

"C.
READY

external logic. ' .•.••(IIH£O

FORWAROIAEV
Each peripheral device in a microcomputer system usually B2C55
..
•••
A

j ......
has a "service routine" associated with it. The routine ,
manages the software interface between the device and the ,
CPU. The functional definition of the 82C55A is programmed by , 0 •••, .•. 11£0\0'1'
, ."
the I/O service routine and becomes an extension of the
..
MOO" ''''"RFHo
lOUT"UTI ::
system software. By examining the I/O devices interface ,
FORWARO/R(V

RI88O/11

characteristics for both data transfer and timing, and matching CARRIAG£SEIOt

this information to the examples and tables in the detailed '<,

'<,
operational description, a control word can easily be de-
veloped to initialize the 82C55A to exactly "fit" the application.
Figures 19 through 25 present a few examples of typical
applications of the 82C55A.
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Supply Voltage +8.0 VOLTS Operating Temperature Range
Operating Voltage Range +4Vto +7V Commercial OOC to +700C
Input Voltage Applied GND-2.0V to 6.5V Industrial -40°C to +85°C
I/O Pin Voltage Applied GND-0.5V to VCC+0.5V Military -55°C to +125°C
Storage Temperature Range -65°C to + 150°C Maximum Power Dissipation 1 Watt

CAUTION: Stresses above those listed inthe "ABSOLUTE MAXIMUM RATINGS" maycause permanent damage lothe device. This is a stress only
rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied.

D.C. ELECTRICAL CHARACTERISTICS

VCC = -5.0V+/-10%; T A = OOC to +700C (C82C55A); TA = -400C to +850C (I82C55A);
T A = -550C to +1250C (M82C55A)
SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS

VIH LOGICAL ONE 2.0 V 182C55A

INPUT VOLTAGE 2.2 V M82C55A
VIL LOGICAL ZERO 0.8 V
INPUT VOLTAGE
VOH LOGICAL ONE 3.0 V 10H ~ -2.5 mA
OUTPUT VOLTAGE VCC-O.4 V IOH~-100p.A
VOL LOGICAL ZERO 0.4 V IOL=+2.5 mA
OUTPUT VOLTAGE
ilL INPUT LEAKAGE -1.0 1.0 p.A OV",VIN"'VCC
CURRENT
10 I/O PIN LEAKAGE -10.0 10.0 p.A OV",VO",VCC
CURRENT
IBHH BUS HOLD HIGH -50 -300 p.A VO=3.0V
CURRENT PORTS A. B. C
IBHL BUS HOLD LOW +50 +300 p.A VO=1.0V
CURRENT PORT A ONLY
IDAR DARLINGTON DRIVE -2.0 mA PORTS A. B. C
CURRENT Test Condition 3
ICC POWER 10 p.A VCC=5.5V
SUPPLY CURRENT VIN=VCC or GND
OUTPUTS OPEN

SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS

CIN" INPUT 5 pi FREQ = 1 MHZ

CAPACITANCE Unmeasured pins
returned to GND
CliO· I/O PIN 20 pi
CAPACITANCE
A.C. CHARACTERISTICS VCC = +5V ±10%, GND = OV; TA = OOC to +700C (C82C55A)
VCC = +5V ±10%, GND = OV; TA = -400C to +850C (I82C55A)
VCC = +5V ±10%, GND = OV; TA = -550C to +1250C (M82C55A)
Bus Parameters
READ I82C55A M82C55A TEST
SYMBOL PARAMETER MIN MAX MIN MAX UNITS CONDITIONS

tAR Address Stable Before READ 0 0 ns

tRA Address Stable After READ 0 0 ns
tRR READ Pulse Width 150 150 ns
tRD Data Valid From READ 100 100 ns 1
tDF Data Float After READ 10 75 10 75 ns 2
tRY Time Between READs 300 300 ns
and/or WRITEs

WRITE I 82C55A M82C55A TEST

SYMBOL PARAMETER MIN MAX MIN MAX UNITS CONDITIONS
tAW Address Stable Before WRITE 0 0 ns
tWA Address Stable After WA ITE 20 20 ns Ports A & B
60 eo ns Port C

tWW WRITE Pulse Width 100 100 ns

tOW Data Valid to WR ITE High 100 100 ns
tWO Data Valid After WRITE High 30 30 ns Ports A & B
60 eo ns Port C

OTHER TIMINGS 182C55A M82C55A TEST

SYMBOL PARAMETER MIN MAX MIN MAX UNITS CONDITIONS
twe WR ::: 1 to Output 350 350 ns 1
tlR Peripheral Data Before AD 0 0 ns
tHR Peripheral Data After RD 0 0 ns
tAK ACK Pulse Width 100 100 ns
tST STB Pulse Width 100 100 ns
tPS Per. Data Before STB High 20 20 ns
tPH Per. Data After STB High 50 50 ns
tAD ACK:: 0 to Output 175 175 ns 1
tKD AC K = 1 to Output Float 20 250 20 250 ns 2
tWOB WR = 1 to OBF = 0 150 150 ns 1
tAOe ACK:: 0 to OBF a= 1 150 150 ns 1
tSIB STB=OtoIBF=l 150 150 ns 1
tAIS RD=ltoIBF:::Q 150 150 ns 1
tRIT RD=OtoINTR=O 200 200 ns 1
tSIT STB= 1 to INTR = 1 150 150 ns 1
tAIT ACK = 1 to INTR = 1 150 150 ns 1
tWIT WR=OtoINTR=O 200 200 ns 1
tRES Reset Pulse Width 500 500 ns see note 1

FROM OUTPUT
UNDER TEST
C1*

I *1ncludes stray and

jig capacitance

TEST CONDITION Vl Rl R2 Cl
1 1.7V 5230 OPEN 150 pI
2 5.0V 2KO 1.7KO 50 pI
3 1.5V 7500 OPEN OPEN
 DATAP_

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;II HARRIS CMOS PROGRAMMABLE
82C59A
INTERRUPT CONTROLLER

Features
• PIN COMPATIBLE WITH NMOS 8259A
• EIQHT LEVEL PRIORITY CONTROLLER
• EXPANDABLE TO 84 LEVELS Ci vee
• FULLY TTL COMPATIBLE
\iIii ,..
• HIQH SPEED, NO "WAIT STATE" OPERATION WITH 8 MHz BOCBB
• PROQRAMMABLE INTERRUPT MODES iiii iNf.'A
• 8080/8085 Ind 8088/8OC88 COMPATIBLE OPERATION I),
IAT
• INDIVIDUAL REQUEST MASK CAPABILITY
D, IAI
• FULLY STATIC DESIQN
• SCALED SAJI IV CMOS PROCESS I), IAI
• SINQLE 5V POWER SUPPLY
D. IA4
• LOW STANDBY POWER -10pA
• COMMERCIAL, INDUSTRIAL Ind MILITARY TEMPERATURE RANQES D, IAI

D, IAI
Description D, IA1
The Harris 82C59A Is a high performance CMOS Priority Interrupt Controller manufactured using a D, lAD
self-aligned silicon gate CMOS process (Scaled SAJI IV). The 82C59A'ls designed to relieve the
system CPU from the task of polling In a multi-level priority Interrupt system. The high speed and CAlD INT
Industry standard configuration of the 82C59A make It compatible with microprocessors such as the CAS 1 8PfEN
80C86, 8086, 8080/85 and NSC800.
DND CAS I
The 82C59A can handle up to eight vectored priority Interrupting sources and Is cascadable to 64
without additional circuitry. Individual Interrupting sources can be masked or prioritized to allow
custom system configuration. Two modes of operation make the 82C59A compatible with both
8080/85 and 80C86/86 formats.
Static CMOS circuit design Insures low operating power. Harris advanced SAJI process results In
performance equal to or greater than existing equivalent products at a fraction of the power.

0,-0. DATA BUS (BI·DIRECTIONAl)

1m READ INPUT
WR WRITE INPUT
AD COMMAND SELECT ADDRESS
CS CHIP SELECT
CAS2·CASO CASCADE LINES
SP/EN SLAVE PROGRAM INPUT ENABLE
INT INTERRUPT OUTPUT
mTA INTERRUPT ACKNOWLEDGE INPUT
IRO -IR? INTERRUPT REQUEST INPUTS
 SYMBOL PIN NO. TYPE NAME AND FUNCTION
Vcc 28 I POWER SUPPLY: + 5V Supply.
GND 14 I GROUND.
ES 1 I CHIP SELECT: A low on this pin enables RD alli!'WR communication between the CPU and the
82C59A. INTA functions are independent of CS.
WR 2 WRITE: A low on this pin when CS is low enables the 82C59A to accept command words from the
CPU.
RD 3 READ: A low on this pin when CS Is low enables the 82C59A to release status onto the data bus for
the CPU.
0,-00 4-11 BIDIRECTIONAL DATA BUS: Control, status and Interrupt-vector information Is transferred via
this bus.
CAS 0- CAS 2 12. 13, 15 CASCADE LINES: The CAS lines form a private 82C59A bus to control a multiple 82C59A
structure. These pins are outputs for a master 82C59A and inputs for a slave 82C59A.
SP/EN 16 SLAVE PROGRAM/ENABLE BUFFER: This Is a dual function pin. When in the Buffered Mode itcan
be used as an output to control buffer transceivers (EN). When not in the buffered mode it is used
as an input to designate a master (SP=1) or slave (SP=O).
INT 17 INTERRUPT: This pin goes high whenever a valid interrupt request is asserted. It is used to
interrupt the CPU, thus It is connected to the CPU's interrupt pin.
IRO-IR7 18-25 INTERRUPT REQUESTS: Asynchronous inputs. An interrupt request is executed by raising an IR
input (iowto high), and holding it high until it is acknowledged (Edge Triggered Mode), or just by
a high level on an IR input (level Triggered Mode),
INTA 26 INTERRUPT ACKNOWLEDGE: This pin is used to enable 82C59A interrupt-vector data onto the
data bus by a sequence of interrupt acknowledge pulses issued by the CPU.
Ao 27 ADDRESS LINE: This pin acts in conjunction with the CS, WR, and RD pins, It is used by the
82C59A to decipher various Command Words the CPU writes and status the CPU wishes to read.
It is typically connected to the CPU Ao address line (A1for 80C86/88).

FuncffonalDescripffon
INTERRUPTS IN MICROCOMPUTER SYSTEMS complete, however, the processor would resume exactly where it left
off.
Microcomputer system design requires that I/O devices such as
keyboards, displays, sensors and other components receive This is the interrupt-driven method. It is easy to see that system
servicing in an efficient manner so that large amounts of the total through put would drastically increase, and thus more tasks could be
system tasks can be assumed by the microcomputer with little or no assumed by the microcomputer to further enhance its cost effective-
effect on throughput. ness.

The most common method of servicing such devices is the Polled The Programmable Interrupt Controller (PIC) functions as an overall
approach. This is where the processor must test each device in manager in an Interrupt-Driven system. It accepts requests from the
sequence and in effect "ask" each one if it needs servicing. It is easy peripherai equipment, determines which of the incoming requests is
to see that a large portion of the main program is looping through this of the highest importance (priority), ascertains whether the
continuous polling cycle and that such a method would have a incoming request has a higher priority value than the level currently
serious, detrimental effect on system through-put, thus limiting the being serviced, and issues an interrupt to the CPU based on this
tasks that could be assumed by the microcomputer and reducing the determination.
cost effectiveness of using such devices.
Each peripheral device or structure usually has a special program or
A more desirable method would be one that would allow the "routine" that is associated with its specific functional or operational
microprocessor to be executing its main program and only stop to requirements; this is referred to as a "service routine". The PIC, after
service peripheral devices when it is told to do so by the device itself. issuing an interrupt to the CPU, must somehow input information
In effect, the method would provide an external asynchronous Input into the CPU that can "point" the Program Counter to the service
that would inform the processor that it should complete whatever routine associated with the requesting device. This "pointer" is an
instruction that is currently being executed and fetch a new routine address in a vectoring table and will often be referred to, in this
that will service the requesting device. Once this servicing is document, as vectoring data.
 illi
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interrupt structure can be defined as required, based on the total

system environment.
The 82C59A is a device specifically designed for use in real time,
interrupt driven microcomputer systems. It manages eight levels of INTERRUPT REQUEST REGISTER (IRR) and
requests and has built-in features for expandability to other 82C59As IN-SERVICE REGISTER (ISR)
(up to 64 levels). It is programmed by system software as an 110
peripheral. A selection of priority modes is available to the The interrupts at the IR input lines are handled by two registers in
programmer so that the manner in which the requests are processed cascade, the Interrupt Request Register (IRR) and the In-Service
by the 82C59A can be configured to match system requirements. The Register (ISR). The IRR is used to store all the interrupt levels which
priority modes can be changed or reconfigured dynamically at any are requesting service, and the ISR is used to store all the interrupt
time during main program operation. This means that the complete levels which are currently being serviced.
 READ (RD)
A LOW on this input enables the 82C59A to send the status of the
Interrupt Request Register (IRR), In Service Register (ISR), the
Interrupt Mask Register (IMR), or the interrupt level (in the poll
1T)0de) onto the Data Bus.

A.
This input signal is used in conjunction with WR and RD signais to
write commands into the various command registers, as well as
reading the various status registers of the chip. This line can be tied
directly to one of the address lines.

This function block stores and compares the IDs of all 82C59As used
in the system. The associated three I/O pins (CASO-2) are outputs
I when the 82C59A is used as a master and are inputs when the
INTERRUPT
REQUESTS 82C59A is used as a slave. As a master, the 82C59A sends the 10 of
the interrupting slave device onto the CASO-2 lines. The slave thus
selected will send its preprogrammed subroutine address onto the
Data Bus during the next one or two consecutive INTA pulses. (See
section "Cascading the 82C59A".)

This logic block determines the priorities of the bits set in the IRR.
The highest priority is selected and strobed into the corresponding
bit of the ISR during the INTA sequence. The powerful features of the 82C59A in a microcomputer system are
its programmability and the interrupt routine addressing capability.
INTERRUPT MASK REGISTER (IMR) The latter allows direct or indirect jumping to the specified interrupt
routine requested without any polling of the interrupting devices. The
The IMR stores the bits which disable the interrupt lines to be normal sequence of events during an interrupt depends on the type of
masked. The IMR operates on the output of the IRR. Masking of CPU being used.
a higher priority input will not affect the interrupt request lines
of lower priority. These events occur in an 8080Al8085 system:
1. One or more of the INTERRUPT REQUEST lines (10-17) are raised
high, setting the corresponding IRR bit(s).
2. The 82C59A evaluates these requests in the priority resolver and
This output goes directly to the CPU interrupt input. The VOH level on sends an interrupt (INT) to the CPU, if appropriate._
this line is designed to be fully compatible with the 8080A, 8085A. 3. The CPU acknowledjjM.the INTand responds with an INTA pulse.
8086 and 80C86 input levels. 4. Upon receiving an INTA from the CPU group. the highest priority
ISR bit is set, and the corresponding IRR bit is reset. The 82C59A
INTERRUPT ACKNOWLEDGE (INTA) will also release a CALL instruction code (11001101) onto the
8-bit data bus through 0.-0,.
INTA pulses will cause the 82C59A to release vectoring information 5. This CALL instruction will initiate two additional iNTA pulses to be
onto the data bus. The format of this data depends on the system sent to the 82C59A from the CPU group.
mode (J.LPM)of the 82C59A. 6. These two INTA pulses allow the 82C59A to release its prepro-
grammed subroutine address onto the data bus. The lower 8-bit
address is released at the first INTA pulse and the higher 8-bit
address is released at the second INTA pulse.
This 3-state. bidirectional8-bit buffer is used to interface the 82C59A 7. This completes the 3-byte CALL instruction released by the
to the system Data 8us. Control words and status information are 82C59A. In the AEOI mode, the ISR bit is reset at the end of the
transferred through the Data Bus Buffer. third INTA pulse. Otherwise, the ISR bit remains set until an
appropriate EOI command is issued at the end of the interrupt
sequence.
The events occurring in an 80C86 system are the same until step 4.
The function of this block is to accept OUTput commands from the
CPU. It contains the Initialization Command Word (ICW) registers 4. Upon receiving an INTA from the CPU group, the highest priority
and Operation Command Word (OCW) registers which store the ISR bit is set and the corresponding IRR bit is reset. The 82C59A
various control formats for device operation. This function block also does not drive the data bus durirlgthis cycle.
allows the status of the 82C59A to be transferred onto the Data Bus. 5. The 80C86 will initiate a second mTA pulse. During this pulse, the
82C59A releases an 8-bit pointer onto the data bus where it is read
by the CPU.
6. This completes the interrupt cyf!L!n the AEOI mode, the ISR bit
A LOW on this input enables the 82C59A. No reading or writing of the is reset at the end of the second INTA pulse. Otherwise, the ISR bit
device will occur unless the device is selected. remains set until an appropriate EOI command is issued at the end
of the interrupt subroutine.
If no interrupt request is present at step 4 of either sequence (i .e.,the
request was too short in duration). the 82C59A will issue an interrupt
A LOW on this input enables the CPU to write control words (ICWs level 7. If a slave is programmed on IR bit 7, the CAS lines remain
and OCWs) to the 82C59A. inactive and vector addresses are output from the master 82C59A.
8080,8085 Content of Third Interrupt Vector Byte

This sequence is timed by three INTA pulses. During the first INTA D7 D6 D5 D4 D3 D2 D1 DO
pulse, the CALL opcode is enabled onto the data bus. A15 A14 A13 A12 A11 A10 A9 A8
First Interrupt Vector Byte Data: Hex CD
80C86, 80C88 INTERRUPT RESPONSE MODE
D7 D6 D5 D4 D3 D2
80C86 mode is similar to 8080/85 mode except that only two
CALL CDDE 1 1 0 0 1 1 Interrupt Acknowledge cycles are issued by the processor and no
CALL opcode is sent to the processor. The first Interrupt
During the second INTA pulse, the lower address of the appropriate acknowledge cycle is similar to that of 8080/85 systems In that
service routine is enabled onto the data bus. When interval = 4 bits, the 82C59A uses it to internally freeze the state of the Interrupts
A,-A, are programmed, while Ao-A. are automatically inserted by the for priority resolution and, as a master, it issues the interrupt
82C59A. When interval = 8, only A. and A, are programmed, while code on the cascade lines. On this first cycle, it does not issue
Ao-A, are automatically inserted. any data to the processor and leaves its data bus buffers disabled.
On the second interrupt acknowledge cycle in 80C86 mode, the
master (or slave if so programmed) will send a byte of data to the
Content of Second Interrupt Vector Byte processor with the acknowledged interrupt code composed as
Interval = 4 follows (note the state of the ADI mode control is ignored and
As-A" are unused in 80C86 mode.)
D7 D6 D5 D4 D3 D2 D1
A7 A6 A5 1 1 1 0 Content of Interrupt
A7 A6 A5 1 100 Vector Byte for BOCB6 System Mode
A7 A6 A5 1 010 D7 D6 D5 D4 D3 D2 D1 DO
A7 A6 A5 1 000 IR7 T7 T6 T5 T4 T3 1 1 1
A7 A6 A5 0 1 1 0 IR6 T7 T6 T5 T4 T3 1 1 0
A7 A6 A5 0 100 IR5 T7 T6 T5 T4 T3 1 0 1
A7 A6 A5 0 010 IR4 T7 T6 T5 T4 T3 1 0 0
A7 A6 A5 0 000 IR3 T7 T6 T5 T4 T3 0 1 1
IR2 T7 T6 T5 T4 T3 0 1 0
Interval = 8 IR1 T7 T6 T5 T4 T3 0 0 1
D7 D6 D5 D4 D3 D2 D1 IRO T7 T6 T5 T4 T3 0 0 0
A7 A6 1 1 100
A7 A6 1 1 000 PROGRAMMING THE 82C59A
A7 A6 1 0 100
The 82C59A accepts two types of command words generated by the
A7 A6 1 0 000
CPU;
A7 A6 0 1 100
1. Initialization Command Words (ICWs): Before normal operation
A7 A6 0 1 000
can begin, each 82C59A in the system must be brought to a
A7 A6 0 0 1 0 0 starting point-by a sequence of 2 to 4 bytes timed by WR pulses.
A7 A6 0 0 000 2. Operation Command Words (OCWs): These are the command
words which command the 82C59A to operate in various interrupt
modes. Among these modes are:
During the third INTA pulse, the higher address of the appropriate a. Fully nested mode c. Special mask mode
service routine, which was programmed as byte 2 of the initialization b. Rotating priority mode d. Polled mode
sequence (A.-A,,). is enabled onto the bus. The OCWscan be written into the 82C59A anytime after initialization.

initialization, an interrupt request (IR) input must make a

low-to-high transition to generate an interrupt.
Whenever a command is issued with AO=O and D4=1, this is b. The Interrupt Mask Register is cleared.
interpreted as Initialization Command Word 1 (ICW1). ICW1 starts c. IR7 input is assigned priority 7.
the initialization sequence during which the following automatically d. Special Mask Mode is cleared and Status Read is set to IRR.
occur.
e. If IC4=O, then all functions selected in ICW4 are set to zero.
a. The edge sense circuit is reset, which means that following (Non-Buffered mode', no Auto-EOI, 8080/85 system).
 ICWl
INITIALIZATION COMMAND WORDS 1 and 2 A, 0, 0. D. D. D. D. 0.
(ICW1, ICW2)
A,-A ••: Page starting address of service routines. In an 8080/85
system, the 8 request levels will generate CALLS to 8 locations '-ICW4NEEDED

equally spaced in memory. These can be programmed to be spaced at 0 •. NO ICW4NEEOEO

intervals of 4 or 8 memory locations. thus the 8 routines will occupy a

page of 32 or 64 bytes, respectively. 1 •• SINGLE
o •. CASCADE MOOE

The address format is 2 bytes long (AD-A••). When the routine interval
is 4. AD-A.are automatically inserted by the 82C59A. while A,-A •• are CAU ADDRESSINTENl
1 -INTERVALOf4
programmed externally. When the routine interval is 8, Ao·A, are o .. INTER\Io\lDFB

automatically inserted by the 82C59A while A6·A15are programmed

externally. 1"" lEVEL TRIGGERED MODE
0", EDGE TRIGGERED MODE
The 8-byte interval will maintain compatibility with current software.
while the 4-byte interval is best for a compact jump table.
A, - .•.• OF INTERRUPT
VECTOR ADDRESS
In an 80C86 system. A••. A" are inserted in the five most significant ICW2
(MCS-IClr8S MODE ONl't1

bits of the vectoring byte and the 82C59A sets the three least A, 0, D. D. 0, D. 0, 0, 0.
significant bits according to the interrupt level. AwA, are ignored and
ADI (Address interval) has no effect.
A,,-Ao Of INTERRUPT
LTIM: If LTIM = 1, then the 82C59A will operate in the level VECTOR ADDRESS

interrupt mode. Edge detect logic on the interrupt T~~~tIF~~~~~~~

VECTOAAOORESS
inputs will be disabled. 1808618088 MODEl

ADI: CALL address interval. ADI = 1 then interval = 4; ADI ICW3 (MASTER oeVICEJ

= a then interval = 8.
A, 0, 0. D. 0, 0, 0, D. 0.

SNGL: Single. Means that this is the only 82C59A in the CD>-
system. If SNGL=1. no ICW3 will be issued. co:
1 •• 1ft INPUT KAS A SLAVE t.>:;:
IC4: If this bit is set-ICW4 has to be issued. If ICW4 is not o •• 1ft INPUT
A SLAVE
ODES NOT HAVE §'l«
u..
needed, set IC4 = O.
ICW3jSLAVEDEVICE}

A, D. 0. D. D. 0, 0, D. D.

$LAVEIOCIi

2345
01 II 1
1 1 0 0
001 1

§lE 1
1
0
1
x- NOH BUfFERED MODE
~ BUFFEREDMQDEtSlAIIE
- BUffERED MODE/MASTER

,- SPECIAL fUUY NESTED

MODE
0 •• NOT SPECIAL FUUY
NESTED MODE

This word is read only when there is more than one 82C59A in the release bytes 2 and 3 (for 80C86. only byte 2) through the
system and cascading is used. in which case SNGL = O. It will load cascade lines.
the 8·bit slave register. The functions of this register are: b. In the slave mode (either when SP=O, or if BUF=1 and MlS=O
a. In the master mode (either when SP=1, or in buffered mode in ICW4). bits 2-0 identify the slave. The slave compares its
when M/S=1 in ICW4), a "1" is set for each slave in the bit cascade input with these bits and if they are equal, bytes 2 and
corresponding to the appropriate IR line for the slave. The 3 of the call sequence (or just byte 2 for 80C86) are released by
master then will release byte 1 of the call sequence (for it on the Data Bus (Note: the slave address must correspond to
8080/85 system) and will enable the corresponding slave to the IR line it is connected to in the master ID).
INITIALIZATION COMMANO WORO 4 (ICW4) OPERATION CONTROL WORDS (OCWs)
SFNM: If SFNM = 1,the special fully nested mode is pro- AO 07 06 05 04 03 02 01 DO
grammed.
OCW1
BUF: If BUF = 1, the..!l.ullired mode is programmed. In
buffered mode, SP/EN becomes an enable output and M7 M6 M5 M4 M3 M2 M1 MO
the masterlslave determination is by MIS. OCW2
MIS: If buffered mode is selected: MIS = 1 means the a R SL EOI a a L2 L1 La
82C59A is programmed to be a master, MIS = a means
the 82C59A is programmed to be a slave. If BUF = 0, OCW3
MIS has no function. a a ESMM SMM a P RR RIS
AEOI: If AEOI = 1, the automatic end of interrupt mode is
programmed.
iLPM: Microprocessor mode: iLPM = a sets the 82C59A for
8080/85 system operation, iLPM = 1 sets the OCW1 sets and clears the mask bits in the interrupt Mask Register
82C59A for 80C86 system operation. (I MR). M,-Mo represent the eight mask bits. M=1 indicates the
channel is masked (inhibited), M=O indicates the channel is enabled.

OPERATION CONTROL WORD 2 (OCW2)

After the initialization Command Words (ICWs) are programmed into
the 82C59A, the device is ready to accept interrupt requests at its R, SL, EOI- These three bits control the Rotate and End of Interrupt
input lines. However, during the 82C59A operation, a selection of modes and combinations of the two. A chart of these combinations
algorithms can command the 82C59A to operate in various modes can be found on the Operation Command Word Format.
through the Operation Command Words (OCWs).
L" L" Lo- These bits determine the interrupt level acted upon when
the SL bit is active.

IRUVEl TOlE
ACTED Uf'OfI
234 7
o , ,
,, , , ,,

NON·SPfClFICEOI COMMAND }-- END Of INTERRUPT

SPECIACEOlCDMMAND
ROTATE ON HON·SPECIRe EOI COMMAND
ROTATE IN AUTOMATIC Eol MODE (SET) ,}- AUTOMATIC ROTAnON
AOTAn IN AUTOMATIC Eol MODE (CLEAR)
* ROTATf OH SPECIFIC EOI COMMAND }-- SPeCIFIC ROTAnON
* SET PRIORITY COMMAND
NO OPERAnON

82C59A OPERATION COMMAND WORD FORMAT

3-68
OPERATION CONTROL WORO 3 (OCW3) wait, in the worst case until each of 7 other devices are serviced at
most once. For example, if the priority and "in service" status is:
ESMM - Enable Special Mask Mode. When this bit is set to 1 it
enables the SMM bit to set or reset the Special Mask Mode. When Before Rotate (IR4 the highest priority requiring service)
ESMM=O,the SMM bit becomes a "don't care".
IS7 IS6 IS5 IS4 IS3 IS2 IS1 ISO
SMM-Special Mask Mode. If ESMM=1 and SMM=1,the 82C59A "IS" STATUS 0 1 0 1 0 0 0 0
will enter Special Mask Mode. If ESMM=1 and SMM=O,the 82C59A
will revert to normal mask mode. When ESMM=O, SMM has no
effect.
PRIORITY 7.... 6 5 1 ,0
STATUS lowest "SO Zhighest

After Rotate (IR4 was serviced, all other priorities rotated corres-
pondingly)
This mode is entered after initialization unless another mode is
programmed. The interrupt requests are ordered in priority from 0 IS7 IS6 IS5 IS4 IS3 IS2 IS1 ISO
through 7 (0 highest). When an interrupt is acknowledged the "IS" STATUS 0 1 0 0 0 0 0 0
highest priority request is deterl)lined and its vector placed on the
bus. Additionally, a bit of the Interrupt Service register (ISO-7) is set. PRIORITY 2 1 0 7 6 5 4 3
This bit remains set until the microprocessor issues an End of STATUS highest=-::J It
Interrupt (EOI) command immediately before returning from the lowest
service routine, or if AEOI (Automatic End of Interrupt) bit is set, until
the trailing edge of the last 'INTA. While the IS bit is set, all further There are two ways to accomplish Automatic Rotation using OCW2,
interrupts of the same or lower priority are inhibited, while higher the Rotation on Non-Specific EOI Command (R=1, SL=O, EOI=1)
levels will generate an interrupt (which will be acknowledged only if and the Rotate in Automatic EOI Mode which is set by (R=1, SL=O,
the microprocessor internal interrupt enable flip-flop has been EOI=O) and cleared by (R=O, SL=O, EOI=O).
re-enabled through software).
After the initialization sequence, IROhas the highest priority and IR7 SPECIFIC ROTATION (Specific Priority)
the lowest. Priorities can be changed, as will be explained, in the
rotating priority mode or via the set priority command. The programmer can change priorities by programming the bottom
priority and thus fixing all other priorities; i.e., if IR5 is programmed
as the bottom priority device, then IR6 will have the highest one.
ENO OF INTERRUPT (EOI)
The Set Priority command is issued in OCW2 where: R= 1, SL= 1;
The In Service (IS) bit can be reset either automatically following the LO-L2 is the binary priority level code of the bottom priority device.
trailing edge of the last in sequence INTA pulse (when AEOI bit in
ICW1 is set) or by a command word that must be issued to the Observe that in this mode internal status is updated by software
82C59A before returning from a service routine (EOI Command). An control during OCW2. However, it is independent of the End of
EOI command must be issued twice if in the Cascade mode, once for Interrupt (EOI) command (also executed by OCW2). Priority changes
the master and once for the corresponding slave. can be executed during an EOI command by using the Rotate on
Specific EOI command in OCW2 (R=1, SL=1, EOI=1 and LO-
There are two forms of EOI command: Specific and Non-Specific. 12=IR level to receive bottom priority).
When the 82C59A is operated in modes which preserve the fully
nested structure, it can determine which IS billo reset on EOI. When
a Non-Specific EOIcommand is issued the 82C59A will automatically
reset the highest IS bit of those that are set, since in the fully nested Each Interrupt Request input can be masked individually by the
mode the highest IS level was necessarily the last level acknowledged Interrupt Mask Register (IMR) programmed through OCW1. Each bit
and serviced. A non-specific EOI can be issued with OCW2 (EOI=1, in the IMR masks one interrupt channei if it is set (1). Bit 0 masks
SL=O, R=O). IRO, Bit 1 masks IR1 and so forth. Masking an IR channel does not
When a mode is used which may disturb the fully nested structure, affect the other channels operation.
the 82C59A may no longer be able to determine the last level
acknowledged. In this case a Specific End of Interrupt must be issued
which includes as part of the command the IS level to be reset. A
specific EOI can be issued with OCW2 (EOI=1, SL=1, R=O, and Some applications may require an interrupt service routine to
LO-L2 is the binary level of the IS bit to be reset). dynamically alter the system priority structure during its execution
under software control. For example, the routine may wish to inhibit
An IRR bit that is masked by an IMR bit will not be cleared by a lower priority requests for a portion of its execution but enable some
non-specific EOI if the 82C59A is in the Special Mask Mode. of them for another portion.
The difficulty here is that if an Interrupt Request is acknowledged and
AUTOMATIC END OF INTERRUPT (AEOI) MODE an End of Interrupt command did not reset its IS bit (i .e., while
If AEOI = 1 in ICW4, then the 82C59A will operate in AEOI mode executing a service routine), the 82C59A would have inhibited all
continuously until reprogrammed by ICW4. In this mode the 82C59A lower priority requests with no easy way for the routine to enable
will automatically perform a non-specific EOI operation at the trailing them.
edge of the last interrupt acknowledge pulse (third pulse in That is where the Special Mask Mode comes in. In the special Mask
8080/85, second in 80C86). Note that from a system standpoint,
Mode, when a mask bit is set in OCW1, it inhibits further interrupts at
this mode should be used only when a nested multi-level interrupt that level and enables interrupts from all other levels (lower as well as
structure is not required within a single 82C59A. higher) that are not masked.
AUTOMATIC ROTATION (Equal Priority Devices) Thus, any interrupts may be seiectively enabled by loading the mask
register.
In some applications there are a number of interrupting devices of
equal priority. In this mode a device, after being serviced, receives The special Mask Mode is set by OCW3 where: SSMM=1, SMM=1,
the lowest priority, so a device requesting an interrupt will have to and cleared where SSMM=1, SMM=O.
command. WO-W2: Binary code of the highest priority level requesting
service.
The Poll command is issued by setting P= 1 iIJJ)CW3.~he 82C59A Equal to a "1" if there is an interrupt.
treats the next RD pulse to the 82C59A (i.e. RD=O, C.5=O) as an
interrupt acknowledge, sets the appropriate IS bit if therus a This mode is useful if there is a routine command common to several
~~est, and reads the priority level. Interrupt is frozen from WR to levels so that the INTA sequence is not needed (saves ROM space).
Another application is to use the poll mode to expand the number of
priority levels to more than 64.

/ TOOTH!AP"'ORITYCELLI
A ,

8080/8S{IIITI~
MODE
mm

For reading the IMR, no OCW3 is needed. The output data bus will
The input status of several internal registers can be read to update the contain the IMR whenever RD is active and AO=1 (OCW1). Polling
user information on the system. The following registers can be read overrides status read when P=f, RR=f in OCW3.
via OCW3 (IRR and ISR or OCW1 (IMR)).
In-Service Register (ISR): 8-bit register which contains the priority
levels that are being serviced. The ISR is updated when an End of This mode is programmed using bit 3 in ICWf.
Interrupt Command is issued.
If LTIM = '0', an interrupt request will be recognized by a low to high
Interrupt Mask Register: 8-bit register which contains the interrupt transition on an IR input. The IR input can remain high without
request lines which are masked. generating another interrupt.

The IRR can be read when, prior to the RD pulse, a Read Register If LTIM = 'f', an interrupt request will be recognized by a 'high' levei
Command is issued with OCW3 (RR=1, RIS=1). on IR input, and there is no need for an edge detection. The interrupt
request must be removed before the EOI command is issued or the
There is no need to write an OCW3 before every status read operation, CPU interrupt is enabled to prevent a second interrupt from
as long as the status read corresponds with the previous one; i.e., occurring.
the 82C59A "remembers" whether the IRR or ISR has been
previously selected by the OCW3. This is not true when poll is used. The priority cell diagram shows a conceptual circuit of the level
In the poll mode, the 82C59A treats the RD following a "poll write" sensitive and edge sensitive input circuitry of the 82C59A. Be sure to
operation as an INTA. After initialization, the 82C59A is set to IRR. note that the request latch is a transparent D type latch.
In both the edge and level triggered modes the IR inputs must remain detected by reading the ISR. A normallR7 interrupt will set the
high until after the falling edge of the first INTA. If the IR input goes corresponding ISR bit, a default IR7 won't. If a default IR7 routine
low before this time a DEFAULT IR7 will occur when the CPU occurs during a normallR7 routine, however, the ISR will remain set.
acknowledges the Interrupt. This can be a useful safeguard for In this case It Is necessary to keep track of whether or not the IR7
detecting interrupts caused by spurious noise glitches on the IR routine was previously entered. If another IR7 occurs It is a default.
inputs. To implement this feature the iR7 routine is used for "clean
up" simply executing a return instruction, thus ignoring the In power sensitive applications, It is advisable to place the 82C59A In
interrupt. If IR7 is needed for other purposes a default IR7 can still be the edge-triggered mode. This will minimize the current through the
pull-up resistors on the IR pins.

IR TRIGGERING
TIMING INT
REOUIREMENTS

This mode will be used In the case of a big system where cascading is When the 82C59A is used in a large system where bus driving
used, and the priority has to be conserved within each slave. In this buffers are required on the data bus and the cascading mode Is
case the fully nested mode will be programmed to the master (using used, there exists the problem of enabling buffers.
ICW4). This mode is similar to the normal nested mode with the
following exceptions: The buffered mode will structure the 82C59A to send an enable
a. When an interrupt request from a certain slave is in service, signal of SP/EN to enable the buffers. In this mode, whenever the
this slave is not locked out from the master's priority logic and 82C59A's data bus outputs are enabled, the SP/EN output
further interrupt requests from higher priority IRs within the becomes active.
slave will be recognized by the master and will initiate This modification forces the use of software programming to
interrupts to the processor, (In the normal nested mode a slave determine whether the 82C59A Is a master or a slave. Bit 3 in ICW4
is masked out when its request is in service and no higher programs the bUffered mode, and bit 2 in ICW4 determines
requests from the same slave can be serviced.) whether it is a master or a slave.
b. When exiting the Interrupt Service routine the software has to
check whether the interrupt serviced was the only one from
that slave. This is done by sending a non-specific End of
Interrupt (EOI) command to the slave and then reading its The 82C59A can be easily interconnected in a system of one
In-Service register and checking for zero. If it is empty, a master with up to eight slaves to handle up to 64 priority levels.
non-specified EOI can be sent to the master, too. If not, no EOI
should be sent.

'U .. "'T IIiTi INT

CAI.

."... ILAYEI CAI'

• • • • • , •
CAI.
iP,iH T
The master controls the slaves through the 3 line cascade bus. The The cascade bus lines are normally low and will contain the slave
cascade bus acts like chip selects to the slaves during the INTA address code from the trailing edge of the first INTA pulse to the
sequence. trailing edge of the third pulse. Each 82C59A in the system must
follow a separate initialization sequence and can be programmed
In a cascade configuration, the slave interrupt outputs are to work in a different mode. An EOI command must be issued
connected to the master interrupt request inputs. When a slave twice: once for the master and once for the corresponding slave.
request line is activated and afterwards acknowledged, the master Chip select decoding is required to activate each 82C59A.
will enable the corresponding slave to release the device routine
address during bytes 2 and 3 of INTA. (Byte 2 only for 80C86t The cascade lines ofthe Master 82C59A are activated only for slave
8088). inputs, non-slave inputs leave the cascade line inactive (low).
 Supply Voltage +8.0 VOLTS
Operating Voltage Range +4V to + 7V
Input Voltage Applied GNO- 2.0V to 6.5V
Output Voltage Applied GNO- 0.5V to VCC+ 0.5V
Storage Temperature Range - 65·C to + 150·C
Operating Temperature Range
Commercial O·C to + 70·C
Industrial - 40·C to + 85·C
Military - 55·C to + 125·C
Maximum Power Olsslpatlon 1 Watt
CAUTION:Stresses abovethose listed In the "ABSOLUTEMAXIMUM RATINGS" may cause permanent damage to the device.
This Is a stress only rating and operation of the device at these or any other conditions abovethose indicated in the operational
sections of this specification Is not implied.

D.C. ELECTRICAL CHARACTERISTICS

VCC = 5.0V ± 10%, TA = O·C to + 70·C (C82C59A), TA= - 40·C to + 85·C (182C59A);
TA= -55·Cto +125·C(M82C59A)
SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS
VIH LOGICAL ONE 2.0 V 182C59A C82C59A
INPUT VOLTAGE 2.2 V M82C59A
VIL LOGICAL ZERO 0.8 V
INPUT VOLTAGE
VOH OUTPUT HIGH VOLTAGE 3.0 V IOH=-2.5 mA
VCC-0.4 V IOH=-100 ~
VOL OUTPUT LOW VOLTAGE 0.4 V IOL=+2.5 mA
ilL INPUT LEAKAGE -1.0 +1.0 oil-A OVE;VINE;VCC
CURRENT
10 OUTPUT LEAKAGE -10.0 +10.0 IJA OVE;VOE;VCC
CURRENT
ICCSB STANDBY POWER SUPPLY 10 ~ VCC=5.5V
CURRENT VIN=VCC or GND
OUTPUTS OPEN

CAPACITANCE
TA=25·C; VCC = GND = OV; VIN = +5V or GND
SYMBOL PARAMETER MIN MAX UNITS TEST CONOITIONS
ClN* INPUT CAPACITANCE 5 pf FREQ = 1 MHz
Unmeasured ~ns
returned to G D
Cour* OUTPUT CAPACITANCE 15 pI
CliO * I/O CAPACITANCE 20 pI
 A.C. CHARACTERISTICS
VCC = +5V±10%, GND = OV: TA = DOCto + 7DoC (C82C59A)
: TA = -4DoC to +85°C (182C59A)
: TA = -55°C to + 125°C (M82C59A)

SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS

TAHRL AO/CS Setup to RD/INTA 10 ns
TRHAX AO/CS Hold after ROil NTA 5 ns
TRLRH RD Pulse Width 160 ns
TAHWL AO/CS Setup to WR 0 ns
TWHAX AO/CS Hold after WR 0 ns
TWLWH WR Pulse Width 190 ns
TDVWH Data Setup to WR 160 ns
TWHDX Data Hold after WR 0 ns
TJLJH Interrupt Request Width 100 ns See Note 1
(Low)
TCVIAL Cascade Setup to Second or 40 ns
Third INTA (Slave Only)
TRHRL End of RD to next RlL.. 160 ns
End of iNTA to next INTA
within an INTA sequence only
TWHWL End of WR to next WR 190 ns
*TCHCL End of Command to next 400 ns
Command (Not same command
type)
End of INTA sequence to
next INTA sequence
*vrorst case timing for TCHCL in an actual microprocessor system is typically much greater than 400 ns (i.e. B085A = 1.611S,8085A-2 = 11J.S,SOCS6 =
11'5).
Note: This is the low time required to clear the input latch in the edge triggered mode.

SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS

TRLDV Data Valid from RD/INTA 120 ns 1
TRHDZ Data Float after ROil NTA 10 85 ns 2
TJHIH Interrupt Output Delay 300 ns 1
TIALCV Cascade Valid from First 360 ns 1
INTA (Master Only)
TRLEL Enable Active from RD or 100 ns 1
INTA
TRHEH Enable inactive from RD 150 ns 1
or INTA
TAHDV Data Valid from Stable 200 ns 1
Address
TCVDV Cascade Valid to Valid Data 200 ns 1

il
V1
INPUT OUTPUT

l VIH+O.4\1 ~ ~ YOH
1.5\1- - -1.5\1
°FU~~: TEST POINT \lll-D.411 - . VOL

T
DEVICE UNDER TEST

R2 C1'

- ':' A.C. Testing: All input signals must switch between VIL-O.4V and
VIH+O.4V. TRand TF must be less than or equal to 15
TEST CONDITION V1 R1 R2 C1 ns.

1 1.7V 5230 OPEN 100 pf

2 4.5V 1.8Kfl 1.8Kfl 30 pf
 ==;:1_ TWHAX

~_ TWHOX

TRLRH -----Jk
I

-_I -TRHOZ
I ---l
•••••1

~,-=---=f- - - -
----....... I_---~I _----

\_--,-~'-'~f--/
-~\--1~TWHWL~'\-~/--
INTA SEQUENCE TJHIH

IR~ __

TJLJ;I~-I

~
___ X-- ----~\-jJ?-1 -<"l
 HARRIS REFERENCE PAGE 5-39 FOR
COMPLETE SPECIFICATIONS
HD-6406
CMOS
Programmable
Asynchronous
Communication Interface

Pinout
Top View
• SINGLE CHIP UART/BRG cso ~ vcc
• DC TO 16MHz OPERATION AD 2 3. cs.
WR 3 3e OR
• CRYSTAL DR EXTERNAL CLOCK INPUT
••
00 37 PE
• ON CHIP BAUD RATE GENERATOR 0' 3. FE
... 72 SELECTABLE BAUD RATES 02 6 3. OE
03 7 3' SOl
• DMA OR VECTORED INTERRUPT MODE O' 6 33 INTA

• MASKABLEINTERRUPTS O'
06 •10 32
31
SFO
SIE
• MICROPROCESSOR BUS ORIENTED INTERFACE 07 11 30 RST

• SCALED SAJI IV CMOS PROCESS AD 12 2. TBRE

13 2e
• SINGLE 6V POWER SUPPLY
Al
ALE ,. 27
CO
m
~ 2' tI"!'"I'l
• LOW POWER - lmA/MHz TYPICAL ~ "16 2' If;
•
•
•
COMPLETE MODEM INTERFACE
LINE BREAK GENERATION AND DETECTION
LOOPBACK AND ECHO MODES
IX
OX
500
ONO
,.
17
,e
20
2'
23
22
21
1m<
CfS
ATIO
TC

Dsscription
The HD-6406 (PACI) is a high performance programmable Universal AsynChronous ReceiverlTrans-
mitter (UART) and Baud Rate Generator (BRG) on a single chip. Utilizing Harris Semiconductor's
advanced Scaled SAJI IV CMOS process, the PACI will support data rates from DC to 1Mbaud
(O-16MHz clock). In addition to all standard UART functions, the PACI includes a complete Data
Communications Equipment (DCE) interface.

Provision is made for DMA control of the PACI so that operation at the higher data rates is not
hindered by slow microprocessor response times. An ALE control input permits direct interfacing
to multiplexed data/address buses common to many microprocessors.

The interrupt structure of the PACI is user-programmable and can be configured to provide a single
interrupt for any status change. A subsequent read of an internal status register will identify the
source of the interrupt. If desired, the PACI can also provide separate hardware interrupt outputs
for the receiver, transmitter and modem status changes. Separate error condition outputs can be
used to pinpoint the exact cause of any detected error condition.

IIrIll
•••
.....
!271 ••
'"
~
m HARRIS
CMOS OCTAL LATCHING
82C82
BUS DRIVER

• FULL EIGHT BIT PARALLEL LATCHING BUFFER Pinout

• BIPOLAR 8282 COMPA TlBLE
• THREE STATE NON-INVERTING OUTPUTS
TOP VIEW
• PROPAGATION DELAY - 35nsec MAX.
010 VCC
• A.C. CHARACTERISTICS GUARANTEED FOR:
011 000
~ FULL TEMPERATURE RANGE
012 001
~ 10% POWER SUPPLY TOLERANCE
013 002
~ CL ~ 300pF
014 003
• SINGLE 5V POWER SUPPLY
• POWER SUPPLY CURRENT - 10IJA MAX. STANDBY OIS 004

• OUTPUTS GUARANTEED VALID AT VCC ~ 2.0 VOLTS 016 DOS

• COMMERCIAL. INDUSTRIAL AND MILITARY TEMPERATURE RANGES 01] 006

• 20 PIN PACKAGE ON 0.3" CENTERS OE DO]

GNO STB

The Harris 82C82 is an octal latching buffer manufactured using a self-

aligned silicon gate CMOS process. This circuit provides an eight bit
parallel latch/buffer in a 20 pin package. The active high strobe (STB)
input allows transparent transfer of data and latches data on the negative
transition of this signal. The active low output enable (DE) permits simple
interface to state-of-the-art microprocessor systems.

010 - 017 Data Input Pins

000 - 007 Data Output Pins
STB Active High Strobe Input
DE Active low Output Enable

STB OE 01 DO

X H X Hi-Z
H L L L
H L H H

+ L X

H = Logic One Hi-Z" High Impedance

L '" logic Zero t;; Negative Transition
X '" Don't Care Latched to value of last data
 Supply Voltaga +8.0 VOLTS Storage Temperature Range
Oparating Voltage Range +4V to +7V Operating Temperature Range
Input Voltage Applied GND -2.0V to +6.5V Commercial DoC to +700C
Output Voltage Applied GND -0.6V to VCC +O.6V Industrial -400C to +860C
Maximum Power Dissipation 1 Watt
CAUTION: Stre" •• abova tholal/I~d In tha "ABSOLUTE MAXIMUM RATINGS" may call •• parmanant dama/lll to tha davlca. Thl'
II a 'tre" only rating and oparatlon of tha davlcaat thala or any othar condition, abovathOla/ndlca~d In tha oparetlonal 'IICtlon, of
thillpacification II not Impl/~.

D.C. ELECTRICAL CHARACTERISTICS

VCC = 5.0V+/-l0%; TA = OOCto +700C (CB2C82); TA = -400C to +850C (182C82)

SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS

VIH LogicalOne 2.0 V See note 1

Input VOltage
VIL Logical Zero O.S V
Input Voitaga
VOH Logical Ona 2.9 V 10H· -SmA
Output Voitaga OE· LOW
VOL Logical Zero 0.4 V 10L ·SmA
Output Voltage ~. LOW
IlL Input Laakage -1.0 1.0 IJA OV~VIN~VCC
Current

10 Output Leakage -10.0 10.0 IJA OV~VO~VCC

Current OE • VCC-0.5V
ICC Power 10.0 jJA VIN • VCC or GND
Supply Current VCC· 5.5 V
OUTPUTS OPEN
CIN· Input 5 pi FREO -1 MHZ
Capacitance TA·250C
VIN • VCC or GND
COUP Output 15 pi FREO·l MHZ
Capacitance TA·250C
VIN· VCC or GND

NOTE1: VIH i. maa.ured by applying a pulse 01 magnituda· VI Hmin to ona data input at a time and chacking tha corre.·
ponding davice output lor e valid logical "I" during valid input high time. Control pins (STB, DEI are talted IOparataly with
all device data input pins at VIHmin'
Supply Voltage +8.0 VOLTS Storage Temperature Range
Operating Voltage Range +4V to +7V Operating Temperature Range
Input Voltage Applied GND -2.0V to +6.5V Military -550C to +1250C
Output Voltage Applied GND -o.5V to VCC +O.5V Maximum Power Dissipation 1 Watt

CAUTION: St",sses ebove those listed in the "ABSOLUTE MAXIMUM RATINGS" mey ceuse permenent damage to the de.ice. This
is a st",ss only rating and OParation of the device at these or any other conditions above those indicated in the OPeretiona' sections of
thillptlcificstion if not implied.

SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS

VIH LogicalOna 2.2 V Sse nota 1

Input Voltaga
VIL Logical Zaro 0.8 V
Input Voltaga
VOH Logical Ona 2.9 V 10H - -8mA
Output Voltaga OE - LOW
VOL Logical Zaro 0.4 V 10L -8mA
Output Voltaga ~- LOW
IlL Input Laakaga -1.0 1.0 IJA OV~VIN~VCC
Current

10 Output Laakaga -10.0 10.0 IJA OV~VO~VCC

Current BE - VCC-0.5V
ICC Power 10.0 IJA VIN - VCC or GND
Supply Currant VCC - 5.5 V
OUTPUTS OPEN
CIN· Input 5 pi FREQ = 1 MHZ
Capacitance TA - 250C
VIN - VCC or GND
COUP Output 15 pi FREQ = 1 MHZ
Capacitance TA - 250C
VIN - VCC or GND

NOTE1: VIH is maasurad by applying a pulsa 01 magnituda - VI Hmin to ona data input at a tima and chacking tha corr •• •
ponding davica output lor a valid logical "I" during valid input high time. Control pins (STB. OEI are testad separately with
all davica data input pins at VIHmin'
A.C. ELECTRICAL CHARACTERISTICS; VCC = 5.0V ±10%; T A = Commercial, Industrial or Military
CL = 300 pf', FREQ = 1 MHZ

SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS

TIVOV Propagation Delav 35 ns see notes 1,2

Input to Output

TSHOV Propagation Delay 55 ns see notes 1, 2

STB to Output

TEHOZ Output Disable 35 ns see notes 1, 2

Time

TELOV Output Enable 50 ns see notes 1, 2

Time

T1VSL Input to STB 0 ns see notes 1, 2

Set Up Time

TSLIX Input to STB 25 ns see notes 1,2

Hold Time

TSHSL STB High Time 25 ns see notes 1, 2

TR,TF Input Rise/Fall 20 ns see notes 1, 2
Times

NOTES: 1. All A.C. parameters tested as per test circuits and definitions in Figures 1-4.
2. Input test signals must switch between VI L-O.4V and VIH+0.4V.
Input rise and fall times must be ~ 20 nsec.

T1VSL

STB

Figure 1

82C82 TIMING RELATIONSHIPS

 O.6V 3.3V

l~n T~n
OUTPUT

50pf·
.::f:. TEST POINT ± TESTPOINT

T T
Figura 3 Figure 4
Figure 2 TEHOZ
TEHOZ
TIVOV, TSHOV, TELOV OUTPUT HIGH DISABLE OUTPUT LOW DISABLE
Load Circuit Load Circuit Load Circuit

The transient current required to charge and discharge the 300 pf load capacitance specified in the 82C82 data sheet is
determined by

Assuming that all outputs change state at the same time and that dV/dt is constant;
I = CL (VCC x 80%)
tR/tF

where tR = 20 ns, VCC = 5.0 volts, CL = 300 pf on each of eight outputs.

I = (8 x 300 x 10-12) x (5.Ovx 0.8)/(20 x 10-9)

= 480 mA

This current spike may cause a large negative voltage spike on VCC, which could cause improper operation of the device.
To filter out this noise, it is recommended that a 0.1 uF ceramic disc decoupling capacitor be placed between VCC and
GND at each device, with placement being as near to the device as possible.
• GENERATES THE SYSTEM CLOCK FOR CMOS OR NMOS
MICROPROCESSORS

• UP TO 25 MHZ OPERATION

• USES A PARALLEL MODE CRYSTAL CIRCUIT OR EXTERNAL

CSYNC Vcc
FREQUENCY SOURCE PCLK Xl
• PROVIDES READY SYNCHRONIZATION AENl X2
• GENERATES SYSTEM RESET OUTPUT FROM SCHMITT TRIGGER INPUT RDYl ASYNC
• CAPABLE OF CLOCK SYNCHRONIZATION WITH OTHER 82C84As READY EFI
• TTL COMPATIBLE INPUTS/OUTPUTS RDY2 FIe
• VERY LOW POWER CONSUMPTION AEN2 OSC
• 18 PIN PACKAGE CLK RES
• SINGLE +5V POWER SUPPLY GND RESET
• COMMERCIAL, INDUSTRIAL AND MILITARY TEMPERATURE RANGES
AVAILABLE

The Harris 82C84A is a high performance CMOS clock generator-driver

which is designed to service the requirements of both CMOS and NMOS
CONTROL
microprocessors such as the 80C86, 80C88, 8086 and the 8088. The chip PIN LOGICAL 1 LOGICAL 0
contains a crystal controlled oscillator, a divide-by-three counter and
complete "Ready" synchronization and reset logic. F/C External Crystal
Clock Drive
Static CMOS circuit design permits operation with an external frequency
REs Normal Reset
source from DC to 25M Hz. Crystal controlled operation to 25MHz is
guaranteed with the use of a parallel, fundamental mode crystal and two RDYl Bus Ready Bus not
small load capacitors. RDY2 ready
Address Address
All inputs (except Xl, X2 and RES)
are TTL compatible with a VIH of
AENl
AEiil'i Disabled Enabled
2.0 volts over the industrial temperature and voltage ranges.
ASYNC 2 Stage Ready 1 Stage Ready
Power consumption is a fraction of that of the equivalent bipolar circuits. Synchronization Synchronization
This speed-power characteristic of CMOS permits the designer to custom
tailor his system design with respect to power and/or speed requirements.
 Pin I/O Definition Pin I/O Definition

AEN1, I ADDRESS ENABLE: AEN is an active lOW ClK a PROCESSOR CLOCK: ClK is the clock out-
AEN2 signal. AEN serves to qualify its respective put used by the processor and all devices
Bus Ready Signal (RDYl or RDY2). AENl which directly connect to the processor's
validates RDYl while AEN2 validates RDY2. local bus. ClK has an output frequency
Two AEN signal inputs are useful in system which is 1/3 of the crystal or EF I input fre-
configurations which permit the processor to quency and a 1/3 duty cycle.
access two Multi-Master System Busses. In
non Multi-Master configurations, the AEN PClK 0 PERIPHERAL CLOCK: PClK is a peripheral
signal inputs are tied true (lOW). clock signal whose output frequency is 1/2
that of ClK and has a 50% duty cycle.
RDY 1, I BUS READY (Transfer Complete). RDY is an
RDY2 active HIGH signal which is an indication OSC a OSCillATOR OUTPUT: OSC is the output
from a device located on the system data bus of the internal oscillator circuitry. Its fre-
that data has been received, or is available. quency is equal to that of the crystal.
RDYl is qualified by AENl while RDY2 is
qualified by AEN2. RES I RESET IN: RES is an active lOW signal
which is used generate RESET.The 82C84A
ASYNC I READY SYNCH RON IZA TION SELECT: provides a Schmitt trigger input so that an
ASYNC is an input which defines the synch- RC connection can be used to establish the
ronization mode of the READY logic. When power-up reset of proper duration.
ASYNC is low, two stages of READY synch-
ronization are provided. When ASYNC is left RESET 0 RESET: RESET is an active HIGH signal
open or HIGH a single stage of READY which is used to reset the 8OC86 family
synchronization is provided. processors. Its timing characteristics are de-
termined by RES.
READY a READY: READY is an active HIGH signal
which is the synchronized RDY signal input. CSYNC I CLOCK SYNCHRONIZATION: CSYNC is
READY is cleared after the guaranteed hold an active HIGH signal which allows multiple
time to the processor has been met. 82C84As to be synchronized to provide
clocks that are in phase. When CSYNC is
Xl, X2 I CRYSTAL IN: Xl and X2 are the pins to HIGH the internal counters are reset. When
which a crystal is attached. The crystal fre- CSYNC goes lOW the internal counters
quency is 3 times the desired processor are allowed to resume counting. CSYNC
clock frequency. needs to be externally synchronized to EFI.
When using the internal oscillator CSYNC
F/e I FREQUENCY/CRYSTAL SELECT: F/e is a should be hardwired to ground.
strapping option. When strapped lOW, F/C
permits the processor's clock to be generated
by the crystal. When F /e is strapped H IG H, GND Ground
ClK is generated from the EFI input.
VCC +5V supply
EFI I EXTERNAL FREQUENCY IN: When F/C is
strapped HIGH, ClK is generated from the
input frequency appearing on this pin. The
input signal is a square wave 3 times the fre-
quency of the desired ClK output.

Capacitors Cl, C2 are chosen such that their combined

capacitance:
The oscillator circuit of the 82C84A is designed primarily Cl • C2
for use with an external parallel resonant, fundamental CT = C1+C2(1ncluding stray capacitance)
mode crystal from which the basic operating frequency
is derived. matches the load capacitance as specified by the crystal
manufacturer. This insures operation within the frequency
The crystal frequency should be selected at three times tolerance specified by the crystal manufacturer.
the required CPU clock. X 1 and X2 are the two crystal
input crystal connections. For the most stable operation
of the oscillator (OSC) output circuit, two capacitors
(Cl = C2) as shown in the waveform figures are recom- The clock generator consists of a synchronous divide-by-
mended. The output of the oscillator is buffered and -three counter with a special clear input that inhibits the
brought out on OSC so that other system timing signals counting. This clear input (CSYNC) allows the output
can be derived from this stable, crystal-controlled source. clock to be synchronized with an external event (such as
 another 82C84A clock). It is necessary to synchronize Synchronization is required for all asynchronous active-
the CSYNC input to the EFI clock external to the 82C84A. going edges of either RDY input to guarantee that the
This is accomplished with two flip-flops. (See Figure 3.) RDY setup and hold times are met. Inactive-going edges
The counter output is a 33% duty cycle clock at one-third of RDY in normally ready systems do not require synch-
the input frequency. ronization but must satisfy RDY setup and hold as a matter
of proper system design.
* The F/C input is a strapping pin that selects either the
crystal oscillator or the EFI input as the clock for the The ASYNC input defines two modes of READY synch-
+3 counter. If the EFI input is selected as the clock
ronization operation.
source, the oscillator section can be used independently for
another clock source. Output is taken from OSC.
When ASYNC is LOW, two stages of synchronization are
provided for active READY input signals. Positive-going
asynchronous READY inputs will first be synchronized to
flip-flop one at the rising edge of CLK (requiring a setup
The CLK output is a 33% duty cycle clock driver designed
time tR1VCH) and then synchronized to flip-flop two at
to drive the 80C86, 80C88 processors directly. PCLK is a the next falling edge of CLK, after which time the READY
peripheral clock signal whose output frequency is 1/2
output will go active (H IGH). Negative-going asynch-
that of CLK. PCLK has a 50% duty cycle.
ronous READY inputs will be synchronized directly to
flip-flop two at the falling edge of CLK, after which time
Reset logic
the READY output will go inactive.This mode of operation
is intended for use by asynchronous (normally not ready)
The reset logic provides a Schmitt trigger input (R ES)
devices in the system which cannot be guaranteed by design
and a synchronizing flip-flop to generate the reset timing.
to meet the required RDY setup timing, tR1VCL, on
The reset signal is synchronized to the falling edge of
each bus cycle. (Refer to Figure 5.)
CLK. A simple RC network can be used to provide power-
on reset by utilizing this function of the 82C84A. Wave-
When ASYNC is high or left open, the first READY flip-
forms for clocks and reset signals are illustrated in Figure 4.
flop is bypassed in the READY synchronization logic.
READY inputs are synchronized by flip-flop two on the
falling edge of ClK before they are presented to the
processor. This mode is available for synchronous devices
Two READY inputs (RDY1, RDY2) are provided to that can be guaranteed to meet the required RDY setup
accommodate two system busses. Each input has a qualifier time. (Refer to Figure 6.)
(~ and AEN2" respectively). The AEN signals validate
their respective RDY signals. If a Multi-Master system is ASYNC can be changed on every bus cycle to select the
not being used the AEN pin should be tied LOW. appropriate mode of synchronization for each device in
the system.

*Note: If EFI input is used, then crystal input Xl must be

tied to VCC or GND and X2 should be left open. If
the crystal inputs are used, then EFt should be tied
to VCC or GND.
 Supply Voltage +8.0 Volts Operating Temperature Range
Operating Voltage Range +4V to +7V Commercial DoC to +700C
Input Voltage Applied GND-2.0V to 6.5V Industrial -400C to +850C
Output Voltage Applied GND-0.5V to VCC + 0.5V Military -550C to +1250C
Storage Temperature Range -650C to +1500C Maximum Power Dissipation 1 Watt

CAUTION: Stresses above those listed in the "ABSOLUTE MAXIMUM RA TlNGS" may cause permanent damage to the device. This
is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied.

D. C. ELECTRICAL CHARACTERISTICS
VCC = 5.0V ± 10%; TA = DoC to +700C (C82C84A); TA = -400C to +850C (I82C84A);
T A = -550C to +1250C (M82C84A)

SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS

VIH Logical One 2.0 V 182C84A

Input Voltage 2.2 V M82C84A

VIL Logical Zero 0.8 V

Input Voltage

VT+ Reset Input 0.6 VCC VCC -0.8 V

High Voltage

VT+ -VT- Reset Input 0.2 VCC

Hysteresis

VOH Logical One VCC-O.4 V IOH=-4.0mA for

CLK output
Output Voltage IOH = -2.5mA for
all others

VOL Logical Zero 0.4 V IOL = +4.0 mA for

CLK output
Output Voltage IOL = +2.5 mA for
all others

IlL Input Leakage -1.0 1.0 IJ.A OV<VIN<VCC except

Current ASYNC. X 1-see note 1

ICC Power 40 mA Crystal

Su pply Cu rrent Frequency = 25M Hz
Outputs Open

NOTES:
1. ASYNC pin includes an internal 17.5Kn nominal pull-up resistor. For ASYNC input at GND, ASYNC input leakage
current = 130,uA nominal.
Xl - crystal feedback input.

SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS

CIN* Input 5 pf Freq. = lMHz

Capacitance
 Symbol Parameter Min. Max. Units Test Conditions

tEHEl External Frequency HIGH Time 13 ns 90% - 90% VIN

tElEH External Frequency lOW Time 13 ns 10%-10% VIN
tElEl EFI Period 36 ns
X IAl ~requency 2.4 25 MHz
tR1VCl RDY1, RDY2 Active Setup to ClK 35 ns ASYNC = HIGH
tR1VCH RDY1, RD2 Active Setup to ClK 35 ns ASYNC- lOW
tR1VCl RDY1 RDY2 Inactive Setup to ClK 35 ns
tClR1X RDY1, RDY2 Hold to ClK 0 ns
tAYVCl ASYNC Setup to ClK 50 ns
tClAYX ASYNC Hold to ClK 0 ns
tA1VR1V AEN1, AEN2 Setup to RDY1, RDY2 15 ns
tClA1X AEN1, AEN2 Hold to ClK 0 ns
tvHEH CSYNC Setup to EF I 20 ns
tEHYl CSYNC Hold to EFI 20 ns
tYHYl CSYNC Width 2·tElEl ns
tl1HCl RES Setup to ClK 65 ns (Note 2)
tCLl1 H RES Hold to ClK 20 ns (Note 2)

A. C. CHARACTERISTICS (cont.)
TIMING RESPONSES

Symbol Parameter Min. Max, Units Test Conditions

tClCl ClK Cycle Period 125 ns

tCHCl ClK HIGH Time (1/3 tClCLI +2.0 ns Fig. 7 & Fig. 8
tClCH ClK lOW Time (2/3 tClcLl -15.0 ns Fig. 7 & Fig. 8
tCH1CH2 ClK Rise or Fall Time 10 ns 1.0V to 3.5V
tCl2Cl1
tPHPl PClK HIGH Time tClCl -20 ns
tPlPH PClK lOW Time tClCL -20 ns
tRYlCl Ready Inactive to ClK (See note 4) -8 ns Fig. 8 & Fig. 10
tRYHCH Ready Active to ClK (See note 3) (2/3 tClcLl -15.0 ns Fig. 9 & Fig. 10
tCLIl ClK to Reset Delay 40 ns
tClPH ClK to PClK HIGH Delay 22 ns
tClPl ClK to PClK lOW Delay 22 ns
tOlCH OSC to ClK HIGH Delay -5 22 ns
tOlCl OSC to ClK lOW Delay 2 35 ns

NOTES:
1. Output signals switch between VOH and VOL unless otherwise specified.
2. Setup and hold necessary only to guarantee recognition 8t next clock.
3. Applies onlv to T3 TW states.
4. Applies only to T2 stetes.
5. All timing delays are measured at'.5 volts unless otherwise noted.
6. Input signals must switch between VIL max -.4 VOH and VIH min +.4 volts
in 15n5 unless otherwise specified.
f4--tClIU'_~ tl'HC~"'"

I
Cl~ 0

~C2

Fie
AE1l1
RDY2
xrJff
CSYNC READY

2.25V

R-74onFOR ALL OUTPUTS EXCEPT CLK

463nFOR eLK OUTPUT
FROM OUTPUT
UNDER TEST
~

r-=- Cl
(SEE NOTE J)

NOTES:
1. Cl. 100pF
2. Cl ·30pF
3. CllNClUDES PROBE AND JIG CAPACITANCE

PARAMETER TYPICAL CRYSTAL SPEC

Frequency 2.4-25MHz, Fundamental, "AT" cut

Type of Operation Parallel
Unwanted Modes -6db (Min)
Load Capacitance 18-32pf
mJ HARRIS 82C88

• PIN COMPATIBLE WITH BIPOLAR 8288

• PROVIDES ADVANCED COMMANDS FOR MUL TI-MASTER BUSSES
• 3-STATE COMMAND OUTPUTS
• BIPOLAR DRIVE CAPABILITY
• FULLY TTL COMPATIBLE
• SCALED SAJI IV CMOS PROCESS
• SINGLE 6V POWER SUPPLY
• LOW POWER OPERATION
~ ICCSB - 10IJA
lOB VCC
~ ICCOP - lmA/MHz
• INDUSTRIAL, MILITARY, AND COMMERCIAL ClK so
TEMPERATURE RANGES fi ~
Description DT/A McefPi5'EN
ALE DEN

AEN CEN
The Harris 82C88 is a high performance CMOS Bus Controller manufactured
MRi51: iNTA
using a self-aligned silicon gate CMOS process (Scaled SAJI IV). The 82C88
provides the control and command timing signals for 80C86 and 8086/88 ~ i5RC
..,>
systems. The high output drive capability of the 82C88 eliminates the need MWTC A'iOWC co:
'-':Ii
for additional bus drivers. High speed and industry standard configuration
make the 82C88 compatible with microprocessors such as the BOC86, 8086,
GND iOWC ...
:li:<
8088,8089,80186, and 80188.

Static CMOS circuit design insures low operating power. Harris's advanced
SAJI processresults in performance equal to or greater than existing equivalent
products at a significant power savings.

- 'MR"DC

- STATUS
DECODER
~
- ™
)
nlWlr MULTleuS
COMMAND COMMAND
SIGNAL RlIll:" SIGNALS
GENERATOR
~
I ~
TIlTJ(

CLK_
-
I DTJ1!I

AEN----. - CONTROL ADDRESS LATCH. DATA

)
CONTROL DEN
SIGNAL

-
TRANSCEIVER. AND
LOGIC GENER· INTERRUPT CONTROL
CEN~ MCE!PoEN
ATOR SIGNALS

- ALE

I I
 PIN
SYMBOL NUMBER TYPE NAME AND FUNCTION

VCC 20 +5V power supply

GND 10 Ground

So,51 19,3 I Status Input pins: These pins are the input pins from the 80C86, 8086/88/8089 processors.
52 18 The 82C88 decodes these inputs to generate command and control signals at the appropriate
time. When Status pins are not in use (passive), command outputs are held HIGH (See Table 1 J

CLK 2 I Clock: This is a CMOS compatible input which receives a clock signal from the 82C84A clock
generator and serves to establish when command/control signals are generated.

ALE 5 0 Address Latch Enable: This signal serves to strobe an address into the address latches. This
signal is active HIGH and latching occurs on the falling (H IGH to LOW) transition. ALE is
intended for use with transparent 0 tYpe latches, such as the 82C82.

DEN 16 0 Data Enable: This signal serves to enable data transceivers onto either the local or system data
bus. This signal is active HIGH.

DT/R 4 0 Data Transmit/Receive: This signal establishes the direction of data flow through the trans-
ceivers. A HIGH on this line indicates Transmit (write to I/O or memory) and a LOW indicates
Receive (Readl.

AEN 6 I Address Enable: AEN enables command outputs of the 82C88 Bus Controller a minimum of
110ns (250ns maximum) after it becomes active (LOW). AEN going inactive immediately 3-
states the command output drivers. AEN does not affect the 1/0 command tines if the 82C88
is in the I/O Bus mode (lOB tied HIGHl.

CEN 15 I Command Enable: When this signal LOW all 82C88 command outputs and the DEN and PDEN
control outputs are forced to their Inactive state. When this signal is HIGH, these same outputs
are enabled.

lOB 1 I Input/Output Bus Mode: When the lOB is strapped HIGH the 82C88 functions in the I/O Bus
mode. When it is strapped LOW, the 82C88 functions in the System Bus mode (See I/O Bus
and System Bus sectionsl.

AIOWC 12 0 Advanced I/O Write Command: The AIOWC issues an I/O Write Command earlier in the machine
cycle to give I/O devices an early indication of a write instruction. Its timing is the same as a
read command signal. AIOWC is active LOW.

10WC 11 0 I/O Write Command: This command line instructs an I/O device to read the data on the data
bus. The signal is active LOW.

10RC 13 0 I/O Read Command: This command line instructs an I/O device to drive its data onto the data
bus. This signal is active LOW.

AMWC 8 0 Advanced Memory Write Command: The AMWC issues a memory write command earlier in the
machine cycle to give memory devices an early indication of a write instruction. Its timing is
the same as a read command signal. AMWC is active LOW.

MWTC 9 0 Memory Write Command: This command line instructs the memory to record the data present
on the data bus. This signal is active LOW.

MRDC 7 0 Memory Read Command: This command line instructs the memory to drive its data onto the
data bus. MRDC is active LOW. .

INTA 14 0 Interrupt Acknowledge: This command tine tells an interrupting device that its interrupt has
been acknowledged and that it should drive vectoring information onto the data bus. This signal
is active LOW.

MCE/PDEN 17 0 This is a dual function pin. MCE (lOB is tied LOW): Master Cascade Enable occurs during an
interrupt sequence and serves to read a Cascade Address from a master 82C59A Priority Interrupt
Controller onto the data bus. The MCE signal is active HIGH. PDEN (lOB is tied HIGH):
Peripheral Data Enable enables the data bus transceiver for the I/O bus that DEN performs
for the system bus. PO EN is active LOW.
 82C88

AMWC - Advanced Memory Write Command

AIOWC - Advanced I/O Write Command
The command logic decodes the three 80C86, 8086, 8088 INTA - Interrupt Acknowledge
or 8089 status lines (SO, 51, 52) to determine what com-
mand is to be issued (see Table 1). INTA (Interrupt Acknowledge) acts as an I/O read during
Table 1. Command Decode Definition an interrupt cycle. Its purpose is to inform an interrupting
device that its interrupt is being acknowledged and that it
B2CBB should place vectoring information onto the data bus.
S2 51 So Processor State Command

0 0 0 Interrupt Acknowledge INTA

0 0 1 Read I/O Port 10RC
0 1 0 Write I/O Port 10WC.AIOWC
1 1
The control outputs of the l!?C88 are Data Enable (DEN).
0 Halt None
Data Transmit/Receive (DT/R) and Master Cascade Enable/
1 0 0 Code Access MRDC
Peripheral Data Enable (MCE/PDEN). The DEN signal
1 0 1 Read Memory MRDC
determines when the external bus should be enabled onto
,
1
1
1 0
1
Write Memory
Passive
MWTC.AMWC
None
the local bus and the DT /R determines the direction of
data transfer. These two signals usually go to the chip
select and direction pins of a transceiver.

The MCE/PDEN pin changes function with the two modes

of the 82C88. When the 82C88 is in the lOB mode (lOB
The 82C88 is in the I/O Bus mode if the lOB pin is strapped
HIGH). the PO EN signal serves as a dedicated data enable
HIGH. In the I/O Bus mode, all I/O command lines 10RC
signal for the I/O or Peripheral System bus.
10WC. AIOWC, INTA) are always enabled (i.e., not de~
pendent on AEN). When an I/O command is initiated by
the processor, the 82C88 immediately activates the com-
mand lines using PO EN and DT /R to control the I/O
The MCE signal is used during an interrupt acknowledge
bus transceiver. The I/O command lines should not be
cycle if the 82C88 is in the System Bus mode (lOB LOW).
used to control the system bus in this configuration because
During any interrupt sequence, there are two interrupt
no arbitration is present. This mode allows one 82C88
acknowledge cycles that occur back to back. During the
Bus Controller to handle two external busses. No waiting
first interrupt cycle no data or address transfers take place.
is involved when the CPU wants to gain access to the I/O
Logic should be provided to mask off MCE during this
bus. Normal memory access requires a "Bus Ready"
cycle. Just before the second cycle begins the MCE signal
signal (AEN LOW) before it will proceed. It is advan-
gates a master Priority Interrupt Controller's (PIC) cascade
tageous to use the lOB mode if I/O or peripherals dedica-
address onto the processor's local bus where ALE (Address
ted to one processor exist in a multi-processor system.
Latch Enable) strobes it into the address latches. On the
leading edge of the second interrupt cycle, the addressed
slave PIC gates an interrupt vector onto the system data
The 82C88 is in the System Bus mode if the lOB pin is bus where it is read by the processor.
strapped LOW. In this mode, no command is issued
until a specified time period after the AEN line is activated If the system contains only one PIC, the MCE signal is not
(LOW). This mode assumes bus arbitration logic will used. In th is case, the second Interrupt Acknowledge
inform the bus controller (on the AEN line) when the bus signal gates the interrupt vector onto the processor bus.
is free for use. Both memory and I/O commands wait for
bus arbitration. This mode is used when only one bus
exists. Here, both I/O and memory are shared by more
than one processor. Address Latch Enable (ALE) occurs during each machine
cycle and serves to strobe the current address into the
82C82 address latches. ALE also serves to strobe the
status (SO, 51, S2) into a latch for halt state decoding.
The advanced write commands are made available to
initiate write procedures early in the machine cycle. This
signal can be used to prevent the processor from entering
an unnecessary wait state. The Command Enable (CEN) input acts as a command
qualifier for the 82C88. If the CEN pin is high, the 82C88
The command outputs are: functions normally. If the CEN pin is pulled LOW, all
command lines are held in their inactive state (not 3-statel.
MRDC- Memory Read Command This feature can be used to implement memory partition-
MWTC - Memory Write Command ing and to eliminate address conflicts between system
10RC- I/O Read Command bus devices and resident bus devices.
10WC- I/O Write Command
 Supply Voltage +8.0 Volts Operating Temperature Range
Operating Voltage Range +4V to +7V Commercial OOCto +700C
Input Voltage Applied GND -2.0V to +6.5V Industrial -400C to +850C
Output Voltage Applied GND -o.5V to VCC +O.5V Military -550C to +1250C
Storage Temperature Range -650C to +1500C Maximum Power Dissipation 1 Watt

CAUTION: Strs •• es ebove those listed under the "Absolute Meximum Retings" mey ceuse permenent demege to the device. These
ers strsss only ratings end functionel operetion of the device et these or et eny other conditions ebove those indiceted in the operetionel
sections of this specificetion is not implied.

D. C. ELECTRICAL CHARACTERISTICS
VCC" 5.0V ±10%; TA = OOCto +700C (C82C88); TA" -400C to +850C (I82C88);T A =-550C to +1250C (M82C88)

SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS

VIH LogicelOne 2.0 V I82C88

Input Voltege 2.2 V M82C88

VIL Logicel Zero 0.8 V

Input Voltege

VIHC CLK Logicel One 0.7 VCC V

Input Voltege

VILC CLK Logicel Zero 0.2VCC V

Input Voltege

VOH Output High Voltage 3.0 V 10H --a.OmA

Command Output. VCC -0.4 V 10H - -2.5mA

Output High Voltage 3.0 V 10H - -4.0mA

Control Output. VCC -0.4 V 10H - -2.5mA

VOL Output Low Voltage 0.5 V 10L - +20.0mA

Commend Output.

Output Low Voltege 0.4 V 10L - +8.0mA

Control Output.

ilL Input Leakage -1.0 1.0 IJ.A OV~VIN~VCC

Current except So.51. 52
IBHH Input Leakege -50 -300 IJA VIN - 2.0V
Current-Status Bus So. 51.52 (.ee Note 1)

10 Output Leakege -10.0 10.0 IJA OV~VO~VCC

Current

ICCSB Stendby Power Supply 10 IJA VCC - 5.5V

VIN - VCC or GND
Output. Open

ICCOP Operetlng Power 1 mAIM Hz VCC - 5.5V

Supply Current Output. Open

CAPACITANCE
TA = 250C; VCC = GND = OV; VIN = +5V or GND

SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS

CIN" Input Cepecltence 5 pf FREQ·1MHz

Unmeasured pins
returned to GND
COUTo Output Capacitance 15 pf

"Gueranteed end .empled. but not 100% te.ted

Notel: IBHH should be measured after rei.ing the VIN on So. s,. 52 to VCC end then lowering to 2.0V.

3-92
VCC = +5V ±10%. GND = OV: TA = OOC to 700C (C82C88)
T A = -400C to +850C (I82C88)
TA = -550C to +1250C (M82C881

TIMING REQUIREMENTS

SYMBOL PARAMETER MIN MAX UNIT TEST CONDITIONS

TCLCL CLK Cycle Period 125 ns

TCLCH CLK Low Time 66 ns
TCHCL CLK High Time 40 ns
TSVCH Status Active Setup Time 35 ns
TCHSV Status Active Hold Time 10 ns
TSHCL Status Inactive Setup Time 35 ns
TCLSH Status Inactive Hold Time 10 ns

TIMING RESPONSES

TCVNV Control Active Delay 5 45 ns 1

TCVNX Control I nactive Delay 10 45 ns 1
TCLLH ALE Active Delay (from CLK) 20 ns 1
TCLMCH MCE Active Delay (from CLK) 25 ns 1
TSVLH ALE Active Delay (from Status) 20 ns 1
TSVMCH MCE Active Delay (from Status) 30 ns 1
TCHLL ALE Inactive Delay 4 18 ns 1
TCLML Command Active Dalay 5 35 ns 2
TCLMH Command Inactive Delay 5 35 ns 2
TCHDTL Direction Control Active Delay SO ns 1
TCHDTH Direction Control Inactive 30 ns 1
Delay
TAELCH Command Enable Time 1 40 ns 3
TAEHCZ Command Disable Time2 40 ns 4
TAELCV Enable Delay Time 110 250 ns 2
TAEVNV AEN to DEN 25 ns 1
TCEVNV CEN to DEN. PDEN 25 ns 1
TCELRH CEN to Command TCLML ns 2
+10
TLHLL ALE High Time TCLCH ns 1
-10

OUTPUT F ROM

UNDE~E~~~~
4 ' V,

Ie,.
TEST

POINT
TEST
CONDITION

3
1
IOH

-4.0mA

-8.0mA

-8.0mA
IOL

+8.0mA

+20.0mA

-
V1

2.13V

2.29V

1.5V
R1

22011

9111

18711
C1

80pf

300pf

300pf

4 -8.0mA - 1.5V 18711 SOpf

 1.5V ><-... .••
-----------....
~VOL
~----VOH

-
, ~'''_I.IIotOWtoONU'Ol'IiIlIHIIll''ICI'UtllIlOaU
f UAOlNG IDOl Of"ALl AND1IIC111DfllllMINIO I" Till 'AllllfG
f
IOGI Of"CUI Ol'IIUTUS GOINGACflV( WHICH(VlII OC(;U"I LAST
A,Ll flYING MIASUlll"'INT'I AM IIlAO' iIlT1 SVUNLUS SPfCI"ID DtMI_It(
m HARRIS
CMOS
SOCSS
8 BIT MICROPROCESSOR

• COMPATIBLE WITH NMOS 8088

• DIRECT SOFTWARE COMPATIBLITY WITH 8OC86, 8086, 8088
• 8 BIT DATA BUS INTERFACE MIN MAX
( MODE
J
• 16 BIT INTERNAL ARCHITECTURE MODE

• COMPLETELY STATIC DESIGN

GND Vcc
~ OPERATION FROM DC TO 5MHz
A14 AIS
• LOW POWER OPERATION
A13 A16/$3
~ ICCSB = 500IJA MAXIMUM
A17154
~ ICCOP = 10mA/MHz TYPICAL AI'
All A18/55
• 1 MBYTE OF DIRECT MEMORY ADDRESSING CAPABILITY
AID A191$6
• 24 OPERAND ADDRESSING MODES
• BIT, BYTE, WORD, AND BLOCK MOVE OPERATIONS A9 550
• 8 and 16 BIT SIGNED/UNSIGNED ARITHMETIC AB MNIMX

• BUS-HOLD CIRCUITRY ELIMINATES PULL-UP RESISTORS ADT Rii

• SCALED SAJI IV CMOS PROCESS AD6 HOLD (1iQ/lffO)
• SINGLE 5V POWER SUPPLY ADS HlDA IlIQ/ffi)
• COMMERCIAL, INDUSTRIAL and MILITARY TEMPERATURE RANGES ADO WR ILOCK)

AD3 101M (S2)

AD' OliA (51)
ADI liEN ISO)
ADO ALE 1050)
The Harris 80C88 high performance 16 bit CMOS CPU is manufactured using a
self-aligned silicon gate CMOS process (Scaled SAJI IV). Two modes of opera- NMI iNlA 1051)

tion, MINimum for small systems and MAXimum for larger applications such as INTR fEST
CLK READY
multi-processing, allow user configuration to achieve the highest performance
GND RESET
level. Full TTL compatibility and industry standard operation allow use of exist-
ing NMOS 8088 hardware and Harris CMOS 80C86 peripherals. Complete soft-
ware compatibility with the 80C86, 8086 and 8088 microprocessors allows use
of existing software in new designs.

INSTRUCTION
STREAM BYTE
QUEUE

BUS
INTERFACE
UNIT

AH Al
8101 Bl
CH Cl
DH Ol
SP
BP

RESET READY
I
MN/MX GND
S'
Dt

V'"
 HARRIS 82C37A
CMOS HIGH PERFORMANCE
PROGRAMMABLE DMA CONTROLLER

• SCALED SAJI IV CMOS PROCESS

• COMPATIBLE WITH THE NMOS 82C37A

• LOW POWER OPERATION

.... .,..
•

•
COMMERCIAL, INDUSTRIAL AND MILITARY

FULLY TTL COMPATIBLE

FOUR INDEPENDANT DMA CHANNELS

TEMPERATURE RANGES

-.. ····
R
RIll

lIIII'i'

...•.
lNOTllll

.,
, ....,

,•
.... ..
..
....
....
AI

••••
AI

.,..
......•• ·
AI
• HIGH PERFORMANCE UP TO 1.6 MBYTES/SEC TRANSFERS
.om
•.. ....
• DIRECTLY EXPANDABLE TO ANY NUMBER OF CHANNELS

... " .....,

....
VC<II.'"

• UPGRADED CAPABILITIES ALLOW SOFTWARE READ OF MOST

INTERNAL REGISTERS AND STATUS BITS .UIT "
".. ...•••
....
••C"
DACKa .... ...
....
o"las
01110.
"..
.....
DACItO

......
....
n

.. ..,
0.10'
Olliao n
The Harris 82C37A Multimode Direct Memory Access (DMA) Controller is a !ONOIV ••
peripheral interface circuit for microprocessor systems. It is designed to
improve system performance by allowing external devices to directly transfer
information from the system memory. Memory-to-memory transfer capabil-
ity is also provided. The 82C37 A offers a wide variety of programmable con-
trol features to enhance data throughput and system optimization and to
allow dynamic reconfiguration under program control.

The 82C37A is designed to be used in conjunction with an external 8-bit

address register such as the 82C82 and may be expanded to any number of
channels by cascading additional controller chips.

The three basic transfer modes allow programmability of the types of DMA
service by the user. Each channel can be individually programmed to Auto-
initialize to its original condition following an End of Process (EOP).

CAUTION; These devices are sansltive to electrostatic discharge. Users should follow standard I,C. Handling Procedures.
3-97
;II HARRIS CMOS OCTAL LATCHING
82C83
INVERTING BUS DRIVER

Pinout
• FULL EIGHT BIT PARALLEL LATCHING INVERTING BUFFER
• BIPOLAR 8283 COMPATIBLE 010 VCC
• THREE STATE NON-INVERTING OUTPUTS 011 500
• PROPAGATION DELAY - 35".oc MAX. 012 50,
• A.C. CHARACTERISTICS GUARANTEED FOR;
013 502
• FULL TEMPERATURE RANGE
014 503
.10% POWER SUPPLY TOLERANCE
015 504
• CL = 300pF
016 505
• SINGLE 5V POWER SUPPLY
• POWER SUPPLY CURRENT - lOIlA MAX. STANDBY 01] 506

• OUTPUTS GUARANTEED VALID AT VCC = 2.0 VOLTS DE 50]

• COMMERCIAL,INDUSTRIAL AND MILITARY TEMPERATURE RANGES GNO STB
• 20 PIN PACKAGE ON 0.3" CENTERS

PIN NAMES
The Harris 82C83 is an octal latching buffer manufactured using a self- 010 - 01] Data Input Pins
aligned silicon gate CMOS process. This circuit provides an eight bit 500 - 50] Inverted Data Output Pins
parallel latch/buffer in a 20 pin package. The active high strobe (STB) STB Active High Strobe Input

input allows transparent transfer of data and latches data on the negative 5E Active Low Output Enable

transition of this signal. The active low output enable (OE) permits simple
interface to state-of-the-art microprocessor systems. The 82C83 provides
inverted data at the outputs.

STB OE 01 DO

X H X Hi-Z
H L L H
H
I
L
L
H
X
.
L

H"" Logic One Hi-Z = High Impedance

L = Logic Zero ,= Negative Transition
X '" Don't Care Latched to value of last data
m HARRIS CMOS CLOCK
82C848
GENERATOR DRIVER

• GENERATES THE SYSTEM CLOCK FOR CMOS OR NMOS

MICROPROCESSORS

• OSCILLATOR - STOP CIRCUITRY ALLOWS MINIMUM POWER

STANDBY CSYNC Vcc
• PIN COMPATIBLE WITH BIPOLAR 8284A AND CMOS 82C84A PClK Xl

• USES A PARALLEL MODE CRYSTAL CIRCUIT OR EXTERNAL AENl X2

FREQUENCY SOURCE
RDYl ASYNC
• PROVIDES READY SYNCHRONIZATION EFI
READY
• GENERATES SYSTEM RESET OUTPUT FROM SCHMITT TRIGGER INPUT RDY2 FIe
• CAPABLE OF CLOCK SYNCHRONIZATION WITH OTHER 82C84As or 82C84B. AlN2 OSC

• TTL COMPATIBLE INPUTS/OUTPUTS ClK RES

• VERY LOW POWER CONSUMPTION GND RESET

• 18 PIN CERAMIC OR PLASTIC PACKAGE

• SINGLE +5V POWER SUPPLY

• COMMERCIAL, INDUSTRIAL AND MILITARY TEMPERATURE RANGES

AVAILABLE
CONTROL
PIN LOGICAL 1 LOGICAL 0

F/C External Crystal

Clock Drive
The Harris 82C848 is a high performance CMOS clock generator-driver which is
designed to service the requirements of both CMOS and NMOS microprocessors RES Normal Reset

such as the 80C86, 80C88, 8086 and the 8088. The chip contains a crystal con- RDYl Bus Ready Bus not
trolled oscillator, a divide-by-three counter and complete "Ready" synchroniza- RDY2 ready

tion and reset logic. AENl Address Address

AEN2 Disabled Enabled

Static CMOS design permits operation with an external frequency source from DC ASYNC 2 Stage Ready 1 Stage Ready
to 25MHz. Crystal controlled operation to 25MHz is guaranteed with the use of Synchronization Synchronization

a parallel, fundamental mode crystal and two small load capacitors. User con- CSYNC· Oscillator Oscillator
trolled halt circuitry stops the internal oscillator and reduces the 82C848 and Stop Run

system power supply currents to standby levels.

Power consumption is a fraction of that of the equivalent bipolar circuits. This

speed-power characteristic of CMOS permits the designer to custom tailor his
system design with respect to power and/or speed requirements.
m HARRIS
CMOS OCTAL
82C86
BUS TRANSCEIVER

Features Pinout
• FULL EIGHT BIT BIDIRECTIONAL BUS INTERFACE TOP VIEW
• INDUSTRY STANDARD B2B6 COMPATIBLE PINOUT
• THREE STATE NDN·INVERTING OUTPUTS AO Vcc
• PROPAGATION DELAY 35 NSEC
• A.C. CHARACTERISTICS GUARANTEED AT RATED CL A1 80
• A SIDE· CL= 1DOpF
=
• B SIDE· CL 3GDpF A2 81
• SINGLE 5V POWER SUPPLY
• POWER SUPPLY CURRENT 10 ~A MAX Standby A3 82
• 20 PIN PLASTIC DR CERAMIC PACKAGE
• CDMMER~IAL, INDUSTRIAL AND MILITARY TEMPERATURE RANGES AVAILABLE A4 83

AS 84

A6 85
Description A7 86
The Harris 82C86 is an octal bus transceiver manufactured using a self·aligned oe 87
silicon gate CMOS process (Scaled SAJI IV). This circuit provides a full eight bit
bidirectional bus interface In a 20 pin package. The Transmit (T) control deter- GND T
mines the data direction. The active low output enable (DE) allows simple inter'
face to the 80C86 and other microprocessors, The outputs of the 82C86 are non·
inverting.
Ao·A7 LOCAL BUS DATA I/O PINS

Bo·B7 SYSTEM BUS DATA I/O PINS

T TRANSMIT CONTROL INPUT

OE ACTIVE LOW OUTPUT ENABLE

T OE A B
X H HI-Z HI·Z
H L I 0
L L 0 I
H = logical one
L = logical zero
I = Input mode
o = output mode
X = don 'I care
HI-Z = high impedance
;II HARRIS 82C87
CMOS OCTAL INVERTING
BUS TRANSCEIVER

Pinout
• FULL EIGHT BIT BIDIRECTIDNAL BUS INTERFACE TOP VIEW
• INDUSTRY STANDARD 8287 COMPATIBLE PINOUT
• THREE STATE INVERTING OUTPUTS AO vcc
•
•
PROPAGATIONDELAY
A.C. CHARACTERISTICS GUARANTEED AT RATED Cl
35 NSEC
Al eo
• A SIDE - Cl = 100pF
• B SIDE - Cl = 300pF A2 Bi
• SINGLE 5V POWER SUPPLY
• POWER SUPPLY CURRENT 10~A MAX Standby
A3 B2
• 20 PIN PLASTIC DR CERAMIC PACKAGE A4 !3
• COMMERCIAL, INDUSTRIAL AND MILITARY TEMPERATURE RANGES AVAILABLE
AS 54
A6 Bs
Description A7 56
The Harris 82C8? is an octal bus transceiver manufactured using a self-aligned OE 87
silicon gate CMOS process (Scaled SAJI IV). This circuit provides a full eight bit
GND T
bidirectional bus interface in a 20 pin package. The Transmit (T) control deter-
mines the data direction. The active low output enable (OE) allows simple inter-
face to state of the art microprocessors. Data at the outputs of the 82C8? are
PIN NAMES
inverted.
Ao-A, LOCAL BUS OATA I/O PINS

Bo-B, SYSTEM BUS OATA I/O PINS

T TRANSMIT CONTROL INPUT

OE ACTIVE LOW OUTPUT ENABLE

T OE A B
X H Hi·Z Hi-Z
H L I 0
L L 0 I
H = logical one
L = logical zero
I = input mode
o = output mode
X = don't care
Hi·Z ~ high impedance
 • INDUSTRY STANDARD 8289 COMPATIBLE PINOUT
• COMPATIBLE WITH 5 AND 8 MHz 80C86
• PROVIDES MULTIMASTER SYSTEM BUS CONTROL AND ARBITRATION
• COMPATIBLE WITH IEEE BUS STANDARD (MULTIBUS'")
• SINGLE 5V POWER SUPPLY !2 vcc
• POWER SUPPLY CURRENT
• 10 ~A MAX standby
iOI
• 1 mA/MHz Operating SYSBIQU So
• 20 PIN PLASTIC DR CERAMIC PACKAGE
RESB ClK
• COMMERCIAL, INDUSTRIAL AND MILITARY TEMPERATURE RANGES AVAILABLE
rn:R ~
1"Im ~
Description P!O ANYRQST
The Harris 82C89 bus arbiter is manufactured using a self-aligned silicon gate fml Am
CMOS process (Scaled SAJI IV). This circuit along with the 82C88 bus mfN aIfO
controller, provides full bus arbitration and control for multi-processor systems.
The 82C89 is typically used in medium to large 80C86 or 8oC88 systems where GND !U!Y
access to the bus by several processors must be coordinated.
The 82C89 also provides high output current and capacitive drive to eliminate the
need for additional bus buffering.

MULTI BUS
COMMAND
80C881socaa { SIGNALS
STATU's

PROCESSOR
CONTROL
I ~
lOCK
ClK

RESB
ANYRQST
lOB
AEN

SYSBIQU
I SYSTEM
SIGNALS

CAUTION: Eleclronic devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.

3.,102
4-2

4-3
HD-6120 12 Bit High Performance Microprocessor 4-3
HD-6121 I/O Controller 4-22
HM-6100 12 Bit Static Microprocessor 4-30
HD-6101 Parallel Interface Element 4-51

HD-6431 Hex Latching Bus Driver 4-59

HD-6432 Hex Bi-directional Bus Driver 4-62
HD-6433 Quad Bus Separator/Driver 4-65
HD-6434 Octal Resettable Latch 4-68
HD-6436 Octal Bus Buffer/Driver 4-71
HD-6440 Latch Decoder/Driver 4-74
HD-6495 Hex Bus Driver 4-78
82C82 CMOS Octal Latching Bus Driver 4-81
82C83 Octal Latching Inverting Bus Driver 4-82
82C86 Octal Bus Transceiver 4-83
82C87 Octal Bus Transceiver 4-84
m HARRIS
CMOS HIGH SPEED
HD-6120
12 BIT MICROPROCESSOR

• lOW POWER, 50 MW OPERATING, 2 MW STATIC

• SINGLE SUPPLY - 5V OUT 1 40 VCC
• OPERATION FROM DC TO 5.1 MHZ DMAGNT 2 39 READ
• INDUSTRIAL AND MiliTARY TEMPERATURE RANGES 15MAREQ 3 38 WRITE
• ON·CHIP CRYSTAL OSCillATOR CIRCUITRY SKiP 4 37 MEMSEl
• ON·CHIP EXTENDED MEMORY ADDRESSING-32K MAIN MEMORY, 32K CONTROL PANEL RUN/HlT 5 36 IOCLR
• OPTIMIZED MICRO-CODE MINIMIZES THE NUMBER OF CLOCK CYCLES REQUIRED FOR RUN 6 35 i:XOAR
All INSTRUCTIONS RESET 7 34 LXMAR
• TWO ON·CHIP STACK POINTERS ACK 8 33 i:XPAR
• SIMPLIFIED MEMORY AND 1/0 CONTROL SIGNALS FOR EASY HARDWARE INTERFACING OSCIN 9 32 DATAF
• VECTORED INTERRUPT CAPABiliTY OSCOUT 10 HD-6120 31 INTGNT
• SOFTWARE IS PAGE RElOCATABlE iFEi'CFi 11 30 iNTREQ
DXO 12 29 CPREQ
Description DX1 13 28 STRTUP
DX2 14 27 EMA2
The HO·6120 is a general purpose high speed, CMOS 12 bit microprocessor. It is DX3
designed to recognize the instruction set of Oigital Equipment Corporation'S 15 26 c1/Ci
POp·a/E' minicomputer. DX4 16 25 co/Co
DX5 17 24 DX11
Many architectural, functional and processing enhancements have been designed DX6 18 23 DX10
into the 6120 such that it can provide much higher system performance than its DX7 19 22 DX9
predecessor, the 6100. VSS 20 21 DX8

The 6120 is targeted toward the experienced pop·a' or 6100 user. Twelve bit
accuracy, rapid interrupt response, battery backup and low power (sealed
enclosure) capability all equate to a processor ideally suited to real time control
applications such as data acquisition, industrial control and harsh environment
military systems.

CPU 12 DX
CONTROL BUS
XTAl
INPUTS

INTERRUPT 12
CONTROL 1/0
DMA CONTROL
AND

DEV
CONTROL
DEV
CONTROL
 Supply Voltage +8.0 VOLTS
Operating Voltage Range +4Vto +7V
Input/Output Voltage Applied VSS-0.3V to VCC+0.3V
Storage Temperature Range -65°C to +150°C
Operating Temperature Range
Industrial (-9, -9+) -40°C to +85°C
Military (-2, -8) -55°C to +125°C
Maximum Power Dissipation 1 Wall

SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS

VIH LOGICAL ONE 70% VCC V
INPUT VOLTAGE
VIL LOGICAL ZERO 30% VCC V
INPUT VOLTAGE
VIH(CLK) LOGICAL ONE VCC-0.5 V 50% duty cycle
CLOCK VOLTAGE Ir, If '" 20 ns
VIL(CLK) LOGICAL ZERO VSS+0.5 V 50% dUly cycle
CLOCK VOLTAGE Ir, If '" 20 ns
VTH+ SCHMITT TRIGGER 50% VCC VCC-0.5 V RESET, DMAREQ, CPREO
POSITIVE
THRESHOLD
VTH- SCHMITT TRIGGER 0.5 30% VCC V RESET, DMAREO, CPREO
NEGATIVE
THRESHOLD
VOH LOGICAL ONE VCC-0.5 V 10H = -1.6mA
OUTPUT VOLTAGE
VOL LOGICAL ZERO 0.5 V 10L = 1.6mA
OUTPUT VOLTAGE
ilL INPUT LEAKAGE -10 10 IJ.A OV",VIN",VCC
CURRENT
10 OUTPUT LEAKAGE -10.0 10.0 IJ.A OV",VO",VCC
CURRENT
ICC POWER SUPPLY 500 IJ.A VIN=VCC or GND
STANDBY CURRENT VCC = 5.25 V
RESET STATE
OUTPUTS OPEN
ICC' POWER SUPPLY 10 ma VIN=VCC or GND
OPERATING VCC = 5.25 V
F = 5.1 Mhz
OUTPUTS OPEN
10SH HOLD CURRENT -0.2 -0.6 ma Vout = VCC-1.0V
DURING DMAGNT -10.0 lJ.a Vout = OV
LXMAR, LXPAR, READ,
WRITE, OUT AND MEMSEL
lOSS HOLD CURRENT -1.6 -10.0 ma Voul = OV
DURING lOT CO, C1, AND SKiP
SAMPLE TIMES OUTPUTS
lOSS HOLD CURRENT -50 -250 lJ.a Voul = OV
DURING lOT INTREO OUTPUT
SAMPLE TIMES
CIN' INPUT 5 pI FREO = 1 MHZ
CAPACITANCE TA=25'C
VIN=VCC or GND
COUT' OUTPUT 15 pf FREO = 1 MHZ
CAPACITANCE TA=25'C
VIN=VCC or GND
• Guaranteed and sampled, but not 100% tested

4-4
 A.C. ELECTRICAL CHARACTERISTICS; VCC=5.0V±5%; TA=lndustrial or Military;
CL=50 pf, FREQ=5.1 MHZ

SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS

F OPERATING FREQUENCY 0 5.1 Mhz

T MINOR CYCLE PERIOD 392 ns T = 2/F

TL LXMAR, LXPAR, LXDAR 125 ns F=5.1 Mhz

PULSE WIDTH

TAS ADDRESS SET UP 60 ns

TIME

TAH ADDRESS HOLD TIME 180 ns

TREAD READ ACCESS TIME 720 ns

TRS READ SET UP TIME 135 ns

TRH READ HOLD TIME 20 ns MEMORY

OPERATIONS
TRP READ PULSE WIDTH 425 ns

TRD READ PULSE DELAY 40 ns

TWPD WRITE PULSE DELAY 200 ns

TWS WRITE SET UP TIME 375 ns

(ALL NON lOT)

TWP WRITE PULSE WIDTH 425 ns

(ALL NON lOT)

TWH WRITE HOLD TIME 200 ns

(ALL NON lOT)

TWSIO WRITE SET UP TIME 200 ns

(lOT)

TWIO WRITE PULSE WIDTH 375 ns

(lOT)

TWHIO WRITE HOLD TIME 125 ns

(lOT)

TDA READ ACK DELAY 150 ns

FOR NO WAIT

TXA WRITE ACK DELAY 150 ns F=5.1 Mhz

FOR NO WAIT

The transient current required to charge and discharge the 50 pF This current spike may cause a large negative voltage spike on
load capacitance specified in the 6120 data sheet is determined by VCC, which could cause improper operation of the device. To filter
i = CL (dv/dt) out this noise, it is recommended that a 0.1 IJ-F ceramic disk
decoupling capacitor be placed between VCC and GNO at each
Assuming that all OX outputs change state at the same time and device, with placement being as near to the device as possible.
that dv/dt is constant;
i ~ CL (VCC x 80%) It is recommendedlthat for systems with greater than 50 pF loading
on the OX outputs that Harris HO-6432 CMOS Hex Bi·directional
tA/tF bus drivers be used to buffer the 6120 from the rest of the system.
where tR=20 ns, VCC=5.0 volts, CL=50 pF on each of twelve The HO-6432 bus driver has \luaranteed performance spec·
outputs. ifications up to a 300 pF load.
i ~ (12 x 50 x 10-12) x (5.0v x 0.8)/(20 x 10-9)
~ 120 mA
 I-T--I
I-TL"'1
~r:::J 1_------
r-TAS~ I

-II
c~~E~~21 ADDRr }J"'---_~----

Mt ~ T~ TRH

~AD

ACK 1IIIIIIIn l\\\\\

OuT d 11 t- TRD

I•' ... _
I I
I Ii"" INSTRUCTION FETCH II
DAi'AF @ ,..-INDIRECT READ ~

-t TL r-
L~ ~~ •••••r-
D"E~~2Cl .=:J<
rn ADDRESS ~ DATA ><==..
I r-TWS-j r- TWH

I --j·TXA t--
LTWP~
ACK I I I I I I I I I I I I I I II
i K\ \ \ \

iiATAF @c
I INDIRECT ~

I
MINOR
CYCLES I-- T --l

L~Or -=oJM _I ~r
~
DXE~~2Cl,::::J, ADDRESS >----{ DATA ~ DATA 'C..
ReAo
I !-TRS++TRH I--TWS-j I-
TWH

--I~LTRP~
I-TREA~ I
I
WRITE I I ~ TWP ~

MEMSEL ------~I -I ------"'- ~r__

H I H--TXA

II II II II II J L\ \ \ v I I I I I I II
TRD---1_f- __

~t;:t8X&<;! <'NDIRECT I
MEMORY READ-MODIFY-WRITE OPERATION

--in!+-
LXDAR I I r-
ox --< '. TAS
.'. .'
I TAH

lOT CMO
I
<x>o<s DATA ) '---D-AT-A--X:=

I I I ~:~;'~TWHIO rTRSt-TTH

CO,Cl,EMA2 m
I I Ii DATA' I~
~TR~

I
jTRH

~
I
SKiP ~tTWPD ~TR~ r TRH
I
I I f+- --J
I
TRP
I C1 = H -I

I I ~ \-T:~~~L
II Cl ~ H

TXAM I TDA I. ~ I
1IIIIInn/i t\ SV I n nl 1\\ \ \ \

DATA'~ _

NOTES Operation IS shortened one Miner Cycle If READ IS not executed .

• Read Data must be held until the r1SInQ edqe 01 LXDAR lor Read lOTs.
iiEAii ------1
r- TRP ---,

I_---------
TRD--+1 -1 r- TRD

777771 I ~ TRS
I

DX~DATA~ ~
TDA+-i I
ACK 7777777777 I K\ \ \ \ \ \ \ \ \ \ \ \ \ \

I-- TWP --j

WR'i'TE ----- •••••1 _

I I
\\\\\\\\1 I
r-
OUT

I ~TWS-1 TWH

DX~ DATA ~

ACK 777777 ;j7;I l\\\\\\\\\\

 Active
I/O Pin Symbol Level Description

0 1 OUT low Bus timing control output which is low during all bus write or addressing operations. This signal
is used to enable outbound bus drivers.

0 2 DMAGNT High Direct memory access grant output - OX, CO, C1, and EMA2 lines are high impedance.

I 3 DMAREQ low Schmitt trigger input. Direct memory access request- DMA is granted at the end of t~
bus operation. Upon DMA grant, the 6120 suspends program execution until the DMAREQ
line is pulled high.

I 4 SKIP low Input which causes the 6120 to skip the next instruction if low during an I/O instruction.

I 5 RUN/HlT Pulsing the RUN/HlT input causes the 6120to alternately run and ha~Changing the state of
the internal RUNHlT flip flop on the positive transition of the RUN/ line.

0 6 RON low This output indicates the operating state of the 6120. It is low at all times except during the reset
and helt states.

I 7 RESET low Schmitt trigger input. Clears the AC and the memory extension registers and loads 7777
(octal) into the PC. RUNHlT is set. The STRTUP line controls whether execution starts in
control panel or main memory. RESET must be held low~t 42 clock cycles ~e clock
starts running in order to initialize the timing generator. lXDAR is held low while RESET is low,
and remains low until after the positive transition of RESET and 10ClR.

I 8 ACK High This Input indicates that peripheral or external memory is ready to transfer data. The 6120 read
or write state gets extended as long as ACK is low. During this time the 6120 is in the lowest
power state with clocks running.

I 9 OSCIN Input to crystal oscillator amplifier. (Also external clock input.)

0 10 OSCOUT Output of crystal oscillator amplifier.

0 11 iF'EfCH low Instruction fetch cycle output.

I/O 12-19, DXO- High Multiplexed bidirectional data in, data out and address
21-24 DX11 lines. (DXO=MSB, DX11 =lSB.)
20 VSS Most negative supply voltage.

I/O 25 CO/CO Multiplexed extended memory address (EMA) active high output MSB end peripheral
device control line active low input from the peripheral device during an I/O transfer.
I/O 26 C1/C1 Multiplexed EMA bit 1 end peripheral control line. See CO.

0 27 EMA2 High low order extended memory address output.

I 28 STRTUP This input is tied to either VCC or VSS. If tied to VSS, the 6120 makes a panel request (caused
by the PWRON flag) as soon as RESET goes to VCC. 7777 is stored in location 0000 offield 0
of panel memory. If STRTUP is tied to VCC, PWRON does not cause a panel request. Instead,
the CPU starts running in location 7777 of field 0 of main memory. location 0000 of main
memory is not altered.
I 29 CPREQ low Schmitt trigger input. External control panel request - a dedicated interrupt which bypasses
the normal device interrupt request structure. CPREQ causes a control panel interrupt request
by setting the bootstrap flag with the negative going transition of CPREQ. Therefore, this input
is transition rather than level sensitive.

I 30 INTREQ low Peripheral device interrupt request input.

0 31 iN'roNT low Peripheral device interrupt grant output.

0 32 DATAF low Output which is low whenever the Data Field is placed on the CO, C1 and EMA2 lines.
0 33 lXPAR low Output which causes control panel memory address register to be loaded. Same as 'LX'MAR,
but for control panel memory operations.
0 34 lXMAR low Output which causes main memory address register to be loaded. Address is strobed into the
main memory at the falling edge of'LX'MAR.

0 35 lXDAR low Output which causes device address register to be loaded. Same as LXMAR or lXPAR, except
for lOT operations. Also used to distinguish between 10ClR signals. See 10ClR below.
0 36 10ClR low Output which is low when RESET is low, or when CAF instruction is given. Us~ear I/O
flags. If caused by RESET, lXDAR is low during and after the trailing edge of 10ClR.
0 37 MEMSEl low Memory select. During memory operations, this output puises to VSS at bus read and write
times.
0 38 WRiTE low Write pulse. This output is low during all bus data write operations; memory, I/O, and write to
switch register.
0 39 READ low Read pulse. This output is low during all bus read operations; memory, I/O and switch register.
It also serves the function of enabling inbound bus drivers.
40 VCC Positive supply voltage.
 ACCUMULATOR (AC) PROGRAM COUNTER (PC)
The AC is a 12-bit register with which arithmetic and logical The 12-bit PC contains the address of the memory location
operations are performed. Data words may be fetched from from which the next instruction is fetched. During an instruc-
memory to the AC or stored from the AC into memory. tion fetch, the PC is transferred to OL and the PC is then
Arithmetic and logical operations involve two operands, one incremented by 1. When there is a branch to another address
held in the AC and the other fetched from memory. The result in memory, the branch address is set into the PC. Branching
of the operation is left in the AC. The AC may be cleared, normally takes place under program control. A skip (SKP,
complemented, tested, incremented or rotated under program SMA, SZA, SNL, etc.) instruction increments the PC by 1
control. The AC also serves as an input-output register. All (again), thus causing the next instruction to be skipped. The
programmed data transfers pass through the AC. skip instruction may be unconditional or conditional on the
state of the AC and/or LINK. During an input-output operation,
Link (L)
a device can also cause the next instruction to be skipped.
L is a 1-bit flip flop that serves as a high-order extension of the
AC. It is used as a carry flip flop for 2's complement arithmetic. TEMPORARY REGISTER (TEMP)
A carry out of the ALU complements L. L can be cleared, set,
The 12-bit TEMP register latches the result of an ALU
complemented and tested under program control and rotated
operation before it is sent to the destination register to avoid
as a part of the AC.
race conditions. The TEMP is also used as an internal register
MQ REGISTER (MQ) during instruction execution.

The MQ is a 12-bit temporary register which is program INSTRUCTION REGISTER (IR)

accessible. The contents of AC may be transferred to the MQ
for temporary storage. MQ can be OR'ed with the AC and the During an instruction fetch, the 12-bit IR contains the instruc-
result stored in the AC. The contents of the AC and the MQ tion that is to be executed by the 6120.
may also be exchanged.
STACK POINTERS (SP1 and SP2)
OUTPUT LATCH (OL)
The stack pointers are two twelve-bit registers which hold the
While accessing memory or I/O, all data or addresses gener- address of the next stack storage location. PPCX or PACX
ated by the 6120 on the DX bus are held in the OL for the time instructions cause post-decrement of the contents of stack
required on the bus. This frees the 6120 internal bus for other pointer SPX. RTNX or POPX cause a pre-increment of the
uses during these operations. The output latch can also be contents of the stack pointer. Stack pointers are loaded from,
read to the 6120 internal bus so that it can function as a and read into, the AC. They may also be used as program-
temporary holding register for internal operations. controlled temporary registers.

INSTRUCTION SAVE FIELD (ISF)

The 3-bit ISF is loaded with the contents of the IF upon
The 3-bit Instruction Field holds the memory field from which
granting of an interrupt. The ISF may be read into the AC. It is
all instructions, all indirect address pointers and all directly
cleared by RESET.
addressed operands are obtained. It may be read into the AC,
and loaded from the lB. It is cleared by RESET.
DATA FIELD (OF)
The 3-bit Data Field holds the memory field from which all
indirectly addressed operands are obtained. The DF may be
loaded from instruction bits, from the AC or from the DSF. It
The 3-bit Instruction Buffer serves as a holding register for may be read into the AC. It is cleared by RESET.
instructions which change the IF. Instead of changing the IF
directly, field bits are loaded into the IB, and transferred to the DATA SAVE FIELD (DSF)
IF atthe nextJMP, JMS, RTN1 or RTN2. The IB may be loaded The 3-bit DSF is loaded with the contents of the DF upon
from instruction bits, from the AC or from the ISF. The IB is granting of an interrupt. The DSF may be read into the AC. It is
cleared by RESET. cleared by RESET.

A 15-bit address is sent on the CO, C1, EMA2 and OX lines for Output transfers are similar to input transfers. The address is
memory reference instructions. The LXMAR or LXPAR defined as given above. ACK controls the length of time for
signals cause an external register to store the address which the WRITE signal is low, similar to the READ line
information~ired. When executing an input-output control.
instruction, LXDAR causes an external register to be loaded
with device address and control information. During an instruction fetch the instruction to be executed is
retained internally and then executed. During the sequencing
Memory data is read for an input transfer (READ). ACK of the instruction the external request lines are sampled by the
controls the transfer duration. If ACK is low during input priority network. The state of this network decides whether the
transfers, the 6120 waits with the READ line low. The high machine is going to fetch the next instruction in sequence or
state of the ACK signal causes the 6120 to continue. service one of the internal or external request lines.
 GENERAL DESCRIPTION is low. LXMAR, LXPAR, READ, WRITE, MEMSEL, INTGNT
The external request lines and the internal request flags are and IFETCH are held high. IOCLR is held low. After RESET is
sampled in an internal priorit~work. The internal riority is changed from low to high, iOClJl is made high. LXDAR is held
RESET, DMAREQ, RUN/RIT. CPREQ, INTRE ,and low for one minor cycle after IOCLR is high. DMAGNT and
IFETCH. The state of the priority network determines the next OUT are low. The first LXMAR or LXPAR occurs 5-1/2 minor
operation. cycles after IOCLR goes high. The PC is set to 7777 (octal)
and execution commences in control panel or main memory,
IFETCH depending on whether the STRTUP input is low or high
If no external or internal requests are pending, the 6120 respectively. If execution commences in control panel mem-
fetches the next instruction pointed to by the contents of the ory, the FZ flag is set, the Panel Data flag is cleared, and 7777
PC. The IFETCH line is low during the cycle in which the is deposited in location 0000 of control panel memory before
instruction is fetched. beginning instruction execution at location 7777. If execution
commences in main memory, location 0000 of main memory
RESET is not modified.
RESET initializes all internal flags and clears the AC, LINK RUN/HLT
and MQ. All memory extension bits (IF, IB, OF, ISF and OS F)
are cleared. The interrupt enable and interrupt inhibit flip flops The RUN/HLT line changes the state of the RUNHLT.!!!P...!!QE.
are cleared. RUNHLT is set to the run state. The RUN line is This flip flop .!§.initially placed in the run state by RESET.
held high by RESET. The states of SPl and SP2 are undefined Pulsing RUN/HLT low causes the 6120 to alternately run and
at power up, and are unaffected by RESET. halt. This is true whether executing in main memory or control
memory. The RUN/HLT line is normally hl.9..b.:The 6120
Upon application of power, the internal timing generator is recognizes the positive transition of the RUN/HLT signal. The
completely initialized within 42 clock pulses after power is HLT instruction (7402 octal) does not cause the RUNHLT flip
within limits with RESET held low. flop to be cleared, but causes entry into panel mode with the
The 6120 remains in the reset state as long as the RESET line HLTFLG set.

The 6120 has a basic addressing capacity of 4096 12-bit significant 5 bits of a 12-bit memory address denote the page
words. The addressing capacity is extended by the internal number and the 7 low order bits specify the address of the
extended memory control hardware. The memory system is memory location within the given page.
organized in 4096 word groups, called memory fields. The first
During an instruction fetch cycle, the 6120 fetches the
4096 words of memory are in field O. If a full 32K block of
instruction pointed to by the IF, PC, and address strobes
memory is installed, the uppermost memory field will be
LXMAR or LXPAR. The contents of the PC are transferred to
numbered 7. Two 32K word blocks of memory may be con-
the OL. The PC is incremented by 1. The PC now contains the
nected to the 6120. One of these blocks is known as main
address of the 'next' sequential instruction. The OL now
memory and the other is known as panel memory.
contains the address of the 'current' instruction which must be
In any given memory field, every location has a unique 4 digit fetched from memory. Bits 0-4 of the OL Identify the current
octal (12 bit binary) address, 0000 to 7777 (0000 to 4095 page, that is, the page from which instructions are currently
decimal). Each memory field is subdivided into 32 pages of being fetched. Bits 5-11 of the OL Identify the location within
128 words each. Memory pages are numbered sequentially the current page. (Page zero, by definition, denotes the first
from page 00, containing octal addresses 0000-0177, to page 128 words of memory within a field, octal addresses 0000-
37 (octal), containing octal addresses 7600-7777. The most 0177.)

The memory reference instructions operate on the contents of Indirectly through this pointer. Upon execution, the MAl
a memory location or use the contents of a memory location to operates on the contents of the location Identified by the
operate on the AC or the PC. Bits 0-2 of a memory reference address contained in the pointer location. The pointer is
instruction specify the operation code, or opcode, and the 9 obtained from the current Instruction Field; the data is In the
low-order bits specify the operand address. Bits 5-11, the page current Data Field.
address, identify the location of the operand on a given page, It should be noted that locations 0010-0017 (octal) In page 0 of
butthey do not identify the page itself. The page is specified by
any field are autoindexed. If these locations are addressed as
bit 4, called the page bit. If bit 4 is a 0, the page address is
Indirect pointers, the contents are incremented by 1 and
interpreted as a location on page O. If bit 4 is a 1, the page
restored before they are used as the operand address. These
address is interpreted to be on the current page. The entire
locations may, therefore, be used for indexing applications.
12-bit address, consisting of the 7 low-order bits from the
During the memory write operation, the OF appears on CO,
instruction and either 0 or the contents of the OL in the 5
C2, and EMA2. Indirect reference to auto index registers from
high-order bits is known as the Instruction address, or IA. The
page 0 work as defined whether the page bit is "1" or "0".
IF provides the 3 high-order bits of the complete 15-bit
address, IA. Data is represented in two's complement integer notation. In
this system of notation, the negative of a number is formed by
Other locations are addressed by utilizing bit 3. When bit 3 is a
complementing each bit in the data word and adding "1" to the
0, the operand is directly addressed, and IA is the location of
complemented number. The sign is indicated by the most-
the operand. When bit 3 is a 1, the operand is indirectly
significant bit. In the 12-bit word used in the 6120, when bit 0 is
addressed, and the contents of IA specify the location of the
a "0", it denotes a positive number and when bit 0 is a "1", it
operand. To address a location that is not on page 0 or the
denotes a negative number. The number range for this system
current page, the absolute address of the desired location is
Is +3777 to -4000 octal (+2047 to -2048 decimal).
stored in one of the 256 directly-addressable locations as a
pointer address. The instruction addresses the operand
amount of time required for a single discrete instruction. Format" templet shows the order in which the microcoded
Instructions listed under Groups 1,2 and 3 represent the most operations are performed. "Introduction to Programming" by
commonly used microcoded instructions for these groups and Digital Equipment Corporation further explains the PDP-S"
are not a complete listing of all possible instructions. The instruction set and the use of microprogramming. This
general rule of thumb is that if an instruction can be rep- handbook is also available from Harris Semiconductor.

The HD-6120 has been designed to work with either a parallel C2 = 20pf. is normally used. For CL = 32pf. Cl and C2 would
resonant, fundamental mode crystal or an external frequency be approximately 47pf. The actual values are normally not
source. critical unless an ultra precise frequency is desired.

EXTERNAL CRYSTAL
When using an external crystal, two capacitors and a resistor C1
are required to complete the oscillator circuit. Table 1 lists the OSCIN
9

E'
required crystal characteristics and Figure 1 shows the correct
circuit connections. 10
c::J MO
HD-6120

10
OSCOUT
C2
Parameter "TYpical Characteristic
Frequency 2.4 - 5.1 Mhz
Type of Operation Parallel resonant, AT cut,
Fundamental mode EXTERNAL FREQUENCY SOURCE
Load Capacitance CL = 20pf or 32pf
When using an external frequency source, the duty cycle
Rse,'es (Max.) 200 {1 at5.1 Mhz
should be 50/50 with rise and fall times less than 20ns. Input
voltage levels should be V'H<>VCC-0.5V and V'L<s0.5V. The
OSCIN pin of the HD-6120 is used in this case with the
The load capacitors Cl, C2 are chosen such that the total OSCOUT pin left open. The Harris S2CS4A CMOS Clock
(including stray) capacitance seen by the crystal matches the Generator is an excellent external frequency source which
specified load capacitance (CL). For CL = 20pf. a value of Cl = provides three outputs at different divide ratios (+1, +3, +6).

Memory Reference Instructions

MICROINSTRUCTION FORMAT
4 5 6 7 8

Indirect Addressing Memory Page

0= Direct 0= Page 0
1 = Indirect 1 = Current Page

Mne- Opcode Minor Cycles Operation

monic Olr Ind Auto
AND Oxxx 7 10 12 LOGICAL AND: Causes a bit-by-bit boolean AND between the contents of the Accumulator and thll
contents of the effective address (xxx) specified by the instruction. The result is left in the AC and the
data word in the referenced location is not altered.
TAD 1xxx 7 10 12 TWO'S COMPLEMENT ADD: Performs a binary two's complement addition between the specified
data word and the contents of the AC; the result is left in the AC. If a carry out occurs, the state of the
Link is complemented. If the AC is initially cleared, this instruction acts as a load from memory.
ISZ 2xxx g' 12' 14' INCREMENT AND SKI P IF ZERO: The contents of the effective address is incremented by 1 and
restored. If the result is zero, the next sequential instruction is skipped.
DCA 3xxx 7 10 12 DEPOSIT AND CLEAR THE ACCUMULATOR: The contents of the AC are stored in the effective
address and the AC is cleared.
JMS 4xxx 7 10 12 JUMP TO SUBROUTINE: The contents of the PC is stored in the effective address and the effective
address + 1 is stored in the PC. The Link, AC and MQ are unchanged.
JMP 5xxx 4 7 g JUMP: The effective address is loaded into the PC thus causing program execution to branch to a new
location.
 Group 1 Operate Instructions
All group 1 instructions require 6 minor cycles,
except those performing an RTR, RTl, or SSW
instruction (8 minor cycles).

0 2 3 4 5 6 7 8 9 10 11

logical Sequence:
GJ ClA Cll CMA CMl
Bit
GJ R1
R2
R2
R3
R3
lAC

1-ClA, Cll 0 0 0 No Rotate

2-CMA, CMl 0 0 1 BSW
3-IAC 0 1 0 RAl
4 - RAR. RAl, RTR. RTl, BSW, R3l 0 1 1 RTl
1 0 0 RAR
1 0 1 RTR
1 1 0 R3l
1 1 1 Do Not Use

Mne- Opcode logical Operation

monic Sequence
NOP 7000 1 No operation.
lAC 7001 3 Increment accumulator-the contents of the AC is incremented by 1. Carry out complements the LINK.
BSW 7002 4 Byte swap - ACO-5 are exchanged with AC6-11 respectively. The LINK is not changed.
RAl 7004 4 Rotate accumulator left-the contents olthe AC and LINK are rotated one binary position to the left. ACO
is shifted to LINK and LINK is shifted to AC11.
RTl 7006 4 Rotate two left - equivalent to two RAL:s.
RAR 7010 4 Rotate accumulator right-the contents of the AC and LINK are rotated one binary position to the right.
AC11 is shifted into the LINK, and LINK is shifted to ACO.
RTR 7012 4 Rotate two right - equivalent to two RAR's.
R3l 7014 4 Rotate AC (but not LINK) left 3 places. ACO is rotated into AC9, AC1 into AC10, etc.
CMl 7020 2 Complement LINK-the contents of the LINK is complemented.
CMA 7040 2 Complement accumulator - the contents of the AC is replaced by its 1's complement.
CIA 7041 2,3 Complement and increment accumulator - the contents of the AC is replaced by its 2's complement.
Cll 7100 1 Clear LINK-the LINK is made O.
Cll RAl 7104 1,4 Clear LINK, rotate left.
Cll RTl 7106 1,4 Clear LINK, rotate two left.
Cll RAR 7110 1,4 Clear LINK, rotate right.
Cll RTR 7112 1,4 Clear LINK, rotate two right.
STl 7120 1,2 Set the LINK -load binary 1 into LINK.
ClA 7200 1 Clear accumulator -load AC with 0000.
ClAIAC 7201 1,3 Clear and increment accumulator-load AC with 0001.
GlK 7204 1,4 Get LINK-place LINK in AC11; clear ACO·10 and LINK.
STA 7240 1,2 Set accumulator- make AC=7777.
ClA Cll 7300 1 Clear AC and LINK.
 Group 2 Operate Instructions
All group 2 instructions require 7 minor cycles,
except OSR and LAS (8 minor cycles).

Logical Sequence:
1-(BIT 8=0)-SMA or SZA or SNL
- (BIT 8= 1) - SPA and SNA and SZL
2-CLA
3-0SR, HLT

Mne- Opcode Loglcall Openltlon

monic sequence

NOP 7400 1 No operation

HLT 7402 3 Set the HLTFLG. Causes entry Into panel mode Instead of executing the next Instruction provided IIFF
Is not set. If IIFF Is set, panel mode Is entered aftertheJMP, JMS, RTN1 or RTN2 which clears IIFF.
This Instruction In panel mode does not cause a re-entry Into panel mode, but does set HLTFLG.
OSR 7404 3 OR with switch register-the contents of an external device are "OR"ed with the contents of the AC,
and the result stored In the AC. The contents of the OF are available for device selection.
SKP 7410 1 Skip - the content of the PC Is Incremented by 1, to skip the next Instruction.
SNL 7420 1 Skip on non-zero LINK - skip If LINK one
SZL 7430 1 Skip n LINK zero
SZA 7440 1 Skip on zero accumulator-aklp If ACmoooo
SNA 7450 1 Skip on non-zero accumulator
SZASNL 7460 1 Skip If AC-OOOOor If L1NK-1
SNASZL 7470 1 Skip n AC not ‫סס‬oo and n LINK Is zero
SMA 7500 1 Skip on minus accumulator (ACO-1)
SPA 7510 1 Skip on positive accumulator (ACO-O)
SMASNL 7520 1 Skip If AC Is minus or n LINK Is 1
SPASZL 7530 1 Skip If AC Is plus and If LINK Is 0
SMASZA 7540 1 Skip If AC Is minus or zero
SPASNA 7550 1 Skip n AC Is positive and non-zero
SMASZA 7560 1 Skip If AC Is minus or If AC Is -‫סס‬oo or If LINK Is 1
SNL
SPASNA 7570 1 Skip If AC Is positive, nonzero and I!-LINK Is zero
SZL
CLA 7600 2 Clear accumulator
LAS 7604 2,3 Load accumulator from switch register
SZACLA 7640 1,2 Skip If AC-oooo, then clear AC
SNACLA 7650 1,2 Skip on non-zero accumulator, then clear AC
SMACLA 7700 1,2 Skip on minus AC, then clear AC
SPACLA 7710 1,2 Skip on positive AC, then clear AC
 Group 3 Operate Instructions
If bits 6, 8, 9 or 10 are set to a one, instruction execution is not altered but the instruction becomes uninterruptable by
either~el or normal interrupts. That is, the next instruction is guaranteed to be fetched barring a reset, DMAREO or
RUN/HLT flip flop in the HLT state.

Group 3 Operate Instructions

All group 3 instructions require 6 minor cycles.
MICROINSTRUCTION FORMAT

0 2 3 4 5 6 7 8 9 10 11

CU ~ 1 CLA MOA
c=J MOL
~ 1

Logical Sequence: BIT 4 5 7

1-CLA 0 0 0 NOP
2-MOA, MOL 0 0 1 AC--+MO,O--+AC
3-ALL OTHERS 0 1 0 (MO + AC)--+AC
• - CAUSES INSTRUCTION TO 0 1 1 MO--+AC
IGNORE INTERRUPTS IF A "1" 1 0 0 O--+AC
1 0 1 O--+AC:O--+MO
1 1 0 MO--+AC
1 1 1 MO--+AC, O--+MO

+ denotes logical OR

Mne- Opcode Logical Operation

monic Sequence

NOP 7401 3 No operation

MOL 7421 2 MO register load-the MO is loaded with the contents of the AC and the AC is cleared. The original
contents of the MO is lost.
MOA 7501 2 MO "OR" with accumulator-the contents of the MO is "OR"ed with the contents of the AC, and the
result left in the AC. The MO is not modified.
SWP 7521 3 Swap contents of AC and MO - the contents of the AC and MO are exchanged
CLA 7601 1 Clear accumulator
CAM 7621 3 Clear AC and MO (actually a CLA MOL)
ACL 7701 3 Load AC with contents of MO
CLA SWP 7721 3 Clear AC, then swap - the MO is loaded into the AC; 0000 is loaded into the MO
The following lOT instructions are internally decoded to case of a ReTurN from control panel memory via a RTN1 or
perform stack operations using internal stack point~ RTN2 instruction. In this case, the main memory stack is
and SP2. These are internal lOT instructions; the LXDAR accessed by the instruction fetched from panel memory. Two
signal is not generated. If instructions are being fetched from separate stacks may be maintained - one for the PC, the
main memory, the stacks are located in field 0 of main second for the AC. An increment of the stack pointer is defined
memory. If instructions are being fetched from panel memory, as a pop off the stack.
the stacks are located in field 0 of panel memory, exceptfor the

Mne- Opcode Operation

monic
PPC1 6205 PUSH PC ON STACK. The contents of the PC arelncremented by one and the result Is loaded into the memory location
pointed to by the contents of SP1. SP1 is then decremented by 1.
PPC2 6245 PUSH PC ON STACK. The same as PPC1 except that SP2 is used as the memory pointer.
PAC1 6215 PUSH AC ON STACK. The contents of the AC is loaded into the memory location poir.ted to by the contents of SP1. The
contents of SP1 is then decremented by 1.
PAC2 6255 PUSH AC ON STACK. The same as PAC1 except that SP2 is used as the memory pointer.
RTN1 6225 RETURN. The contents of the stack pointer (SP1) Is incremented by one. The contents of the Instruction Buffer (IB) is
loaded into the Instruction Field (IF) register. If a prior PEX instruction was executed, the Controi Panel Flip Flop
(CTRLFF) is cleared. If the Interrupt Inhibit Flip Flop (IIFF) is set, then the Force Zero (FZ) flag is cleared. The contents
of the memory iocation pointed to by SP1 is loaded into the PC. Prior PEX is cieared.
RTN2 6265 Same as RTN 1 except that SP2 Is used as the stack pointer.
POP1 6235 The contents of SP1 is iMremented by 1. The contents of the memory location pointed to by SP1 is then loaded into the
AC.
POP2 6275 Same as POP1 except that SP2 is used as the stack pointer.
RSP1 6207 The contents of SP1 is loaded into the AC.
RSP2 6227 The contents of SP2 is loaded into the AC.
LSP1 6217 The contents of the AC is loaded into SP1. The AC is cleared.
LSP2 6237 The contents of the AC is loaded into SP2. The AC is cleared.
CAUTION: When switching between main and control panel memory, the stack po!ntsrs must be saved and restored.

Internal Control Instructions

Note that these instructions apply if the 6120 is executing
instructions from main memory or control panel.

Mne- Opcode Operation

monic
ION 6001 Turn on interrupt system. The interrupt Enable Flip Flop Is set. Neither INTREQ or any control panel request will be
granted until after execution of the next instruction. (6 minor cycles.)
10F 6002 Turn off interrupt. The interrupt enable flip flop is cleared immediately. If INTREQ is low while this instruction is being
processed, the interrupt will not be recognized. (6 minor cycles.)
RTF 6005 Load the following from the AC:
ACblt To
0 LINK
1 GT
4 IEFF
6-8 18
9·11 OF
The IIFF is set. The AC is cleared following the load operation. (8 minor cycles.)
SGT 6006 Skip if the GT flag is set. (7 minor cycles.)
CAF 6007 The AC, LINK and GT flag are cleared. Interrupt enable flip flop is cleared. i'C5CCRisgenerated with IX5A'R high,
causing peripheral devices to clear their flags. (7 minor cycles.)
WSR 6246 Write to switch register. The contents of the AC are written to an external device using a special 110transfer. The AC is
then cleared. The contents of the OF are available for device selection. OATAF is asserted. (7 minor cycles.)
GCF 6256 Get current fields. The following bits are loaded into the AC:
ACblt Function
0 LINK
1 GT!!M..-
2 1 if INTREQ Is low
o if INTREQ Is high
3 PWRONflag
4 IEFF
5 0
6·8 IF 0·2
9·11 OF 0·2
(9 minor cycles.)
 Main Memory Control Instructions
Note that these instructions apply only if the 6120
is executing instructions from main memory.

Mne- Opcode Operation

monic
SKON 6000 Skip if interrupt on, and turn off interrupt system. (7 minor cycles.)
SRQ 6003 Skip if the device interrupt line is low. Note that this skip does not depend on the state of the memory extension control's
interrupt inhibit flip flop. The SRQ merely tests the state of the INTREQ pin. (7 minor cycles.)
GTF 6004 Get flags. The following bits are loaded Into the AC:
ACblt Function
0 LINK
1 GT~
2 1 if INTREQ is low
o if INTREQ is high
3 PWRONflag
4 1
5 0
6-8 ISF 0-2
9-11 DSFO-2
(9 minor cycles.)
PRO 6206 These four opcodes have the same effect. The PNLTRP is set, causing the 6120 to enter panel mode instead of
PR1 6216 executing the next instruction, provided the interrupt inhibit flip flop is not set. If the interrupt inhibit flip flop is set,
PR2 6226 the panel mode will be entered following the JMP, JMS, RTN1 or RTN2 which clears the interrupt inhibit flip flop.
PR3 6236 These instructions are a NOP in panel mode. (6 minor cycies.)

The 6120's control panel is implemented in software. The system application.

software implementation olthe control panel need not use any
part of the main memory or change the processor state. This is Panel mode is entered because of the occurrence of any of
an important feature, since the final version of the system may four events. Each of these events sets a status flag, as well as
not have a control panel and the system designer would like to causing the entry into panel mode. It should be noted that
use the entire capacity of the main memory for the specific more than one event might happen simUltaneously.

Flag Set by Cleared by

PWRON RESET low and PRS and PEJ

STRTUP low
PNLTRP PRO (main memory) PRS and PE)
HLTFLG HLT instruction PGO
(or any OPR2 instruction
with bit 10 a 1)
BTSTRP High-to-Iow' PRSif
transition of CPREO BTSTRP
was set
when
status read

Panel mode entry is functionally similar to the granting of an A ConTRoL panel Flip Flop, CTRLFF, which is internal to the
interrupt with some important differences. Entry into panel 6120, is set when the CPREO is granted. The CTRLFF
mode for any reason is inhibited by the interrupt inhibitflip flop. prevents further CPREOs from being granted, bypasses the
Note that this means that a PRO or HLT instruction executed interrupt enable system and redefines several of the internal
when the interrupt inhibit flip flop is set will not be recognized control instructions.
until after the interrupt inhibit flip flop is cleared on the next
JMP, JMS, RTN1 or RTN2. Entry into panel mode is also As long as the CTRLFF is set, LXPAR is used for all instruc-
inhibited immediately following the ION instruction but will be tion, direct data and indirect pointer references. Also, while
recognized after the instruction following the ION is executed. CTRLFF is set, the INTGNT line is held high but the interrupt
grant flip flop is not cleared. lOTs executed while CTRLFF is
When a panel request is granted, the PC is stored in location set do not clear the interrupt grant flip flop.
0000 of the control panel memory and the 6120 resumes
operation at location 7777 (octal) of the panel memory. During Indirectly addressed data references by control panel AND,
PC write, o appears on CO, C1 and EMA2. The states of the IB, TAD, ISZ or DCA instructions reference panel memory or
IF, DF, ISF and DSF registers are not disturbed by entry into main memory as controlled by a Panel Data Flag (PDF)
the control panel mode but execution is forced to commence internal to the 6120. If set, this flag causes indirect references
in field zero. The panel memory would be organized with RAM from control panel memory to address control panel memory
in the lower pages and ROM or PROM in the higher pages of using LXPAR. If cleared, this flag causes indirect references
field zero. The control panel service routine would be stored in from control panel memory to address main memory using
the nonvolatile ROMs, starting at 7777 (octal). LXMAR.
The PDF is cleared unconditionally whenever the panel mode Control panel instruction fetch is specified by IF.
is entered for any reason. It is also cleared by an instruction Control panel indirect address fetch is specified by IF.
called CPD (Clear Panel Data). The PDF is set by an instruc-
Control panel current page or page zero data opera-
tion called SPD (Set Panel Data). The state of the Panel Data
tions are specified by IF.
flag is ignored when not operating in panel mode.
Control panel indirect data operations are specified by
Extended memory operations are implemented for panel DF. Main or control panel memory access is
mode instructions by a 1-bit flag in the EMA logic (the Force specified by the panel data flag.
Zero-FZ-flag). This flag is always set when panel mode is
Once the FZ flag is cleared in panel mode, it is not set until
entered and before the first panel mode memory operation
panel mode is entered again. The state of the FZ flag when not
(the store of the PC at control panel memory location 0000).
in panel mode is a "don't care".
As long as the FZ flag is set, zero appears on CO, C1 and
EMA2 in place of the IF except for special CO, C1, EMA2 Exiting from the control panel routine is normally achieved by
contents defined during write intervals, which remain undis- executing the following sequence:
turbed by FZ being set. The IF remains unchanged, however,
PEX
and may be read by the RIF instruction. The data field is
JMP I 0000 Ilocation 0000 in control panel memory
unaffected by the FZ flag and functions as defined above,
using the panel data flag to determine whether operands are The second instruction in this sequence may be any JMP,
in main or control panel memory. In particular if FZ=O: JMS, RTN1 or RTN2 instruction. The use of JMS is not
recommended, since the programmer has no means of
Control panel instruction fetch is to control panel field O. preserving the FZ and panel data flags.
Control panel indirect address fetch is to control panel The PEX instruction will cause the next JMP, JMS, RTN1 or
field O. RTN2 instruction to reset the CTRLFF. Location 0000 in the
Control panel current page or page zero direct data control panel memory contains either the original return
operations are to control panel field O. address deposited by the 6120 when the control panel routine
was entered or it may be a new starting address defined by the
Control panel indirect data operations are specified by
DF. Main or control panel memory access is control panel routine. The IF and DF registers may also
contain their original field designations or may have been
specified by the panel data flag.
altered by the control panel routine. If an exit is made from the
The FZ flag is cleared in panel mode simultaneously with the control panel routine with the HLTFLG set, one instruction is
(IF)_ (IB) transfer following the first panel mode instruction executed in main memory before control panel mode is
which may change the IF. These instructions are CIF (62X2), reentered due to the HLTFLG being set. Note that this allows a
CDF CIF (62X3), RTF (6005). and RMF (6244). The software-controlled single step operation of programs in main
(IF)_(IB) transfer (and hence the FZ clear) takes place memory. Caution: Single step operation will not occur for any
during the first JMP, JMS, RTN1, or RTN2 following the uninterruptable instructions or any instructions which set the
instruction. Once the FZ flag is cleared, the EMA logic IIFF. Exiting from a control panel routine can also be achieved
operates in control panel memory as it does in main memory by activating the RESET line, since reset has a higher priority
with the exception that the panel data flag controls whether than control panel request. If the RUN/HLT line is pulsed while
indirect data operations are to control panel or main memory. the 6120 is in the panel mode, the 6120 will halt at the
In particular: completion of the current instruction.

Panel Mode Control Instructions

Note that these instructions apply only if the 6120
is executing instructions from Control Panel Memory

Mn&- Opcode Description

monic

PRS 6000 Read panel status bits into ACD-4, a into remainder of AC.
The bits are read as follows:
ACblt Function
a BTSTRP
1 PNLTRP
2 1 if INTREQ is low
a if INTREQ is high
3 PWRON
4 HLTFLG
5-11 a
Following the reading of the flags into the AC, the flags are cleared, with the exception of HLTFLG. BTSTRPis
cleared only if a 1 was read into ACO. (8 minor cycles).
PGO 6003 Reset the HLTFLG flip flop. (6 minor cycles).
PEX 6004 Exit from panel mode into main memory at the end of the next JMP, JMS, RTN1 or RTN2 instruction. Clear PWRON
and PNLTRP. (6 minor cycles).
CPD 6266 Clear Panel Data Flag (PDF). Clears the panel data flag so that indirect data operands of panel mode instructions
are obtained from main memory. The panel data flag is also cleared upon entry into panel memory. (5 minor cycles).
SPD 6276 Set panel data flag. Sets the panel data flag so that indirect data operands of panel mode instructions are obtained
from panel memory. (5 minor cycles).
 Memory Extension Instructions
Most memory extension instructions require 6 minor cycles,
except for RIB which requires 9 minor cycles.
The internal memory extension control extends the basic 4K that there is no carry from the most-significant PC bit into the
addressing structure of the 6120 to 32K. It does so by IF. The IF is also used for directly-addressed operands, and for
appending three high-order bits to the memory address. indirect address pointers.
These bits, which appear on CO, Cl and EMA2lines, apply to The Data Field (OF) serves to extend the address of indirectly
addresses within main memory or control panel memory. The addressed operands, external lOTs, OSR and WSR functions.
changing of memory fields is accomplished via internal
control instructions. The Instruction Save Field and Data Save Field are used to
retain the contents of the IF and the OF which existed prior to
The Instruction Field (IF) serves as an extension to the PC, an interrupt.
prOViding three high-order bits during instruction fetches. Note

Mn. Opcode Opel'lltlon

monic

CoF 62Xl Change Data Field to X. X is loaded into OF.

CIF 62X2 Change Instruction Field to X. X Is loaded into lB. and the IIFF Is set. (The set state IIFF causes the priority network to
Ignore Interrupt requests). The contents of IB are loaded Into the IF at the end of the nexlJMP, JMS. RTNl or RTN2
Instruction. At the same time the Interrupt Inhibit flip flop Is cleared.
CoFCIF 62X3 A mlcroprogrammed combination of CoF and CIF. Both fields are set to X.
RoF 6214 Load the contents olthe Data Field register Into bits 6-8 olthe AC. DFo-2 goes to AC6-8 respectively. ACo-S and 9-11
are unchanged.
RIF 6224 Load the contents olthe Instruction Field register Into bits 6-8 of the AC. IFo-2 goes to AC6-8 respectively. ACo-S and
9-11 are unchanged.
RIB 6234 Load the contents of the ISF and oSF Into bits 6-11 of the AC. ISFo-2 goes to AC6-8 and oSFo-2 goes to AC9-11
respectively. ACo-S are unchanged.
RMF 6244 Load the contents of ISF Into IB, DSF Into OF,and selthe Interruptlnhlbltfllp flop. This Instruction Is used to restore the
contents of the memory field registers to their values before an Interrupt occurred.

Input/output transfer instructions, which have an opcode of 6, teletypes, cassettes, card readers and CRT displays. Interrupt
are used to initiate the operation of peripheral devices and to transfers use the Interrupt system to service several
transfer data between peripherals and the 6120. Three types peripheral devices simultaneously, on an intermittent basis,
of data transfer may be used to receive or transmit information permitting computational operations to be performed concur-
between the 6120 and one or more peripheral 110 devices. rently with I/O operations. Both programmed data transfers
Programmed data transfer provides a straight-forward means and program interrupt transfers use the accumulator as a
of communicating with relatively slow I/O devices, such as buffer, or storage area, for all data transfers.

lOT INSTRUCTION FORMAT

2 3 4 5 6 7 8 9 10 11
o 1-- ----OEyICE SE'ECT CO:OE ----~IOPE~ATION¢OOE

Bits 0·2 are always set to 6 (110) to specify an lOT Instruction. instruction are placed on DXO·ll; the data field Is placed on
The next six bits, 3-8, contain the device selection code that CO, Cl and EMA2; and DATAF Is asserted. LXDAR then falls.
determines the specific I/O device for which the lOT Instruc- signalling the beginning of the lOT execute phase. These bits
tion is intended. Device selection codes 00 and 2X specify must be latched in an external register, since they are then
internal operations, and may not be used by external devices. removed to free the OX bus for 110 data exchanges. Following
Up to 55 I/O devices can be specified. The last three bits, 9-11 , the fall of LXDAR, the 6120 generates a write signal. During
contain the operation specification code that determines the the WRITE, the 6120 reads the SKIP, CO and Cl lines. SKIP,
specific operation to be performed. The nature of this opera- CO, and Cl define the type of I/O operation. If Cl Is pUlled low
tion for any given lOT Instruction depends entirely upon the during the write signal, then the 6120 adds one minor cycle
circuitry designed into the I/O device Interface (see the 6121 and performs a read operation after the write.
specification).
The control line SKIP, when low during the write portion of an
Programmed data transfer begins when the 6120 fetches an lOT, causes the 6120 to skip the next instruction. This feature
instruction from the memory and recognizes that the current is used to sense the status of various signals in the device
instruction is an external lOT. The 6120 sequences the lOT interface. The CO and Cl lines are treated independently of
instruction through an execute phase. Bits 0-11 of the lOT the SKIP line.
 Control Lines Operation Description
CO C1

High High (Device)-(AC) The contents of the AC is sent to the device.

Low High (Device)~(AC), CLA The contents of the AC is sent to the device; then the AC is cleared.
High Low (AC)-(AC)V(Device) Data is received from a device, "OR"ed with the data in the AC, and the result is stored in the AC.
Low Low (AC)~(Device) Data is received from a device and loaded into the AC.

The program interrupt system may be used to initiate pro- and control panel) from occurring when there is a possibility
grammed data transfers in such a way that the time spent that the IF is not equal to the lB. More specifically, the interrupt
waiting for device status is greatly reduced. It also provides a inhibit flip flop is set whenever the IB is loaded (I.e., by the
means of performing programmed data transfers between the instructions CIF, CDF CIF, RMF or RTF), and cleared
6120 and peripheral devices while executing another pro- whenever the IF is loaded from the IB (i.e., at the proper phase
gram. This is accomplished by isolating the I/O handling of JMP, JMS, RTN1 or RTN2 instructions). Device interrupts
routines from the mainline program and using the interrupt are recognized only if the interrupt system ~ enabled, the
system to ensure that these routines are entered only when an interrupt inhibit flip flop is cleared and INTRE is low.
I/O device is set, indicating that the device is actually ready to
Upon recognition of an interrupt, the 6120 stores the PC in
perform the next data transfer.
location 0000 of field 0 and clears the interrupt enable flip flop.
The interrupt system allows external conditions to interrupt Zero appears on CO, C1 and EMA2 when the PC is stored. At
the computer program (which must be in main memory) by the same time, INTGNT goes low. During the interrupt grant
driving INTREQ low. If no internal higher priority requests are sequence, IF is loaded into ISF and OF is loaded into DSF. IF,
outstanding and the interrupt system is enabled, the 6120 IB and OF are then cleared. The next instruction is fetched
grants the device interrupt at the end of the current instruction. from location 0001 of main memory field O. INTGNT remains
After an interrupt has been granted, the interrupt enable flip low until the trailing edge of the first LXDAR generated by a
flop in the 6120 is reset so that no more interrupts are main memory lOT following the recognition of the interrupt.
acknowledged until the interrupt system is re-enabled under The granting of an interrupt requires 4 minor cycles. If a control
program control. panel interrupt is granted while INTGNT is low, INTGNTwili be
The interrupt inhibit flip flop prevents interrupts (both device forced high as long as CTRLFF is set but will return to the low
state when CTRLFF is cleared.

Direct memory access, sometimes called data break, is the very small pull-up drive. These lines can then be pulled down
preferred form of data transfer to use with high-speed storage by an external device. In this way, these control lines are stable
devices such as magnetic disk or tape units. The DMA until the external device can gain control of them. IFETCH and
mechanism transfers data directly between memory and LXDAR are both held high. RUN is held low. The states of
peripheral devices. The 6120 is involved only in setting up the DATAF and INTGNT are undisturbed.
transfer; the transfers take place with no 6120 intervention on
The external DMA device must not drive the bus until
a "cycle stealing" basis. The DMA transfer rate is limited only
DMAGNT is high. The DMA device must:
by the bandwidth of the memory and the data transfer
characteristics of the device. a. Drive all signals with three-state devices.
b. Provide all address, data, LXPAR, LXMAR, and other
The external device generates a DMA request when it is ready
control signals with the proper timing.
to transfer data. The 6120 grants the DMAREQ by pulling the
c. Return all control lines to the high state before
DMAGNT signal high at any point in any of the instructions, or
relinquishing the bus.
between instructions, when the 6120 is not using the OX bus in
d. Three-state all drivers at or before DMAREQ is pulled
performing a bus read, write or read-modify-write operation.
high by the device.
The 6120 suspends its internal timing until the DMAREQ line
is high. The OX lines, EMA2, CO and C1 lines are tristated. After the DMAREQ line is pulled high, the 6120 negates
LXPAR, LXMAR, MEMSEL, OUT, READ and WRITE are all DMAGNT and re-establishes proper timing before pro-
held high by a device on each of these lines which only has a ceeding.
 Set Clear Load
Name Conditions Conditions Conditions Comments

IEFF ION inst. 1. RESET=low RTF inst. INTERRUPT ENABLE FLIP FLOP: Tested by
2. 10F inst. the SKON instruction. GCF inst. loads state
3. During INTGNT of IEFF into AC4. INTREQ is honored only
sequence if IEFF is set (1).
4. SKON inst.
IIFF 1. CIF inst. 1. RESET=low none INTERRUPT INHIBIT FLIP FLOP: Suppresses
2. CIFCDF 2. JMP, JMS, RTN any INTREQ or Control Panel mode request.
3. RMF inst.
4. RTF
CTRLFF Upon entry 1. RESET=low none CONTROL PANEL FLIP FLOP: Indicates control
into panel 2. Next JMP, panel operation. Interrupts are not honored
mode JMS or RTN when set.
after PEX
inst.
FZ Upon entry First JMP, JMS none FORCE ZERO FLAG: Forces control panel
into panel or RTN inst. instruction field access to field zero.
mode executed with Indirect data accesses are not affected.
IIFF set.
PDF SPD inst. 1. Panel mode none PANEL DATAFLAG: When set causes indirect data
entry operations executed in control panel to
2. CPD inst. access CP memory. Otherwise they are to
main memory. PDF is ignored when executing
in main memory.
RUNHLT RESET=low none On the low RUN HALT FLIP FLOP: When cleared the 6120
to high will halt after the first instruction in which
transition thi~detected. The 6120 will respond
of the to DMAREQ in this state.
RUN/HLTlIne
HLTFLG HLT inst. 1. RESET=low none HALT FLAG: When set, panel mode will be entered
2. PGO inst. unless the IIFF is set or RESET is low. IIFF can
be cleared on the next JMP, JMS or RTN
instruction at which point panel mode will
be entered.
PNLTRP PRO, PR1, 1. RESET=low none PANEL TRAP FLAG: Same result as
PR2, PR3 inst. 2. PRS inst. defined for HLTFLG.
(main only) 3. PEX inst.
BTSTRP High to low 1. RESET=low none BOOTSTRAP FLAG: Same result as
transition 2. PRS inst. defined for HLTFLG.
ofCPREQ
PWRON REmand 1. RESET and none POWER-ON FLAG: Causes entry into
STRTUP=low STRTUP=high panel mode when RESET is released and
2. PRS inst. this flag is set.
3. PEX inst.
GT none RESET=low RTF inst. GREATER THAN FLAG: General purpose flag
which has no arithmetic significance.
m HARRIS
HD-6121

• LOW POWER. TYP. < 2 mW

• SINGLE SUPPLY - 5V
• INDUSTRIAL AND MIUTARY TEMPERATURE RANGES
• 8120 COMPATIBLE INTERFACE
•

•
CONTROLS ANY COMBINATION OF FIVE INPUT OR OUTPUT PORTS WITH
HANDSHAKING
EUMINATES GATED READ ANDWflITE SIGNALS THROUGH THE CONTROLLER
INTGNT
PAl
1
2
- 40
39
VCC

• CONFORMS TO DEC' CONVENTIONS REGARDING DEVICE ADDRESSING AND STROBEl 3 38 ~

COMMANDS SENSEl 4 37 WRITE
• INDEPENDENT PROGRAMMING OF EACH DEVICE'S ADDRESS AND DATA DIRECTION ENABLE1 5 36 DXD
• COMPLETE INTERRUPT AND SKIP LOGIC FOR EACH DEVICE INCLUDING PRIORITY STROBE2 6 35 DXl
INTERRUPT VECTORING SENSE2 7 34 DX2
• STROBE OUTPUTS ARE PROGRAMMABLE HIGH OR LOW TRUE ENABLE2 6 33 DX3
STROBE3 9 32 DX4
• SENSE INPUTS ARE PROGRAMMABLE FOR LEVEL OR EDGE SENSITIVITY SENSE3 10 HD·6121 31 DX5
• ENABLE OUTPUTS FUNCTION AS USER PROGRAMMABLE CHIP SELECTS ffiBm 11 30 DX8
STROBE. 12 29 DX7
Description SENSE4 13 26 DX8
ENABLE4 14 27 DX9
The HD-6121 Input/Output Controller (IOC) is a high performance, CMOS support 26 DX1D
STROBE5 15
circuit for the 6120 microprocessor. Fully programmable, this device offers SENSE5 16 25 DXll
independent control of any combination of five. 12 bit input or output ports. ENAIl.I.E.5 17
Used in con/'unction with the 6120 microprocessor, the 6121 provides user
PRO
SKIP
18
19
24
23
22
Ma
Ci
programmab e chip select decoding, priority vectored interrupt control, software VSS 20 21 Co
readable status and I/O port handshaking signals.
The Priority In (PRI) and Priority Out (PRO) control signals permit up to eleven 6121s
to be used without any additional hardware. Industrial control and other I/O intensive
systems can profit greatly from the highly hardware/software efficient capability
provided by the 6120/6121chip set.

INTREQ
CO OUTPUT
C1 BUFFER
SKIP PROGRAMMING
AND
INTERRUPT
READ CONTROL
WRITE ENABLE
10C I/O PORT
INTGNT STROBE
fOC[R CONTROL CONTROL
LOGIC
LXDAR SENSE

OX BUS
BUFFER
Supply Voltage +8.0 VOLTS Operating Temperature Range
Operating Voltage Range +4Vto+7V Industrial (-9, -9+) -40°C to +85°C
Input/Output Voltage Applied VSS-0.3V to VCC+0.3V Military (-2, -8) -55°C to +125°C
Storage Temperature Range -65°C to +150°C Maximum Power Dissipation 1 Walt

SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS

VIH LOGICAL ONE 70% VCC V
INPUT VOLTAGE
VIL LOGICAL ZERO 30% VCC V
INPUT VOLTAGE
VOH LOGICAL ONE VCC-0.5 V 10H = -1.6mA
OUTPUT VOLTAGE Except for SKIP,
INTREQ, Co and C1
which are open drain.
VOL LOGICAL ZERO 0.5 V 10L = 1.6mA
OUTPUT VOLTAGE Except for SKiP,
INTREQ, CO and Ci.
VOL LOGICAL ZERO 0.5 V IOL = 15 mA
OUTPUT VOLTAGE SKIP, INTREQ, Co, Ci
OUTPUTS
ilL INPUT LEAKAGE -10 10 I-'A OV",VIN"'VCC
CURRENT
10 I/O, OUTPUT -10 10 I-'A OV",VO",VCC
LEAKAGE CURRENT NOTE 1
ICC POWER SUPPLY 100 I-'A VIN=VCC or GND
CURRENT VCC = 5.25 V
OUTPUTS OPEN
CIN' INPUT 5 p-F FREQ = 1 MHZ
CAPACITANCE TA=25'C
VIN=VCC or GND
COUT' OUTPUT 15 pF FREQ = 1 MHZ
CAPACITANCE TA=25'C
VIN=VCC or GND

A.C. ELECTRICAL CHARACTERISTICS; VCC=5.0V±5%; T.=lndustrial or Military;

CL=50 pf,
SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS
TAS ADDRESS SET UP 30 ns
TIME
TAH ADDRESS HOLD TIME 70 ns
TRWE WRITE ENABLE DELAY 100 ns
TRWD WRITE DISABLE DELAY 100 ns
TWS WRITE SET UP TIME 50 ns
TWH WRITE HOLD TIME 50 ns
TPDE ENABLE OUTPUT DELAY 125 ns
TPDD ENABLE OUTPUT 200 ns
DISABLE DELAY
TRE READ VECTOR ENABLE 100 ns
TRD READ VECTOR DISABLE 100 ns
TWPD WRITE PULSE DEU>.Y 100 ns
TLXH RESET DELAY, 10CLR 100 ns
TO LXDAR
DECOUPLING CAPACITORS where tR=20 ns, VCC=5.0 volts, CL=50 pf on each of twelve
outputs.
The transient current required to charge and discharge the 50
pf load capacitance specified in the 6121 data sheet is i;;; (12 x 50 x 10-12) x (5.0v x 0.8)/(20 x 10-9)
determined by ;;; 120 mA

i = CL (dv/dt) This current spike may cause a large negative voltage spike on
VCC, which could cause improper operation of the device. To
Assuming that all DX outputs change state at the same time filter out this noise, it is recommended that a 0.1 /LF ceramic
and that dv/dt is constant; disk decoupling capacitor be placed between VCC and GND
i =0 CL (VCC x 80%) at each device, with placement being as near to the device as
tA/tF possible.

___________ --'r-
DATA VECTO
I
TWS1TWHr- ~
~
I I

A 4 TRWD

)
.

~
I \
6120 PULLS HIGH
I I I I
~ \
~TPDE1
~~."'
I CI· H DURING
I CI. L
WR!TE
1

-------------- 1
CAF INSTRUCTION ~
POWER ON RESET 1
 ACTlVE
I/O PIN SYMBOL LEVEL DESCRIPTION

I 1 INTGNT Low Interrupt grant signal from the 6120.

I 2 PRI Low Input for priority string. Low implies no higher priority up the string. Device #1 internally is the
highest priority device.
0 3,6,9, STROBE High Output strobes set true by a transfer command. Cleared by a Set Flag command or by the
12,15 1-5 or corresponding sense input going true. Programmable polarity.
Low
I 4,7,10, SENSE High Status inputs from an external device. Can cause lOT skips or interrupts. Programmable edge
13,16 1-5 or or level sense and polarity.
Low
0 5,8,11, ENABLE Low Bus transfer enable pulses for external devices. True during LXDAR.
14,17 1-5
0 18 PRO Low Output for priority string. Low implies enable for next device down the string. Device #5
internally is the lowest priority device and drives this output.
0 19 SKIP Low True during LXDAR and WRITE to indicate to the 6120 that a skip is to occur on the current
lOT. N-Channel open drain.
20 VSS Power supply ground.
0 21,22 Co,C1 Low Control signals to the 6120 which specify the type of transfer required for an I/O instruction.
See Table 1. N-Channel open drain.
0 23 i'N'TREQ Low Interrupt request to the 6120. N-Channel open drain output.
I 24 READ Low 6120 bus read pulse.
I/O 25-36 DX11-0 High 6120 data/address bus. (DXO= MSB, DX11= LSB)
I 37 WRi'fE Low 6120 bus write pulse.
I 38 LX5AR Low 6120 I/O transfer enable signal. True during the execute phase of external lOT instruction.
Also true during power on reset.
I 39 10CLR Low Reset from the 6120 generated by power on reset or CAF instruction.
40 VCC Positive supply voltage.

CONCEPT: eliminates a separate interrupt controller IC. Up to eleven 6121

10Cs can be daisy chained without the need for any interfac-
The concept of the 10C is to prOVide basic control and enable ing logic. This results in vectored interrupt control of up to 55
signals for the devices which it controls but not be involved in I/O ports. The Priority In (PRI) and Priority Out (PRO) control
the critical speed timing of the OX bus transfers to and from
signals are used for this I/O expansion capability.
these devices. Each input or output port still has its own output
latch or input driver interface which results in maximum Another major on-chip feature of the 612110C is the inclusion
fleXibility with regard to I/O device characteristics. Because of I/O port handshaking signals. These signals provide the
these latches and input drivers are not included in the 6121, capability of polling the status of an Input port (SENSE inputs)
this 40 pin device is able to prOVide complete handshaking for and that of signaling an Output port that it has received data
five I/O ports. (STROBE outputs). These signals can be thought of as "Input
Buffer FUll" and "Output Buffer FUll" status lines. The charac-
Software programmable chip select decoding (ENABLE
teristics of these signals are software programmable which
outputs) provides a means whereby I/O device addressing is
greatly increases their flexibility.
readily changed with no change to the users PC board. This
on-chip feature replaces the 2-5 IC's normally associated with 6120 lOT INSTRUCTION SEQUENCING:
chip select decoding.
The 6121 is designed to interface with the 6120 external lOT
Another feature of the 6121 10C is an on-chip priority interrupt sequence. This sequence begins when the 6120 fetches an
controller. The interrupt logic includes software programma- instruction from the memory and recognizes that the current
ble vectors and complete interrupt request/grant handshaking instruction is an external lOT. An external lOT is any lOT (Bits
for the 6120 microprocessor. This on-chip feature of the 6121 0-2=6) whose device code (Bits 3-8) is not 00 or 2X.

5 6 7 8 9 10 11

~EVICE
A~DRESS:------.I ~OMMAN~
The 6120 sequences the lOT instruction through an execute The control line SKIP, when low during an lOT, causes the 6120
phase. Bits 0-11 of the lOT instruction are available on DXO-11 to skip the next instruction. This feature is used to sense the
as LXDAR falls near the start of the execute phase. The 6121 status of various signals in the device interface. The CO and C1
lac accepts the lOT command on the falling edge of LXDAR lines are treated independently of the SKIP line. The input
and latches this information into an internal command latch. ~nd signals, CO, C1 and SKIP, are sampled during
WRITE or REAl5"is active low to enable data transfers between LXDAR low· WRITE low. The data from the 6120 is available to
the 6120 and the peripheral device(s). The 6121 communicates the device(s) during LXDAR low· WRITE low. If C1 is low at
with the 6120 through 3 control lines ... CO, C1 and SKIP. The LXDAR low· WRITE low, a read is also performed and data is
type of data transfer during an lOT instruction is specified by the read from the peripheral into the 6120 during LXDAR low·
peripheral device by asserting the control lines as shown in READ low.
Table 1.

CONTROL LINES
CO Ci OPERATION DESCRIPTION
High High (Device)+-(ACl The contents of the AC is sent to the device.
Low High (Devicel_(ACl, The contents of the AC is sent to the device, then the AC is cleared.
Clear (AC)
High Low (ACl_(AClV(Device) Data is received from a device,"OR'ed" with the data in the AC and the result
stored in the AC.
Low Low (ACl+-(Devicel Data is received from a device and loaded into the AC.

INTERNAL DEVICE CONTROLLER the falling edge of INTGNT. The falling edge of INTGNT sets
FLIP FLOP DEFINITIONS: the interrupt sample flip flop if the flag flip flop and interrupt
enable flip flop are set and the priority input is true. If the flag
There are five device controllers within the 6121 lac. Each
~is clear or the priority input is false at the fall of
controller has a set of control and status flip flops which are
fi'iIiG1'IT, the state of the interrupt sample flip flop is not
defined below:
changed. The interrupt sample flip flop is cleared by the SKIP
FLAG FLIP FLOP - Internal device control status flip flop ON FLAG lOT, by the reset state of the interrupt enable flip flop
which only has meaning ilthe IS programming bit is a 1. It is set or by 10CLR. If this flip flop is set, the device's priority output is
by a SET FLAG lOT or by true going edge of sense input. It is false (high).
cleared by the SKIP ON FLAG instruction only if it was
sampled by that instruction as being set; by the interrupt PROGRAMMING:
vector operation; or by 10CLR. If the flag is set, interrupts can
be generated if otherwise enabled. If the IS programming bit is Immediately after power on reset, the five device controllers
0, the flag flip flop is held in the cleared state. within the lac are set to a state such that the first lOT
command received with PRI low will be interpreted as a
FLAG SAMPLE FLIP FLOP -Internal device control flip flop programming command to set up various lac parameters.
which samples the state of the flag flip flop at the falling edge This is true only for power on reset and is not true for the reset
of LXDAR. The set state of this flip flop causes the skip line to generated by the 6120 CAF instruction. Power on reset from
be pUlled and the flag flip flop to be cleared during WRITE the 6120 is distinguished by LXDAR being low atthe end olthe
pulses of a skip lOT. 10CLR pulse. During the reset caused by the CAF instruction,
STROBE FLIP FLOP-Internal device control flip flop which LXDAR is high throughout the 10CLR pulse. Each of the five
controls strobe output line. It is set by a transfer lOT at the device controllers within the lac are programmed indepen-
trailing edge of the LXDAR pulse. It is cleared by 10CLR, the dently by separate lOT commands. If PRI is low, the first lOT
true going edge of the sense input (if the IS programming bit programs the highest priority device (Device #1). The second
set) or the SET FLAG lOT command. The STROBE output lOT programs the second highest priority device (Device #2).
reflects the state of this ~ any time the strobe flip flop is This continues unt~ the devices in the lac are program-
cleared or at the end of LXDAR if the strobe flip flop is set. med, at which time PRO is made low so that programming can
commence on the next lac (if any) down the priority chain.
INTERRUPT ENABLE FLIP FLOP -Internal device control
The lac will not accept any operational lOT commands to any
flip flop which allows program enable of interrupts. This bit is
of the five devices until all five devices have been program-
set by 10CLR. This bit is loaded by DX11 during WRITE of
med. The programming lOT writes data from the 6120
LOAD INTERRUPT ENABLE lOT, If this flip flop and the flag
accumulator. The lower 9 bits of the lOT instruction itself
flip flop are both set, then the INTREQ pin is pulled low.
perform no programming function. The lOT instruction must
INTERRUPT SAMPLE FLIP FLOP -Internal device control be an external lOT, not device #00 or 2X. The programming
flip flop which samples the state of the interrupt condition at format from the accumulator is shown below:
 PROGRAMMING COMMAND FORMAT
456 7

_O_P IP ls_l- ?EVICE ~DDRES~

OP Output polarity additional constraint is that each device must have its own
1= High true strobe output unique address.
O=Low true strobe output Note that unused devices must be turned off during program-
IP Input polarity ming simply by programming them with an internal lOT
1=High true sense polarity address (00 or 2X). and with the IS programming bit set to "0"
0= Low true sense polarity to prevent interrupts. Also. sense inputs must be tied to
IS Input edge sensitivity ground. Internal 6120 lOT's do not generate LXDAR. The lOT
1=Set flag flip flop and interrupt (if interrupts ena- controller is therefore made insensitive to all external lOT
bled) on true-going edge of sense input. Skip on commands when programmed with an internal lOT address.
flag flip flop set. Whenever a device controller within the 10C responds to its
0= Skip on sense line input level true. (No interrupt on programming lOT,it pulls the COline low so that the 6120 will
sense true.) perform an output operation from the AC followed by clearing
theAC.
DEVICE ADDRESS The 6 bit device address assigned to the
device controller. IOC COMMANDS:
EN Enable output control select. Power on reaet- This is indicated by the 10CLR input low and
1= Enable output is true (low) whenever the device is I3Cl5PJflowat the end of the 10CLR pulse. This operation sets
addressed. (Except for programming and vector up the 10C to be programmed as discussed above. Also. all
operations.) five flag flip flops are cleared as are the flag sample and
O=Enable is true only when a transfer command (48 interrupt sample flip flops. The interrupt enable flip flops are all
or 6e) is given.
set. The strobe flip f~~LEre cleared. the STROBE outputs are
C C line control. set low and the EN outputs are set high. Note that if a
O=Transfer commands do not cause C lines to be controller is programmed for a low true STROBE output, then
controlled. there will be a low to high transition on the strobe output when
1= Transfer commands cause C lines to be control- this device is programmed. Also, care must be taken to assure
led. that the state of the flag, flag sample, interrupt sample,
I/O Input or output port select. This programming bit has no interrupt inhibit and strobe flip flops are not disturbed by the
meaning if the "C" programming bit is set to a "0". programming function.
1= Tmnsfer commands cause outputs to the device. The 6120 Clear All Flags (CAF) Instruction - This instruc-
(C1 is not pulled low.)
0= Tmnsfer commands cause inputs from the device.
tion is Indicated to the
staying high during the I
Igg by ~ going low and LXDAR
LR pulse. This operation performs
(C1 is pulled low.)
exactly the same operation as power on reset on the device
After all five devices of the 10C are programmed. they are flag. flag sample, interrupt sample. Interrupt enable and
ready to respond to lOT commands with their programmed strobe flip flops. It does not set up the 10C for programming,
addresses. Because of this. no operational lOT commands nor does it disturb the state of any of the programming
can be used until all system 10C's have been programmed. An information stored within the 10C.

EXTERNAL lOT COMMAND FORMAT

0 2 3 4 5 6 7 8 9 10 11

CJ 0
I_ ~EVICE :ADDRESS: ~I ~OMMAN~

Bit 9 10 11
SET FLAG. CLEAR STROBE 0 0 0
SKIP ON FLAG. CLEAR FLAG 0 0 1
CLEAR ACCUMULATOR 0 1 0
(If programmed for input)
NOP 0 1 1
DATATRANSFER 1 0 0
(CO not pulled low)
LOAD INTERRUPT ENABLE 0
(From DX11)
DATATRANSFER 0
(COpUlled low)
NOP

4-27
 __ .,~ ••• .,:::f ••• , •.••.••••••.•• ~ •..•, '''' 'wIn .." a Ivau .1"\11 U'='Vlv'=' vUJllfUJltJJ::;;
IQI
Ul ••••II I~ ••••' IIlltJ IIUtJ lV U'=' ~t::ll dJIU C11::;;U
I'Q~ clears tne::> I HUtjt:
which have their interrupt sample flip flops set will hold their
output to the programmed false state. If the device is prog-
respective priority outputs high. All device controllers with a
rammed for level sensitive SENSE input, then the flag flip flop
high priority input hold their priority outputs high and also
is not set by this instruction, but the STROBE output is cleared.
are inhibited from driving the INTREQ bus low.
SKIP ON FLAG, CLEAR FLAG - The skip on flag operation
2. When the first lOT is executed with INTGNT low, one of two
depends on whether the device is programmed for edge or
events occurs, depending on the lOT command:
level sensitivity. If programmed for level sensitivity and the
SENSE input is logic true, then the SKIP line is pulled low a. If the command issued is a SKIP ON FLAG (1.) command,
during the lOT WRITE pulse; the clear flag operation has no then the normal operation of the lOT command occurs in
meaning. If programmed for edge sensitivity, then the state of the addressed device. A SKIP ON FLAG (18) instruction will
the flag fI1p flop is sampled to the flag sample flip flop at the clear the interrupt sample flip flop of the addressed device
falling edge of LXDAR. During the lOT WRi'l'E pulse, the SKIP and will clear the flag flip flop if it is set.
line will be pulled low if the flag sample flip flop is true. If the b. If the command is nota SKIP ON FLAG (18) command, then
flag sample flip flop is set, then the flag flip flop will be cleared the fact that INTGNT is low causes special action. During
some time before or at the trailing edge of LXDAR. the WRITE pulse CO and C1 are both pulled low by the
highest priority device with its interrupt sample flip flop set.
CLEAR ACCUMULATOR - This command only functions if No other device (not even the addressed device) will
the C line control programming bit (bit 10= 1) has been respond on this lOT. This lOT specifies a JAM read cycle.
programmed for the device to control the C lines and the The 6120 then generates a READ pulse which causes the
device has been programmed as an input device (bit 11 =0). device address of the highest priority device with its
When enabled by the above two programming conditions, this interrupt sample flip flop set to put its device address on
command will cause CO to be pulled low during the lOT DX6-11 and all zeros on DXO-5. Also, the f1a9..!!!.P.!!2l?of that
WRITE pulse. This will cause the 6120 accumulator to be device is cleared, causing it to remove the Tf'ITREQ drive.
cleared. The interrupt sample flip flop is not cleared at this time so
that the priority output of that device continues to be held
DATA TRANSFER (48 or 6.) - Either transfer command will
false (high).
unconditionally set the STROBE output to its true state. If the
"c" programming bit is set, the transfer commands will also c. Near the end of the interrupt service routine of that
cause the "c" lines to be controlled to specify the type of I/O particular device, the software should (with the 6120
transfer to be performed. If not, then the lac device does not interrupts disabled) execute a SKIP ON FLAG lOT to the
control the "c" lines. If the device "I/O" programming bit is 1, device. This will clear the interrupt sample flip flop of the
then C 1 is not pulled low and an output transfer is specified by device, which in turn will set the priority output of that device
either 4. or 6•. If the I/O programming bit is 0, then an input true, enabling interrupts from devices lower in the chain.
transfer is specified by pullinJ!.. Ci low during the WRITE pulse.
Command 4. does not pull CO low. For an output, this corres-
ponds to not clearing the AC after the output. For an input, this
corresponds to "OR'ing" the input data with the AC. Command SOFTWARE NOTES:
6. always pulls CO low. For an output, this causes the AC to be
1. When performing the interrupt vector operation from the
cleared following the output. For an input, this corresponds to
6120, the accumulator must be loaded with a "no interrupt"
the input data being loaded into the AC. The STROBE output
vector address (such as zero) before the vector lOT is
is cleared when the flag flip flop is set by the SENSE transition
issued. This vector is left in the accumulator if no internal
or by a SET FLAG command.
vector is returned by a device controller.
LOAD INTERRUPT ENABLE- This command causes a write
2. Before a device's interrupts are turned off by resetting its
of 6120 AC bit 11 to the addressed device's interrupt enable
interrupt enable flip flop with a 6XX5 command the 6120's
flip flop. This write holds neither CO nor Ci low so that a write
interrupts must be turned off. Failure to do so can result in
without a clear of the AC is performed. The device is incapable
an unidentifiable interrupt from the device.
of generating interrupts if the interrupt enable flip flop is
cleared. 3. When turning on a device's interrupt with a 6XX5 command,
an immediate interrupt will result if the device's flag is set
and the 6120 interrupts are turned on.
INTERRUPT LOGIC: 4. Because the lac programming sequence relies on an
A device controller within the lac is capable of generating an exact sequence of lOT instructions to be executed and
10CLR enables interrupts, the programming instructions
interrupt by pulling the INTREQ line low if all of the following
conditions are true: must be executed with the 6120's interrupts off.
5. Use of the level sensitive "Skip on Flag, Clear Flag"
1. The device is programmed for edge sensitive SENSE
operation 16xx1), requires that a redundant skip instruc-
input, and
tion followed by a Nap be used to guarantee that the
2. The device flag flip flop has been set, and
"Flag Sample Flip Flop" is reset.
3. The device interrupt enable flip flop is set, and
4. The priority string input for that device is true.
Normally, with no system interrupts outstanding, all device
prio~nputs and outputs are low. At the highest priority laC, TESTING NOTE:
the PRI input must be tied to Vss.
The PRO line cannot go true after any 10CLR true pulse
Whenever the interrupt conditions are met at any device on (either in programming or in a CAF) untilthere is at least one
the laC, the INTREQ line is pulled low and the following READ pulse. In addition, no external lOT commands can be
sequence of events occurs: executed during an 10CLR true pulse.
 SUMMARY OF 6120, 6121 CONDITIONS:
The following table provides a brief summary of all the 6120 and 6121 Operations.
lOT COMMANDS PROGRAMMING BITS
BIT BIT BIT OUTPUTS 6120 6121
9 10 11 C 110 co C1 OPERATION OPERATION
0 1 0 1 1 HiZ HiZ Output (AC) NOP
1 0 0 1 1 HiZ HiZ Output (AC) Generate ENABLE. (Output to device.) Set STROBE
output.
1 1 0 1 1 Low HiZ Output (AC) Generate ENABLE. (Output to device.) Set STROBE
then (AC)_ 0 output.
0 1 0 1 0 Low HiZ Output (AC) NOP except for low CO output. Result is only to clear
then (AC)_O 6120 AC.
1 0 0 1 0 HiZ Low (AC)_lnput Generate ENABLE. (Input from device.) Set STROBE
V(AC) output.
1 1 0 1 0 Low Low (AC)_lnput Generate ENABLE. (Input from device.) Set STROBE
output.
1 0 1 X X HiZ HiZ Output (AC) Load interrupt enable flip flop from OXll.
0 0 0 X X HiZ HiZ Output (AC) Set flag flip flop if its prog. bit is set. Clear STROBE
output.
0 0 1 X X HiZ HiZ Output (AC) Pull SKIP low and clear Flag FF if flag sample flip
flop is a 1 during the write pulse.
X 1 1 X X HiZ HiZ Output (AC) No operation.
Vector Read X X Low Low (AC)_lnput Place interrupt vector on OX bus, clear Flag FF
Programming lOT X X Low HiZ Output (AC) Load programming information to device program-
then (AC)_O ming register from the OX bus during write.

'Opl co/co

",,{ OSCIN
cI'Ci
SKP
iNimi
0' 10MO iNTGNT
Mh, iOCUi
OSCOUT
'Opl

1001C0

--.L
GND 0
. REm

I' 1"

ox.
OX7

ox.
ox.
v~ OX10
OXtl
MAIN!
STARTUP

PANEL
m HARRIS HM-6100
CMOS 12 BIT
MICROPROCESSOR
(CPU)

Features
• LOW POWER -TYP.<5.0j.lW
• SINGLE +5V POWER SUPPLY
• FULL TEMPERATURE RANGE -550C TO +125OC
• STATIC OPERATION VCC DATAF
• SINGLE PHASE CLOCK, ON CHIP CRYSTAL ose. RUN INTGNT
• SOFTWARE COMPATIBLE WITH PDP-8/E DMAGNT ~
• 12-BIT DATA WORD DMAREQ MEMSEL
• OVER 90 SINGLE WORD INSTRUCTIONS CPREO IFETCH
• RELOCATABLE MEMORY ORGANIZATION RUN/RTf SKP
• BASIC ADDRESSING TO 4K 12 BIT WORDS RESET C2
• PROVISION FOR DEDICATED CONTROL PANEL INTREO C'i
• 128 GENERAL PURPOSE REGISTERS XTA CO
• 8 AUTOINDEXING REGISTERS LXMAR SWSEL
• FLEXIBLE PROGRAMMED 1/0 TRANSFERS WAIT ~
• VECTORED INTERRUPT CAPABILITY XT8 LINK
XTC DX11
Description OSCOUT DX10
The HM-6100 is a single address, fixed word length, parallel transfer OSCIN GND
microprocessor using 12-bit two's complement arithmetic. It is a gen- DXO DX9
eral purpose processor which recognizes the instruction set of Digital DX1 DX8
Equipment Corporation's PDP-8/E Minicomputer. DX2 DX7
DX3 DX6
Standard features include indirect addressing and facilities for instruction DX4 DX5
skipping, program interrupts as a function of input/output device condi-
tions, and auto-restart. Five 12-bit registers are used to control ~icropro-
cessor operations, address memory, perform arithmetic or logical opera-
tions, and store data. The device design is optimized to minimize the
number of external components required for interfacing with standard
memory and peripheral devices.

SYSTEM
SELECT
LINES
 Supply Voltage (VCC - GND) -o.3V to +8.0V
Input or Output Voltage Applied (GND - 0.3V) to (VCC +0.3V)
Storage Temperature Range -650C to 1500C
Operating Temperature Range
Industrial HM-6100-9 -400C to +850C
Military HM-6100-2 -550C to +1250C

SYMBOL PARAMETER MIN TYP MAX UNITS TEST CONDITIONS

VIH Logical "'1"' Input Voltage 70%VCC V

VIHC Logical "'1"' Osc. Input Voltage VCC-.5 V
VIL Logical "'0" Input Voltage 20% VCC V
VILC Logical"O"' Osc.lnputVoltage GND +.5 V
IlL Input Leakage (1) -1.0 +1.0 jJ.A OV~VIN~VCC
VOH Logical "'1"' Output Volt. (2) 2.4 V 10H = -O.2mA
VOL Logical "0"' Output Volt. (2) 0.45 V 10L = 2.0mA
10 Output Leakage -1.0 +1.0 jJ.A OV~VO~VCC
ICCl Supply Current (Static) 400 IJ.A VIN = VCC, Freq. = 0
ICC2 Supply Current (Operati ng) 2.5 mA VCC=5.5V, Freq=2.0MHz
CI I nput Capacitance (3) 5 7 pF
CO Output Capacitance (3) 8 10 pF
CIO Input/Output Capacitance (3) 8 10 pF
COSC Oscillator IN/OUT CAP. (3) 30 pF

Notes: (1) Except pin 14 and 15

(2) Except pin 14
(3) Guaranteed and sampled, but not 100% tested.

TA = 250C TA = Indust. TA = Military

VCC= 5.0V VCC= VCC=
(1) 5.0 ±'10%V 5.0 ±'10%V

SYMBOL PARAMETER MIN MAX MIN MAX MIN MAX UNITS TEST CONDITIONS

fMAX Max Operating Frequency 4.0 3.33 2.5 MHz CL = 50pF

TS Major State Time 500 600 800 ns See Timing Diagram
TLX LXMAA Pulse Width 220 230 355 ns
TAS Address Setup Time 80 85 200 ns
TAH Address Hold Time 150 125 175 ns
TAL Access Time from LXMAR 450 520 745 ns
TEN Output Enable (Memory) 250 300 470 ns
TEND Output Enable (I/O) 300 470 655 ns
TWP Write Pulse Width 200 235 330 ns
TDS Data Setup (Memory) 160 135 250 ns
TDSD Data Setup 0/0) 185 225 350 ns
TDH Data Hold Time 125 125 170 ns
TST Status Signals Valid 250 300 325 ns
TAS Request Inputs Setup 0 0 0 ns
TAH Request Inputs Hold 200 250 300 ns
TWS Wait Setup Time 0 50 50 ns
TWH Wait Hold Time 100 100 150 ns
TAHS Aun Halt Setup Time 0 50 50 ns
TAHP Aun Halt Pulse Width 100 100 150 ns

All devices guaranteed at worst case limits. Room temperature, 5V data provided for
information - not guaranteed.
 Supply Voltage 8.0V
Input or Output Voltage Applied Gnd -O.3V to VCC +O.3V
Storage Temperature Range -650C to 1500C
Operating Temperature Range
Industrial HM-6100C-9

SYMBOL PARAMETER MIN TYP MAX UNITS TEST CONDITIONS

VIH Logical "1" Input Voltage 70% VCC V

VIHC Logical "1" Osc.lnputVoltage VCC-.5 V
VIL Logical "0" Input Voltage .8 V
VILC Logical "0" Osc.lnputVoltage GND +.5 V
IlL Input Leakage (1) -10 +10 !J.A OV~VIN~VCC
VOH Logical "1" Output Volt. (2) 2.4 V 10H = -D.2mA
VOL Logical "0" Output Volt. (2) 0.45 V IOL=1.6mA
10 Output Leakage -10 +10 !J.A OV~VO~VCC
ICC1 Supply Current (Static) 600 !J.A VIN = VCC, Freq. = 0
ICC2 Supply Current (Operating) 5.0 mA VCC=5.5V, Freq=2.0MHz
CI Input Capacitance (3) 5 7 pF
CO Output Capacitance (3) 8 10 pF
CIO InputlOutput Capacitance (3) 8 10 pF
COSC Oscillator I NIOUT CAP. (3) 30 pF

Notes: (1) Except pin 14 and 15

(2) Except pin 14
(3) Guaranteed and sampled, but not 100% tested.

TA = 250C TA = Indust.
VCC=5,OV(1) VCC = 5,0 :!:5%

SYMBOL PARAMETER MIN MAX MIN MAX UNIT TEST CONDITION

fMAX Max operating Freq. 3.33 2.5 MHz CL = 50pF

TS Major State Time 600 800 ns See Timing Diagram
TLX LXMAR Pulse Width 270 335 ns
TAS Address Setup Time 100 120 ns
TAH Address Hold Time 150 175 ns
TAL Access Time from LXMAR 500 650 ns
TEN Output Enable (Memory) 300 400 ns
TEND Output Enable lI/O) 350 575 ns
TWP Write Pu Isa Width 250 320 ns
TDS Data Setup (Memory) 180 240 ns
TDSD Data Setup (1/0) 200 275 ns
TDH Data Hold Time 130 175 ns
TST Status Signals Valid 300 350 ns
TRS Request Inputs Setup 0 0 ns
TRH Request Inputs Hold 100 130 ns
TWS Wait Setup Time 0 0 ns
TWH Wait Hold Time 100 130 ns
TRHS Run Halt Setup Time 0 70 ns
TRHP Run Halt Pulse Width 100 130 ns

Note 1: All devices guaranteed at worst case limits. Room temperature, 5V data provided
for information - not guaranteed.
4-32
The HM-6100 generates all the timing and state signals internally. A crystal is used to control the CPU operating
frequency. The CPU divides the crystal frequency by two. With a 4MHz crystal, the internal states will be of 500ns
duration. The major timing states are described in Figure 1.

T1 For memory reference instructions, a 12-bit address is sent on the DataX, DX, lines. The Load External
Address Register, LXMAR, is used to clock an external register to store the address information externally,
if required. When executing an Input-Output I/O instruction, the instruction being executed is sent on the
DX lines to be stored externally. The external address register then contains the device address and control
information.

Various CPU request lines are priority sampled if the next cycle is an Instruction Fetch cycle. Current state
of the CPU is available externally.

T2 Memory/Peripheral data is read for an input transfer (READ). WAIT controls the transfer duration. If
WAIT is active during input transfers, the CPU waits in the T2 state. The wait duration is an integral mult-
iple of the crystal frequency - 250ns for 4M Hz.

For Memory reference instructions, the Memory Select, MEMSEL, lines are active. For I/O instruction
the DEVSEL, line is active. Control lines, therefore, distinguish the contents of the external register as
memory or device address.

External device sense lines CO, C1, C2, and SKP are sampled if the instruction being executed is an I/O
instruction.

Control Panel Memory Select, CPSE L, and Switch Register Select, SWSE L, become active low for data
transfers between the HM-61 00 and Control Panel Memory and the Switch Register, respectively.

T3,T4,T5
ALU operation and internal register transfers.

T6 This state is entered for an output transfer (WR ITEl. The address is defined during T1. WAIT controls
the time for which the WR ITE data must be maintained.

The following illustrates the timing of the CPU when its operating frequency is low enough that propagation delays can
be ignored. It effectively shows the timing of the CPU when it is single clocked.

LXM'. l.r--, I I I
I
I
~
I
I i~
I .---,_' ---------' I
J----------~ I ----I------ r-
.....
r-
XTC

IFETCH i I I I i I I I

DX,o-1I,
1 'DD @."D~A 'DD @ •••
D~Aw.'TEDAT.W
iKPiCOl I I I I I I I I I 1 1
cT.Cz~AVAL'D~A/W/AYIi;;
DMM}' 1 1 1 1 1 1 1 1 I I 1

.~Alv'L'D~~
WAiT $W'MV.LID~Av.L'Df00'0'?'~Av.LID~P
I I I I I I I I I I I I

FIGURE 1 - Static Timing

4-33
The dynamic or high frequency timing illustrates the propagation delays at specified operating frequencies. (Refer to
specifications) It defines the interface requirements for memory and I/O devices on the bus.

I
I
I

XTBJ~---~ I
XTCJ -u-~ ~
I
I
I TRS%I TWSiU_Tw_H TW~ltr-W-H---
_____ RH I I

REO --=:It TST I I I

=x:::
STATUS I
I TRHTC1 TRHS
RUN/HLT HI1
FIGURE 2 - Dynamic Timing

The block diagram of the CPU architecture, shown on the front page, consists of the following major functional
segments:

• CPU Registers
• Arithmetic and Logic Unit
• Ox-Bus Multiplexer
• Timing and Control Unit

CPU REGISTERS
The CPU consists of five, 12-bit registers, of which three are user programmable; 1) Accumulator (AC), 2) Program
Counter (PC), and 3) Multiply Quotient (MQl. The remaining two registers are the Instruction Register (lR) and the
Memory Address Register (MAR) which are used exclusively for internal operations. The CPU registers are defined as
follows.

All arithmetic and logical operations are performed in the AC. For any arithmetic operation, the AC data and memory
data are combined in the ALU and the result is temporarily stored in the AC. Under software control, the AC can be
cleared, set, complemented, incremented, tested or rotated. Using the Operate Microinstructions, a variety of register
operate instructions can be derived.

The link is a one-bit extension of the AC. It can be complemented with a carry out of the ALU or cleared, set, com-
plemented, tested and rotated along with the rest of the AC. It also serves as the carry output for two's complement
arithmetic.

MULTIPLY QUOTIENT (MQ)

The MQ register can be used as a temporary storage for the AC. The MQ may be OWed with the AC and the result
stored in the AC or the contents of the AC and MQ may be swapped. The MQ is used in conjunction with the AC to
perform multiplication, division, and double-precision operations.
PROGRAM COUNTER (PC)
The PC supports both memory and input-output device operations. For memory operations, the PC is controlled
exclusively by internal logic and instructions fetched from memory. During an instruction fetch cycle the contents of
the PC are transferred to the memory addressregister (MAR) while the current instruction is being decoded. The PC is
then loaded with a new addressor simply incremented for the next instruction depending upon the type of instruction.
The next instruction obtained from memory is then loaded into the Instruction Register. For example, if the instruc-
tion is a JMP X, then the branch addressX is loaded into the PCfor program controlled branching.

Branching can also be controlled by an external device during input-output operations. This feature allows I/O con-
trolled vectored interrupts.

MEMORY ADDRESS REGISTER (MAR)

The MAR contains the address of the memory location that is currently selected for memory or I/O read-write oper-
ations. It is also used for microprogram control during data transfers to and from memory and peripherals.

INSTRUCTION REGISTER OR)

The instruction fetched from memory is held in the IR while being interpreted by the Instruction Decoder. The I R
specifies the initial step of the microprogram sequencefor each instruction and is also used to store temporary data
for microprogram control.

ARITHMETIC AND LOGIC UNIT (ALU)

The ALU performs 12-bit arithmetic, logical and rotate operations. Its input is derived from the AC and anyone of
the other CPU registers. The type of operations performed by the A LU include:
ADD Left-right shifts and rotates
Logical AND Increment
Logical OR Complement
Test AC Set/Clear

OX-BUS MULTIPLEXER
To keep the CPU pin count to a reasonable40 and still maintain a 12-bit word structure, the addressand data paths
are multiplexed by the DX-Bus Multiplexer. It handles data, address and instruction transfers between the CPU and
memory or peripheral deviceson a time-multiplexed basis.

TIMING AND CONTROL UNIT

The Timing and Control Unit generatesthe state and cycle timing signals from a single-phase clock and maintains the
proper sequencesof events required for any processing task. It also decodesthe instruction obtained from the IRand
combines the result with various timing signalsand external control inputs to provide control and gating signals requir-
ed by other functional units (both internal and external to the CPU).

The HM-6100 has a basic addressingcapacity of 4096 12-bit words. The addressingcapacity may be extended to 32K
words by Extended Memory Control hardware. Every location has a unique 4 digit octal (12 bit binary) address,OOOOS
to 7777S (000010 to 409510). The Memory is subdivided into 32 PAGES of 12S words each. Memory Pagesare
numbered sequentially from Page OOS,containing addresses0000-0177S, to Page37S, containing addresses7600S-
7777S. The first 5 bits of a 12-bit MEMORY ADDRESS denote the PAGE NUMBER and the low order 7 bits specify
the PAGE ADDRESS of the memory location within the given Page.
The HM-6100 instructions are 12-bit words stored in memory. The HM-6100 makes no distinction between instruc-
tion and data; it can manipulate instructions as stored variables or execute data as instructions. There are three general
classes of HM-6100 instructions. They are Memory Reference Instructions (MRI), Operate Instructions (OPR). and
Input/Output Transfer Instructions (lOT).

During an instruction fetch cycle, the HM-6100 fetches the instruction pointed to by the PC. The contents of the PC
are transferred to the MAR. The PC is incremented by 1. The PC now contains the address of the "current" instruc-
tion which must be fetched from memory. Bits 0-4 of the MAR identify the CURRENT PAGE, that is, the Page from
which instructions are currently being fetched and bits 5-11 of the MAR identify the location within the Current Page.
(PAGE ZERO (0). 0000B-01778, by definition, denotes the first 128 words of memory and is called the Register Page.)

Since the HM-6100 is a static design it can operate at any crystal frequency from 0 to 8MHz. State times required for
execution are given for each instruction. Execution time can be calculated from the equation:

MEMORY REFERENCE INSTRUCTIONS (MRI)

The Memory Reference Instructions operate on the contents of a memory location or use the contents of a memory
location to operate on the AC or the PC. The first 3 bits of a Memory Reference Instruction specify the operation
code, or OPCODE, and the low order 9 bits, the OPERAND address, as shown in Figure 4.

IA: Indirect Addressing 0 = Direct; 1 = Indirect

MP: Memory Page 0 = Register Page; 1 = Current Page

Bits 5 through 11, the PAGE ADDR ESS, identify the location of the OPE RAND on a given page, but they do not iden-
tify the page itself. The page is specified by bit 4, called the CURRENT PAGE OR REGISTER PAGE BIT. If bit 4 is
a 0, the page address is interpreted as a location on the Register Page. If bit 4 is a 1, the page address specified is inter-
preted to be on the Current Page.

By this Method, 256 locations may be directly addressed, 128 on the REGISTER PAGE and 128 on the CURRENT
PAGE. Other locations are addressed by using bit 3. When bit 3 is a 0, the operand address is a DIRECT ADDRESS.
An INDIRECT ADDRESS (pointer address) identifies the location that contains the desired address (effective address).
To address a location that is not directly addressable, not in the REGISTER PAGE or in the CURRENT PAGE, the
absolute address of the desired location is stored in one of the 256 directly addressable locations (pointer address).
Upon execution, the MR I will operate on the contents of the location identified by the address contained in the pointer
location. Note that locations 00108-00178 in the Register Page are AUTOINDEXED. When these locations are used
for index registers their contents are incremented by 1 and restored before they are used as the operand address. These
locations are therefore convenient for indexing applications.

Combinations of mode and page bits yield four (4) addressing modes:
• Current Page, Direct
• Current Page, Indirect
• Register Page, Direct
• Register Page, Indirect

A fifth addressing mode results from use of the AUTOINDEX registers:

• Register Page, Autoindexed
 NUMBER OF STATES
MNE- OP AUTO-
MONIC CODE DIRECT INDIRECT INDEXED

LOGICAL AND: Causes a bit-by-bit boolean AND be-

tween the contents of the Accumulator and the contents of
the effective address (XXX) specified by the instruction.
The result is left in the AC and the data word in the refer-
enced location is not altered.

TWO'S COMPLEMENT ADD: Performs a binary two's

complement addition between the specified data word and
the contents of the AC; the result is left in the AC. If a
carry out occurs, the state of the Link is complemented.
If the AC is initially cleared, this instruction acts as a
LOAD from memory.

INCREMENT AND SKIP IF ZERO: The contents of the

effective address are incremented by 1 and restored. If the
result is zero, the next sequential instruction is skipped.

DEPOSIT AND CLEAR THE ACCUMULATOR: The con-

tents of the AC are stored in the effective address and the
AC is cleared.

JUMP TO SUBROUTINE: The contents of the PC are

stored in the effective address and the effective address + 1
is stored in the PC. The link, AC, and MO are unchanged.

JUMP: The effective address is loaded into the PC thus

causing program execution to branch to a new location.

INPUT/OUTPUT TRANSFER: Used to initiate the opera-

tion of peripheral devices and to transfer data between the
peripherals and the CPU.

OPERATE Instructions: Used to perform logical opera-

tions on the contents of the major registers.
2 - Cycle OPERATE
3 - Cycle OPERATE

The Operate Instructions, which have an OPCODE of 78(111), consist of 3 groups of microinstructions. Group 1
microinstructions, which are identified by the presence of a 0 in bit 3, are used to perform logical operations on the
contents of the accumulator and link. Group 2 micro instructions, which are identified by the presence of a 1 in bit 3
and a 0 in bit 11, are used primarily to test the contents of the accumulator and then conditionally skip the next
sequential instruction. Group 3 microinstructions have a 1 in bit 3 and a 1 in bit 11 and are used to perform logical
operations on the contents of the AC and MO.

The basic OPR instruction format is shown in Figure 5. Operate microinstructions from any group may be micropro-
grammed with other operate microinstructions of the same group. The actual code for a microprogrammed combina-
tion of two, or more, microinstructions is the bitwise logical OR of the octal codes for the individual microinstructions.
When more than one operation is microprogrammed into a single instruction, the operations are performed in a pre-
scribed sequence, with logical sequence number 1 microinstructions performed first, logical sequence number 2 micro-
instructions performed second, logical sequence number 3 microinstructions performed third, and so on. Two opera-
tions with the same logical sequence number, within a given group of microinstructions, are performed simultaneously.
 MICROINSTRUCTION A B

Group 1 0 0/1

Group 2 1 0

Group 3 1 1

GROUP 1 MICROINSTRUCTIONS
Figure 6 shows the instruction format of a group 1 microinstruction. Anyone of bits 4 to 11 may be set, loaded with
a binary 1, to indicate a specific group 1 microinstruction. If more than one of these bits is set, the instruction is a
microprogrammed combination of group 1 microinstructions, which will be executed according to the logical sequence
shown in Figure 6.

logical Sequences: BIT B BIT9 BIT 10 FUNCTION

1- ClA Cll
2 - CMA CMl 0 0 1 BSW
3 -lAC 0 1 0 RAl
4 - RAR RAl RTR RTL BSW 0 1 1 RTl
1 0 0 RAR
1 0 1 RTR

Table 2-1 lists commonly used group 1 microinstructions, their assignedmnemonics, octal number, instruction format,
logical sequence,the operation they perform, and the number of states. The sameformat is followed in Table 3 and 4
which corresponds to group 2 and 3 microinstructions, respectively.

There are severalcommonly used microprogrammed combinations of group 1 microinstructions. These are listed in
Table 2-2. When writing programs it is necessaryto load various constants into the AC for such purposes as initiallizing
counters and to provide comparisons. Table 2-3 lists those constants which can be loaded directly via microprogramm-
ed combinations of group 1 instructions.

NUMBER
MNE- OCTAL LOGICAL OF
MONIC CODE SEQUENCE STATES OPERATION
NOP 7000 1 10 NO OPERATION - This instruction causesa 10 state delay in program
execution, without affecting the state of the HM-6100. It may be used
for timing synchronization or as a convenient means of deleting an
instruction from a program.

CLA 7200 1 10 CLEAR ACCUMULATOR - The accumulator is loaded with binary O's.
 NUMBER
MNE- OCTAL LOGICAL OF
MONIC CODE SEQUENCE STATES OPERATION

CLL 7100 1 10 CLEAR LINK - The link is loaded with a binary O.

CMA 7040 2 10 COMPLEMENT ACCUMULATOR - The content of each bit of the AC is

complemented. This has the effect of replacing the contents of the AC
with its one's complement.

CML 7020 2 10 COMPLEMENT LINK - The content of the link is complemented.

lAC 7001 3 10 INCREMENT ACCUMULATOR - The content of the AC is increment-

ed by one (1) and the carry out componments the Link (L).

BSW 7002 4 15 BYTE SWAP - The right six (6) bits of the AC are exchanged or
SWAPPED with the left six bits. AC(O) is swapped with AC(6). AC(1)
with AC(7), etc. The link is not affected.

RAL 7004 4 15 ROTATE ACCUMULATOR LEFT - The content of the AC and L are
rotated one binary position to the left. AC(O) is shifted to Land L is
shifted to AC(11). The ROTATE instructions use what is commonly
called a circular shift, meaning that any bit rotated off one end of the
accumulator will reappear at the other end.

RTL 7006 4 15 ROTATE TWO LEFT - The contents of the AC and L are rotated two
binary positions to the left. AC(1) is shifted to Land L is shifted to
AC(10).

RAR 7010 4 15 ROTATE ACCUMULATOR RIGHT - The contents of the AC and L are
rotated one binary position to the right. AC(11) is shifted to Land Lis
shifted to AC(O).

RTR 7012 4 15 ROTATE TWO RIGHT - The contents of the AC and L are rotated two
binary positions to the right. AC(10) is shifted to Land L is shifted to
AC(l).

NUMBER
MNE- OCTAL LOGICAL OF
MONIC CODE SEQUENCE STATES OPERATION

CLA CLL 7300 1 10 CLEAR ACCUMULATOR - CLEAR LINK

CIA 7041 2,3 10 COMPLEMENT AND INCREMENT ACCUMULATOR - The con-

tent of the AC is replaced with its two's complement. The carry
out complements the link. This is a microprogrammed combina-
tion of CMA and lAC.

STL 7120 1,2 10 SET THE LINK - The LINK is loaded with a binary 1 correspond-
ing with a microprogrammed combination of CLL and CML.

STA 7240 1,2 10 SET THE ACCUMULATOR - Each bit of the AC is set to 1 corr-
esponding to a microprogrammed combination of CLA and CMA.

CLA lAC 7201 1,3 10 Sets the accumulator to a 1.

 NUMBER
MNE- OCTAL lOGICAL OF
MONIC CODE SEQUENCE STATES OPERATION

GlK 7204 1,4 15 GET LINK - The AC is cleared and the content of the link is
shifted into AC(11) while a 0 is shifted into the link. This is a
microprogrammed combination of ClA and RAL.

Cll RAl 7104 1,4 15 CLEAR LINK - ROTATE ACCUMULATOR lEFT

Cll RTL 7106 1,4 15 CLEAR LINK - ROTATE TWO lEFT

Cll RAR 7110 1,4 15 CLEAR liNK - ROTATE ACCUMULATOR RIGHT

Cll RTR 7112 1,4 15 CLEAR LINK - ROTATE TWO RIGHT

NUMBER
OCTAL lOGICAL OF DECIMAL
MNEMONIC CODE SEQUENCE STATES CONSTANT INSTRUCTIONS COMBINED

NlOOOO 7300 1 10 0 ClA Cll

NlOO01 7301 1,3 10 1 ClA Cll lAC
NlOO02 7305 1,3,4 15 2 ClA Cll lAC RAl
NlOO03 7325 1,2,3,4 15 3 ClA Cll CMl lAC RAl
NlOO04 7307 1,3,4 15 4 ClA Cll lAC RTl
NlOO06 7327 1,2,3,4 15 6 ClA Cll CMl lAC RTl
Nl0100 7303 1,3,4 15 64 ClA lAC BSW
Nl2000 7332 1,2,4 15 1024 ClA Cll CMl RTR
Nl3777 7350 1,2,4 15 2047 ClA Cll CMA RAR
Nl4000 7330 1,2,4 15 -0 ClA Cll CMl RAR
Nl5777 7352 1,2,4 15 -1025 ClA Cll CMA RTl
Nl6000 7333 1,2,3,4 15 -1024 ClA Cll CMl lAC RTR
Nl7775 7346 1,2,4 15 -3 ClA Cll CMA RTl
Nl7776 7344 1,2,4 15 -2 ClA Cll CMA RAl
Nl7777 7340 1,2 10 -1 ClA Cll CMA

GROUP 2 MICROINSTRUCTIONS
Figure 7 shows the instruction format of group 2 microinstructions, Bits 4 - 10 may be set to indicate a specific group
2 microinstruction. If more than one of bits 4 - 7 or 9 - 10 is set, the instruction is a microprogrammed combination
group 2 microinstructions, which will be executed according to the logical sequence shown in Figure 7 .

logical Sequences: • Reverse sensing BIT:

1 (BIT 8 = 0) -SMA or SZA or SNl Unconditional SKIP when
(BIT 8 = 1) -SPA or SNA or SZl BITS 5, 6, & 7 are O's
2 -ClA
3 -OSR,HlT

Skip microinstructions may be microprogrammed with ClA, OSR, or H l T microinstructions. Skip microinstructions
which have a 0 in bit 8, however, may not be microprogrammed with skip microinstructions which have a 1 in bit 8.
When two or more skip microinstructions are microprogrammed into a single instruction, the resulting condition on
which the decision will be based is the logical OR of the individual conditions when bit 8 is 0, or when bit 8 is 1, the
decision will be based on the logical AND.
 NUMBER
MNE- OCTAL LOGICAL OF
MONIC CODE SEQUENCE STATES OPERATION

NOP 7400 1 10 NO OPERATION - See Group 1 microinstructions.

CLA 7600 2 10 CLEAR ACCUMULATOR - The accumulator is loaded with binary

O's.

HLT 7402 3 10 HALT - Program stops at the conclusion of the current machine
cycle. If H LT is combined with others in OPR 2, the other opera-
tions are completed before the end of the cycle.

SKP 7410 1 10 SKIP - The content of the PC is incremented by 1, to skip the next
instruction.

SNL 7420 1 10 SKIP ON NON-ZERO LINK - The content of L is sampled; the

next sequential instruction is skipped if L contains a 1. If L contains
a 0, the next instruction is executed.

SZL 7430 1 10 SKIP ON ZERO LINK - The instruction is skipped if the link con-
tains a O.

SZA 7440 1 10 SKIP ON ZERO ACCUMULATOR - The content of the AC is sam-

pled; the next sequential instruction is skipped if all AC bits are O.
If any bit in the AC is a 1, the next instruction is executed.

SNA 7450 1 10 SKIP ON NON-ZERO ACCUMULATOR - The next instruction is

skipped if anyone bit of the AC contains a 1. If every bit in the AC
is 0, the next instruction is executed.

SMA 7500 1 10 SKIP ON MINUS ACCUMULATOR - If the content of AC(O) con-

tains a negative two's complement number, the next sequential in-
struction is skipped. If AC(O) contains a 0, the next instruction is
executed.

SPA 7510 1 10 SKIP ON POSITIVE ACCUMULATOR - If the content of AC(O)

contains a 0, indicating a positive two's complement number, the
next sequential instruction is skipped.

OSR 7404 3 15 OR WITH SWITCH REGISTER - The content of the Switch Regist-
ter is inclusively OWed with the content of the AC and the result
stored in the AC. The HM-6100 sequences the OSR instruction
through a 2-cycle execute phase referred to as OPR 2A and OPR 28.
This instruction provides the simplest way to input data to the HM-
6100 from peripherals.

LAS 7604 1,3 15 LOAD ACCUMULATOR WITH SWITCH REGISTER - The content
of the AC is loaded with the content of the SR, bit for bit. This is
equivalent to a microprogrammed combination of CLA and OSR.
Table 3 - 2 lists every legal combination of skip microinstructions, along with the resulting condition upon which the
decision to skip or execute the next sequential instruction is based. When these combinations include a CLA, the
accumulator is cleared after the decision is made. This is a useful trick to save code when a new value will be T AD'ed
into the AC.

NUMBER
OCTAL LOGICAL OF
MNEMONIC CODE SEOUENCE STATES OPERATION

SZA SNL 7460 1 10 Skip if AC = 0 or L = 1 or both.

SNA SZL 7470 1 10 Skip if ACJ"O and L = O.
SMA SNL 7520 1 10 Skip if AC< 0 or L = 1 or both.
SPA SZL 7530 1 10 Skip if AC ~O and L = O.
SMA SZA 7540 1 10 Skip if AC ~O.
SPA SNA 7550 1 10 Skip if AC >0.
SMA SZA SNL 7560 1 10 Skip if AC~O or L = 1 or both.
SPA SNA SZL 7570 1 10 Skip if AC >0 and L = O.

When writing an actual program, it is useful to think in terms of the FORTRAN relational operators -.L T., .EO., etc.-
when trying to compare numbers. The following method along with Table 3 - 3 will provide this.

CLA CLL I Initialize AC and Link

TAD B IFetch 2nd number
CML CMA lAC ICreate "-B" lAC & L act like a 13 bit accumulator)
TAD A IFetch 1st number
Test CLA IUse instructions from Table 3 - 3 to provide test
/The C LA is optional to provide a clear AC after test
IBranch to FAI L routine if test failed
ITest passed, continue with program

UNSIGNED SIGNED
SKIP IF COMPARE COMPARE

A. NE. B SNA SNA

A. LT. B SNL SMA
A. LE.B SNL SZA SMA SZA
A. EO. B SZA SZA
A.GE. B SZL SPA
A. GT. B SZL SNA SPA SAN

Figure 8 shows the instruction format of group 3 microinstructions which requires bits 3 and 11 to contain a 1. Bits 4,
5 or 7 may be set to indicate a specific group 3 microinstruction. If more than one of the bits is set, the instruction is
a microprogrammed combination of group 3 microinstructions following the logical sequence listed in Figure 8.

Logical Sequences:
1 - CLA
2 - MOA, MOL
3 - NOP
 NUMBER
MNE- OCTAL LOGICAL OF
MONIC CODE SE~UENCE STATES OPERATION

NOP 7401 3 10 NO OPERATION - Seegroup 1 microinstructions.

CLA 7600 1 10 CLEAR ACCUMULATOR

MQA 7501 2 10 MQ REGISTER INTO ACCUMULATOR - The content of the MQ

is logical OR'ed with the content of the AC and the result is loaded
into the AC. The original content of the AC is lost but the original
content of the MQ is retained. This instruction provides the pro-
grammer with an inclusive OR operation.

MQL 7421 2 10 MQ REGISTER LOAD - The content of the AC is loaded into the
MQ, the AC is cleared and the original content of the MQ is lost.
This is similar to a DCA instruction.

ACL 7701 1,2 10 CLEAR ACCUMULATOR AND LOAD MQ REGISTER INTO

ACCUMULATOR - This is equivalent to a mlcroprogrammad com-
bination of CLA and MQA. It is similar to the two instruction
combination of CLA and TAD.

CAM 7621 1,2 10 CLEAR ACCUMULATOR AND MQ REGISTER - Tha content of

the AC and MQ are loaded with binary O's. This is equivalent to a
microprogram combination of CLA and MQL.

SWP 7521 2 10 SWAP ACCUMULATOR AND MQ REGISTER - The content of

the AC and MQ are interchanged by accompilshing a mlcropro-
grammed combination of MQA and MQL.

CLA SWP 7721 1,2 10 CLEAR ACCUMULATOR AND SWAP ACCUMULATOR AND
MQ REGISTER - Tha content of the AC Is cleared. The content
of the MQ Is loaded Into the AC and the MQ Is cleared.

Input Output Trllns!sr Instructions (lOT)

The Input/output transfer Instructions, which have an OPCODE of 68 are used to initiate the operation of paripheral
devices and to transfer data between peripherals and the HM-6100. Three types of data transfer may be used to receive
or transmit information between the HM-6100 and one or more peripheral I/O devices. PROGRAMMED DATA
TRANSFER provides a straightforward means of communicating with relatively slow I/O devices, such as Teletypes,
cassettes,card readers and CRT displays. INTERRUPT TRANSFERS usa the interrupt system to serviceseveralperi-
pheral devices simultaneously, on an intermittent basis,permitting computational operations to be performed concurr-
ently with the data I/O operations. Both Programmed Data Transfers and Program Interrupt Transfers use the accumu-
lator as a buffer, or storage area, for all data transfers. Since data may be transferred only between the accumulator
and the peripheral, only one 12 bit word at a time may be transferred. DIRECT MEMORY ACCESS, DMA, Transfers
variable-size blocks of data between high-speed peripherals and the memory with minimum of program control requir-
ed by the HM-6100.

lOT INSTRUCTION FORMAT

 The first three bits, 0 - 2, are always set to 68 (110) to specify an lOT instruction. The next 9 bits, 3 - 11, are user de-
finable and can provide a minimal implementation when each bit controls one operation. When following PDP-8/E
format, the next six bits, 3 - 8, contain the device selection code that determines the specific I/O device for which the
lOT instruction is intended and, therefore, permit interface with up to 64 I/O devices. The last three bits, 9 - 11, con-
tain the operation specification code that determines the specific operation to be performed. The nature of this opera-
tion for any given lOT instruction depends entirely upon the circuitry designed into the I/O device interface.

Programmed Data Transfer is the easiest, simplest, most convenient and most common means of performing data I/O.
For microprocessor applications, it may also be the most cost effective approach. The data transfer begins when the
HM-6100 fetches an instruction from the memory and recognizes that the current instruction is an lOT @. This is
referred to an IFETCH and consists of five (5) internal states. The HM-6100 sequences the lOT instruction through a
2-cycle execute phase referred to as IOTA and 10TB. Bits 0 - 11 of the lOT instruction are available on DXO - 11 at
IOTA /\ LXMAR @. These bits must be latched in an external address register. DEVSEL is active low to enalbe data
transfers between the HM-6100 and the peripheral device @)&@. Input-Output Instruction Ti~g~ shown in-.£.!g-
ure 10. The selected peripheral device communicates with the HM-61 00 through 4 control lines - CO, C1, C2 and SKP.
In the HM-6100 the type of data transfer, during an lOT instruction, is specified by the peripheral device(s) by assert-
ing the control lines as shown in Tables 5-1 and 5-2.

The control line SKP, when low during an lOT, causes the HM-6100 to skip the next sequential instruction. This fea-
ture is used to sense the status of various signals in the device interface. The CO, C1, and C2 lines are treated indepen-
dently of the SKP line. In the case of a RELATIVE or ABSOLUTE JUMP, the skip operation is performed after the
jump. The input signals to the HM-6100, DXO - 11, CO, C1, C2 and SKP, are sampled during IOTA on the rising edge
of time state 3 @. The data from the HM-6100 is available to the device during DEVSEL /\ XTC @. The 10TB
cycle is internal to the HM-6100 to perform the operations requested during IOTA. 80th IOTA and lOTS consists of
six (6) internal states.

T-5TATES Tl Tl Tl Tl
I 1 1 I
DXIO-11J~ ~ Cll1l:J•.....-------------C
I I I I
IFETCH j I r
I I 1
lXMAR -F"l n
...• r
XTA
I
~r__1 ~r__1 ~r__1•. _1

1 1 I
XTB ..J! ~r-"1 ~ ...... ~r__
I I I
XTC j •.... .:-------... ...• L- ---',
1 I
MEMlli --, _
I 1
DEVffi ~-------U----------------
__ I I
sg.~-_-_-_-_-_-_-_-_-_- -I ,- -_-_-_-_-_-_-_-_-_-_-_-_-_-_- __
. I I I I
WAiT -_ -_-L---...l\....- -_-_-_ -_-L--...l\....-_ -_-_- _-L.....1\...-_-_-_-_-_-_-_ -_ -_- _-_- _-

I I
 TABLE5-1
AC DATA TRANSFERS

CONTROL LINES
SKP CO C1 C2 OPERATION DESCRIPTION

H H H H DEV-AC The content of the AC is sent to the device.

H L H H DEV-AC;CLA The content of the AC is sent to a device and then the AC is

cleared.

H H L H AC-ACV DEV; Data is received from a device 0 R'ed with the data in the AC
DEV-AC and the result is stored in the AC. The new AC content is
sent to the device.

H L L H AC-DEV; Data is received from a device and loaded into the AC. The
DEV-AC new AC content is sent to the device.

L H H H DEV-AC; The content of the AC is sent to the device and the micro-
PC-PC+ 1 processor skips the next sequential instruction.

L L H H DEV - AC; CLA; The content of the AC is sent to a device, the AC is cleared,
PC -PC+ 1 and the microprocessor skips the next sequential instruction.

L H L H AC-ACV DEV; Data is OR'ed into the AC, the new AC sent to the device,
DEV-AC; and the microprocessor skips the next sequential instruction.
PC-PC+1

L L L H AC-DEV; Data is loaded into the AC, the new AC contents sent to the
DEV-AC device, and the next sequential instruction skipped.
PC-PC+1

TABLE5-2
PC VECTOR TRANSFERS

CONTROL LINES
SKP CO C1 C2 OPERATION DESCRIPTION
H
· H L PC - PC + DEV Data from the device is added to the contents
This is referred to as a RELATIVE JUMP.
of the PC.

H
· L L PC -DEV Data is received from a device and loaded into the PC. This
is referred to as an ABSO LUTE JUMP.

L
· H L PC-
PC-PC+1
PC + DEV; The RELATIVE JUMP is performed and then the micropro-
cessor skips the next sequential instruction.

L · L L PC-DEV;
PC-PC+1
The ABSOLUTE JUMP is executed and then the next se-
quential instruction is skipped.

The program interrupt system may be used to initiate programmed data transfers in such a way that the time spent
waiting for device status is greatly reduced or eliminated altogether. It also provides a means of performing concurr-
ent programmed data transfers between the HM-6100 and the peripheral devices. This is accomplished by isolating
the I/O handling routines from the mainline program and using the interrupt system to ensure that these routines are
entered only when an I/O device status is set, indicating that the device is actually ready to perform the next data
transfer, or that is requires some sort of intervention from the running program.
 TABLE 6
PROCESSORlOT INSTRUCTIONS

MNE- OCTAL
MONIC CODE OPERATION
SKON 6000 SKIP IF INTERRUPT ON - If Interrupt system is enabled, the next sequential instruction is
skipped. The Interrupt system is disabled.

ION 6001 INTERRUPT TURN ON - The internal interrupt acknowledge system is enabled. The inter-
rupt system is enabled after the CPU executes the next sequential instruction.

IOF 6002 INTERRUPT TURN OFF - The interrupt system is disabled. Note that the interrupt system
is automatically disabled when the CPU acknowledges an INT request.

SRO 6003 SKIP IF INT REOUEST - The next sequential instruction is skipped if the INT request bus
is low.

GTF 6004 GET FLAGS - The following machines states are read into the indicated bits of AC.
bit 0 - Link
bit 1 - Greater than flag" bit 4 - Interrupt Enable FF"
bit 2 - INT request bus bit 6 - User fleg"
bit 3 - Interrupt Inhibit FF" bit 6 - 11 - SeveField Register"
" These bits are modified by externel devices driving the DX bus and the ~-IInes (CO· L,
Ci· L). For exemple, bits 1 and 6 - 11 ere pert of the Extended Memory Control.

RTF 6006 RETURN FLAGS - Link is restored from AC (0). Interrupt system is enebled after the next
sequentiel instruction Is executed. All AC bits ere available externelly to restore externel
stetes. (ex. Extended memory control). (CO· H, 'Ci • H)

SGT 6006 SKIP ON GREATER THAN FLAG - Operetion is determined by external devices, if eny.
This fleg Is external and must control the skip line.

CAF 6007 CLEAR ALL FLAGS - AC and link are cleared. Interrupt system is disabled.

The interrupt system allows certain external conditions to Interrupt the computer program by driving the 'iiii'i'REQ
input to the HM-6100 low. If no higher priority requestsare outstanding and the interrupt system is enabled, the HM-
6100 grants the device interrupt at the end of the current instruction. After an interrupt has been grented, the Inter-
rupt Eneble Flip-Flop in the HM-6100 is reset so that no more interrupts are acknowledged until the interrupt system
is re-enabled under progrem control.

The current content of the Program Counter, PC, is deposited in location OOOOaof the memory and the program fetch-
es the Instruction from location 0001a. The return addressis available in location OOOOa.This addressmust be saved,
possibly in a software stack, if nested interrupts are permitted. The INTGNT signal is activated by the HM-6100 when
a device interrupt is acknowledged. This signal is reset by executing any lOT instruction. The INTGNT is also useful in
implementing an External Vectored Priority Interrupt network.

The user program controls the interrupt mechanism of the HM-6100 by executing the processor lOT instructions listed
in Table 6. Several of these interrupt lOT instructions are also used if the memory is extended beyond 4K words.

Direct Memory Access,sometimes called data break, is the perferred form of data transfer for use with high-speed stor-
age devices such as magnetic disk or tape units. The DMA mechanism transfers data directly between memory and
peripheral devices. The HM-6100 is involved only is setting up the transfer; the transfers take place with no processor
intervention on a "cycle stealing" basis. The DMA transfer rate is limited only by the bandwidth of the memory and
the data transfer characteristics of the device.

The device generatesa DMA Request when it is ready to transfer data. The HM-6100 grants the DMAREO by activat-
ing the DMAGNT signal at the end of the current instruction. The HM-6100 suspendsany further instruction fetches
until the DMAREO line is released. The OX lines are tri-stated, all SEL lines are high, and the external timing signals
XTA, XTB, and XTC are active. The device which generated the DMAR EO must provide the address and necessary
control signals to the memory for data transfers. The DMAREO line can also be used as a level sensitive "pause" line.
The HM-6100 CPU provides a unique Control Panel (CP) feature through its CPREO input and CPSEL output lines.
After acknowledging the control panel request, the CPU generates the necessary timing to execute program code in CP
memory while also providing the capability to transfer data between CP memory and the user memory using the AC as
a buffer. This allows the user memory to be examined and/or modified by the CP software. The CPU will output the
MEMSEL signal for all user memory references while the CPSEL signal is generated for CP memory references as shown
in Figure 11.

The designer can make use of the control panel features to implement various functions that will be "transparent" to
the user's (main) memory. Some of the more common functions include:
• Binary Loader and Punch
• Register Examination and Modification
• Single Cycle
• Octal Debug with Breakpoints
• Octal listing
• Auto Bootstrap

When a CPREO is granted the PC is stored in location 0000 of Panel Memory and the HM-6100 resumes operation at
location 7777 of the Panel Memory. The CPR EO bypasses the interrupt enable system and the processor lOT instruc-
tion, ION and IOF, are ignored while the HM-6100 is in the Control Panel Mode. Once a CPREO is granted, the HM-
6100 will not recognize any DMAREO or INTREO until the CPREO has been fully serviced.

During Control Panel program execution access to the user memory is gained through use of indirect TAD, AND, DCA
and ISZ instructions. The CPU will transfer control from CPSEL to MEMSEL during the execute phase of these in-
structions. The instructions are always fetched from control panel memory.

Exiting from the control panel routine is achieved by executing the following sequence:
• ION
• JMP I DODO/Exit via location 0000 in Panel Memory

Location 0000 contains either the original return address deposited by the HM-61 00 when the CP routine was entered,
or it may be a new starting address defined by the CP routine.

After an instruction is completely sequenced, the major state generator scans the internal priority network as shown in
in Figure 12. The state of the priority network decides the next sequence of the HM-6100.

The CPU samples the RESET line, the request lines CPR EO, DMAREO, and INTREO, and the state of its internal RUN
flip-flop during the last execute cycle of each instruction. The worst case response time of the HM-6100 to an external
request is, therefore the time required to execute the longest instruction preceded by any 6-state execution cycle. For
the HM-6100, this is an autoindexed ISZ, 22 states, preceded by any 6-state execution cycle instruction. The worst
case response time is, therefore, 28 states, 14 IJs at 4M Hz clock frequency.
When the HM-6100 is initially powered up, the state of the timing generator is undefined. The generator is automatic-
ally initialized with a maximum of 34 clock pulses. The request inputs, as the HM-6100 is powered on, must span at
least 58 clock pulses to be recognized, 34 clocks for the counter to initialize and a maximum of two HM-6100 cycles
(20 to 24 clocks) for the state generator to sample the request lines. A positive transition of RUN/HLTshould occur at
least 10 clock pulses after RESET to be recognized.

The priority hierarchy is:

• RESET - If the RESET line is asserted at the sample time, the processor immediately sets its program counter
to 7777, clears the Accumulator and Link, and puts the processor in the HALT state. While halted, the pro-
cessor continues to cycle and generate the timing signals XTA, XTB, and XTC. During reset the DX line is tri-
stated and the SE L lines are high.
• CPREQ - If the RESET line is not found to be asserted, but the CPREQ line is, the processor grants the control
panel interrupt request at the end of the current cycle.

• RUN/HLT - If neither of the foregoing lines are asserted, but the processor finds its internal RUN FF in the halt
state, it enters the HALT cycle at the end of the last execute cycle. Pulsing the RUN/H LT line low causes the
HM-6100 to alternately run and halt. The internal RUN FF changes state on the rising edge of the RUN/HLT
line. While halted the processor continues to generate the timing signals XTA, XTB, and XTC.

• DMAREQ - DMA requests are granted at the end of the current cycle only if none of the above actions are
pending.
• iiiJ'i'REQ - An interrupt request is granted at the end of the current cycle only if none of the higher priority
lines preempts it.
• IFETCH - If none of the above actions are indicated, the processor will fetch the next sequential instruction in
the next cycle.

The HM-6100 samples the WAIT line during input-output data transfers. The WAIT line, if active low, controls the
transfer duration. If WAIT is active during input transfers (READ). the CPU waits in the T2 state. For an output trans-
fer {WRITEL WAIT controls the time for which the write data is maintained on the DX lines by extending the T6 state.
When operating at the max frequency, the internal delay of the HM-6100 causes the falling edge select lines to be past
the WAIT setup time for WRITE. The rising edge of the select line for READ can be used to activate WAIT for a
WR ITE. The wait duration is an integral multiple of the oscillator time period (Figure 13).
 ADVANCE
STATE
COUNTER

ADVANCE
ONE CLOCK
PULSE

An inexpensive crystal can be used th~reby eliminating the need for a clock generator. The crystal operates at parallel
resonance, and thus is looks inductive in the circuit. An "AT" cut crystal should be used because it has a low tempera-
ture coefficient and can be used over a wide temperature range. The Feedback resistor and shunt capacitance are in-
cluded internally. The crystal parameters needed are:
• Frequency
• Mod of Resonance - Parallel (anti-resonant)
• Maximum Power level - 1 milliwatt
• Load Capacitance - 32pF
• Series Resistance (max) - 250n

For precise frequency determination the effect of the stray circuit capacitance and internal 30pF capacitance must be

---=-1
taken into account.

OSC r---
OUT 141

o XTAL I I
~ I
USING AN EXTERNAL CLOCK GENERATOR
L ---~FIGURE 14 - Oscillator input schematic

When a system clock is needed, egofor a baud rate generator for UARTs, the HM-6100 can be externally clocked, thus
eliminating the need for separate crystals. The external clock can be connected to the oscillator output pin while
grounding oscillator input. This has the effect of over driving the small internal oscillator inverter causing an increase
in supply current.
Duty cycle - 50/50
T rise, Tfall - 20m
 ACTIVE ACTIVE
PIN SYMBOL LEVEL OESCRIPTION PIN SYMBOL LEVEL OESCRIPTION

1 VCC Supply voltage. 10 LXMAR H The Load External Address Register is

2 RUN H The signal indicates the run state of the used to store memory and peripheral
CPU and may be used to power down address externally.
the external ci rcuitry II WAIT L Indicates that peripherals or external
3 DMAGNT H Direct Memory Access Grant-OX lines memory is not ready to transfer data.
are three-state. The CPU state gets extended as long as
4 DMAREQ L Direct Memory Access Request-DMA WAIT is active. The CPU is in the lowest
is granted at the end of the current in- power state with clocks running.
struction. Upon DMA grant, the CPU 12 XTS H External coded minor cycle timing-
suspends program execution until the signifies output transfers from the
~ line is released. H~100.
5 CPREQ L Control Panel Request-a dedicated in- 13 XTC H External coded minor cycle timing-
terrupt which bypasses the normal used in conjunction with the Select Lines
device interrupt request structure. to specify read or write operations.
6 RUN/HLT L Pulsing Ihe Run/Halt line causes the 14 OSCOUT Crystal input to generate the internal
CPU to alternately run and halt by timing (also external clock input).
Chang~ the state of the internal 15 OSCIN See Pin 14-0SC OUT (also external
RUN/ flip flop. clock ground)
7 RESET L Clears the AC and loads 77778 into the 16 DXO DataX-multiplexed data in, data out
PC. CPU is halted. and address lines.
8 INTREQ L Peripheral device interrupt request. 17 DX1 See Pin 16-DXO.
9 XTA H External coded minor cycle timing- 18 DX2 See Pin 16-DXO.
signifies input transfers to the HM.£100. 19 DX3 See Pin 16-DXO.
20 DX4 See Pin 16-DXO.

ACTIVE ACTIVE
PIN SYMBOL LEVEL OESCRIPTION PIN SYMBOL LEVEL OESCRIPTION
21 DX5 See Pin 16-DXO. 33 C1 L See Pin 32-CO.
22 DX6 See Pin 16-DXO. 34 C2 L See Pin 32-CO.
23 DX7 See Pin 16-DXO. 35 SKP L Skips the next sequential instruction if
24 DX8 See Pin 16-DXO. active during an I/O instruction. IT able 5)
25 DX9 See Pin 16-DXO. 36 IFETCH H Instruction Fetch Cycle
26 GND Ground 37 MEMSEL L Memory Select for memory transfers.
27 DX10 See Pin 16-DXO. 38 CPSIT L The Control Panel.Memory Select be-
28 DX11 See Pin 16-DXO. comes active, instead of the MEMSEL,
29 LINK H wnk flip flop. for control panel routines. Signal may be
30 DEVSEL L Device Select for I/O transfers. used to distinguish between control
31 SWSEL L Switch Register Select for the OR THE panel and main memories.
SWITCH REGISTER INSTRUCTION 39 INTGNT H Peripheral device Interrupt Grant
(OSR). OSR is a Group 2 Operate 40 DATAF H Data Field pin indicates the execute
Instruction which reads a 12 bit external phase of indirectly addressed AND,
switch register and OR's it with the con- TAD, ISZ and DCA instructions so that
tents of the AC. the data transfers are controlled by the
32 CO L Control line inputs from the peripheral Data Field, OF, and not the Instruction
device during an I/O transfer (Table 5). Field. IF, if Extended Memory Control
hardware is used to extend the address-
ing space from 4K to 32K words.
;II HARRIS CMOS PARALLEL
HD-6101
INTERFACE ELEMENT
(PIE)

• HM-6100 COMPATIBLE

• LOW POWER STANDBY ~OO/-LW MAX

• SINGLE SUPPLY 4-11 VOLTS

• FULL TEMPERATURE RANGE -550C TO +12SoC Vcc POUT

~/iNT
• STATIC OPERATION INTGNT
PRIN WRITE 2
• 4 PROGRAMMABLE OUTPUTS (FLAGS)
SENSE 4 ~
• 4 PROGRAMMABLE SENSE INPUTS SENSE 3 WRITE 1

• CONTROL FOR TWO 12 BIT INPUT PORTS SENSE 2 RUJ)l

SENSE 1 C2
• CONTROL FOR TWO 12 BIT OUTPUT PORTS
SEL 3 Ci
• PRIORITY VECTORED INTERRUPTS SEL 4 FLAG 1

• UP TO 31 PIE'S PER SYSTEM LX MAR FLAG 2

SEL 5 FLAG 3
• 16 INSTRUCTIONS FOR PIE CONTROL
SEL 6 FLAG 4
XTC OEVSEL
SEL 7 GNO

The HD-6101 Parallel Interface Elements (PIE) are high speed, low power, OXO OX11
OXl OX10
silicon gate CMOS general purpose devices which provide addressing
OX2 OX9
interrupt and control for a variety of peripheral functions, such as UARTs,
OX3 OX8
FIFOs, Keyboards, etc. Data transfers between the HM-6100 CMOS OX4 OX7
Microprocessor and the HD-6101 are via Input-Output Transfer (lOT) OX5 OX6
instructions, control lines and DX bus.

Data transfers between peripheral devices and the DX bus are controlled
by the PIE via 2 read, 2 write, 4 sense and 4 flag functions. Internal
pi E registers are programmed under software control for write polarities,
sense levels or edges, flag values and interrupt enables. Another software
controlled register stores the address for vectored interrupt operation.

lXMAR
SENSE ')
lrrVm SENSE 2 4 seNSE INPUTS
XTC SENSE 3

I
SENSE 4

FLAG 1
FLAG 2 4 PROGRAMMABLE
FLAG 3 OUTPUTS
FLAG 4

SEL 3

j SEl4

I
PBIORITY SELECTION
UP TO 31 PIE SEt 5 TOANO FROM
ADDRESSES OTHER PIE'S
SEl6 CONTROL FOR TWO
SEL 7 12-81T INPUT PORTS

CONTROL FOR TWO

INTGNT } 12-81T OUTPUT PORTS
Il'/TISl(J
C1
e2
 Supply Voltage (VCC - GND) -O.3V to +8.0V
Input or Output Voltage Applied (GND - O.3V) to (VCC + O.3V)
Storage Temperature Range -650C to +1500C
Operating Temperature Range
Industrial HD-6101-9 -400C to +850C
Military HD-6101-2 -550C to +1250C

SYMBOL PARAMETER MINIMUM TYPICAL MAXIMUM UNITS TEST CONDITIONS

VIH Logical "1" I nput Voltage 70% VCC V

VIL Logical "0" Input Voltage 20% VCC V

IlL Input Leakage -1.0 +1.0 J.lA OV ~ VIN '" VCC

VOH Logical "1" Output Voltage(t) 2.4 V 10H = -o.2mA

VOL Logical "0" Output Voltage 0.45 V 10L = 2.0mA
10 Output Leakage -1.0 +1.0 J.lA OV ~ Vo ~ VCC

ICC Supply Current (Static) 1.0 100 J.lA VIN = Vcc. Freq. =0
CI Input Capacitance(2) 5 7 pF

Co Output Capacitance(2) 8 10 pF

CIO Input/Output Capacitance(2) 8 10 pF

TA= TA=
TA = 25°C INDUSTRIAL MILITARY
VCC = 5.0V(1) VCC = 5V t10% VCC ~ 5Vt10%

SYMBOL PARAMETER MIN MAX MIN MAX MIN MAX UNITS TEST CONDITIONS

tDR Delay: DEVSEL to READ 200 300 330 ns CL = 50pF

tDW Delay: DEVSEL to WRITE 100 220 140 300 150 330 ns See Timing
tDF Delay: DEVSEL to FLAG 200 375 415 ns Diagram
tDC Delay: DEVSEL to Ci. C2 160 460 510 ns

tDI Delay: DEVSEL to SKP/INT 210 460 510 ns

tDA Delay: DEVSEL to DX 350 460 510 ns

tLX LXMAR Pulse Width 200 240 265 ns

tAS Address Set-Up Time 60 80 90 ns

tAH Address Hold Time 100 125 140 ns

tDS Data Set-Up Time 50 80 80 ns

tDH Data Hold Time 100 100 110 ns

 Supply Voltage (VCC - GND) -O.3V to +8.0V
Input or Output Voltage Applied (GND - O.3Vl to (VCC +O.3V)

Storage Temperature Range -650C to +1500C

Operating Temperature Range
Industrial HD-6101C-9

SYMBOL PARAMETER MINIMUM TYPICAL MAXIMUM UNITS TEST CONDITIONS

VIH Logical "1" Input Voltage 70% VCC V

VIL Logical "0" Input Voltage .8 V

IlL Input Leakage -10 +10 /lA OV ~ VIN ~ VCC

VOH Logical "1" Output Voltage(1) 2.4 V 10H = -o.2mA

VOL Logical "0" Output Voltage 0.45 V 10L = 1.6mA

10 Output Leakage -10 +10 /lA OV~ Vo ~ VCC

ICC Supply Current (Static) 1.0 800 /lA VIN = VCC. Freq. = 0
CI I nput Capacitance (2) 5 7 pF

Co Output Capacitance (2) 8 10 pF

CIO Input/Output Capacitance(2) 8 10 pF

TA=
TA = 250C INDUSTRIAL
VCC = 5.0V(1) VCC =5V±5%

SYMBOL PARAMETER MIN MAX MIN MAX UNITS TEST CONDITIONS

tDR Delay: DEVSEL to READ 230 375 ns CL = 50pF

tDW Delay: DEVm to WRITE 100 240 125 375 ns See Timing
tDF Delay: DEVSEL to FLAG 230 475 ns Diagram

tDC Delay: DEVSEL to C1. C2 190 560 ns

tDI Delay: DEVSEL to SKP/M 250 560 ns

tDA Delay: 5EVSIT to DX 400 560 ns

tLX LXMAR Pulse Width 230 300 ns

tAS Address Set-Up Time 80 100 ns

tAH Address Hold Time 120 150 ns

tDS Data Set-Up Time 60 90 ns

tDH Data Hold Time 120 150 ns

Timing for a typical transfer is shown below. During an on the DX lines, or control outputs RE"A'D'i and ~
instruction fetch the processor places the contents of the are generated to gate peripheral data to the DX lines. A
PC on the bus <D and obtains from memory an lOT in- low going pulse on DEVSEL while XTC is low ® is used
struction of the form 6XXX ®. During IOTA of the to generate WR ITE 1 and WR ITE 2 controls. These signals
execute phase the processor places that instruction back on are used to latch accumulator data into peripheral devices.
the DX lines @ and pulses LXMAR transferring address
and control information for the lOT transfer to all periph- All PIE timing is generated from HM-6100 signals LXMAR,
eral devices. A low going pulse on DEVSEL while XTC is DEVSEL, and XTC. No additional timing signals, clocks,
high @ is used by the addressed PI E along with the decod- or one shots are required.
ed control information to generate CPU control signals
C1, C2, and SKP. Also at this time either the Control Propagation delays, pulse width, data setup and hold times
Register A or the Interrupt Vector Register are outputed are specified for direct interfacing with the HM-6100.

lOT INSTRUCTION •
f:=FETCH ·1- IOTA ..I- IOTB ..
STATE TIMES

XTC

LXMAR

CPU MEMSEL

DEVSEL

OX (0-11)

READ

Ci,C2

PIE SKP!INT

FLAG (1 OR 3)

WRITE

FLAG (1-4) VIAWCRA

OX data, ~,Ef, C2, and SKP

are read by the HM-6100 on
the rising edge of T3.
The HM-6100 communicates with the PI E and with per- The 5 address bits (3-7) are compared with the pin pro-
ipherals through the PIE via lOT commands. During the grammable select inputs SEL3, SEL4, SEL5, SEL6, SEL7
IOTA cycle an instruction of the form 6XXX is loaded to address 1 of 31 possible PIEs. Address zero is reserved
into all PIE instruction registers. The bits are interpreted for lOT's internal to the HM-6100. The four control
as shown below. bits are decoded by the PIE to select one of 16 instructions
which are described below.

PIE INSTRUCTION FORMAT

3 4 5 6 7 8 9 10 11

CONTROL MNEMONICS

0000 READ1 The READ instructions generate a pulse on the appropriate read outputs. This signal is used by
1000 READ2 the peripheral device to gate onto the OX bus to be "OR'ed" with the HM-6100 accumulator data.
The HM-6100 accumulator is cleared prior to reading peripheral data when CO is asserted low.

0001 WRITE1 The WRITE instructions generate a pulse on the appropriate write output. This signal is used by
1001 WRITE2 peripherals to load the HM-6100 accumulator data on the OX lines into peripheral data registers.
The HM-6100 AC is cleared after the write operation when the CO input is asserted low.

0010 SKIP1 The SKIP instructions test the state of the sense flip flops. If the input conditions have set the
0011 SKIP2 sense flip flop, the PIE will assert the SKP/INT output causing the HM-6100 to skip the next
1010 SKIP3 program instruction. The sense flip flop is then cleared. If the sense flip flop is not set, the PIE
1011 SKIP4 not assert the SKP/INT output and the HM-61 00 will execute the next instruction.

0100 RCRA

0101 WCRA
1101 WCRB
1100 WVR

0110 SFLAG1
1110 SFLAG3

0111 CFLAG1
1111 CFLAG3

(600718 CAF

FLAGs (1-4) - The FLAGs are general purpose outputs the WCRA commands. In addition, FLAG1 and FLAG3
that can be set and cleared under program control. can be set and cleared directly by the commands SFLAG1,
GLAG1 follows bit FL1 in Control Register A and etc. CFLAG1, SFLAG3 and CFLAG3.
FLAGs can be changed by loading new data into CRA via
The sense inputs are used to set sense flip flops (SENSE FF) The SENSE FF's are sampled when LXMAR is high.
inside the PIE. For each sense input there are two FF's, Interrupt requests are generated only when the sense flip
one for skip and one for interrupt. Conditions for setting flops are set by an edge and interrupts are enabled by
each SENSE FF, levels or edges and positive or negative writing to control reg A. Sense flip flops are reset on the
polarities, are set by control bits SL and SP in CRB. following conditions.

SENSE FLIP FLOPS

CONDITION SKIP FF INTERRUPT FF

CAF Instruction 160078) Clears All Clears All

SKIP Instruction Clears Corresponding FF Clears Corresponding FF

Vectored Interrupt Not Cleared Clears Highest Priority FF

on Selected PIE After
Vectoring

Interrupt Disabled liE = "0") Not Cleared Disables Interrupt by Holding

Corresponding FF in Reset
State

READ 11-2) - The READ outputs are activated by the struction, is specified by the PI E's assertion of the C1 and
read instructions and are used by peripheral devices to get C2 control lines as shown below.
data onto the DX lines for transfer to the HM-6100.
Read lines are active low. Interrupt and skip information are time multiplexed on the
same line (SKP!INT). Since the HM-6100 samples skip
WRITE (1-2) - The WRITE outputs are activated by the and interrupt data at separate times there is no degradation
write instructions and are used by peripheral devices to load in system performance. The PIE samples the sense flip
HM-6100 AC data from the DX lines into peripheral flops and generates an interrupt request for enabled bits
data registers. Output polarity is controlled by the WR ITE (IE1-4) when LXMAR is high. Interrupt requests are
POLARITY bits of CRA. A logic one causes pulses to be asserted by the PIE driving the INT/SKP line low. During
positive while a logic zero causes pulses to be negative. IOTA of SKIP instructions the INT/SKP reflects the
SENSE FF data when DEVSEL is low and XTC is high.
I/O CONTROL LINES' - There are three I/O control If the SENSE flip flop is set, the INT/SKP line is driven low
lines from the PI E to the microprocessor - C1, C2, and to cause the HM-6100 to skip the next instruction. A!!
INT/SKP. The type of data transfer, during an lOT in- these outputs are open drain.

CONTROL LINES

SKP CO- C1 ~ OPERATION DESCRIPTION

H H H H PIE_ AC The contents of the AC is sent

to the PIE.

H H L H AC_ ACVPIE Data is received from the PIE,

OR'ed with the data In the AC
and the result stored in the AC.

H H L L PC -- Vector Address Vector address received from

PI E and loaded into PC. This is
referred to as an absolute jump.

L H H H PC -PC+l Forces Microprocessor to skip

next sequential instruction.
The CRA can be read and written by the HM-6100 via the IE (1-4) - A high level on INTERRUPT ENABLE enables
RCRA and WCRA commands. interrupts for the SENSE inputs.

Otherwise these inputs provide conditional skip testing as

defined by the SKIPl-4 instructions.
Fl (1-4) - Data on FLAG outputs corresponds to data
in FL (1-4). Changing the Fl bits under software control WP (1-2) - A high level on WRITE POLARITY bits causes
changes the corresponding FLAG outputs. positive pulses at the WRITE outputs.

The CRB can be written by the HM-6100 via the WCRB up to be edge sensitive and interrupts are enabled via
instruction. It has no read back capability. The format and the IE bits of CRA.
meaning of control bits are shown.
SP (1-4) - A high level on the SENSE POLARITY bits
SL (1-4) - A high level on the SENSE LEVEL bits causes causes the flip flop to be set by high level or positive
the SENSE inputs to be level sensitive. A low level in the going edge. A low level causes the flip flop to be set by a
SL bits causes the SENSE inputs to be edge sensitive. low level or negative going edge.
An interrupt request is generated only if a sense line is set

A hardware priority network uniquely selects a PI E to the chain. Within the PIE, SENSE1 has the highest priority
provide a vectored address. The first lOT command of any and SENSE 4 has the lowest. The vector address generated
type, after the HM-6100 signal INTERRUPT GRANT by the PIE consists of 10 bits from the vector register and
goes high, resets the INTGNT line to a low level. The two bits that indicate the sense input within the highest
INTGNT signal is used to freeze the priority network and priority PIE that generated the interrupt. If PIN is tied to
enable vector generation. The highest priority PIE has GND, then the PIE will respond as a non-vectored inter-
PIN tied to VCC. The lowest priority PIE is the last one on rupt device.

VPRI CONDITIONS
00 SENSE 1
01 SENSE 2
10 SENSE 3
11 SENSE 4
 ACTIVE ACTIVE
PIN SYMBOL DESCRIPTION PIN SYMBOL DESCRIPTION
LEVEL LEVEL
1 VCC Positive voltage 8 SEL 3 TRUE Matching SELECTI3·7) inputs with PIE
2 INTGNT H A high level on INTERRUPT GRANT addressing on DX(3-7) during IOTA selects a
inhibits recognition of new interrupt requests PI E for programmed input output transfers.
and allollYSthe priority chain time to 9 SEL 4 TRUE See Pin 8 .- SEL 3
uniquely specify a PIE. 10 LXMAR H A positive pulse on LOAD EXTERNAL
3 PRIN H A high level ON PRIORITY IN and an ADDRESS REGiSTER loads address and
interrupt request will select a PIE for control data from OX 13-11) into the address
vectored interrupt. register.
4 SENSE 4 PROG The SENSE input is controlled by the SL 11 SEL 5 TRUE See Pin 8 - SEL 3
(sense level) and SP (sense polarity) bits of 12 SEL 6 TRUE See Pin 8 - SeL 3
control register B. A high SL level will cause 13 XTC H The XTC input is a timing signal produced by
the sense flip flop to be set by a level while a , the microprocessor. When XTC is high a low
low SL level causes then sense flip flop to be going pulse on OEVSEL initiates a "read"
set by an edge. A high SP level will cause the operation. lNhen XTC is low, a low going pulse
sense flip flop to be set by a positive going on ~ initiates a write operation.
edge or high level. A high It: (interrupt
14 SEL 7 TRUE See Pin 8 - SEL 3
enablellevel generates an interrupt request
whenever the sense flip flop is set by an edge. 15 OX 0 TRUE Data transfers between the microprocessor and
5 SENSE 3 PROG See pin 4 - SENSE 4 PI E take place via these input/output pins.
6 SENSE 2 PROG See pin 4 - SENSE 4 16 OX 1 TRUE See Pin 15 - OX 0
7 SENSE 1 PROG See pin 4 - SENSE 4 17 OX 2 TRUE See Pin 15 - OX 0
18 OX 3 TRUE See Pin 15 - OX 0
19 OX 4 TRUE See Pin 15 - OX 0
20 OX 5 TRUE See Pin 15 - OX 0

ACTIVE ACTIVE
PIN SYMBOL DESCRIPTION PIN SYMBOL LEVEL DESCRIPTION
LEVEL
21 OX6 TRUE SeePin15-0XO 34 C2 L See Pin 33 - Ci
22 OX 7 TRUE See Pin 15 - OX 0
23 OX 8 TRUE See Pin 15 - OX 0 35 i'iEADi PROG Outputs REA01 and REA02 are used to gate
24 OX9 TRUE See Pin 15 - OX 0 data from peripheral devices onto the OX bus
25 OX 10 TRUE See Pin 15 - OX 0 for input to the HM-6100 Note the data
26 OX 11 TRUE See Pin 15 - OX 0 does not pass through the PI E.
27 GNO
28 im7SIT L The OEVSEL input is a timing signal 36 WRITE1 PROG Outputs WRITE1 and WRITE2 are used to
produced by the microprocessor during lOT gate data from the HM-6100 OX bus into
instructions. It is used by the PI E to generate peripheral devices. Data does not pass
timing for controlling PIE registers through the PI E.
and "read" and "V\lrite" operations.
37 REA02 PROG See Pin 35 - R"'E"ADi
29 FLAG 4 PROG The FLAG outputs reflect the data stored in
control register A. Flags (1-41 can be set or
38 WRITE2 PROG See Pin 36 -- WRITE1
reset by changing data in CRA via a WRA
lwrite control register Al command. FLAG 1 39 SKPIINT L The PIE asserts this line low to generate
and FLAG3 can be controlled directly by interrupt requests and to signal the HM-61 00
PIE commands SFLAG1, CFLAG1, when sense flip flops are set during SKIP
SFLAG3 and CFLAG3. instructions. This output is open drain.
30 FLAG 3 PROG See Pin 29 - FLAG 4
31 FLAG 2 PROG See Pin 29 - FLAG 4 40 POUT H A high level on priority out indicates no
32 FLAG 1 PROG See Pin 29 - FLAG 4 higher priority PIE interrupt requests are
33 C1 L The PI E decodes address. control and priority outstanding. This output is tied to the PIN
information and asserts outputs C"i and C2 input of the next lower priority
during the IOTA cycle to control the tYpe of pie in the chain.
data transfer. These outputs are open drain
for bussing and require a pullup register
to~CC' _
C1tU, C2tLl - vectored interrupt
aiLI. C2IH)· READ1. REA020r
RRA commands
Ci (HI, C2IH) - all other instructions
;II HARRIS HD-6431
CMOS HEX
LATCHING BUS DRIVER

• SINGLE POWER SUPPLY

L VCC
• HIGH NOISE IMMUNITY

• INOUSTRIAL AND MILITARY GRADES

'A E
DRIVE CAPACITY 300pF 'Y 6A

SOURCE CURRENT 4mA

2A 6y
SINK CURRENT 6mA
2y SA
PROPAGATION DELAY 7SnoecMAX.

3A Sy

4A

4y

Truth Tabls
CONTROL DATA PORT
INPUTS STATUS
The HD-6431 is a self-aligned silicon gate CMOS Latching Three-State
Bus Driver. This circuit consists of 6 non-inverting latching drivers with E L A Y

separate input and output. A high on the strobe line L allows data to go
H L X HI-Z'
through the latches and a transition to low latches the data. A high on
the Three-State control E forces the buffers to the high impedance mode
H
L
H
I
X
X .
HI-Z

without disturbing the latchild data. New data may be latched in while L H L L
L H H H
the buffers are in the high impedance mode.
• Oat8 is latched to the value
of the lest input
X =
Don't Cere
H I-Z = High Impedance
~ = Transition from High to
Low level

(2) (7)
1A 3y
 Supply Voltage +8.0V
Input or Output Voltage Appl ied GND -O.3V to VCC +O.3V
Storage Temperature Range -650C to +1500C
Operating Temperature Range
Industrial HD-6431-9 -400C to +850C
Military HD-6431-2/8 -550C to +1250C
Operating Voltage Range +4 to +7V

SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS

VIH Logical "'" Input Voltage 70% VCC V

VIL Logical "0" Input Voltage 20% VCC V

IlL I nput Leakage -1.0 1.0 J..lA OV~VIN~VCC

VOH Logical "1" Output Voltage VCC -0.4 V 10H = -4.0mA.
E= Low

VOL Logical "a" Output Voltage 0.4 V 10L =6.0mA

E= Low

10 Output Leakage -1.0 1.0 f..LA OV~VO~VCC.

E = High
ICC Supply Current 10 f..LA VIN = VCC or GNO.
VCC = 5.5V
CIN Input Capacitance- 5 pF VIN = OV; TA = 25°C;
f = lMHz

Co Output Capacitance· 15 pF VIN = OV; TA = 25°C;

f = lMHz

Vcc= 5.0V <D VCC = 5.0V ± 10%

25°C TA = Indus. or Mil.

SYMBOL PARAMETER MIN MAX MIN MAX UNITS

tpo Propagation Delay 65 75 ns

tEN Enable Time 80 90 ns

tOIS Disable Time 80 90 ns

tSET I nput Setup Time 15 15 ns

tHOLO Input Hold Time 15 15 ns
tpw Pulse Width 25 30 ns
tR Output Rise Time 80 90 ns
tF Output Fall Time 70 80 ns

NOTE <D All devices guaranteed at worst case limits. Room temperature,
5V data provided for information-not guaranteed.
 _____ 5_0%+===.PW --XO% _
==================:~;ET -+'HOlOX_~ -_-_-_
~ 'PO K=
10%

"1=.OIS,__---
10%

The transient current required to charge the load capacitance is given by IT = C dv. Assuming that all outputs may
dt

change state at the same time and that dv is constant; IT = (1: CL) (VCC x 80%) ego [tR = 80ns. VCC = 5.0V, each
dt \ tR or tF
CL = 300pF, IT = (4) (300 x 10-12\ 5.0 x 0.8 - 90mAJ This current spike may cause a large negative voltage
J 80 x 10-9
spike on VCC, which if it becomes a diode drop less than any input, may cause the device to latch up. It is recom-
mended that a 0.1 J.l.F ceramic disk decoupling capacitor be placed between VCC and GNO at each device to filter
out this noise.

1.8
1.24 1.8
1.18 1.4
1.08 1.2

~1.00 ~,.o
tPD (JOOpF) 0,92 1R. 1F (3OOpFI 0.8

0.&0 0.6
0.76 0.4
0.68 0.2

o 50 100 200 300 400 500 o 50 100 200 300 400 500
CllpFI CllpFI
FIGURE 1 FIGURE 2

The above example will illustrate the calculation of a more fore 75 x 0.84 or 63nsec. To obtain the rise and fall times
useful propagation delay. The system on this example uses check the A.C. specs for the rise and fall times at 4.5V and
a 5 volt supply with a tolerance of ± 10%, an ambient tem- 1250C to obtain a worst case rise time of 90nsec. Use
perature of as high as 1250C, and a calculated load capaci- Figure 2 to find it's degradation multiple to be 0.65. The
tance of 150pF. This application requires the H0-6431-2. adjusted rise time is, therefore, 90 x 0.65 or 58nsec. To
The table of A.C. specs shows the tpo at 4.5V· and 1250C obtain the standard 50% to 50% propagation delay. add the
is 75nsec. Use the graph in Figure 1 to get the degradation adjusted propagation delay to half of the adjusted rise time
multiple for 150pF. The number shown is 0.84. The ad- to get a propagation delay of 92nsec. The rise time was
justed propagation del~y, to the 10% or 90% point, is there- used here because it is always the worst case.
m HARRIS
CMOS HEX BI-DIRECTIONAL
HD-6432
BUS DRIVER

• SINGLE POWER SUPPLY 1A

• HIGH NOISE IMMUNITY 18

• INDUSTRIAL AND MILITARY GRADES 2A

• DRIVE CAPACITY
28
• SOURCE CURRENT
3A

• SINK CURRENT 6mA

3B
• PROPAGATION DELAY 55"_ MAX.
~BA

EBA

GND

CONTROL DATA PORT

The HD-6432 is a self-aligned silicon gate CMOS bi-directional bus driver. INPUTS STATUS
This circuit consists of 12 drivers organized as 6 bi-directional pairs. EAB EA8 EBA E8A A 8

Four enable lines select drive direction or Three-State mode. L X H L 0 I

X H H L 0 I
H L X H I 0
H L L X I 0
L X L X ISOLATED
X H X H ISOLATED
L X X H ISOLATED
X H L X ISOLATED
H L H L NOT
ALLOWED

(8)
EBA
 Supply Voltage +8.0V
Input or Output Voltage Applied GND -O.3V to VCC +O.3V
Storage Temperature Range -650C to +1500C
Operating Temperature Range
Industrial HD-6432-9 -400C to +850C
Military HD-6432-2/8 -550C to +1250C
Operating Voltage Range +4 to +7V

SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS

V,H Logical "1" Input Voltage 70% VCC V

VIL Logical "0" Input Voltage 20% VCC V

IlL Input Leakage -1.0 1.0 IJ.A OV~VIN~VCC

VOH Logical "1" Output Voltage VCC -0.4 V 'OH = -4.0mA
VOL Logical "0" Output Voltage 0.4 V 10L = 6.0mA
10 Output Lea kage -1.0 1.0 IJ.A OV~VO~VCC.
EAB ~ EBA = Low
ICC Supply Current 10 IJ.A VIN = VCC or GND.
VCC = 5.5V
C,N Input Capacitance· 5 pF VIN = OV; TA = 25°C;
f = lMHz

CliO 110 Capacitance* 20 pF VIN = OV; TA = 25°C;

f = lMHz

Vcc = 5.0V
25°C
G)II Vcc
TA =
= 5.0V ± 10%
Indus. or Mil.

SYMBOL PARAMETER MIN MAX MIN MAX UNITS

tpD Propagation Delay 45 55 ns

tEN Enable Time 65 75 ns
tDIS Disable Time 100 110 ns
tR Output Rise Time 100 110 ns
tF Output Fall Time 70 80 ns

NOTE <D; All devices guaranteed at worst case limits. Room temperature,
SV data provided for information-not guaranteed.
 A
I(
EBA EAB

EBA EAB 60%

A.Bor
T~F

dv
The Transient current required to charge the load capacitance is given by IT = C . Assuming that all outputs may
dt

change state at the same time and that ~ is constant; IT =IXCL) (VCC x 80%\ ego [tR = lOOns VCC = 5.0V each
dt ~ tR or tF -;
12 5.0 x 0.8 ]
CL = 300pF IT = (6) (300 x 10- ) 9 - 72mA. This current spike may cause a large negative voltage
100 x 10-

spike on VCC, which if it becomes a diode drop less than any input, may cause the device to latch up. It is recom-
mended that a 0.1 II F ceramic disk decoupling capacitor be placed between VCC and GND at each device to filter
out this noise.

1.8
1.24 1.1
1.16 1.'
1.08 1.2

A/;-Y~6O%-IPO
90% JO"
-tp:1~ ~.
~,.oo
tpo 1300pF) 0.92
0.&0
~1.0
IA.tF I~F) 0.'
0.'
B/A 90% 0.18 0.'
tF tR 0.88 0.2

o 60 100 200 300 400 600 o 60,00 200 300 400 &00
CllpF) CllpF)
FIGURE 1 FIGURE 2

The above example will illustrate the calculation of a more fore 55 x 0.84 or 46nsec. To obtain the rise and fall times
useful propagation delay. The system on this example uses check the A.C. specs for the rise and fall times at 4.5V and
a 5 volt supply with a tolerance of ± 10%, an ambient tem- 1250C to obtain a worst case rise time of 110nsec. Use
perature of as high as 1250C, and a calculated load capaci- Figure 2 to find it's degradation multiple to be 0.65. The
tance of 150pF. This application requires the HD-6432-2. adjusted rise time is, therefore, 110 x 0.65 or 72nsec. To
The table of A.C. specs shows the tPD at 4.5V and 1250C obtain the standard 50% to 50% propagation delay, add the
is 55nsec. Use the graph in Figure 1 to get the degradation adjusted propagation delay to half of the adjusted rise time
multiple for 150pF. The number shown is 0.84. The ad- to get a propagation delay of 82nsec. The rise time was
justed propagation delay, to the 10% or 90% point, is there- used here because it is always the worst case.
m HAR~IS
CMOS
HD-6433
QUAD BUS
SEPARATOR/DRIVER

• SINGLE POWER SUPPLY

• HIGH NOISE IMMUNITY

• INOUSTRIAL AND MILITARY GRADES

• DRIVE CAPACITY 300pF

• SOURCE CURRENT 4mA

• SINK CURRENT 6mA

• PROPAGATION DEI.AY 60nlOe MAX,

The HD-6433 is a self-aligned silicon gate CMOS bus separator/driver.

CONTROL
This circuit consists of 8 drivers organized as 4 pairs of bus separators
INPUTS FUNCTION
which allow a unidirectional input bus and a unidirectional output bus to
be interfaced with a bi-directional bus. EA E8 A 8 Y

L L I a a
L H I D a
H L D a I
H H ISOLATED

I = I nput, a = Output,
o= Disconnected

4y 4A 48 3y 3A 38
(15) (14) (13) (121 (11) (10)

(2) (31 (4) (61 (6)

1A 18 2y 2A 28
 Supply Voltage +8.0V
Input or Output Voltage Applied GND -O.3V to VCC +O.3V
Storage Temperature Range -650C to +1500C
Operating Temperature Range
Industrial HD-6433-9 -400C to +850C
Military HD-6433-2/8 -550C to +1250C
Operating Voltage Range +4 to +7V

SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS

VIH Logical "1" Input Voltage 70% VCC V

VIL Logical "0" Input Voltage 20% VCC V

IlL Input Leakage -1.0 1.0 P.A OV~VIN~VCC

VOH Logical "," Output Voltage VCC -0.4 V 10H = -4.0mA
VOL Logical "0" Output Voltage 0.4 V 10L = 6.0mA
10 Output Leakage -1.0 1.0 P.A OV~VO~VCC
EA = EB = High
ICC Supplv Current 10 P.A VIN = VCC or GNO.
VCC = 5.5V
CIN Input Capacitance* 5 pF VIN = OV; TA = 25°C;
f = lMHz

CliO I/O Capacitance'" 20 pF VIN = OV; TA = 25°C;

f = lMHz
Co Output Capacitance tI 15 pF VIN = OV; TA = 25°C;
f = lMHz

VCC =5.0V CD VCC=5.0V±10%

25°C TA = Indust. or Mil.

SYMBOL PARAMETER MIN MAX MIN MAX UNITS

tpo Propagation Delay 40 50 ns

tEN Enable Time 60 70 ns
tOIS Disable Time 90 100 ns
tR Output Rise Time 85 95 ns
tF Output Fall Time 70 80 ns

NOTE <D All devices guaranteed at worst case limits. Room temperature,
5V data provided for information-not guaranteed.
 A ~_50%_-tP-O~------

aA 50%~t~~tOI8:J.8O%

Y -------- 40% 1~ --fi"o;r

,*,,, vcc

VAT
T 300pP

OUTPUT TEST CIRCUIT

FOR THREE-8TATE DELAYS

The trensient current required to cherge the loed cepecitence Is given by IT a C~. Assuming thet ell outputs mey
dt
chenge state et the seme time end thet ~ Is constant; IT· (J:, CL) (VCC x 80%) eg, [tR • 85ns, VCC· 5.0V, eech
dt tR or tF
CL· 300pF, IT· (4) ( 300 x 10-12\ ~. 56.5mA.1 This current spike mey ceuse e lerge negetlve voltage
!85 x 10-9
spike on VCC, which if it becomes a diode drop less then eny input, mey cause the device to latch up. It is recom-
mended that a 0.1 IlF ceramic disk decoupling capacitor be placed between VCC and GND at each device to filter
out this noise.

1,1'
1.24 1.1
1.11 1.4
1.01 1.2

;;-Y~IOlI'----tPO

Y/8 1& JO!\

-~:1~ ~ 80%
~1.00
'PO 1300pFI0.12
0.14
~1.0
tA.tp (IOOpPI0,1
0,1
0.71 0.4
tF tR 0.11 0,2

o 150100 200 300 400 IlOO o 150100 200 300 400 IlOO
CLlpFI CLlpFI
PIOUAE1 PIOUAE2

The above example will Illustrate the calculation of a more fore 50 x 0.84 or 42nsec. To obtain the rise and fall times
useful propagation delay. The system on this example uses check the A.C. specs for the rise and fall times at 4.5V and
a 5 volt supply with a tolerance of ± 10%, an ambient tem- 1250C to obtain a worst case rise time of 95nsec. Use
perature of as high as 1250C, and a calculated load capaci- Figure 2 to find it's degradation multiple to be 0.65. The
tance of 150pF. This application requires the HD-6433-2. adjusted rise time is, therefore, 95 x 0.65 or 62nsec, To
The table of A.C, specs shows the tPD at 4,5V and 1250C obtain the standard 50% to 50% propagation delay, add the
is 50nsec, Use the graph in Figure 1 to get the degradation adjusted propagation delay to half of the adjusted rise time
multiple for 150pF. The number shown is 0.84. The ad- to get a propagation delay of 73nsec. The rise time was
justed propagation delay. to the 10% or 90% point, isthere- used here because it is always the worst case.
m HARRIS
CMOS OCTAL RESETTABLE
HD-6434
LATCHED BUS DRIVER

Pinout
TOPVIEW

• SINGLE POWER SUPPLY 4y VCC

• HIGH NOISE IMMUNITY 3y Sy

2y 6y
• INDUSTRIAL AND MILITARY GRADES
1y 7y
• DRIVE CAPACITY 1A Sy
2A SA
• SOURCE CURRENT
3A 7A
• SINK CURRENT
4A 6A
• PROPAGATION DELAY A1 SA
R2 L2
E1 L1
GND E2

The HD-6434 is a self-aligned silicon gate CMOS latching Three State Truth Table
bus driver. This circuit consists of 8 non-inverting latching drivers with
CONTROL INPUTS DATA
separate input and output. A Iowan both strobe lines (ll allows data
R, R2 E, '2 L, L2 A Y
to go through the latches and a transition to high latches the data. A X X H X X X X Hi-Z

high on either Three State control (E) forces the buffers to the high X X X H X X X Hi-Z

impedance mode without disturbing the latched data. A Iowan either L X L L X X X L

reset line unforces each of the latches to a low level. New data may be
X L L L X X X L

..
H H L L L L L L

latched in while the buffers are in the high impedance mode. H H L L L L H H

H
H

H
L

L
L

L
t
L
,
L X

x • Don'1 Car. Hi-Z. High Imped.nce L - Low

H - High *. oltl ,slatched to the value of the last input
t a Transition from a Low to High level
 Supply Voltage +8.0V
Input or Output Voltage Applied GND -O.3V to VCC +O.3V
Storage Temperature Range -650C to +1500C
Operating Temperature Range
Industrial HD-6434-9 -400C to +850C
Military HD-6434-2/8 -550C to +1250C
Operating Voltage Range +4V to +7V

SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS

VIH Logical "1" Input Voltage 70% VCC V

VIL Logical "0" Input Voltage 20% VCC V

IlL Input Leakage -1.0 1.0 J.lA OV~VIN~VCC

VOH Logical "1" Output Voltage VCC -0.4 V 10H = ~.OmA.

E1 = E2 = Low

VOL Logical "0" Output Voltage 0.4 V 10L = 9.0mA

E1 = E2 = Low

10 Output Leakage -10 10 J.lA OV~VO~VCC.

E1 = E2 = High

ICC Supply Current 10 J.lA VIN = VCC or GND.

VCC = 5.5V

CIN I nput Capacitance * 5 pF VIN = OV; TA = 25°C;

f = 1MHz

Co Output Capacitance* 15 pF VIN = OV;TA = 25°C;

f = 1MHz

VCC =5.0V VCC :l:5.0V :1:10%

TEMP = 250C TEMP = IND OR MIL
CL = 50pF <D CL = 300pF

SYMBOL PARAMETER TYP MIN MAX UNITS

tPD Propagation Delay 40 50 ns

tEN Enable Time 45 50 ns

tDIS Disable Time 45 50 ns

tSET Input Setup Time 25 35 ns

tHOLD I nput Hold Time 40 45 ns

tPW Pulse Width 45 65 ns

tR Output Rise Time 45 50 ns

tF Output Fall Time 30 50 ns

tRESET Reset Delay Time 75 125 ns

 r 60,,"'1<' PW----..,r50,,"
:::::::::::::::_-::_-::.
...
-~-5:
1: OK=:
t

-l-tHOL:X_~_O%
tpo
_

10%

50%~ tOIS =180%_---

10%

DECOUPLING CAPACITORS
The instantaneous current required to switch a large capacitance load may cause a voltage
spike on VCC. which if it becomes a diode drop less than any input. may cause the device
to latch up. It is recommended that a O.lJ.lF ceramic disk decoupling capacitor be placed
between VCC and GND at each device to filter out this noise.

1.8
1.24 1.8
1.18 1.4
1.08 1.2
~1.00 tR.tF 1.0
tpo (30OpFI 0.92 tR. tF (3OOpF) 0.8
0.84 0.8
0.78 0.4
o.ee 0.2

o 50 100 200 300 400 600 o 60 100 200 300 400 600
CL(pFI Cl(pF)
FIGURE 1 FIGURE 2
m HARRIS
CMOS OCTAL BUS
HD-6436

BUFFER/DRIVER

4y
• SINGLE POWER SUPPLY
3y
• HIGH NOISE IMMUNITY 2y
• INDUSTRIAL AND MILITARY GRADES ly

• DRIVE CAPACITY 300pF lA

2A
• SOURCE CURRENT 6mA
3A
• SINK CURRENT
4A
• PROPAGATION DELAY
El
GND

CONTROL
The HD-6436 is a self-aligned silicon gate CMOS Three State buffer INPUTS INPUT OUTPUT
driver. The circuit consists of 8 non inverting buffers with separate
El E2 A Y
inputs and outputs which permit this driver to be used for bi-directional
or uni-directional busing. A high on either Three State control line E1 L L L L

or E2 will force the drivers to the high impedance mode. L L H H

L H X Hi-Z
H L X Hi-Z
H H X Hi-Z

L =Low, H = High
X= Don't Care
Hi-Z = High Impedance

BA By 7A 7y 6A 6y 5A 5y
(15) (16) (14) (17) (13) (lB) (12) (19)

(4) (1)
ly 4y
 Supply Voltage +8.0V

Input or Output Voltage Applied GNO -0.3V to VCC +O.3V

Storage Temperature Range -650C to +15QOC

Operating Temperature Range

Industrial H 0-6436-9 -400C to +850C

Military HO-6436-2/8 -550C to + 1250C

Operating Voltage Range +4V to +7V

ELECTRICAL CHARACTERISTICS
VCC = 5.0V ± 10%; T A = Industrial or Military

SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS

VIH Logical "1" Input Voltage 70% VCC V

VIL Logical "0" Input Voltage 20%VCC V

IlL I nput Leakage -1.0 1.0 !J.A OVSVINSVCC

VOH Logical "1" Output Voltage VCC -0.4 V IOH ~ -6.0mA.

E1 - E2 - Low

VOL Logical "0" Output Voltage 0.4 V 10L -g.OmA

E1 • E2 - Low

10 Output Leakage -10 10 !J.A OVSVoSVCC.

E1 = E2 = High

ICC Supply Current 10 !J.A VIN - VCC or GNo.

VCC - 5.5V

CIN Input Capacitance· 5 pF VIN-OV;TA-250C;

f·1MHz

Co Output Capacitance* 15 pF VIN = OV; TA· 250C;

f = 1MHz

VCC-5.0V VCC • 5.0V ±10%

TEMP-25OC TEMP - IND OR MIL
CL - 50pF <D CL·300pF

SYMBOL PARAMETER TYP MAX UNITS

tPo Propagation Delay 35 55 ns

tEN Enable Time 50 65 ns

tolS Disable Time 50 55 ns

tR Output Rise Time 30 55 ns

tF Output Fall Time 25 55 ns

 -----_50% 50% ---------

~'EN~60% L'DlS -=i ~O%

40% ~

r 50PF

The instantaneous current required to switch a large capacitance load may cause a voltage
spike on VCC. which if it becomes a diode drop less than any input. may cause the device
to latch up. It is recommended that a O.1J.LFceramic disk decoupling capacitor be placed
between VCC and GND at each device to filter out this noise.

1.8
1.24 1.6
1.16 1,4
1.08 1.2
'PO 1.00 'R. 'F 1.0
'PO (300pFI 0.92 'R. 'F (30OpFI 0.8

0.84 0.6
0.76 0.4
0.68 0.2

o 50 100 200 300 400 500 50 100 200 300 400 500
CL(pFI CL(pF)
FIGURE 1 FIGURE 2
;II HARRIS HD-6440
CMOS LATCHED 3 TO 8
LINE DECODER-DRIVER

Pinout
TOP VIEW
• HIGH SPEED DECODING FOR MEMORY ARRAYS
L2 vcc
• INCORPORATES 3 ENABLE INPUTS TO SIMPLIFY EXPANSION
• LOW POWER .........•..... TYPICALLY<SOP W@SVSTANBDY L' Y7

• HIGH NOISE IMMUNITY AO Y6

• AVAILABLE IN BOTH MILITARY AND INDUSTRIAL TEMPERATURE A, Y5

RANGE A2 Y.

• HIGH CAPACITANCE DRIVE .•.•.•.•..............•. 200pF

G3 Y3
• HIGH OUTPUT DRIVE .••.••••..•....• IOH = -2mA, IOL = 2.4mA
112
• SINGLE POWER SUPPL Y
1l,

GNO Yo

The HD-6440 is a self aligned silicon CMOS gate latched decoder. One
of 8 output lines is decoded, and brought to a low state, from the 3 INPUTS
input lines. There are two latch enables (L" L2). one complemented ENABLE ADDRESS OUTPUTS

and one not, to eliminate the need for external gates. The output is G, 02G3 Ll LZ A2A,AO YaY, YZVJY" '1'5'1'6Y7 FUNCTION

enabled by three different output enables (Gl, G2, G3), two of them X X L X X X X X H H H H H H H H

X H X X X X X X H H H H H H H H DISABLE
complemented and one not. Each output remains in a high state until H x X x x x x X H H H H H H H H

it is selected, at which time it will go low. L L H L H L L L L H H H H H H H

L L H L H L L H H L H H H H H H

When using high speed CMOS memories, the delay time of the HD-6440 L L H L H L H L H H L H H H H H

L L H L H L H H H H H L H H H H
OECODE
and the enable time of the memory is usually less than the access time of L L H L H H L L H H H H L H H H

the memory. This assures that memory access time will not be lengthened L L H L H H L H H H H H H L H H

L L H L H H H L H H H H H H L H
by the use of the HD-6440 latched decoder driver. The latch is useful for L L H L H H H H H H H H H H H L

memory mapping or for systems which use a multiplexed bus. L L H X L X X X YOY1YZY3't'4't'SY6't'1

LATCHED
L L H H X X X X YOV1VZ"'3Y4YSY6Y7

A2 (61

L1I21
L2C11
01(8)
02(71
G3(6)
 Supply Voltage +8.0V
Input or Output Voltage Applied GND -0.3V to VCC +0.3
Storage Temperature Range -650C to +1500C
Operating Temperature Range
Industrial HD-6440-9 -400C to +850C
Military HD-6440-2/8 -550C to +1250C
Operating Voltage Range +4 to +7V

SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS

VIH Logical "1" Input Voltage 70% VCC V

VIL Logical "0" Input Voitage 20% VCC V
IlL Input Leakege -1.0 1.0 J.lA OV~ VIN ~ VCC
VOH Logical "1" Output Voltage VCC -0.4 V IOH = -2.0mA
VOL Logical "0" Output Voltage 0.4 V IOL = 2.4mA
ICC Supply Current 10 J.lA VCC = 5.5V
CIN Input Capacitance· 5 pF VIN = OV; TA = 25°C; f = 1MHz
Co Output Capacitance· 15 pF VIN = OV; TA = 25°C; f = 1MHz

Vcc= 5.0V <D VCC • 5.0V ± Hl%

CL = 200pF 250C TA· Indust. or Mil.

SYMBOL PARAMETER MIN MAX MIN MAX UNITS

tSET Input Setup Time 20 20 ns

tHOLD Input Hold Time 20 20 ns

tpD Propagation Delay 65 100 ns
tEN Enable Time 50 90 ns

tDIS Disable Time 50 90 n.

tpw Pulse Width 30 30 ns
tR Output Rise Time 60 90 ns
tF Output Fall Time 50 80 ns

NOTE:
<D All devices guaranteed at worse case limits. Room
temperature, 5V data provided for information -
not guaranteed.
 - _~O'J(,
a, &G2 5O%t
.3 "'"' -'EN-~-- 5~DIS--j, _:..

YO-7 -----,90% ~I- •• -------

r
TOUTPUT

20DpF

The Transient current required to charge the load capacitance is given by IT = C~. Assuming that all outputs may
dt

change state at the same time and that dv is constant; IT = (ECL) (VCC x 80%) ego [tR = 60ns. VCC = 5.0V, each
dt tR or tF
CL = 200pF, IT = (2) (200 x 10-12) 5.0 x 0.8 = 26.7mA.j This current spike may cause a large negative voltage spike
60 x 10-9
on VCC. which if it becomes a diode drop less than any input. may cause the device to latch up. It is recommended
that a 0.1 J..lFceramic disk decoupling capacitor be placed between VCC and GND at each device to filter out this noise.

1.20 2.2
1.16 2.0
1.12 1.8
1.08 1.8
1.04 1.'
~1.00 1.2
tPD (200pF)
0.96 1.0
0.92 0.8
0.98 0.8
0.84 0.'
0.90 0.2
o 50 100 200 300 400 500 o 60100 200 300
cL IpF) CL IpF)
FIGURE 1 FIGURE 2

The above example will illustrate the calculation of a more therefore 100 x 0.97 or 97nsec. To obtain the rise and fall
useful propagation delay. The system on this example uses times check the A.C. specs for the rise and fall times at
a 5 volt supply with a tolerance of ± 10%, an ambient tem- 4.5V and 1250C to obtain a worst case rise time of 90nsec.
perature of as high as 1250C. and a calculated load capaci- Use Figure 2 to find it's degradation multiple to be 0.85.
tance of 150pF. This application requires the HD-6440-2. The adjusted rise time is, therefore, 90 x 0.85 or 76.5nsec.
The table of A.C. specs shows the tPD at 4.5V and 1250C To obtain the standard 50% to 50% propagation delay, add
is 100nsec. Use the graph in Figure 1 to get the degrada- the adjusted propagation delay to half of the adjusted rise
tion multiple for 150pF. The number shown is 0.97. The time to get a propagation delay of 135nsec. The rise time
adjusted propagation delay. to the 10% or 90% point, is was used here because it is always the worst case.
The HD-6440 is especially well suited for use in battery backup systems
in conjunction with low power CMOS RAM arrays. When designing
a RAM array in conjunction with the HD-6440, the following criteria
should be met:

1. As RAM VCC drops, the inputs logical one voltages should

follow so as not to exceed VCC +0.3V and logical zero voltages
do not go below GND -0.3V.

2. G1 or G2 must be held high at CMOS VCC, or G3 held low.

L 1, L2 and address inputs should be held at either GND or
CMOS VCC.

3. YO - Y7 will maintain a VOH of VCC -0.3 or greater at IOH

of 100pA provided the HD-6440 VCC is ~2.0V.

4. When exiting from the battery backup mode, VCC should

ramp without ring on discontinuities.

5. The HD-6440 can begin operation when VCC reaches the min-
imum operating voltage.

6. The HD-6440 should be disabled one tDls before VCC reaches

the minimum operating voltage.
m HARRIS HD-6495
CMOS HEX
BUS DRIVER
Pinout
TOP VIEW
• SINGLE POWER SUPPLY
E1
• HIGH NOISE IMMUNITY
1A
• INDUSTRIAL AND MILITARY GRADES

• DRIVE CAPACITY 300pF 1y

• SOURCE CURRENT 4mA

2A
• SINK CURRENT 6mA
2y 5A
• PROPAGATION DELAY 46nlllC MAX.

3A 5y

3y 4A

GND 4y

Truth Table
The HD-6495 is a self aligned silicon gate CMOS Three-State buffer dri-
CONTROL
ver. The circuit consists of 6 non-inverting buffers with separate inputs
INPUTS INPUT OUTPUT
and outputs which permit this driver to be used for bi-directional or
uni-directional busing. A high on either Three-State control line E1 or E2 E1 E2 A Y

will force the drivers to the high impedance mode.

L L L L

L L H H

L H X HI-Z

H L X HI-Z

H H X HI-Z

X ~ OON'T CARE

HI-Z = HIGH IMPEOANCE

6A 6y 5A 5y 4A 4y
(14) (13) (12) (11) (10) (9)
 Supply Voltage +8.0V
Input or Output Voltage Applied GND -O.3V to VCC +O.3V
Storage Temperature Range -650C to +1500C
Operating Temperature Range
Industrial HD-6495-9 -400C to +850C
Military HD-6495-2/8 -550C to +1250C
Operating Voltage Range +4 to +7V

SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS

VIH Logical "1" Input Voltage 70% VCC V

VIL Logical "0" Input Voltage 20% VCC V

IlL I nput Leakage -1.0 1.0 J.lA OV~VIN~VCC

VOH Logical "1" Output Voltage VCC -0.4 V 10H = -4.0mA.
El = E2 = Low

VOL Logical "0" Output Voltage 0.4 V 10L =6.0mA

E1=E2=Low
10 Output Leakage -1.0 1.0 J.lA OV~VO~VCC.
E1 =
E2 = High
ICC Supply Current 10 J.lA VIN = VCC or GNO,
VCC = 5.5V
CIN Input Capacitance· 5 pF V,N = OV; TA = 25°C;
f = 1MHz

Co Output Capacitance * 15 pF VIN = OV; T A = 25°C;

f = 1MHz

VCC·5.0V <D VCC-6.0V±10%

26°C TA· Indus. or Mil.

I
SYMBOL PARAMETER MIN MAX MIN MAX UNITS

tpo Propagation Delay 36 45 n,

tEN Enable Time 90 100 n,

tOIS Disable Time 90 100 n,

tR Output Rise Time 85 95 n,

tF Output Fall Time 65 75 n,

NOTE <D All devices guaranteed at worst case limits. Room temperature,
5V data provided for information-not guaranteed.
 ----_ 50% 50% -------

I: =1:
tEN 80% L -=.i 'OIS ~O%

40% ~

The transient current required to charge the load capacitance is given by IT = C~. Assuming that all outputs may
dt

change state at the same time and that dv is constant; IT =(ECL) (VCC x 80%) ego [tR =85ns, VCC =5.0V, each
dt tR or tF
5.0 x 0.8 ]
CL = 300pF, IT = (6) ( 300 x 10-12 ) ----= 84.7mA. ThiS current spike may cause a large negative voltage
85 x 10-9

spike on VCC, which if it becomes a diode drop less than any input, may cause the device to latch up. It is recom-
mended that a 0.1 !J. F ceramic disk decoupling capacitor be placed between VCC and GND at each device to filter
out this noise.

1.8
1.24 1.8
1.16 1.4
1.08 1.2
~1.00 ~1.0
tpo 1300pFI 0.92 tn. tF (3OOpFI 0.8

0.84 0.6
0.76 0.4
0.68 0.2

o 50 100 200 300 400 600 o 50 100 200 300 400 600
CLlpFI CLlpFI
FIGURE 1 FIGURE 2

The above example will illustrate the calculation of a more therefore 45 x 0.84 or 38nsec. To obtain the rise and fall
useful propagation delay. The system on this example uses times ch'eck the A.C. specs for the rise and fall times at
a 5 volt supply with a tolerance of ± 10%, an ambient tem- 4.5V and 1250C to obtain a worst case rise time of 95nsec.
perature of as high as 1250C, and a calculated load capaci- Use Figure 2 to find it's degradation multiple to be 0.65.
tance of 150pF. This application requires the HD-6495-2. The adjusted rise time is, therefore, 95 x 0.65 or 62nsec.
The table of A.C. specs shows the tPD at 4.5V and 1250C To obtain the standard 50% to 50% propagation delay, add
is 45nsec. Use the graph in Figure 1 to get the degrada- the adjusted propagation delay to half of the adjusted rise
tion multiple for 150pF. The number shown is 0.84. The time to get a propagation delay of 69nsec. The rise time
adjusted propagation delay, to the 10% or 90% point, is was used here because it is always the worst case.
 REFERENCE PAGE 3-77 FOR
HARRIS COMPLETE SPECIFICATIONS 82C82
CMOS OCTAL LATCHING
BUS DRIVER

• FULL EIGHT BIT PARALLEL LATCHING BUFFER Pinout

• BIPOLAR 8282 COMPATIBLE
• THREE STATE NON-INVERTING OUTPUTS
TOP VIEW
• PROPAGATION DELAY - 350sec MAX.
D10 vCC
• A.C. CHARACTERISTICS GUARANTEED FOR:
D1l DOO
• FULL TEMPERATURE RANGE
DI2 DO,
• 10% POWER SUPPLY TOLERANCE
DI3 D02
• CL = 300pF
DI4 D03
• ~NGLE5VPOWERSUPPLY
015 004
• POWER SUPPL Y CURRENT - 1ll;JA MAX. STANDBY
• OUTPUTS GUARANTEED VALID AT VCC = 2.0 VOLTS 016 DOS

• COMMERCIAL, INDUSTRIAL AND MILITARY TEMPERATURE RANGES DI7 D06

• 20 PIN PACKAGE ON 0.3" CENTERS OE D07

GNO STS

The Harris 82C82 is an octal latching buffer manufactured using a self-

aligned silicon gate CMOS process. This circuit provides an eight bit
parallel latch/buffer in a 20 pin package. The active high strobe (sTB)
input allows transparent transfer of data and latches data on the negative
transition of this signal. The active low output enable (OE) permits simple
interface to state-of-the-art microprocessor systems.

010 - 01] Data Input Pins

000 - 007 Data Output Pins
STB Active High Strobe Input
5E Active low Output Enable

STS OE DI 00

X H X Hi-Z
H L L L
H L H H

+ L X

H = Logic One Hi-Z:: High Impedance

L = Logic Zero t = Negative Transition
X = Don't Care Latched to value of last data
m HARRIS CMOS OCTAL LATCHING
82C83
INVERTING BUS DRIVER

Pinout
• FULL EIGHT BIT PARALLEL LATCHING INVERTING BUFFER
• BIPOLAR 8283 COMPATIBLE 010 VCC
• THREE STATE NON-INVERTING OUTPUTS 011 500
• PROPAGATION DELAY - 35n.oc MAX. 01 2 50,
• A.C. CHARACTERISTICS GUARANTEED FOR: 013 502
• FULL TEMPERATURE RANGE
014 503
.10% POWER SUPPLY TOLERANCE
• CL· 300pF
OIS 504
• ~NGLE5VPOWERSUPPLY
016 50s
• POWER SUPPLY CURRENT - 10f.lA MAX. STANDBY 7
01 506
• OUTPUTS GUARANTEED VALID AT VCC· 2.0 VOLTS 6E 507
• COMMERCIAL,INDUSTRIAL AND MILITARY TEMPERATURE RANGES GNO STB
• 20 PIN PACKAGE ON 0.3" CENTERS

PIN NAMES
The Harris 82C83 is an octal latching buffer manufactured using a self-
010 - 017 Data Input Pins
aligned silicon gate CMOS process. This circuit provides an eight bit 500 - 507 I nverted Data Output Pins
parallel latch/buffer in a 20 pin package. The active high strobe (STB) STB Active High Strobe Input

input allows transparent transfer of data and la'tches data on the negative 6E Active Low Output Enable

transition of this signal. The active low output enable (OE) permits simple
interface to state-of-the-art microprocessor systems. The 82C83 provides
inverted data at the outputs.

r-------,
~ I~
I I
I I
I I
I I
I I
L J
STB OE 01 DO

X H X Hi-Z
H L L H
H L H L
I L X

H" LogiC One Hi-Z" High Impedance

L '" Logic Zero '''' Negative Transition
X" Don'{ Care Latched to value of last data

CAUTION: Electronic devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.

4-82
m HARRIS
CMOS OCTAL
82C86
BUS TRANSCIEVER

Pinout
• FUll EIGHT BIT BIDIRECTIONAL BUS INTERFACE TOP VIEW
• INOUSTRY STANDARD 82B6 COMPATIBLE PINOUT
• THREE STATE NDN·INVERTING OUTPUTS Ao Vcc
• PROPAGATION DELAY 35 NSEC
• A.C. CHARACTERISTICS GUARANTEED AT RATED Cl A1 80
• A SIDE· Cl = 100pF
• B SIDE· Cl = 30DpF A2 81
• SINGLE 5V POWER SUPPLY
• POWER SUPPLY CURRENT 10 ~A MAX Standby A3 82
• 20 PIN PLASTIC OR CERAMIC PACKAGE
• COMMERCIAL, INDUSTRIAL AND MilITARY TEMPERATURE RANGES AVAilABLE A4 83
AS 84
A6 8s
Description A7 86
The Harris 82C86 is an octal bus transceiver manufactured using a self·aligned OE 87
silicon gate CMOS process (Scaled SAJI IV). This circuit provides a full eight bit
bidirectional bus interlace In a 20 pin package. The Transmit (T) control deter· GND T
mines the data direction. The active low output enable (OE) allows simple inter·
face to the 80C86 and other microprocessors. The outputs of the 82C86 are non·
PIN NAMES
Inverting.
Ao·A7 LOCAL BUS DATA I/O PINS

Bo·B7 SYSTEM BUS DATA I/O PINS

T TRANSMIT CONTROL INPUT

DE ACTIVE LOW OUTPUT ENABLE

T DE A B
X H HI·Z HI·Z
H L I 0
L L 0 I
H = logical one
L = logical zero
I = input mode
o = output mode
X = don'l care
Hi·Z = high impedance

CAUTION: Electronic devices are sensitive 10 electrostatic discharge. Proper I.C. handling procedures should be followed.

4-83
 ~Vo;:J I n#-\I'I~l,;t:IVt:H

Pinout
• FULL EIGHT BIT BIDIRECTIONAL BUS INTERFACE TOP VIEW
• INDUSTRY STANDARD 8287 COMPATIBLE PINOUT
• THREE STATE INVERTING OUTPUTS AO Vcc
• PROPAGATIONDELAY 35 NSEC
• A.C. CHARACTERISTICS GUARANTEED AT RATED Cl Al SO
• A SIDE· Cl = 100pF B,
• B SIDE - Cl = 300pF A2
• SINGLE 5V POWER SUPPLY
• POWER SUPPLY CURRENT 10 ~A MAX Standby
A3 B2
• 20 PIN PLASTIC OR CERAMIC PACKAGE A4 !3
• COMMERCIAL, INDUSTRIAL AND MILITARY TEMPERATURE RANGES AVAILABLE
AS B4
A6 as
Description A7 B6
The Harris 82G8? is an octal bus transceiver manufactured using a self-aligned OE 87
silicon gate GMOS process (Scaled SAJI IV). This circuit provides a full eight bit
GND T
bidirectional bus interface in a 20 pin package. The Transmit (T) control deter-
mines the data direction. The active low output enable (OE) allows simple inter-
face to state of the art microprocessors. Data at the outputs of the 82G8? are
PIN NAMES
inverted.
Ao·A, LOCAL BUS OATA I/O PINS

Bo-B, SYSTEM BUS OATA I/O PINS

T TRANSMIT CONTROL INPUT

OE ACTIVE LOW OUTPUT ENABLE

T OE A B
X H Hi-Z Hi·Z
H L I 0
L L 0 I
H = logical one
L = logical zero
I = input mode
o = output mode
X = don't care
Hi·Z = high impedance

CAUTION: Electronic devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
4-84
5-2

5-3
HD-15530 Manchester Encoder-Decoder 5-3
HD-15531 Manchester Encoder-Decoder 5-10
HD-15531B Programmable Manchester Encoder-Decoder 5-18
HD-6408 Asynchronous Serial Manchester Adapter 5-25
HD-6409 Manchester Encoder-Decoder 5-30
HD-6406 Programmable Asynchronous 5-39
Communication Interface
82C52 Serial Controller Interface 5-50
HD-6402 LSI Universal Asynchronous Receiver Transmitter 5-51
HD-4702 Programmable Bit Rate Generator 5-56
m HARRIS HD-15530

VALID waRD 24 Vec

SUPPORT OF MIL-STD-1553 ENCODER SHIFT CLOCK 23 ENCODER CLOCK
TAKE DATA 22 SEND CLOCK IN
• 1.25 MEGABIT/SEC DATA RATE
SERIAL DATA OUT 21 SEND OATA
• SYNC IDENTIFICATION AND LOCK-IN
DECODER CLOCK 20 SYNC SELECT
• CLOCK RECOVERY BIPOLAA ZERO IN 19 ENCODER ENABLE
• MANCHESTER II ENCODE, DECODE BIPOLAR ONE IN 18 SERIAL DATA IN

• SEPARATE ENCODE AND DECODE UNIPOLAR DATA IN 17 BIPOLAR ONE OUT

DECODER SHIFT CLOCK 16 OUTPUT iN"Hiii"T
• LOW OPERATING POWER: 50mW AT 5 VOLTS
COMMAND/DATA SYNC 15 BIPOLAR ZERO OUT
• FULL MILITARY TEMPERATURE RANGE DECODER RESET '4 +60UT
GNO 13 MASTER REseT

The Harris HD-15530 is a high performance CMOS This integrated circuit is fully guaranteed to support
device intended to service the requirements of MI L- the 1MHz data rate of MIL-STD-1553 over both
STD-1553 and similar Manchester II encoded, time temperature and voltage. It interfaces with CMOS,
division multiplexed serial data protocals. This LSI TTL or N channel support circuitry, and uses a
chip is divided into two sections, an Encoder and a standard 5 volt supply.
Decoder. These sections operate completely in-
dependent of each other, except for the Master Reset The HD-15530 can also be used in many party line
function. digital data communications applications, such as an
environmental control system driven from a single
This circuit meets many of the requirements of twisted pair cable or fiber optic cable throughout
M I L-STD-1553. The Encoder produces the sync the building.
pulse and the parity bit as well as the encoding of the
data bits. The Decoder recognizes the sync pulse and
identifies it as well as decoding the data bits and
checking parity.

12) OND
13 MASTER RESET

22 UNIPOLAR
DATA IN
14 BIPOLAR BIPOLAR 7 TAKE DATA

ONE OUT ONI! IN COMMAND/DATA

BIPOLAR SYNC
BIPOLAR ZERO IN
ZERO OUT •• IE RIAL
DATA OUT

DECODER a , VALID
CLOCK WORD

MAlTER • DECODER
AElET SHIFT
CLOCK

SEND SERIAL SYNC

DATA DATA IN SELECT

ENCODER ENCODER
SHIFT ENABLE
CI.OCK
 Supply Voltage +7.0V

Input or Output Voltage Applied GND -O.3V to VCC +O.3V

Storage Temperature Range -650C to +150oC

Operating Temperature Range

Industrial HD-15530-9 -400C to +850C

Military HD-15530-2/8 -550C to + 1250C

SYMBOL PARAMETER MINIMUM TYPICAL MAXIMUM UNITS TEST CONDITIONS

VIH Logical "," Input Voltage 70% VCC V

VIL Logical "0" Input Voltage 20% VCC V
VIHC Logical "1" Input Voltage (Clock) VCC -0.5 V
VILC Logical "0" Input Voltage (Clock) GND +0.5 V
IlL Input Leakage -1.0 +1.0 f..LA
OV" VIN " VCC
VOH Logical "1" OutPUt Voltage 2.4 V IOH = -3mA
VOL Logical "0" Output Voltage 0.4 V IOL = 1.8mA
'CCSS Supply Current Standby 0.5 2 mA VIN = VCC = 5.5V
Outputs Open
ICCOp Supply Current Operating* 8.0 10.0 mA VCC = 5.5V.
f =lMHz
CIN Input Capacitance* 5.0 7.0 pF
CO Output Capacitance* 8.0 10.0 pF

-Guaranteed and sampled but not 100% tested.

ENCODER TIMING VCC = 5.0V ±10% TA = Industrial or Military

FEC Encoder Clock Frequency 0 15 MHz CL = 50pF

FESC Send Clock Frequency 0 2.5 MHz
TECfl Encoder Clock Rise Time 8 ns
TECF Encoder Clock Fall Time 8 ns
FED Data Rate 0 1.25 MHz
TMR Master Reset Pulse Width 150 ns
TEl Shift Clock Delay 125 ns
TE2 Serial Data Setup 75 ns
TE3 Serial Data Hold 75 n,
TE4 Enable Setup 90 n,
TE5 Enable Pulse Width 100 n,
TEB Sync Setup 55 n,
TE7 Sync Pulse Width 150 n,
TE8 Send Data Delay 0 50 n,
TE9 Bipolar Output Delay 130 n,

DECODER TIMING VCC = 5.0V ±10% TA = I ndustrial or Military

FDC Decoder Clock Frequency 0 15 MHz CL = 50pF

TDCR Decoder Clock Rise Time 8 ns
TDCF Decoder Clock Fall Time 8 n,
FDD Data Rate 0 1.25 MHz
TDR Decoder Reset Pulse Width 150 n,
TDRS Decoder Reset Setup Time 75 n,
TMR Master Reset Pulse Width 150 n,
TDl Bipolar Data Pulse Width TDC +10 n,
TD2 Sync Transition Span 18TDC n'
TD3 One Zero Overlap TDC -10 n,
TD4 Short Data Transition Span BTDC n,
TD5 Long Data Transition Span 12TDC n,
TDB Sync Delay (ON) -20 110 ns
TD7 Take Data Delay (ON) 0 110 n,
TD8 Serial Data Out Delay 80 n,
TD9 Sync Delay (OF F I 0 110 n,
TDlD Take Data Delay (OFF) 0 110 n,
T011 Valid Word Delay 0 110 n,

NOTE <D : TDC = Decoder Clock Period ~ tic

These parameters are guaranteed but not 100% tested.
PIN SECTION NAME DESCRIPTION

1 Decoder VALID WORD Output high indicates receipt of a valid word.

2 Encoder ENCODER SHIFT CLOCK Output for shifting data into the Encoder. This
clock shifts data on a low-ta-high transition.

3 Decoder TAKE DATA Output is high during receipt of data after ident-
ification fa a sync pulse.
4 Decoder SERIAL DATA OUT Delivers received data in correct NRZ format.

5 Decoder DECODER CLOCK Input drives the transition finder, and the synchron-
izer which in turn supplies the clock to the balance
of the Decoder.

6 Decoder BIPOLAR ZERO IN A high input should be applied when the bus is in its
negative state. This pin must be held high when
the Unipolar input is used.

7 Decoder BIPOLAR ONE IN A high input should be applied when the bus is in
its positive state, this pin must be held low when
the Unipolar input is used.

8 Decoder UNIPOLAR DATA IN With pin 6 high and pin 7 low, this pin enters unipolar
data into the transition finder circuit. If not used this
input must be held low.

9 Decoder DECODER SHIFT CLOCK Output which delivers a frequency (Decoder Clock
.;- 12), synchronized by the recovered serial data
stream.
10 Decoder COMMAND SYNC Output of a high from this pin occurs during output
of decoded data which was preceded by a Command
(or Status) synchronizing character. A low output
indicates a Data synchronizing character.
11 Decoder DECODER RESET A high input to this pin during a rising edge of
DECODER SHIFT CLOCK resets the decoder bit
counting logic to a condition ready for a new word.
12 Both GROUND Ground supply pin.
13 Both MASTER RESET A high on this pin clears 2: 1 counters in both the
Encoder and Decoder.
14 Encoder -:- 6 OUT Output from 6: 1 divider which is driven by the
ENCODER CLOCK.
15 Encoder BIPOLAR ZERO OUT An active low output designed to drive the zero or
negative sense of a bipolar line driver.
16 Encoder OUTPUT INHIBIT A low on this input forces pin 15 and pin 17 high,
the inactive states.
17 Encoder BIPOLAR ONE OUT An active low output designed to drive the one or
positive sense of a bipolar line driver.
18 Encoder SERIAL DATA IN Accepts a serial data stream at a data rate equal to
ENCODER SHIFT CLOCK.
19 Encoder ENCODER ENABLE A high on this input initiates the encode cycle.
(Subject to the preceding cycle being complete.)
20 Encoder SYNC SELECT Actuates command sync for an input high and data
sync for an input low.
21 Encoder SEND DATA Is an active high output which enables the external
source of serial data.
22 Encoder SEND CLOCK IN Clock input at a frequency equal to the data rate X2.
23 Encoder ENCODER CLOCK Input to the 6: 1 divider.
24 Both VCC Positive supply pin.
The Encoder requires a single clock with a frequency of clocked into the SERIAL DATA input with every low-
twice the desired data rate applied at the SEND CLOCK to-high transition of the ENCODER SHIFT CLOCK @ -
input. An auxiliary divide by six counter is provided on @. After the sync and the Manchester II coded data are
chip which can be utilized to produce the SEND CLOCK transmitted through the BIPOLAR Ol'rr
and BIPOLAR
by dividing the DECODER CLOCK. ZE RO outputs, the Encoder adds on an additional bit
which is the parity for that word ®.
At any time a low on
The Encoder's cycle begins when ENCODER ENABLE is OUTPUT INHIBIT input will force both bipolar outputs to
high during a falling edge of ENCODER SHIFT CLOCK <D. a high state but will not affect the Encoder in any other
This cycle lasts for one word length or twenty ENCODER way.
SH I FT CLOCK periods. At the next low-to-high transition
of the ENCODER SHI FT CLOCK, a high at SYNC SEL- To abort the Encoder transmission a positive pulse must
ECT input actuates a command sync or a low will produce be applied at MASTER RESET. Anytime after or during
a data sync for that word @ . When the Encoder is ready this pulse, a low to high transition on SEND CLOCK
to accept data, the SEND DATA output will go high and clears the internal counters and initializes the Encoder
remain high for sixteen ENCODER SHIFT CLOCK per- for a new word.
iods @. During these sixteen periods the data should be

I" I "1" I" I" 1 I I

{lJlflIlJl.I1.A

~
---.J t\\\\,\\\\\\\\\\.~9IDctcAREfu\.'''\\\%\\~ ~\\\\\\\\\\\\\\\.\\\Wj
\%.\\\\'FALlQ&\W'\\\
'\\\\\\,\_'1 CA."$I.\\\\\\\.~~ }%.\.\\\\\~\\\\\. "\\\\\\\\\\ \\\\\"",,\\W
f

: ,12 1,10 I
~-'-I2T;T;-F I
~_d_~L,,-L.!'-LU
<M5

The Decoder requires a single clock with a frequency of Decoder is transmitting the decoded data through SERIAL
12 times the desired data rate applied at the DECODER DATA OUT. The decoded data available at SERIAL
CLOCK input. The Manchester II coded data can be pre- DATA OUT is in a NRZ format. The DECODER SHIFT
sented to the Decoder in one of two ways. The BIPOLAR CLOCK is provided so that the decoded bits can get shifted
ONE and BIPOLAR ZERO inputs will accept data from a into an external register on every low-to-high transition
comparator sensed transformer coupled bus as specified of this clock ®-@.
in Military Spec 1553. The UNIPOLAR DATA input can
only accept non-inverted Manchester II coded data. (e.g. After all sixteen decoded bits have been transmitted @ the
from BIPOLAR ITRO mJT of an Encoder.) data is checked for odd parity. A high on VALID WORD
output ® indicates a successful reception of a word with-
The Decoder is free running and continuously monitors its out any Manchester or parity errors. At this time the
data input lines for a valid sync character and two valid Decoder is looking for a new sync character to start another
Manchester data bits to start an output cycle. When a output sequence.
valid sync is recognized<D ,the type of sync is indicated on
COMMAND/DATA SYNC output. If the sync character At any time in the above sequence a high input on DE-
was a command sync, this output will go high @ and re- CODER RESET during a low-to-high transition of DE-
main high for sixteen DECODER SHIFT CLOCK periods CODER SHIFT CLOCK will abort transmission and initial-
@ , otherwise it will remain low. The TAKE DATA ize the Decoder to start looking for a new sync character.
output will go high and remain high @ - @ while the
 TIMING 11 0 ' 1 ,I 31' I ' I· 1,1' 1 1 "1"1" I,. 1 1 I I
DECODER
SHIFT CLOCK ~
rr_!L'..Ld_U _
7r']'JoI p]

o f..\\\\\\\\.~
~--------------,-
&50

II NO CLOCK --j ~T11 I

INCDDIR IHIH CLOCK ----J ~ T14 1 I I

INCDOERINAILI -------~~T ••

IVNC IILICT -~-~-$-1-.~-$-~-~-$-~-~"'-$-~-~-~-1-.~~ VALID

T17

INCDOIR IHIH CLOCK ----J

IIND DATA
TIed E_=============
IINDCLOCK~TI'
'JJ1J&D
~rmllltJ'l'
M lSUT'or -----~
'- J, ~ ~---

NDTE: UNIPOLAR IN· 0, FOR NIXT DIAGRAMS

81P0LAR ON'

BIPOLAR ZERO IN
IN
~BITPERIDO

"foi=k\%\%\&\\\\\\.\\\\\\\\\\\':
:
I BIT PERIOD

TD27o~\\\'\\\'\\\\'\)"W\\\\'§\~e
I BITPERIDD~

F
i i I T02 I

OATA8VNC

i I i :
BlPOLARONEIN~' : r.-TO;;&\\.\\\"~~--r.-:
T
BIPOLAR ZERO IN Io- 03 ~\\\"WTD3 i~~T03

I-- T[)4 TOll 4- TOll T[)4--i

ZERO ONE

NOTE: BljLAR ONE IN· 0; BIPOLAR ZERO IN· t. FOR NEXT DIAGRAMS.

UNIPOLAR IN :J~-----T02 T02

COMMAND SYNC

UNIPOLAR IN J~; -----TO'----~_-----TO, r\\\\\\\.\.'l!

DATASVNC

UNIPOLAR IN --t===, T[)4 T05--~----TO' ~:T[)4:::::::t-

ONE ZERO ON'
DECOOEASHIFTCLOCK ~ I I r-
CQMMAND!DATASYNC ~ _

TAKE
DATA
~_I-----------------------

O'COO'.SHOFTCCOCK
~ r-
SEAIAL ~-----O'-T-'-B-'T------X::::::::::::::::::::::::::::::::::::::::::=
DATA OUT

OECOOEASHIFTCLOCK ~
_------<
TD9-1 ••..••

COMMANOI6ATA SYNC -::-n._,-o=1-,-."i------------------------

TAKE DATA ---, _

=-'"=
TOAS~ ~-----_.-- _

____ ~I.•-------------------- --1- _

V ZZZZZZZZZZZ7777ZZZJ
The 1553 standard defines a time division multiplexed
data bus for appl ication with in aircraft. The bus is defined
to be bipolar, and encoded in a Manchester II format, so
no DC component appears on the bus. This allows trans-
former coupling and excellent isolation among systems and
their environment.

The HD-15530 supports the full bipolar configuration,

assuming a bus driver configuration similar to that in
Figure 1. Bipolar inputs from the bus, like Figure 2,
are also accommodated.

The signaling format in MI L-STD-1553 is specified on

the assumption that the network of 32 or fewer terminals
are controlled by a central control unit by means of Com-
mand Words. Terminals respond with Status Words. These
control words reference Data Words. Each word is preced-
ed by a synchronizing pulse, and followed by parity bit,
occupying a total of 20Jlsec. The word formats are shown
in Figure 4. The special abbreviations are as follows:

P Parity, which is defined to be odd, taken

across all 17 bits.

TF Terminal Flag, if set, calls for controller

to request self-test data.

The paragraphs above are intended only to suggest the

content of MIL-STD-1553 and do not completely
describe its bus requirements, timing or protocols.

I ~----_---

9:::l 5
~l 5 I_~~
I -------f-------- SYNC I TERMINAL
I I SUBADDRESS I DATA WORD I I
p

~E~~O+E~~~~~~cFl
ADDRESS /MOOE COUNT
RIT
DATA WORD (SENT EITHER DIRECTION)

~I~
t
1_6

SYNC I DATA WORD I I

p

LOGICAL ONE DATA

LOGICAL ZERO DATA r 1

ME
I
9

CODE FOR FAILURE MODES ITFI p

1 1

I
IJ HARRIS HD-15531

VALID WORD
"cc
,
1 '"" 40
39
COUNT
COUNT
Cl
C4
TAKE DATA' 3 38 DATA SYNC
• SUPPORT OF MIL-5TO-1553
SERIAL
TAKE
DATA
DATA
OUT
•
5 ,.
31 ENCOOER
COUNT C3
CLOCK

• 1.25 MEGABIT/SEC OATA RATE SYNCHAONOUS DATA

SR.
• " N.C.

"
SYNCHRONOUS DATA 7 ENCOOEA SHIFT CLOCK
• SYNC IDENTIFICATION AND LOCK-IN SYNCHRONOUS CL.OCK
,• 33 SEND CLOCK IN

• CLOCK RECOVERY
ceCOCER
SYNCHRONOUS CLOCK
CLOCK
SEL. ,. ",.
"
SEND
ENCOOER
DATA
PARITY SEL.

• VARIABLE FRAME LENGTH TO 32 BITS BIPOLAR ZERO IN

" SYNC SELECT
ENCODER ENABLE
• MANCHESTER II ENCODE, DECODE
BIPOLAR ONE IN
",.
13 " SERIAL DATA IN
UNIPOLAR QATA IN
""
• SEPARATE ENCODE AND DECODE
DECODER SHIFT
TRANSITION
CLOCK
SEL.
,.
" ""
~1SNl&i'f
OUTPUT iNHiBiT

,.
N.C. BIPOLAR ZERO OUT

,.,.
• LOW OPERATING POWER: 50mW (ijl5 VOLTS COMMAND SYNC 17
" +80UT

""
DECODER PARITY SEL. COUNT C2
• FULL MILITARY TEMPERATURE RANGE DECODER RESET MASTER RESET
COUNT Co 21 GNO

The Harris HD-15531 is a high performance CMOS MIL-STD-1553 by allowing the frame length to be
device intended to service the requirements of MI L- programmable. The frame length may be programmed
STD-1553 and similar Manchester II encoded, from 2 to 28 data bits plus sync and parity. This
time division multiplexed serial data protocals. This chip also allows selection of either even or odd
LSI chip is divided into two sections, an Encoder parity for the Encoder and Decoder separately.
and a Decoder. These sections operate independently
of each other, except for the Master Reset and This integrated circuit is fully guarenteed to support
frame length functions. the lMHz data rate of MIL-STD-1553 over both
temperature and voltage. It interfaces with CMOS,
This circuit provides many of the requirements of TTL or N channel support circuitry, and uses a
M I L-STD-1553. The Encoder produces the sync standard 5 volt supply.
pulse and the parity bit as well as the encoding of
the data bits. The Decoder recognizes the sync pulse The HD-15531 can also be used in many party line
and identifies it as well as decoding the data bits digital data communications applications, such as
and checking parity. an environmental control system driven from a single
twisted pair of fiber optic cable throughout a
building.

UNIPOLAR
DATA IN TAKE DATA
BIPOLAR COMMAND
ONE IN IYNC
BIPOLAR DATA SYNC
ZERO IN
SERIAL DATA OUT

DECODER
CLOCK VALID WORD
TRANSITION PARITY
SElECT SELECT
SYNCHRONOUS
,. DECODER SHIFT
CLOCK
CLOCK
29 30 31 SYNCHRONOUS 10
SERIAL CLOCK SELECT 22
DATA MASTER
OUT SELECT RESET
ENCODER ENCODER ENCODER
SHIFT ENABLE PARITY
ClOCK SElECT
The 1553 standard defines a time division multiplexed
data bus for application within aircraft. The bus is defined
to be bipolar, and encoded in a Manchester II format, so
no DC component appears on the bus. This allows trans-
former coupling and excellent isolation among systems and
their environment.

The HD-15531 supports the full bipolar configuration,

assuming a bus driver configuration similar to that in
,.~.
Figure 1. Bipolar inputs from the bus, like Figure 2,
are also accommodated. uo•. >-{>-!J
The signaling format in MIL-STD-1553 is specified on
the assumption that the network of 32 or. fewer terminals
are controlled by a central control unit by means of Com-
mand Words, and Data. Terminals respond with Status
Words, and Data. Each word is preceded by a synchron-
izing pulse, and followed by parity bit, occupying a total
of 20 fJ. sec. The word formats are shown in Figure 4.
The special abbreviations are as follows:

P Parity, which is defined to be odd, taken

across all 17 bits.

TF Terminal Flag, if set, calls for controller

to request self-test data.

The paragraphs above are intended only to suggest the

content of M I L-STD-1553, and do not completely
describe its bus requirements, timing or protocols.

I -------r--------
COMMAND WORD (FROM CONTROLLER TO TERMINAL!

9:::j 5 8 5 I 5

I -------f-------- SYNC I TERMINAL I I SUBADDRESS I DATA WORD

~E~~e+E~~o+e~~~
ADDRESS RIT /MODE COUNT

DATA WORD (SENT EITHER DIRECTION!

c::R I~
t
l_6

SYNC I DATA WORD I I

p

LOGICAL ONE DATA

LOGICAL ZERO DATA r 1

ME
I CODE FOR FAILURE
9 1

MODES ITFI P
1
 Supply Voltage +7.0V
Input or Output Voltage Applied GND -O.3V to VCC +O.3V
Storage Temperature Range -650C to +1500C
Operating Temperature Range
Industrial HD-15531-9 -400C to +850C
Military HD-15531-2/8 -550C to +1250C

SYMBOL PARAMETER MINIMUM TYPICAL MAXIMUM UNITS TEST CONDITIONS

VIH Logical "1" Input Voltage 70% VCC V

VIL Logical "0" Input Voltage 20% VCC V
VIHC Logical "1" Input Voltage (Clock) VCC -0.5 V
VILC Logical "0" Input Voltage (Clock) GND +0.5 V
IlL I nput Leakage -1.0 +1.0 }lA OV" VIN " VCC
VOH Logical "1" Output Voltage 2.4 V IOH = -3mA
VOL Logical "0" Output Voltage 0.4 V IOL = 1.8mA
ICCS8 Supply Current Standby 0.5 2.0 mA VIN = VCC = 5.5V
Outputs Open
ICCOp Supply Current Operating· 8.0 10.0 mA VCC = 5.5V,
f=15MHz
CIN Input Capacitance· 5.0 7.0 pF
Co Output Capacitance· 8.0 10.0 pF
-Guaranteed and sampled but not 100% tested.

ENCODER TIMING

FEC Encoder Clock Frequency 0 15 MHz CL = 50pF

FESC Send Clock Frequency 0 2.5 MHz
TECR Encoder Clock Rise Time 8 ns
TECF Encoder Clock Fall Time 8 ns
FED Data Rate 0 1.25 MHz
TMR Master Reset Pulse Width 150 ns
TEl Shift Clock Delay 125 ns
TE2 Serial Data Setup 75 ns
TE3 Serial Data Hold 75 ns
TE4 Enable Setup 90 ns
TE5 Enable Pulse Width 100 ns
TE6 Sync Setup 55 ns
TE7 Sync Pulse Width 150 ns
TEa Send Data Delay 0 50 ns
TE9 Bipolar Output Delay 130 ns
DECODER TIMING

FDC Decoder Clock Frequency 0 15 MHz CL = 50pF

FDS Decoder Synchronous Clock 0 2.5 MHz
TDCR Decoder Clock Rise Time 8 ns
TDCF Decoder Clock Fall Time 8 ns
FDD Data Rate 0 1.25 MHz
TDR Decoder Reset Pulse Width 150 ns
TDRS Decoder Reset Setup Time 75 ns
TMR Master Reset Pulse Width 150 ns
TDl Bipolar Data Pulse Width TDC +10 ns
TD2 Sync Transition Span 18TDC ns
TD3 One Zero Overlap TDC -10 ns
TD4 Short Data Transition Span 6TDC ns
TD5
TD6
Long Data Transition Span
Sync Delay (ON I -20
12TDC
110
ns
ns
~
TD7 Take Data Delay (ON I 0 110 ns
TD8 Serial Data Out Delay 80 ns
TD9 Sync Delay (OF F) 0 110 ns
TD10 Take Data Delay (OFF) 0 110 ns
TDll Valid Word Delay 0 110 ns
TD12 Synchronous Clock To Shift Clock Delay 75 ns
TD13 Synchronous Data Setup 75 ns
NOTE <D: TDC = Decoder Clock Period =_1_
FDC
These parameters are guaranteed but not 100% tested.
PIN SECTION NAME DESCRIPTION

1 Both VCC Positive supply pin.

2 Decoder VALID WORD Output high indicates receipt of a valid word.
3 Decoder TAKE DATA' A continuous, free running signal provided for host timing or data
handling. When data is present on the bus, this signal will be
synchronized to the incoming data and will be identical to take data.

4 Decoder TAKE DATA Output is high during receipt of data after identification of a sync pulse
5 Decoder SERIAL DATA OUT Delivers received data in correct NRZ format.
6 Decoder SYNCHRONOUS DATA I nput presents Manchester data directly to character identification
logic. SYNCHRONOUS DATA SELECT must be held high to use
this input. If not used this pin should be held high.
7 Decoder SYNCHRONOUS DATA SELECT I n high state allows the synchronous data to enter the character identi-
fication logic.
Input provides externally synchronized clock to the decoder.
8 Decoder SYNCHRONOUS CLOCK
This input should be tied high when not in use.
9 Decoder DECODER CLOCK Input drives the transition finder, and the synchronizer which in
turn supplies the clock to the balance of the decoder.
10 Decoder SYNCHRONOUS CLOCK SELECT In high state directs the SYNCHRONOUS CLOCK to control the decoder

11 Decoder
I BIPOLAR ZERO IN
character identification logic. A low state selects the DECODER CLOCK
A high input should be applied when the bus is in its negative state.
This pin must be held high when the unipolar input is used.
12 Decoder BIPOLAR ONE IN A high input should be applied when the bus is in its positive state.
This pin must be held low when the unipolar input is used.
13 Decoder UNIPOLAR DATA IN With pin 11 high and pin 12 low, this pin enters unipolar data into
the transition finder circuit. If not used this input must be held low.
14 Decoder DECODER SHIFT CLOCK Output which delivers a frequency (DECODER CLOCK + 12),
synchronized by the recovered serial data stream.
15 Decoder TRANSITION SELECT A high input to this pin causes the transition finder to synchronize on
every transition of input data. A low input causes the transition finder
to synchronize only on mid-bit transitions.
16 Blank N.C. Not connected.
17 Decoder COMMAND SYNC Output of a high from this pin occurs during output of decoded data
which was preceded by a Command (or Status) synchronizing character
18 Decoder DECODER PARITY SELECT An input for parity sense, calling for even parity with input high and
odd paritY with input low.
19 Oecoder DECODER RESET A high input to this pin during a rising edge of DECODER SHIFT
CLOCK resets the decoder bit counting logic to a condition ready
for a new word.
20 Both COUNT Co One of five binary inputs which establish the total bit count to be
encoded or decoded.
21 Both GROUND Supply pin.
22 Both MASTER RESET A high on this pin clears 2: 1 counters in both the encoder and decoder.
23 Both COUNT C2 See pin 20.
24 Encoder 6 OUT Output from 6: 1 divider which is driven by the ENCODER CLOCK.
25 Encoder BIPOLAR ZERO OUT An active low output designed to drive the zero or negative sense of
a bipolar line driver.
26 Encoder OUTPUT INHIBIT A Iowan this pin forces pin 25 and 27 high, the inactive states.
27 Encoder BIPOLAR ONE OUT An active low output designed to drive the one or positive sense of
a bipolar line driver.
2B Encoder SERIAL DATA IN Accepts a serial data stream at a data rate equal to ENCODER SHIFT
CLOCK.
29 Encoder ENCODER ENABLE A high on this pin initiates the encode cycle. (Subject to the preceed-
ing cycle being complete.)
30 Encoder SYNC SELECT Actuates a Command sync for an input high and Data sync for an
input low.
31 Encoder ENCODER PARITY SELECT Sets transmit parity odd for a high input, even for a low input.
32 Encoder SEND DATA Is an active high output which enables the external source of serial data
33 Encoder SEND CLOCK IN Clock input at a frequency equal to the data rate X2.
34 Encoder ENCODER SHIFT CLOCK Output for shifting data into the Encoder. This shift clock shifts data
on a low-to-high transition.
35 Blank N.C. Not connected.
36 Both COUNT C3 See pin 20.
37 Encoder ENCODER CLOCK Input to the 6:1 divider.
38 Decoder DATA SYNC Output of a high from this pin occurs during output of decoded data
which was preceded by a Data synchronizing character.
39 Both COUNT C4 See pin 20.
40 Both COUNT C, See pin 20.
The Encoder requires a single clock with a frequency of to accept data, the SEND DATA output will go high for
twice the desired data rate applied at the SEND CLOCK K ENCODE R SH I FT CLOCK periods ®.
During these
input. An auxiliary divide by six counter is provided on K periods the data should be clocked into the SER IAL
chip which can be utilized to produce the SEND CLOCK DATA input with every low-to-high transition of the
by dividing the DECODER CLOCK. The frame length is ENCODER SHIFT CLOCK G) - ®.
After the sync and
set by programming the COUNT inputs. Parity is selected Manchester II encoded data are transmitted through the
by programming ENCODER PARITY SELECT high for BIPOLAR ONE and BIPOLAR ZERO outputs, the Encoder
odd parity or low for even parity. adds on an additional bit with is the parity for that word
®. At any time a low on OUTPUT INHIBIT input will
The Encoder's cycle begins when ENCODER ENABLE is force both bipolar outputs to a high state but will not
high during a falling edge of ENCODER SHIFT CLOCK affect the Encoder in any other way.
CD. This cycle lasts for one word length or K + 4 EN-
CODER SHIFT CLOCK periods, where K is the number of To abort the Encoder transmission a positive pulse must
bits to be sent. At the next low-to-high transition of the be applied at MASTER RESET. Any time after or during
ENCODER SHIFT CLOCK, a high at SYNC SELECT this pulse, a low-to-high transition on SEND CLOCK
input actuates a Command sync or a low will produce a clears the internal counters and initializes the Encoder for
Data sync for that word @. When the Encoder is ready a new word.

I ' I ' I' I ' I• I ' I• I' I I ,~ I ,-3 I ,., I '., I ,I I I

Jl]lJlJUUlfUUUl
,rLJ1...lLJU1..
W;w/W///M
,wwu///////////////ffi
I , I~ _

r;IT;IB"TiI;iT;IB'Tl1;;';-~

l~l!
~I!'!!I~:!I!t!!.f~~!.3
I I
<il!l>

To operate the Decoder asynchronously requires a single bits to be received. If the sync character was a data sync
clock with a frequency of 12 times the desired data rate the DATA SYNC output will go high. The TAKE DATA
applied at the DECODER CLOCK input. To operate the output will go high and remain high (2) - @ while the
Decoder synchronously requires a SYNCH RONOUS Decoder is transmitting the decoded data through SERIAL
CLOCK at a frequency 2 times the data rate which is DATA OUT. The decoded data available at SERIAL
synchronized with the data at every high-to-Iow transition DATA OUT is in NRZ format. The DECODER SHIFT
applied to the SYNCHRONOUS DATA input. The Man- CLOCK is provided so that the decoded bits can get shifted
chester II coded data can be presented to the Decoder into an external register on every low-to-high transition of
asynchronously in one of two ways. The BIPOLAR ONE this clock ®-@.
and BIPOLAR ZERO inputs will accept data from a com-
parator sensed transformer coupled bus as specified in After all K decoded bits have been transmitted @ the
Military Spec 1553. The UNIPOLAR DATA input can data is checked for parity. A high input on DECODER
only accept non inverted Manchester II coded data. (e.g. PARITY SELECT will set the Decoder to check for even
from BIPOLAR ZERO OUT on an Encoder). parity or a low input will set the Decoder to check for odd
parity. A high on VALID WORD output ®
indicates
The Decoder is free running and continuously monitors its a successful reception of a word without any Manchester
data input lines for a valid sync character and two valid or parity errors. At this time the Decoder is looking for
Manchester data bits to start an output cycle. When a valid a new sync character to start another output sequence.
sync is recognized CD ' the type of sync is indicated by a
high level at either COMMAND SYNC or DATA SYNC At any time in the above sequence a high input on DE-
output. If the sync character was a command sync the CODER RESET during a low-to-high transition of DE-
COMMAND SYNC output will go high ®and remain high CODER SHIFT CLOCK will abort transmission and initial-
for K SH I FT CLOCK periods G), where K is the number of ize the Decoder to start looking for a new sync character.
5-14
 I ' I ' I' I ' I• I' I • I' I • I I I I I I
N-> N·' N-' N I I I
'l..rLruUUUUl.1
~

__________
~I ~~-----------------
L-
_________
~I ~ :m.m__m. L-

""ALD'''DU' W'&4!i"B'h'f)0@"43 MOO la'''·'F''''+''3: : 1.".1""I "" I"" I"" ~4

(ffllOM"RIVIOUlfltClI'TIOHI _I r--
11 ~~

FRAME PIN WORD

DATA LENGTH
BITS (BIT PERIODS) C. C3 C2 C, Co

2
3 •
7
L
L
L
L
H
H
L
H
H
L
•• 8
•
L
L
L
H
H
L
H
L
H
L
• '0 L H L L H

,.,.,.
7 L H L H L
8 "
'2 L H L H H
•
'0
'3 L
L
H
H
H
H
L
L
L
H
L H H H L
"
,.
,.
'2
'3

,.
17

,.
'8
L
H
H
H
H
L
L
L
H
L
L
L
H
L
L
H
H
L
H
L

,.
17
'8

20
2'
20
2'
22
23
2'
2.
H
H
H
H
H
H
L
L
L
L
L
H
L
H
H
H
H
L
H
L
L
H
H
L
H
L
H
L
H
L
22 2. H H L L H
23 27 H H L H L
2' 28 H H L H H
2. 2. H H H L L
2. 30 H H H L H
27 3' H H H H L
28 32 H H H H H

The above Table demonstrates all possible combinations of frame lengths ranging from 6 to 32 bits. The pin word
described here is common to both the Encoder and Decoder.

SEND CLOCk --1 ~TE1 I

'NCOO'.8H'FTCLDCK --.J ---I~,.I I I
ENCODER ENABLE ~~~~~ '-T( TEe

SVNCSELECT ~~ VALID

TE7

SEND DATA
nld X__t=- -_-_-:.-:.-:.-:.-:.-:.-:.-:.-:.-:.-:.-:.-:.-:.-:
SEND CLOCK

8~~u:r;:::::::::::::::::::::::::::::::::::_-----~
 8lPOlARONElN 1Dl::WA ; F=TD~ ~
~ ~f--TD3' --l~~D3
BlPOlARlEROIN~~ ; I=TD
r--TD4 I TOS I TD5 .1 TD4---1

UNIPOLAR IN ::1------To'
I COMMAND SYNC

UNIPOLAR IN J~; -----TO'

DATA SYNC

UNIPOLA' oN ~- To< ~: TD4==L..-

ON'

DECODER SHIFT CLOCK ---, I L-.

COMMANO/DATASYNC ~ _

TAtcEDATA ~_I----------------

DECODERSHIFTClOCtc ----, __ -- " L-

SERIAL DATA OUT ~
TD8--t Ii""=-----------_
~X:::
DECODER SHIFT CLOCK ---,
T""-.-__
------
COMMAND/i5A'fA SYNC -~-.'-0=l-'--"f-----------------
TAKE DATA ~ _

TO"'* L-
__
 ENCODER TIMING
Jl T"1-

~~:
=~::8--~TI~-i~--~;i-;-;.Jfr~;; ~

____ L , _
~
mJ HARRIS CMOS Programmable
HD-15531B
Preliminary Manchester Encoder -Decoder

Vcc 1 ~
~ 40 COUNT Cl
VALID WORD 2 39 COUNT c.
• 2.5 MEGABIT/SEC DATA RATE

·•
TAKE DATA' 3 38 DATA SYNC
TAKE DATA 37 ENCOOER CLOCK
• SYNC IDENTIFICATION AND LOCK-IN SERI .•••L DATA DUT 5 38 COUNT C3

• CLOCK RECOVERY
SYNCHRONOUS
SYNCHRONOUS DATA
DATA
SEL. 7 ,." N.C.
ENCODER SHIFT CLOCK

•
•
VARIABLE FRAME LENGTH TO 32 BITS
MANCHESTER II ENCODE AND DECODE
SYNCHRONOUS
DECODeR
SYNCHRONOUS CLOCK SEI..
CLOCK
CLOCK
,.
•• 33
32
31
SEND
SEND
ENCODER
CLOCK
DATA
IN

PARITY SEI..

• HALF OR FULL DUPLEX OPERATION

BIPOLAR ZERO
BIPOLAR ONE IN
IN
"
12
3.

'"
SYNC
ENCODER
seLECT
ENABLE

• FULL MILITARY OR INDUSTRIAL TEMPERATURE UNIPOLAR DATA IN

,.
13 2. SERIAL DATA IN
RANGES DECODER SHIFT
TRANSITION
CLOCK
SE\,.
,." 37
26
ii1S&n m lro'
0U'fPlj'j'iN'HTii'i'f

,.
N.C. iiPOLAA ZERO OUT
• WORD TYPE SELECT AND RECOGNITION
COMMAND SYNC 17 ,." +80UT
• DETECTS ALL SINGLE, DOUBLE, OR TRIPLE DECODER PARITY SEL. 23 COUNT C2
SAMPLING ERRORS DeCODER
COUNT
RESET
Co "
20
22
21
MASTER
OND
RESET

The Harris H D-15531 B Programmable Manchester of synchronization characters and a parity bit.
Encoder-Decoder (MED) is intended to be used as a Independent selection of even or odd parity for the
high speed, low power, serial data link controller in encoder and decoder is included.
applications where data integrity combined with low
overhead is important. It is manufactured using An internal error detection algorithm will detect all
Harris' Self Aligned Junction Isolated (SAJI) CMOS single, double or triple sampling errors. In addition,
process. this algorithm will typically detect better than 99%
of four or more errors in anyone word.
This LSI chip is divided into two sections. an encoder
and a decoder. These sections operate independently Ideal applications include party line Local Area
of each other except for the Master Reset and frame Networks as well as data acquisition systems where
length select function. In addition to encodingl 8, 12 or 16 bit AID converters are typically used for
decoding of NRZ data the HD-15531B frames the digital transmission of data.
variable length data (2-2B bits) with one of two types

UNIPOLAR
DATA IN TAitE DATA
BIPOLAR COMMAND
ONE IN SYNC
BIPOLAR DATA$YNC
ZEROIH

DECODE A
CLOCK
TRANSITION
SELECT
SYNCHRONOUS
CLOCK
SYNCHRONOUS 10
CLOCK SELECT
SYNC MASTER
SELECT RESET
ENCODER ENCODER ENCODER
SHIFT ENABLE PARITY
CLOCK SElEeT
 Supply Voltage +7.0V
Input or Output Voltage Applied GND -O.3V to VCC +O.3V
Storage Temperature Range -650C to +1500C
Operating Temperature Range
Industrial HD-15531B-9 -400C to +850C
Military HD-15531B-2/8 -550C to + 1250C

SYMBOL PARAMETER MINIMUM TYPICAL MAXIMUM UNITS TEST CONDITIONS

VIH Logical "1" Input Voltage 70% VCC V

VIL Logical "0" Input Voltage 20% VCC V
VIHC Logical "1" Input Voltage (Clock) VCC -0.5 V
VILC Logical "0" Input Voltage (Clock) GND +0.5 V
IlL Input Leakage -1.0 +1.0 J.l.A OV'" VIN '" VCC
VOH Logical "1" Output Voltage 2.4 V IOH = -3m A
VOL Logical "0" Output Voltage 0.4 V IOL = 1.8mA
ICCSB Supply Current Standby 0.5 2.0 mA VIN = VCC = 5.5V
Outputs Open
ICCOp Supply Current Operating- 16.0 20.0 mA VCC ~ 5.5V
f =30MHz
CIN Input Capacitance· 5.0 7.0 pF
Co Output Capacitance· 8.0 10.0 pF
-Guaranteed and sampled but not 100% tested.

ENCODER TIMING

FEC Encoder Clock Frequency 0 30 MHz CL = 50pF

FESC Send Clock Frequency 0 5 MHz
TECR Encoder Clock Rise Time 8 ns
TECF Encoder Clock Fall Time 8 ns
FED Data Rate 0 2.5 MHz
TMR Master Reset Pulse Width 150 ns
TE1 Sh ift Clock Delay 80 ns
TE2 Serial Data Setup 50 ns
TE3 Serial Data Hold 50 ns
TE4 Enable Setup SO ns
TE5 Enable Pulse Width 100 ns
TE6 Sync Setup 55 ns
TE7 Sync Pulse Width 150 ns
TE8 Send Data Delay 0 50 ns
TES Bipolar Output Delay 130 ns
DECODER TIMING

FDC Decoder Clock Frequency 0 30 MHz CL = 50pF

FDS Decoder Synchronous Clock 0 5 MHz
TDCR Decoder Clock Rise Time 8 ns
TDCF Decoder Clock Fall Time 8 ns
FDD Data Rate 0 2.5 MHz
TDR Decoder Reset Pulse Width 150 ns
TDRS Decoder Reset Setup Time 75 ns
TMR Master Reset Pulse Width 150 ns
TD1 Bipolar Data Pulse Width TDC +10 ns
TD2 Sync Transition Span 18TDC ns
TD3 One Zero Overlap TDC -10 ns
TD4 Short Data Transition Span 6TDC ns
TD5
TD6
Long Data Transition Span
Sync Delay (ON) -20
12TDC
110
ns
ns
~
TD7 Take Data Delay (ON) 0 110 ns
TD8 Serial Data Out Delay 80 ns
TDS Sync Delay (OFF) 0 110 ns
TD10 Take Data Delay (OFF) 0 110 ns
TD11 Valid Word Delay 0 110 ns
'TD12 Synchronous Clock To Shift Clock Delay 75 ns
TD13 Synchronous Data Setup 75 ns
TDC = Decodor Clock Period =Fi5c
NOTEQ) :
These parameters are guaranteed but not 100% tested.
PIN SECTION NAME DESCRIPTION

1 Both VCC Positive supply pin.

2 Decoder VALID WORD Output high indicates receipt of a valid word.

3 Decoder TAKE DATA' A continuous, free running signal provided for host timing or data
handling. When data is present on the bus, this signal will be
synchronized to the incoming data and will be identical to take data.

4 Decoder TAKE DATA Output is high during receipt of data after identification of a sync pulse
5 Decoder SERIAL DATA OUT Delivers received data in correct NRZ format.
6 Decoder SYNCHRONOUS DATA Input presents Manchester data directly to character identification
logic. SYNCHRONOUS DATA SELECT must be held high to use
this input. If not used this pin should be held high.
7 Decoder SYNCHRONOUS DATA SELECT In high state allows the synchronous data to enter the character identi-
fication logic.
Input provides externally synchronized clock to the decoder.
8 Decoder SYNCHRONOUS CLOCK
This input should be tied high when not in use.
9 Decoder DECODER CLOCK Input drives the transition finder, and the synchronizer which in
turn supplies the clock to the balance of the decoder.
10 Decoder SYNCHRONOUS CLOCK SELECT In high state directs the SYNCHRONOUS CLOCK to control the decoder
character identification logic. A low state selects the DECODER CLOCK
11 Decoder BIPOLAR ZERO IN A high input should be applied when the bus is in its negative state.
This pin must be held high when the unipolar input is used.
12 Decoder 81POLAR ONE IN A high input should be applied when the bus is in its positive state.
This pin must be held low when the unipolar input is used.
13 Decoder UNIPOLAR DATA IN With pin 11 high and pin 12 low, this pin enters unipolar data into
the transition finder circuit. If not used this input must be held low.
14 Decoder DECODER SHIFT CLOCK Output which delivers a frequency (DECODER CLOCK -;- 12),
synchronized by the recovered serial data stream.
15 Decoder TRANSITION SELECT A high input to this pin causes the transition finder to synchronize on
every transition of input data. A low input causes the transition finder
to synchronize only on mid-bit transitions.
16 Blank N.C. Not connected.
17 Decoder COMMAND SYNC Output of a high from this pin occurs during output of decoded data
which was preceded by a Command (or Status) synchronizing character
18 Decoder DECODER PARITY SELECT An input for parity sense, calling for even parity with input high and
odd parity with input low.
19 Decoder DECODER RESET A high input to this pin during a rising edge of DECODER SHIFT
CLOCK resets the decoder bit counting logic to a condition ready
for a new word.
20 Both COUNT Co One of five binary inputs which establish the total bit count to be
encoded or decoded.
21 Both GROUND Supply pin.
22 Both MASTER RESET A high on this pin clears 2: 1 counters in both the encoder and decoder.
23 Both COUNT C2 See pin 20.
24 Encoder 6 OUT Output from 6: 1 divider which is driven by the ENCODER CLOCK.
25 Encoder BIPOLAR ZERO OUT An active low output designed to drive the zero or negative sense of
a bipolar line driver.
26 Encoder
------
OUTPUT
INHIBIT A Iowan this pin forces pin 25 and 27 high, the inactive states.
27 Encoder BIPOLAR ONE OUT An active low output designed to drive the one or positive sense of
a bipolar line driver.
28 Encoder SERIAL DATA IN Accepts a serial data stream at a data rate equal to ENCODER SHIFT
CLOCK.
29 Encoder ENCODER ENABLE A high on this pin initiates the encode cycle. (Subject to the preceed-
ing cycle being complete.l
30 Encoder SYNC SELECT Actuates a Command sync for an input high and Data sync for an
input low.
31 Encoder ENCODER PARITY SELECT Sets transmit parity odd for a high input, even for a low input.
32 Encoder SEND DATA Is an active high output which enables the external source of serial data
33 Encoder SEND CLOCK IN Clock input at a frequency equal to the data rate X2.
34 Encoder ENCODER SHIFT CLOCK Output for shifting data into the Encoder. This shift clock shifts data
on a low-to-high transition.
35 Blank N.C. Not connected.
36 Both COUNT C3 See pin 20.
37 Encoder ENCODER CLOCK I nput to the 6: 1 divider.
38 Decoder DATA SYNC Output of a high from this pin occurs during output of decoded data
which was preceded by a Data synchronizing character.
39 Both COUNT C4 See pin 20.
40 Both COUNT C1 See pin 20.
The Encoder requires a single clock with a frequency of to accept data, the SEND DATA output will go high for
twice the desired data rate applied at the SEND CLOCK K ENCODER SHIFT CLOCK periods @. During these
input. An auxiliary divide by six counter is provided on K periods the data should be clocked into the SERIAL
chip which can be utilized to produce the SEND CLOCK DATA input with every low-to-high transition of the
by dividing the DECODER CLOCK. The frame length is ENCODER SH I FT CLOCK @ - @. After the sync and
set by programming the COUNT inputs. Parity is selected Manchester II encoded data are transmitted through the
by programming ENCODER PARITY SELECT high for BIPOLAR ONE and BIPOLAR ZERO outputs, the Encoder
odd parity or low for even parity. adds on an additional bit with is the parity for that word
®. At any time a low on OUTPUT INHIBIT input will
The Encoder's cycle begins when ENCODER ENABLE is force both bipolar outputs to a high state but will not
high during a falling edge of ENCODER SH I FT CLOCK affect the Encoder in any other way.
CD. This cycle lasts for one word length or K + 4 EN-
CODER SHI FT CLOCK periods, where K is the number of To abort the Encoder transmission a positive pulse must
bits to be sent. At the next low-to-high transition of the be applied at MASTER RESET. Any time after or during
ENCODER SHIFT CLOCK, a high at SYNC SELECT this pulse, a low-to-high transition on SEND CLOCK
input actuates a Command sync or a low will produce a clears the internal counters and initializes the Encoder for
Data sync for that word @. When the Encoder is ready a new word.

".'.G I I ' I ' I ' I ' I • I • I• I ' I I .~ I •., I •., I •., I • I I I

JlJUlJlM[lJlJU1
ENCODEAIHIFTCLOCK ~

'.000" ••••" ~ ~'-LL='-LL='-LL~<.L<.L.L<..L<.L.LL<U'LL.< ~A1

"",m,,,W~vAuo~~4DGr''''I00000/~ ~M
I J I.

riIT~J-;IT;I;;~2I;;;:~}~~;-~

d
1!1! ~I.~I! ~f~~~~
~'~d~'!
I I
<!)<!l

To operate the Decoder asynchronously requires a single bits to be received. If the sync character was a data sync
clock with a frequency of 12 times the desired data rate the DATA SYNC output will go high. The TAKE DATA
applied at the DECODER CLOCK input. To operate the output will go high and remain high @ - @ while the
Decoder synchronously requires a SYNCH RONOUS Decoder is transmitting the decoded data through SE RIAL
CLOCK at a frequency 2 times the data rate which is DATA OUT. The decoded data available at SERIAL
synchronized with the data at every high-to-Iow transition DATA OUT is in NRZ format. The DECODER SHIFT
applied to the SYNCHRONOUS DATA input. The Man- CLOCK is provided so that the decoded bits can get shifted
chester II coded data can be presented to the Decoder into an external register on every low-to-high transition of
asynchronously in one of two ways. The BIPOLAR ONE this clock @-@.
and BIPOLAR ZERO inputs will accept data from a com-
parator sensed transformer coupled bus as specified in After all K decoded bits have been transmitted @ the
Military Spec 1553. The UNIPOLAR DATA input can data is checked for parity. A high input on DECODER
only accept noninverted Manchester II coded data. (e.g. PAR ITY SELECT will set the Decoder to check for even
from BIPOLAR ZERO OUT on an Encoder). parity or a low input will set the Decoder to check for odd
parity. A high on VALID WORD output @ indicates
The Decoder is free running and continuously monitors its a successful reception of a word without any Manchester
data input lines for a valid sync character and two valid or parity errors. At this time the Decoder is looking for
Manchester data bits to start an output cycle. When a valid a new sync character to start another output sequence.
sync is recognized CD ' the type of sync is indicated by a
high level at either COMMAND SYNC or DATA SYNC At any time in the above sequence a high input on DE-
output. If the sync character was a command sync the CODER RESET during a low-to-high transition of DE-
COMMAND SYNC output will go high @and remain high CODER SHIFT CLOCK will abort transmission and initial-
for K SH I FT CLOCK periods@, where K is the number of ize the Decoder to start looking for a new sync character.
 I• I ' I ' I' I• I• I• I' I• I I N-'I N_'I N-'I N I I I I
'U1JlJ1MMJU1JUU
~

COMMAND ''I'NC l ~ :. nn.L--

__________ I ~~-----------uu- _.._.L--
"""DATAOU' @WMi{Nfrh9Wff& ••• 1"H-,~"'·+"'·3:: 1.".1 "" I "" I "" I OIl' WWA
l'IIlOM'llllV.OU.fl'CI'TIOHI ~I r--
1~ 1~

FRAME PIN WORD

DATA LENGTH
BITS (BIT PERIODS) C. C3 C2 Cl Co

2 6 L L H L H
3 7 L L H H L
••
6
••
10
L
L
L
L
H
H
H
L
L
H
L
L
H
L
H
7 11 L H L H L

•• ,.
12 L H L H H
'3 L H H L L
10 L H H L H
"
,.I.
11 L H H H L

,.
12
13
16
17
L
H
H
H
L
L
H
L
L
H
L
L
H
L
H

,.I.
"
16
17

20
20
21
22
23
2'
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
L
L
H
H
L
H
L
H
L
H
2' 2. H H L L L
22 26 H H L L H
23 27 H H L H L
2' 2. H H L H H
2. 2. H H H L L
2. 30 H H H L H
27 3' H H H H L
2. 32 H H H H H

The above Table demonstrates all possible combinations of frame lengths ranging from 6 to 32 bits. The pin word
described here is common to both the Encoder and Decoder.

SIND CLOCK ------1 ~T'1 I

.NCOO••••• "'OLOC. --.J ------I~
•• I II
INCODU tNAILI TlB I
IVNCIILICT "Z"'U"'''I'''''I'''''I'''2'''%'''%'''~'''''I'''''I'''~'''%'''%'''%'''~ VALID

fI'

INCDDI" IHIIIT CLOCIC --.J

.IND DATA 'lid E~:::::::::::::_-_-_-_-_-_-_
'INOCLOCI(~fI'
I"l'JlSt:Ul506tWo, -----~-
Imlrn Rlllllltl'l' ------- -------
 Non: UNIPOLAR IN. 0, 'OR NUT CIAaRAMI

IIPOLARONEIN

lll"OLAAZEROIN
-t
r
~8IT'IR'OD
TD1 =rtVPfl2'llYAff4Z?Z?'l1\::
TDz-----j:TD~ffi~
I BtHIRIOD I IIHIRIOO----f

F
: : I TD' I

. , : :
""'''''DH.,N : : ~Dl~~
BIPOLAR ZIRO IN ]Jro1;yazr.aZiz,ynnvd/ TD3
i T03

: : I . TD' I
OATA'YHC

i i:
.II'OLARONEIN~l : ~;:V/Z'lZ~ ~
Ill'OLARZEROIN I-TD~~T03 J ~TD3

I--TOo4 T06 ~ T06 TD4~

aNI ZERO aNI

Non: 1l1,,?LAR ONE IN· 0; BlPOLA" ZERO IN· " fOR NEXT DIAGRAMS.

UNIPOLAR IN J~:.-----T02 . T02

, COMMAND SYNC

UNIPOLAR IN J~;-----TD2----~------TD' rwu/4

DAT .•.• VNC

UNll'OLAlIIlN ~,~ T04-----TDt--~----TDt

~'" TD4=L
ONE I ZERO ONE ONE

D'CDD" "'''TC'o<'

COMMANDJISAll.IVNC

TAKI DATA
~

::1~--------------------
--l-1
I L-

D.CDD
••••• "TC'o<. ~ L-
I.'UAL DATA OUT ~ DATA liT :::x::
DICODU: SHifT CLOCK -----,
->--------~
TDt.•.•
COMMANDfl5Xn: SYNC ~

TAKE DATA ~~~_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-=

DICODIIIlIHI,rCLOCK --,~ ~ L-
DICODER RlllT TD_R.~ _
 ____ L .. . .. I _
~

The following is a partial listing of technical articles that have been published which discuss Harris Semi-
conductors line of Manchester Encoder-Decoders.

Additional literature is available from Harris in the form of Technical Briefs (TB-15, 20, 28, 29,43) and
Article Reprints of published articles.
m HARRIS
CMOS Asynchronous Serial
HD-6408
Manchester Adapter (ASMA)

Pinout TOP VIEW

vw 2' VCC
• LOW BIT ERROR RATE ESC 23 EC
• ONE MEGABIT/SEC OATA RATE TO 22 SC,
SOD 21 SO
• SYNC IDENTIFICATION ANO LOCK-IN
DC 20 55
• CLOCK RECOVERY BZ' EE

• MANCHESTER II ENCODE,DECODE eo, "18 SO,

UD' 17 BOO
• SEPARATE ENCODE AND DECODE
DSC 16 6i
• LOW OPERATING POWER: 50mWAT 5 VOLTS CDS 15 BZD
DR DBS
• SINGLE POWER SUPPL Y
GND "
13 MR
• 24 PIN PACKAGE

The H0-6408 is a CMOS/LSI Manchester Encoder/ signal. Th is Decoder puts the Manchester code to
Decoder for creating a very high speed asynchronous full use to provide clock recovery and excellent
serial data bus. The Encoder converts serial N RZ noise immunity at these very high speeds.
data (typically from a shift register) to Manchester II
encoded data adding a sync pulse and parity bit. The HD-6408 can be used in many commercial
The Decoder recognizes this sync pulse and identifies applications such as, security systems, environmental
it as a Command Sync or a Data Sync. The data is control systems, serial data links and many others.
then decoded and shifted out in the N RZ code It utilizes a single 12X clock and achieves data rates
(typically into a shift register). Finally, the parity of up to one million bits per second with a very
bit is checked. If there were no Manchester or minimum overhead of only 4 bits out of 20, leaving
parity errors the Decoder responds with a valid word 16 bits for data.

16 Oi
800 eOI

UOI

CAUTION: These devices are sensitive to electronic discharge.

Proper I.C. handling procedures should be followed.
 Supply Voltage +7.0V

Input or Output Voltage Applied GND -O.3V to VCC +O.3V

Storage Temperature Range -650C to +1500C

Operating Temperature Range -400C to +850C

SYMBOL PARAMETER MINIMUM TYPICAL MAXIMUM UNITS TEST CONDITIONS

VIH Logical "1" Input Voltage 70% VCC V

VIL Logicel "0" Input Voltaga 20% VCC V
VIHC Logicel "1" Input Voltage (Clock) VCC -0.5 V
VILC Logice' "0" Input Voltage (Clock) GNO +0.5 V
ilL Input Leakage -1.0 +1.0 IJ.A OV ~ VIN ~ VCC
VOH Logical "1" Output Voltaga 2.4 V IOH --3mA
VOL Logical "0" Output Voltage 0.4 V IOL -l.BmA
ICCSB Supply Current Standby 0.5 2 mA VIN - VCC - 5.5V
Outputs Open
ICCOP Supply Current Operating· B.O 10.0 mA VCC - 5.5V.
f -lMHz
CIN Input Capacitance- 5.0 7.0 pF
Co Output Capacitance- B.O 10.0 pF

·Guaranteed and sampled but not 100% tested.

ENCODER TIMING VCC = 5.0V 15% TA = -400C to +850C

FEC Encoder Clock Frequency 0 12 MHz CL = 50pF

FESC Send Clock Frequency 0 2.0 MHz
TECR Encoder Clock Rise Time B ns
TECF Encoder Clock Fall Time B ns
FED Data Rate 0 1.0 MHz
TMR Master Reset Pulse Width 150 ns
TEl Sh ift Clock Oeley 125 ns
TE2 Serial Data Setup 75 ns
TE3 Serial Data Hold 75 ns
TE4 Enable Setup 90 ns
TE5 Enable Pulse Width 100 ns
TE6 Sync Setup 55 ns
TE7 Sync Pulse Width 150 ns
TEB Send Data Delay 0 50 ns
TE9 Bipolar Output Delay 130 ns

DECODER TIMING VCC = 5.0V 15% TA = -400C to +850C

FOC Decoder Clock Frequency 0 12 MHz CL = 50pF

TOCR Decoder Clock Rise Time B ns
TOCF Decoder Clock Fall Time B ns
FOO Data Rate 0 1.0 MHz
TOR Decoder Reset Pulse Width 150 ns
TORS Decoder Reset Setup Time 75 ns
TMR Master Reset Pulse Width 150 ns
TOl Bipolar Data Pulse Width TOC +10 ns (l)
T02 Sync Transition Span lBTOC ns CD
T03 One Zero Overlap TOC -10 ns CD
T04 Short Data Transition Span 6TOC ns CD
T05 Long Data Transition Span 12TOC ns (l)
T06 Sync Oeiay (ON) -20 110 ns
T07 Take Oeta Delay (ON) 0 110 ns
TOB Serial Data Out Delay BO ns
T09 Sync Delay (OFF) 0 110 ns
T010 Take Data Delay (OFF) 0 110 ns
T011 Valid Word Delay 0 110 ns

NOTE CD : TOC = Decoder Clock Period = ~OC

These parameters are guaranteed but not 100% tested.
PIN SYMBOL SECTION OESCRIPTION

1 VW Decoder Output high Indlcatas receipt of a VALID WORD.

2 ESC Encoder ENCODER SHIFT CLOCK Is an output for shifting data

Into the Encoder. This clock shifts data on a low-to-nlgh
transition.
3 TO Decoder TAKE DATA output Is high during receipt of data after
Identification of a sync pulse.
4 SDO Decodar SERIAL DATA OUT delivers recalved data In correct NRZ
format.
5 DC Decoder DECODER CLOCK Input drives the transition finder, and the
synchronizer which In turn supplies the clock to the balance
of the Decoder.
6 BZI Decodar A high Input should be applied to BIPOLAR ZERO IN when
the bus Is In Its nagatlve state. This pin must be held high
when the Unipolar input is used.
7 BOI Decodar A high input should be applied to BIPOLAR ONE IN when
the bus is in Its positive state, this pin must be hald low when
tha Unipolar input is used.
8 UDI Decoder With pin 6 high and pin 7 low, this pin entars UNIPOLAR
DATA IN to the transition findar circuit. If not used this
Input must be held low.
9 DSC Decoder DECODER SHIFT CLOCK output dallvers a frequency
(DECODER CLOCK +
12), synchronized by the racovered
serial data stream.
10 CDS Decoder COMMAND/DATA SYNC output high occurs during output of
dacoded data wh ich was preceded by a Command synchron-
izing character. A low output indicates a Data synchronizing
character.
11 DR Decoder A high input to DECODER RESET during a rising edge of
DECODER SHIFT CLOCK resets tha decoder bit counting
logic to a condition ready for 8 new word.
12 GND Both GROUND supply pin.

PIN SYMBOL SECTION DESCRIPTION

13 MR Both A high on MASTER RESET clears the 2: 1 countars In both

the encoder and decoder and the 12 counter. +
14 DBS Encoder DIVIDE BY SIX Is an output from 6: 1 divider which is driven
by the ENCODER CLOCK.
15 BZO Encoder BIPOLAR ZERO OUT is an active low output designad to
drive the zero or negative sense of a bipolar line driver.
16 15i Encoder A low on OUTPUT INHIBIT forcas pin 15 and 17 high,
their inactive states,
17 BOO Encoder EiTP5IA'R ON E OUT is an active low output designed to
drive the one or positive S8nse of a bipolar line driver.
18 SOl Encoder SERIAL DATA IN accepts a serial data stream at a data
rata equal to ENCODER SHIFT CLOCK.
19 EE Encoder A high on ENCODER ENABLE initiates the encode cycla.
(Subject to the preceding cycle being complete.)
20 SS Encoder SYNC SE LECT actuates a Command sync for an input high
and Data sync for an input iow.
21 SO Encoder SEND DATA is an active high output which enables the
external source of serial data.
22 SCI Encoder SEND CLOCK IN is 2X the Encodar data rate.
23 EC Encoder ENCODER CLOCK is the input to the 6:1 divider.
24 VCC Both Positive supply pin.
The Encoder requires a single clock with a frequency of During these sixteen periods the data should be clocked
twice the desired data rate applied at the SClock input. An into the SDlnput with every high-to-Iow transition of the
auxiliary divide by six counter is provided on chip which ESC @ - @). After the sync and Manches~1 encoded
can be utilized to produce the SClock by dividing the data are transmitted through the BOO and BZO outputs,
DClock. the Encoder adds on an additional bit which is the (odd)
parity for that word ® .
At any time a low on Oi will
The Encoder's cycle begins when EE is high during a falling force both bipolar outputs to a high state but will not
edge of ESC CD. This cycle lasts for one word length or affect the Encoder in any other way.
twenty ESC periods. At the next low-to-high transition of
the ESC, a high at SS input actuates a Command sync To abort the Encoder transmission a positive pulse must
or a low will produce a Data sync for that word When 0. be applied at MR. Any time after or during this pulse,
the Encoder is ready to accept data, the SD output will go a low-to-high transition on SCI clears the internal counters
high and remain high for sixteen ESC periods @ - @) . an initializes the Encoder for a new word.

TIMING I 0 I 1 I ' I 3 I• I 5 I• I 7 I I 15 I 15 I " I 18 I "1 I I

SCI {l.fl.IlIlI1.fi
Ese ~

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ss ?/7///AVAlIDt////ZI//////ZOGN'T CAR'27m/lffi/~ W//I///ffi//l/l/ m/lllZll/ll7/h
I f

: 3 I , I ' I 0 I
~PT2T'To-rpI
~_d_!.I_,-L.2_1-,_J
U

The Decoder requires a single clock with a frequency of The decoded data available at SDO is in a N RZ format.
12 times the desired data rate applied at the DClock input. The DSC is provided so that the decoded bits can get
The Manchester II coded data can be presented to the shifted into an external register on every low-to-high
Decoder in one of two ways. The BOI and BZI inputs transition for this clock 0
-@.
will accept data from a differential output comparator.
The UDI input can only accept non inverted Manchester II After all sixteen decoded bits have been transmitted@the
coded data (e.g. from BZO of an Encoder), data is checked for odd parity. A high on VW output @
indicates a successful reception of a word without any
The Decoder is free running and continuously monitors Manchester or parity errors. At this time the Decoder is
its data input lines for a valid sync character and two valid looking for a new sync character to start another output
Manchester data bits to start an output cycle. When a sequence.
valid sync is recognized CD '
the type of sync is indicated
by the CDS output. If the sync character was a command, At any time in the above sequence a high input on DR
this output will go high @ and remain high for sixteen during a low-to-high transition of DSC will abort trans-
DSC periods @ , otherwise it will remain low. The TD mission and initialize the Decoder to start looking for
output will go high and remain high 0-
@ while the a new sync character.
Decoder is transmitting the decoded data through SDO.
 I 0 I ' I 2 I 3 I• I 5 I • I 7 I • I I" I " I ,. I ,. I I I I
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NOTE: Ul- O. FOR NEXT DIAGRAMS

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I I I T02 I TO ~~---------------------------

COMMAND SYNC

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I NOTE: 801" 0; Bll" 1 FOR NEXT DIAGRAMSI TORS=Ri=~ -_-_-_-_-_-_-_-_-_-_-_-r-
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m HARRIS HD-6409
CMOS Manchester
Encoder-Decoder (MED)

Pinout
• CONVERTER OR REPEATER MOOE TOP VIEW

• INOEPENOENT MANCHESTER ENCODER AND DECODER OPERATION

BZI VCC
• STATIC TO ONE MEGABIT/SEC DATA RATE GUARANTEED
BOI BOO
• LOW BIT ERROR RATE
UDI BZO
• DIGITAL PLL CLOCK RECOVERY
SO/CDS SS
• ON CHIP OSCILLATOR
SDO ECLK
• SINGLE POWER SUPPLY
SRST CTS
• LOW OPERATING POWER: 50mWAT5VOLTS
NVM MS
• INDUSTRIAL OR MILITARY TEMPERATURE RANGE
DCLK Ox
• 20 PIN PACKAGE
RST Ix
Description GND Co
The HD-6409 Manchester Encoder-Decoder (MED) is a high speed, low
power device manufactured using self-aligned silicon gate technology. The
device is intended for use in serial data communication, and can be oper- Logic Symbol
ated in either of two modes. In the converter mode, the MED converts
Nonreturn-to-Zero code (NRZ) into Manchester code and decodes Man-
chester code into Nonreturn-to-Zero code. For serial data communica- ss Ox
tion, Manchester code does not have some of the deficiencies inherent Co Ix
in Nonreturn-to-Zero code. For instance, use of the MED on a serial
line eliminates DC components, provides clock recovery, and gives a SO-CDS BOO
relatively high degree of noise immunity. Because the MED converts the ECLK BZO
most commonly used code (N RZ) to Manchester code, the advantages of m
using Manchester code are easily realized in a serial data link.
MS
In the Repeater mode, the MED accepts Manchester code input and RST
reconstructs it with a recovered clock. This minimizes the effects of
noise on a serial data link. A digital phase lock loop generates the recov- 500 BOI
ered clock. A maximum data rate of 1MHz requires only 50mW of power. DCLK BZI
Manchester code is used in magnetic tape recording and in fiber optic Ni7M UDI
communication, and generally is used where data accuracy is imperative.
Because it frames blocks of data, the HD-6409 easily interfaces to proto- SRST DECODER
col controllers.
 Used in conjunction with pin 2, Bipolar One Input (BOil, to
input Manchester II encoded data to the decoder. BZI and
BOI are logical complements. When using pin 3, Unipolar
Data Input (UDl)for data input, BZI must be held high.

Used in conjunction with pin 1, Bipolar Zero Input (BZI). to

input Manchester II encoded data to the decoder. BOI and
BZI are logical complements. When using pin 3, Unipolar Data
Input (UDI) for data input, BOI must be held low.

An alternate to bipolar input (BZI, BOI). Unipolar Data Input

(U D I) is used to input Manchester II encoded data to the
decoder. When using pin 1 (BZI) and pin 2 (BOI) for data
input, UDI must be held low.

SD/CDS Serial Data/Command In the converter mode, SD/CDS is an input used to receive
Data Sync serial N RZ data. N RZ data is accepted synchronously on
the falling edge of encoder clock output (ECLK). In the re-
peater mode, SD/CDS is an output indicating the status of
last valid sync pattern received. A high indicates a command
sync and a low indicates a data sync pattern.

The decoded serial NRZ data is transmitted out synchronous-

ly with the decoder clock (DCLK). SDO is forced low when
RST is low.

In the converter mode, SRS'i' follows~. In the repeater

mode, when RSi goes low, ~ goes low and remains low
after RST goes high. SRST goes high only when RST is high,
the reset bit is zero, and a valid synchronization sequence is
received.

A low on NVM indicates that the decoder has received in-

valid Manchester data and present data on Serial Data Out
(SDO) is invalid. A high indicates that the sync pulse and
data were valid and SDO is valid. NVM is set low by a low
on RST, and remains low after RST goes high until valid
sync pulse followed by two valid Manchester bits is received.

The decoder clock is a 1X clock recovered from BZI and BOI

to synchronously output received N RZ data (SDO).

In the converter mode, a low on RST forces SDO, DCLK,

NVM, and SRST low. A high on RST enables SDO and
DCLK, and forces SRST high. NVM remains tow after RST
goes high until a valid sync pulse ·followed by two Manchester
bits is received, after which it goes high. In the repeater
mode, RST has the same effect on SDO, DCLK and NVM as
in the converter mode. When RST goes low, SRST goes low
and remains low after RST goes high. SRST goes high only
when RST is high, the reset bit is zero and a valid synchron-
ization sequence is received.

(I) - Input
(0) - Output
 PIN MNEMONIC NAME

10 (I) GND Ground

11 (0) Co Clock Output Buffered output of clock input Ix. May be used as clock
signal for other peripherals.

12 (I) Ix Clock Input Ix is the input for an external clock or, if the internal
oscillator is used, Ix and Ox are used for the connection
of the crystal.

13 (I) Ox Clock Drive If the internal oscillator is used, Ox and Ix are used for
the connection of the crystal.

14 (I) MS Mode Select MS must be held low for operation in the converter mode,
and high for operation in the repeater mode.

15 (I) CTS Clear to Send In the converter mode, a high disables the encoder, forcing
outputs BOO, BZO high and ECLK low. A high to low tran-
sition of CTS initiates transmission of a Command sync
pulse. A low on CTS enables BOO, BZO, and ECLK. In the
repeater mode, the function of CTS is identical to that of
the converter mode with the exception that a transition of
CTS does not initiate a synchronization sequence.

In the converter mode, ECLK is a 1X clock output used to

receive serial N RZ data to SO/CDS. In the repeater mode,
ECLK is a 2X clock which is recovered from BZI and BOI
data by the digital phase locked loop.

17 (I) SS Speed Select A logic high on SS sets the data rate at 1/32 times the clock
frequency while a low sets the data rate at 1/16 times the
clock frequency.

18 (0) BZO Bipolar Zero Output BZO and its logical complement BOO are the Manchester
data outputs of the encoder. The inactive state for these
outputs is in the high state.

19 (0) BOO Bipolar One Out

20 (I) VCC VCC

(I) - Input
(0) - Output
 OPERATING RANGE
Supply Voltage +7.0V Operating Temperature Range
Industrial HD-6409-9
Input or Output Voltage Applied GND -O.3V Military HD-6409-2/8
to VCC +O.3V Operating Voltage Range
Industrial HD-6409-9
-650C to +1500C Military HD-6409-2/8

• CAUTION: Sr",••e. ebove thOIB Ii.ted under "Ab.olute Mexlmum Rerlngl" mey cau.e permanenr
demagero the device. Thl. i. e .r", •• only raring end funcr/onal operarion of the devicear the.e or ar any
other condlr/on. above thOle indicated In rhe opererional .ecrion. of rhi•• peclflcer/on i. nor Implied.

TEST
SYMBOL PARAMETER MIN TYPICAL MAX UNITS CONDITIONS

VIH Logic-1 Input Voltage 70% VCC - V

VIL Logic-o Input Voltage 20% VCC V
VIHR Logic-1 Input Voltage (!'<eSOt) vcc -0.5 V
VILR Logic-o Input Voltage (Reset) GND +0.5 V
VIHC Logic-1 Input Voltage (Clock) VCC -0.5 V
VILC Logic-o Input Voltage (Clock) GND +0.5 V
IlL I nput Leakage -1.0 +1.0 J.JA OV<: VIN<:VCC
VOH Logic-1 Output Voltaga VCC -0.4 V 10H =-2.0mA
VOL Logic-o Output Voltage 0.4 V 10L = 2.0mA
ICCO Supply Current Quiescent 1.0 100 J.JA VIN = VCC - 5.5V,
ICCOP Supply Current Operating- 7.0 12.0 mA VCC = 5.5V, fco = 16MHz
CIN Input Capacitance- 6.0 8.0 pF
COUT Output Capacitance- 8.0 15.0 pF

fc Clock Frequency 16 MHz Ix or Xtal

tc Clock Period 1/Ic s
t1 Bipolar Pulse Width tc -10 ns
t2 Sync Transition Span 1.5 x CR x tc <Dl2> ns
t3 One-Zero Overlap tc -10 ns
t4 Short Oat8 Transition Span 0.5 x CR x tc <D0 ns
t5 Long Data Transition Span CR x tc ns
t6 Output Rise & Fall Time 50 ns CL - 20pF for Co,
Clock Out Co Rise & Fall Time 1/(5 x fel s 50pF Otherwise
t7 Input Rise & Fall Time 1/(5 x fel s 50ns Max.
t8 Clock High Duty Cycle 20 ns TCYCLE = 62ns Fig.5
t9 Clock Low Duty Cycle 20 ns TCYCLE = 62ns Fig.5

ENCODER SECTION

tCE1 SO Setup Time 70 ns

tCE2 SO Hold Time 0 ns
tCE3 SO to BlO, BOO Prop Delay 1 1.5 DBP
tCE4 CTS Low to BlO, BOO Enabled 1 1.5 DBP
tCE5 CTS Low to ECLK Enabled 10.5 DBP
tCE6 CTS High to ECLK Disabled 1.0 1.5 DBP
tCE7 CTS High to BlO, BOO Disabled 2.0 2.5 DBP

DECODER SECTION

tCD1 UDI to 500, NVM 2.5 3 D8P <3>

tCD2 DCLK to 500, NVM 40 ns
tCD3 RST Low to DCLK, 500. 0.5 1.5 DBP (:J) CL = 50pF
NVM Low
tCD4 RST High to DCLK Enabled 0.5 1.5 DBP <3> CL = 50pF

UDI to BOO, BlO

ECLK to BlO
UDI to 500, NVM

NOTES: <D CR - Clock Rate, either 16X or 32X

(2) tc = 11fc
(3) DBP - Data Bit Period, CR = 16X, one DBP = 16 Clock cycles; CR = 32X, one DBP = 32 clock cycles
Guaranteed and sampled but not 100% tested.
The encoder uses free running clocks at 1X and 2X the data "a" bits followed by a command sync pulse. @ A com-
rate derived from the system clock IX for internal timing. mand sync pulse is a three bit wide pulse with the first 114
CTS is used to control the encoder outputs, ECLK, BOO and bits high followed by 114 bits low. @ Serial NRZ data is
BZO. A free running 1X ECLK is transmitted out of the clocked into the encoder at SO/CDS on the high to low
encoder to drive the external circuits which supply the transition of ECLK during the command sync pulse. The
NRZ data to the MEO at pin SO/CDS. N RZ data received is encoded into Manchester II data and
transmitted out on BOO and liZO following the com-
A low on CTS enables encoder outputs ECLK, BOO and
mand sync pulse. @) Following the synchronization se-
BZO, while a high on CTS forces BZO, BOO high and hOlds
quence, input data is encoded and transmitted out contin-
ECLK low. When CTS goes from high to low <D ,
a synch-
uously without parity check or word framing. The length
ronization sequence is transmitted out on BOO and BZO.
of the data block encoded is defined by CfS. Manchester
A synchronization sequence consists of eight Manchester
data out is inverted.

d>-------------------,--,--,-
! h..hS-
,
I
,
,
,
I

I
______
-_ - __--.- _ _r

, ,,
,
I
I
I : I-"~----EIGHT "0',"
,,
I
,
,, i I-·~---SYNCHRONIZATION SEQUENCE

: I

1- I"

The decoder requires a single clock with a frequency There is a three bit delay between UOI, BOI or BZI input
16X or 32X the desired data rate. The rate is selected on and the decoded NRZ data transmitted out of SOO.
the speed select with SS low producing a 16X clock and
high a 32X clock. For long data links the 32X mode should Control of the decoder outputs is provided by the RST
be used as this permits a wider timing jitter margin. The in- pin. When RST is low, SOO, OCLK and NVM are forced
ternal operation of the decoder utilizes a free running clock low. When RST is high, SOO is transmitted out synch-
synchronized with incoming data for its clocking. ronously with the recovered clock OCLK. The NVM out-
put remains low after a low to high transition on !lST until
The Manchester II encoded data can be presented to the a valid sync pattern is received.
decoder in either of two ways. The Bipolar One and Bi-
polar Zero inputs will accept data from differential inputs The decoded data at SOO is in NRZ format. OCLK is pro-
such as a comparator sensed transformer coupled bus. The vided so that the decoded bits can be shifted into an exter-
Unipolar Data input can only accept noninverted Manches- nal register on every high to low transition of this clock.
ter II encoded data, i.e. Bipolar Zero Out of an encoder. Three bit periods after an invalid Manchester bit is received
The decoder continuously monitors this data input for on UOI, or BOI and BZI, NVM goes low synchronously
a valid sync pattern. Note that while the MEO encoder with the questionable data output on SOO. Further, the
section can generate only a command sync pattern, the de- decoder does not reestablish proper data decoding until
coder can recognize either a command or data sync pattern. another sync pattern is recognized.
A data sync is a logically inverted command sync.
 I : ,
: I
•••
.
COMMAND
SYNC
.., I
I

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I
: 0
•
:
, ; 0 : ,
I

:
,

0 : 1 1 0 : ,
! : I : : : : I
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i!
I I

H H
I I I

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:
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:
,
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!
:
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:
,
j

It!
I I j

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I

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1--1-_--
:
~i _

Manchester II data can be presented to the repeater in either A low on CTS enables ECLK, BOO, and BZO. In contrast
of two ways. The inputs Bipolar One In and Bipolar Zero to the converter mode, a transition on CTS does not initiate
In will accept data from differential inputs such as a com- a synchronization sequence of eight O's and a command
parator or sensed transformer coupled bus. The input Uni- sync. The repeater mode does recognize a command or
polar Data In accepts only non-inverted Manchester II data sync pulse. SO/CDS is an output which reflects the
coded data. The decoder requires a single clock with a state of the most recent sync pulse received, with high in-
frequency 16X or 32X the desired data rate. This clock dicating a command sync and low indicating a data sync.
is selected to 16X with Speed Select low and 32X with
When RST is low, the outputs SDO, DCLK, and NVM are
Speed Select high. For long data links the 32X mode should
be used as this permits a wider timing jitter margin.
low, and Si'iST
is set low. SRST remains low after RST
goes high and is not reset until a sync pulse and two valid
The inputs UDI, or BOI, BZI are delayed approximately manchester bits are received with the reset bit low. With
1/2 bit period and repeated as outputs BOO and BZO. RST high, N RZ Data is transmitted out of Serial Data Out
The 2X ECLK is transmitted out of the repeater syn- synchronously with the 1X DCLK.
chronously with BOO and BZO.

INPUT
COUNT 2

ECLK

UDI

BZO
I
I
I
I
I
:__
BOO
~
I
---.-------.~
I I :
RST I

-,
I
I
I

SRST
501.rT1~~ I .--
5ll: ~~1T~T3
I I I ~ .JI
COMMANO SYNC

1 I
'0' II =-.uU-T3~t-=T3
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I NOTE: BOI· 0: Bll· 1 FOR NEXT OIAGRAMS I

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FIGURE 6
5-36
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NOTE: tCE5 - See Figure 1

tCE6 - See Figure 1

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I MANCHESTER I MANCHESTER I MANCHESTER I MANCHESTER 1

) LOGIC-l I LOGIC-O I LOGIC-O I LOGIC-l I
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MANCMESTER ',' MANCHESTER '0'

I• tA3 • I
SDD_
 there is no transition, an error indiction is given, and
synchronization must be re-established. This places rela-
Nonreturn to Zero (N RZl code representsthe binary values tively stringent requirements on the incoming data.
logic-O and logic-1 with a static level maintained through-
out the data cell. In contrast, Manchester code represents The synchronization advantages of using the HD-6409
data with a level transition in the middle of the data cell. and Manchester code are several fold. One is that Man-
Manchester has bandwidth, error detection, and synchron- chester is a self clocking code. The clock in serial data
ization advantagesover NRZ code. communication defines the position of each data cell.
Non self clocking codes, as NRZ, often require an extra
The Manchester II code Bipolar One and Bipolar Zero clock wire or clock track (in magnetic recording). Further,
shown below are logical complements. The direction of there can be a phase variation between the clock and data
the transition indicates the binary value of data. A logic-O track. Crosstalk between the two may be a problem. In
in Bipolar One is defined as a low to high transition in the Manchester, the serial data stream contains both the clock
middle of the data cell, and a logic-1 as a high to low mid and the data, with the position of the mid bit transition
bit transition. Manchester I code is not properly decoded representing the clock, and the direction of the transition
by the HD-6409. Manchester II is also known as Biphase-L representing data. There is no phase variation between
code. the clock and the data.

The bandwidth of NRZ is from DC to the clock frequency A second synchronization advantage is a result of the
fc/2, while that of Manchester is from fc/2 to fc. Thus, number of transitions in the data. The decoder resynch-
Manchester can be AC or transformer coupled, which has ronizes on each transition, or at least once every data cell.
considerable advantagesover DC coupling. Also, the ratio In contrast, receiversusing NRZ, which does not necessarily
of maximum to minimum frequency of Manchester extends have transitions, must resynchronize on frame bit transit-
one octave, while the ratio for NRZ is the range of 5-10 ions, which occur far less often, usually on a character
octaves. It is much easier to design a narrow band than basis. This more frequent resynchronization eliminates the
a wideband amp. cumulative effect of errors over sucessivedata cells. A final
synchronization advantage concerns the HD-6409's sync
Secondly, the mid bit transition in each data cell provides pulse used to initiate synchronization. This three bit
the code with an effective error detection scheme. If wide pattern is sufficiently distinct from Manchester data
noise produces a logic inversion in the data cell such that that a false start by the receiver is unlikely.

I
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;II HARRIS CMOS Programmable
HD-6406
Asynchronous
Communication Interface

Top View

• SINGLE CHIP UART/BRG CSD ~ vcc

• OC TO 16MHz OPERATION AD 2 3. CS1
WA 3 38 OR
• CRYSTAL OR EXTERNAL CLOCK INPUT 00 4 37. PE

••
• ON CHIP BAUD RATE GENERATOR 0' 3. FE
•.• 72 SELECTABLE BAUD RATES 02 3. OE
03 7 34 SO,
• DMA OR VECTORED INTERRUPT MODE 04 8 33 INTR

• MASKABLE INTERRUPTS O.
O.
•
'0
32
31
SFO
S,E
• MICROPROCESSOR BUS ORIENTED INTERFACE 07 30 RST

• SCALED SAJI IV CMOS PROCESS AD "

12 2. TBRE

,.,.
A' '3 28 CO
• SINGLE 5V POWER SUPPLY ALE '4 27 m
• LOW POWER - 1mA/MHz TYPICAL
~ 2. ~
RXDACK 2. !Ii
•
•
•
COMPLETE
LINE BREAK
LOOPBACK
MODEM INTERFACE
GENERATION
AND ECHO MODES
AND DETECTION
,x
Ox
SOO
GNO
,.
n
'8

20
24
23
22
21
1m!
CfS
P:LS6
TC

The HD-6406 (PACI) is a high performance programmable Universal Asynchronous Receiver/Trans-

mitter (UART) and Baud Rate Generator (BRG) on a single chip. Utilizing Harris Semiconductor's
advanced Scaled SAJI IV CMOS process, the PACt will support data rates from DC to 1Mbaud
(O-16MHz clock). In addition to all standard UART functions, the PACI includes a complete Data
Communications Equipment (DCE) interface.

Provision is made for DMA control of the PACI so that operation at the higher data rates is not
hindered by slow microprocessor response times. An ALE control input permits direct interfacing
to multiplexed data/address buses common to many microprocessors.

The interrupt structure of the PACI is user-programmable and can be configured to provide a single
interrupt for any status change. A subsequent read of an internal status register will identify the
source of the interrupt. If desired, the PACI can also provide separate hardware interrupt outputs
for the receiver, transmitter and modem status changes. Separate error condition outputs can be
used to pinpoint the exact cause of any detected error condition.

""""AA''
All
TlfllXOl<

""""""

U Ilrnl
I ."..

"""RT
!211 •• ~
 ACTIVE
I/O PIN SYMBOL LEVEL DESCRIPTION

I 1,39 CSO, CS1 Low, High CHIP SELECTS: The chip select inputs act as enable signals for the R15 and WF1" input signals during
all non-DMA bus operations.

I 2 RD Low READ: The RD input causes data to be output to the data bus (DO-D71. The data output depends
upon the state of the address inputs (AO, A 1) during non-DMA operations. During DMA raad oper-
ations (~ true) the address inputs are ignored and the contents of the Receiver Buffer Register
is output providing the DR bit in the Modem Status Register IMSR) is true.

I 3 WR Low WRITE: The WR input causes data from the data bus (00-07) to be input to the PACI. Addressing
and chip select action is the same as for read operations with the exception that TX"5"A'Ci< provides
the select qualifier for DMA write operations providing the TBRE bit in the MSR is true.

I/O 4-11 DO-D7 High DATA BITS 0-7: The Data Bus provides eight, 3-St8t8 input/output lines for the transfer of data, control
and status information between the PAC I and the CPU. For character formats of less than 8 bits, the
corresponding 07. 06 and 05 are considered "don't cares" for data writes and are 0 for data reads.
These lines are normally at their high impedance state except during read operations. DO is the LSB
and is the first serial data bit received or transmitted.

I 12,13 AO,A1 High ADDRESS 0, 1: The address lines select the various internal registers during CPU bus operations.
Quaiified DMA operations ignore the address inputs and access the appropriate receive or transmit
buffer register.

I 14 ALE High ADDRESS LATCH ENABLE: ALE true enables the internal transparent address latches for the AO, A1
inputs. The address is latched when ALE goes false (Iowl.

I 15 TXDACK Low TRANSMIT DMA ACKNOWLEDGE: A true TXDACK notifies the PACI that a transmit DMA cycle
has been granted. It acts as a chip select which enables the WR input to access the Transmitter Buffer
Buffer Register when the TBRE bit in the MSR is true.

I 16 RXDACK Low RECEIVE DMA ACKNOWLEDGE: A true RXDACK notifies the PACI that a receive DMA cycle has
been granted. It acts as a chip select which enables the RO input to access the Receiver Buffer Register
when the DR bit in the MSR is true.

1,0 17,18 IX,OX CRYSTAL/CLOCK: Crystal connections for the internal Baud Rate Generator. IX can also be used
as an external clock input in which case OX should be left open.

0 19 500 High SERIAL DATA OUTPUT: Serial data output from the PAC I transmitter circuitry. A Mark 111 is high
and a Space (01 is low. SOO is held in the Mark condition when the transmitter is disabled with CTS
false, RST true, when the Transmitter Register is emptY, or when in the Loop Mode.

20 GND Low GROUND: Power supply ground connection.

0 21 TC High TRANSMISSION COMPLETE: TC goes true when a complete character, including stop bits, has been
been transmitted and TBRE is true. TC is reset with a data write to TBR. RST will set TC true.

I 22 RLSD Low RECEIVE LINE SIGNAL DETECT: The logical state of this input is reflected in the R LSD bit of the
Modem Status Register. Any change of state will cause an interrupt on INTR if INTEN and MIEN
are true.

I 23 CTS Low CLEAR TO SEND: The logical state of the CTS line is reflected in the CTS bit of the Modem Status
Register. Any change of state of CTS causes INTR to be set true when INTEN and MIEN are true.
A false level on CTS will inhibit transmission of data on the SOO output and will hold SOO in the Mark
(high) state. If CTS goes false during transmission, the current character being transmitted will be com-
pleted. CTS does not affect the Loop mode of operation.

I 24 DSR Low DATA SET READY: The logical state of the DSR line is reflected in the Modem Status Register. Any
change of state of '5S'R will cause INTR to be set if INTEN and MIEN are true. The state of this signal
does not affect any other circuitry within the PACI.

I 25 RI Low RING INDICATOR.:.... The logical state of the RI line is reflected in the Modem Status Aegister. Any
change of state of RI wiil cause iNTR to be set if INTEN and MIEN are true. The state of this signal
does not affect any other circuitry within the PACI.

0 26 DTR Low DATA TERMINAL READY: The OTR signal can be set (low) by writing a logic 1 to the appropriate
bit in the Modem Control Register (MCR), This signal is cleared (high) by writing a logic 0 to the same
bit in the MCR or whenever a AST (Highl is applied to the PAC\,
 ACTIVE
I/O PIN SYMBOL LEVEL DESCRIPTION

0 27 RTS Low REQUEST TO SEND: The RTS signal can be set (low) by writing a logic 1 to the appropriate bit in
the MCR. This signal is cieared (High) by writing a logic 0 to the same bit in the MCR or whenever e
RST (High) is epplied to the PACI.

0 28 CO CLOCK OUT: This output is user programmable to provide either buffered IX output or a buffered
8aud Rate Generator (16x) clock output. The buffered ix (Crystal or external clock source) output
is provided when the 8RSR bit 7 is set to a zero. Writing a logic one to BRSR bit 7 cau.es the CO output
to provide a buffered version of the internal Baud Rate Generator clock which operates at sixteen times
the programmed baud rate,

0 29 TBRE High TRANSMITTER BUFFER REGISTER EMPTY: The TBRE output is set (high) whenever the Trans-
mitter Buffer Register (TBR) has transferred its data to the Transmit Register, Application of a RST to
the PACI will also set the TBRE output. TBRE is cleared (Low) whenever data is written to the TBR.

I 30 RST High RESET: The RST input forces the PACI into an "Idle" mode in which ali serial data activities are sus-
pended. The Modem Control Register (MCR) along with its associated outputs are cleared. The UART
Status Register (USR) is cleared except for the TBRE and TC bits which are set. The PACI remains in an
"Idle" state until programmed to resume serial data activities. The RST input is a Schmitt trigger input.

I 31 SIE High SINGLE INTERRUPT ENABLE: A true (high) level on the SIE input enables interrupts caused by the
DR and TBRE status bits. This enables the user to utilize a single hardware interrupt signal (INTR) for
any status change within the PAC!.

I 32 SFD High STATUS FLAGS DISABLE: Holding the SFD input

true (high) prevents the true state of the USR
bits PE, DE, FE and TC from causing an interrupt. This control input, like the SI E input, enables the
user to define what status changes will effect the INTR output.

0 33 INTR High INTERRUPT REQUEST: The INTR output is enabled by the INTEN bit in the Modem Control
Register (MCRl. The MIEN bit and the SIE and SFD control inputs selectively enable various status
changes to provide an input to the INTR logic. Figure 9 shows an overall view of the relationship of
these interrupt control signals.

I 34 SOl High SERIAL DATA INPUT: Serial data input to the PACI receiver circuits. A Mark (1) is high, and a Space
(0) is low. Data inputs on SDI are disabled when operating in the loop mode, when AST is true or when
the Receiver Enable (REN) bit in the MCR register is false.

0 35 OE High OVERRUN ERROR: A true level on the DE output indicates that the Receiver Buffer Register (RBR)
was full when a character was received. Transfer to the RBR will not occur. OE ;s updated each time a
character is transferred to the RBR. RST high will set OE low.

0 36 FE High FRAMING ERROR: A true level on the FE output indicates that there were invalid stop bits in the last
received character. The FE output is updated each time a character is transferred to the RBR. RST
high will reset FE.

0 37 PE High PARITY ERROR: PE is set true whenever the paritY of a received character does not match the pro-
grammed paritY. The PE output is updated each time a character is transferred to the ABA. PE is reset
whenever AST is true or when no paritY check is programmed.

0 38 DR High DATA READY: A true level indicates that a character has been received, transferred to the ABR and
is ready for transfer to the CPU. DR is reset on a data read of the RBA or when AST is true.

40 VCC High +5 VOLT SUPPLY: Positive power supply connection.

• Clears the UART Status Register (USR) except for TC

During and after power-up, the PACI should be given a and TB RE wh ich are set. The Modem Control Register
RST high for at least two IX clock cycles in order to initial- (MCR) is also cleared. All of the discrete lines, memory
ize and drive the PACI's circuits to an idle mode until prop- elements and miscellaneous logic associated with these
er programming can be done. A high on RST causes the register bits are also cleared or turned off. Note that
following events to occur: the UART Control Register (UCR) is not affected.

• Resets the internal BRG circuits, clock counters and Following removal of the reset condition (RST low). the
bit counters. The Baud Rate Select Register (BRSR) is PACI remains in the idle mode until programmed to its
not affected. desired system configuration.
The complete functional definition of the PACI is program-
med by the systems software. A set of control words (UCR,
BRSR and MCR) must be sent out by the CPU to initialize STOP BfT SELECT O· htop bit

the PACI to support the desired communication format. 1-1 ,5 stop biu (Tx)and 1 SlOp bit
(Ax) if 5d,t, bit5selacted
These control words will program the character length, '-2nopbiufor6,7or8d.Ubits
l,lected
number of stop bits, even/odd/no parity, baud rate etc.
Once programmed, the PACI is ready to perform its com- PARITV CONTROL 000" TK Ind Ax Evan
001 .• Tll and Rll Odd
munication functions. 010· Tx Even, Rx Odd
all" Tx Odd, Ax Even
100· TK Even, Fhtctleclc disabled
The control registers can be written to in any order, how- 101" TxOdd, All check ditabled
l1X" Gentration.ndcheck
ever the MCR should be written to last because it controls disabled

the interrupt enables, modem control outputs and the WORD LENGTH 00" 5 biu
receiver enable bit. Once the PACI is programmed and op- SELECT 01 .• 6biu
10 .• 7 bits
erational these registers can be updated any time that the 11 •• 8biu
PACI is not immediately transmitting or receiving data.

Table 1 shows the required control signals to access the

PACI's internal registers.

ALE CSO CSl Al AO WR RD OPERATION

lor "l... 0 , 0 0 J , Data bus~TBA
, or"l... 0 1 0 0 1 '"l... RBR---+Oata bus
, orL 0 1 0 1
....r 1 Data bus---+ UCR
10rt. 0 1 0 1 1 '"l... USR-+Data bus
The PACI is designed to operate with a single crystal or
10r"l... external clock driving the IX input pin. The Baud Rate
0 1 1 0 J 1 Databus---+ MeR
Select Register is used to select which divide ratio (one of
10rt... 0 1 1 0 1 ""'t... MCA--+Data bus
, or"l.. 0 1 1 , J 1 Data bus---+BRSR
72) the internal Baud Rate Generator circuitry will use.
The internal circuitry is seperated into two separate count-
1 ort.. 0 1 1 1 1 '"l... MSR ---+ Data bus ers, a Prescaler and a Divisor Select. The Prescaler can be
set to anyone of four division rates, +1, +3, -;.4 or ~ 5.
This Prescaler design has been optimized to provide stand-
ard baud rates using anyone of three popular crystal
The Address Latch Enable (ALE) input acts as an address frequencies. By using one of these common system clock
latch control signal during these operations. If ALE is left frequencies, 1.8432 MHz, 2.4576 MHz or 3.072 MHz and a
high, the address inputs AO, A 1 must be held true during Prescaler of + 3, + 4 or -;.5 respectively, the Prescaler out-
the entire bus operation (demultiplexed bus operation). put will provide a constant 614,400 Hz. When this fre-
For multiplexed bus applications the address inputs AO, A 1 quency is further divided by the Divisor Select counter, any
are latched when ALE goes low. In this case AO and A 1 are of the standard baud rates from 50 to 38.4 KBaud can be
not required to be held true for the entire bus cycle. selected (see- Table 2). Non-standard baud rates up to 1
Mbaud can be selected by using different input frequencies
DMA control of the PACI is discussed in a later section of (up to 16 MHz) and/or different Prescaler and Divisor
this data sheet and involves reading and writing of the Select ratios. The baud rate generator provides a clock
Receiver and Transmitter Buffer Registers (RBR and TBR). which is 16 times the desired baud rate. For example, in
order to operate at a 1 Mbaud data rate a 16 MHz crystal,
The following descriptions discuss the control registers in a Prescale rate of +1, and a Divisor Select rate of "external"
detail.
would be used to provide a 16 MHz clock as the output of
the Baud Rate Generator to the Transmitter and Receiver
Circuts.

The UCR is a write only register which configures the The CO select bit in the BRSR selects whether a buffered
UART transmitter and receiver circuits. Data bits D7 and version of the external frequency input (IX input) or the
D6 are not used but should always be set to a zero in order Baud Rate Generator output (16X baud rate clock) will be
to insure software compatability with future product up- output on the CO output (pin 28). The Baud Rate Gen-
grades. During the Echo Mode, the transmitter always erator output will always be a 50% nominal duty cycle ex-
repeats the received word and parity, even when the UCR is cept when "external" is selected and the Prescaler is set to
programmed with different or no parity. +30r+5.
 The MCR is a general purpose control register which can
PRESCALER SELECT 00· + 1
01 • + 3
be written to and read from. The RTS and OTR outputs
10 • + 4 are directly controlled by their associated bits in this
11 • + 5
register. Note that a 109iC one asserts a true 109iC level
DIVISOR SELECT 00000 • + 2 (low) at these output pins. The Interrupt Enable (I NTEN)
00001 • + 4
00010 • + 16/3
bit is the overall control for the INTR output pin. When
00011 • + 8 INTEN is false, INTR is held false (low). The Operating
00100 • + 32/3
00101 • + 16 Mode bits configure the PACI into one of four possible
00110· + 58/3 modes. "Normal" configures the PACI for normal full or
00111 • + 22
01000 • + 32 half duplex communications. "Transmit Break" enabies
01001 • + 64 the transmitter to only transmit break characters (Start,
01010 • + 128
01011 • + 192 Oata and Stop bits all are logic zero). The Echo Mode
01100· + 256 causes any data that is received on the SOl input pin to
01101· + 288
01110· + 352 be re-transmitted on the SOO output pin. Note that this
01111 • + 512
10000 • + 768
output is a buffered version of the data seen on the SOl
11111. extern,l (+1) input and is not a re-synchronized output (see Figure4).
The Loop Test Mode internally routes transmitted data
to the receiver circuitry for the purpose of self test. The
transmit data is disabled from the SOO output pin. The
Receiver Enable bit gates off the input to the receiver
circuitry when in the false state. Modem Interrupt Enable
BAUD RATE DIVISOR
will permit any change in modem status line inputs (CfS;

38,4K external
AT; RLSO, OSR) to cause an interrupt when this bit is
enabied. Bit 07 must always be written to with a logic
19.2K 2
zero to insure correct PACI operation.
9600 4
7200 16/3
4800 8
3600 32/3 Z
REOUEST TO SEND o - 'rnoutputtllgtl 0
2400 16
2000"
1800
58/3
22
DATA TERMINAL READY'
1 - Moutpullow

o-~oUlputtllgtl
1 - l:5'T"A'oulPutlow
<3
<z
1--
o=>
1200 32 INTERRUPT ENABLE lINTEN) o
1
-
-
Interruptldlubled
Interrupuenlbled
=:
=:
600 64 0
300 128 MODE SELECT 00-
01-
Normll
Trln,mitbruk
'-'
200 192 10- Ectlomode
11- Looplutmode
150 256
RECEIVER ENABLE o - Notenlbled
134.5" 288 lREN) I - Enebled

110" 352 MODEM INTERRUPT ENABLE o - Notenebled

(MIEN)
75 512 1 - En.bl.d

50 768

Note: These baud rates are based upon the following

input frequency/Prescale divisor combinations.
1.8432MHz and Preseale = +3
2,4576MHz and Preseale = +4
3.072MHz and Preseal. = +5
* All baud rates are exact except for:

PERCENT
BAUD RATE ACTUAL ERROR

2000 1986.2 0.69%

134.5 133.33 0.87%
110 109.71 0.26%
 HD-6406

The Data Ready (DR) bit indicates that the RBR has been
loaded with a received character and that the CPU may
The USR provides a single register that the controlling access this data. An interrupt will be generated (INTR) if
system can examine to ascertain if errors have occured or if SIE input is high and the INTEN bit is enabled.
other status changes in the PACI require the system's atten-
MODEM STATUS REGISTER (MSR)
tion. For this reason, the USR is usually the first register
read by the CPU to determine the cause of an interrupt or
The Msr, provides a means whereby the CPU can read the
to poll the status of the PAC!. Three error flags OE, FE
modem signal inputs by accessing the data bus interface of
and PE report the status of any error conditions detected
the PAC!. Like all of the register images of external pins in
in the receiver circuitry. These error flags are updated with
the PACI, true logic levels are represented by a high (1)
every character received during reception of the stop bits.
signal level. By following this consistent definition the
The Overrun Error (OE) indicates that a character in the
system software need not be concerned with whether ex-
Receiver Register has been received and cannot be transfer-
ternal signals are high or low true. In particular the modem
red to the Receiver Buffer Register (RBR) because the RBR
was not read by the CPU. Framing Error (FE) indicates signal inputs are low true, thus a 0 (true assertion) at a
that the last character received contained improper stop modem input pin is represented by a 1 (true) in the MSR.
bits. This could be caused by the total absence of the re-
quired stop bit(s) or by a stop bit(s) that was too short to Any change of state of any of the modem input signals
be properly detected. Parity Error (PE) indicates that the Will set the Modem Status (MS) bit in the USR register.
last character received contained a parity error based on the When this happens an interrupt (INTR) will be generated if
programmed parity of the receiver and the calculated parity the M IEN and INTEN bits of the MCR are enabled.
of the received characters data and parity bits.
The Ring Indicator (AI) input indicates to the PAC! that
The Received Break (RBRK) status bit indicates that the the modem is receiving a ringing signal.
last character received was a break character. A break
character would be considered to be an invalid data char- The Receive Line Signal Detect (R LSD) input is used to
acter in that the entire character including parity and stop notify the PACI that the signal quality received by the
bits are a logic zero. modem is within acceptable limits.

The Modem Status bit is set whenever a transition is detect- The Data Set Ready (DSR) input is a status indicator from
ed on any of the Modem input lines (Ri, RLSD, CTS or the modem to the PACI which indicates that the modem is
DSR). A subsequent read of the Modem Status Register ready to provide received data to the PACI receiver cir-
will show the state of these four signals. Assertion of this cuitry.
bit will cause an interrupt (INTR) to be generated if the
MIEN and INTEN bits in the MCR register are enabled. Clear to Send (CTS) is both a status and control signal from
the modem that tells the PACI that the modem is ready to
The Transmission Complete (TC) bit indicates that both the receive transmit data from the PACI transmitter output
TBR and Transmitter Registers are empty and the PACI (SDO). A high (false) level on this input will inhibit the
has completed transmission of the last character it was PACI from beginning transmission and if asserted in the
commanded to transmit. The assertion of this bit will middle of a transmission will only permit the PAC! to finish
cause an interrupt (INTR) if the SFD (pin 32) input is low transmission of the current character.
and the INTEN bit in the MCR register is true.

TRANSMITTER BUFFER
REGISTER EMPTY (TBREl

DATA READY (DR)

The receiver circuitry in the PACI is programmable for 5, 6,

FIGURE 5
7 or 8 data bits per character. For words of less than 8
The Transmitter Buffer Register Empty (TBRE) bit indi- bits, the data is right justified to the LSB (DO). Bit DO of a
cates that the TB R register is empty and ready to receive data word is always the first data bit received. The unused
another character. Assertion of this bit will cause an inter- bits in a less than 8 bit word, at the parallel interface, are
rupt if the SIE (pin 31) input is high and the INTEN bit set to 0 by the PACI. Received data at the SOl input pin
in the MCR is enabled. is shifted into the Receiver Register by an internal 1X clock
5-44
which has been synchronized to the incoming data based on made for the transmitter parity to be the same or different
the position of the start bit. When a complete character from the receiver. The TBRE output pin and flag (USR
has been shifted into the Receiver Register, the assembled register) reflect the status of the TBR. The TC output pin
data bits are parallel loaded into the Receiver Buffer and flag (USR register) indicates when both the TB Rand
Register. Both the DR output pin and DR flag in the USR TR are empty.
register are set. This double buffering of the received data
permits continuous reception of data without losing any
of the received data. While the Receiver Register is shift-
ing a new character into the PACI, the Receiver Buffer
The PAC I has provision for both software and hardware
Register is holding a previously received character for the
masking of interrupts generated for the INTR output
system CPU to read. Failure to read the data in the RBR
pin. The two input pins, SIE and SFD, provide the mask
before complete reception of the next character can result
control for the receiver and transmitter status interrupts.
in the loss of the data in the Receiver Register. The OE flag
Two control bits in the MCR register, MIEN and INTEN,

I
in the USR register indicates the overrun condition.
control modem status interrupts and overall PACI inter-
RBR rupts respectively. Figure 9 illustrates the logical control
function provided by these signals.

The modem status inputs (RLSD, RI, DSR and CTS)

B;\O
Bit 1 will trigger the edge detection circuitry with any change of
Bit 2 5 bit status. Reading the MSR register will clear the detect
word circuit but has no effect on the status bits themselves.
Bit 3
These status bits always reflect the state of the input
pins regardless of the mask control signals. Note that the
Sit4
state (high or low) of the status bits are inverted versions
of the actual input pins.

The edge detection circuits for the USR register signals will
trigger only for a positive edge (true assertion) of these
status bits. Reading the USR register not only clears the
edge detect circuit but also clears (sets to 0) all of the status
bits. The output pins associated with these status bits
are not affected by reading the USR register.

The Transmitter Buffer Register (TBR) accepts parallel

data from the microprocessor data bus (DO-D7) and holds
it until the Transmitter Register is empty and ready to ac-
cept a new character for transmission. The transmitter
always has the same word length and number of stop bits as
the receiver. For words of less than 8 bits the unused bits
at the microprocessor data bus are ignored by the trans-
mitter. Bit 0, which corresponds to DO at the data bus, is
always the first serial data bit transmitted. Provision is

B;\OI
Bit 1

Bit 2

Bit 3

Bit 4
5 bit
word
!
6 bit
word
Because
provision
buffer
of the high data rates possible
for DMA control of the transmitter
registers has been included
with the PACI,
and receiver
in the design. The
Bit 5 RXDACK and TXDACK inputs in conjunction with the
RD and WR inputs are driven by the system DMA con-
troller to access the RBR and TBR registers respectively.

Reading of the RBR via the RXDACK control signal re-

quires that the DR bit in the USR is set (high) and that
the RD input be driven low. When these conditions are
met the address logic overrides the address inputs (AO,
A1) and forces a read of the RBR. Similarly, a DMA
write to the TBR requires that the TBRE bit in the USR PARAMETER TYPICAL CRYSTAL SPECIFICATION
register is set (high) and that TXDACK and WR are as-
Frequency '.0 to 16MHz
serted by the DMA controller. Once again the address Parallel resonent, Fund. mode
Type of Operation
logic overrides the address inputs and forces a write to the Load Capacitance (ell 20 or 32 pf, (tyP.)
Aseries(Mu.l 100 ohm. (1016 MHz. CL' 32pf.)
TB R register. 200 ohms (f-16 MHz, CL· 20pf.)

The CSO and CS1 inputs would normally be in their in-

active state during DMA accesses. The AO, A 1, and ALE
inputs are overridden during DMA operations and as such
their logical state is a don't care.

The PACI crystal oscillator circuitry is designed to operate

with a fundamental, parallei resonent crystal. This circuit
is the same as used in the Harris B2CB4A clock generator/
driver and as such the general applications information
contained in Tech Brief TB-47 that applies to the oscillator
operation will be pertinent to the PACI. To summarize
Table 3 and Figure 10 show the required crystal parameters
and crystal circuit configuration respectively.

When using an external clock source the Ix input is driven

and the Ox output is left open. Power consumption when
using an external clock is typically 2 times lower than
when using a crystal. This is due to the sinusoidal nature
of the drive circuitry when using a crystal.

BIT ASSIGNMENT
REGISTER
NAME MNEMONIC LSB 0 1 2 3 4 6 6 MSB7

Receiver RBR Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Buffer

Transmitter TBR Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit S Bit 6 Bit 7
Buffer

UART USR ParitY Framing Overrun Aeceived Modem Tr.nsmission Transmitter Data
Status Error Error Error Break Status Complete Buffer Reg. Ready
IPEI (FEI IOEI (RBRKI IMSI (TCI empty (TBRE) IORI

UART UCR Stop Bit Parity Parity Parity Word Word

Control Select Control 0 Control 1 Control 2 Length 0 Length 1 Reserved* Reserved·

Modem MCR Request Data Interrupt Mode Mode Receiver Modem

Control To Send Terminal Ready Enable Salect 0 Select 1 Enable Interrupt 0
IRTSI IDTRI IINTENI IRENI enable (MIENl

Modem MSR Clear to Data Received Line Ring Not Not Not NOI
Status Send ICTSI Set Ready Signal Detect Indicator Used Used Used Used
(DSRI (RLSDI (RII

Bit Rate BRSR Prescaler Prescaler Divisor Divisor Di>.fisor Divisor Divisor Co
Select SeleCl0 Select 1 Select 0 Select 1 Select 2 Select 3 Select 4 Select
 HD-6406

ABSOLUTE MAXIMUM RATINGS

Supply Voltage +8.0 Volts Operating Temperature Range
Operating Voltage Range +4V to +7V Industrial -40oC to +850C
Input Voltage Applied GND -2.0V to +6.5V Military -550C to +1250C
Output Voltage Applied GND -0.5V to VCC +O.5V Maximum Power Dissipation 1 Watt
Storage Temperature Range -650C to +150oC

CA UTION: Stressesabove those listed in the "ABSOLUTE MAXIMUM RA TINGS" may causepermanent damage
to the device. This is a stress only rating and operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.

D. C. CHARACTERISTICS
VCC = 5.0V 110%; T A = -40oC to +850C (-9); TA = -550C to +1250C (-2, -8)

SYMBOL PARAMETER MIN MAX UNITS TEST CONOITIONS

VIH Logical One 2.0 V

Input Voltage

VIL Logical Zero 0.8 V

I nput Voltage

VTH Schmidt Trigger VCC -0.5 V Reset Input

Logical One
Input Voltage

VTL Schmidt Trigger GNO +0.5 V Reset Input

Logical One
Input Voltege

VIH (CLK) Logical One VCC -0.5 V

Clock Voltage External Clock

VIL (CLK) Logical Zero GND +0.5 V

Clock Voltage External Clock

VOH Output High Voltage 3.0 V IOH = -2.5mA

VCC -0.4 V IOH = -400J.LA
VOL Output Low Voltage 0.4 V IOL = +2.5mA
ilL Input Leakage -1.0 +1.0 J.LA OV<VIN<VCC
Current

IOL Output Leakage -10.0 +10.0 jiA OV~VO~VCC

Current
ICCOP' Operating Power 3 ma External Clock
Supply Current F = 2.4576 MHz
VCC = 5.5V
VIN = VCC or GND
Outputs Open
CAPACITANCE
TA = 250C; VCC = GND = OV; VIN = +5Vor GND

SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS

CIN" Input Capacitance 10 pI FREQ =

1 MHz
Unmeasured pins
returned to GND
COUTo Output Capacitance 15 pf
CliO' I/O Capacitance 20 pf

VCC = +5V ±10%, GND = OV: TA = -40oC to +850C (-9)

TA = -550C to +1250C (-2, -8)

SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS

TLHLL ALE Pulse Width 50 ns

TAVLL Address Setup 20 ns

TLLAX Address Hold 20 ns

TSVCTL Select Setup to Control 30 ns

leading edge

TCTHSX Select Hold from Control 50 ns

Trailing Edge

TCTLCTH Control Pulse 150 ns Control Consists of

Width RD or WR

TCTHCTL Control Disable to 100 ns

Control Enable

TRLDV Read low to Data Valid 120 ns 1

TRHDZ Read Disable 0 60 ns 2

TCTHLH Control Inactive to ALE High 20 ns

TDVWH Data Setup Time 50 ns

TWHDX Data Hold Time 20 ns

FC Clock Frequency 0 16 MHz TCHCL + TCLCH must be

:2: 62.5ns

TCHCL Clock High Time 25 ns

TCLCH Clock Low Time 25 ns

TR/TF IX Input tx ns tx S1/16FC) or 50ns

Rise/Fal1 Time (10% -90%) whichever is smaller
(External Clockl

TFCO Clock Output 15 ns CL = 50pf

Fall Time

TRCO Clock Output 15 ns CL = 50pf

Rise Time
 INPUT OUTPUT
VIH + O.4V ~------ VOH

1.5V X... X1.5V

OUTPUT
FROM
DEVICE UNDER TEST

TEST CONDITION Vl R1 R2 CL
A. C. Testing: All input signals must switch between VIL
1 Propagation Delay 1.7V 520 00 100pF -OAV and VIH +OAV. TR and TF must be Ie" than or
2 Disable Delay VCC 5K 5K 50pF equal to 15ns.

w"'"
OPERATION {
00-07

BlI,CSt.AO.AI
OR T"XOAEii:
OR R'XDACK

WII
WRITE
OPERATION

l 00-07

l
AD
READ
OPERATION

00-07
m HARRIS
REFERENCE PAGE 3-27 FOR
COMPLETE SPECIFICATIONS 82C52
CMOS Serial
Controller Interface

• SINGLE CHIP UART/BRG

• DC TO leMHz OPERATION
• CRYSTAL OR EXTERNAL CLOCK INPUT
• ON CHIP BAUD RATE GENERATOR
... 72 SELECTABLE BAUD RATES cso
• INTERRUPT MODE WITH MASK CAPABILITY vcc
DR
• MICROPROCESSOR BUS ORIENTED INTERFACE
SOl
• BOCBS COMPATIBLE INTR
• SCALED SAJI IV CMOS PROCESS RST
• SINGLE 5V POWER SUPPLY TBRE
CO
• LOW POWER - lmA/MHz TYPICAL
m
• MODEM INTERFACE OTR
• LINE BREAK GENERATION AND DETECTION DSR

• LOOPBACK AND ECHO MODES ffi

GND
SOD

The 82C52 is a high performance programmable Universal Asynchronous

Receiver/Transmitter (UART) and Baud Rate Generator (BRG) on a single
chip. Utilizing the Harris advanced Scaled SAJI IV CMOS process. the
82C52 will support data rates from D.C. to 1M baud asynchronously with a
16X clock (0-16 MHz clock frequency).

The on-chip Baud Rate Generator can be programmed for anyone of 72

different baud rates using a single industry standard crystal or external
frequency source. A unique pre-scale divide circuit has been designed to
provide standard RS-232-C baud rates when using anyone of three in-
dustry standard baud rate crystals (1.8432 MHz. 2.4576 MHz. or 3.072MHz).

A programmable buffered clock output (CO) is available and can be pro-

grammed to provide either a buffered oscillator or 16X baud rate clock for
general purpose system usage.

Inputs and outputs have been designed with full TTL/CMOS compatibility
in order to facilitate mixed TTL/NMOS/CMOS system design.

VCC - PIN 27
GND - PIN 16

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow standard Ie Handling Procedures.
5-50
:II HARRIS CMOS/LSI Universal Asynchronous
HD-6402
Receiver Transmitter (UART)

• OPERATION PROM D. C TO 2.OMHI 0 5.0 VOLTS

• LOW POWER-TYPo 10mW 0 2.OMHz AND 5.0 VOLTS VCC TRC
• PROGRAMMABLE WORD LENGTH,STOP BITS AND PARITY NC EPE
GND CLSl
• AUTOMATIC DATA FORMATTING AND STATUS GENERATION
RRD CLS2
• COMPATIBLE WITH INDUSTRY STANDARD UART'S RBR8 SBS

• SINGLE POWER SUPPLY RBR7 PI

RBR8 CRL
RBRS TBR8
RBR4 TBR7
RBR3 TBR8
RBR2 TBRS
RBR1 TBR4
The HD-6402 is a CMOS/LSI subsystem for interfacing computers or
PE TBR3
microprocessors to an asynchronous serial data channel. The receiver
FE TBR2
converts serial start, data, parity and stop bits to parallel data verifying OE TBR1
proper code transmission, parity, and stop bits. The transmitter converts SFD TRO
parallel data into serial form and automatically adds start, parity, and stop RRC TRE
DRR TBRL
bits. The data word length can be 5, 6, 7 or 8 bits. Parity may be odd or
DR TBRE
even. Parity checking and generation can be inhibited. The stop bits RRI MR
may be one or two or one and one-half when transmitting 5 bit code.

The HD-6402 can be used in a wide range of applications including mo-

dems, printers, peripherals and remote data aquisition systems. CMOS/LSI
2
technology permits operation clock frequencies up to 2.0MHz (125K 0

Baud) an improvement of 10 to lover previous PMOS UART designs. <~

1--
Power requirements, by comparison, are reduced from 300mW to 10mW. <2
Q::>
Status logic increases flexibility and simplifies the user interface.
Control Definition ~
~
0
(.)

CONTROL WORD CHARACTER FORMAT

C C
-----1 L L P E S
I S S I P B START DATA PARITY STOP
I 2 1 E S BIT BITS BIT BITS
I
I 0 0 0 0 0 5 ODD 1
TII••,.••••lnllllll.O ••TlIiI I
0 0 0 0 1 5 ODD 1.5
I 0 0 0 1 0 5 EVEN 1
I 0 0
I 0 1 1 5 EVEN 1.5
0
0
0
0 ,
1 X
X
0
1
5
5
NONE
NONE
1
1.5
0 1 0 0 0 6 ODD 1
0 1 0 0 1 6 ODD 2
0 1 0 1 0 6 EVEN 1
0 1 0 1 1 6 EVEN 2
0 1 1 X 0 6 NONE 1
0 1 1 X 1 6 NONE 2
1 0 0 0 0 7 ODD 1
1 0 0 0 1 7 ODD 2
1 0 0 1 0 7 EVEN 1

,
1 0 0 1
0 1 X
1
0
7
7
EVEN
NONE
2
1
1 0 1 X 1 7 NONE 2
1 1 0 0 0 8 ODD 1
1 1 0 0 1 8 ODD 2
1 1 0 1 0 8 EVEN 1
1 1 0 1 1 8 EVEN 2
1
1 ,
1 1
1
X
X
0
1
8
8
NONE
NONE 2
1

CAUTION: These devices are sen.ltl", to electronic dllCharge.

Proper I.C. handling procedure •• hould be followed.
 Supply Voltage +B.OV
Input or Output Voltage Applied GND -O.3V to VCC +O.3V
Storage Temperature Range -650C to +1500C
Operating Temperature Range
Industrial HD-6402-9
Military HD-6402-2/B

SYMBOL PARAMETER MINIMUM TYPICAL MAXIMUM UNITS CONDITIONS

VIH Logical "1" Input Voltage 70% VCC V

VIL Logical "0" Input Voltage 20% VCC V
IlL Input Leakage -1.0 1.0 J.1.A OV ~ VIN ~ VCC
VOH Logical "1" Output Voltage 2.4 V IOH = -0.2mA
VOL Logical "0" Output Voltage 0.45 V 'OL = 2.0rT)A
10 Output Leakage -1.0 1.0 J.1.A OV ~ VO ~ VCC
ICC Supply Current 1.0 100 J.1.A VIN = GND or VCC;
VCC = 5.5V, Output
Open
CIN Input Capacitance* 7.0 8.0 pF
Co Output Capacitance* 8.0 10.0 pF

VCC =5.0V <D VCC-5.0V+l0%

TA = 250C TA = Indust.or Mi1.

SYMBOL PARAMETER MIN TYP MAX MIN TYP MAX UNITS CONDITIONS

fclock Clock Frequency D.C. 3.0 D.C. 2.0 MHz

tpw Pulse Widths CRL, DRR. TBRL 150 150 ns CL = 50pF
tMR Pulse Width MR 350 400 ns See Switching Time

tSET Input Data Setup Time 50 50 ns Waveforms 1,2, 3

tHOLD Input Data Hold Time 60 60 ns

tEN Output Enable Time 125 160 ns

Transmitter Operation
The transmitter section accepts parallel data, formats it to the transmitter register, TREmpty is cleared, TBR-
and transmits it in serial form on the TROutput terminal. Empty is set high, and serial data transmission is started.
® Data is loaded into the transmitter buffer register from Output data is clocked by TRClock. The clock rate is 16
the inputs TR 1 through TRB by a logic low on the times the data rate. ©
A second pulse on TBRload loads
TBRload input. Valid data must be present at least tSET data into the transmitter buffer register. Data transfer to
prior to and tHOlD following the rising edge of TBR l. the transmitter register is delayed until transmission of the
If words less than B bits are used, only the least significant current character is complete. @
Data is automatically
bits are used. The character is right justified into the least transferred to the transmitter register and transmission of
significant bit, TRL ® The rising edge of TBRl clears that character begins one clock cycle later.
TBREmpty. 0 to 1 clock cycles later, data is transferred

TBR:~
TBRE

TRE ----T-CH OCK

k= ~1I CLOCK

TRO ~ ,D-A-T-A---'~
•.•
® ® ~==--_...~ LAST STOP BIT
 Supply Voltage +8.0V
Input or Output Voltage Appl ied GND -O.3V to VCC +O.3V
Storage Temperature Range -650C to +1500C
Operating Temperature Range (Industrial -9) -400C to +850C

SYMBOL PARAMETER MINIMUM TYPICAL MAXIMUM UNITS CONDITIONS

VIH Logical "1" Input Voltage 70% VCC V

VIL Logical "0" Input Voltage 20% VCC V
IlL I nput Leakage -10.0 +10.0 J.lA OV~ VIN ~VCC

VOH Logical "1" Output Voltage 2.4 V 10H = -0.2mA

VOL Logical "0" Output Voltage 0.45 V 10L = 2.0mA
10 Output Leakage -10.0 +10.0 J.lA OV ~ Vo ~ VCC
ICC Supply Current 1.0 800 J.lA VIN = GND or VCC
VCC = 5.5V
Input Capacitance* 7.0 8.0 pF Output Open
CIN
Co Output Capacitance* 8.0 10.0 pF

VCC =5.0V
TA·250C
CD VCC z 5.0V± 10%
T A • Industrial

SYMBOL PARAMETER MIN TYP MAX MIN TYP MAX UNITS CONDITIONS

fclock Clock Frequency D.C. 2.0 D.C. 1.0 MHz

tpw Pulse Widths CRL, ORR, T8RL 200 225 ns CL = 50pF
tMR Pulse Width MR 500 600 ns See Switching Time

tSET Input Data Setup Time 60 75 ns Waveforms 1,2, 3

tHOLO Input Data Hold Time 75 90 ns
tEN Output Enable Time 150 190 ns

Data is received in serial form at the Rlnput. When no data least significant bit RBR1. A logic high on oError indicat-
is being received, Rlnput must remain high. The data is es overruns. An overrun occurs when DReady has not been
clocked through the RRClock. The clock rate is 16 times cleared before the present character was transferred to the
the data rate. ® A low level on DR Reset clears the RBRegister. ©
1 clock cycle later DReady is reset to a
DReady line. ® During the first stop bit data is transferr- logic high, and FError is evaluated. A logic high on FError
ed from the receiver register to the RBRegister. If the word indicates an invalid stop bit was received, a framing error.
is less than 8 bits, the unused most significant bits will be A logic high on PError indicates a parity error.
a logic low. The output character is right justified to the

JI:"""'
I I
..., _ 7% CLOCK CYCL

~J

®
-® ®
-, CLOCK
The receiver uses a 16X clock for timing. ®
The start bit could rical square wave, the center of the start bit will be located within
have occurred as much as one clock cycle before it was detect- ±v, clock cycle, ±-t bit or 3.125% giving a receiver margin of
ed, as indicated by the shaded portion. The center of the start 46.875%. The receiver begins searching for the next start bit at
bit is defined as clock count 7V,. If the receiver clock is a symet- the center of the first stop bit.

PIN SYMBOL DESCRIPTION PIN SYMBOL DESCRIPTION

1 VCC Positive Voltage Supply 14 FE A high level on FRAMING ERROR indicates the first
2 NC No Connection stop bit was invalid.
3 GND Ground 15 OE A high level on OVERRUN ERROR indicates the data
4 RRD A high level on RECEIVER REGISTER DISABLE received flag was not cleared before the last character
forces the receiver holding outputs RBR1-RBR8 was transferred to the received buffer register.
to a high impedance state. 16 SFD A high level on STATUS FLAGS DISABLE forces the
5 RBR8 The contents of the RECEIVER BUFFER REGISTER outputs PE, FE, OE, OR, TBR E to a high impedance
appear on these three-state outputs. Word formats state.
17 RRC The RECEIVER REGISTER CLOCK is 16X the re-
lessthan 8 characters are right justified to RBR,.
ceiver data rate.
6 RBR7 See Pin 5 - RBR8
18 DRR A low level on DATA RECEIVED RESET clears the
7 RBR6 See Pin 5 - RBR8
data received output OR to a low level.
B RBR5 See Pin 5 - RBR8 A high level on DATA RECEIVED indicates a char-
19 DR
9 RBR4 See Pin 5 - RBR8 acter has been received and transferred to the receiver
10 RBR3 See Pin 5 - RBRS buffer register.
11 RBR2 See Pin 5 - RBR8
20 RRI Serial data on RECEIVER REGISTER INPUT is
12 RBR1 See Pin 5 - RBR8 clocked into the receiver register.
13 PE A high level on PARITY ERROR indicates received MR A high level on MASTER RESET clears PE, FE, OE,
21
parity does not match parity programmed by control and OR to a tow level and sets the transmitter output
bits. When parity is inhibited this output is low. to a high level after 18 clock cycles. MR does not
clear the receiver buffer register. This input must be
pulsed at least once after power up.

PIN SYMBOL DESCRIPTION PIN SYMBOL DESCRIPTION

22 TBRE A high level on TRANMITTER BUFFER REGISTER 29 TBR4 See Pin 26 - TBR 1
EMPTY indicates the transmitter buffer register has 30 TBR5 See Pin 26 - TBR 1
transferred its data to the transmitter register and is 31 TBR6 See Pin 26 - TBR 1
ready for new data. 32 TBR7 See Pin 26 - TBR 1
23 TBRL A low level on TRANSMITTER BUFFER REGISTER 33 TBR8 See Pin 26 - TBA 1
LOAD transfers data from inputs TBR 1- TBRS into 34 CRL A high level on CONTROL REGISTER LOAD loads
the transmitter buffer register. A low to high tran- the control register.
sition on TBRL indicates data transfer to the trans- 35 PI A high level on PARITY INHIBIT inhibits parity gen-
mitter register is busy, transfer is automatically delay- eration. Parity checking and forces PE output low.
ed so that the two characters are transmitted end to 36 SBS A high level on STOP BIT SELECT selects 1.5 stop
end. bits for 5 character format and 2 stop bits for other
24 TRE A high level on TRANSMITTER REGISTER EMPTY lengths.
indicates completed transmission of a character in- 37 CLS2 These inputs program the CHARACTER LENGTH
cluding stop bits. SELECTED ICLSI low CLS2 low 5 bits) ICLS1 high
25 TRO Character data, start data and stop bits appear serially CLS2 low 6 bits) ICLSl low CLS2 high 7 b;ts) ICLS1
at the TRANSMITTER REGISTER OUTPUT. high CLS2 high S bits)
26 TBR1 Character data is loaded into the TRANSMITTER 38 CLSI See Pin 37 - CLS2
BUFFER REGISTER via inputs TBR1-TBRS. Fa, 39 EPE When PI is low, a high level on EVEN PARITY EN-
character formats less than S bits the TBRS, 7, and 6 ABLE generates and checks even parity. A low level
inputs are ignored corresponding to the programmed selects odd parity.
word length. 40 TRC The TRANSMITTER REGISTER CLOCK is 16X the
27 TBR2 See Pin 26 - TBR 1 transmit data rate.
28 TBR3 See Pin 26 - TBR 1
 C,
SKIP
DEVin
MEMSEL
XTC
lXMAR
DX1'
DX10
OX.
ox.
OX,
ox.
ox.
OX.
OX3
OX2
OX,
ox.
llJll O~C
.... ~. O~C
.. ~z 1!~~II~~~=c~c~cc

READ 1 RRD
ORR
WRITE' TR l
31 SENSE t DR
~ :z T

RB8

CONTROL CONTROL
HD-6402 HD-6402
CONTROL
RBl

FIGURE 1 FIGURE 2 FIGURE 3

Data Input Cycle Control Register Load Cycle Status Flag Output Enable Time
or Data Output Enable Time
m HARRIS
CMOS PROGRAMMABLE
HD-4702
BIT RATE GENERATOR

Pinout
TOP VIEW

• HD-4702 - PROVIDES 13 COMMONLY USED BIT RATES

QO VCC
• USES A 2.4576MHz CRYSTAL/INPUT FOR STANDARD FREQUENCY
Q1 1M
OUTPUT (16 TIMES BIT RATE)
02 So
• TTL COMPATIBLE - OUTPUT WILL SINK 1.6mA

• LOW POWER DISSIPATION 4.5mW TYP. @2.4576MHz ECP S1

CP S2
• CONFORMS TO EIA RS-404
• ONE HD-4702 CONTROLS UP TO EIGHT TRANSMISSION Ox S3
CHANNELS IX Z
• INITIALIZATION CIRCUIT FACILITATES DIAGNOSTIC FAULT
GND CO
ISOLATION

• ON-CHIP INPUT PULL-UP CIRCUIT PIN NAMES

CP External Clock Input
ECp External Clock Enable
I nput (Active Low)
Ix Crystal Input
1M Multiplexed Input
So - S3 Rate Select Inputs
CO Clock Output
Ox Crystal Drive Output
QO-Q2 Scan Counter Outputs
Z Bit Rate Output
The HD-4702 Bit Rate Generator provides the necessary clock signals
for digital data transmission systems, such as a UART. It generates 13
commonly used bit rates using an on-chip crystal oscillator or an external
Truth Tables
input. For conventional operation generating 16 output clock pulses
per bit period,the input clock frequency must be 2.4576MHz (i.e. 9600
Baud x 16 x 16, since there is an internal.;.-16 prescaler). A lower input
frequency will result in a proportionally lower output frequency.
L Clocked from IX
n....n. Clocked from CP
The HD-4702 can provide multi-channel operation with a minimum of H Continuous Aeset
.r1.. Resllt During ,It CP" HIGH Time
external logic by having the clock frequency CO and the +B prescaler
outputs 00, 01, 02 available externally. All signals have a 50% duty NOTE: Actual output freQuency is 16 times tt1e
indicated Output Rate, Illuming. clock
cycle except 1BOO Baud, which has less than 0.39% distortion and 3600
frequency of 2.4576MHz.
Baud, which has less than 0.7B% distortion.
H •• HIGH Level
The four rate select inputs (SO-S3) select which bit rate is at the output L •• LOW Level
X •• Don't care
(Z). The table lists select code and output bit rate. Two of the 16 for J""L •• 1st HIGH level Clock Pulse
after ECP goes LOW
the HD-4702 do not select an internally generated frequency, but select
J1..J1 '"'Clock Pulse
an input into which the user can feed either a different frequency, or a
static level (High or Low) to generate "ZERO BAUD".

The bit rate most commonly used in modern data terminals (110, 150,
OUTPUT
300, 1200, 2400 Baud) require that no more than one input be grounded 535251 so RATE III
for the HD-4702, which is easily achieved with a single 5-position switch.
L L L L MUX INPUT IIMI <D
L L L H MUX INPUT (1M)
L L H L 50 BAUD
The HD-4702 has an initialization circuit which generates a common L H H 75 BAUD
L
master reset for all flip-flops. This signal is derived from a digital L H L L 134.5 BAUD
L H L H 200 BAUD
differentiator that senses the first high level on the CP input after the ECp L H H L 600 BAUD
input goes low. When ECp is high, selecting the crystal input, CP must L H H H 2400 BAUD
H L L L 9600 BAUD
be low. A high level on CP would apply a continuous reset. H L L H 4800 BAUD
H L H L 1BOO BAUD
H L H H 1200 BAUO
For the HD-4702, all inputs except IX have on-chip pull-up circuits H H L L 2400 BAUD
which provide TTL compatibility and eliminate the need to tie a perm- H H L H 300 BAUD
H H H L 150 BAUD
anently high input to VCC. H H H H 110BAUO

CAUTION: These devices ere sensitive to electronic discherge.

Proper I.C. hendling procedures should be followed.
 Supply Voltage +8.0V
Input or Output Voltage Applied (GND -0.3Vl to (VCC +O.3V)
Storage Temperature Range -650C to +1500C
Operating Temperature Range
Industrial HD-4 702-9 -400C to +850C
Military HD-4702-2/8 -550C to +1250C
Operating Voltage Range +4 to +7V

D.C.: VCC ~ 5V ± 10%; TA = Industrial or Military.

A.C.: VCC = 5V; TA = 250C.

HD-4102-2 HO-4702-9

SYMBOL PARAMETER MIN TVP MAX MIN TVP MAX UNITS TEST CONDITIONS

vee vee
VIH Input High Voltage 70" 70% V

VIL Input Low Voltage Vee Vee V

30% 30%

VOHl Output High Voltage Vee Vee V IOH~-lfJA

-.05 -.05

VOL1 Output Low Voltage 0.05 0.05 V 10L ~+11JA

IIH Input High Current -1 +1 -1 +1 I'A VI • Vec. All other pins· Ov

IlL INPUT (1) (all other -30 -100 -30 -100 I'A
LOW inputs)
'ILX CURRENT (IX inputs) -1 +1 -1 +1 I'A VI • O. All other pins - Vec
IOHX OUTPUT (OX) -<l.' -<l.' mA VQUT - Vec -.5 Input at a or Vec
IQHl HIGH (all other outputsl -1.0 -1.0 mA VaUT '" 2.SV per Logic Function
IOH2 CURRENT (alt other outputs) -<l.3 -<l.3 mA VaUT = Vec -.5 or Truth Table

lalX OUTPUT IOXI 0.1 0.1 mA VaUT -.4V

LOW
CURRENT (all other outputs) 1.6 1.6 mA VOUT = .4V
'OL
SUPPLY ()) 1500 1500 I'A ECP'" Vec. CP"" O. All other inputs· GND
Ice CURRENT 1000 1000 I'A 'EcP· VCC, CP· 0, All other inputs· VCC
(STATIC!

tPLH Propagation Delay, 300 300 ns CL~7pF on Ox 12>

tPHL IX to CO 250 250 ns

tPLH Propagation Delay, 2'5 215 ns CL·15pF,lnput

tPHL CP to CO 195 195 ns Transition Times ~ 20ns

tPLH Propagation Dalay, \§) \§) ns

tPHL CO to On ns

tPLH Propagation Delay, 75 75 ns

tPHL Co to Z 65 65 ns

tTLH Output Transition 80 80 ns

tTHL Time (except OX) 40 40 ns

tPLH Propagation Delay, 350 350 ns

tPHL IX toCO 275 275 ns CL~7pF on Ox 12>
tPLH Propagation Delay, 260 260 ns CL - 5OpF, Input
tPHL CP to CO 220 220 n. Transition Times ~20nl

tPLH Propagation Delay, ® ® ~ns

tPHL Co to On ns

tPLH Propagation Delay, 85 85 ns

tPHL CO to Z 75 75 ns

tTLH Output Transition 160 160 ns

tTHL Time (except OX) 75 75 ns

ts Set-Up Time, Select to CO 350 350 ns

th Hold Time, Select to CO 0 0 ns CL57pF on ox 12>
ts Set-Up Time, 1M to CO 350 350 ns CL • 15pF,Input
lh Hold Time, 1M to CO 0 0 ns Transition Times 520ns

twCP(L) Minimum Clock Pulse-Width 120 120 ns

twCP(H} Low and High Q> ~ '20 120 ns

twCP1LI Minimum IX Pulse Width, '60 160 n.

twCP1H) Low and High ~ '60 '60 n.

Input Current and Oulescent Power Supply Current are relatively higher for this device because of active pull-up circuits on all
inputs except IX. This Is done for TTL compatibility.
Propagation Delays (tPLH and tPHL) and Output Translstion Times (tTLH and tTHLl will change with Output Load Capacitance
(eL). Set-Up Times (ts), Hold Times (th), and Mininum Pulse Widths (tw) do not vary with load capacitance.
The first High Level Clock Pulse after ECP goes Low and must be at least 350ns long to guarantee reset of all Counters.
It Is recommended that input rise and fall times to the Clock Inputs (CP, IX) be less than 161Js.
For multichannel operation, Propagation Delay (CO to On) plus Set-Up Time, Select to CO, Is guaranteed to be ~ 367ns.
 r-:: tw(H) =T-twILI-j
CP/1X
-----"
~ '50% .y 50%

r--------..,
I I
r - - - -;O~N;E;N;";O;K- - - f MULTiPLExER"

I
OSCILLATOR
CIRCUIT I
I I@@@@@'
o IX
I
I
I
I
:
I
'M So S, Sz S3

o Ox
I
L ...J
I I

(VECP

o CP

r----------------, 5 ZOO
I J
I I 6 600
I I
I I 7 2400 o Q
I I FF
I I B 9600
CP
: IMR MR
9 4800
: INITIALIZATION i
L __ ~~':!.T ..1 '0 1800

1200
"
'Z 2400

,.
13 300

'50

'5 110

Vec· PIN 16
GND - PIN 8
O· PIN NUMBER
 eight different frequency signals. The 93L34 8 Bit Ad-
dressable Latch, addressed by the same Scan Counter Out-
Figure 1 shows the simplest application of the HD-4702.
puts, re-converts the multiplexed single Output (Z) of the
This circuit generates one of five possible bit rates
HD-4702 into eight parallel output frequency signals.
as determined by the setting of a single pole, 5-position
In the simple scheme of Figure 2, input S3 is left open
switch. The Bit Rate Output (Z) drives one standard TTL
(HIGH) and the following bit rates are generated:
load or four low power Schottky loads over the full tem-
perature range. The possible output frequencies correspond 00: 110 Baud 01: 9600 Baud 02: 4800 Baud
to 110, 150, 300, 1200, and 2400 or 3600 Baud. For many
03: 1800 Baud 04: 1200 Baud aS: 2400 Baud
low cost terminals, these five bit rates are adequate.
06: 300 Baud 07: 150 Baud
SIMULTANEOUS GENERATION
OF SEVERAL BIT RATES
Other bit rate combinations can be generated by changing
Figure 2 shows a simple scheme that generates eight bit the Scan Counter to Selector interconnection or by insert-
rates on eight output lines, using one HD-4702 and ing logic gates into this path.
one 93L34 Bit Addressable Latch. This and the following
applications take advantage of the built-in scan counter
(prescaler) outputs, As shown in the block diagram, these Though a 19200 Baud signal is not internally routed to
outputs (00 to 02) go through a complete sequence of the multiplexer, the HD-4702 can be used to generate
eight states for every half-period of the highest output this bit rate by connecting the 02 output to the 1M
frequency (9600 Baud). Feeding these Scan Counter input and applying select code. An additional 2-input
Outputs back to the Select Inputs of the multiplexer causes NOR gate can be used to retain the "Zero Baud" feature
the HD-4702 to interrogate sequentially the state of on select code 1 for the HD-4702 (See Figure 3).

110 Baud
150 Baud
300 Baud
1200 Baud
2400 Baud

FIGURE 1
Switch selectable bit rate ganer.tor
configuration providing five bit rates.

TABLE 3
CRYSTAL SPECIFICATIONS

Frequency 2.4576 MHz "AT" Cut

Series ResIstance (MaxI 250
Unwanted Modes -G.OdS (Mini
Type of Opera lion Parallel
Load Capacllance 32pF +0.5

FIGURE 3
19200 Baud Operation
Quality Control 6-2

Quality Assurance 6-4

The Product Assurance Department at Harris Semiconductor Products Group is responsible
for assuring that the quality and reliability of all products shipped to customers meet their
requirements. During all phases of product fabrication, there are many independent visual
and electrical checks performed by Product Assurance personnel.

Prior to shipment, a final inspection is performed at Quality Assurance Plant Clearance to

insure that all requirements of the purchase order and customer specifications are met.

The following military documents provide the foundation for HARRIS Product Assurance
Program.

MIL-M-38510D "General Specification of Microcircuits"

M I L-Q-9858A "Quality Program Requirements"
MI L-STD-883B "Test Methods and Procedures for Microelectronics"
NASA Publication 200-3 "Inspection System Provisions"
MI L-C-45662A "Calibration System Requirements"
MI L-I-4508A "Inspection System Requirements"

The Harris Semiconductor Reliability and Quality Manual, which is available upon request,
describes the total function and policies of the organization to assure product reliability and
quality. All customers are encouraged to visit the Harris Semiconductor facilities and survey
the deployment of the Product Assurance function.

The Quality Control Department consists of Process Control with Chemical Mix as an avail-
able supporting service.

Process Quality Control is responsible for quality engineering and controls in the wafer
processing modules, assembly, mask and materials production areas, and electrical wafer
probe.

The primary responsibilities of Process Quality Control are:

a. To establish and maintain effective controls for monitoring manufacturing processes

and equipment

c. to initiate, design, and develop statistically controlled experiments to further improve

product reliability and quality levels.

Statistical control charts on processes and operating procedures are used in the manufac-
turing areas and in the evaluation of process and product parameters utilized to qualify
new processes.

When necessary, fixed gate inspections are permanently employed to assure specified quality
levels.

On a regular basis, process audits are performed to verify conformance to operating pro-
cedures.
Statistical control charts are maintained on processes and workmanship for all phases of
assembly and environmental testing.

PROCESS CONTROL
WAFER FABRICATION - GENERAL PROCESS FLOW

o PRODUCTION

o PRODUCTION INSPECTION

o QUALITY CONTROL LOT ACCEPTANCE

£. QUALITY CONTROL MONITOR/AUDIT

The primary responsibility of the Quality Assurance Department is to assure that all de-
livered products meet the rigid standard of reliability and quality of Harris Semiconductor
Products Group. The Quality Assurance department is responsible for process control and
product quality from product test to shipment. Random sampling of products at specified
points and intervals is used to ensure quality. This includes performance and analysis of
sample electrical testing (Group· A) and environmental and life testing (Groups B, C and 0).
In addition, mechanical and visual inspections specified by the Quality Assurance Test Plans,
as well as customer and military specifications are performed. The random selection and
distribution of samples, the routing of devices through specified testing and adherence to
inspection programs are controlled and implemented by Quality Assurance.

All packaged microcircuits are marked by a code indicating the date the lot was sealed.
This code provides product traceability and meets customer date coding requirements.
Traceability is maintained through lot acceptance, testing and shipment to the customer.

Harris Semiconductor Products Group employs a comprehensive approach to reliability

evaluation to ensure that reliability is designed and built into all products. This approach
is referred to as the Reliability Evaluation Procedures and outlines the basic guidelines for
evaluation of the total inherent reliability capability of all products types. The Reliability
Evaluation Procedures are applied as an overlay during the early product development phase,
subsequent prove-in via preproduction and final maturity in the manufacturing of all new
product types. They also provide guidelines for evaluation of new process technologies
deployed in all applicable products. The Reliability Evaluation Procedures also encompass
a package qualification procedure, and the "Add-on" program which is a quarterly reliabil-
ity monitor of all process groups. These documents are available upon request. The follow-
ing test matrix (Table 1) outlines the minimum requirements necessary for product qualifi-
cation.
 Design New New New New Exist Exist Exist Exist
Package New New Exist Exist New New Exist Exist
Process New Est. New Est. New Est. New Est.

Abuse Tests
X X X X X X X
20 Units

Max. Ratings
X X X X X X
20 Units: No Failures

86/86 or Autoclave
50 Units: No Failures X X X X X X

Constr. Analysis
X X X X X X X X
5 Units: No Failures

Centrifuge
50 Units: No Failures X X X X

Ele. Charac.
20 Units: No Failures X X X X X X X

ESD Immunity
20 Units: No Failures X X X X X X X

Fig. Test
20 Units: No Failures X X X X X X

HTOL Sample Groups 200 200 200 200 200 200 200 200
(min) (min) (min) (min) (min) (min) (min) (min)

Latch-up
20 Units: No Failures X X X X X
Lead Integrity
20 Units: No Failures X X X X X X

Mech. Charac.
20 Units: No Failures X X X X

Mech. Schock
50 Units: No Failures X X X X

Moisture Resist
50 Units: No Failures
X X X X

Oja/Ojc
X X X X
20 Units

Solvent Resistance
4 Units: No Failures
X X X X

Solderability
X X X X
20 Units: No Failures

Temperature Cycling
X X X X
50 Units: No Failures

Thermal Shock
50 Units: No Failures X X X X

Vibration
50 Units: No Failures
X X X X
The HARRIS CMOS product line has had a continual evolution of new and enhanced pro-
cess~. From SAJI I (Self Aligned Junction Isolated) to the most recent SAJI V process.
There has been an ongoing effort to increase performance, density and reliability. The cur-
rent RAM products (4K and up) along with the microprocessors and peripheral families
utilize the SAJI IV, scaled SAJI IV, and SAJI V processes. Table II is a summary of recent
reliability data taken on the various SAJI processes. Table III lists the activation energies
of the most common defects associated with the CMOS products. Table IV gives a break-
down of field returns by failure mechanism.

At Harris, accelerated life Tests are utilized to estimate the field failure rate of our product.
A typical life test consists of 200 devices tested at +1250C to +1500C ambient, dynamic
operation, 5.5V to 6.5V, for 1000 hours. All failures are carefully analyzed to determine
the failure mechanism and associated activation energy (EA) utilizing the arrehnius equation
derating factors back to +550C ambient, 5.5volts operation are determined.
Derating factor = D. F. = e -(EA) (..1- _
K T2
-D
T1) where EA = Activation Energy
K = Soltzman's Constant
T2 = Life Test Junction Temp.
T1 = Junction Temp. at +550C
Ambient
Projected field failure rates are calculated at 60% and 95% confidence levels. This means
that either 60% or 95% of the product will meet or exceed the reliability demonstrated in
the test. We also ensure that the failure rate is decreasing with time to prevent any wear-
out mechanism from reaching our customers.

SAJI Device Feilure Rate. (%/K Hours)

Process No. of Hours No. of EA @TA=+550C
Type Devices (+1250C) Failures (ev) Observed 6u~ (;onTiaence 90~ (;onTiaence

I 2,046 4,019,046 1 1.0ev

4 .6 ev
6 .5ev
.0007 .001 .002

1,515 1,791,668 2 1.0ev

" 1 .7ev
2 .6ev
2 .5ev
.004 .013 .Q28

III 440 938,844 0 - .002 .005 .015

IV 687 740,464 1 .6ev

2 .5ev
.020 .025 .044

Scaled 1740 3,387,860 21 1.0ev

IV 2 .7ev
3 .6ev
6 .5ev
.012 .015 .025
 TABLE III CMOS PRODUCTS-
ACTIVATION ENERGY

Activation
Failure Mechanism Energy lEA)

Oxide Defects O.5ev

Defective Apertures O.6ev

Photoresist Flaws O.7ev

Assembly Defects O.Bev

Ionic Contamination 1.0ev

ASSEMBLY DEFECTS

EOS

5 10 15 20 25 30 35

% OF RETURNS
In 1972 Harris Semiconductor began development of a SAJI CMOS process that would
become the basis for all Harris CMOS devices. In 1973, Harris perfected the SAJI I process
and proved its potential for high speed, low power and high packing density. By 1975,
the SAJI I process had proved to be successful in volume production of high density CMOS
components as evidenced by the reliability of the 1K CMOS RAMs. SAJI I utilizes a single
level of polysilicon and a single level of metal interconnect.

To achieve higher packing density, SAJI II was implemented in the 4KCMOSRAMsin 1978.
SAJI II represents the evolution of SAJI processes into a second generation, incorporating
smaller (scaled) devices and a second level of polysilicon interconnect, labeled N + POLY 2.
Buried contacts allow the interface of multiple interconnect levels. This process relies
upon the thick oxide for device isolation and guardbanding.
 .-
DEEP
OXIDE
-L

In 1980, SAJI III was introduced with the redesigned (2nd generation) 4K CMOS RAMs.
SAJI III advances include device scaling for increased packing density and die size reduc-
tions, and selective oxidation processing, which exhibits more planar device surface struc-
tures improving step coverage and device reliability. The selective oxidation process involves
the deposition of a nitride layer in the gate region of each device. This nitride layer pro-
hibits the growth of oxide in the gate region. As a result, thick oxide is not grown across
the entire face of the die but only in areas not inhibited by the nitride layer. Thick oxide
growth now occurs between devices and below the surface of the die. The lower inherent
capacitance in the gate area due to a thinner gate oxide results in increased device speed.
Previous SAJI processes are easily retrofitted to this process.

GOLD BACK

HARRIS PATENTED
ION IMPLANTED GUARD RINGS

The next generation process was SAJI IV. SAJI IV features the selection oxidation and
planar surface characteristics of SAJI III while adding further device scaling with the option
of high resistivity substrates which reduces internal junction capacitances and increases
speed. Self-aligned implanted P+ and N+ guardbands were also added, which increased the
isolation between devices and reduced adjacent device interaction and increased packing
density.
Since the introduction of MOS, manufacturers have searched for effective and safe ways
of handling this voltage sensitive device. High input impedance of CMOS, coupled with
gate-oxide breakdown characteristics, result in susceptibility to electrostatic charge damage.

Figure 2 shows a C'ffoss-section, of a silicon gate MOS structure. Note the very thin oxide
layer (:::::500-1 OOOA) present under the gate material. Actual breakdown voltage for this
insulating layer ranges from 70V to 100V.
Handling equipment and personnel, by simply moving, can generate in excess of 10kV of
static potential in a low humidity environment. Thus, static voltages, in magnitudes suf-
ficient to damage delicate MOS input gate structures, are generated in most handling en-
vironments.
A failure occurs when a voltage of sufficient magnitude is applied across the gate oxide
causing it to breakdown and destruct. Molten material then flows into the void creating a
short from the gate to the underlying silicon. Such shorts occur either at a discontinuity
in doping concentration, or at a defect site in the thin oxide. If no problems appear in the
oxide, breakdown would most likely occur at gate/source, or gate/drain intersection coin-
cidence due to the doping concentration gradient.
Noncatastrophic degradation may result due to overstressing a CMOS input. Sometimes
an input may be damaged, but not shorted. Most of these failures relate to damage of the
protection network, not the gate, and show up as increased input leakage.

Figure 2 - Silicon-gate PFET structure cross-section shows the

heavily doped source and drain region. They are separated by a
narrow gap over which lies a thin-gate oxide and gate material.

·NOTE: 151.(Angstrom = 10-8 em)

Voltage Limiting Input Protection

During the evolution of monolithic MOS, manufacturers developed various protection

mechanisms that are an integral part of the circuit. However, several of these earlier tech-
niques have been replaced by improved methods now in use. The object of most of these
schemes is to prevent damage to input-gate structures by limiting applied voltages.

Recent CMOS designs employ a dual-diode concept in their input protection networks.
Figure 3 illustrates such a protection circuit.

One characteristic of junction-isolated CMOS protection circuits is the ~ 2000 current

limiting resistor. Cross sectional area of the metall ization leading to the resistor, and the
area of the resistor are, therefore, designed to absorb discharge energy without sustaining
permanent damage. This dual-diode protection has proved very effective and is the most
commonly used method in production today.
To protect input device gates against destructive overstress by static electricity accumulating
during handling and insertion of CMOS products, Harris provides a protection circuit on all
inputs. The general configuration of this protection circuit is shown in Figure 3.

~200n
POLYSILICON
RESISTOR

NOTE: FOR CMOS, VOO IS MOST

POSITIVE; Vss IS MOST
NEGATIVE.

Figure 3 - Junction isoleted duel-diode protection networks ere most

commonly used in todey's CMOS circuits.

Both diodes to the VDD and VSS lines have breakdown voltages averaging between 35 and
40 volts. Excessivestatic charge accumulated on the input pin is thus effectively discharged
through these diodes which limit the voltage applied from gate to drain and source. The
200 ohm resistor provides current limiting during discharge. Depending on the polarity of
the input static charge and on which of the supply pins aregrounded, the protective diodes
may either conduct in the forward direction or breakdown in the reversedirection.
In order to test this concept, step stress tests have been performed at Harris using an approx-
imate equivalent circuit to simulate the static charge encountered in handling operations.
The equivalent circuit consists of a 100pF capacitor in series with a 1.5K ohm resistor
and is considered the rough equivalent of a human body. Step stressing takes the form of
charging the capacitor to a given voltage and then discharging it into an input pin of the
CMOS device under test according to the sequence given in MI L-M-38510.
Stress Voltege Cumulative Failures
500 o
700 o
1000 o
1400 1
1600 3
1800 4
There are two trade-offs to consider when fabricating an input protection scheme, namely
effectiveness of the overvoltage protection and performance of the overall circuit. It is
obvious that increasing the series resistance and capacitance at an input limits current and
this, in turn, increases the input protection's ability to absorb the shock of a static dis-
charge. However, such an approach to protection can have a significant effect on circuit
speed and input leakage. The input protection selected must therefore provide a useful
performance level and adequate static-charge protection.
Commonly used MOS-input protection circuits all have basic characteristics that limit
their effectiveness. The zener diodes, or forward-biased pn-junctions, employed have
finite turn-on times too long to be effective for fast rise-time conditions. A static dis-
charge of 1.5kV into a MOS input may bring the gate past its breakdown level before the
protection diodes or zener becomes conductive.
Actual turn-on times of zeners and pn-diodes are difficult to determine. It is estimated
that they are a few nanoseconds and a few tens of picoseconds, respectively. A low-im-
pedance static source can easily produce rise times equal to or faster than these turn-on
times. Obviously the input time constant required to delay buildup of voltage at the gate
must be much higher for zener diodes or other schemes having longer turn-on times.

Consider an example. Figure 4 shows a test circuit that simulates the discharge of a 1.5kV
static charge into a CMOS input. Body capacitance and resistance of the average person
is represented by a 100pF capacitor through 1.5kn. Switch A is initially closed, charging
100pF to 1.5kV with switch B open. Switch A is opened, then B is closed, starting the
discharge. With the 1.5Kn x 5pF time constant to limit the charge rate at the DUT input,
it would take approximately 350psec to charge to 70V above VDD. Diode turn-on time
is much shorter than 350psec, hence the gate node would be clamped before any damage
could be sustained.

I
I
I
I
~~I
1.5kV A 1.. B0--<>:
100PF !
I Vss

TEST SETUP
:

i DEVICE
Vss

UNDER TEST (OUT)

Figure 4 - Input protection network test setup illustrates how diode clamping
prevents excessive voltages from damaging the CMOS device.
There is no completely foolproof system of chip-input protection presently in production.
If static discharge is of high enough magnitude, or of sufficiently short rise-time, some
damage or degradation may occur. It is evident, therefore, that proper handling procedures
should be adopted at all times.

• Use conductive work stations. Metallic or conductive plastic tops on work benches
connected to ground help eliminate static build-up.

• Smocks, clothing, and especially shoes of certain insulating materials (notably nylon)
should not be worn in areas where devices are handled. These materials, highly di-
electric in nature, will hold or aid in the generation of a static charge.

• Control relative humidity to as high a level as practical. A higher level of humidity

helps bleed away any static charge as it collects.

• Ionized air blowers reduce charge build-up in areas where grounding is not possible
or desirable.

• Devices should be in antistatic conductive carriers during all phases of transport. If

antistatic carriers are used the devices and carriers should be in a static shielding bag.

• In automated handling equipment, the belts, chutes or other surfaces the leads contact
should be of a conducting nature. If this is not possible, ionized air blowers may be a
good alternative.

Harris currently ships all CMOS products in Benstat TM tubes placed inside static shielding
bags. Packing materials are all antistatic.

Monolithic CMOS integrated circuits employ a single-crystal silicon wafer into which
FET sources and drains are implanted. For complex functions many thousands of tran-
sistors may be required and each must be electrically isolated for proper operation.

Junction techniques are commonly used to provide the required isolation - each switching
node operating reverse-biased to its respective substrate material. Additionally, as pre-
viously mentioned, protection diodes are provided to prevent static-charge related damage
where inputs interface to package pins. Forward-biasing any of these junctions with or
without power applied may result in malfunction, parametric degradation, or damage
to the circuit.

High currents resulting from an excessive forward-bias can cause severe overheating local-
ized to the area of a junction. Damage to the silicon, overlying oxide and metallization
can result.
BIPOLAR PARASITICS
Care must always be exercised not to forward-bias junctions from input or output pads.
A complex and potential defect phenomenon is the interaction of a npn/pnp combin-
ation a la SCR (Figure 5). Forward-biasing the base-emitter junction of either bipolar
component can cause the pair to latch up if ,8npn x ,8pnp ~ 1. The resultant low imped-
ance between supply pins can cause fusing of me.tallization or over-dissipati.on of the chip.
Figure 5 shows how an SCR might be formed. The p+ diffusion labeled INPUT is connected
to aluminum metallization and bonded to a package pin. Biasing this point positive with
respect to VDD supplies base drive to the pnp through R2. Although gain of these lateral
devices is normally very low, sufficient collector current may be generated to forward-
bias and supply substantial base current to the vertical npn parasitic. Once the pair has
been activated, each member provides the base current required to sustain the other. A
latched condition will be maintained until power is removed or circuit damage disables
further operation.

Figure 5 -Improper biasing can latch-up this SeR configuration. A

p+ guard ring is commonly used to kill lateral pnp action. This ring is
diffused into the surface at the junction of p- and n- silicon.

A system using CMOS devices must have reliability designed in. No amount of testing can
guarantee long term reliability when poor design practices are evident .
• Never apply signals which exceed maximum ratings to a CMOS circuit before or after
power has been turned on (to prevent latch-up)
• Supply filter capacitance should be distributed such that some filtering is in close
proximity to the supply pins of each package. Testing has shown 0.01 fJF/package to be
effective in filtering noise generated by most CMOS functions.
• CMOS signal lines are terminated at the driving end by a relatively high impedance when
operating at the low end of the supply voltage range. This high-impedance termination
results in vulnerability to high-energy or high-frequency noise generated by bipolar or
other non-CMOS components. Such noise must be held down to manageable levels on
both CMOS power and signal lines.

• Where CMOS must interface between logic frames or between different equipments,
ground differences must be controlled in order to maintain operation within absolute
maximum ratings.
 • Capacitance on a CMOS input or output will result in a forward-bias condition when
power is turned off. This capacitance must discharge through forward-biased input or
output to substrate jun'ctions as the bus voltage collapses. Excessivecapacitance (thou-
sands of pF) should be avoided as discharging the stored energy may generate excessive
current densities during power-down.
• Where forward-biasing is inevitable, current limiting should be provided. Current should
not be permitted to exceed 1mA on any package pin excluding supply pins.

All CMOS is susceptible to damage due to electrical overstress. It is the user's respons-
ibility to follow a few simple rules in order to minimize device losses.
First, select a source for the CMOS device that employs an effective input protection
scheme. This will allow a greater margin of safety at all levels of device handling since
the devices will not be quite so prone to static charge damage. Next, he should apply a
sound set of handling and design rules. At minimum, this will eliminate electrical stres-
ing or hold it to manageable levels.
With an effective on-chip protection scheme, good handling procedures and sound design,
users should not lose any CMOS devices to electrical overstress.
Advantages of Standard Flows 7-3

Standard Manufacturing Flows 7-3

CMOS Military Product Description 7-4

High reliability, the Military and Harris Semiconductor have enjoyed a cooperative relation-
ship for more than a decade. Over ten years ago, Harris was the first to manufacture and,
subsequently, JAN-qualify bipolar PROMS. Harris currently has government certified man-
ufacturing lines producing a variety of high-rei products.

Early commitment to CMOS technology has made Harris the premier manufacturer of high
performance CMOS VLSI devices. HARRIS fast, low power components are designed to
offer significant power reduction, lower operating temperatures, improved reliability, re-
duced packaging costs and improved performance for extended temperature range applica-
tions. For the military/hi-rei market, Harris also has standard CMOS hi-rei grades which
accommodate the requirements of virtually all applications.

Wherever feasible, and in accordance with good value engineering practice, it is beneficial to
the IC user to specify Hi-Rei device grades based on one of the five standard Harris man-
ufacturing flows. These generally meet or exceed the requirements of the majority of appli-
cations.

Advantages gained by basing designs on the standard data book or slash sheet (as applicable)
electrical limits and calling out standard as opposed to custom flows include:

• LOWER COST than the same or an equivalent flow executed on a custom basis. This
results from the higher efficiency achieved with a constant product flow and the elim-
ination of such extra cost items as special fixturing, test programs, additional handling,
and added documentation.

• FASTER DELIVERY since the manufacturer often can supply many items from in-
ventory and, in any case, can establish and maintain a better product flow when there
is no need to restructure process and/or test procedures.

• INCREASED CONFIDENCE in the Hi-Rei devices, as a continuing flow of a given

Hi-Rei product permits the manufacturer to monitor trends which may influence end-
product performance or reliability and to effect necessary corrective action.

Harris has developed standard flows which should satisfy most requirements. Produced
in accordance with established manufacturing flows, the standard Harris Hi-Rei grades and
their indicated areas of application are as follows:

• DASH-9+ [PLUS] products are processed to Harris high reliability test conditions
and are designed for industrial use. Performance is guaranteed over a temperature
range of -40oC to +850C. For added reliability, devices packaged in ceramic (CERDIP)
are burned-in for 160 hours at +1250C, while the burn-in requirement for epoxy
packaged parts is 96 hours at +1250C.

• DASH-8 products are designed for general use in the military environment, with per-
formance guaranteed over a temperature range of -550C to +1250C. Included in
Harris DASH-8 processing is 160 hours of burn-in at 1250C.

• DESC drawing parts are manufactured in accordance with drawings provided by the
Defense Electronic Supply Center which call out full military screening and lot accep-
tance testing requirements.
MILITARY PART PIN PAGE
NUMBER FUNCTION COUNT REF

8/16-BIT MICROPROCESSORS
MD80C86/B 16 BIT CMOS MICROPROCESSOR (5MHz) 40 3-4
MD80C86-2/B 16 BIT CMOS MICROPROCESSOR (8MHz) 40 3-4
MD80CB8/B 8 BIT CMOS MICROPROCESSOR (5MHz) 40 3-96
MD80C88-2/B 8 BIT CMOS MICROPROCESSOR (8MHz) 40 3-96

80C86/88 PERIPHERAL CIRCUITS

MD82C52/B CMOS SERIAL COMMUNICATION INTERFACE 28 3-27
MD82C54/B CMOS PROGRAMMABLE INTERVAL TIMER 24 3-28
MD82C55A/B CMOS PROGRAMMABLE PERIPHERAL INTERFACE 40 3-43
MD82C59A/B CMOS PRIORITY INTERRUPT CONTROLLER 28 3-62
MD82C37A/B CMOS DMA CONTROLLER 40 3-97

80C86/88 BUS SUPPORT CIRCUITS

MD82C82/B CMOS OCTAL LATCHING BUS DRIVER 20 3-77
MD82C83/B CMOS OCTAL LATCHING INVERTING BUS DRIVER 20 3-98
MD82C84A/B CMOS CLOCK GENERATOR/DRIVER 18 3-82
MD82C86/B CMOS OCTAL BUS TRANSCEIVER 20 3-100
MD82C87/B CMOS OCTAL INVERTING BUS TRANSCEIVER 20 3-101
MD82C88/B CMOS BUS CONTROLLER 20 3-89
MD82C89/B CMOS BUS ARBITER 20 3-102

12-BIT MICROPROCESSORS
HM-6100-8 CMOS 12 BIT MICROPROCESSOR 40 4-30
HD-6120-8 CMOS HIGH PERFORMANCE 12 BIT MICRO 40 4-3

12-BIT PERIPHERAL CONTROLLERS

HD-6101-8 CMOS PARALLEL INTERFACE ELEMENT (PIE) 40
"-
4-51
HD-6121-8 CMOS I/O CONTROLLER (I0C) 40 4-22

BUS SUPPORT CIRCUITS

HD-6431-8 CMOS HEX LATCHING BUS DRIVER 16 4-59
HD-6432-8 CMOS HEX BIDIRECTIONAL BUS DRIVER 18 4-62
HD-6433-8 CMOS QUAD BUS SEPARATOR/DRIVER 16 4-65
HD-6434-8 CMOS OCTAL LATCH BUS DRIVER W/RESET 24 4-68
HD-6436-8 CMOS OCTAL BUS BUFFER/DRIVER 20 4-71
HD-6440-8 CMOS LATCHED 3 TO 8 LINE DECODER/DRIVER 18 4-74
HD-6495-8 CMOS HEX BUS DRIVER 16 4-78

SERIAL COMMUNICATION CIRCUITS

HD-4702-8 CMOS BIT RATE GENERATOR 16 5-56
HD-6402-8 CMOS UART 40 5-51
HD-6406-8 CMOS PROG. ASYNC. COMMUNICATION INTERFACE 40 5-39
HD-6409-8 CMOS MANCHESTER ENCODER-DECODER 20 5-30
HD-15530-8 CMOS MANCHESTER ENCODER-DECODER 24 5-3
HS-15530RH CMOS MANCHESTER ENCODER-DECODER (RADIATION
RESISTANT) 24 9-17
HD-15531-8 CMOS MANCHESTER ENCODER-DECODER 40 5-10
HD-15531B-8 CMOS MANCHESTER ENCODER-DECODER 40 5-10
HS-3182 CMOS ARINC 429 BUS INTERFACE LINE DRIVER CIRCUIT 16 9-28
HS-3282 CMOS ARINC 429 BUS INTERFACE CIRCUIT 40 9-29
 MILITARY STANDBY DATA RET. OPERATING
PART CON FIG- PIN ACCESS CURRENT- CURRENT- CURRENT-
NUMBER URATION COUNT TIME ICCSB ICCDR ICCOP REF

1K - SYNCHRONOUS ~
HM-6508-8 1K x 1 16 250n5 10/lA 10/lA 4mA/MHz 2-5
HM-6508B-8 1K x 1 16 180n5 10/lA 5/lA 4mA/MHz 2-5
HM-6518-8 lK x 1 18 250n, 10/lA 10/lA 4mA/MHz 2-11
HM-6518B-8 1K xl 18 180n5 10/lA 5/lA 4mA/MHz 2-11
HM-6551-8 256 x 4 22 300ns 10/lA 10/lA 4mA/MHz 2-17
HM-6551B-8 256 x 4 22 220ns 10/lA 10/lA 4mA/MHz 2-17
HM-6561-8 256 x 4 18 300ns 10/lA 10/lA 4mA/MHz 2-25
HM-6561B-8 256 x 4 18 220n5 lOIJA 10/lA 4mA/MHz 2-25

4K - SYNCHRONOUS
HM-6504-8 4K x 1 18 300ns 50/lA 25IJA 7mA/MHz 2-29
HM-6504B-8 4K xl 18 200ns 50/lA 25IJA 7mA/MHz 2-29
HM-6504S-8 4K xl 18 120ns 50/lA 25/lA 7mA/MHz 2-29
HM-6514-8 1K x 4 18 300ns 50/lA 25/lA 7mA/MHz 2-40
HM-6514B-8 1K x 4 18 200ns 50IJA 25/lA 7mA/MHz 2-40
HM-6514S-8 1K x 4 18 120ns 50/lA 25IJA 7mA/MHz 2-40

16K - SYNCHRONOUS
HM-6516-8 2K x 8 24 200ns 100IJA 50IJA 10mA/MHz 2-51
HM-6516B-8 2K x 8 24 120n5 50IJA 25IJA 10mA/MHz 2-51

16K - ASYNCHRONOUS
HM-65162-8 2K x 8 24 90n5 100>, A 40IJA 70mA 2-57
HM-65162B-8 2K x 8 24 70n5 50IJA 20/lA 70mA 2-57
HM-65172-8 2K x 8 24 90n5 100IJA 40IJA 70mA 2-70
HM-65172B-8 2K x 8 24 70n5 50/lA 20/lA 70mA 2-70

CMOS RAM MODULES

HM-6564-8 64K 40 350ns 800/lA 400IJA 28/56mA/MHz 2-85
HM-92560-8 256K 48 150n, 500/lA 350/lA 15/30mA/MHz 2-96
HM-92570-8 BUFFERED 48 250n, 600IJA 450IJA 15/30mA/MHz 2-104
256K

CMOS RADIATION HARDENED RAMS

STANDBY DATA RET. OPERATING
PART CONFIG- PIN ACCESS CURRENT- CURRENT- CURRENT- PAGE
NUMBER URATION COUNT TIME ICCSB ICCDR ICCOP REF

HS-6504RH 4K x 1 18 300ns 100/lA 50/lA 7mA/MHz 9-18

HS-6508RH 1K xl 16 300ns 100/lA - 4mA/Mtlz 9-19
HS-6514RH 1K x 4 18 200ns 250/lA 50/lA 7mA/MHZ 9-20
HS-6551 RH 256 x 4 22 300ns 100IJA - 4mA/MHz 9-21
HS-6564RH 16K x 4 40 350n, 800/lA - 32mA/MHz 9-22
RAM MODULE or 8K x 8

--
STANDBY DATA RET. OPERATING
PART CONFIG- PIN ACCESS CURRENT- CURRENT- CURRENT- PAGE
NUMBER URATION COUNT TIME ICCSB ICCDR ICCOP REF
HM-6641-8 512 x 8 24 250ns 100/lA - 10mA/MHz 2-113
HM-6616-8 2K x 8 24 120n5 100/lA - 13mA/MHz 2-118
8-2

8-3
Defense Electronics
Part 1 Microprocessor Family Turns to Low Power 8-3
Part 2 High Density LCC Packages 8-10

Computer Design
Providing CMOS Benefits to Peripheral Chips 8-17

Electron ics
Custom Microprocessor Powers Portable Workstation 8-23

Electronic Design
For Data Communication, Manchester Chip Could be the Best 8-27

Electronic Design
Industrial Controller Joins M I L-STD-1553 Bus 8-37

EON
Take a Total System Approach with CMOS Memories 8-44

EON
LCC Implementation Procedures Enhance a Valuable Technology 8-51
 Microprocessor Family
Turns to Low-Power CMOS
The BOCB6 microprocessor adds a proven design and low power to high
performance defense systems.

,\'(',\"1 Mom". Purr" in 1/''',\ IInJ-I'Uff ,writ-.' "11

mic ro/"o("('.\.\OO \I'ill ('xumillt' lhc' frun,;ti"" I~I
111(' 1011'-1'0,,'('1" XOCXtllumily 10 im/Ii,",.y .Hun-
clanl/t'ud/c',\.\ chi/I clIfl'iel' /W(·/..'ugl'.\,

Wal,t'1' .\'i('\\';t'nJ..i i.\ tI (('chnical murkc'lillg

l'l1gll1c'er with lIar";\ Corl'0fUlipl1',\ Sc'm;nll/-
ducwr Groll/>, c'\fOS Ojgilul ProtlUC"I.\ J>;\';-
,';0/1, P.o. lJox XX3, .HS 54-I.W. ,\It,thourm'.
FI.3.'YIII.

CMOS e4uivalents of existing high per-

formance circuits offer obvious ad-
vantages to the military system de-
signer -allowing immediate reduc-
tions in critical system operating
power. reduced power supply re4uire-
ments. sealable enclosures. and
lighter. higher density packaging. Sys-
tem reliability is improved due to
lower ambient and junction tempera-
tures and the high radiation tolerance
of the CMOS process. In the past.
however. this power reduction usually
came at the expense of lower sys-
tem performance.
The new gOCg6 products from
Harris Semiconductor have been de-
signed especially for high performance
military systems. Initial device specifi-
cations for the product line include 5
MH/ operation over the full-55°C to
+ 125°C temperature range. with se-
lected products available in g MHZ
versions. Upgrades of all circuits to g
MH/ compatibility are planned. MIL·
STIJ-XXJIlprocessing allows full imple-
mentation of CMOS products in
military designs.

80C86 Functional Compatibility

Full functional compatibility with
existing g086 NMOS/bipolar e4uiva- Herrl. Semiconductor will begin delivering the 80G86 mil·spec CMOS microprocessor ana
the six support chips by August. Aaaitional parts will follow into fourth quarter 1983 to
lents is provided in the 80Cg6 family. complete the family. The 80G86 is an exact replica of the NMOS 8086 processor, ana takes
Programs that test original source aavantage of existing software ana support tools.

Reprinted from DEFENSE ELECTRONICS, June 1983; © 1983 EW CommunicatIons, Inc.

8-3
devices are being used to verify func-
tionality and compatibility. In-system CMOS 80C86 Microprocessor Family
testing has been done by both the
Harris Semiconductor CMOS Applica- P.rt Desc:rtplion Scheduled
Type Av.Ullblllly
tions Group and selected external cus-
tomer sites to verify functionality in a CMOS 16-Bit CPU Aug '83
80C86
real system. real time environment
providing an additional level of com- 82C54 CMOS Programmable Interval Timer Now
patibilityassurance.
Product compatibility with existing 82C55A CMOS Programmable Peripheral Interface Now
industry standard devices and devel-
opment systems can immediately im- 82C59A CMOS Priority Interrupt Controller Now
prove system performance with re-
CMOS Octal Latch Now
-
spect to power and reliability. Life 82C82
spans of existing hardware and soft-
82C84A CMOS Clock Generator/Driver Now
ware designs can be extended by pro-
viding direct low-power. high per- 82C88 CMOS Bus Controller Now
formance upgrades for existing 8086-
based systems. HD~ CMOS PACI (UART/BRG) .. Q3CY83
The unit's hardware interface and
instruction set are compatible with 82C89 CMOS Bus Arbiter Q4CY83
proven design and de\ elopment tool>.
Software de\eloped for projecb using 82C83 CMOS Inverting Octal Latch
the HOH6can be used directly with the 82C86 CMOS Bus Transceiver Q4CY83
82C87 CMOS Inverting Bus Transceiver
HOC86 family. reducing the manpower
investment and resulting in decreased
.
development time and cost. With
standard software (Ada. Jovial. etc.)
for military. defense. and aenlspaee supply \oltage range and at the maxi- trol signals for the on-board mcmory.
applications. this soft\lare compatibil- mum rated loads. These \lorst case both CMOS RAM and non-\olatile
ity can result in significant savings in specifications insure reliable operation CMOS PROM. and for the peripheral
new and existing projects. under ad\ erse conditioos such as ex- circuib.
treme temperature variations. !luetu-
Worst Case Design for ating power supply level. and hcavy CMOS Memor)' Options
Defense Applications output load. CMOS memory circuits offer the
As with all system components. Limits specified for the 80C86 fam- designer several options. The H M-
CMOS devices best perform within ily AC and DC parameters reflect 6516. a 2K x 8 CMOS static RAM.
their specified operating conditions. maximums and minimums over the offers a low operating power of 10
The problem facing the designer is entire military (-55°C to + 125°C) mA MHZ. maximum. for military ap-
one of insuring these system operating temperature range. Capacitive loads plications. Access times as low as 120
conditions will not degrade device are 100 to 150 pF for standard periph- ns make this device compatible with
performance beyond the limits im- erals and 300 pF for the 82C82 and many high-speed applications. Where
posed by the design. Devices guar- H2C8H bus interface devices. which increased performance is necessary.
anteed to operate to specifications interface directly with the system bus. the HM-65162 asynchronous 16K
over "worst case ranges" make this These guarantees insure a system is CMOS RAM can be used with an ac-
task easier (for example. parametcr designed to worst case specifications; cess time of 70 ns. maximum.
limits guaranteed over the full tem- no performance degradation calcula- CMOS fuse link PROMS are used in
perature range and propagation de- tions for guaranteed parametcrs will this application because of the high
lays guaranteed at realistic 100 to 300 bc needed during initial design: and. reliability re4uirements of military
pF capacitive loads as opposed to 15 the system will operate properly ovcr systems. The long-term data retention
to 45 pF). All AC parameters are testcd the full specified operating ranges. characteristics of polysilicon fuses in-
and guaranteed with worst case speci- surc reliablc operation in extreme en-
fied loads on the appropriate outputs. Low-Power System Application vironments. The low power (13 mA
The HOCH6 product line has been The 80CH6 CPli. operating in the MHI for the 16K density CMOS PROM)
designed for military applieations: maximum mode. is the focal point in and 150 ns access time provide the
specific operation goals over the mili- the control module for !light naviga- performance needed for this genera-
tary temperature range were estab- tion. Non-inverting octal latches tion of CMOS systems.
lished and maintained throughout the (82C82) and transceivers (82C86) pro-
design process. Performanee is also vide the address data latching and Multiple CPUs
guaranteed at worst case conditions. buffering for the local bus. The H2CH8 Expanding system capabilities be-
including operation over the power CMOS bus controller provides the eon- yond the le\el available with a single
 (:MO$
PROM Arf''''''
!'lM-"H~
Memory 21(XR <:"'0$ "ROM>
Command
SllilnalS

l
Mode 2 ]
Strobed Control and
BidirectIonal Dlsplly
Bus 110 Processor

E ng,ne O ••
"emp ]
Fuel Pressure
Low Power
Fuel CapacIty
Power Lon System
Interrupti

Event
Count
Interrupt

MIL-STD
-1553
or Other
High-Speed
Menchelt.r
O.t. Link

rroce~sol' can he accomplislH:d in ~e\- ,"ailahle frol11 thc proccssor. I his ogics is possihle \\ ith thc full I II
~ral \lay,. I'hc addition of anothcr typc of l'onfiguration eliminatcs thc compalihilit, prcsclll on thc XOCX6
CI'I ,uh",tcm. along \\ith thc appro- nccd lor thc X2CXX hus conll'llllcrs products. I'his compatihility on hoth
priate interrace to allo\\ common ac- and Ihc additional l11ultiproccssor inputs and outputs cascs intcrfacing
cc~~ to data. significantly impro\l"~ illterl~lL'eL'irL'uitl'~. 10 '\ \1OS and hipolar circuits. ('\10'
,ystcm throughput. 1'0 accol11nlOdatc output drhcrs. along \lith thc dual
this multiproccssing schcmc. thc ~li,in~ Tcchnolo~ie, "Oil ~pcciric:ation. guarantee opera-
X2CXX hus colllroller and th~ X2CX", ;\notl1l.:r \\a~ h) incl'ca~c '~~tcm tion at C\10S and I II logic le\els.
hus arhilcr prO\ idc thc control and thl'llughpul. cspcciall, in cascs \\ hcrc
arhitration for thc s,slcm hus. Il1\crt- arithmctic functions and numcric data Mil-SId Bus
ing latchcs (X2CX.1) and transcci\crs manipulation an: critical. i~to auu an Whcn data communication hCI\\~Cn
(X2CX7) m~ct thc ncccssary functional XOX7 numcric copl'llccssor to thc sys- suh,yst~ms is dcsircd. hut not ncccs-
compatihility for ~,isting industry tcm. Although not a\ailahle in CMOS. sarily at parallcl hus sp~~ds. a MII.-
standard multiproccssor hus s, stcms. thc dc\ icc can hc uscd in a C\10S S 11>-155.1or alt~rnat~ protocol Man-
If thcrc is no nccd to c.\pand hc- XOCX6 "stcm. pnn iding thc incrcasc ch~st~r-hascd s~rial hus can he used.
yond a ~inglt: board or enlarge to a in po\\cr di~~ipation i~acccptable, I hc addition or an H D-6406 pro-
multiproccssor systcm. thc XOCX(l can I'hc addition of thc '\ \10' XOX7 to grammahle 'IS,nchronous communi-
run in thc Minimum modc. \lhcrc thc OtheT\\ isc all-C\IO' XOCX6 systcm cation intcrracc (I'ACI) and an H D-
dccod~d mcmory and I () signals arc and thc suhscljuclll mi.\ing of lcchnol- 155.10 Manch~stcr cncod~r-decod~r
(M ED) form a high-speed serial link
between several remote systems. Stan-
dard eight-bit data transfers can be INTERNAL
accomplished in the non-ISSJ bus ap- (RD-WR)
CIRCUITRY
plications by using the military ver-
sion of the H 0-6409 Manchester en-
coder-decoder -which allows more
freedom than the MIL-SID-ISSJ bus for
formatting the serial data. EXTERNAL
PORT A
The H 0-6406 provides the UAR I PIN
parallel-to-serial/ seria I-to-pa rallel con-
version function and bit rate generator
in a single 40-pin package. A 2S-pin
version (S2C52) will also be available
for higher packing density applica- INTERNAL
tions. The H D-6406 functions arc (RD-WR)
CIRCUITRY
fully programmable through a micro-
processor-compatible bid irectional
bus. which has a maximum serial data
rate of one mega baud (asynchronous
transmission with a 16X clock). Thc
HO-15530 (1.25 M-bit sec) and the
H D-6409's (I M-bit sec) maximum Undefined input voltage bels arc cuits maintain these pins at a Logic
data rates can fully support a one forhiddeh in CMOS system design. Un- One level internally and externally
M-bit serial bus interface for mili- defined input states allo" the input until they arc defined as outputs or
taryapplications. circuitry to "l1oal" within the devices' arc overdriven by an external source.
active regions. Unfortunately, 110ating An external driver must be capable
CMOS inputs tend to migrate toward of supplying 300 fJ.A minimum sink
the threshold voltage and increase or source current at valid input vol-

11
1('(' substantially. All CMOS inputs. if tage levels in order to overdrive the
INPUT r PCHANNEL unused. must be tied to vcc or
(;:\D to avoid oscillation and high
bus-hold circuits. Since this circuitry
is active and not a passive pull-up
N CHANNel
ICC conditions. resistive-type element. the S2C55A,
Pull-up pull-down resistors are the stand by current is kept to 10 fJ.A.
most common method for defining maximum.
CMOS inputs when no driving source System needs and overall compat-
is present. But. this techniljue has ibility dictated the placing of hus-hold
several disadvantages. Additional com- circuits on spceific deviccs. The XOCX6
ponents (resistors) arc necessary. CI'LI has bus-hold devices on selectcd
which increase production costs and pins (ADO ADIS. etc.). which arc
reduce overall reliability. Higher common to the local bus This elim-
power operation can actually occur inates the compounding of the over-
"hen using pull-up down resistors. drive current necessary if all XOCS6
Since the driving circuit must supply family members had bus-hold cir-
the current needed when switched to cuitry. and keeps all current reljuire-
the opposite state of the pull-up down ments within I ILLS I I L capabilities.
Peripheral Monitor and resistor. the result can be a signiticant
Control Functions increase over normal CMOS input Gated Inputs
Several peripheral functions mon- leakage current levels of I fJ.A. The S2CS2 octal latch also has
itor system I a and timing control. specialized input circuitry to minimi7e
The S2C55A programmable peri- Bus-Hold Circuitry power dissipation and help climinate
pheral interface can be used for dis- To avoid the need for external resis- the need for external resistors. Gated
play control or for information pas- tors and eliminate the high power el~ inputs minimize the effects on the ICC
sing between subsystems. using the bi- fects of floating inputs. the S2C55A. from switching and undefined inputs.
directional handshaking mode. Upon along" ith the SOCS6 CPU. uses on- This gating function. initiated by the
RESET, the 82C55A port pins become chip "bus-hold" circuitry to provide falling edge of the strobe (S I'B) input.
defined as inputs. If these inputs arc valid input voltages to specific inputs: disconnects the input inverter from
not used or will eventually become this is important when there is no the vcc by turning off the upper 1'-
outputs. they have no driving source driving source (i.e .. a no-connect or a channel (QI) and lower i\-channel
and arc in an undefined. or "float." driving input that goes to a high (Q2). Thus. there is no current path.
condition. impedance state). The bus-hold cir- other than leakage. between vcc and
 Polled or On-Demand Data Sensing
The X2C59A priority interrupt con-
vcc vcc
troller and thc X2C54 programmable

~;
interval timer managc system inter-
rupt and polling control functions.
Two methods. uscd eithcr separately
or concurrently. arc a\ailable for con-
trolling the systcm sequcncing of data
acquisition. Polled acquisition or in-
tcrrupt-driven data taking can be ac-
complishcd \I ith the circuit describcd.
Thc X2C54 timcr can be pro-
grammcd. using single or multiple
Gated Inputs on the 82C82 octal latch ellmmate extraneous current spikes due to mput 16-bit timcrs (threc pcr package). to
conditions unrelated to latch operation. While data IS latched. floatmg mputs can be dlfectfy
pI'''' ide an input to thc X2C59/\ intcr-
connected to the 82C82 mputs without usmg pUfl-up resistors.
rupt controllcr and causc exceution
of a data acquisition softwarc routinc:
rhis procedure can be rcpeated by
using the X2C54 in thc rate gcncrator
mode (Mode 2). il1\crting thc signal.
and inputting it to the X2C59A pro-
grammcd for edge-triggercd inputs.
I! certain rllnctioll~ Il1U~t hc e,Xc-
Cllled onl\ e\en '\th C\e1c. thc X2C54
rimer 0 'outpu't (ot 1'(1) can be fcd
into the e10d 01 I imcr I (CI.K I).
H,rrIS
82C55A rimer I can be programmed to opcr-
SlOP A¢J
ate as an e\ent counter (Mode 0
~~~ll'to' pc¢ £!
AD intcrrupt on terminal count) and intcr-
Low FreQuencv FI,g PC' WR rupt thc X2C59A e\er~ '\th count.
Ihe X2C59A is also used for con-
trol 01 other e.xternal interrupts such
a~ cmcrgcncy condition~ li"c engine
o\cr-tempcraturc. rrc~~un: high low.
and other on-demand situations. If
desirable. the rcpeated interrupt for
polling purposes can bc disablcd by
using the X2C59A\ interrupt masking
abilit~. \\hich onl~ allo\\s gencration
of critical situation intcrrupts.
I he X2C59A intcrrupt inpub can
be prioriti/cd. When both 'polled and
on-c..kmand ~c4uence ... an: u~ed con-
currentl~. the on-demand emergency
situations \\ould be considcred highcst
For power critical applications where power IS reduced to the POint that even full-flme priority.
operation at reduced frequency IS not desIrable, the BOCB6's static circuitry allows the clock
to be stopped. Tailoring Low-Power
System Operation
(;.,\1) during input transitions when pull-up resistors \I hcn data is latched. Se\ cral circuit dcsign techniqucs
data is latched in the X2CX2. Inter- In an XOCX6 system. the Sill input can bc \aluable in c.\amining 10\\-
nally. logic states are held \alid by is dri\ en by an 1\1.1' (address latch po\\cr operation at thc systcm Ic\e!.
the fecdback logic signal in thc cir- cnable). At 5 .\lH/. thc high pulse C'v!os is onl~ a first stcp. Significant
cuit's latch scction. \I idth of thc I\I.E is 9X ns or appro.xi- rcductions in s~stcm-level p<l\\cr con-
Input gating also isolatcs the dri\- matel~ 15 to 20 pcrccnt of t hc bus sumption can be rcali/cd if proper
ing sourcc from thc intcrnal circuitry. cyelc pcriod. rhcrefore. X2CX2 inputs de ...ign approachc.:~ arc.: ta~c.:n.
Invalid logic states from !loating in- are disablcd XO percent of thc timc. In an aircralt ~ituation. po\\cr i~
puts cannot bc transmitted to suc- During this time. ICC transients from not normall~ a problcm. II'. ho\\c\cr.
ceeding stagcs whcn the inputs are input s\\ itching arc eliminatcd. rcsult- the microsystcm po\\cr fails indcpen-
turned all. eliminating thc necd for ing in a lo\\cr operating current. dent of thc main aircraft power. full
navigation controb can rcmain intact dCI ice\ masimum ratcd rreLjuencics. X()CX6\ static internal circuitry allm"
and operational with the XOCXo ('MOS rhe t':vIOS XOCXo static design al- docks to hc stopped. I his capahility
control system. With a hackup hattery 10\ls the systcm clock to drop to a eliminates thc plmer dissipation as-
power supply. the powcr sensing unit lower rreLjucncy (100 kill. ror e.\am- sociated \\ ith S\\ itching. and reduccs
can transfer the systcm rrom main pie). nlaking rull computational and del icc currents to standhy bels. With
power opcration to hattery supply. data manipulation po\\ers ,t\ailahlc static Dt' opcration. indil idual peri-
With system power leleb appro.\i- \\ hile signiricantly reducing system pheral del il'C standhy currcnts arc
matcly 10 percent or eLjuil'alent powcr consumption. This low rre- guaranteed to hc less than 10 Mil.
:--MOS hipolar circuits. rull 5 :villi Ljuenl'y operation is not alailahle \\ith with the XOCX6 (,I't typically less
operation can be maintaincd. most :\ "lOS processors. induding the than 500 Mil.
As primary pO\\er is diminished :\ :viOS XOXo \I here 2 "lill is the mini- Static design can also stop and
(hattery discharging) or removcd mum allmlCd dock rreLjueney. Dy- single-step the system dock during
(pO\l cr intnruption hattery hackup namic rcgister dcsigns in the \:vIOS system prolllty ping. I his dchug
op.·ration) in porta hie or rcmote h:l\- ('I't sneed III he rerrcshed at ,I mini- mcthod allo\\s the designn to insp\'ct
tcry-plmercd applications. running at mum rate and do not allo\\ low the system hus and esaminc spcciric
a In\l~l.'r Irl'ljlll·IH.'~ t~l f,,:nll:"l\.'r\I,.' fHlWi.'l' operating rrcLjuencies. operations. I'he rcal time complica-
hecomcs import'lnt. Opcmting pm\cr ry pica I operating power 1'01' thc tions or 5 Mill hus transfers arc clim-
is nitical in IO\l-pm\.·r applications. XOCXo (,I't at 5 Mill is 40 m". de- inatcd and system dehug is simplilied.
and t'\-tos opcrating pO\lcr is dir.·.·tly ratcd linearly as rrequcncy drops (,11'-
related to frcLjucncy. pro.\imately 2 m\ at 100 kill). Sim-
With the XOCXo ramily's static dc- ilar dnatings are also I alid 1'01' thc
sign. power reLjuircmcnts can hc uscr pO\ler dissipations or thc peripheral. Although the X2CX4A dock gcncra-
controlled: lo\\ering the rreLjucncy re- support. and mcmOl'y \·ircuits. tor's 40 mil It'(' limit is significantly
duces power. Static design (i.e .. no hnally. gil.·n a 1",\1.'1' nitical situa- lower than the hi polar X2X4A\ 162
internal dynamil' rcgisters needing tion I\hcrc pO\lcr is diminishcd tothc mil limit. it is still the largcst. single
constant docking or rcrrcsh) aillms point that Clcn Im\ IrcLjucllcy. lull- po\\cr user in a (,"lOS XOCXo systcm:
opemtion from Dt' III the indil idual tim\' opcration is undesirahle. thc this is duc III the high rrcLjuency or

CMOS/NMOS/Bipolar Parametric Comparison

CMOS NMOS CMOS NMOS CMOS NMOS CMOS NMOS CMOS Blpol.r CMOS Blpol.r CMOS Blpol.r
80C86 8086 82C54 8254 82C55A 8255A 82C59A 8259A 82C82 8282 82C84A 8284A 82C88 8288

VIH 2.2V 2.0V 2.2V 2.0V 2.2V 2.0V 2.2V 2.0V 2.2V 2.0V 2.2V 2.0V Z2V 2.0V

Vil O.BV O.BV O.BV O.BV O.BV O.BV O.BV O.BV O.BV O.BV O.BV O.BV O.BV
-_. __ ._-
O.BV

3.0VI 3.0VI 3.0VI 3.0VI 3.0Vl

VOH VCC 2.4V VCC 2.4V VCC 2AV VCC 2.4V 2.9V 2.4V VCC 2.4V VCC 2AV
OAV OAV 0.4V 0.4V 0.4V 0.4V

-2.5mAI -2.5MAI -2.5mAI -2.5mA! -1mA -BmA!

IOH -400/,A -400/,A -400/,A -400/,A -BmA -SmA -2.5mA -SmA
-100/,A -100/,A -100/,A -100/,A -2.5mA

0.4V 0.5VI
VOL 0.4V O.45V OAV 0.45V 0.4V 0.45V 0.4V 0.45V 0.4V 0.45V 0.45V 0.5V
0.4V

+20mAI +32mAI
IOl +2.5mA +2.5mA +2.5mA +2mA +2.5mA +2.5mA +2.5mA +2.2mA +BmA +32mA +2.5mA +5mA
+BmA +16mA
--
500/,A Not
ICCBB Typic.1 Appli- 10"A 140mA 10/,A 120mA 10/,A B5mA 10/,A 160mA 10/,A 162mA 10/,A 230mA
c.ble Typlc.1

40mA 1mAI 1mAI 1mAI 1mAI 40mA 162mA 1mAI

ICCOP @5MHz 340mA MHz 140mA MHz 120mA MHz B5mA MHz 160mA @ @ MHz 230mA
Typical Typical Typical Typical Typical 25 MHz 25 MHz

100 pFI 100 pFI 300 pFI 300 pFI

Cl 100 pF 100 pF 150 pF 150 pF 150 pF. 150 pF 100 pF 100 pF 300 pF 300 pF
30 pF 30 pF 80 pF 80pF
 op~ration (15 24 \1111 lT~slal fr~- to \CC anu (;\1> k\c1s with an ~.\-
yu~nc~ for \ \1111 s~st~m fr~yu~ncy) h:rnal ..,nun,,:e l11on: dlecti\dy turns
Ice MAX. 125 C CRYSTAL anu th~ non-iu~al w;l\d"orm of th~ inl~rnal circuitr~ on and oil. r~sulting
25M/ '.EQUENCY'25M
••
cry~tal signal. in u~cr~as~d op~rating pO\\cr.
Wh~n using th~ X2CX4A in a stop- rh~ clock fr~yu~ncy r~duction must
I
~
CRVSTAl
FREQUENCY· 15M,""
clock application, th~ ~:\t~rnal fr~- b~ prop~rl~ tim~d to m~ct minimum
yu~ncy input (HI) mou~ of op~ration XOCX6 clock high- and lo"'-tim~ r~-
~ T.•. ·25C must b~ us~d. Th~ X2CX4A clock g~n- yuir~m~nts. Th~rcfore, along with thc
I
I
erator has a minimum crystal fr~- appropriat~ di\ ide-down circuitry
yuency of 2.4 M HI (corresponding to ne~ded to PHl\ ide the pro pCI' 10\\ cr
XOOkHI syst~m fr~yucncy) for internal freyuency, synchronilation bCl\\een
oscillator operation. Thc HI input thc 10\\ frcyucncy signal linc and the
allows usc of an c.xt~rnal clock to pro- control circuitry is neccssary. Care
\ id~ the l11ain timing. This ~xternal must be takcn to avoid cases of
clock is process~u through th~ sal11~ asynchronous timing crrors caused by
int~rnal X2CX4A circuitry as th~ crys- irregular clocks that arc outsid~ the
g:::r~'\,N tal oscillator input. sO timing within CI'I' speeilication limits.
th~ systl.:l11 r('mains th(' same, rhe X2C55A 1'1'1 pr<l\'iu~s the paral-

1____
~ __
EXTERNAL
FREOUENCY
INPUT
An audition;lI h~n~lit. critical to th~
succ~ssful u~sign of a stop-clo~k cir-
cuit. is th~ X2CX4A's r~uuc~u op~rat-
Ici Cl'l' interfac~ to thc control cir-
cuitry. An interrupt from thc X2C59A
priority intcrrupt controller can pro-
o H ~
1
25
ing power when w..ing an external fn:- \iJc lh~ start-up signal for thc systcm
yu~ncy sourc~ to dri\~ th~ FFI input. clock l'ontrol circuitry. The X2C59A
With .\ I anu \~ crystal op~ration, allm" prioriti/ing and masking of
th~ input transistors sp~nd a gr~atcr int~rrupting sources so thai: during
p~rc~ntag~ of tim~ in the acti\'c r~gion the til11~ th~ system is stoppcd, only
Power curves for the 82C84A show the
effects of both frequency and voltage de- due to thc sinusoidal nature of thc thc mOst critical signals may restart
creases on the Ice. crystal circuit. Dri\ ing thc HI input thc proccssor. •
 High Density Leadless Chip Carrier
Packages Increase Reliability, Save Weight
A military CMOS 16-bit microprocessor packaged in LCCs reduces operating
temperatures, size, and weight, adding to that family's low-power advantages.

Last month, DE looked at the 80C86 family,

which adds low-power CMOS 10 a proven
design for high performance defense systems.
This month, Part Il in thiJ two-part series
on microprocessors will examine thatfamily's
transition to industry standard lead/ess chip
carrier packages.

Just as critical as power consumption

is packaging technique. The low-power
operation of the CMOS 80C86 family.
along with memory and support chips,
allows for design of sealed, portable
system enclosures, In turn, this type of
packaging reduces operating tempera-
tures and minimizes hostile external
environment effects, increasing system
reliability,

System Level Reductions

Replacing higher power devices with
their CMOS equivalents can reduce
system "hot spots" caused by localized
high dissipation circuits. A direct Laadla•• chip ca,,'a,. altached to a ceramic dual-in-line substrate allow Harris Semicon-
ductor 10 package the complete 16-bit CMOSmicroprocessor as a single unit. Harris has
replacement with low-power CMOS
a/raady used this packaging concept to produce 64K- and 256K-bit RAM arrays based on
components will significantly reduce 16Kand 64K chips. Alilhase LCCpackaged products are military qualilied.
system ambient temperatures, Using
the power supply current requirements
of the CMOS 82C88 and bipolar 8288
bus controller, along with a typical OjA
(junction to ambient temperature rise The rise in the die surface tempera-
with respect to power dissipation) of ture of CMOS is approximately two
SO"C/w, the following device tempera- percent of the increase seen in NMOS
ture comparison can be made: products. This lower CMOS die
temperature results in a significant in-
For SO°C/W x (S mAl
CMOS x S.SV + 12S0C

SO°C/W x .027S mW
For SO°C/W x (230 mAl + 12S0C
bipolar x s.sV + 12S0C

SOOCjW x 1.26SW
+ 12S0C 126.37SoC, typical

DEFENSE ELECTRONICS: JULY 1983 Reprinted from DEFENSE ELECTRONICS, July 1983; © t983 EW Communlcetions, Inc,
8-10
crease in the mean time between fail- to lower levels, enabling the use of carriers (LCC) have recently become
ure (MTBF). The MTBF equation shows sealed enclosures with a minimum of popular because of their small size and
the direct relationship of the failure cooling. light weight.
rate and temperature: Temperature also affects circuit and The trend toward using dual-in-line
system performance. CMOS leakage packages has proven sufficient in most
currents and, therefore, standby power applications. But, where very light and
dissipation increase at the high end of small, complex electrical functions are
the temperature range. Performance required, LCCs offer space and fleXi-
also degrades because of increased bility. DIPs occupy approximately
channel resistances on the P- and N- three times the space an LCC package
channel transistors. Keeping the system uses for the same pin count. And un-
ambient temperature low results in an like an LCC package, the DIP has leads
improved overall performance. that can bend or break, adding a para-
Replacing existing circuits with low- sitic resistance and capacitance.
power CMOS offers many benefits. The introduction of flatpacks to
However, the system environment military applications proved an alterna-
remains constant-that is, compatible tive to the DIP package in reducing
Similar increased MTBF numbers can with NMOS/bipolar operation. Power board space requirements. But, flat-
be estimated for system operation supplies, cooling equipment, and pack costs are high because of the large
when system ambient temperatures are enclosure size and weight all remain amounts of gold used in the package
reduced by CMOS circuits. the same. plating. Long lead length and narrow
With decreased system temperatures, In order to optimize the reductions spacing also require special carriers
the need for special cooling equipment possible in weight and cost and in- for handling. And, when soldering to
and enclosure openings can be elimi- crease reliability, the system must be printed circuit boards, the long lead
nated or reduced. The use of cooling designed with low power in mind. length permits package vibration,
techniques such as heat pipes, liquid Smaller system power supply require- which could affect the reliability of
coolants, heat sinks, and louver assem- ments and lower temperatures elimi- the leads or their solder connections.
blies can add weight and volume to nate the need for cooling components. Leadless chip carriers offer small
systems. Besides these physical dis- package sizes, no leads to bend or
advantages, the lower reliability of Device Level Miniaturization break, and premium electrical perfor-
electromechanical operation and the Decreasing an individual device's mance due to full parametric testing
system's exposure to hostile environ- package can lead to miniaturization allowed at the package level. For criti-
ments adds an additional risk factor to and portability. Flatpacks and DIPs cal military applications, MIL-STD·883B,
system reliability. CMOS systems can are the main packages used in military group A, B, C, and 0 can be applied
keep the system operating temperature system designs. However, leadless chip to leadless chip carriers in a method
similar to those applied to dice pack-
aged in a size-brazed DIP.
Many devices cannot be manufac-
tured in LCCS or must be placed in
larger pad count carriers because of
bipolar and NMOS technologies' exces-
sive power dissipations. But with • A111t1

....
CMOS, power dissipation is reduced- n IHtJS1 ~

optimizing package size and pin count.

The leadless chip carrier pinout def- Lee
44 PAD
•

:M
MH/MX

IlQlDT4I
..
Dl

D3
initions for the CMOS 80C86 family JEDEC TYPE C

follows, for the most part, predefined

pinout and package assignments as
established by the original NMOS
source. With certain device types, spe-
cifically the original source products,
larger than necessary packages were
used. For example, the 8282 octal
latch, 8284A clock generator, and
8288 bus controller are packaged in
28-pad LCCs, while 20-pad LCC
packages are standard for the 82CXX
CMOS equivalents. One of the main
reasons for using this enlarged pack-
age for bipolar devices is its higher-
than-CMOS power dissipation. With
CMOS' lower power characteristics,
however, minimum package sizes can
be achieved. Using 20-pad LCCs for
the CMOS versions of the above
devices allows for maximum system
packing density.
Leadless chip carriers for high den-
sity packaging and minimized pad
counts further reduce board space and
weight in high density systems. In
addition, LCC packages' reduced pack- Ii
age lead lengths and interconnect
lower the parasitic inductance of the Ii I~ II
circuitry. Parasitic inductance is a
major contributing factor to noise in
high-speed CMOS system designs (See
sidebar, "System Noise Reduction in
High-Speed CMOS Design").

LCC Assembly Techniques

The relatively recent revival of the
LCC package, along with the advan- NC
I.'
tages of implementing these packages cs I.'
on printed circuit boards and sub- I.'
strates, allows designers a high~ensity .¢ I.'
packaging option. To ease the transi- eLK2 '.3
OlJT'
tion from conventional DIP/PCB assem-
blies to the LCC/PCB packaging option, I.'
the designer must understand the dif-
ferences between the two packaging ~~
~z
-
~§ $
Q v
technologies. 8 Q
Q
Q U

!3 ~ ~I~.. ! Z
Substrate Material Selection Q U ~

The basic concern for selection of

the substrate material is matching the
 CMOS vs NMOS Power Requirements
PMt CMOS Opermlng NMOSlBlpolar Equtv.
Type Deecrlpllon l'Ower Supply Current !'Ower Supply Current

8OC86 CMOS 16-Bit CPU 40mA 340mA

82C54 CMOS Intervallimer SmA 140mA
82C55A CMOS Parallel Interface 1 mA 120mA
82C59A CMOS Interrupt Controller 1 mA 85mA
HD-6406 CMOS UART/BRG 3mA 100mA
82C82 CMOS Octal Latch 1 mA 160mA
82C83 CMOS Octal Latch (Inv) 1 mA 160mA
82C84A CMOS Clock Generator 25 mA 162mA
82C86 CMOS Bus Transceiver 1 mA 160mA
82C87 CMOS Bus Transceiver (Inv) 1 mA 130mA
82C88 CMOS Bus Controller SmA 230 mA
82C89 CMOS Bus Arbiter SmA 165mA

8OC86 Family Package Comparisons

PMt DIP LCC DIP Area LCCArea DIP Welght LCC Welght
Type Pin Count Pad Count (Sq •• n.) (Sq. In.) (Gr.) (Gr.)

8OC86 40 44 1.2 0.423 1D.92 1.18

82C54 24 28 0.75 0.198 6.48 0.55
82C55A 40 44 1.2 0.423 10.92 1.18
82C59A 28 28 0.997 0.198 7.56 0.55
HD-6406 40 44 1.2 0.423 10.92 1.18
82C82 20 20 0.3 0.123 2.9 0.34
82C83 20 20 0.3 0.123 2.9 0.34
82C84A 18 20 0.283 0.123 2.48 0.34
82C86 20 20 0.3 0.123 2.9 0.34
82C87 20 20 0.3 0.123 2.9 0.34
82C88 20 20 0.3 0.123 2.9 0.34
82C89 20 20 0.3 0.123 2.9 0.34

Syatern ArealWelght Summary 7.43 Sq. In. 2.52&Sq. In. 88.&&Gr. 7.02 Gr.

Material Thermal Propertle&

TCE
Subltrate Mmet1al (In.lln.l° C • 10-&) Commenll

Alloy 42 5.3 42% NI, Balance Fe

96% Alumina 6.3 Industry Standard
94% Alumina 6.4 Industry Standard
92% Alumina 6.4
Copper Clad I nvar 6.4
99.5%B8O 6.4 Expensive
Low Carbon Steel 12.0 Porcelanized
Polyimide G30 14.3 Industry Standard
Epoxy/Glass G10 15.8 Industry Standard
Triazine G40 16.0 Industry Standard
CDA 101 Copper 17.3 Very High TCE
8061 Aluminum 23.6 Very High TCE
linear thermal coefficient of expansion
(TCE). Matching the TCEs is critical to
attaching an LCC to a substrate when
the assembly must be able to survive
the number of thermal cycles typical
of military applications and testing.
When the LCC is soldered on a board,
the solder interface is not only the elec-
trical contact but the mechanical con-
nection as well.
When the TCEs of both the package
and mounting substrate are not pro-
perly matched, thermostatic deflection
(warp) can occur during temperature
cycles. When these two materials warp,
torque is directed to the solder joints,
which results in a fatigued mechanical/
electrical connection. This problem
becomes even more apparent as the
LCC pin count increases. Larger pack-
age and substrate sizes result in higher
stress levels. The selection and use of
board material should follow this
general rule: The larger the difference
between the TCEs of the two materials Printed circuli board metallization should extend beyond Ihe Lees outer edge. This exten-
used (the LCC and the substrate sion permits molten solder to flow up the castellated regions. and to lorm a liflet 01 solder
material), the smaller the substrate sur- to complete the electrical connection while strengthening the mechanical bond.
face area should be. Available mate-
rials range widely in cost and TCE center. This spacing allows one .01Q-in. mounting is the most reliable method
characteristics. line at .01O-in. spacing to be run be- for assembly.
tween the LCC mounting pads. The basic principle for attaching
Printed Circuit Considerations If lines are run close to other metal- LCes to boards and substrates is reflow
After selecting the substrate mate- lization, a solder mask should be used soldering. Both the leadless package
rial, the printed circuit trace geometries on the board to prevent solder bridg- I/O metallization and the interconnect-
should be investigated. The circuit ing during the reflow process. When ing substrate metallization are pre-
traces for LCC foot pads should be the using multilayer boards or substrates, tinned with solder; the two are then
same size as the metallization on the a clean layout can be made by allocat- mated and heated by one of a number
bottom of the LCC and slightly longer ing the surface layer metallization of means. Surface tension and the
to the outer edge of the package. This exclusively to LCC mounting pads- cohesive properties of the molten sol-
metallization allows the solder, when eliminating the need for a solder mask der align the package over the sub-
heated to the reflow temperature, to and reducing the concern for solder strate metallization. The assembly is
wet both the base contacts and the bridging. Electrical noise problems can then cooled, making complete the
LCC package's castellations. be diminished by power gridding the electrical/ mechanical bond.
The outer surface of the solder supply buses on a unique layer while The best results are usually obtained
deposit forms a fillet where it extends routing signal lines on other layers of from reflow soldering, and when both
over the metallization pad on the sub- the substrate. the LCC and the metallization on the
strate's surface, strengthening the substrate it is to be attached to are
mechanical bond. This type of bond LCC Mounting Techniques pre-tinned. The LCC package pads can
raises the LCC away from the board's Socketing and soldering directly to be pre-tinned by fluxing and dipping.
mounting surface to facilitate cleaning the board are the two methods possible The substrate pads are usually tinned
the residual flux and debris under the for mounting LCCs on circuit boards. by wave soldering or screening on a
package. In military applications, socketing be- solder paste.
To optimize packaging density, rela- comes a disappointing compromise for When using a wave solder tinning
tively tight geometries in layout are LCC mounting because of the socket's approach, and after the substrate has
of concern. Leadless package layouts bulky size. An LCC socket has its place been tinned, an adhesive must be
often require .01O-in. lines, OIO-in. in less critical applications, but can applied temporarily to hold the LCC
spaces between lines, and .020-in. or severely sacrifice packing density, and in place over the substrate metalliza-
smaller feed-through holes. The pads falls short of the stringent environmen- tion during the reflow process.
that connect to the LCCs are typically tal testing required by most military In implementing the screened on
.02Q-in. wide, and are .OSQ-in.center to applications. Direct LCC to substrate solder paste technique, the paste is
 applied to the substrate contacts using
VCC = 5.0V a screen printing technique. Normally,
ICC a layer of "wet" paste, eight to nine
!JA
TA=2S C
mils thick, is deposited on the sub-
strate contacts. Then the contact area,
600
covered with paste, is air dried until

500
~
INPUT ~ .,""", tacky before the LCC is attached. The
LCC is then mounted to the corre-
r sponding contacts manually or by
N CHANNEL automatic placement.
400
One important step in the LCC
assembly process is baking the popu-
300 lated substrates dry before soldering,
which allows the air and flux pockets
200 in the paste to evacuate, minimizing
the volatility effects in a vapor phase
soldering operation. This process is
100
vital because unevacuated flux pockets
will cause the package to float during
the reflow operation. Floating affects
the package's positioning properties,
and an unacceptable package align-
ment can occur. Also, the liquid vehi-
cle of the solder paste is evaporated
and the LCC is temporarily held to
the substrate by the paste, which is
now dry.
LCC placement on the substrate is
not as critical as it might appear. Dur-
The majority of current flow in an all CMOSsystem is transient by nature, occurring ing the reflow process, the dried solder
on the waveform edges or transitions where instantaneous demand for current paste holds the Lce in place while the
occurs. These current transients result from: paste reaches the reflow temperature.
• charging and discharging of output load capacitance During this process, the surface tension
• simultaneous P-channel and N-channel switching
of the solder will pull the LCC into
The currents generated by these switching conditions can be large and cause
noise on the power supply lines. However, the current's magnitude is not the only alignment over the substrate contacts.
factor in determining the size of VCC/GNDvariations-The time period over which The placement must be accurate
this current is switched is also critical. If this time period is relatively long, the enough to insure the LCC solder pads
current can be categorized as steady or bulk current, and the transient effect on the do not overlap the adjacent intercon-
power supply voltage is minimal.
However, as the time period decreases, these inductance effects begin to playa nect on the metallization below.
more important role. The relationship of time and inductance are given by: Heat must be applied to melt the
V=L di/dt solder and connect the LCC and the
substrate. Methods such as belt fur-
Switching the same amount of current more quickly will have as great an effect
on the VCCas an increase in the magnitude of the current change in the same time
naces, heated air chambers, and in-
period. As propagation delays and output rise/fall times decrease, the effect of the frared radiated heat techniques can be
related inductance becomes more significant. used, but are not finding widespread
The parasitic inductance is a result of system interconnect, socket, decoupling acceptance. The most popular heating
capacitor, and device package contributions. The inductance must be minimized to method for high-volume production is
reduce this transient effect. The main sources of inductance are lead lengths (both
IC and decoupling capacitor), PCboard interconnect (VCCto capacitor to GND),and the vapor phase reflow technique.
the capacitor, itself. In vapor phase reflow, the populated
Although the designer can do little about standard IC packaging and lead length, substrate to be soldered is lowered into
manufacturers can employ several techniques for controlling the IC's parasitic a saturated vapor above a pool of
inductance. Matching device size to package cavity area allows minimum bond wire
lengths in assembly. Doubling the VCC and GND bond wire interconnect also high boiling point, flourinated hydro-
reduces parasitic inductance effects within the package. carbons. Usually, vapor phase solder-
Printed circuit board runs should be kept to minimum lengths with VCCand GND ing systems have two operation zones.
lines 3/16-in. to 5/16-in. wide to reduce power line inductance. In prototype circuits, The primary zone is used for heating;
extra care should be taken in limiting wire length and including sufficient decoup-
the secondary zone is used as an inter-
ling since the wire and socket lead length add inductance beyond that normally
found in PC boards. Low inductance capacitors and socket elimination will help mediate cooling and cleansing zone
control system related inductance. -WJ.N. & J,M.W • before the assembly is removed from
the soldering operation.
 As the board is lowered into the Other removal methods are possible, only the memory circuitry-This
primary zone, the solder joints are such as using a soldering iron with a approach increases the system pack-
reflowed uniformly by the vapor, con- specially shaped tip to heat the con- ing density when large amounts of
densing over the surface of the sub- tacts or by heating the defective pack- memory are necessary. Maximum re-
strate, which gives up its latent heat age and its surrounding area with a duction, however, is not accomplished
from vaporization. This thermal forced hot air gun. because bus drivers and decoders
exchange heats the board quickly and The heat gun method is usually the must be added externally to the
evenly. When the substrate is raised most convenient, inexpensive, and module assembly. To achieve a greater
into the secondary zone, the now con- practical for rework. When the LCC is reduction in size, as many functions as
densed fluid from the primary zone heated by the gun, the package should possible must be placed on high
drips off the board into the boiling be removed with tweezers-the now density assemblies.
liquid below. The substrate assembly exposed substrate contacts can be tin- The Harris HM-92S70is a beginning
exits from the process, uniformly ned, if necessary, as could the LCC to the "system on a substrate" develop-
oldered, dry, and relatively clean. contacts on the replacement device. ment. By providing Lcc-packaged
Cleaning the soldered assembly The LCC is manually replaced in close CMOS bus drivers and decoders on
should be performed immediately after proximity to its final position. The the substrate, all the functions of a
the vapor phase reflow process while repair area or entire board is then 256K-bit memory board are contained
the boards are still hot. Uncongealed heated to the solder reflow tempera- in one high density assembly. The
residue can be easily removed at this ture to complete the operation. HM-92.S70address inputs are buffered
time, resulting in thorough cleaning. and have an input current leakage limit
Another reflow technique employs System on a Substrate Concept of JOllA so direct connection to the
hot solder oil. The substrate with posi- When the appropriate LCC system CPU address bus is possible without
tioned LCCs are fully immersed in a components are assembled on a additional buffering. The HO·6440
hot oil bath to bring the solder and ceramic substrate with dual-in-line CMOS decoders on the substrate meet
parts up to the reflow temperature pins, the space, weight, and reliability the memory array decoding needs.
quickly. The assembly is then removed advantages of LCCS are made more The Digital Equipment Corporation
from the oil and allowed to cool. accessible. This "system on a sub- Micro/J-lI, a CMOS module assembly,
Rinsing the assembly afterwards strate" technique allows LCCs to be which is a two-chip set equivalent of
removes residual oil and excess flux. used in more traditional system con- the POP·IJ minicomputer, has adapted
This technique is useful for experi- figurations such as those using stan- this concept to the microprocessor
mentation and low-volume production dard DIP packaging. area. Two CMOS devices manufactured
because of its relatively small capital One of the first movements in this by Harris, the control chip and the
investment. concept direction has been the develop- data chip, are packaged in 64-pad
ment of memory arrays on ceramic LCCS and are mounted on a 60-pin
LCC Assembly Rework substrates. The HM-6S64,a 64K CMOS ceramic DIP substrate, compatible with
The repair and replacement of a RAM module, was first introduced in the POP·II'S full instruction set. Com-
failed device packaged in an LCC is 1979, and uses sixteen 4K x I CMOS pared to the original POP·IJ assembly,
important in chip carrier assembly RAMSmounted on both the substrate's which consisted of several boards, this
processes. The advantages in rework top and bottom. This packaging tech- transition to a 60-pin substrate offers
stem from the ease of reflow soldering. nique further increases an LCC'Sfunc- significant size and power reduction
Since there are no leads on LCCs and tional density on the RAM module. advantages.
usually no holes in the substrate to Other products available in module The next step will be the combina-
deform, many rework cycles are al- form include the Texas Instruments tion of CPU, I/O, and a significant
lowed. Of course, rework is dependent TMS4164, a 64K dynamic RAM amount of memory onto a single sub-
on the reflow technique, type of solder, assembly, and a 64K EEPROM strate assembly. The development of
reflow temperature, and the thickness assembly from National Semiconduc- more highly integrated processor, such
of the metallization used in a particular tor, the NMH2864. as the 80C 186, that include I/O and
application. During a rework situation, With the introduction of the 16K control functions on-chip will make
LCC removal can be accomplished CMOS RAM, a step-up in module den- the logistics of providing all capabili-
using sC"veraltechniques. sity is also seen. The HM·92S60 uses ties in a single high-density unit easier
One method is to use the same hot sixteen HM·6SI6RAMs, and has a total to handle. With all functions available
solder oil immersion technique for capacity of 256K bits of static CMOS in one unit, systems can be imple-
applying the LCCs to a board. After memory. The HM·92S60 can be con- mented with one assembly connected
the immersion and subsequent reflow figured as a 16K x 16 or 32K x 8 static to the outside world, or additional
of the solder, a pair of tweezers, or a RAM array. assemblies added to provide greater
similar tool, can be used to remove The HM·6S64 and HM·92S60, along amounts of memory or high-density
the defective LCC from the board. with the other such modules, provide multiprocessing capabilities. •
SYSTEI DESIBII! D~rnrnlA1mm) rnDrnrnOOD~

PROVIDING CMOS
BENEFITS TO
PERIPHERAL CHIPS
CMOS technology is finally being extended beyond processors
to peripheral support chips. An era of low power, high
performance designs may result.

T
Oday's complementary metal oxide semiconductor
microprocessors have evolved in differing ways-
some through direct hardware/software emulation
of existing N-channel metal oxide semiconductor micro-
processors, others by the merging of several archi-
tectures and instruction sets. In both cases, performance
improvement and low power operation result.
In order to take advantage of these microprocessor operation to meet specific system requirements. Syn-
advancements, logic and memory also had to improve. chronous 16k CMOS random access memories (RAMS),
For example, an entire second generation of high speed for example, have a guaranteed operating current of
small scale integration/medium scale integration 10 mA/MHz maximum for low power or battery oper-
(SSI/MSI) logic appeared in the 74HCXX174SCXXprod- ated systems. In addition, asynchronous 16k CMOS
ucts. These logic devices offered low power Schottky RAMs, with the same configuration, have access times as
transistor-transistor logic (LS/TTL) equivalent propa- low as 70 ns.
gation delays at complementary metal oxide semicon- CMOS nonvolatile memory support is available with
ductor (CMOS) operating power levels and provided the both erasable programmable read only memory
necessary high speed "glue" for advanced CMOS micro- (EPROM) and fuse link programmable read only mem-
processor systems. ories (PROMs). CMOSPROMs offer the greatest benefits in
Similarly. higher density CMOS memories are now nonvolatile applications where low power and reliable
available at much greater speeds. Functional options data retention are critical. Present CMOS fuse link
include both synchronous and asynchronous memory PROMs store data in programmed polysilicon fuses. Fuse
link technology yields permanent, stable storage charac-
Walter J. Niewierski is a technical marketing engineer teristics for the life of the device. Polysilicon fuses,
at Harris Corp, Semiconductor CMOSDigital Products combined with the low power of CMOS, provide an
Div, Melbourne, FL 32901, where he is responsible excellent alternative to EPROMS or bipolar PROMS for
for technical support of CMOSdigital products. Mr battery operated and other low power systems.
Niewierski has a BSEEfrom the University of For high performance, low power 2716-type memory
Michigan. applications, 16k CMOS synchronous fuse link PROMs
CoPVright by Computer Design Publishing Company, © Februery 1983.
All rights reserved. Reprinted by permission.
 method for data movement, using
read (RD) and write (WR) lines, allows
TABLE 1 interface to almost any recent genera-
CMOS SOCSS Family Parlpharal Support Chlpa tion microprocessor.
In addition, consistent family speci-
Pert CMOS device typelfunction fications make system design easier.
82CS2 octel letch Tpo • 36 nl mIX It CL • 300 pf All peripheral product ac and dc spec-
82C84A clock generator/driver 8-MHz IYltem clock frequency ifications are guaranteed over the in-
82C88 bUI controller Stetul decode function dustrial ( - 40 °C to 8S 0c) or military
82C64 programmable interval timar 10-MHz count frequency ( - SS °C to 12S 0c) temperature
82C65A programmable paripharal Control word reed cepebility range and S-Y ± 10070voltage range.
interface Timing specifications for peripheral
priority interrupt controller circuits allow full speed operation
with a CMOS 8OC86central processing
unit (cpu) at S MHz, with no wait
states.
provide a low 13-mA/MHz operating current with Dual specifications for the logical I output voltage
17S-ns access times. Moreover, performance upgrades (YOH) ensure interface compatibility of the peripherals
to 12S-ns access times will soon be possible. In non- with both CMOS and TTL devices. Even in an all-CMOS
volatile memory, CMOS has a significant speed advan- design, there may be the need for circuit functions avail-
tage over N-channel MOS (NMOS), while showing a large able only in NMOS or bipolar. In this case, the periph-
power reduction. erals allow direct interface without pullup resistors or
additional buffers. For future system enhancements
Improving peripheral support with circuits of other technologies, the retrofit problems
Although sophisticated CMOS microprocessors have that occur with non-TTL compatible devices are elimi-
brought high performance to low power designs, they nated.
cannot reach their full potential without equally high Several techniques used to design the peripherals
performance, low power consumption support chips. improve CMOS's natural low power operation. During
For the most part, CMOS peripheral circuit design normal system operation, bus signals at the latch inputs
efforts have lagged. This has limited the development of can exhibit high impedance or make transitions unre-
systems attempting to use CMOS devices exclusively. A lated to latch operation. These voltage transitions cause
new family of microprocessor peripheral circuits fills an increase in power dissipation due to the low resis-
this void by providing increased performance and func- tance path between Y cc and ground created when the
tionality without sacrificing low power consumption. input circuitry switches.
Because the Harris 80C86 peripheral product line (see In Harris' 82C82octal latching bus driver, gated inputs
Table I) has a wide functional range, complex, high per- eliminate input switching current transients by turning
formance systems for low power applications can be off the inputs when data are latched (strobe pin = low).
designed. The peripherals are TTL compatible CMOSver- See Fig I. The strobe pin (STB) disconnects the input
sions of industry standard NMOS devices. In addition, inverter from the power supply by turning off the upper
they incorporate improvements that eliminate tradi- P-channel (QI) and lower N-channel (Q2). No current
tional problems in hardware, software, and power flow from Y cc to ground occurs during input tran-
consumption. With the peripheral circuit family, cost- sitions. Invalid logic states from floating inputs are not
effective, low power designs can be implemented at transmitted to succeeding circuitry, thereby eliminating
superior performance levels. the need for pullup resistors.
Drop-in replacements for their NMOS equivalents
(see Table 2), the 8OC86peripheral family offers equal or Steering clear of high currant conditions
greater performance. The peripheral family's architec- Bus-hold circuitry used on specific pins avoids high cur-
ture is fully compatible with 80C8S- and 80C86-type rent conditions caused by floating inputs to CMOS
microprocessors. However, the popular 2-line control devices. These circuits maintain a valid logic state when

TAeLE 2
Peripheral Interface Compatibility

Logical 1 Logical 0 Logical 1 logical 1 logical 0 logical 0

Input voltage Input voltage Output voltage Output current Output voltage Output current
(VIHI (Vlll (VOHI (IOHI (VOll (lOll
80C86 2.0 V/2.2 V 0.8 V 3.0 V - 2.5 mA 0.4 V 2.5 mA
Peripherals Ind/Mii Vcc-O.4 V - 100 ~A
NMOS 8086 2.0 V 0.8 V 2.4 V -400 ~A 0.46 V 2.5 mA
Family
CMOS 70% Vcc 30% Vcc Vcc-0.5V - 10 ~A 0.4 V 2.0 mA
LS/TTl 2.0 V 0.8 V 2.5 V -400 ~A 0.4 V 4.0 mA-Military
2.7 V - 400 ~A 0.5 V 8.0 mA - Commercial
 based on system operating frequencies. CMOS operating

L'·
power is directly related to frequency; the lower the fre-
quency, the lower the operating power dissipation. At a
dc frequency, device standby currents are typically less
than IO/LA.
~"' , Where voltage is concerned, the peripheral family
maximum input voltage limit (ground - 2.0 V 4 V1N
"'-6.5 V) essentially eliminates the problem of device
latch-up. Latch-up results from an overvoltage condi-
tion on the inputs or outputs that causes a parasitic
silicon controlled rectifier on the die to become active.
This creates a high power supply current (ICC) condi-
tion. The increased input/output (I/O) voltage range on
the peripherals offers greater protection from system-
induced noise, as well as increased noise immunity.

Fig 1 Gated Inputs of 12C12 octal latching bus drivers. Such Expanding parallel ports
Internal circuitry eliminates need for external pullup Adding parallel I/O ports to an 8OC48 family micro-
resistors. computer using a PPI is well documented. However,
designing this system in CMOS (see Fig 3) requires addi-
no driving source is present (ie, an unconnected pin or a tional attention to the port reset condition and the state
driving input that goes to a high impedance state). In the of unused port inputs. The CMOS PPI eliminates these
82CSSA programmable peripheral interface (PPI), all port concerns and, in conjunction with a unique feature of
pins have bus-hold circuitry (Fig 2). Port pins are de- the 82C82 octal latch, keeps power dissipation low
fined as inputs at reset. If they are either open or will enough for battery operation. An extremely low stand-
eventually become outputs, they have no driving source by power supply current of 10 /LA maximum is
and are floating. With normal CMOS input circuitry, this guaranteed over the full operating temperature range
could cause a high current situation. On the PPI port for both the PPI and the octal latch. This is especially
pins, however, bus-hold circuits maintain a logic I level desirable in idle or low power modes of operation. Since
internally and externally until the ports are either de- these devices see mostly static operation, the standby
fined as outputs or overdriven by an external source. current level is the dominant factor in overall power
To overdrive the bus-hold circuits, an external driver dissipation.
must supply 300-/LAminimum sink or source current at With the use of bus-hold devices on all port inputs,
valid input voltage levels. Since this bus-hold circuitry is the PPI eliminates the need for pullup resistors to pre-
active and not a resistive-type element, the associated vent undefined signal states. Upon being reset, all port
power supply current is negligible. The PPI standby cur- (A, B, and C) pins are pulled high by internal bus-hold
rent specification is 10 /LAmaximum. devices instead of the standard NMOS PPI procedure of
All 8OC86 peripheral family devices are designed with putting all port pins into the high impedance state. The
fully static circuitry. This allows the devices to be bus-hold devices also provide valid logic levels to CMOS
operated from dc to their individual maximum rated inputs connected to the port pins prior to port initializa-
frequencies. Since operating power is 'critical in low tion. Shaded areas in Fig 3 indicate where pullup resis-
power applications, the user can control this parameter, tors, normally needed for CMOS systems, are eliminated.
A low level external drive input (10 = 300 /LA) can
overcome the bus-hold function. If the port input is
unused, the bus-hold device maintains a high logic level
and provides a valid logic input to the port pin. Since
the bus-hold device is an active component on the chip
and the PPI standby current is specified as 10 /LAmaxi-
mum, dc standby current is decreased by a factor of
1000 from the levels seen with pullup resistors.
Functional update is simplified by a readable control
word on the PPI. Status of this device can be obtained by
EXTERNAL PROGRAMMABLE
PERIPHERAL INTERFACE a control-word read operation. Data are transferred
PORT B,C 110 PINS from the PPI control register, eliminating the need to
store port configurations in system memory or internal
registers.
Used in this application for address/data bus demulti-
plexing, the octal latch keeps power at a minimum with
Flg:2 Bus-hold circuitry used 0:1 the I1CS5A programmable a specialized input circuit design. Gated inputs on the
peripheral Interface CMOS peripheral. Logic 1 level Is octal latch prohibit the passing of invalid input states to
maintained Internally on undefined port pins to keep power octal latch internal circuitry during the time data are
conlumptlon to a minimum. latched. This prevents undefined logic states and high
current transients due to input switching.
 Fig 3 Parallel I/O port PORT
expansion with CMOS A
peripheral low power Vex
consumption and
elimination of external PORT
pull up resistors (shaded 8
areas) are benefits of CMOS Vex
techniques.

PC7
80C48 82C55A
FAMILY PROGRAMMA8LE
MICROCOMPUTER PERIPHERAL INTERFACE

Waking up the processor

One of the most appealing features in many CMOS Addressing for the 82CS9A PIC takes a 2-level approach-
microprocessors is the interrupt wake-up from power- standard read/write operations and interrupt vector
down mode. In this operation, the CPU is brought back transfer. Since there is no interrupt acknowledge (INTA)
from a low power idle mode by an external interrupt. signal available from the processor (this line is needed to
Typically, simple interrupt schemes must be imple- transfer the interrupt vector information from the PIC).
mented since only a single external interrupt is avail- the necessary decoding for these two sets of operations
able at the processor itself. With the 82CS9A CMOS must be handled elsewhere. A single HD-644Q CMOS line
priority interrupt controller (PIC). eight separate inter- decoder and one 74HCOO quad 2-input NAND gate will do
rupting sources can wake up the processor on a priority the job. A single bit from port B (PBI) is used to gate the
basis. For complex systems, 64 interrupts can be ser- microcomputer RD signal to the 82CS9A PIC RD input for
viced via the cascaded connection of up to eight PICS. standard data transfers (PBI = logic 0), or to the INTA
Fig 4 shows how the PIC accommodates several inter- input for vector information (PBI = logic I).
rupts in a single-chip CMOS microcomputer system.

AS

F1a4 Multiple laterrupt

AI2
All
I--
SYSTEM CS

B
haadUaa la priority IRO

I
P80 AD
laterrupt coatroUer CMOS
chip. Up to elaht levels of P81 EXTERNAL
INTA
INTERRUPTS
laterrupts are possible,
with a slape 1I1C59A priority
iDterrupt coatroller. \VA IR7

Riw III
CASCADE LINES
87 01 CASO TO OTHER
CASI PRIORITY
80 CAS2 INTERRUPT
00 CONTROlLERS
IlQ INI ~Mli Vex
MC146805E2 82C59A PRIORITY
PROCESSOR INTERRUPT CONTROllER
 vectoring. The lower three bits (DO through 02) provide
TABLE 3 the offset based on the interrupting source.
INTA signals are generated by decoding specific ad-
Priority Interrupt Controller Chip Interrupts
dresses' output during load accumulator (lOA) instruc-
Interrupt Bit Assignments tions. The vector information transferred during the last
INTA cycle can be used in an interrupt service routine
Interrupt using an indexed jump to locate the specific service
Request
Innuts 07 06 05 04 03 02 01 DO program.
The timing diagram in Fig 5 shows a 146805 micro-
IR7 T7 T6 T5 T4 T3 1 1 1
computer's response to a wake-up interrupt, along with
IR6 T7 T6 T5 T4 T3 1 1 0
the necessary INTA generation and vector information
IR5 T7 T6 T5 T4 T3 1 0 1
retrieval from the PIC. The ability to wake up an idle
IR4
IR3
T7
T7
T6
T6
T5
T5
T4
T4
T3
T3
1
0 , ,
0 0
CMOS microcomputer with any of several interrupting
sources greatly increases single-chip system flexibility.
IR2 T7 T6 T5 T4 T3 0 1 0
IR1 T7 T6 T5 T4 T3 0 0 1
IRO T7 T6 T5 T4 T3 0 0 0 High resolution timing
Although the increased speeds of CMOS microprocessors
A PIC response can occur in either of two user pro- meet the timing requirements of many applications,
grammable modes. The first mode is the classic 8080/85 some demand a more precise reflection of time. In these
format where a call opcode is transmitted with two bytes situations, the 82C54 CMOS programmable interval timer
of additional vector information. For the most efficient (PIT) provides high frequency count capability while the
interrupt response in this system, however, the 8086 82C84A CMOS clock generator/driver (CaD) delivers,
compatible mode should be used. This mode needs only from a single input frequency, both a high frequency
two INTA pulses instead of the three required for mode 1 timer input and a lower frequency CPU clock. High
operation. During the initial INTA cycle in the 8086 resolution timing is thus accomplished with relatively
compatible mode. the PIC freezes the state of the inter- low system clock frequencies.
rupts, resolves priority, and issues the master interrupt In the system depicted in Fig 6, an 8-MHz timer fre-
codes on the cascade lines. No data are transmitted on quency is used with a 4-MHz CPU clock. The caD gener-
the data bus during the first cycle. On the second INTA ates three output signals: osc is the crystal frequency;
cycle, a byte of interrupt code is sent to the CPU. This ClK is the crystal frequency divided by three; and PClK
acknowledgment byte is defined in Table 3. The host is the clock frequency divided by two. A 24-MHz paral-
CPU programs the upper five bits (03 through 07) at ini- lel resonant, fundamental mode, AT cut crystal on the
tialization. They provide the base address for interrupt caD results in a 24-MHz OSC frequency, 8-MHz ClK

146805 iRQ BIT SElINSTRUCTION TO ENABLE INITIAL

--.j WA'E·UP 1 RESPONSE 1 PRIORITY INTERRUPT CONTROLLER INTA I-INTA GENERAlION_I_SECOND INTA_!

OSC 1 ~Jf//////////////Jf~JfmzmJ/l/j//////II/7////I,0?ff,0V///l/ff/!07/@/$////f//l/

PBI
v
~~lAEJCTION
j/'
lIRST LOA INSTRUCliON
GENERATES fiRST

--'1
INTA

"-.'NTA
NO DATA TRAtrERRE~
FROM PRIORITY INTERRUPT
CONTROLLER ON FIRST INTA

\
SECOND LOA
FOR SECOND
INTA
f INTERRUPT VEClOR TRANSfERRED

ON SECOND INTA

CS PRIORITY ENABLED
INTERRUPT _ _
~~ U u
p~~6~,l~ LJ LJ
INTERRUPT
CONTROLLER

Fig 5 Timing diagram of microprocessor response to a wake-up interrupt. Any of several

Interrupts can initiate the wake-up response.
 Cl RESET ill
XI

J~,mm ::~~i
Flg 6 CMOS programmable
F CI
XI
AENI
iINi
'HI
CSINC
CL'
PCL'
OSC
ASINC C!
ViR
CLK 0
GATE 0
Interval timer and clock ifIj OUT 0
F/e ROYl OCTAL LATCH
generator. Such a system GNO ROIl CLK I
provides high timing 00 AO GATE I
8/C84A 001 Al OUT I
resolution from low system CLOCK
clock frequencies. GENERATOR/DRIVER CLK I
GATE I
OUT 2

8/CS4
PROGRAMMABLE
INTERVAL TIMER

frequency, and 4-MHz PCLK frequency. The system read count operation is initiated, the current count is
thus has an 8-MHz count frequency and 2-MHz NSC800 held in a count register until the read is completed. The
operation. If an upgrade to 4-MHz operation is desired, count register is then updated to the new elapsed count
the 8-MHz CLK output from the PIT can clock both the status. If lower system operating power is desired, or if
processor and the PIT. The guaranteed maximum count a slower CPU speed is needed, the 82C84A CGD base fre-
frequency for the PIT is 10 MHz minimum. The 8-MHz quency can be reduced. Since CMOS operating power is
output from the CGD meets the minimum pulse width directly related to frequency, both CGD and PIT oper-
requirements for the PIT clock input. This high count ating power will be lower at these reduced frequencies.
frequency allows resolution of time increments down to The advent of a diverse group of CMOS peripheral
125 ns, even with processor T-state periods of 500 ns. chips heralds a new era in system design. Applications
Two software features-a readable status word and demanding low power consumption, high performance,
realtime count indication-allow full 82C54 PIT control and portability can now be served by an entirely CMOS
in high frequency applications. The status-word read oriented approach. Broadening CMOS applications into
capability enables the processor to get an accurate indi- areas hitherto restricted to the realm of other tech-
cation of device status and reconfigures the counter nologies will allow designers more flexibility in creating
when necessary. For accurate realtime count readings, tomorrow's systems.
the PIT can be read while still incrementing. When a
 CUSTOM MICROPROCESSOR
POWERS OFFICE WORK STATION

o Generous use of complementary-Mas semiconductor A significant jump in transistor density on the 6120
technology in a new processor chip and in many other owes much to the move to 4-",m technology, but it is also
circuit components imparts high performance and out- due in part to enhanced on-chip interconnection tech-
standing reliability to a combined small-business com- niques. The die size of the 6120 is 230 mils by 210
puter and office-automation work station. Beneficiary of mils-only a 20% increase in die area for a 175%
the C·MOS magic is the DECmate Work Processor, the increase in transistor count as compared with the 6100.
newest member of the fully compatible family of word-
Old reliable
and data-processing systems based on the 12-bit PDP-8
architecture. Its new integrated-circuit processor, called The high reliability experienced with the 6100 C-MOS
the 6120, runs an extended PDP-8/ A instruction set, chip in more than four years in the field, as well as the
including memory-address expansion on chip. low power consumption and other design benefits of this
For both the 6120 processor and the 6121 input/out- technology, made it an easy decision to use such logic in
put controller, C-MOS was deemed superior to less- the 6120 processor chip. Furthermore. there were many
power-efficient static n-channel MaS technology and good reasons to extend the use of C-MOS in preference to
also to more complex dynamic noMOS technology. noMOS and TTL logic wherever possible among support
Although dynamic noMOS could have reduced the functions surrounding the central processor.
amount of power required, as compared with static parts. C-MOS was also chosen for the 6121 custom I/O con-
a dynamic design would not have been as clean to work troller chips designed for this product-two of them on
with for the logic functions needed. the processor board and one on the optional communica-
In the asynchronous environment of static logic, chip tions-controller board. C-MOS is used. as well, for the
designers need not be as precise in planning timing' read-only and random-access memories in the control
tolerances as is necessary to maintain two-phase clock store of the processor board and for the universal asyn-
synchronization in dynamic logic. Moreover. single-step chronous receiver-transmitters in the serial printer and
design debugging in static logic allows the designer to keyboard control circuitry, also on board. The control
see individual problems as they happen at slow clock memory is used for such functions as self-testing, termi-
speeds. The system clock may be brought down to de if nal I/O emulation, floppy-disk control, and a buffer
desired, there being no minimum cycling rate required. memory and control registers for the video display.
Altogether, there are 27 static C-MOS ICs on the
C-MOS is superior
microcomputer board and 14 more on the communica-
The 6120 chip (Fig. I) was a joint development proj- tions-controller board. However, dynamic noMOS was
ect between DEC's Small Systems Engineering group and chosen for main memory to achieve the maximum stor-
the Harris Semiconductor division of Harris Corp., Mel- age capacity per dollar. These RAMS are the only dynam-
bourne, Fla. It is about three times faster than the ic circuitry on the processor board.
predecessor 6100 C-MOS processor used in the earlier
Memory control
WS78 computer.
The speed improvement was measured executing a On-chip memory-extension control in the 6120 boosts
representative mix of instructions. In fact. the 6120 is its addressing capability over previous family members
even a little faster than a PDP-8/ A minicomputer run- from 4-K 12-bit words to 32-K words in each of two
ning the software of the WS200 multiterminal word- separate memory spaces. In addition, the new chip exe-
processing system. cutes the memory-extension instructions faster. It also
Two differences between the 6100 and 6120 are chief- contains 12 special-purpose registers and control logic,
ly responsible for the speed hike. First. the 6120 was along with the arithmetic and logic unit.
designed to perform some operations in parallel, but the Extensions to the PDP-8/ A instruction set include
6100 processes all functions serially. For example, the stack-command macroinstructions that permit more effi-
page addresses in memory are calculated at the I/O pins cient encoding of the ROM-based firmware. Another
while data is being computed in the arithmetic and logic benefit from the expanded instruction set is the addition
unit. Secondly, the shrink from 6-micrometer geometry of power-up self-test diagnostics. The 6120 costs about
in the 6100 to 4-",m features in the 6120 reduced on-chip the same as the 6100, but by taking over memory-
capacitance, boosting transfer speeds with little increase extension control, it reduces total system cost.
in power dissipation. The mostly C·MOS, cool-running single-board micro-

Reprinted from ELECTRONICS, October 6,1981.

Copyright © 1981, McGraw-Hili Inc. All rights reserved.
 DIRECT MEMORY
AND
DEVICE CONTROL

1. Chip0" the old block. The 6120 C-MOS processor chip implements the much-used PDp·a architecture, executing an extended PDP·al A
Instructions set. The design uses two system buses-the data and address 1/0 bus and the C-bus-and 12 special-purpose registers (tinted).
2. Energy-eniclenl worker. The C-MOS-intensive DECmate desktop system packs a lot of function onto a small number of low-power
boards. The processor board alone handles eight functions. The building blocks implemented totally or partly in C-MOS are shaded.

computer (Fig. 2), requiring a mere IS watts. is the of gold-wire bonds subject to temperature cycling and
controller of all functions in the computer. The 11.1- possible failure. Equally important is the massive switch
by-IO.5-inch DEc-standard extended quad board con- to cool-running, low-power C·MOS. The temperature rise
tains eight major functional units: the processor. the on such a die is only about 25% above the ambient
32-K 12-bit-word main memory. address space for as temperature. while the rise on a similarly sized TTL or
much as 32-K words of control memory. a real-time noMOS die is roughly 100%. In the latter case. then. a
clock. and four control circuits. much greater temperature strain is imposed on wire
bonds and metal lines. as well as on the Ie devices
Smaller package
themselves.
The new chips allow the microprocessor and its main Like any MaS part, a C-MOS IC is self-limiting-
memory to fit on a single board. The equivalent ICs circuit currents drop as temperature rises. In TTL parts.
including the 6100 processor in the older WS78 occupy higher temperatures result in increased currents-which
three larger boards and one slightly smaller one. The can ultimately lead to cyclic degeneration or thermal
number of 14-pin-chip equivalents was reduced from runaway. Since C-MOS runs cooler than other MaS tech-
375 in the WS78 to 200 in the DECmate. The 80% net nologies. the resultant parts offer a more generous tem-
reduction in board area stems in part from the use of perature safety margin.
large-scale integrated circuits. the other factors being Through the use of static CoMes logic in the 6121 I/O
the combining of the terminal and central processors controller, board space and power were saved again.
that were separate in the WS78 and the tighter board Because the 6121 spends much of real time in an inactive
layout possible with improved printed-circuit boards. state. dynamic logic would have required a good deal of
The almost 50% reduction in chip population increases refresh circuitry either on the chip or in discrete logic.
long-term reliability because it reduces the total number The three 40-pin 6121 s perform I/O control for five
 THREE'STATE ENABLE LATCHED BUS

INPUT/OUTPUT WRITE, RW

3. C-MOS to the re.cue. When the DP278 communications controller for the DECmate was using too much power. consumption was cut
from 6 to 4 watts by using the C-MoS 6121 ilo controller chip and replacing 16 TIL chips with 14 C-MoS chips (tinted).

channels each. They are programmable, so the board ware registers, and dedicated address decoding. In gen-
designer has more flexibility in establishing channel eral, this reduced system bus noise and power require-
characteristics. ments.
C·MOS logic also offers reduced ringing and over- The system power requirements were set at a low
shoot-a cleaner signal that is especially valuable on a enough level so as to ensure reliability within a convec-
bus. There tend to be fewer difficulties with electromag- tion-cooled terminal housing. An important design goal
netic and radio-frequency interference-a point that has was as small a power supply as possible, while maintain-
increased importance today in view of the new Govern- ing the ability of adding options. A 60-w supply is used,
ment emissions regulations on office equipment. The requiring 75 w from a wall outlet. As a comparison, the
noise margins offered by C-MOS are superior to those of WS78 used somewhat over 200 w.
TTL, there being a wider tolerance for noise introduced Well into the design effort, the small power supply,
between the maximum input and output low voltages: coupled with a fixed power allotment for the processor
\.4 v versus 0.4 v. Similarly, a C-MOS receiver has a board and any further options, necessitated a very lim-
high-voltage margin of 1.4 v versus 0.4 v. ited power allotment for the DP278 communications-
control optional board. The DP278 was originally
Little wetts
designed in noMOS (four ICS) and 7400-series TTL parts
Low power consumption, chiefly as a means of optim- to minimize cost. The TTL, however, caused the module's
izing reliability, was, from the beginning of the design power requirement to be 50% over its allotment. So in
effort, a principal reason for specifying C-MOS in both the 10 functions shaded in Fig. 3, C-MOS parts were
custom and off-the-shelf parts. Whenever off-the-shelf used to cut the projected power to 4 w at 5 v dc.
C-MOS chips were available, they were used in preference Replacing 16 TTL chips were 14 C-MOS equivalents-
to their TTL counterparts for bus buffering, special hard- about 19% of the module. 0
 "Reprinted with permission from Electronic Design,
Vol. 30, No. 16; copyright Hayden Publishing Co., Inc., 1982."

For many data-communication tasks, commercial or military, a

programmable Manchester encoder-decoder circuit has the edge over
UARTs or protocol controllers.

For data-comm links,

Manchester chip could be best
Although there are many LSI chips
for interfacing computers, terminals,
and other subsystems with serial data-
communication links, in many applica-
tions the programmable Manchester
encoder-decoder offers significant ad-
vantages over the other chips. These
advantages become apparent when
comparisons are made at the system
level.
The list of competing circuits in-
cludes universal asynchronous re-
ceiver-transmitters (UARTs), multi- ~
protocol controllers (such as those for i,
various levels of data-link control), and ,
several types of encoders and decoders.
But it is often difficult to compare ..
capabilities at the chip level because of
the chips' different natures. Perfor-
mance must therefore be compared at
the system level, taking into account
the required throughput, accuracy, and
communication protocols.
In many situations, such analysis
shows that programmable Manchester
encoder-decoder circuits have higher
data rates, overhead efficiency, and accuracy. Unlike thanks to its programmability, to compete with
other controller chips, however, these devices do not UARTs and multiprotocol controllers in a wide range
perform serial-to-parallel or parallel-to-serial data of commercial applications as well.
conversion. Also, additional circuitry is needed to It is built with CMOS technology and comes in a
implement some standard data protocols, thereby 40-pin package. Capable of data rates up to 2.5
making them less cost-effective in those applications. Mbits/s, the 15531 has power dissipation of only 50
The Harris HD-15531 aptly illustrates the mW. As a transmitter, it encodes nonreturn-to-zero
capabilities of systems built with a Manchester code into Manchester code; as a receiver, it decodes
encoder-decoder chip. Originally aimed at military the Manchester back into NRZ. The data word length
applications (see "Interfacing with a Military Data- is programmable from 2 to 28 bits.
Comm Bus"), the 15531 is sufficiently versatile, Other programmable characteristics include pari-
Lester Sanders, Member of the Technical Staff ty polarity and synchronous/asynchronous clock
Harris Corp., Semiconductor Digital Products Division operation. Independent encoder and decoder sections
P.O. Box 883, Melbourne. Fla. 32901 on the chip allow full-duplex data communication.
Also available are lower-cost preprogrammed UARTs and data-link controllers on the basis of data
versions (the HD-15530 and HD-6408) in 24-pin rate alone. However, the questions of communication
packages. protocol and overhead efficiency remain to be re-
solved. In many cases the 15531 will offer further
Speed without sacrificing accuracy
advantages in those areas.
The goal in data-communication systems is max- Since accuracy should not be sacrificed to achieve
imum throughput combined with maximum ac- throughput, the synchronization schemes used by
curacy. But there are several conflicting tradeoffs. the various data-communication circuits must be
First, a need for extreme accuracy tends to restrict considered. Synchronization is the key to accurate
the throughput. Then, too, throughput depends on reception of incoming data. Because they transmit
both the data rate and the overhead efficiency. data in Manchester code rather than NRZ,
Finally, overhead efficiency relates directly to the Manchester circuits are better at synchronization
communication protocol employed. than UARTs and DLCs. Also, the 15531 establishes
Therefore protocol and data rate are used to synchronization by recognizing a 5-bit sequence, and
measure the effectiveness of data-communication its relatively powerful error detection circuitry
ICs. The most popular LSI circuits for data com- further enhances accuracy.
munications are UARTs and data-link control chips. Manchester code offers other useful advantages in
Some UARTs operate at up to 500 kbits/s, but most addition to reliable synchronization (see "Manches-
work in the 40-to-50-kbaud range. Similarly, some ter Code Gaining on NRZ"). For one, it is self-
data-link controllers operate at up to 2 Mbits/s, but clocking, so that a wire for the clock signal is not
1 Mbit/s is more typical. With a maximum data rate needed, thus reducing transmission-line costs. In
of 2.5 Mbits/s, the 15531 clearly outpaces both addition the Manchester code has no dc or low-
frequency components in the waveform; therefore

Bitpe,;od

~
NRZ data
I' \21314151617\819110111112\
r-
• - -
)( I )( )( )( ) ()(

IStart I
- -

08'8
-
)()(
-
)()(
-,I
')(

1 I
-rr-
Stop
signals can be ac-coupled with transformers
capacitors, thereby lowering system costs, and in
some applications avoiding errors or failure caused
by interference.
Protocols and data formats
or

(I) bils

Usually, system designers select data-communica-

tion ICs primarily on the basis of the data structure
used in a particular application. For example,
80'
16 bils
I Any number
01 bits
I 8 bits
I UARTs and programmable Manchester circuits
transmit data asynchronously (though synchronous
(b) operation is possible with the 15531), whereas data-
link controllers send data synchronously.
=-:1---] ~~
Dparity A data-communication protocol is the implied set
Command or
16 dala bits
of rules that establishes communication between a
data sync
(e)
transmitting and receiving station. The information
structure in any serial data-communication scheme

=:-=1---'
Command or ~~
o Parity
includes both control information and data. The
control information performs such functions as de-
data sync
2 to 28 dala bits lineating data, defining the amount of data to be
(d)
transmitted, providing the addresses of the
transmitting and receiving stations, and error han-
1. The datalormats 01 UARTS (a), protocol controllers (b), dling. Figure 1 compares the data formats ofUARTs,
and Manchester encoder-decoders (c and d) differ vastly, the DLC circuits and the 15531.
each offering advantages lor different applications. The
UARTs have programmable data formats. They
HD-6408 and HD-15530(c) have allxed, 16-blt word length,
whereas the HD-15531 (d) has a programmable word length. frame from 5 to 8 data bits with 2 to 4 frame bits,
using start and stop frame bits to define the begin-
ning and end of a character. A programmed parity
bit can provide error detection.
In data transmission, those bits that are not data
are considered to be overhead, and overhead efficien-
cy is a measure of the amount of data contained in
a message. To calculate the typical overhead efficien-
cy of a DART, assume that a 7-bit ASCII character 87.5%.
is transmitted and that the DART is programmed Data-link, or multiprotocol, controllers typically
for a parity bit and one stop bit. Thus, including the generate such bit-oriented protocols as Synchronous
start bit, 3 control bits are used in a 10-bit frame, Data Link Control (SDLC), High-level Data Link
for an overhead efficiency of 70%. Control (HDLC), and Advanced Data Communica-
With the 15531, the length of the transmitted tions Control Procedure (ADCCP). These protocols
character is also programmable-in this case, from frame blocks of data with byte-wide or multibyte-
2 to 28 data bits. A 3-bit synchronization pulse and wide fields like preframe sync, address, control,
a parity bit frame the data word. The 3·bit sync pulse cyclic redundancy check (two bytes), and post-frame
is an invalid Manchester pattern generated by the sync so that six control bytes are required to send
encoder and recognized by the decoder. The sync a data field of 0 to 256 bytes (extended with HDLC
pattern consists of llh bits in one state followed by and ADCCP). Therefore the overhead efficiency of
llh bits in the opposite state. (As will be shown later, multiprotocol controllers ranges from zero to nearly
this particular pattern has definite advantages for 98%. Table 1 compares the overhead efficiencies and
synchronization.) The use of 3 bits plus parity means other important characteristics of all three types of
that 4 overhead bits are required to send as many data-communication circuits.
as 28 data bits-yielding an overhead efficiency of Arbitrarily sized gaps between characters occur

Although nonreturn-to-zero The diagram compares NRZand Note that with NRZ code, only
(NRZ)code is still the most widely Manchester codes for the binary one symbol (lor 0) is required to
used in data-communication sys- expression 01100. Note that the represent a data cell. Therefore
tems, Manchester code is gaining NRZ version represents the binary the data transfer rate is the same
ground rapidly. Already it is ex- value with a static level through- as the information rate. With
tremely common in magnetic tape out a bit period-where a binary Manchester, however, two sym-
recording and fiber-optic com- o is a low logic level and a binary bols are needed for each cell. That
munication systems. More recent- 1 is a logic high. Manchester code, means that a modulation rate
ly, it has gained support for serial on the other hand, has a logic twice that of NRZ is needed to
data communications. The Ether- transmit the same amount of data
net office network-supported by BI.perlod I i1 2 : 3 !•! i 5 -a possible drawback in band-
Xerox, Digital Equipment Corp., t I I I I I
width-limited communication
Bln.rYCOd'~1 0 I 1 I 1 I 0 I 0 I
Intel, Hewlett-Packard, and '. I I channels.
Nonraturn 0 I I I
others-specifies Manchester The advantages of Manchester
phase encoding. Also, MIL- 'ozo,o ,
Manch •• tIT11-
'lJ1lJllJ1.r1'
I I
I code include self-clocking, in-
STD-1553 specifies Manchester o I
herent error detection, and the
code for an avionics data bus (see absence of a dc component-which
"Interfacing with a Military Data- transition at the middle of each bit allows ac coupling.NRZ,however,
Comm Bus"). period. The binary value of data requires no additional encodingor
Strictly speaking, the coding is represented by the direction of decoding, and it makes the most
scheme referred to as "Manches- the transition: a high-to-low mid- efficient use of a communication
ter" should be called "Manchester bit transition represents a logic 1, channel's bandwidth. Another ad-
II," as it differs from the original and a low-to-high represents logic vantage of NRZ is that it is sup-
Manchester code, which is almost O. The midbit transition repre- porte<1by a wide range of ICs.
never used today. Also known as sents both the data and the clock. However, the introduction of
biphase-L, Manchester code is dis- Because the clock' and data are Manchester LSI chips, such as the
tinguished from NRZ and others included in a single serial data HD-15531,signals increasing sup-
by a transition at the center of stream, Manchester is known as a port of Manchester code by
each data cell. self-clocking code. semiconductor companies.
with asynchronous data transfer. Typically such control, and CRC fields-clearly inefficient for
transfer occurs when a human-operated peripheral, transmission of a single character.
such as a keyboard, interfaces with a computer; the A programmable Manchester circuit like the 15531
interval between characters is arBitrary. In contrast, is much better suited to process-control applications.
with synchonous data transfer the characters are In addition to providing high data rates, it has a
transmitted contiguously. Synchronous data trans- programmable data format, which can be useful for
fer occurs typically in computer-to-computer in- interfacing with a-d and d-a converters. For example,
terfaces. Although there are exceptions, UARTs are the programmable character length makes it easy
traditionally used for asynchronous data transfers, to upgrade an 8-bit conversion system to, say, 10-
and protocol controllers for synchronous data. Usual- or 12-bit resolution. In contrast, UARTs are limited
ly-but not necessarily-synchonous data transfer to 8-bit characters and are therefore difficult to
is faster than asynchronous. operate with 10- or 12-bit converters.
In many situations, however, both UARTs and Protocol requirements are satisfied with various
data-link chips are limited in speed, overhead effi- degrees of completeness by available data-com-
ciency, or both. UARTs, especially, lack the munication circuits. UARTs merely provide a frame
throughput needed for the more demanding data for the character, plus bits for framing and parity
networks. Data-link controllers, on the other hand, error checking. Protocol controllers provide some-
have excessive overhead when single characters are what more, using established fields to facilitate data
transmitted, because, as explained, each frame has communication. For example, the address field de-
an overhead of six bytes, even if the frame length fines the address of the remote station for which the
is only one or a few bytes. data is intended, and the control field defines the
As an example of the limitations of protocol nature of the transfer. Both types, UARTs and
controllers, consider systems for process control or protocol controllers, perform the parallel-to-serial
data acquisition. Typically, such systems have many and serial-to-parallel conversions needed for com-
remote stations sending data to a primary comput- puter interfacing. In addition, most protocol con-
er. At the remote stations, input or output devices trollers provide address recognition.
(such as temperature sensors) communicate a single Several of the 15531's functions prove useful in
8-, 10-, or 12-bit word through analog-to-digital or generating a protocol. The Sync Select input, for
digital-to-analog converters. With a protocol con- instance, allows the polarity of the synchronization
troller, however, the fixed-format frame would re- pulse to be selected at the encoder. Since this polarity
quire the opening and closing flags and the address, is subsequently recognized by the decoder, it provides

2. Two sections of the 15531 decoder circuitry playa role In synchronization. The synchronizer
detects signal edges and operates at 12 times the data rate, and the synchronlZ8tlon-pulse
recognizer detects specific paltarns.
 The HD-15531 Manchester en- signals can be ac-coupled, allowing The figure shows the connections
coder-decoder was developed origi- the use of transformers and when the 15531 is used with a
nally for military applications. simplifying the design of fiber- UART from Standard Microsys-
Specifically, it was designed to optic transmission systems. In tems. The COM-1553A SMART
meet MIL-STD-1553A, a time- turn, the isolation provided by (synchronous-mode avionics re-
division- multiplexed bus for mili- transformers or fiber-optic cables ceiver-transmitter) converts par-
tary aircraft. minimizes interference from other allel data into serial form and vice
Manchester code brings several electrical systems. versa, recognizes addresses, and
important benefits to military Of course, the 15531 and other counts words for error detection.
avionics. For example, because it ICs designed for MIL-STD-1553B Also, it provides a convenient in-
is self-clocking, it allows serial meet the temperature and other terface with a microcomputer or
data transmission over a single environmental requirements of other controller via an 8-bit data
twisted-wire pair, thus minimiz- military systems. The military bus. As can be seen, in the figure,
ing weight and space require- standard provides a 1-MHz data- the two chips are extremely com-
ments. Also, accurate synchroni- communication channel, so that patible.
zation and simplified error detec- real-time control is achieved To read or transmit the control
tion enhance system reliability, so even when many signals are and data words, two read or write
that the technique can safely be multiplexed. pulses must be generated to the
used for aircraft instrumentation Companion ICs for the 15531 are Read Data Enable or the Write
and control signals. In addition, available from Standard Micro- Data Enable pin respectively. Con-
unlike signals resulting from other systems Corp., Circuit Technology nections to the data-communica-
coding schemes, Manchester Inc., and ILC Data Device Corp. tion bus are from BZO and BOO.

v",
v'"
30

• RCVR INT
V", 38
Sync selecl ,
6
XmltterlNT V'"
Trans select 15
'2 3 Take dala
INT ACK Encoder par select 31
4 Take data
Qj26
Data req 6
Sync elK
Data avail 20 26 6
XMIT NAZ Sync data
Serial data in
Message complete 29 39
XMIT enable '8 Encoder enable C.
Invalid word 32 40
Send data Send data C.
OWF "
'9 34 c.2O
XMIT eLK Encoder shift elK
Aeceive data enable
XMIT data enable

COM·15S3A Valid word 14 2 Valid word HD-15531

Receive elK 13 '4 Decoder shift elK
Receive NAZ 9 5 Senel data oul
17
Command sync ;
Data sync
~ ~:::~E;.::~C
18 Decoder par selact
10 Sync eLK select
7 Sync data select
36 C)
23 C,

21 GND
a way to distinguish between two types of words in data. The optimum time to do that is midway
the communication between the transmitting and between the data transitions, because this allows
receiving stations. Then, for example, the transmit- time for the signal waveform to settle from the rise
ter can generate a command sync pulse to indicate and fall times.
to the receiver that a particular word contains Since transitions in Manchester code occur at the
address and control information. Similarly, a data beginning and center of the data cells, the sample
sync denotes a data word. points should be one-quarter and three-quarters of
the way through the data cell. A transition detector,
Techniques for synchronization
a counter, and logic circuitry team up to locate the
To compare the accuracy of a UART and the 15531, required sampling points. With a clock of 12 times
it is necessary to understand how the two circuits the data rate, the decoder counts to 3 to find the one-
synchronize with data. Typically, a UART employs quarter data-cell point and to 9 for the three-quarters
a clock rate of 16 times the data frequency to data-cell point. For resynchronization, the algorithm
synchronize with incoming data. The stop bitfrom is reset at each transition-which occurs once or
the transmitter has a high logic level, and the gap twice in each data cell. Thus synchronization of the
between words (known as the idle state of the line) 15531 is far superior to that of a UART, which
also is high. The start bit is a low level for one bit synchronizes only once per character. With the
cell. To detect this bit, the receiver recognizes a high- 15531, sampling error does not accumulate over
to-low-level transition of the input (from the stop adjacent data-bit cells, whereas it does with UARTs.
bit or idle state). The receiver then verifies the start Interfacing with a serial data bus
bit in two steps: by counting eight cycles of the 16x
clock to reach the center of the start bit and by The 15531 performs word framing, error checking,
checking to make certan that the start bit is still low. and Manchester encoding and decoding for a serial
If the sample yields a high logic level, the receiver interface. It interfaces with a serial bus in either a
knows that the start bit is false. It then continues single-ended or a differential format. Because the
to look for a high-to-low transition. Thus circuit receives and sends NRZ serial data, parallel-
synchronization with a character is initiated on the to-serial and serial-to-parallel shift registers are
basis of two states. needed to communicate with computers, which
Two sections of the 15531's decoder are involved operate on parallel data.
in the synchronization: the synchronizer and the To interface with a 16-bit parallel data bus, two
sync-pulse recognizer (Fig. 2). The former includes
edge-detection circuitry, and its clock frequency is Table 1. Comparing data-comm circuits
12 times the data rate. The latter can detect a
particular type of data pattern that is 5 bits wide. Manchaatar
Protocol ancodar·
The pattern consists of Ilh data cells at one logic level, UART controllar decoder
followed by Ilh data cells at the opposite level, Maximum 50 kbaud 1-2 Mbaud 2.5 Mbaud
followed by two valid Manchester bits (Fig. 3). A data rate
valid Manchester bit is defined as one with a midbit Overhead
transition, and it is detected by the Exclusive-OR efficiency 70% 0-97% 80%
gates shown in Fig. 2. Error Parity. framing Cyclical Bit count.
detection redundancy parity, valid
Although the synchronization scheme of the 15531 check Manchester
requires three bits of preframe sync, as opposed to Code NRZ NRZ, NRZ-1 ManChester
a UART's single bit, it checks a total of 10 states Disad- Poor Inefficient Requires
for synchronization. Therefore synchronization is vantages throughput overhead for shift registers
much more reliable with the 15531 than with a for large character
blocks of data transmission
UART.
Manchester code has a transition in the center of
a data cell, and depending upon the data pattern,
it also may have a transition at the beginning of the
data cell. Transitions not only determine whether the
data is a logic 0 or a logic 1, they also provide
references to which the decoder can synchronize.
Unlike UARTs, which synchronize only at the begin-
ning of each character, the 15531 synchronizes with
each transition. After it has been reset, the decoder
needs to know when to sample the logic state of the
74C165 shift registers can be used (Fig. 4). The 15531 An example of how the 15531 interfaces with a
strobes the CLK inputs of the shift registers with controller for use as a transmitter, with the help of
the NAND product of the Send Data and Encoder an Intel 8255A programmable peripheral interface
Shift Clock outputs. The parallel inputs are loaded (PPI) chip, is shown in Fig. 4. A general-purpose I/O
just before Send Data goes high, which happens after device, the 8255A has 24 1/0 pins that can be
the sync pulse has been shifted out of the encoder configured for any of three modes of operation. An
(it returns low before the parity bit is generated). 8-bit data bus allows it to be connected directly to
When Send Data is high, NRZ data is shifted into a microcomputer. The microcomputer selects the
the chip. operating mode and defines the port directions with
To transmit a word, the controller or microcom- commands via the data bus.
puter must apply a high logic level to the Encoder In Mode 1, used in this example, the 24 I/O pins
Enable input of the 15531. If this line stays high, of the 8255A are configured as two 8·bit data ports
so that contiguous words are transmitted out of the and one 8-bit control and status port for handshaking
encoder, the only gap in the NRZ data is the 3-bit operations. The data ports, Port A and Port B,
sync pulse and the parity bit. As noted, the type of interface directly with the two parallel-to-serial shift
word transmitted (control or data) is selected with registers.
the Sync Select input. Operation as a transmitter

To transmit, the microcomputer generates a write

signal to the 8255A, which then sends an Output
Buffer Full (OBF) signal to the Encoder Enable input
of the 15531. One of the two programmable I/O pins
(PC. in this case) controls the polarity of the sync
pulse to define the type of word transmitted. If
desired, the Send Data output of the 15531 can be
used to acknowledge the transmission of a word.
3. For synChronization, the decoder section 01the 15531
When Send Data returns low, the microcomputer can
s.mples at 10 points to recognize a pattern that h.s • tot.1
length 015 bits. The p.ttarn h.s 1Y2 bits .t onaloglc lavel,
generate another word. The 15531 transmits
lollowed by 1Y2 bits .lthe opposite level, end culmlnetes with Manchester code onto the serial bus as logical com-
two velld Menchester bits. plements at the Bipolar Zero Out (BZO) and Bipolar

4. The transmitter section ola terminal based on the 15531 Includes 74C165 shift registers to convart parallel
signals from the controller Into serial data lor the Manchester encoder. An 8255A programmable peripheral
Interlace bullers the processor to minimize system overhead.
 .LV iI.LV"lU"" Q .LV-Ul'" ilQ.LQll""l nv.LU "U~U "'u'"' .LVVV.L

is operated as a receiver, the Serial Data Out (SDO) tion circuitry is provided, the 15531 must interrupt
pin of the 15531 is connected to a pair of cascaded the 8255A with the reception of every control and
74C164 serial-to-paral1el shift registers (Fig. 5). The data word on the data bus. That will require that
Take Data (TD) and Decoder Shift Clock (DSC) the microcomputer read each control word to find
outputs of the 15531 are ANDed and used to strobe the terminal for which the message is intended. Of
the shift registers. The Valid Word (VW) signal goes course, regardless of the address-recognition scheme
high approximately half a clock cycle after the final used, the data words fol1owing another station's
bit in a word is shifted out, and the latter action message should be ignored.
is indicated when TD returns low. The paral1el data The system shown in Fig. 5 includes hardware that
from the 74C164s must be latched to define the provides address recognition for one of 16 terminals.
beginning and end of the word. The VW output of the 15531 latches data into the
To operate the 15531 as a receiver, a second 8255A 82C82 CMOS octal latching bus drivers. Hard-wired
is used; as shown in Fig. 5. As with the transmitter inputs, bo-ba, of a 7485 magnitude comparator
subsystem, the 8255A is configured in Mode 1..Once define the station's address. The receiving terminal's
again, Port A and Port B serve ad the interface with corresponding address on the data bus is input ao-aa.
the data bus, and Port C provides the necessary If these inputs match the hard wired inputs, the
handshaking signals between the 15531 and the signal a = b goes high.
microcomputer. A signal into the"STB pin latches The 7485 has no way of distinguishing between
the data word into the 8255A. The 8255A subsequent- control and data words. Therefore, since a data word
ly outputs an Input Buffer Ful1 (IBF) signal and may contain a pattern that arbitrarily reproduces
fol1ows with an Interrupt (INT) signal. a terminal's address, the a = b output is NANDed
Depending on the required functions, the receiver with the VW and CMD SYNC outputs from the 15531.
interface has a variety of possible forms. Many of The CMD SYNC output must be latched, because it
the functions can be provided by either hardware or returns low before VW goes high. For a serial bus

Table 2. Control codes for a network protocol

Control
field From To Control command
o 0 0 Primary Remote Transmit a character to the
terminal primary; message poll
o 0 1 Remote Primary Transmit character feedback;
terminal remote terminal has message
to transmit
o 0 1 Primary Remote Receive the following message
or remote terminal
terminal or primary
1 0 0 Primary Remote End of messag&-from originating
or remote terminal to receiving remote terminal
terminal or primary
1 0 1 Primary Remote Message error; retransmit-from
or remote terminal originating to receiving remote
terminal or primary terminal
11 0 Primary Remote Acknowledge valid messag&-from
or remote terminal receiving to originating remote
terminal or primary terminal
111 Originating Primary Message transfer Is compiete;
remote bus is free
terminal
with more than 16 terminals, 7485s can be cascaded to receive. As before, the C ports provide the control
to provide the expanded address recognition. and status functions for handshaking between de-
Some functions, however, are usually better vices. The modified bus structure allows reading or
served by software than by hardware. One such writing of the 16 data bits in a single operation.
function is the word count of the message length. Distinguishing control Information
The transmitting station generates a word that
contains the message length-that is, number of As shown earlier, the 15531 generates and detects
words in the message. To ensure that the message programmable sync pulses that can be used to tag
is transmitted and received accurately, the receiving different types of information. Thus the chip
station counts the Data Sync outputs and matches generates and recognizes two types of words: control
the total with the transmitted word count. (If the and data. To communicate control information
24-pin Manchester chip, the HD-6408, is used, the between transmitting and receiving stations, specific
Data Sync output is multiplexed with the Command meanings must be preassigned to various bit com-
Sync output. Therefore Take Data can be Exclusive- binations. That, of course, must be done as part of
ORed with the Command/Data Sync output to pro- the system design.
vide the word count.) To illustrate the design procedure, consider a
For interfacing with a microcomputer or controller multidrop serial data communication network. The
with a 16-bit data bus, a different design is ap- system will handle both asynchronous character
propriate. This scheme, too, uses two 8255As in Mode transfers (such as instrumentation data) and block
1. But instead of dedicating one 8255A to messages. Basically, the system consists of a single
transmission and the other to reception, it uses the primary station and a user-definable number of
A ports of both 8255As to transmit and the B ports remote terminals. For simplicity, just one primary

74Cl64 Q .• 017 a2C82 00, PA, 8255A

serial-Io-parallel octal latching programmable

CLK
shift register bus driver
~~~~:~:l 080

010 000 PA,

DO, PA,
DO, PA,
DO, PA,
74C164 01, 01, 82C82 DO. PA,
serial·to-parallel oclal latching 005 PA,
shift register busdriver 00.
PA,
DO, PA, 5T8.
PC,

7485 a=b
magnitude
comparator

5. A receiver circuit built around the 15531 uaea 74C164 ahlll reglatera for aerlal-to-parallel converalon. The
82C82 latching bua drlvera and the 7485 magnitude comparator provide hard-wired addreas recognition. As
with the receiver, an 8255A acta aathe Interface to the controller.
and two remote stations will be used as a design a primary's control word.
example. In an actual system, of course, the pro- The control code in the control field instructs
grammable word length of the 15531 specifies the the receiving station to "receive the following mes-
number of stations addressed and the control sage." A list of control code commands is given in
messages. For the initial design, the length of a Table 2.
control word will be fixed at 16 bits. The receiving station identifies the source of a
Assume now that the control word is divided into message by reading the address field of the control
three fields, each of which plays a role in the protocol word. The originating remote terminal then
of the data-communication network. For this exam- transmits a special data word (the only data word
ple, the first six bits of the control word give the that is used as a control word). Since in all other
address of the station transmitting the control word, instances data words contain only data, this excep-
the next four bits form the control field, and the last tion must be recognized by the controller software
six bits provide the address of the intended receiving of the receiving terminal. This data word gives the
station. With such an arrangement, the number of number of words in the message. Were a control word
possible stations that can be addressed is 26, or 64, used here instead of a data word, the arbitrary data
and the number of control commands that can be pattern indicating the message length could trigger
issued is 2·, or 16. the address-recognition circuitry of another terminal
The system uses a primary terminal to poll remote on the bus. The address and control fields could be
terminals for a character feedback-such as a tem- repeated, but this would mean that the message
perature reading for an energy control system. At length, as defined by the word, would be limited to
the same time, it provides for block data transfers, 26 characters-which is too short.
such as messages. Actually blocks are not If there is a message, the first remote terminal
transferred synchronously, as with a protocol con- transmits the message continuously. After complet-
troller. However, the higher data rate and overhead ing the message, it transmits a control word in which
efficiency of the 15531-based system yield higher the control code indicates "end of message." Upon
overall throughput than is possible with systems receiving this word, the receiving terminal checks
with conventional block transfers. to see if the correct number of data words were
The system has the following protocol: First, the received. Then it responds to the originating remote
primary station polls the first remote terminal, terminal with a control word indicating one of two
requesting a character feedback. The control field responses.
contains a control code that indicates the type of data If the receiving terminal did not receive the
transfer. Then the remote terminal responds with message properly (the number of data words does
a control word, which verifies its address, and a not equal the number indicated by the sending
control field, which indicates whether or not it has terminal), the receiving terminal indicates this with
a message to transmit. In either case, the terminal a "message error, retransmit" control code. When the
subsequently transmits a data word-which is the originating remote terminal receives this code, it can
single-character feedback. The primary terminal go back several steps and begin retransmitting the
receives this character and stores it in memory. message with the original control word. The number
Depending upon the response of the remote terminal of retries should be limited by the sender's controller
to the message poll, the primary performs one of two software.
options. If the remote terminal did not have a If the message was received properly, the receiving
message, the primary proceeds to poll the next terminal indicates that fact to the sender with the
station, for the character feedback and message flag. appropriate control code. When the latter receives
If, on the other hand, the remote terminal indicates the indication, it transmits a control word to the
in its control-word response that it has a message primary with a control code signifying that the
to transmit, the primary idles and relinquishes message transfer is complete and the bus is free.
control of the bus. Even if there is repeated failure to acknowledge the
Control codes give commands message, the originating terminal must indicate
after the retries that the bus is free. The primary
The primary terminal's receiver remains active can then poll the next remote terminal.D
because it, as well as remote stations, can receive
messages. Message transfer can take place from any
terminal, primary or remote to any other terminal.
The message need not go through the primary. To
transfer a message, the first remote terminal
generates a control word with the same format as
 LOCAL NETWORKS
Industrial controller
joins the
MII:-STD-1553 bus
Based on low-cost, low-power
CMOS circuitry, an Industrial-
grade local-area network
controller brings high-speed
data communications to the
1553data bus.
David Q, Wllilaml, Member 01the Technical Stalf
Harris Corp., Semiconductor Group
P.O. Box 883, Melbourne, Fla, 32901

Protecting the integrity of in-

formation is the most important
function of a data-communications
system. One way to ensure secure
data communications is to design
the system's local-area network
similar to the specifications de-
fined in MIL-STD-1553. Originally
intended for the high-noise en-
vironment of military aircraft,
1553's provisions are applicable to
a variety of industrial and com-
mercial systems that must provide
high performance under adverse
conditions (see "Riding the 1553
Bus").
To bring 1553's data integrity to
nonmilitary applications, the net-
work design must cost-effectively meet space, power (l5¢1 ft per pair)
consumption, and data-rate requirements. With a A component cost of $60 per controller
these factors in mind, a CMOS network controller a The use of multidrop topology
can be designed with the following features: a Low chip count, using LSI technology
a A I-Mbit/s data rate, upgradable to 2.5 Mbits/s The block diagram of the controller is shown in
a An extremely low bit-error rate Fig. 1.Its principal component is Harris Semiconduc-
a An operating power consumption of just 150 tor CMOS HD-6408 Manchester encoder-decoder
mW, including line drivers and receivers chip, which operates at data rates of up to 1
a A bus length of 1000 ft (expandable) Mbit/s (ELECTRONIC DESIGN, Aug. 5, p.201). To
a The use of low-cost, shielded-twisted-pair cable obtain higher data rates-up to 1.25 Mbits/s-and
Reprinted with permission from Electronic Design, Vol. 30, No. 21; Copyright Hayden Publishing Co., Inc,. 1982.
Electronic oe.lgn • October 14, 1982
operation over the full military temperature range, functional equivalent of an original Intel bipolar
the HD-6408 can be replaced by the pin-compatible device, but being CMOS, it operates at a much lower
HD-15530-8, which conforms to MIL-STD-883 power-supply current-about 1 mA/MHz.
specifications. If the application warrents the Components that interface with the serial data bus
highest data rates-up to 2.5 Mbits/s-the play an extremely important role in the overall
HD-15531B can be substituted for the HD-15530-8. design. No matter how well the controller itself
To interface the controller with virtually any 8- performs, the line driver-receiver and cable combina-
or 16-bit microprocessor, the design uses two 82C55A tion can create a bottleneck through which all data
programmable peripheral interface chips. A CMOS must flow. Consequently, deficiencies in interface
functional equivalent of an original Intel part, it design become a limiting factor in the controller's
operates at much lower power levels and with far data throughput and integrity.
greater speed, thanks to circuit and technology High data rates, long cable lengths, and low power
improvements. consumption present a designer with conflicting
Selecting a suitable clock generator was one of the requirements. Most conventional line drivers and
more difficult tasks in designing the controller. The receivers handle larger amounts of power than
HD-6408 requires a 12-MHz clock input which CMOS. To accommodate CMOS technology, the con-
switches within 0.5 V of the power supply rails, and troller uses a so-called current-mode transmission
has both rise and fall times of 8 ns or less. An 82C84A system (see "Why Current-Mode Transmission").
CMOS clock generator-driver was chosen because it Current-mode transmission was developed for
supplies a buffered clock output of up to 30 MHz space satellites, in which low-power drains and very
when running from a fundamental, parallel-mode low levels of radiated and conducted electromagnetic
crystal and two capacitors. This device is another interference are mandatory. Basically, the technique

1. A self·contalned local·area network controller for driving a data bus similar to the MIL·STD·1553 data bus
with Manchester II data, tllis system runs at data rates of up to 2.5 Mbll/s and Interfaces with most 8· and
16·blt microprocessors.
switches a constant current between each of two there is another reason for its use. Because of
conductors in a twisted-pair transmission line. The CMOS's low power consumption, a sealed enclosure
total current in the pair remains constant and flows often becomes feasible. With strict FCC regulations
in the same direction for any transmission. Current governing allowable RFI emissions, sealing the box
flows through line-termination resistors and returns becomes important. Moreover, sealed enclosures are
to the transmitter as a steady dc current on the more suitable for the extremely hostile environments
transmission-line shield. The net effect is near-zero encountered in most military and some industrial
current through the complete shielded twisted pair, applications.
resulting in very low levels of EM!. Getting down to details
The major advantages of current-mode transmis-
sion are very low system power levels: typical dis- Figure 2 shows a complete schematic of the con-
sipation is 25 mW when the system is active and 100 troller. The system interfaces with an 8-bit
/lW on standby, for a transmitter operating at a 1- microprocessor by tying together the Do-D7 inputs
Mbit/s data rate over a transmission line of 1000 feet of the 82C55As to form an 8-bit bus. These devices
or longer. Moreover, using multiple twisted pairs must be programmed individually to their mode 1,
within the same shield is possible, since there are strobed I/O, configuration. A double-buffered inter-
no high crosstalk levels like those common to rupt-driven interface can then be achieved.
differential-voltage switching systems. Port A of each 82C55A is programmed as an output
As for CMOS, besides all the obvious advantages, port to supply data to the HD-6408 for subsequent

82C55AT •
0, «
0, S
~1 33pF

g;
0.
T" SOl O"~ 33pF
!2?- ~
RD 0

~1
Ao
1.3.'.8,7~D
,13.'.,15
A,
EE

+5V
U"
800
'vw 8Z0

HD-6408

82C55A T SDO
UDI ..
0, «
0, "
CDS v••
:~: 7
0, if GND
UJ'"
..JI-
g: 1 (.)2

j,
D. ~g:
~I
"'UJ
<C'"

\'1B 15
cs Q.

::: 1.
u, GNO
INTR;r~
I'ST8.
INTA,,~
if~c. U,andU,-70C1.
U,-70CC00
lACK
MR ••• OBF .•.
GND
lho-701<XM

2. The complete schemetlc olthe network controller shows a data-communications system designed around
tha HD-6406 Manchester encoder-decoder chip (U,,) and a pair 01 82C55A programmable peripheral Interface
devices (U, and U.). The system operates as both trensmltter and receiver, and because the two tunctlons
are Independent, It can be conllgurad lor either hall- or lull-duplex operation.
transmission. A pair of 74C165s (8-bit parallel- The mw signal controls the Encoder Enable (EE)
loading, serial-output shift registers) convert 16-bit input on the 6408. This signal prompts the 6408 to
transmission data from parallel into serial form. Bits start transmission. Once transmission begins, the
3, 6, and 7 of port C provide the handshaking signals 6408 responds with a Send Data (SD) signal, which
for port A data. forms an acknowledgment (ACK) to Ce.The response
When data is written by the microprocessor to port resets OBF and prompts the 82C55A to issue a
A, bit 7 of port C (C,) goes low, producing an Output Transmit Interrupt signal from line Ca to the
Buffer Full (U'BF) signal. Although this signal ap- processor's CPU. This signal informs the CPU that
pears at the output of each 82C55A wh('n data is the transmitter is ready to receive another word for
written to them, only the mw
signal from the device transmission. A double-buffered transmitter results
containing the most significant byte of data is used that permits continuous data transmissions without
-in this case, U2• The reason is that all 16 bits of interword gaps or idle time.
transmitted data must be available to the network At a 1-Mbyte/s data rate, the CPU has about 16
controller before transmission starts. When data is liS in which to send a new data word without having
written to the 82C55As, the least significant byte is any idle time. This is a relatively short response time
written first, followed by the most significant byte. for an 8-bit processor. An upgraded version of the
controller would use a faster 16-bit microprocessor
such as an Intel 8086 or a Harris CMOS 80C86. Under
this condition, the Do-D, inputs must be connected
as a 16-bit bus (Do- D1S) and simultaneous chip-
selection signals (CSo-CSIl must be applied to both
82C55As.
The system can be upgraded further with a DMA
controller, which lets the CPU spend more time on
other processing tasks. But this addition is necessary
only for high data-rate systems-lower data-rate
systems operate satisfactorily without DMA or
interrupt-driven schemes. In slower controllers, the
interrupt outputs (Co and Ca) are unused, and the
CPU can poll the status word of port C by reading
the port.
The receiver operates much as does the transmit-
ter and is likewise double-buffered. Since the re-
ceiver and transmitter are independent, the con-
troller can be set up for either half- or full-duplex
operation. The receiver circuitry ignores spurious
data on the bus and begins its response sequence only
on receipt of a valid sync character, followed by two
valid Manchester II bits. This procedure is im-
plemented with circuitry internal to the 6408.
After a validation sequence has occurred, the 6408
3. Oscilloscope photos of the network controller's receiver
output show waveforms taken at data rates ofl Mbll/s (a) generates a Take Data (TD) signal, enabling the
and 2.5 Mblts/s (b). Although distortion Is slightly greater at 74C164-based shift register to accept the Serial Data
the higher data rate,the difference Is virtually Inslgnilicant. Output (SDO) of the 6408. The trailing edge of TD
indicates that all 16 data bits have been transferred
to the shift register and also serves to generate a
strobe signal (STB) for the 82C55As. STIl, C2 causes
the devices to load the received data into their port
B inputs. Then the 82C55A responds with an Input
Buffer Full (IBF) signal, which resets the'STB line.
The shift register is available immediately to receive
the next 16-bit word. Since there is always a
minimum time of four bit periods between data
words-because of the parity bit and sync character
-the design guarantees successful reception of so-
called back-to-back data words.
 STB also causes the 82C55A to generate a Receive 99.99% of all possible errors. Thus, at a system level,
Interrupt on the Co output. As in the transmitter, undetected errors occur five or six orders of
this interrupt can be either used directly or polled magnitude less frequently than detected errors.
under software control. Two types of synchronization characters can be
The 6408 indicates acceptance of an error-free supplied by the 6408 to differentiate between com-
word by generating a Valid Word (VW) signal. VW mand and data words. The Command/Data Sync
is latched and presented to a spare input at C5, and (CDS) output reflects the reception of a command
the microprocessor reads the bit to validate correct or data word based on the sync character. The signal
data. With a slight hardware modification, VW can is latched and presented to the spare input at C. of
be used to enable"STl3, thereby reducing the required VI and can be read under software control. Since the
software and its overhead. use of CDS depends on the application, it is employed
The 6408's error-detection circuitry checks every at the designer's option.
data bit for correct Manchester II encoding and also The 6408's transmitter section has two control
verifies correct parity. As a result of its composite signal inputs which connect to the spare port C
error-detection algorithm, the chip detects 100% of outputs on V 2. Sync Select (SS) determines whether
three or fewer sampling errors in any data word. a command or data sync character is to be
When more than three errors occur, the 6408 will transmitted, and Output Inhibit (Of) is a low-true
correctly detect-on a statistical basis-better than signal used to put the mm
and'BZO transmit-data

MIL-STD-1553defines a time- ments of 1553.At the same time,

division- multiplexed data bus for the CMOSdeviceis flexibleenough
use in military aircraft. The bus to implement other signaling pro-
carries bipolar signals and uses a tocols.The 16data bits in both the
single twisted-pair shielded cable. 1553's command and data words
Data going out on the bus is en- are defined by the user and can be
coded in the Manchester II format. generated by the hardware-soft-
Under this system, no dc signal ware combination in the network
components appear on the bus. controller. For example, expand-
Thus transformer coupling is ing the system to any number of
permitted, resulting in excellent terminals is possible by redefining
isolation between data-handling the meaning of bit assignments
systems and their environment. within command words. Addi-
The signaling format of 1553is tionally, error codescan be deleted
specified assuming that 32 or or expanded. By substituting the
fewer terminals are managed by HD-15531Manchester encoder-de-
a central control unit that uses coder for the HD·6408,additional
command words. Provision is user-defined features can be in-
made for dynamic reassignment of corporated, such as expanding the
the control unit using the token- word length of the bus to 28 data
passing technique. Each word bits, if desired.
transmitted is preceded by a
synchronizing pulse and followed
by a parity bit, resulting in a total
word time of 20 /,s. The character
and word formats of the MIL-STD
1553bus are shown in Figs. A and
q..--j
Command word (from controller 10 terminal)
1'1 I 1'1
B, respectively.
The HD-6408Manchester encod-
er-decoder, which is the key com-
~:~~1----1-- --- Sync I
5
Terminal
address RIT
I
5
ISubaddressil
mode
5
oala word
count
I I
Parity

I B,t.1 Bit I B,t I Data word (either direction)

ponent of the network controller, n;riodlPeri~riod1 d=1 16
is designed to meet the require-
t
LogiC 1 dala
Sync I Oala word

q..--jI
Status word (from terminal to controller)

LogicOdala I- Sync
5
Terminal
address
1,1
If I
Message error
9
Code for failure
modes /
1,1,1
I I I
Parity

Terminal flag
outputs in their inactive states (high). These signals tains two twisted pairs inside a common shield. The
are also application-dependent, and are therefore shield has both braided and foil conductors to ensure
optional. 100% coverage.
Evaluating controller performance
Tying the ends of two twisted pairs together at
the end of a 500-ft length of cable produces an
To check the controller's design, breadboards can effective cable length of 1000 ft. This configuration
be connected using Belden Corp. 9855 Twinaxial is useful for observing the effects of possible
cable. This inexpensive high-performance cable con- crosstalk between adjacent pairs inside a common

The two most common methods A logic 1 is produced by line 4>, -

for transmitting digital informa- conducting a certain current. This
tion over wire are the RS-232 c.urrent travels down the trans-
voltage mode and differential- mission line, through a 50-0
voltage switching. A long-time in- terminating resistor R.r (right
dustry standard, RS-232can take half), and returns through the
the abuse that results when many shield to the common point of the
different types of equipment are transmitter's power supply. A
connected on its lines. But RS-282 logic 0 results when the current is
is limited to systems working at prevented from flowing in 4>"and
low speed over short lines. flows in 4>,. The shield carries the
Differential-voltage techniques . same dc current constantly, since
overcome many of the limitations lines 4>, and 4>, always conduct
of RS-282, providing high-speed, alternately.
long-line data links that have a Small variations in transmis-
high degree of immunity to ex- sion-linecurrent can occur if there
ternally generated noise sources. is overlap between the turn-on and
Both RS-282 and differential- turn-off times of 4>, and 4>,. How-
ever, the complementary outputs
of the HD-6408 are designed for
near-zero overlap.
With sign·alswings typically 20
times smaller than in differential-
voltage systems, and with its non-
saturating current-switching
transmitter producing smooth
ramps without overshoot or ring-
ing, current-mode transmission is
far superior to differential voltage
systems in limiting conducted and
radiated RFI. The three types of
voltage switching have three externally generated noise that af-
drawbacks: they are high power fect digital signal-line transmis-
consumers, generate crosstalk sion are: magnetic and capacitive
between adjacent lines, and pro- pickup from nearby electrical con-
duce noise in the form of con- ductors, magnetic and capacitive
ducted and radiated RFI. The re- crosstalk between transmission
latively unknown technique called lines sharing a common shield,
current-mode transmission can and ground-line noise between
eliminate these drawbacks and transmitter and receiver. Current-
works well over long lines. mode transmission combats the
A current-mode transmitter first two types of noise as well as
(left half) alternately applies cur- or better than the other systems.
rent to each of two conductors (4),, The ground-noise problem is
4>.) in a twisted pair. The total usually eliminated by avoiding
current is constant and always ground loops as dictated by stan-
flows in the same direction. dard design practices.
shield. Current-mode transmission systems exhibit rate, some pulse distortion results because of inade-
very low levels of crosstalk, thereby permitting quate gain of the simple low-power receiver used.
multiple twisted-pairs within a single shield. Figure 3 shows oscilliscope photos taken at the
Voltage-mode transmission schemes, on the other receiver's outputs-note the slightly higher distor-
hand, may require separately shielded cables for long tion in Fig. 3b compared with Fig. 3a. The problem
runs, resulting in much higher cable costs than in can be solved by substituting premium transistors
current-mode systems. in place of the 2N4124s ordinarily used. An
In an actual system, the additional twisted pair alternative solution to that is to replace the discrete
may be used as a secondary bus for higher system line receiver with an industry-standard 75107 line
throughput or as a redundant bus to increase system receiver.
reliability. Another option is to provide a full-duplex In a worst-case design, which accounts for tem-
point-to-point data link. perature and voltage variations, the CMOS shift
A standard five-pin DIN shielded audio connector registers may be too slow at a 2.5-Mbit/s data rate.
is an ideal low-cost method of connecting the bread- However, they can be replaced with fast new devices
boards to the 9855 cable. Its shielded shell provides offered by several manufacturers without com-
adequate integrity for all but the most stringent promising the low-power aspects of the design.
requirements. Because of the design's low power dissipation, the
A complete 1000-ft cable running at a 1-Mbit/s components can be incorporated into a single module
data rate serves as a reliable data link and when using leadless chip carriers, with a ceramic substrate
tested produced no detectable transmission errors or providing the connections between components.
crosstalk. The typical power consumption is 150 mW. Another option is to house the components in a chip-
By inserting a 30-MHz crystal at the 82C84A's input, and-wire hybrid, which results in even greater
the data rate can be increased to 2.5 Mbits/s. At this packaging density. 0
 Take a total-system approach,
with advanced CMOS memories
CMOS memories are undergoing continual refinement, and new devices
are increasingly competitive with those in other technologies. For
these devices, though, specs such as standby and operating current
are system parameters, not merely device descriptors.

Walter J Nlewlerskl and Russell M Pate,

Harris Semiconductor

Memory manufacturers have improved CMOS so much

that it now competes favorably with NMOS in speed
while retaining its edge in power consumption. New
CMOS devices, though, present design considerations «.s 50
somewhat different from those of older CMOS memo- .2 40
ries; you must take a systems approach to designing
with them.
CMOS-memory choices have definitely expanded.
CMOS RAMs, for example, now store as much as 64k ----- ---- -
bits and achieve access time as short as 55 nsec, I i\
--- J_
operating current of 7 mAIM Hz and standby current of
10 fLA.
,
I
_.1. __

22.43
I~
4 4.5 5~
Additionally, CMOS fuse-link PROMs hold 16k bits
and spec access time of 200 nsec, 10-mAlMHz opera- V"IV) t t Vcc

ting-current consumption and 100-fLAstandby-current TTL VOH CMOS VOH

consumption. The short access time, along with an lee
requirement lower than for NMOS or bipolar devices, Fig 1~MOS-memory operating current varias widely
gives CMOS the best PROM speed-power product. over device operating-voltage range. Standby current is at a
CMOS EPROMs also compete well with their NMOS minimum when V" is at either power-supply rail. Note the
counterparts; devices store as much as 64k, and access difference in operating current associated with the V""
(highest output-voltage level) for TTL and CMOS.
time reaches 300 nsec with lee of 25 mAlMHz vs 100
mA for NMOS. At a 350-nsec access time, CMOS
improves NMOS operating current by 4:1 and standby CMOS static RAMs even preceded NMOS units by
current by 250:1. Finally, in EEPROMs, you'll find approximately 6 months.
1kx8 block-erasable CMOS devices. However, NMOS, What about price? Lower density (4k) CMOS RAMs
because of higher densities and byte-erase capability, are competitive with NMOS devices, but other CMOS
still holds a slight edge here, although future CMOS memory types still sell at a premium. However,
units will also offer these features. because NMOS is a mature process in all device types
These performance levels exemplify a trend in MOS and CMOS isn't yet fully mature in all areas, the price
memories: the narrowing time span between the gap should decrease.
appearance of an NMOS device and its CMOS counter- CMOS memories provide another plus: You have a
part. For instance, CMOS EEPROMs followed their choice unavailable in most other technologies--
NMOS equivalents after less than 1 yr. Indeed, 16k synchronous or asynchronous operation. Roughly equal
in price, both types have design advantages.
Synchronous memories provide on-chip address
This article is based on a paper presented at latches; thus, the address on the bus must be valid for
Midcon/B1. only a short time, during which it's latched with the
Chip Enable signal. This feature allows minimum-
Reprinted from EDN, April 1982; © 1982 Cahners Publishing Co.

8-44
CMOS memories compete favorably
with NMOS In speed

parts-count interfaces for systems with multiplexed polarity when a stable bus address is present (Refs 1, 2
address/data buses. Synchronous devices also spec and 3). This signal causes the selected memories to
lower average operating power. latch the address, freeing up the system bus.
Asynchronous memories, on the other hand, achieve Despite CMOS memories' increasing speed and other
shorter cycle times, even at the same access time as a advantages, though, designers generally favor them
synchronous unit. Why? Synchronous units require a primarily for their low power consumption in both
minimum TEHEL (enable-pulse HIGH time) to pre- Operating and Standby mode. The operating current
charge the matrix-column lines that speed up transi- arises mainly when device-enable inputs get switched;
tions of the column lines to the proper logic states. additional current arises when input circuits enter their
Previously, 4k CMOS RAMs, like most memories, linear operating regions. The low-Z path that occurs
were strictly asynchronous-a feature that gave rise to when an input voltage crosses through the switching-
availability problems. A circuit that accepts both types, threshold region increases power-supply current (Icc),
however, provides the flexibility of dealing with more which varies directly with the enable and switching
device suppliers, especially for 4k and 16k RAMs. The frequencies.
trick to designing such circuits is to devise a Chip Input-switching frequency also affects another major
Enable signal that undergoes a transition of the proper contributor to CMOS operating power-the charging of
output loads. Increased load capacitance increases the
current needed to charge and discharge such a load.
Thus, Icc increases with output-drive requirements.
CMOS memories consume microwatts in Standby
mode with input levels stable at Vcc or ground; the
corresponding current consists of surface, junction and
channel-leakage contributions. When using battery-
backed CMOS RAMs, you can minimize standby
current by idling the devices when not in use and by
deselecting all inputs, which you should hold at either
power-supply rail.
Given this state of the art in CMOS memories, some
designer reorientation might be required to use the
newest devices. Users sometimes dispute standby-
UPPER· current specs, for example, because they observe
ADDRESS
BUS above-spec values in memory devices that are disabled
but that remain connected to active address and data
buses. This phenomenon arises because of CMOS
Icc-vs- V1N transfer characteristics (Fig 1), and it
reinforces the need to examine device operation within
DIS EN
CD40116 the context of the system.
A, Note that the current for a CMOS input increases
A.
AI significantly near the threshold or switching voltage.
At that point, both enhancement-mode input transis-
tors that implement the input's inverter are ON to some
degree (typically 1.3 to 2.2V at room temperature),
introducing a dc path between the power-supply rails.
When this transient current is time-averaged (account-
MULTIPLEXED ing for the rise and fall times of bus transitions) and
ADDRESS/DATA
BUS then multiplied by the number of disabled device inputs
connected to an active bus, the disabled device's
CD40118 CONTROl·SIGNAL TRUTH TABLE
current can increase by a factor of 60 to 100.
ENABLE DISABLE FUNCTION
X 0 CMOS TO TTL You can observe a similar effect when driving CMOS
1 0 TTL TO CMOS inputs with devices that have valid logic levels within
o 1 HIGH IMPEDANCE
or near threshold regions. To maintain minimum
standby current, you might need pull-up resistors to
Fig 2-81d1~lonll !lvil Ihlftlra (C040116s) Interfece
stenderd 5V;:10% CMOS memory end perlpherel chIps to
keep V OH from these devices above the thresholds.
the NSCBOO, whIch requires 3 to 11V power. You might also need pull-up or -down resistors on
some CMOS RAMs in battery-backed applications to
EDN APRIL 28, 1982
 Yo

I'""'''''~
""
AI
Ai DECODER/
G, DRIVER
ALE G2 (HM-6440)
Go
10/fA
74C02 G
G y, E i5E AD E i5E AD
A" A" W WR A"
A. A. A, 2k xB PROM
2kx8RAM
A. A. IHM·65161 A. IHM.66161

NOTE:
ALL INPUTS WITH DRIVERS THAT COULD BECOME
HIGH IMPEDANCE OR HAVE NO DRIVING INPUT A7 87
MUST HAVE PULL·UP/DOWN RESISTORS BIDIRECTIONAL
BUS
TRANSCEIVER ~
(B2CB6)
T EN ~

FIg3-To decode the Io_r 16k byte. of memory in FIg 2's multiplexed output into 2k-byte blocks suited tor CMOS RAMs, this
circuit uses en HM-6440 decoder driver. For data-bus interfacing, it incorporates an 82C86 bus transceiver.

keep inputs from floating through and around the away from Vee and ground toward operating levels,
threshold region when power is lost to other system then note the Ice associated with the output-voltage
devices. Input voltages in reduced-power-supply appli- levels of bipolar and CMOSbus drivers. For example, a
cations should be no more than 0.1V from Vce or 16k-byte CMOS static-RAM array running at 5V and
ground. Otherwise, the battery-discharge rate increas- 25°C and cycling at 1 MHz dissipates 1.35W with
es considerably because of the higher lee caused by 74LS365 LSTTL bus drivers but only 475 mW with a
floating inputs. But these resistors can affect the CMOS bus driver.
transition times of driver outputs: In Operating mode, Bus-interface considerations also help answer per-
pull-down resistors might slow the rise time of TTL haps the most often asked question in memory-system
drivers by as much as 20%, and puIl-up resistors design: Can memory be accessed rapidly enough to be
increase their fall times by the same fraction. speed compatible with the •.•. P-system operating fre-
CMOS-memory manufacturers have removed some of quency? Many designers often overlook the effect of
these design obstacles by adding two MOSFETs to bus-interface-device speed-bus-buffer delays can re-
standard 2-transistor input-inverter circuits. Such strict memory speed. But a tradeoff arises: Increasing
gated or disabled-input configurations prohibit the bus-driver propagation delay by just 1 nsec, for
circuit's inverter from reacting to input transitions or example, might call for buying faster, more expensive
floating inputs while the device is disabled. This feature memory devices.
simplifies battery-backup designs, reduces standby and Other system conditions can affect CMOS-memory
operating current and cuts system parts count by operation. For instance, CMOS parameters generally
eliminating the need for pull-up resistors. improve as ambient temperature dpcreases--output-
When interfacing to CMOS memories not equipped drive capability increases, providing greater current to
with this input gating, you might overwhelm the charge and discharge load capacitances and thus
operating power of bus drivers with the memory increasing device speed. Standby power dissipation also
array's operating current. Avoid this problem by using decreases as the temperature drops.
CMOS bus drivers, which can reduce array power Voltage levels of supplies and inputs also affect device
consumption as much as 70% compared with LSTTL performance. Raising the supply level increases device
buffers, mainly because of the differences in permissi- speed and power consumption; input levels above spec
ble output-voltage ranges between CMOS and LSTTL, can greatly increase current and even damage devices.
Fig 1 clearly illustrates this advantage. Note the Device ac characteristics depend greatly on the
memories' higher power consumption as V1N moves capacitive loading arising from interconnect and input
EDN APRIL 28, 1982
Ice increases significantly
near input-threshold values

capacitances of devices attached to the memory out- number of charge cycles. (However, it has a faster
puts. Loads greater than spec can increase memory discharge rate and doesn't suit applications requiring
propagation delay. data retention for extended periods-a IF capacitor
Other capacitive effects become more important in holds a lkx8 synchronous-RAM array for 2 to 3 hrs.)
the newer high-speed CMOS memories. For instance, If you take the aforementioned CMOS-memory
the large current transients associated with fast design factors into account and your battery-backed
rise/fall times call for installing a decoupling capacitor array is still losing data, use a checklist to troubleshoot
(0.01 ~F min) between the power-supply rails of every most cases:
device in CMOSmemory arrays. Youshould also install • Is Vee dropping to less than 2V? If so, the
a large electrolytic capacitor where power enters the problem probably arises during transitions into or
array. This provision proves especially important in out of Backup mode.
large arrays of synchronous devices, where the largest • Is the Write (W) line being pulled up with the
transients occur on the Vee and ground lines during Chip Enable (E) line as an added precaution?
chip-enable transitions. • Are Vee, E and W transitions glitch free, and do
they ramp up and down smoothly?
CMOS RAMs In data-retention systems • Are all other inputs held at Vee or ground during
When using CMOS RAMs in battery-power or the backup period? Floating inputs increase Ice
battery-backup applications, be aware of several addi- and shorten battery life.
tional design precautions. For instance, input and • If you drive RAM inputs with LS drivers, are
output voltages can create prohlems. Thus, be sure to their outputs pulled up? They needn't be in most
establish safe power-up and -down sequences because cases, because LS outputs tend to go to a
junction-isolated CMOS devices' inputs contain a para- low-Z-to-ground state when Vee fails. (Some
sitic SCR that remains inactive during nonnal opera- 3-state Schottky drivers don't exhibit this charac-
tion but becomes active when input or output voltages teristic.)
exceed spec'd values. To avoid problems, raise and • Are CMOS bus drivers being powered from the
lower supplies in an order that prevents inputs and CMOS Vee supply and not the system supply?
outputs from existing at potentials higher than Vee or This should be the case, and you should hold
lower than ground. driver inputs HIGH or LOW with resistors. The
Note also that you don't always need batteries in outputs of CMOS drivers, however, should never
CMOS data-retention systems: Capacitor manufactur- be pulled up with resistors.
ers now supply high-value, low-voltage units that can • For synchronous memories, is E held HIGH for at
substitute for batteries. For instance, a IF, 5V least one TEHEL period after Vee has risen to
capacitor measuring 44 mm in diameter and 18.5 mm nonnal operating level?
high requires less maintenance than a battery, exhibits The following design examples, besides showing how
a longer useful lifetime and pennits an unlimited to account for such system considerations, illustrate

RAM (HM-6512) RAM (HM-6512)

ADR ADR
es MSEL STR es MSEL STR

XTe

MEMSEL

Fig ~nt.rf.clng CMOS memory to CMOS ",Pa such as the 12-bit HM-6100 proves simple. With this all-CMOS design, you can
easily create a small data-acquisition system that accommodates 10- or 12-bit AID or D/A transfers in one byte.
 G,
A,

G, D6~~~~RJ
IHM·64401

how to implement all-CMOS ILC-memory systems and impedance state, achieved with the ILP'SBus Acknowl-
how to adapt CMOS memories to NMOS-processor edge (BACK) line. When the ILPgives up control of the
systems. bus to another processor or peripheral, these lines have
The first example uses an NSC800 8-bit CMOS ILP. a high impedance. Finally, the multiplexed low-address/
While most CMOS devices require 5V:t 10%, this ILP data bus is controlled by the ILP'SRD signal, which gets
and a family of support devices accommodate a 3 to 11V inverted and applied to that CD40116's Disable input.
operating range. You might, however, need some You can translate remaining control signals (such as
CMOS devices of the standard 5V:t10% type, and using WAIT, INTA or BACK) with additional CD40116s or
a system supply voltage outside this range for both with 74C90X translators as shown.
types can present interfacing problems. To decode the lower 16k bytes of memory provided in
To implement such interfacing, the system must be the multiplexed output into 2k-byte blocks, use the
able to shift voltage levels quickly; for this task, the circuit shown in Fig 3. Its HD-6440 decoder/driver,
circuit shown in Fig 2 uses the CD40116 octal with three device enables, allows the circuit to decode
bidirectional level shifter. This device exhibits a addresses directly. You need only a NOR gate to
15-nsec propagation delay when shifting from 12 to 5V combine ALE (Address Latch Enable) and IO/M
and 30 nsec when going from 5 to 12V. (Input-Output/Memory). The 6440 also provides eight
Fig 2's 10V/5V translation interface uses two 2k-block enables for the CMOS memories shown.
CD40116 control signals to determine the direction of Moreover, because the circuit uses synchronous memo-
data flow and voltage translation. CMOS inputs AI-8 can ry devices with on-chip address latches, it needs no
withstand levels as high as VDD (10V in this case), while external latches.
inputs B1.s are TTL compatible only. The NSC800 controls memory operation with RD and
The control signals are generated separately (via WR lines, which connect to the all-output enable (OE)
three level shifters) for address- and data-bus and controls and the Write line on each RAM. The
control-line buffering. Of these, the control-line inter- decoder/driver generates each RAM's enable (E) sig-
face is the simplest: Its level shifter is constantly nal. If you need additional data-bus buffering, or if you
enabled for CMOSITTL conversion. And because these choose not to use a CD40116 for voltage translation,
NSC800 control signals and upper addresses are consider the 82C86 CMOS bidirectional bus trans-
unidirectional outputs, controlling them involves only a ceiver for the data-bus interface. This device remains
shift between CMOSITTL conversion and the high- enabled unless the ILP gives up bus control (BACK
EDN APRIL 28, 1982
Gated-input devices don't
react to floating inputs

controls the bus transceiver's enable); RD determines HM-6561 synchronous RAMs. It needs two such 256x4
data direction. devices to fill the 80C48's 256-byte data memory.
You can apply this CMOS-based circuit to the NMOS The RAMs have two select pins (S1.2)and one enable
8085. Using CMOS memories in an NMOS system can (E); this latter line latches the address bits onto the
improve reliability and system operation by decreasing chip and is active LOW. Address latching occurs on E's
power requirements and providing higher noise immu- HIGH-to-LOW transition. The !J.C's ALE (Address
nity than NMOS devices. Furthermore, by using CMOS Latch Enable) connects to the E line, and this signal
bus drivers with CMOS memories, you can further has the proper polarity and its HIGH-to-LOW transi-
reduce circuit operating-power requirements. tion occurs when addresses are stable on the processor
The second all-CMOS microsystem example uses the bus. The ALE signal serves for the E function on all
HM-6100, which suits applications such as remote data devices in the memory array. Chip Select lines (SI.2)
acquisition. Fig 4 shows a minimum memory configura- select the appropriate RAM; S, is derived from the
tion for this !J.P. A 1kx12 CMOS ROM (an HM-6322) 80C48's RD and WR signals while the S2pins get tied to
holds the main program and also provides decoding for ground. The two memory signals occur whenever a
the system's 64 x 12 CMOS RAMs. The ROM's XS data-memory read or write is in progress; you need no
(External Select) output places the RAM in the further decoding because these signals are active only
memory map as determined by its decoding logic, which during data-memory transfers.
you program. This output enables system RAM For program-memory expansion, this circuit uses an
whenever the RAM area gets addressed. Both ROM HM-6616 2kx8 CMOS PROM; this high-density device
and RAM devices provide on-chip address latches and eliminates extensive decoding, reducing parts count for
latch this data on the falling edge of the LXMAR (Latch both the decoding scheme and the memory devices.
External Memory Address Register) signal from the Individual output enables from the HD-6440 decoder
!J.P.To add memory to the system, you can adapt nearly are available for each PROM along with an EEPROM
any standard device. enable. If you use no other devices for program
The final design example, which uses the CMOS memory, you can eliminate the decoder; in that case use
80C48 single-chip !J.C, destroys the myth that single- the processor's PSEN signal for enabling PROM
chip systems should have as few devices as possible for because it's active only for external program-memory
lowest power consumption-the capabilities of new fetches. EOII
CMOS devices can compensate for this factor in system
expansion. This circuit (Fig 5) expands both data and
program memory via CMOS devices. This expansion References
concept, though, is applicable to systems with CMOS or
1. Niewierski. W J and Patl:, R M, "Total CMOS
NMOS versions of the 8048 or other family members memory system design," paper presented at Midcon/81.
with few modifications. When using an NMOS 8048 2. Patstone, W, "Trio of 2kx8 CMOS RAMs poses
with VOH spec'd at 2.4V, you might need to add a few design tradeoffs." EDN, November 20.1980, pgs 45-49.
pull-up resistors in the worst case. Timing, though, 3. Hochstedler, C M, "Synchronous static CMOS RAMs
presents no problems. increase system performance," EDN, April 5, 1979, pgs
93-94.
Within the CMOS !J.C, data and program memory
reside in separate areas, each with its own control
signals. For data-memory expansion, this design uses
 Lee implementation procedures
enhance a valuable technology
Meeting tight military and commercial packaging requirements, standard
leadless chip carriers offer weight, space and density benefits.
To take advantage of these fortes, though, you must
pay close attention to assembly techniques.

Despite their much-touted benefits-primarily in- SUBSTRATE TeE·

MATERIAL (IN.lINrCxl0-6)
creased packaging density, higher reliability and lower
ALLOY 42 5.3 42% Ni. 58% Fe
cost compared with other types of IC packages- 96% ALUMINA 6.3 INDUSTRY STANDARD
leadless chip carriers (LCCs) haven't made the expect- 94% ALUMINA 6.' INDUSTRY STANDARD
92% ALUMINA 6.' INDUSTRY STANDARD
ed inroads with system designers. Why? Largely COPPER CLAD INVAR 6.• INDUSTRY STANDARD
because published information has focused on design 99.5% BeO 6.' EXPENSIVE
LOW CARBON STEEL 12.0 PORCELAINIZED
concepts and techniques rather than on practical POLYIMIDE G30 14.3 INDUSTRY STANDARD
implementation procedures .. Consequently, this article EPOXY/GLASS G10 15.8 INDUSTRY STANDARD
TRIAZINE G40 16.0 INDUSTRY STANDARD
describes LCC mounting, soldering, heating and re- CDA 101 COPPER 17.3 VERY HIGH TCE

working guidelines to help you overcome the con- 6061 ALUMINUM 23.6 VERY HIGH TCE

straints posed by the need for compact packaging (see

box, "LCCs shine in high-density packaging").

Match, don't mix, mating materials

After having chosen LCC-packaged ICs for your
application (EDN, May 27, 1981, pg 49), you must
determine the means of attaching these packages to a
pc board or substrate material. To accomplish this
chore, evaluate LCC mounting materials (table).
Selecting a board or substrate material involves
matching its linear thermal coefficient of expansion
(TCE) to the LCC's. When the TCEs don't match,
thermostatic deflection (twisting or warping) results
during the wide temperature changes characteristic of
military applications. During twisting, for example,
torque effects bear on the solder joints, causing
electrical and mechanical connection fatigue.
This thermal problem gets worse with larger LCC
pinouts because of increased package size and stress
levels. Accordingly, follow a general rule when select-
ing a substrate material: The larger the TCE difference
between LCC and substrate materials, the smaller the
substrate's surface area must be. Alumina substrates,
Fig 1-Achlevlng significant space and weight savings compared
for instance, work best when they don't exceed 24 in.2 with the equivalent DIP configuration, this multilayer 92%-alumina
Ideally, therefore, choose the same material for both ceramic substrate holds 92%-alumina Lees. The materials matching
the substrate and the LCC: a 92%-alumina ceramic prevents parts from undergoing thermostatic deflections (twisting or
warping) during the temperature changes typical of military applica-
LCC attached to a 92%-alumina substrate (Fig 1), for tions. Note that the Lees, carrying 256k static-RAM-module proto-
example. types from Harris, mount on both sides of the substrate.

EDN JUNE 23, 1982 Reprinted from EDN, June 1982; © 1982 Cahners Publishing Co.

8-51
Military circuits benefit from
LCC size, weight, density assets

In picking pc-board materials, military specifications 28809 for printed-wiring assemblies, mandates thermal
playa dominant role. One MIL spec, MIL-STD-883B, shocks in accordance with MIL-STD-202, Test Methods
Method 5004.4, Class B, for instance, outlines pertinent for Electronics and Electronic Component Parts,
test and qualification methods. It requires Method Method 107. This method's applicable worst-case test
1010.2, Condition C thermal cycling (ie, over -64 to specifies 100 temperature cycles, ranging over -65 to
+ 150·C with 10-min durations at each extreme) for at + 150·C with 5-min maximum intermediate hold periods
least 10 cycles. This standard covers microelectronic at 25·C, and with soak times at temperature extremes
devices, such as those with an LCC as a component, but determined by the assembly's weight. (In most cases,
doesn't apply to printed-wiring-board assemblies. soak times run 0.5 or 1 hr.)
Another military spec, MIL-P-55110C for printed- Not everyone agrees completely with these tempera-
wiring boards, calls for 100 thermal-shock cycles, ture-cycle requirements. Martin Marietta (Orlando,
spanning -65 to + 125·C for expoxy boards and -65 to FL), for instance, has been mounting LCCs on
+204·C for polyimide boards. Yet another, MIL-P- printed-wiring boards for more than 6 yrs. And based

Leadless-chip-carrier (LCC) prod- cient in meeting strict space-vs- When similarly contrasted with
uct designs appear to be becom- function requirements, chip-and- DIPs, LCCs offer much smaller
ing the industry-preferred pack- wire hybrids have become size and weight. For example, an
age for high-density, high-pinout popular. Extremely compact, 18-pin DIP occupies 0.276 in.'; an
ICs. In fact, they should supplant these hybrids provide multiple 18-pin LCC, only 0.100 in.' The
flatpacks and hybrids in the short functions within a small area. space-saving ratio with LCCs
term and surpass DIPs in the long Typically, though, they cost more therefore approaches 3:1. like-
term. They meet the need for very than DIPs and pc boards because wise, comparing weights, an
small, dense and lightweight cir- of high assembly and test costs, 18-pin DIP weighs 2.48g; an
cuit packaging, especially in mili- low rework yields and the expen- 18-pin LCC, 0.32g. The LCC thus
tary applications, which stress sive manufacturing equipment re- proves 7.75 times lighter.
highly reliable electrical and me- quired. In military applications, LCCs' electrical benefits are
chanical performance. however, small size and light- outstanding as well. Their small
In the past, DIPs have proved weight design generally take prior- sizes and leads on four edges
sufficient for these applications. ity over cost. permit the use of very short
But as military-circuit specifica- Manufacturers commonly as- conductor lengths from the exter-
tions continue to demand smaller semble hybrids from dice. This nal leads to the internal chip-
size and less weight for more procedure, however, results in cavity bond pads. This layout
complex electrical functions, an- limited device performance be- results in lower parasitic resis-
other packaging method-the flat- cause of IC-manufacturing con- tances, capacitances and induc-
pack-has evolved. straints on wafer-level testing. tances than those demonstrated
Flatpacks have proved a worthy Less-than-stringent testing thus by corresponding DIPs.
alternative to DIPs for reducing passes less-than-perfect devices What's more, you can use clock
board space. However, they also for hybrid assembly. Neverthe- rates as high as 4 GHz with LCCs;
exhibit shortcomings. For one, less, subsequent hybrid-level test- DIPs' parasitic deficiencies restrict
package cost is high because of ing assures quality products, al- their speed to about 500 MHz.
extensive gold plating. Moreover, though low device yields prove And besides their small size-
long lead lengths and narrow expensive. often only slightly larger than the
spacings mandate special han- An LCC-packaged device at- installed die-and lack of leads to
dling carriers. Further, during sol- tached to a board or substrate break or bend, LCCs withstand
dering to pc boards, the long lead material achieves higher perform- the rigors of MIL-STD-883B test-
lengths allow package vibration, ance at a lower price than a hybrid ing at the package level, including
jeopardizing lead connection and device. Furthermore, LCC pack- Groups A, B, C and D.
solder-joint reliability. ages permit full parametric testing To ensure industry-wide accept-
Because ICs packaged in DIPs plus burn-in, yielding higher relia- ance, the Joint Electron Device
and flatpacks have proved defi- bility units. Engineering Council (JEDEC) and
on its experience and test data, it concludes that 100 metallization allows the solder, when heated to reflow
temperature cycles are excessive. The packaging temperature, to wet both the base contacts and the
industry, on the other hand, favors increased cycling grooved region on the LCC package's sides.
but over a narrower temperature range-300 cycles at The solder deposit's outer surface thus fonns a fillet
-55 to + 125°C. that extends over the metallization pad on the board or
substrate surface (Fig 2b). This extension aids in
Take care with pc-trace layouts strengthening the mechanical bond. Additionally, this
After board- or substrate-material selection, investi- type of bond elevates the LCC above the board's
gate pc·trace geometries. In accordance with industry· mounting surface, facilitating the cleaning of residual
proven practices, make the LCC foot pads' circuit flux and debris from under the package.
traces the same size as the metallization on the LCC's To take advantage of LCCs' high packaging density,
bottom surface and slightly longer at the package's maintain relatively tight geometries in board-
outer edge (Fig 2a). Lengthening the pc board's metallization layout and manufacturing. Successful

the Dept of Defense (000) have stalling LCCs on pc boards. To module approach usually is more
sought to develop chip-carrier overcome these problems, con- cost effective, Furthermore, major
packaging concepts and stan- sider an alternative packaging semiconductor manufacturers
dards for military applications. method-cofired ceramic sub- offer off-the-shelf ceramic mother
These efforts have resulted in a strates with attached LCCs. boards.
standard line of LCCs with two These substrate mother boards or For example, Mostek makes a
packaging styles-<>ne with 50- modules provide interesting de- 43320 32k dynamic-RAM pack-
mil-center terminal spacing and sign tradeoffs compared with chip- age using two 4116E 18-pin LCC
another with 40-mil centers. With- and-wire hybrids and pc-board- devices. It also plans to combine
in these package styles, a variety mounted LCCs. two 64k 4164E dynamic·RAM
of pin counts is available-16 As one benefit, you don't need LCCs on a mother board to yield a
through 156 in 16 common sizes. LCC-handling and reflow- 128kx 1 dynamic RAM.
The USAF Materials Lab soldering equipment. As another, Texas Instruments employs a
(AFML) has directed and super- you can mount LCCs on both similar approach in its SMJ-
vised 000 LCC development ef- sides of the module, achieving a 444164 256k dynamic RAM,
forts, funded through the Manu- parts density twice that of a which contains four TMS4164 64k
facturing Technology (MANTECH) single-sided pc-board assembly. dynamic RAMs mounted in 28-pin
portion of the DoD's R&D budget. (Note that you can build 2-sided LCCs. And Harris Semiconductor
This group has also financed LCC-based pc-board assemblies, furnishes the HM5-6564 64k
Hughes Aircraft's development but they are difficult for a first- CMOS static RAM. Double-side
and manufacturing of a line of design effort.) As yet another mounted on a ceramic mother
50-mil LCCs and RCA's develop- benefit, you can choose among a board along with four decoupling
ment of 40-mil types. variety of LCC packages and capacitors, this RAM contains an
JEDEC's endeavors have cen- quickly configure a system. array of 16 HM·6504 4k RAM
tered on coordinating industry On the debit side, though, man- chips in LCC packages.
projects with the MANTECH pro- ufacturers charge more for fin- Finally, an analog signal proc-
gram to minimize duplicating ished module products than the essor from Harris, the Hi5-5900,
tasks. Coordinated investigations sum of the parts costs: They comes assembled with five LCC
have produced eight standard typically add the expenses of packages and eight O.1-IJ.Fde-
LCC packages, with two more additional assembly and test time coupling capacitors. The LCCs
versions expected soon. as well as the substrate cost. include an input multiplexer, dual
Many system designers, how- To make a worthwhile pc-board- buffers, a programmable-gain in-
ever, can't justify the time and vs-module comparison, therefore, strumentation amplifier, a refer-
expense required to buy manufac- you must make the traditional ence buffer and a track/hold.
turing equipment and develop build-or-bUy decision. If your ap-
new assembly procedures for in- plication calls for high density, the
guidelines dictate chip-carrier package layouts with In military applications, socketing falls short: Avail-
O.OlO-in.-wide trace lines, O.OIO-in. spaces between able sockets are bulky and have unwieldy construction,
lines and 0.020-in.-diameter (or smaller) feedthrough and although adequate for routine uses, they're defi-
holes. Pads that connect to the LCCs typically run cient for critical ones that demand high packing density
0.020 in. wide on 0.050-in. center spacings. This and undergo severe environmental stresses. As a
center-spacing dimension permits one O.OlO-in.-wide result, reflow soldering, although far from ideal for
line and O.OIO-in.line spacing between LCC mounting attaching LCCs to boards or substrates, works best.
pads (Fig 3). If you must run trace lines between (or To aid the reflow-soldering process, pretin both the
very near) pads, apply a solder mask to the pc board to LCC's package I/O metallization and the interconnect-
prevent solder bridging during the reflow process. ing substrate's metallization. Fluxing and dipping
Using multilayer boards or substrates calls for added methods serve well for pretinning the LCC's package
layout awareness. For example, use the surface-layer pads; use wave soldering or screen on a solder paste for
metallization exclusively to implement LCC mounting the substrate's pads.
pads. This allocation eliminates the need for a solder For wave soldering, after tinning the substrate, use
mask and minimizes solder bridging. Furthermore, to an adhesive or glue to secure the LCC on top of the
reduce electrical noise, arrange the power-supply buses substrate's metallization during reflow soldering. Im-
in a gridded array within a single layer and route signal plementing the solder-paste option calls for applying
lines on other substrate layers. Moreover, if you employ the paste to the substrate's contacts with a screen-
the services of a board manufacturer, make sure that printing technique. This process involves depositing an
the vendor can reproduce the product accurately and 8- to 9-mil-thick layer of wet paste on the contacts and
reliably with the required line widths, hole diameters, then air drying the board until the paste becomes
solder masks and multilayer construction before initiat- tacky. You then mount the LCC, either manually or by
ing LCC layout. machine insertion, onto the corresponding contacts.
Another pre soldering process producing favorable
Mounting LCCs can be difficult results involves bake drying the populated substrate. It
Now that the finished boards are on hand, you must allows air- and flux-pocket evacuation within the paste,
populate them. Attaching LCCs to conventional pc minimizing volatility effects in a vapor-phase soldering
boards entails bonding problems that defy straightfor- operation. Otherwise, unevacuated flux pockets would
ward solutions. Currently, you can choose between two float the LCC package during reflow soldering .and
methods-soldering or socketing. result in misaligned positioning. Bake drying also

I I

-J I EXTENDED
r--SUBSTRATE
METALLIZATION

Fig 2-For proper installation on a substrate or board material, make an LGG's foot-pad metallization the same size as the
associated pc traces. but slightly larger at the chip carrier's outer edge (a). Elongating the pc metallization permits the heated solder
to wet the base contacts and the grooves located on the chip carrier's sides, Forming a fillet. the solder deposit's outer surface
extends over the metallization pad on the substrate's surface (b). This arrangement completes the LGG-to-substrate electrical
connection. strengthens the mechanical bond and slightly lifts the LGG from the substrate for cleaning purposes,
 PRINTED·CIRCUIT
1
META. LCC
LlIZATlON
PADS FO)R

+
rn':~'"0 .'=t"
SECONDARY
VAPOR

PRIMARY

-l-
SATURATED

H0020
VAPOR

D PRIMARY LIQUID
t

D Fig 4-To meet hlgh-yolume production naeda, vapor-

phase ref/ow soldering bonds LCCs to a substrate through
Fig ~Igh LCC pack8glng denalty calls for tight geome- the use of dried solder paste. Within·the soldering chamber,
tries in board metallization, layout and manufacturing. Typical the populated substrate absorbs heat in the primary
chip-ca"ier layouts mandate O.OIO-in.-wide pc traces, saturated-vapor region and reflows the solder joints. Ufting
O.050-in. LCC center spacings and O.OIO-in. spaces be- the substrate into the secondary-vapor ragion cools, dries
tween traces and LCC mounting-pad metallization. and cleans the soldered assembly.

reduces the solder paste's liquidity, temporarily hold- substrate and drops into the boiling liquid. Then the
ing the LCC to the substrate. substrate leaves the chamber soldered, dry and rela-
Locating the LCC on the substrate, however, doesn't tively clean. A final cleaning process ensues immediate-
require critical placement. During reflow soldering, the ly after substrate removal before any residue congeals.
dried solder paste bonds the LCC in position while Yet another reflow-soldering techniqu~ost effec-
heating to reflow temperature: The solder's surface tive for experimental and low-volume production needs
tension pulls the LCC into alignment over the substrate ---€mploys hot solder oil. In this method, the populated
contacts. Placement thus needs only enough accuracy substrate is immersed into a hot oil bath, quickly
to ensure that the LCC's solder pads don't overlap heating the solder and parts to reflow temperature.
other pads on the metallization below. After removal from the bath, the substrate undergoes a
Whatever soldering procedure you choose, though, cooling interval. Finally, a rinsing operation removes
you must apply sufficient, controlled heat to melt the residual oil and excess flux.
solder. Widely used methods include belt furnaces,
heated air chambers and infrared radiation; however, Reflow soldering simplifies reworking
they haven't received widespread industry acceptance. In addition to the board-assembly techniques just
The vapor-phase reflow-soldering technique, on the discussed, you must pay an equal amount of attention to
other hand, proves efficient for high-volume LCC removing LCCs for repair or replacement. Because
production (Fig 4). It typically involves a chamber LCCs contain no leads and board substrates possess no
containing a primary heating zone, a secondary inter- holes to deform, rework proves straightforward. Of
mediate cooling and cleansing zone and a pool of course, soldering factors such as reflow technique and
high-boilingcpoint fluorinated hydrocarbons. temperature, solder type and metallization thickness
During vapor-phase reflow soldering, a populated greatly affect the degree of rework difficulty.
substrate gets lowered into the primary zone. Here, One LCC-package-removal method merely reverses
the saturated vapor causes uniform solder-joint reflow: the hot-solder-oil immersion technique for installing
It condenses over the substrate's surface, dispensing its LCCs. In this approach, after substrate immersion and
latent heat through vaporization. This thermal ex- solder reflow, you remove the LCC from the board
change quickly and evenly heats the substrate. using tweezers or a similar tool.
Next, the substrate gets lifted into the secondary Another removal method involves the use of a
zone. In this vaporized region, the condensed fluid soldering iron containing a specially shaped tip for
accumulated within the primary zone drips off the heating LCC contacts. Youcan also use a forced-hot-air
Vapor-phase reflow soldering
dominates bonding techniques

gun to !Jeat the LCC package and surrounding area.

This heat-gun method is widely used because it's
convenient, inexpensive and practical. After heating,
you lift the package off the board using tweezers.
Before soldering a replacement LCC, though, make
sure you tin its contacts and the substrate's exposed
contacts. Then manually position the new LCC close to
its designated location. Finally, heat the surrounding
area or the entire board to the solder-reflow tempera-
ture, bonding the LCC to the board and completing the
rework cycle. mMII

References
1. Caswell, Greg, and Isaacson, Dale, "Hermetic chip
carrier assembly process and materials evaluation."
Electronic Packaging and Production, January 1982.
2. Dance, Francis J. and Wallace, John L, "Clad metal
circuit board substrates lor direct mounting 01 ceramic
chip carriers," Electronic Packaging and Production,
January 1982.
3. Fennimore, John E, "Hermetic ceramic chip carrier
Implementation." Elactronlc Packaging and Production,
May 1981.
4. Hochstedler. Charles M. and Wilkinson, Jeffrey M.
"Lead less carriers and CMOS technology yield high-
density low-power memory systems," Wescon Procead-
Ings, Session 24, 1980.
5. Jonas, A W, and Garner, L E. Leadless chip carriers:
The packagIng technique of the 1980s, Harris Semicon-
ductor publication.
6. Tsantes. John. "Leadless chip carriers revolutionize
IC packaging." EDN, May 27. 1981, pgs 49-74.
GW(3 C_U_~_i~_:_:
__i_t,_sn_~_e_?V_r_i_:~:~

Introduction 9-2
Custom Capabilities 9-3
Semicustom Capabilities 9-7
Radiation Hardened Products 9-15
Specialized Products 9-27
Product Assurance 9-31
CICO Sales Office Locations 9-33
Harris. A reputation in hi-rei custom circuits no one else can match. An emerging force in
gate arrays and standard cells. A leader with all the options.

Fifteen years of pace-setting experience from programs like Trident and Peacekeeper to
commercial satell ites and heart pacemakers make Harris your logical choice for quality,
speed and performance in custom/semicustom ICs. From commercial screening all the way
to Class S equivalents. And beyond.

If fast turnaround to market introduction or system prove-out in low volumes is your

need, look to Harris gate arrays. Minimum initial investment and development time make
them the logical choice. And upgrading to standard cell or full custom is easy.

Quick turnaround combined with ease of design and medium-to-Iarge volume cost efficien-
cies make Harris standard cells your best buy.

However, for highest performance, lowest unit price, maximum retiability and smallest
silicon area in high-volume requirements, Harris full custom ICs are the preferred option.

Choose the technology. Analog or Digital. Bipolar or CMOS. Separately, or combined

onto a single chip. Let us apply our vast experience to provide you with the right product,
in the right package, at the right price.

You can even choose your level of design and layout participation to make best use of your
in-house capabilities. Use our engineers or use your own. Full capability or silicon foundry,
we offer all the support you need.

And if you have radiation hardeness requirements look no further. Harris is the leading
supplier of radiation hardened circuits in the military marketplace.

1.'

1.'

1.3

1.2
RElATIVE
COMPOSITE
o GATE ARRAY
COST 1.1
• FULL CUSTOM
.•. STANDARD CEll
1.0

0 .•

0.8

T i I ii'
10 20 30 40 50
VOLUME (K UNITS)

For more information or data sheets, mail your request to: Harris Custom Integrated
Circuits Division, P. O. Box 883, Mail Stop 53/107, Melbourne, Florida 32902.
Or Call: (305) 729-5681
 G~G

CUSTOM CAPABiliTIES

• VLSI Development Alternatives

• Custom VLSI Services
• General Custom Capabilities
• Process Alternatives
for MOS Design
 DEVELOPMENT ADVANTAGES

Full Custom Highest speed, highest density (smaller die), lowest recurring cost,
lowest power consumption.

Custom/Semicustom Custom blocks have the advantages of the "full custom" development
(custom blocks & with high speed, density and power in the standard cell section.
standard cells)

Semicustom High speed, density and low power, low recurring and nonrecurring
(standard cell) cost. Proven cells give high probability of success.

Gate Array Lowest nonrecurring cost. Proven cells and macros.

TYPE SERVICES SUPPLIED CUSTOMER INPUTS

System/Chip Partitioning Development of device specification System specification

Logic Simulation Verify logic using CAD equipment Logic diagram

Test Word Generation Generate the test vectors, add para- Logic diagram and specification
metrics and produce a test program

Fault Analysis Analyze test program for detection Logic diagram and test word
of failed states

Circuit Design AC simulations, chip plan device Specification

design

Circuit Layout Generate data base for circuit Design package

fabrication

Mask Fabrication Generate optical or MEBES masks PG, Calma or MEBES data base

Wafer fabrication Produce wafers and if required probe, Masks

assemble, test and burn-in

Device Characterization Analyze units for compliance with Test program and units
specifications and map working zone

"Built to Print" Run wafers and if required probe, Masks, test program and
Production assemble, test and burn-in specification
 Custom Capabilities
GENERAL CUSTOM CAPABILITIES

High Performance Digital Basic process for custom developments, 1OO+MHz operation of clocks,
Si-Gate CMOS high density and low power.

Useful in increasing the level of integration. Utilizes mixed high perfor-

mance Si-Gate CMOS and analog elements.

Class B and Class S Full high reliability screening capabilities (i.e., Burn-in, SEM, Failure
Equivalent Screens Analysis, Wafer lot identity, etc.).

All CICD design personnel have appropriate clearances to participate in

classified developments. Manufacturing and test areas are cleared to
process classified material.

PROCESS ALTERNATIVES
FOR CUSTOM MOS DESIGN
RAD-
CHARAC- HARD
PROCESS TERISTICS fMAX GATE tpd OPTION APPLICATIONS

CMOS VT~0.6 to L1V Yes Custom & semicustom cell library for
Self-Aligned BVDSS >7V computers, industrial controls, inter-
face circuits, memories, heart pace-
Silicon Gate VDD = -1.8 to 7V makers, Telecomm, Dat8comm,
nuclear reactor controls.
SAJI I [email protected], rv5ms Custom
125°C "'10ns HL
Cell Librarv

SAJI IV ~100MHz @4.5V, ""-.J 2ns Custom

125°C rv4ns HD
Cell Library

CMOS VT = 0.5 to 1.5V 5MHz @ 10V 50n.@ 10V Yes Digital communications, interface
Metal Gate BVDSS >15V circuits, logic.

PMOS VT~L5V lMHz 125n5 Average No Digital communications, dynamic

Silicon Gate BVDSS >15V shift register
VDD = -7V
VGG = 15V

PMOS VT = -3V to-4V ~ 1MHz "'-.J125ns Average No Digital communications, dynamic

Metal Gate BVDSS ~30V shift register
VDD -15V =
VGG = -27V

Analog SAJI IV with add- "'-' 2M Hz - Yes Mix analog & digital on same chip for
CMOS ad high value resis- op amps, comparators, oscillators,
tors & voltage inde- analog switches, switched capacitor
pendent capacitors filter, voltage mulitpliers.

High Voltage SAJI , with 40V ~ 50MHz @ 4.5V rv 5ns Custom Yes Interface circuits, industrial control,
CMOS Capability 125°C 10ns automotive.
Cell Library
 G~G

• Design Automation Support

• Standard Cell
• Gate Array
• SSI/MSI Library for
Semicustom Design
;II HARRIS DIAL_A_CHlpSM
CODING & LOGIC
SIMULATION

Features
• DIAL·UP CAPABILITY

• TEGAS SIMULATION

• AUTOMATIC TEST PROGRAM

GENERATION

• EASE OF DESIGN

Description logic simulation program. During this phase, the system

In this phase the designer converts the discrete logic designer simulates the functional operation of the logic
schematic to an equivalent schematic using Harris design, evaluates circuit speed and determines how
SSI/MSI library functions from the cell library. effective his Input test patterns are In detecting circuit
faults.
The designer enters the logic description code at the
terminal. The code is written in the form of a from-to
connection list similar to the component wiring list of a PC
Customer Input
board. The overall procedure Is to code each software
block In a hierarchical manner beginning with the lowest A design may contain SSI/MSI functions which are
level and progressing to the highest. Software macros may required by the design and are not found in the Harris
be defined by the designer on repetitive circuitry to make macro library. If It is decided to have Harris design these
logic coding simpler. After each block Is coded, an macros a design cost will be Incurred. This additional
error-checking program Is run to check for coding errors. design charge may be avoided by the customer by
Errors are corrected using a basic line editor before breaking down the circuit Into primitive logic before defining
proceeding to the next block. the logic In the Harris LDF code.
Once all software blocks are coded, a logic description file • Customer Is to provide a set of test words In TDF truth
IS created which represents the Input database for the table format to be used to develop a test program
complete circuit design. It is used as input to several • Fault simulation of the device must exceed 90% on
programs which perform logic simulation (TEGAS), Initial supplied test word.
layout (MERLYN or MP2D) and network checking • Customer is responsible for Identifying critical paths and
(NETCHK). associated worst case delays.
The next step is to generate a test description file which will • The customer is expected to provide logic simulation and
be used for simulation and test program generation. fault simulation until TEGAS Is approved In the
By having the test vector In this TDF language, a Sentry Teledeslgn'· software package.
test program can be made quickly and easily. • Customer supplies conventional logic diagram in 7400 or
Design verification Is next conducted using the TEGAS 4000 logic.

Harris Output
• Approved LDF and TDF database.
/-::::==============================================:::::--'""
mJ HARRIS HSC-CXXXXX

Features

• 3 MICRON CMOS TECHNOLOGY

• INDIVIDUALL Y PROGRAMMABLE 1/0 BUFFERS

• VARIABLE DIE SIZE

• COMPATIBLE
AUTOMATION
WITH
SYSTEM
DIAL_A_CHlpSM
oO
DESIGN

• 3n5 TYPICAL GATE DELAY

• BI-DIRECTIONAL AND THREE STATE 1/0

• 50MHz TOGGLE FREQUENCY

• TTL AND CMOS COMPATIBILITY

• 74LS-SSI, MSI LIBRARY IMPLEMENTED

• COMMERCIAL TEMPERATURE RANGE

• ADVANCED CAD TELEDESIGNTM

o

SOFTWARE SUPPORT
• MILITARY TEMPERATURE RANGE

• VARIABLE DIE SIZE

• MULTIPLE PACKAGE OPTIONS

Harris Custom Integrated Circuits Division offers a complete family of custom and semicustom products. The
HARRIS Standard Cell product is a very cost effective alternative to gate arrays or full custom. The standard
cell circuit is manufactured using the HAR RIS state-of-the-art SAJI IV local oxidation process. The process
offers 3 IJ. m channel lengths with typical gate delays of 3ns and toggle frequencies of 50MHz. Each input-out-
put buffer can be individually programmed as input, output, three-state or bi-directional. CMOS and TTL com-
patibility can be specified. The same SSI MSI 74LS functions used to design the gate array are used for the
standard cell circuits.

The logic description and simulator functions are identical for both standard cell circuits and gate arrays. How-
ever, the standard cell circuit dimensions can change dynamically for each individual circuit. Where the gate array
is a fixed number of gates and fixed chip size, the standard cell uses only enough silicon to fully implement the
desired logic function. Typically a standard cell chip is 30% smaller than a fully utilized gate array offering a
cost savings benefit to those customers with medium to high volumes.

The standard cell chip does require a complete set of masks rather than the three required by the gate array. The
standard cell circuit is fully supported by the HARRIS Teledesign™ software and the HARRIS Dial-A-ChipsM
timeshare service. This allows the customer to perform as much of the design and development as he desires
from his own office with a data terminal.
 m HARRIS
HGA-C00600
HGA-CO 1200
HGA-C02500

• 3 MICRON CMOS TECHNOLOGY PART GATE DIE I/O ROWS/

TRAN-
SISTOR EQUIV. SIZE CELLS
• 600,1200, AND 2500 GATE ARRAYS NO. PINS
(MILS)
• 3"0 TYPICAL GATE DELAY
• 50 MHz TOGGLE FREQUENCY HGA-e00600 2592 648 198 X 165 54 6 X 36

• 74LS-SSI,MSI LIBRARY IMPLEMENTED HGA-e01200 5184 1296 257 X 198 78 12 X 36

• ADVANCED CAD TELEDESIGNTM HGA-e02500 10.080 2520 272 X 287 100 14 X 60

SOFTWARE SUPPORT
• COMPATIBLE WITH DIAL-A-eHIPSM
DESIGN AUTOMATION SYSTEM
• INDIVIDUALLY PROGRAMMABLE I/O BUFFERS
• BI-DIRECTIONAL AND THREE STATE I/O
• TTL AND CMOS COMPATIBILITY
• COMMERCIAL TEMPERATURE RANGE
• MILITARY TEMPERATURE RANGE
• MULTIPLE PACKAGE OPTIONS
p C

A N

B N

Harris Custom Integrated Circuits Division offers a complete family of custom and semicustom logic. The
HGA-C00600, HGA-C01200 and HGA-C02500 are three CMOS gate arrays manufactured using the HARRIS
state-of-the-art SAJI IV process. This local oxidation process offers 3 m channel lengths and 2 minimum
features. Typical propagation gate delay is 3ns with 50MHz toggle frequencies possible. Personalization is
accomplished by patterning two levels of interconnection on three mask layers: polysilicon, contacts and metal.

The entire process is fully supported by advanced CAD Teledesign TM· software. With the HAR R IS Dial-A-
Chip SM·· design automation system a customer chooses the amount of his participation in the design and
development of his circuit. Using the HAR R IS Teledesign TM timeshare system, logic description, simulation,
and artwork editing can all be performed by the customer in his own office via a digital data communications
link or if he so chooses, he may use the Customer Design Center in Melbourne.

The HARRIS system minimizes the amount of design and logic coding by offering a library of 74LS equivalent
551 and MSI function designs. There is no need to implement large MSI functions with primative gates. Each
function has a complete data sheet specifying propagation delays and A. C. parameters. A final software program
verifies that the original logic description matches the finished artwork.

Each input-output buffer can be individually specified to be input, output, three-state, or bi-directional. CMOS
or TTL compatiblity can also be specified. The large number of I/O buffers keeps the input/output to gate ratio
high insuring that the design is not pin limited.

Transition from gate arrays to standard cell circuits is very simple. The same logic description files are used as
input to the Dial-A-ChipSM software. Both utilize the same 551, MSI 74LS library.
 For use with HARRIS CMOS Gate Array
and Standard Cell Family

HCAOOOXB DUAL 2 INPUT NAND

HCAOOOIB DUAL 2 INPUT NAND WITH INVERTER
HCAOO2XB DUAL 2 INPUT NOR
HCA0021B DUAL 2 INPUT NOR WITH INVERTER
HCA004XB TRIPLE INVERTER
HCA007XB HIGH FANOUT BUFFER (5 pF DRIVE)
HCA008XB 2 INPUT AND
HCA010XB 3 INPUT NAND
HCA011XB 3 INPUT AND
HCA020XB 4 INPUT NAND
HCA021XB 4 INPUT AND
HCA027XB 3 INPUT NOR
HCA029XB 6 INPUT NAND
HCA030XB 8 INPUT NAND
HCA032XB 2 INPUT OR
HCA051XB 4 INPUT AND-OR-INVERT GATE
HCA073XB JK FLIP FLOP WITH RESET
HCA074RB D FLIP FLOP WITH RESET
HCA074SB D FLIP FLOP WITH SET
HCA074XB D FLIP FLOP WITH SET AND RESET
HCAN74RB D FLIP FLOP WITH RESET-NEGATIVE EDGE TRIGGERED
HCAN74SB D FLIP FLOP WITH SET-NEGATIVE EDGE TRIGGERED
HCAN74XB D FLIP FLOP WITH SET AND RESET-NEGATIVE EDGE
TRIGGERED
HCA075XB QUAD D TYPE LATCH WITH INDIVIDUAL RESETS
HCA083SB BCD FULL ADDER
HCA085XB 4-BIT MAGNITUDE COMPARATOR
HCA086XB 2 INPUT EXCLUSIVE OR
HCA138XB 3 'TO 8 LINE DECODER
HCA139XB 2 TO 4 LINE DECODER
HCA152XB 8 TO 1 DATA SELECTOR
HCA157XB QUAD 2 TO 1 DATA SELECTOR
HCA161XB 4-BIT SYNCHRONOUS BINARY COUNTER WITH ASYNCHRONOUS
RESET
HCA163XB 4·BIT SYNCHRONOUS BINARY COUNTER WITH SYNCHRONOUS
RESET
HCA164XB 8-BIT PARALLEL OUTPUT SHIFT REGISTER
HCA165XB 8-BIT PARALLEL LOAD SHIFT REGISTER
HCA173XB 4-BIT D REGISTER WITH THREE STATE OUTPUTS
HCA175XB QUAD D FLIP FLOP WITH RESET
HCA180XB 9-BIT PARITY GENERATOR
HCA192XB 4-BIT SYNCHRONOUS UP DOWN DECADE COUNTER
HCA193XB 4-BIT SYNCHRONOUS UP DOWN BINARY COUNTER
HCA194XB 4-BIT SYNCHRONOUS LOAD BI-DIRECTIONAL SHIFT REGISTER
HCA225XB EXPANDABLE 4 WORD BY 1 BIT FIFO
HCA240XB OCTAL INVERTING THREE STATE BUFFER
HCA244XB OCTAL NON-INVERTING THREE STATE BUFFER
HCA257XB QUAD 2 TO 1 LINE DATA SELECTOR
HCA273XB OCTAL D FLIP FLOP WITH COMMON CLOCK
HCA283XB 4-BIT BINARY FULL ADDER WITH FAST CARRY
HCA352XB DUAL 4 TO 1 LINE DATA SELECTOR
HCA377XB OCTAL D FLIP FLOP WITH ENABLE
HCA393XB 4-BIT BINARY RIPPLE COUNTER
HCA645XB OCTAL BUS TRANSCEIVER
HCA1000B 15:1 RATIO PULL UP RESISTOR WITH ENABLE
 Semicustom Capabilities

HCA SSI/MSI LIBRARY

For use with HARRIS CMOS Gate Array
and Standard Cell Family

HCA900XB CMOS INPUT BUFFER

HCA901XB CMOS INPUT BUFFER WITH 18K PULL UP RESISTOR
HCA910XB TTL INPUT BUFFER
HCA911XB TTL INPUT BUFFER WITH 18K PULL UP RESISTOR
HCA950XB 3.2 MA OUTPUT BUFFER
HCA951XB 3.2 MA OUTPUT BUFFER-OPEN DRAIN P-CHANNEL
HCA952XB 3.2 MA OUTPUT BUFFER-OPEN DRAIN N-CHANNEL
HCA960XB 3.2 MA OUTPUT BUFFER-THREE STATE
HCA970XB 3.2 MA BI-DIRECTIONAL BUFFER-CMOS INPUT
HCA971XB 3.2 MA BI-DIRECTIONAL BUFFER-CMOS INPUT WITH 18K PULL UP
HCA980XB 3.2 MA BI-DIRECTIONAL BUFFER- TTL INPUT
HCA981XB 3.2 MA BI-DIRECTIONAL BUFFER-TTL INPUT WITH 18K PULL UP
RESISTOR
HCAVSSXB PLACEABLE VSS I/O PAD
HCAVIA VIA CELL

STANDARD CELL I/O BUFFERS

HCC900XB CMOS INPUT BUFFER
HCC901XB CMOS INPUT BUFFER WITH 18K PULL UP
HCC905XB CMOS INPUT BUFFER-INVERTING
HCC906XB CMOS INPUT BUFFER-INVERTING WITH PULL UP
HCC908XB SCHMITT TRIGGER INPUT BUFFER
HCC910XB TTL INPUT BUFFER
HCC911XB TTL INPUT BUFFER WITH 18K PULL UP
HCC915XB TTL INPUT BUFFER WITH 18K PULL UP INVERTING
HCC950XB 3.2 MA OUTPUT BUFFER
HCC951XB 3.2 MA OUTPUT BUFFER WITH OPEN DRAIN P-CHANNEL
HCC952XB 3.2 MA OUTPUT BUFFER WITH OPEN DRAIN N-CHANNEL
HCC955XB 8.0 MA OUTPUT BUFFER
HCC960XB 3.2 MA OUTPUT BUFFER THREE STATE
HCC965XB 8.0 MA OUTPUT BUFFER THREE STATE
HCC970XB 3.2 MA BI-DIRECTIONAL WITH CMOS INPUT
HCC971XB 3.2 MA BI-DIRECTIONAL CMOS INPUT AND 18K PULL UP
HCC975XB 8.0 MA BI-DIRECTIONAL WITH CMOS INPUT
HCC976XB 8.0 MA BI-DIRECTIONAL CMOS INPUT AND 18K PULL UP
HCC980XB 3.2 MA BI-DIRECTIONAL TTL INPUT
HCC981XB 3.2 MA BI-DIRECTIONAL TLL INPUT AND 18K PULL UP
HCC985XB 8.0 MA BI-DIRECTIONAL TTL INPUT
HCC986XB 8.0 MA BI-DIRECTIONAL TTL INPUT AND 18K PULL UP
HCC990XB UNBUFFERED INPUT WITH STATIC PROTECTION
HCCVDDYB VDD SUPPLY PAD
HCCVSSYB VSS SUPPLY PAD
 HIGH DENSITY HD CELL LIBRARY (PRIMITIVE FUNCTIONS)

FUNCTIONAL
CELL DESCRIPTION SIZE DELAY TRANS
HD1100 LOGIC I/O CONNECTION 132 x 20 Jim N/A N/A
HD1110 INVERTER 132 x 30 Jim 3.0 ns 4.7 ns
HD1130 3XINVERTER 132 x 40 Jim 2.7 ns 4.5 ns
HD1150 5XINVERTER 132 x 50 Jim 3.1 ns 5.0 ns
HD1160 CMOS BUFFER 132 x 50 Jim 2.7 ns 1.5 ns
HD1180 TTL TO CMOS BUFFER 132 x 50 Jim 4.0 ns 2.5 ns
HD1210A 2 INPUT NAND 132 x 40 Jim 3.0 ns 5.0 ns
HD1220 2 INPUT AND 132 x 50 Jim 3.5 ns 2.7 ns
HD1230 2 INPUT NOR 132 x 40 Jim 3.0 ns 5.3 ns
HD1240 2 INPUT OR 132 x 50 Jim 3.5 ns 3.0 ns
HD1310 3 INPUT NAND 132 x 50 Jim 3.1 ns 4.9 ns
HD1320A 3 INPUT AND 132 x 60 Jim 3.3 ns 2.8 ns
HD1330A 3 INPUT NOR 132 x 50 Jim 3.3 ns 5.6 ns
HD1340 3 INPUT OR 132 x 70 Jim 3.8 ns 2.8 ns
HD1410 4 INPUT NAND 132 x 60 Jim 3.3 ns 5.0 ns
HD1420 4 INPUT AND 132 x 70 Jim 3.5 ns 2.5 ns
HD1430 4 INPUT NOR 132 x 90 Jim 4.8 ns 3.0 ns
HD1440 4 INPUT OR 132 x 80 Jim 3.5 ns 2.6 ns
HD2120 EXCLUSIVE-OR 132 x 80 Jim 4.7 ns 3.5 ns
HD2130 EXCLUSIVE-NOR 132 x 70 Jim 5.4 ns 3.4 ns
HD2140 TRANSMISSION GATE 132 x 40 Jim 1.2 ns 7.3 ns
HD2150 TRI·STATE INV 132 x 50 Jim 2.0 ns 4.4 ns
HD2210 4 TO 1 MUX 132 x 240 Jim 5.0 ns 5.0 ns
HD2220 2 TO 1 MUX 132 x 100 Jim 3.9 ns 2.5 ns
HD2230 2, 2-AND, 2-NOR 132 x 60 Jim 4.1 ns 6.6 ns
HD2240 2, 3-AND, 2-NOR 132 x 80 Jim 4.4 ns 6.9 ns
HD2250 3, 2-AND, 3-NOR 132 x 80 Jim 4.8 ns 7.8 ns
HD3100 D FF 132 x 120 Jim 2.5 ns 3.2 ns
HD3110 D FF W/RESET 132 x 150 Jim 3.4 ns 3.2 ns
HD3120 D FF W/RESET, OBR 132 x 170 Jim 4.3 ns 4.0 ns
HD3130 D FF W/SET, RESET 132 x 180 Jim 5.0 ns 3.8 ns
HD3140 D FF W/SET, OBAR 132 x 170 Jim 4.2 ns 4.2 ns
HD3150 D FF W/OBAR 132 x 140 Jim 4.5 ns 3.5 ns
HD3200A JK FF 132 x 160 Jim 4.5 ns 5.0 ns
HD3210 JK FF W/RESET 132 x 180 Jim 4.8 ns 4.8 ns
HD3220A JK FF W/RESET, OBR 132 x 210 Jim 5.4 ns 3.5 ns
HD3230 JK FF W/SET, RESET 132 x 250 Jim 5.4 ns 4.3 ns
HD3240 JK FF W/SET 132 x 210 Jim 5.0 ns 5.4 ns
HD3250 JK FF W/OBAR 132 x 210 Jim 6.7 ns 7.0 ns
HD3260A JK FF W/R, OBAR (POS) 132 x 210 Jim 5.5 ns 3.6 ns
HD5040A 4·BIT SHIFT REGISTER 132 x 340 Jim 4.6 ns 4.6 ns
HD5060A 6-BIT SHIFT REGISTER 132 x 500 Jim 4.6 ns 4.6 ns

NOTE: DESIGN AND DEVELOPMENT SUPPORT FOR THIS LIBRARY IS

PROVIDED BY CUSTOM INTEGRATED CIRCUITS DIVISION
ENGINEERING.
 FUNCTIONAL
CELL DESCRIPTION SIZE DELAY TRANS
HD5080A 8-BIT SHIFT REGISTER 132 x 660 pm 4.6 ns 4.6 ns
HD6210 2 INPUT NAND (INV) 132 x 50 pm 3.4 ns 4.9 ns
HD6220 2 INPUT AND (INV) 132 x 70 pm 4.0 ns 3.0 ns
HD6230 2 INPUT NOR (INV) 132 x 60 pm 4.0 ns 5.3 ns
HD6240 2 INPUT OR (INV) 132 x 50pm 3.4 ns 5.0 ns
HD6310 3 INPUT NAND (INV) 132 x 70 pm 3.7 ns 4.9 ns
HD6320 3 INPUT AND (INV) 132 x 80 pm 4.5 ns 3.0 ns
HD6330 3 INPUT NOR (INV) 132 x 70 pm 4.2 ns 5.6 ns
HD6340 3 INPUT OR (INV) 132 x 80 pm 4.5 ns 3.1 ns
HD6410 4 INPUT NAND (INV) 132 x 80 pm 4.0 ns 5.1 ns
HD6420A 4 INPUT AND (INV) 132 x 80 pm 5.3 ns 2.6 ns
HD6430 4 INPUT NOR (INV) 132 x 110 pm 5.0 ns 2.6 ns
HD6440 4 INPUT OR (INV) 132 x 100 pm 4.7 ns 3.1 ns
HD8120A P CHAN TEST DEVICES 239 x 269 pm N/A N/A
HD8220A N CHAN TEST DEVICES 239 x 269 pm N/A N/A
HD8310AQ N- TEST CAPACITOR 174 x 397 pm N/A N/A
HD8320 P- TEST CAPACITOR 186 x 358 pm N/A' N/A
HD8420A TEST RESISTORS 185 x 251 pm N/A N/A
HD8510 ALIGNMENT MARKS 66 x 302 pm N/A N/A
HD8520 MASK REVISION 10 64 x 272 pm N/A N/A
HD8530 CRITICAL DIMENSION 86 x 174 pm N/A N/A
HD8610 CORNER ROT. MARK 1 28 x 78pm N/A N/A
HD8620 CORNER ROT. MARK 2 28 x 78pm N/A N/A
HD8710 COPYRIGHT SYMBOL 82 x 87 pm N/A N/A
HD8720 "HARRIS" 34 x 239 pm N/A N/A
HD8730 HARRIS LOGO 146 x 146 pm N/A N/A
HD8750 CICD 40 x 154 pm N/A N/A
HD8810 #1 PAD 10 (1 SIDE) 21 x 105 pm N/A N/A
HD8820 #2 PAD 10 (2 SIDES) 126 x 126 pm N/A N/A
HD8910 VIA 6x 6pm N/A N/A
HD8920 FEED THROUGH CELL 132 x 10 pm N/A N/A
HD9100 VDD TYPE A 314 x 170 pm N/A N/A
HD9130 VSS TYPE B 314 x 170 pm N/A N/A
HD9210 INPUT W/PROTECT A 314 x 240 pm N/A N/A
HD9220 INPUT W/PULLUP A 314 x 250 pm N/A N/A
HD9230 INPUT W/PULLDOWN A 314 x 280 pm N/A N/A
HD9240 BUFFERED OUTPUT A 314 x 320 pm 6.1 ns 4.1 ns
HD9250 BI-DIRECTIONAL A 314 x 390 pm 6.8 ns 5.0 ns
HD9310 INPUT W/PROTECT B 314 x 240 pm N/A N/A
HD9320 INPUT W/PULLUP B 314 x 260 pm N/A N/A
HD9330 INPUT W/PULLDOWN B 314 x 280 pm N/A N/A
HD9340 BUFFERED OUTPUT B 314 x 320 pm 6.1 ns 4.1 ns
HD9350 BI-DIRECTIONAL B 314 x 390 pm 6.8 ns 5.0 ns

NOTE: DESIGN AND DEVELOPMENT SUPPORT FOR THIS LIBRARY IS

. PROVIDED BY CUSTOM INTEGRATED CIRCUITS DIVISION
ENGINEERING.
 GwG
RADIATION HARDENED
CMOS PRODUCTS

• Current Products
• Future Products
BUS INTERFACE CIRCUITS
HS-15530RH Rad Hard Mil. Std. 1553 Encoder/Decoder (24 Pins)

RAD HARD MEMORIES

HS-6504RH Rad Hard 4K x 1 CMOS RAM
HS-6508R H Rad Hard 1K x 1 CMOS RAM
HS-6514RM Rad Hard 1K x 4 CMOS RAM
HS-6551 RH Rad Hard 256 x 4 CMOS RAM
HS-6564RH Rad Hard 64K Memory Module (8K x 8 or 16K x 4)
HS-6532RH Rad Hard 32K Memory Module (8K x 4 or 16K x 2)

ANALOG SWITCHES/MULTIPLEXERS
HS-508ARM Rad Hard 8 Channel Multiplexer
HS-1840RH Rad Hard 16 Channel Multiplexer
;m HARRIS HS-15530RH
Radiation Resistant
CMOS Manchester Encoder-Decoder

VALIOWQRQ vcc
SUPPORT OF MIL-STD-1553 ENCODER SHIFT CLOCK ENCODER CLOCK
TAKE DATA SEND CLOCK IN
• 1.0 MEGABIT/SEC DATA RATE
SERIAL OATA OUT SEND DATA
• SYNC IDENTIFICATION AND LOCK-IN
DECODER CLOCK 5 SYNC SELECT
• CLOCK RECOVERY BIPOLAR ZERO IN 6 ENCODER ENABLE
• MANCHESTER II ENCODE, DECODE BIPOLAR ONE IN 7 SERIAL DATA IN

• SEPARATE ENCODE AND DECODE UNIPOLAR DATA IN 8 BIPOLAR ONE OUT

DECODER SHIFT CLOCK 9 OUTPUT INHiBIT
• LOW OPERATING POWER: 50mW AT 5 VOLTS
COMMAND/DATA SYNC 10 ~ZEAOOUT
• FULL MILITARY TEMPERATURE RANGE .:-60UT
DECODER RESET 11
• FUNCTIONAL TOTAL DOSE .. , 1 x 104 RAD(Sil GNO 12 MASTER A ESET

• LATCH·UP FREE TO 5 x 1011 RAD (Si)/sec

The Harris HS-15530RH is a high performance, radia- pulse and the parity bit as well as the encoding of the
tion resistant, CMOS device intended to service the data bits. The Decoder recognizes the sync pulse and
requirements of MIL-STD-1553 and similar Manches- identifies it as well as decoding the data bits and
ter II encoded, time division multiplexed serial data checking parity.
protocals. This LSI chip is divided into two sections,
an Encoder and a Decoder. These sections operate This integrated circuit is fully guaranteed to support
completely independent of each other, except for the the 1MHz data rate of M I L- STD-1553 over both
Master Reset function. temperature and voltage while residing in a radiation
environment. It interfaces with CMOS, TTL or N
This circuit provides many of the requirements of channel support circuitry, and uses a standard 5 volt
MIL-STD-1553. The Encoder produces the sync supply.

12~ GND Vcc <24

13 MASTER RESET
OUTPUT
UNIPOLAR
22 iNiiiiiTT 16
DATA IN
BIPOLAR 7
TAKE DATA
IiTPOLAR ONE IN COMMANO!DAlA
ONE OUT
BIPOLAR SYNC
BIPOLAR ZERO IN
4 SERIAL
l"E"ROOUf
DATA OUT
m HARRIS HS-6504RH

Preliminary
Features Pinout
• LOW POWER STANDBY 25pWTYP.
TOPVIEW
• LOW POWER OPE RATION 25mW/MHz TYP.
• EXTREMELY LOW SPEED POWER PRODUCT AO VCC
• FUNCTIONAL TOTAL DOSE 1 x 105 RAD SI A1 AS
• DATA UPSET > loB RAD SI/. A2 A7
• LATCH· UP FREE TO > 5 x 1011 RAD SII. AJ A8
• TTL COMPATIBLE INPUT/OUTPUT A4 A9
.THREE ·STATE OUTPUT AS Al0
• STANDARD JEDEC PINOUT a All
• FAST ACCESS TIME W D
• MILITARY TEMPERATURE RANGE OND E
.18 PIN PACKAGE FOR HIGH DENSITY
• ON CHIP ADDRESS REGISTER

Description
The HS-6504RH is a 4096 x 1 static CMOS RAM fabricated using the
Harris Custom Integrated Circuits Division radiation hardened self·aligned
silicon gate technology. The device utilizes synchronous circuitry to achieve
high performance and low power operation.

On-chip latches are provided for addresses. data input and data output
allowing efficient interfacing with microprocessor systems. The data out-
put can be forced to a high impedance for use in expanded memory arrays.

The HS-6504RH is a fully static RAM and may be maintained in any state A - Addr." Input
E Chip Enablt!
for an indefinite period of time. iN WrtttEn,bl,
0- 011. Input
a- DIl.Outpul

Functional Diagram
A8
A7
A6
Al
A2
A3

ALL LINES ACTIVE HIGH - POSITIVE LOGIC

THREE STATE BUFFERS:
C HIGH ~ OUTPUT ACTIVE
LATCHES:
C LOW •....•.O· 0
a LATCHES ON RISING EDGE OF C

Information on this devlce;s preliminary. Data is subject to change unless otherwise specifically agreed. No obligations are assumed tor notice of
change or future manufacture of this device.
CAUTION: These devices are sensitive to
electrostatic discharge.
mJ HARRIS HS-6508RH

Pinout
TOPVIEW
• FUNCTIONAL TOTAL DOSE ......•... ..... 2 x 104 RAD Si
• LATCH-UP FREE TO ...........•.•. 5.0 x 101' RAD Si/sec vcc
• LOW STANDBY POWER .. ... 550J.lW MAX
AD D
• LOW OPERATING POWER. 25mW/MHz MAX
• FAST ACCESS TIME .... 300n,ec MAX A' Vi
• TTL COMPATIBLE INIOUT A2 A9
• HIGH OUTPUT DRIVE - 2 TTL LOAOS
A3 AS
• HIGH NOISE IMMUNITY
• ON-CHIP ADDRESS REGISTER A' A7

• MILITARY TEMPERATURE RANGE a A6

• THREE-STATE OUTPUTS
GND AS
• 16 PIN PACKAGE FOR HIGH DENSITY

A - Address Input D - Data Input

E - Chip Enable Q - Data Output
W - Write Enable

The HS-6508RH is a 1024 by 1 static CMOS RAM fabricated using the

HARRIS Programs Division radiation hardened self-aligned silicon gate
technology. Synchronous circuit design techniques are employed to
achieve high performance and low power operation.

On-chip latches are provided for addresses allowing efficient interfacing with
microprocessor systems. The data output buffers can be forced to a high
impedance state for use in expanded memory arrays.

The HS-6508RH is a fully static RAM and may be maintained in any

state for an indefinite period of time.
 ;II HARRIS HS-6514RH
Preliminary
Pinout
TOPVIEW
• LOW POWER STANDBY 25/lW TYP.
• LOW POWER OPERATION 25mW/MHz TYP.

• FUNCTIONAL TOTAL DOSE 1 x 105 RADSi

• DATA UPSET > 108 RADS Sits

• LATCH - UP FREE TO > 5 x 1011 RAD Sits

• TTL COMPATIBLE INPUT/OUTPUT

• COMMON DATA IN/OUT

• THREE - STATE OUTPUTS

• STANDARD JEDEC PINOUT

• FAST ACCESS TIME

• MILITARY TEMPERATURE RANGE

• 18 PIN PACKAGE FOR HIGH DENSITY

• ON - CHIP ADDRESS REGISTER

The HS-6514RH is a 1024 x 4 static CMOS RAM fabricated using the

Harris Custom Integrated Circuits Division radiation hardened self-aligned
silicon gate technology. The device utilizes synchronous circuitry to achieve
high performance and low power operation.
On-chip latches are provided for the addresses allowing efficient interfacing
with microprocessor systems. The data output can be forced to a high
impedance state for use in expanded memory systems. A - Address I,..pul
E - ChiP Enable
The HS-6514RH is a fully static RAM and may be maintained in any state iN Write En.b1e
DO - Oil. In/QUI
for an indefinite period of time.

GATED COLUMN
DECODER
AND
DATA
INPUTIOUTPUT

All LINES ACTIVE HIGH -

POSITIVE lOGIC
THREE STATE BUFFERS:
A HIGH_ OUTPUT ACTIVE

ADDRESS REGISTERS:
LATCH ON RISING EDGE OF l
GATED DECODERS·
GATE ON RISING EDGE OF G

E W A6 AO /4.1 A2

Information on this device Is preliminary. Dat. Is subject to change unless otherwise specifically agreed. No obligations are assumed for notice of
change or future manufacture of this device.
CAUTION: These devices are sensitive to
electrostatic discharge. 9-20
m HARRIS HS-6551RH

• FUNCTIONAL TOTAL DOSE 2. 104 RAD Si

• LATCH-UP FREE TO 5.0. 1011 RAD Si/_
• LOW STANDBY POWER 550~WMAX
• LOW OPERATING POWER 25mW/MHz MAX
• FAST ACCESS TIME 300nsMAX
• TTL COMPATIBLE IN/OUT
• HIGH OUTPUT DRIVE - lTTL LOAD
• HIGH NOISE IMMUNITY
• ON CHIP ADDRESS REGISTER
• MILITARY TEMPERATURE RANGE
• THREE-5TATE OUTPUTS
• 22 PIN PACKAGE FOR HIGH DENSITY

A - Address Input W- Write Enable

E- Chip Enable D - Data Input
g- Chip Select Q - Data Output

The HS-6551 RH is a 256 by 4 static CMOS RAM fabricated using the

Harris Programs Division radiation hardened self-aligned silicon gate
technology. Synchronous circuit design techniques are employed to
achieve high performance and low power operation.

On-ehip latches are provided for addresses, allowing efficient inter-

facing with microprocessor systems. The data output buffers can be
forced to a high impedance state for use in expanded memory arrays.

The HS-6551 RH is a fully static RAM and may be maintained in any

state for an indefinite period of time.

allUD
COLU."
olCooI"
AMo 0"''''
""U'lOunu,
;II HARRIS HS-6564RH
Radiation Resistant
8K x 8, 16K x 4 CMOS RAM
Preliminary
Pinout
500llW MAX
TOP VIEW
• LOW POWER STANDBY
• LOW POWER OPERATION 180mW/MHz MAX 'GND 40 VCC'
• DATA RETENTION 3.0 V MIN 04 39 00
• TTL COMPATIBLE IN/OUT D4 38 DO
• THREE STATE OUTPUTS as 37 01
• FAST ACCESS TIME DS 36 Dl
• MILITARY TEMPERATURE RANGE AO 3S. A6
• ON CHIP ADDRESS REGISTERS Al 34 A7
• ORGANIZABLE 8Kx8 OR 16Kx4 A4 33 A8
• 40 PIN DIP PINOUT 2.000" x 0.900" E3 32 El
• FUNCTIONAL TOTAL DOSE 1xl0s RAD Si 'W2 31 W,
• DATA UPSET > 10' RAD Si/SEC W2 30 W,,
• LATCH-UP FREE TO > 5 x 1011 RAD SI/SEC E4 29 E2
All 28 A3
Description Al0 27 A2
A9 26 AS
The HS-6564RH is a radiation resistant 64K bit, synchronous CMOS RAM. It D6 25 D2
consists of 16 HS-6504RH 4Kxl radiation resistant CMOS RAMs, in lead less 06 24 02
carriers, mounted on a ceramic substrate. The HS-6564RH is configured as an extra D7 23 D3
wide, standard length 40 pin DIP. The memory appears to the system as an array of 07 22 03
16 4Kxl static RAMs. The array is organized as two 8K by 4 blocks of RAM sharing 'VCC 21 GND'
only the address bus. The data inputs, data outputs, chip enables and write enables 'NOTES:
are separate for each block of RAM. This allows the user to organize the
Pins 20 and 40 (Vee) are internally connected.
HS-6564RH RAM as either an 8K by 8 or a 16K by 4 array. Similarly pins 1 and 21 (Ground) are connected. The

This 64K memory provides a unique blend of low power CMOS semiconductor user is advised to connect all four VCC pins and
Ground pins 10 his board busses. This will improve
technology and advanced packaging techniques. The HS-6564RH is intended for
power distribution across the array and will enhance
use in radiation environments where a large amount of RAM is needed, and where
decQupling.
power consumption and board space are prime concerns. On-chip latches are
Pin 10 is internally connected to pin 11, and pin 30 is
provided for addresses, data input and data output allowing efficient interfacing with
connected to pin 31. For those users wishing to
microprocessor systems. The data output can be forced to a high impedance for use
preserve board compatibility with possible future
in expanded memory arrays. The guaranteed low voltage data retention characteris- RAM arrays, we recommend connections to the write
tics allow easy implementation of non-volatile read/write memory by using very lines be made at pins 11 and 31, leaving pins 10 and
small batteries mounted directly on the memory circuit board. 30 free for future expansion.

0.Q.t 0505 0606 0107

Information on this device Is prelim;nary. Data;s subject to change unless otherwise specifically agreed. No obligations are assumed for notice of
change or future manufacture of this device.
CAUTtON' These c1e..•.•
ces are sensiti ..•.
e to electrOniC discharge.
 HS-508ARH
:II HARRIS Radiation Resistant
8 Channel CMOS Analog Multiplexer
Preliminary With Overvoltage Protection

• ANALOG/DIGITAL OVERVOLTAGE PROTECTION The HS-508ARH is a dielectrically isolated, radiation reo

• FAIL SAFE WITH POWER LOSS (NO LATCHUP) sistant, CMOS analog multiplexer incorporating an important
• BREAK-BEFO RE-MAKE SWITCHING
feature; it withstands analog input voltages much greater
• DTL/TTL AND CMOS COMPATIBLE
• ANALOG SIGNAL RANGE ±15V than the supplies. This is essential in any system where
• ACCESS TIME (TYP.) 500ns the analog inputs originate outside the equipment. They
• SUPPLY CURRENT AT lMHz can withstand a continuous input up to 10 volts greater
ADDRESS TOGGLE (TYP.) 4mA than either supply, which eliminates the possibility of damage
• STANDBY POWER (TYP.) 7.5mW when supplies are off, but input signals are present. Equally
• RADIATION ENVIRONMENT
importani, it can withstand brief input transient spikes of
NEUTRON FLUENCE (<I» 1 x 109 n/cm2 (E ~ 10KeV)
several hundred volts; which otherwise would require com·
GAMMA RATE ( Y ) . . 1 x 108 RADs(Si)/s
GAMMA DOSE ( )' ) . 1 x 105 RADs(Si) plex external protection networks. NecessarilY,ON resistance
is somewhat higher than similar unprotected devices, but
very low leakage current combine to produce low errors·
Pinout Reference Application Notes 520 and 521, available from
the Analog Products 0 ivision of Harris, for further infor·
mation on the 508A multiplexer in general.
TOP VIEW

AO Al
16
The HS-508ARH has been specifically designed to meet
EN 15 A2
exposure to radiation environments. Operation from -550C
-Vsup 14 GND to +1250C is guaranteed.
IN! 13 +Vsup

IN2 12 IN5

IN3 11 IN6

IN4 10 IN)

OUT IN8

-,

01 c; I TA ~
-,
lloolUS
Cl

~::::::::I""'"
-, '-'
'-'

.290 J
.320---'

n
I .790 I .ZOO
L......'2Z°-j1
.125 • ,
100 I I 1:
~~ I -,
TI!
-1.1 :
.060 -. "-I
.014
m
t- U I-
.030
:oro
-j
I I
.100
BsC
.015
r .098 F60 t ~\\-
-I
OO~150 .008
N
 HS-1840RH
ml HARRIS Radiation Resistant
16 Channel CMOS Analog
Preliminary Multiplexer with Hlgh·Z Analog
Input Protection

• HIGH ANALOG INPUT IMPEDANCE

OURING POWER LOSS (OPEN)
• LOW POWER CONSUMPTION
(STANDBY)
• ACCESS TIME The HS·1840RH is e radiation resistant, monolithic 16 channal
• EXCELLENT IN HI·REL REDUNDANT SYSTEMS multiplexer constructed with the Harris LinBer Dielectric Iso·
• BREAK·BEFORE·MAKE SWITCHING
lation CMOS process. It is dasigned to provide a high input
• NO LATCH·UP
impedance to the anelog source if device power fails (open)
• RADIATION ENVIRONMENT
NEUTRON FLUENCE (t/I ) • 1 x 109 n/cm2(E ~ 10KeV) or the analog signal voltage inadvertantly axceeds the supply
GAMMA RATE ( ;. ) • 1 x lOB RADs (Sill. rails during pOW8~ed operation. Excellent for use in redundant
GAMMA DOSE ( Y ) . • • . . 2 x 105 RADs(Sil applications, sincB the sacondary davice can be operated in a
standby unpowared mode affording no additional power drain.
But more significantly, a very high impedancB exists bBtwBan tha
active and inactiva devicas preventing any intaraction. One of
sixtaen channel selection is controlled by a 4·bit binary addrass
plus an Enable·lnhibit input which convBniently controls the
o NIO F F operation of sevaral multiplexers in a systam. All digital
inputs have elBctrostatic dischargB protection.

The HS·1840RH has been specifically designed to meet exposura

to radiation anvironments. It is available in a 28 pin dual·in·line
package and is guaranteed operational from -550C to +1250C.

A,
+VSUPPL V 1 28 OUT
NC 2 21 -VSUPPLV
NC 3 26 IN 8 A,
IN 16 4 25 IN 1 DIGITAL
AODIHSS
IN 15 5 24 IN 6
IN 14 6 23 IN 5
A,
IN 13 1 22 IN 4
IN 12 8 21 IN 3 A,
IN 11 9 20 IN 2
IN 10 10 19 IN 1
IN 9 11 18 ENABLE
GND 12 11 ADDRESS AO
(+5VSUPPL vi VRE F 13 16 ADDRESS Al I
L. J ______ J
ADDRESS A3 14 15 ADDRESS A2
AOOIIUIiI""UTIUFFEII MULll'LU
ANOlEVnSHIFTEII SWIlC:Hf$
 FUTURE RADIATION HARDENED 80C85 FAMILY

INDUSTRY AVAIL-
DEVICE SANDIA PIN EOUIVALENT HCICD PIN ABILITY

8 Bit CPU SA3000 8085 HS-80C85RH 20 '84

256 x 8 CMOS RAM SA3001 8155/56 HS-8155/56R H 20 '84
with I/O Ports and Timer

2K x 8 CMOS RAM SA3002 8355 HS-8355RH 20 '84

3 to 8 Li ne Decoder SA2995 74138 - 20 '84

Bi-directional CMOS/TTL SA2996 40116 - 20 '84

Level Converter

Bus Transceiver SA2997 8208 - 20 '84

Input/Output Port SA3026 8212 - 20 '84

FUTURE RADIATION HARDENED PROMs

ORGANI- INDUSTRY AVAIL-

DEVICE ZATION EOUIVALENT COMMENTS ABILITY

4K CMOS PROM 512 x 8 HM-6641 • Latch-up Free 20 '84

• Total Dose Goal
~ 1 x 105 RADS (SI)

FUTURE RADIATION HARDENED STATIC RAMs

ORGANI- AVAIL-
DEVICE ZATION COMMENTS ABILITY

16K CMOS STATIC 16K x 1 • Immune to single event upset 20 '84

Asynchronous RAM • Total Dose Tolerant to ~ 5 x 105
RADs (Si)
• Latch-up Free
 GwG

Bus Interface Circuits

• HS-3182 ARINC 429 Line Driver
• HS-3282 ARINC 429
Line Receiver/Transmitter

Other
• HS-3819 Video Character Generator
m HARRIS HS-3182
ARINC 429 Bus Interface
Line Driver Circuit

• INPUTS Th AND CMOS COMPATIBLE The HS-3182 ARINC 429 bus interface driver circuit is a
monolithic dielectrically isolated bipolar differential line driver
• ADJUSTABLE RISE AND FALL TIMES VIA designed to meet the specifications of ARINC 429. This device
2 EXTERNAL CAPACITORS is intended to be used with a companion chip, HS-3282 CMOS
ARINC bus interface circuit. which provides the data formatting
• PROGRAMMABLE OUTPUT DIFFERENTIAL RANGE
and processor interface function.
VIA VOLTAGE REFERENCE INPUT IVREFI
All logic inputs are T2L and CMOS compatible. In addition to the
• POWER STROBE INPUT PERMITS LOW QUIESCENT DATAIAI and DA TAIB) inputs there are also Inputs far a CLOCK and
POWER OF 2DmW < SYNC signal which are AND' 0 with the DATA inputs. This feature
• OUTPUTS ARE INHIBITED 10 VOLTSIIF DATA (AI AND was added to enhance system performance and to allow the
DATA (BIINPUTS ARE BOTH IN THE "LOGIC ONE" HS-3182 to be used with devices other than the HS·3282. Also ad-
STATE ding to system performance is the STROBE input. To minimize
power consumption the ~ input can be asserted to place the
• CAN OPERATE UP TO A 100 KILOBITS DATA RATE chip in the power-down mode where It draws substantially less cur-

• OUTPUT SHORT CIRCUIT PROOF AND CONTAINS

rent. Four power supplies are required; + V + 15V ±1 0%, =
-V= -15V±10%, V1 =5V±5% andVREF. VREFisusedtopro-
OVERVOLTAGE PROTECTION
gram the output voltage swing, such that VOUT IDIFF) = ± 2VREF.
• DATA "A" AND DATA "B" SIGNALS ARE "AND'D" Typically, VREF=V' =5V±5%.
WITH CLOCK AND SYNC SIGNALS
The driver output impedance is 75n ±20% at 25°C. Output
• FULL MILITARY TEMPERATURE RANGE rise and fall times are programmed through the use of two
external capacitors, CA and Ce. To meet the requirements for rise
and fall times as specified in ARINC 429,CA=CB=75pF for the
high speed operation 1100 KBPSJ and 500 pF for the low speed
operation (12-14.5 KBPS). The outputs are protected against

a I 0 I overvohage and short circuit as shown in the Block Diagram. This

device is designed to operate with a case temperature range of
-55°C to +125°C.

~
B " S

LEAD DIM DIM. DIM. DtM. ['11M. DIM. DIM. DIM. DIM. DIM. DIM.
COUNT
• B C D E F G
" L a s STROBE SYNC CLOCK DATA
,.,
DATA AOUT BOUT COMMENTS
lA'
IDO 015
16 -
2DO
014
023
DOB
015
-
B40
220
310
790
320
030
070 BSC '"
200 060 060
"
x x x X HI·Z HI·Z Power-Down
State
l X l X X Ov OV NULL
L L X X X OV ov NULL
l l l OV OV NULL
l
L "" "" L
"l
- VREF + VREF
-VREF
LOW
HIGH
l "" "" "" "
+ VREF
OV OV NULL

Pinout TOP VIEW

VREF Vl
'"Aoo, Si'R'OiiE NC

SYNC CLOCK

" DATA (A) DATA (B)

"
'. 'ov,
011
CA
AOUT
-V
CB
BOUT

NC
v, IHIl
GND +V
$'i1i'OiE (21
 m HARRIS HS-3282
CMOSARINC
Bus Interface Circuit

The Harris HS·3282 is a high performance CMOS • ARINC SPECIFICATION 429 COMPATIBLE
bus Interface circuit that Is intended to meet the reo • DATA RATES OF 100 KILOBITS OR 12.5 KILOBITS
quirements of ARINC Specification 429, and similar • SEPARATE RECEIVER AND TRANSMITTER SECTION
encoded, time multiplexed serial data protocols. • DUAL AND INDEPENDENT RECEIVERS, CONNECTING
The ARINC 429 bus Interface circuit consists of two DIRECTLY TO ARINC BUS
(2) receivers and a transmitter operating Indepen· • SERIAL TO PARALLEL RECEIVER DATA CONVERSION
dently as shown In Figure 1. The two receivers oper· • PARALLEL TO SERIAL TRANSMITTER DATA CONVERSION
ate at a frequency that is ten (10) times the receiver • WORD LENGTHS OF 25 OR 32 BITS
data rate, which can be the same or different from • PARITY STATUS OF RECEIVED DATA
the transmitter data rate. Although the two recelv· • GENERATE PARITY OF TRANSMITTER DATA
ers operate at the same frequency, they are func· • AUTOMATIC WORD GAP TIMER
tlonally Independent and each receives serial data • SINGLE S-VOLT SUPPLY
asynchronously. The transmitter section of the • LOW POWER DISSIPATION
ARINC bus Interface circuit consists mainly of a • FULL MILITARY TEMPERATURE RANGE
Flrst·ln Flrst·Out (FIFO) memory and timing circuit.
The FIFO memory Is used to hold eight (8) ARINC
data words for transmission serially. The timing clr·
cuit Is used to correctly separate each ARINC word
as required by ARINC Specification 429.

Even though ARINC Specification 429 specifies a

32·bit word, including parity, the HS·3282can be pro·
grammed to also operate with a word length of 25
bits. The Incoming receiver data word parity is Pinout
checked, and a parity status Is stored in the receiver
latch and Is outputted on Pin B008 during the 1st TOP VIEW
word. [A logic "0" Indicates that an odd number of
logic "1 "s were received and stored; a logic "1" indio vcc , 40 N/C
cates that an even number of logic "1 "s were recelv· 429011fAI 39 Mil
ed and stored]. In the transmitter the parity gener· 429011fBI 3B TX ClK
ator will generate either odd or even parity depend· 4290121AI 37 TTL ClK
ing upon the status of PARCK control signal. A logic 4290121BI FC
38
"0" on B012 will cause odd parity to be generated
35 F
and inputted to the output data stream. Conversely,
a logic "1" on B012 will result in the generation of 0/R2 34 CWs'T"R
even parity that will be Inputted to the output data SEl 33 ENTX

stream. 32 i29Do
31 42900 Q

More versatility is provided in both the transmitter 30 TX/R '-'

(:;
and receiver by the addition of an external TTL clock B014 29 m
input allowing the bus Interface circuit to operate at B013 28 'PLi'
data rates from 0 to 1 megabits. The TTL external B012 27 BOOO
clock must be ten (10) times the data rate to insure B011 28 B001
no data ambiguity. B010 25 B002

B009 24 B003
The ARINC bus interface circuit is fully guaranteed BOOB 23 B004
to support the data rates of ARINC specification 429 B007 22 BOOB
over both the voltage (± 10%) and full military tem· 21 GND
perature range. It interfaces with TTL, CMOS or
NMOS support circuitry, and uses the standard
5-volt VCC supply.
 M~-~~-I~
(it HARRJSj
Preliminary Video Character Generator

Features
Pinout
• OPERATION (DOT CLOCK) FROM 1.0 TO 27 MHz
• DESIGNED TO INTERFACE WITH INTEL
~~
1
2
40 :J
39 :J
Vec
GRAPHE
8275 PROGRAMMABLE CRT CONTROLLER

·•
AD ( 3 3. :J EO

• DIRECTLY DECODES (FROM ON-CHIP ROM); "

.2 (
(
S
37 :J
38:JE6
E7

• ASCII 96 CHARACTER SET S3 ,

LO ,
3S~E5
34 £4
• 32 PSEUDO-GRAPHIC CHARACTERS
Le2 ~
7
• 33;~
• 10 OVERLAY PATTERNS Le,
LCD (
9

'0
32 E2

• EXPANDABLE CHARACTER TABLE EXEN ( 11

3' ~
30
~
EO

• 9 X 12 DOT MATRIX WITH DESCENDER CAPABILITY ROMOIS (: 12

eC6 c '3
29 :;
28:JRnn'
DOTCLK

• HANDLES VIDEO MODIFIERS; 27 ::J

ceLK

•
•
BLANK
ees ~
eC4
ee3
IS
C I.
" 26
25
:J
:J
vsp
lTEN

•
VIDEO
REVERSE VIDEO
SUPPRESS ee2
ee,
ceo
C 17
c
C 19
,. 2. :J
23 :J
RVV
iilK
22 :: VID2
• LIGHT ENABLE GND 20 21 VIOl

LCO-3 - LINE COUNT

CC0-6 - CHARACTER CODe

Description ROMOIS - ROM DISABLE

LTEN - LIGHT ENABLE
RVV - REVERSE VIDEO
The HS-3819 is a CMOS/LSI Video Character Generator designed to vsp -VIDEO SUPPRESS.
BlK - BLANK
help interface an Intel 8275 Programmable CRT Controller to a video
51-3 - SPECIAL FUNCTION
monitor. The character generator must be supplied with a clock frequency EXEN - E~PANSION ENABLE

of between 1 and 27 MHz which will be used as the dot clock. This signal e0-8 - EXPANSION INPUTS

GRAPHE - GRAPHICS ENABLE

is then divided by nine to form the character clock output needed by the ViR - WRITE
CRT Controller. The HS-3819 then converts character data into a video cs - CHIP SelECT
AO - AODR ESS 0
output signal, through use of an internal (ROM) character table. Stored in VIDl·2 - VIDEO OUTPUTS
this ROM are the standard 96 ASCII characters, 32 pseudo-graphic charac- RESET - RESET
OOTClK - DOT CLOCK
ters and 10 overlay patterns used to modify characters. Additional charac- celK - CHARACTER ClOCK

ters, if needed, can easily be decoded from an external memory field.

Standard Character Set Overlay Patterns Dot Matrix

0 1 2 3 4 S 6 7 CRISS CROSS X# CROSS HATCH
,-, 1
r-1
2 3 ,-,
4 5 6
r-1 ,-,
7
r-1
o NUll
£ SP 0 @ P
, UNDERLINE
- - HORIZONTAL STRIKE
THROUGH A B A
• "•
A A • A B A B A
•
, '" • 0lIf
I 1 A a a
P
q
CRISS CROSS
DIAGONAL STRIKE
X
/
,
2 ,
I
--. " 2 B R b r
DIAGONAL STRIKE
DIAGONAL STRIKE
/
/
2
3
,
• •
•i]o--:' *
3 3 C S C DASHED UNDERLINE
'·1
DASHED UNDERLINE
4 $ 4 0 T d I S 2
DASHED UNDERLINE
e u OPEN BOX • 3

•5>~c~
S % S E U 0
OPEN BOX 0 7
."

-
6 6 F f v
•
L...-l & V UNDERDOT
7 E3 7 G W 9 w
,
UNDERDOT
REVERSE DIAGONAL ,
, • • ~c
-.
8~ I 8 H X h REVERSE DIAGONAL
7

9 ~ ) 9 I Y i Y DOUBLE UNDERLINE
= •
X Z z •
A

A - *+ J
K
Z

[
j

I
-- .
B ; k
NOTES,
C I'D
I-D -
<
=
L·
'- I I 1. EACH ROW MAY HAVE DOTS
IN SET A OR SET B ONLY.
0 M ] m I
=. ~ 2. EACH CHARACTER MAY HAVE
E J: > N 1\ n DOTS IN NORMAL SET OR
OESCENOER SET ONLY.
F ~
= / ? 0 0 ¢
 GwG

For the custom, semicustom and rad hard products offered by CICD, any necessary screen-
ing or special product assurance testing is available. Class S and Class B military screening
is routinely performed. Fabrication lot integrity is maintained, and product traceability to
individual wafers is available.

CICD is a supplier to the most demanding high-reliability applications - specifically, for

strategic missiles, satellites and heart pacers. If needed, customers may obtain a fully custom
designed quality/reliability program to fit their unique requirements.
 Northeast Region 2600 Virginia Avenue
Suite 800
Washington, DC 20037
202-342-3900
Telecopier: 202-338-3878

5 Old Concord Road

Burlington, MA 01803
617-273-1020
TWX: 710-332-1074
Quip: 617-272-7956

106 Seventh Street

Garden City, NY 11530
516-747-6776
TWX: 510-220-1527

Southeast Region Suite 113

7040 Lake Ellenor Drive
Orlando, FL 32809
305-851-9450
Telex: 808819
Telecopier: 305-851-5141

Central Region Suite 704

2850 Metro Drive
Minneapolis, MN 55420
612-854-3224
TWX: 920-576-3418
Telecopier: 612-854-7359

Suite 110
17120 Dallas Parkway
Dallas, TX 75248
214-248-3239
TWX: 910-860-5446

Western Region Suite 320

1503 South Coast Drive
Costa Mesa,CA 92626
714-957-6557
TVVX: 910-595-1533
Telecopier: 714-957-6557

European SalesOffice Harris Semiconductor

P. O. Box 27
145 Farnham Road
Slough SL 1 4XD, England
011-447-5334666
Telex: 84B174 Harris G
TIm
 H M 65162 B

T
JT
'"':,"'X"_,,,
FAMILY:==:.J
0-
M -
PL -

S -
Digital
Memory

CICO
(1)
Programmable
Logic
PACKAGE-
1 -
1B -
3
4
Ceramic Dip
Brazed Seal
Epoxy Dip
Leadtess Carriers
T
PART NUMBER
15SXX
61 XX
63XX
64XX
-
-
-
-
PERFORMANCE
GRADE:
8 -

5-
High Speed
C - Relaxed
Very

CMOS Manchester
CMOS Microprocessor
CMOS ROM
CMOS Intetface Device
Specification
High Speed

TEMPERATURE
2
5
6
-550C to +125OC
coe to +700C
100% 250C Probe Idice On1vl
5 - Ceramic Substrate 65XX - CMOS RAM 8 Dash 8 Program
6 Slimline 65XXX - CMOS RAM 9 -400C to +850C
7 Mini Dip 66XX - CMOS PROM 9+ - -400C to +850C With Burn-In
9 Flat Pack 76XX - Bipolar PROM RH - Radiation Hardened
o Chip Form 92XXX - CMOS Module

M D 82C82

T
T
T
PACKAGE
TEMPERATURE TYPE DASH 8
RANGE P - Plastic
o - Ceramic
PROGRAM
C - Commercial
I - Industrial X - Unpackaged
Device PART
M - Military A - Leldless
X - 250C chip NUMBER
carrier 80CXX
82CXX -

As a service to users of High Rei products, Harris makes readily available via the high reliability DASH 8 program many products
from our product lines.

SPECIAL ORDERS
For best availability and price, it is urged that standard "Product Code" devices be specified which are available worldwide from
authorized distributors. Where enhanced reliability is needed, note standard "Dash 8" screening described in this Data Book.
Harris application engineers may be consulted for advice about suitability of a part for a given application.

If additional electrical parameter guarantees or reliability screening are absolutely required, a Request for Quotation and Source
Control Drawing should be submitted through the local Harris Sales Office or Sales Representative. Many electrical parameters
cannot be economically tested, but can be assured through design analysis, characterization. or correlation with other parameters
which have been tested to specification limits. These parameters are labeled "Sampled and guaranteed, but not 100% tested".
 EPOXY* LEADLESS MODULE
PART NUMBER CERDIP (Ag) CARRIER SUBSTRATE

CMOS SOCS6Family
80C86 DE FF EA -
82C82 52 7M LS -
82C55A 4H FD EG -
82C84A 4N 7W LS -
82C88 52 7M LS -
82C59A 1M FJ LX -
82C54 5F FG EH -
82C52 -- 1M - - -
HD-6406 4H FD EA -
80C88 DE FF EA -
82C84B 4N 7W LS -
1K RAM
HM-6508 5C 71 - -
HM-6518 5E 7D LA -
HM-6551 4M 3E - -
HM-6561 4N 7D LA -

4K RAM
HM-6504 5E 7D LB -
HM-6514 5E 7D LB -

CMOS Memory 16 RAM

HM-6516 5F 72 EC -
HM-65162 5F 72 EC -
HM-65172 5F 72 EC -

RAM Modules
HM-6564 - - - MA
HM-92560 - - - MD
HM-925JO - - - MF

• Epoxy (Ag) is the type of leadframe that is recommended. The Epoxy (Au) is an
emergency back-up when the silver type (Ag) is not available .

•• This part can only be built in Cerdip at this time. Other packages will be built after
the 82C52R is redesigned.
 EPOXY· LEADLESS MODULE
PART NUMBER CERDIP (Ag) CARRIER SUBSTRATE

Future Products
HM-65262 5M 7F - -
HM-65642 DD - ED -
HM-92562 - - - MH

Programmable Memories
HM-6641 DC, SF - LZ -
HM-6616 DC, SF - EC -
HM-6664 DD - ED -
,uProcessors&
Peripherels Microprocessors
HD-6120 5H FE - -
HD-6121 5H FD - -
HM-6100 5H FE - -
HM-6101 5H FE - -
Peripherals
HD-6431 4Z 7H LA -
HD-6432 4N 7D LA -
HD-6433 4Z 7H LA -
HD-6434 4K GB - -
HD-6436 5Z 7J - -
HD-6440 4N 7W LA -
HD-6495 4Z 7H LA -
Data Communications
HD-15530 4K 7C LX -
HD- 15531/15531 B 5H FE - -
HD-6408 4K 7C LX -
HD-6409 5Z 7M LS -
HD-6406 4H FE EA -
HD-6402 5H FD - -
HD-4702 4Z 7H LA -
• Epoxy (Ag) is the type of leadframe that is recommended. The Epoxy (Au) is an
emergency back-up when the silver type (Ag) is not available.
 PKG. LEAD DIM. DIM. DIM.

C
DIM.

0
DIM.

E ,
DIM. DIM. DIM. DIM.

L
DIM.

0
DIM.

S
DIM.

TYPE COUNT A B G H
"
16 140 016 .OOB .760 .265 290 .050 .090 .125 .020 .025 0"
4Z
MSI ~ .018 :ol2 790 .285 :J1O .070 :1iO .150 .040 .045 1"50

16 .140 .016 .008 .790 .285 .300 .050 .090 .125 .020 .025 0"
5C
LS' ~ 018 :oi2 760 .305 .320 070 11"0 .150 040 .045 150

4N 18 .140 .016 008 .885 .285 .300 050 090 .125 020 .040 0"
5E LSI m .018 0i2 .m .305 .320 070 .liO .150 040 .060 150

5Z.5M. ZO .140 .016 .008 940 .285 300 .050 .090 .125 .020 .020 0"
- - -- 4L LSI 110 .018 0i2 .970 .305 .320 .070 :liD .150 .040 .040 150

Z4 .150 .016 .008 1240 .285 300 .050 .090 .125 .020 .060 0"
I-E-I DC
SLIM 180 :oii :oi2 f270 305 .320 .070 ~ .150 :040 .090 150
C'1/_~ -,- -" NOTE: 11 Dimensionl'''; ~~NX.

21 All Dimenlionlin Inches

OJ
CERDIP .400

PKG. LEAD OIM. DIM. DIM. DIM. DIM.

,
DIM. DIM. DIM. DIM. DIM. DIM. DIM.

TYPE COUNT A B C 0 E G H L 0 S
"
22 .150 .016 .008 1055 .375 .395 .050 .090 .125 .020 .030 0"
4M
~ .018 .012 i085 .395 4i5 .070 m .150 .040 .050 1"50

NOTE; 11 Dimenlionl8re ~~~.

21 All oimenlionl In inches

a- -

c-#-I_,_
I-E-I
-"
--

PKG. LEAD DIM. DIM. DIM. DIM. DIM. DtM. DIM.

TYPE COUNT A B C 0 E S
"
24 150 016 008 124 .515 595 050 .090 125 020 .060 0"
5'
4< MSI 180 0i8 0i2 m .535 ill 070 :1iO .150 .045 090 ""1"50

1M 28 160 016 008 1.44 515 595 .050 090 125 .020 .060 0"
DO MSI '"i9O 0i8 0i2 147 535 :6i5 070 :liO :150 .060 090 ;SO
41-4.5H. 40 160 016 .OOB 2035 515 .595 050 090 .125 020 065 0"
DE MSI :200 0i8 1i12 2,075 535 ill 070 ~ .150 060 .095 150
NOTE; 11 Dimensions ere: M!!L.
MAX.
21 All Dimenslonlin inchel
71, 3L, 7W, 7V, 70, 7M, 7F, 7H, 7J

PKG. L.EAD DIM. DIM. DIM. DIM. DIM.

, DIM. DIM. DIM. DIM. DIM. DIM. DIM.
TYPE

71
7H
COUNT

,. A

126
140
B

01.
020
C

.008
0i2 7iO
D

760 246
2.5 310
F

290
G

050
070
H

.090
1iO
L

.150
.170
0

.020
.040
6

025
035
"
()O

;SO

7W.7V, 18 126 01. 008 900 245 290 OSO 090 lSO .020 040 ()O

70 140 020 ,012 .920 2.5 310 070 1iO m 040 060 "i5"O

a
7M,7F, 20 .130 01. 008 1,030 .250 290 .050 .090 150 .020 0.0 ()O
7J 145 .020 0i2 1""050 .270 ill .070 ill rn .040 :oao 1"50
-.- ~-
-,-I
c-;J_F- -"l
SI
EPOXY,400

PKG.
TYPE
LEAD
COUNT
DIM.
A
DIM.
8
DIM. DIM.

D ,
DIM. DIM.
F
I DIM.
G
DIM.

H
DIM. DIM.

0
DIM.

6
DIM.
C L
"
3'
22 . 140 01 • 008 1 10 .335 390 I .050 .090
~ ~ 025 ()O

:i7O 0i8 .012 ill 355 .410 070 110 170 040 045 150

FG,7Z,FJ,FO,FF,7C,FE

PKG. LEAD
COUNT
DIM. DIM. DIM.

C
DIM.
,
DIM. DIM.

F
DIM.

G
DIM.

H
DIM. DIM. DIM. DIM.
TYPE A B D L 0 6
"
7C. FG, 24 145 01. .008 1.24 540 .590 .050 .090 .150 020 .065 0°
7Z,GS 155 .020 m2 126 560 j""1Q .070 TiO 170 .040 :ass ;SO

28 145 .016 .008 154 540 590 .050 .090 lSO 020 .110 ()O
FJ
""i55 :020 012 i5'7 560 .610 .070 110 170 040 .130 ;SO
FE, FD, 40 145 01. .008 205 .540 .590 .050 .-90 150 020 .070 ()O
FF 155 020 012 2.07 .560 :610 .070 ~ 1'7'0 040 ,090 1SO
LB,LA,LS,LX,LZ,EC,ED,EA,EG,EH

PKQ. l.EAD DIM. DIM. DIM, DIM. DIM. DIM. DIM. DIM,
TYPE COUNT A 0 e 0
• F Q
"
LO
LA
10 .060
07i
020
rn
.060
m
.342
35i
.277
:m
~
.095
~
osc
~ .055

'0 .050 .020 .060 .342 .342 .060 .050 .040

LS
:m 0.30 .090 35i .m :oi5 iiC :065
'0 .050 .020 .060 '90 .390 .000 .050 .040
LX
,400 Ilq. 07li 0.30 .090 :m :ii'i 0.' BSC 055
,e ,050 .020 .060 ,442 .442 .000 .050 .040
LZ .4110 eq. :m Q.3O .090 .468 ill .096 sse .m
Ee, ED, .050 .020 .060 .645 .060 ,osa ,040
E" " m 030 ,090 iiO
4"
4ii .oii OSC :oii
EA 44 0'0 ,020 ~.o .•.• 3 .043 ,000 ,osa ,040
EO :m 0.30 .090 .662 :ill :oi5 ese ,055

I[[]]]]][]-r
..L
A
---.1
C

_ MODULE SUBSTRATE Im1 MODULE SUBSTRATE

64K CMOS RAM MODULE HM-6564 HM-92560, HM-92562

TYPICAL 32 PIN
lEADL.ESS CARAIER
PACKAGE, ONE OF
SIXTeEN

,040 ~Z,300 ;,008 AEF,,030TYP,I,90MAX, J'l~,

"'O;'D'OF-~==~~"x'l======:t
z
.160 r '~,l .
.04~2i~l[ I" .010 : ..::
MAX. .100!.OO8 1--1.310REF,---l

mil MODULE SUBSTRATE

HM-92570

,IoDDD TYPICAL 32 PIN

LEAD LESS CARRIER
PACKAGE, ONE OF
SIXTeEN

~O~hJDDDD
.090 MAX.
I

.110.!..010

.160±.04~
MAX,
09D
(MAX .

'==9-
1_- 1.310REF.---I
.016
MAX.
 TITI

Harris CMOS Products are available in chip form to the hybrid micro circuit designer.
The standard chips are DC electrically tested at +1250C to the data sheet limits for the
commercial device and are 100% visually inspected. Packaging for shipment consists of
waffle pack carriers plus an anti-static cushioning strip for extra protection.

The hybrid industry has rapidly become more diversified and stringent in its requirements
for integrated circuits. To meet these demands Harris has several options additional to
standard chip processing available upon request at extra cost. For more information consult
the nearest Harris Sales Office.

Standard and special chip sales are direct factory order only. The minimum order on all
sales is $250.00 per line item. Contact the local Harris Sales Office for pricing and delivery
on special chip requirements.

Dimensions: All chip dimensions nominal with a tolerance of ±.003". Maximum chip
th ickness is .023".
Bonding Pads: Minimum bonding pad size is .004" x .004" unless otherwise specified.
ELECTRICAL INFORMATION

Die substrate must be electrically connected to VCC through conductive

die attach, to assure proper electrical operating characteristics.

DICE GEOMETRIES AND DIMENSIONS

May be obtained by contacting the factory of your local Harris Sales Office.

PR~~::a:rriS)

FAMILY:
M =
HMO
Jj
Memory
I 6508
(
MODEL NUMBER

TEMPERATURE:
6 =
T
6

250C Probe'
x X 82C82
II ·Contact Harris for
availability of -2
I-550C to +1250C)
dice.

D = Digital
Sector Alpha-Numeric Product Index 12-3

Harris Sales Locations 12-8

 Alpha-Numeric Product Index
Analog

HA-1608 +10V Adjustable Voltage Reference

HA-2400/04/05 PRAM, Four Channel Operational Amplifiers
HA-2420/25 Fast Sample and Hold Operational Amplifiers
HA-2420/02/05 Precision High Slew Rate Operational Amplifiers
HA-2500/02/05 Precision High Slew Rate Operational Amplifiers
HA-2510/12/15 High Slew Rate Operational Amplifiers
HA-2520/22/25 Uncompensated High Slew Rate Operational Amplifiers
HA-2539 Super High Slew Rate Wideband Operational Amplifiers
HA-2540 Ultra High Slew Rate Operational Amplifiers
HA-2600/02/05 Wideband, High Impedance Operational Amplifiers
HA-2620/22/25 Very Wideband, Uncompensated Operational Amplifiers
HA-2630/35 High Performance Current Booster
HA-2640/45 High Voltage Operational Amplifiers
HA-2650/55 Dual High Performance Operational Amplifiers
HA-2720/25 Wide Range Programmable Operational Amplifiers
HA-2730/35 Wide Range Dual Programmable Operational Amplifiers
HA-2740 Quad Programmable Operational Amplifiers
HA-4156 High Performance Quad Operational Amplifiers
HA-4600/02/05 High Performance Quad Operational Amplifiers
HA-4620/22/25 Wideband, High Performance Quad Operational Amplifiers
HA-4741 Quad Operational Amplifier
HA-4900/0205 Precision Quad Comparators
HA-5033 High-Speed Current Buffer
HA-5062 Dual Low Power, JFET Input Operational Amplifier
HA-5064 Low Power, JFET Input Quad Operational Amplifier
HA-5082 Dul JFET Input Operational Amplifer
HA-5084 JFET Input Quad Operational Amplifier
HA-5100/05 Wideband, J F ET Input Operational Amplifiers
HA-5110/15 Wideband, JFET Input, Uncompensated Operational Amplifiers
HA-5130/35 Precision Operational Amplifiers
HA-5141/42/44 Power Operational Amplifier, Single, Dual & Quad
HA-5160/62 Wideband, JFET Input, High Slew Rate, Uncompensated
Operational Amplifiers
HA-5170 Precision J F ET Input Operational Amplifiers
HA-5180/5180A Ultra Low IBIAS JFET Input Precision
Operational Amplifier
HA-5190/95 Wideband, Fast Settling Operational Amplifiers
HA-5320 High Speed Precision Monolithic Sample and Hold Amplifier
HC-5116A/5156A Monolithic CODECS (Preliminary)
HC-5502 SLlC-LC Subscriber Line Interface Circuit (PBX)
HC-5504 SLIC-LC Subscriber Line Interface Circuit (PBX)
HC-5510/5511 Monolithic CODECs (Preliminary)
HC-5512/5512A PCM Monolithic Filter
HC-5531 Automatic Line Balance Network
HC-55536 Decode Digital Continuously Variable Slope
Delta Modulator (CVSD)
Encode and Decode all Digtal Continuously
Variable Slope Delta Modulator (CVSD)
HD-0165 Keyboard Encoder
HI-200 Dual SPST CMOS Analog Switch
HI-201 Quad SPST CMOS Analog Switch
HI-201HS High Speed Quad SPST CMOS Analog Switch
HI-300 Dual SPST CMOS Analog Switch
HI-301 SPDT CMOS Analog Switch
HI-302 Dual DPST CMOS Analog Switch
HI-303 Dual SPDT CMOS Analog Switch
HI-304 Dual SPST CMOS Analog Switch
HI-305 SPDT CMOS Analog Switch
HI-306 Dual DPST CMOS Analog Switch
HI-307 Dual SPDT CMOS Analog Switch
HI-3B1 Dual SPST CMOS Analog Switch
HI-3B4 Dual DPST CMOS Analog Switch
HI-3B7 SPDT CMOS Analog Switch
HI-390 Dual SPDT CMOS Analog Switch
HI-506/507 Single 16/Differential B Channel CMOS Analog Multiplexers
H 1-506A/507 A 16 Channel CMOS Analog Multiplexers with
Overvoltage Protection
H 1-506 Ll507 L Latched, 16/B Channel Analog Multiplexer
HI-50B/509 Single B/Differential 4 Channel CMOS Analog Multiplexers
H 1-50BA/509A B Channel CMOS Analog Multiplexers with
Overvoltage Protection
H 1-50B Ll509 L Latched, B/4 Channel Analog Multiplexer
HI-516 16 Channel/Differential B Channel CMOS High Speed
Analog Multiplexer
HI-51B B Channel/Differential 4 Channel CMOS High Speed
Analog Multiplexer
HI-524 4 Channel Video Multiplexer
HI-539 Monolithic, Four Channel, Low Level, Differential
Multiplexer
HI-562A 12 Bit High Speed Monolithic Digital-to-Analog Converter
HI-565A High Speed Monolithic Digital-to-Analog Converter
with Reference
Fast, Complete 12 Bit A-to-D Converter with
P Interface
High Speed, Complete 12-Bit A-to-D Converter
with P Interface
HI-1B1BA/1B2BA Low Resistance B Channel CMOS Analog Multiplexer
HI-5040 Low Resistance SPST Switch
HI-5041 Low Resistance Dual SPST Switch
HI-5042 Low Resistance SPDT Switch
HI-5043 Low Resistance Dual SPDT Switch
HI-5044 Low Resistance DPST Switch
HI-5045 Low Resistance Dual DPST Switch
HI-5046 Low Resistance DPDT Switch
HI-5046A Low Resistance DPDT Switch
HI-5047 Low Resistance 4PST Switch
HI-5047A Low Resistance 4PST Switch
HI-504B Low Resistance Dual SPST Switch
HI-5049 Low Resistance Dual DPST Switch
HI-5050 Low Resistance SPDT Switch
HI-5051 Low Resistance Dual SPDT Switch
HI-5610 10 Bit High Speed Monolithic Digital-to-Analog Converter
H 1-5618A/18B 8 Bit High Speed Digital-to-Analog Converters
HI-5660 High Speed Monolithic D-to-A Converter
HI-5680 12 Bit Low Cost Monolithic D-to-A Converter
HI-5685 High Performance Monolithic 12 Bit D-to-A Converter
HI-5687 Wide Temperature Range Monolithic 12 Bit D-to-A
Converter
HI-5712/12A High Performance 12 Bit Analog-to-Digital Converters
HI-5900 Analog Data Acquisition Signal Processor
HI-5901 Analog Data Acquisition Signal Processor
HI-7541 12 Bit Multiplying Monolithic Digital-to-Analog Converter
HI-DAC801 12 Bit High Speed Monolithic Digital-to-Analog Converter
HI-DAC16B/C 16 Bit D-to-A Converter
HV-1000/1000A Single-Phase Induction Motor Energy Saver
LF347 Wideband Quad JFET Input Operational Amplifiers
LF353 Wideband Dual J F ET Input Operational Amplifier
LF355 Series Monolithic JFET Input Operational Amplifiers
LF356 Series Wideband Monolithic JFET Input OPerational Amplifiers
LF357 Series Decompensated Wideband Monolithic JFET Input
Operational Amplifiers
LM108/308 Operational Amplifiers
L M 108A/308A Operational Amplifiers
LM118/318 Operational Ampl ifiers
LM143/343 High Voltage Operational Amplifiers
LM 143A/343A High Voltage Operational Amplifiers
LM146/346 Programmable Quad Operational Amplifiers
LM148/348 Quad 741 Operational Amplifiers
LM148A/348A Quad 741 Operational Amplifiers
LM 1558A/1458A Dual Operational Amplfiers
LM2908 Quad Operational Amplifiers
LM4250/4250C Programmable Operational Amplifiers
HD-6600 Quad Power Strobe
HM-0104 10 X 4 Diode Matrix
HM-0168 6 X 8 Diode Matrix
HM-0186 8 X 6 Diode Matrix
HM-0198 9 X 8 Diode Matrix
HM-0410 4 X 10 Diode Matix
HM-7602/03 32 X 8 Bit Generic PROM
HPROM-0512 64 X 8 HPROM
HM-7610/11 256 X 4 Bit Generic PROM
HM-7610A/11A 256 X 4 Bit High Speed Generic PROM
HM-7610B/11B 256 X 4 Bit Ultra High Speed Generic PROM
HM-7620/21 512 X 4 Bit Generic PROM
HM-7620A/21A 512 X 4 Bit High Speed Generic PROM
HM-7620B/21B 512 X 4 Bit Ultra High Speed Generic PROM
HM-7640/41 512 X 8 Bit Generic PROM (24-Pin)
HM-7640A/41A 512 X 8 Bit High Speed Generic PROM (24-Pin)
HM-7649 512 X 8 Bit Generic PROM (20-Pin)
HM-7649A 512 X 8 Bit High Speed Generic PROM (20-Pin)
HM-7642/43 1024 X 4 Bit Generic PROM
HM-7642A/43A 1024 X 4 Bit High Speed Generic PROM
HM-7642B/43B 1024 X 4 Bit Ultra High Speed Generic PROM
HM-7681 1024 X 8 Bit Generic PROM
HM-7681A 1024 X 8 Bit High Speed Generic PROM
HM-7685 2048 X 4 Bit Generic PROM
HM-7685A -2048 X 4 Bit High Speed Generic PROM
HM-76161 2048 X 8 Bit Generic PROM
HM-76161A 2048 X 8 Bit High Speed Generic PROM
HM-76165 4096 X 4 Bit Generic PROM
HM-76321 4096 X 8 Bit Generic PROM
HM-76641 8192 X 8 Bit Generic PROM
HPL-77153 20-Pin Field Programmable Logic Array
HPL-77209 20-Pin Field Programmable Array Logic (Active Low Outputs)
HPL-77215 20-Pin Field Programmable Array Logic (Active
Low Outputs)
20-Pin Field Programmable Array Logic (Programmable
Output Polarity)
20-Pin Field Programmable Array Logic (Active
Low Dedicated Outputs)
20-Pin Field Programmable Array Logic (Active
High Dedicated Outputs)
20-Pin Field Programmable Array Logic (Enhanced
HPL-77317)
20-Pin Field Programmable Array Logic (Enhanced
HPL-77318)
M38510120701BEB 32 X 8 Open Collector QPL 1 PROM
M38510/20702BEB 32 X 8 Three State QP L 1 PROM
M38510/201 01 BJB 64 X 8 Open Collector QPL 1 PROM
M38510/20301 BEB 256 X 4 Open Collector QPL 1 PROM
M38510/20302BEB 256 X 4 Three State QPL 1 PROM
M38510/20401 BEB 512 X 4 Open Collector QPL 1 PROM
M3851 0/20402B EB 512 X 4 Three State QPL 1 PROM
M3851 0/20801 BJB 512 X8 Open Collector QPL 1 PROM
M3851 0/20802BJ B 512 X 8 Three State QPL 1 PROM
M38510/20602BVB 512X8ThreeStateQPL1 PROM
M3851 0/20904BJ B 1024 X 8 Three State QPL 1 PROM
M38510/20902BVB 2048 X 4 Three State QPL 1 PROM
M38510/21002BJB 2048 X 8 Three State QPL 1 PROM
HD-15530 Manchester Encoder-Decoder
HD-15531 Manchester Encoder-Decoder
HD-4702 Programmable Bit Rate Generator
HD-6101 Parallel Interface Element
HD-6120 12 Bit High Performance Microprocessor
HD-6121 I/O Control Ier
HD-6402 LSI Universal Asynchronous Receiver Transmitter
HD-6406 Programmable Asynchronous Communication Interface
HD-6408 Asynchronous Manchester Adapter
HD-6409 Manchester Encoder-Decoder
HD-6431 Hex Latching Bus Driver
HD-6432 Hex Bi-directional Bus Driver
HD-6433 Quad Bus Separator/Driver
HD-6434 Octal Resettable Latch
HD-6436 Octal Bus Buffer/Driver
HD-6440 Latch Decoder/Driver
HD-6495 Hex Bus Driver
HM-6100 12 Bit Static Microprocessor
HM-6504 4K X 1 Synchronous RAM
HM-6508 1K X 1 Synchronous RAM
HM-6514 1K X 4 Synchronous RAM
HM-6516 2K X 8 Synchronous RAM
HM-65162 2K X 8 Asynchronous RAM
HM-65172 2K X 8 Asynchronous RAM
HM-6518 1K X 1 Synchronous RAM
HM-65262 16K X 1 Asynchronous RAM
HM-6551 256 X 4 Synchronous RAM
HM-6561 256 X 4 Synchronous RAM
HM-6564 64K Synchronous RAM Module
HM-6616 2K X 8 Fuse Link PROM
HM-6641 512 X 8 PROM
HM-6664 8K X 8 Fuse Link PROM
HM-92560 256K Synchronous RAM Module
HM-92570 256K Synchronous RAM Module
HPL- 16LC8 Programmable Logic
HPL-16RC4 Programmable Logic
HPL-16RC6 Programmable Logic
HPL-16RC8 Programmable Logic
80C86 16 8it Microprocessor
80C88 8 Bit Microprocessor
82C37A High Performance Programmable DMA Controller
82C52 Full Duplex UART
82C54 Programmable Interval Timer
82C55A Programmable Peripheral Interface
82C59A Priority Interrupt Controller
82C82 Octal Latch
82C83 Octal Latching Inverting Bus Driver
82C84A Clock Generator/Driver
82C84B Clock Generator Driver
82C86 Octal Bus Transceiver
82C87 Octal Bus Transceiver
82C88 Bus Controller
82C89 Bus Arbiter
 Suite B120 Harris-Matra-Harris GMBH
883 Stierlin Road Walsroderstrasse71
Suite 215 Mt. View, CA 94043 0-3012 Langenhagen1
3890 West Commercial Blvd. (415) 964-6443 Tel: 49-511-737037
Ft. Lauderdale, FL 33309 TWX: 9230474 HM HH 0
(305) 739-0016 Suite 205
6400 CanogaAvenue
Suite 400 Woodland Hills, CA 91367
875 Johnson Ferry Road (213) 992-0686
Atlanta, GA 30342
(404) 256-4000 33919 9th Avenue South Transistor Vetriebsgesellschaft
Federal Way, WA 98003 mbH & Co. KG.
Suite 308 (206) 838-4878 Auhofstr. 41A
1 Burlington Woods Drive A-1130 Wien
Burlington, MA 01803 Suite 8 Tel: 43-0222-82-94-01
(617) 273-5942 2005 Broadway TWX: 133738 TVGWN
Vancouver, WA 98663
P. O. Box 31747 (206) 696-0043
Raleigh, NC 27622
Betea S.A
Suite 1101 755 Chausseede Louvain
996 Old EagleSchool Road B-1140 Brussels
Wayne, PA 19087 Tel: 32-2-7368050
(215) 687-6680 TWX 23188

Suite 273
555 Broadhollow Road Harris-MHS GMBH
Melville, L. I., NY 11747 Headquarters Ditz Schweitzer A. S.
(516) 249-4500 Erfurterstrasse 29 Vallensbaekvej 41
8057 Eching DK-2600 Glostrup
West Germany Tel: 45-2-453044
TEL: 49-89-319-1035 TWX: 33257
Suite 300 TWX: 5-213-866
6400 Shafer Court
Rosemont, IL 60018
(312) 692-4960 Yleiselektronikka OY
Atomitie 5 B (P.O. Box 33)
Suite 101
SF-00370 Helsinki 37
1717 East 116th Street
Tel.: 358-0-90-562-1122
Carmel, IN 46032 Harris Systems Ltd.
(317) 844-8011 Harris Semiconductor Div.
153 Farnham Road
Suite 703 Slough SL1 4XD Matra-Harris Semiconductor
2850 Metro Drive Tel: 44-753-34666 Harris S. A
Minneapolis, MN 55420 TWX: 848174 Harris Semi. Division
(612) 854-3558
6 Av Charles de Gaulle
F-78150 Le Chesnay
Suite 110
Tel: 33-3-9548000
17120 Dallas Parkway Harris Italiana, Inc. TWX: 696514
Dallas, TX 75248 20092 Cinisello Balsamo (Milano)
(214) 248-3237 Via Fratelli Cracchi 48 Matra Harris Semiconductor
Tel 39-2-6187249/6188282 B.P.942
TWX: 311164 Agerisi Nates Cedex
Suite 250 Tel: 33-40-490820
1717 E Morten Avenue TWX: 711930
Phoenix, AZ 85020
(602) 870-0080 Harris-Matra Semiconductors
Deutschland GmbH
Suite 320 Erfurterstrasse 29
1503 South Coast Drive 8057 Eching
Costa Mesa,CA 92626 Tel: 49-89-319-1035
(714) 540-2176 TWX: 5-213-866
12-8