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Homework #0: Inverter Sample: ECE 126 Homework #0 Page 1 of 7

This document describes the design and simulation of a CMOS inverter. It includes the schematic, layout, LVS matching between the schematic and layout, and transient simulations to verify functionality and measure propagation delay. The PMOS and NMOS are sized to make the rise and fall times equal. Calculations show the inverter layout occupies an area of 149.04um2.

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Mostafa M. Sami
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73 views7 pages

Homework #0: Inverter Sample: ECE 126 Homework #0 Page 1 of 7

This document describes the design and simulation of a CMOS inverter. It includes the schematic, layout, LVS matching between the schematic and layout, and transient simulations to verify functionality and measure propagation delay. The PMOS and NMOS are sized to make the rise and fall times equal. Calculations show the inverter layout occupies an area of 149.04um2.

Uploaded by

Mostafa M. Sami
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd
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Homework #0: Inverter Sample

Thomas Farmer

ECE 126

Professor M.E.Zaghloul

October 16, 2007

ECE 126 Homework #0 Page 1 of 7


Author: Thomas Farmer
1. Draw the schematic and layout of a CMOS inverter using the CADENCE tool. Size the
transistors to make tpHL=tpLH. Calculate the area of the layout

Schematic:

Fig 1.1 – Inverter Schematic, PMOS 2.4u/.6u, NMOS 1.5/.6u

Test Bench:

Fig 1.2 – Inverter Test Bench, CL=10pF, VPULSE 0 to 5V, width=25us, period=50us

ECE 126 Homework #0 Page 2 of 7


Author: Thomas Farmer
Layout and Extracted Views:

Fig 1.3a – Inverter Layout Fig 1.3b – Extraction of Layout

LVS Report:

@(#)$CDS: LVS.exe version 5.1.0 09/12/2006 23:55 (cicsun11) $

Command line: /apps/cadence2005/ic5141usr4/tools/dfII/bin/32bit/LVS.exe -dir


/home/grad/tfarmer/ece126/LVS -l -s -t /home/grad/tfarmer/ece126/LVS/layout
/home/grad/tfarmer/ece126/LVS/schematic
Like matching is enabled.
Net swapping is enabled.
Using terminal names as correspondence points.
Compiling Diva LVS rules...

Net-list summary for /home/grad/tfarmer/ece126/LVS/layout/netlist


count
4 nets
4 terminals
1 pmos
1 nmos

Net-list summary for /home/grad/tfarmer/ece126/LVS/schematic/netlist


count
4 nets
4 terminals
1 pmos
1 nmos

Terminal correspondence points


N3 N4 VIN
N2 N3 VOUT
N1 N1 gnd!
N0 N0 vdd!

Devices in the rules but not in the netlist:


cap nfet pfet nmos4 pmos4

ECE 126 Homework #0 Page 3 of 7


Author: Thomas Farmer
The net-lists match.

layout schematic
instances
un-matched 0 0
rewired 0 0
size errors 0 0
pruned 0 0
active 2 2
total 2 2

nets
un-matched 0 0
merged 0 0
pruned 0 0
active 4 4
total 4 4

terminals
un-matched 0 0
matched but
different type 0 0
total 4 4

Probe files from /home/grad/tfarmer/ece126/LVS/schematic

devbad.out:

netbad.out:

mergenet.out:

termbad.out:

prunenet.out:

prunedev.out:

audit.out:

Probe files from /home/grad/tfarmer/ece126/LVS/layout

devbad.out:

netbad.out:

mergenet.out:

termbad.out:

prunenet.out:

prunedev.out:

audit.out:

Table 1.1 – LVS Report indicating match between Schematic and Layout

ECE 126 Homework #0 Page 4 of 7


Author: Thomas Farmer
Simulations:

Fig 1.4a – Transient Simulation of Inverter (Fig 1.2) to show functionality, Total sim. time = 150us

Fig 1.4b – Transient Simulation of Inverter (Fig 1.2) to show rise time, Total sim. time = 150us, Rise Time = 112ns

Fig 1.4c - Note: show VTC Graph in this section as well

ECE 126 Homework #0 Page 5 of 7


Author: Thomas Farmer
Calculations/Explanations:

To make tpLH=tpHL the PMOS of the inverter was sized to: W/L=2.4um/.6um. The NMOS of the
inverter was sized to: W/L=1.2um/.6um. The determination of this size was shown in Fig 1.4c.

The total area utilized in the layout of the inverter is: 7.2um x 20.7um = 149.04um 2. The
determination of this area was shown in Fig 1.3a.

ECE 126 Homework #0 Page 6 of 7


Author: Thomas Farmer
2. Start Each Question on New Page.

 Use Header/Footer to ensure your name is on every page


 Attempt to print your report in color, double sided.
 If color is not available, black and white is acceptable as long as contrast on pictures is
adjusted to show salient details.
 Include Schematic, Test Benches, Functionality simulations, layout (if asked), LVS (if
layout is performed), for all questions.
 Never resize a picture so small that details of importance (numbers, measurements, etc.)
cannot be read.
 If a crucial # is unreadable, no matter what size the picture is, be sure to use the caption
under the picture to emphasize it.
 If LVS is suspected to have been falsified, you may be required to show results to GTA on
your workstation.

ECE 126 Homework #0 Page 7 of 7


Author: Thomas Farmer

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