INDEX

S.NO EXPERIMENT NAME DATE OF DATE OF REMARK

EXPERIMENT SUBMISSION & SIGN

1.

2.

3.

4.

5.

6.

7.

8.

9.

10.

11.

12.

13.

14.

15.

16.

1
 A
LAB REPORT
ON
MICROELECTRONICS AND VLSI DESIGN LAB
EC-1653

Submitted to:

Submitted by:

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

MOTILAL NEHRU NATIONAL INSTITUTE OF TECHNOLOGY
ALLAHABAD

2
 DATE- 08/01/2018
EXPERIMENT NO. : 01
AIM : To design and simulate different logic gates using Verilog HDL.
EDA TOOL USED :- Xilinx ISE Design Suit 14.4
METHODOLOGY :-
LOGIC GATE :- In electronics, a logic gate is a device which performs logical operation on
one or more logical inputs and produces a single logical output. NAND Gate and NOR Gate
are universal gates.
AND GATE :- Output of a AND gate is logic high if all the inputs are set (logic high).
Otherwise output is logic low.
OR GATE :- Output of a OR gate is logic high if any one of the inputs is set (logic high). If
all the inputs are clear then the output is logic low.
NAND GATE :- Output of a NAND gate is logic low if all the inputs are set (logic high).
Otherwise output is logic high.
NOR GATE :- Output of a NOR gate is logic low if any one of the inputs is set (logic high).
If all the inputs are clear then the output is logic high.
XOR GATE :- If odd number of inputs are set then the output is logic high, otherwise
output is logic low.
XNOR GATE :-
If odd number of inputs are set then the output is logic low, otherwise output is logic high.

BOOLEAN EXPRESSIONS AND SYMBOLS:

AND gate: OR gate:

Boolean algebra: Y=A.B Boolean algebra: Y=A+B

3
XNOR gate: NAND gate:

Boolean algebra: Y=AʘB Boolean algebra: Y=

NOR gate: XOR gate:

Boolean algebra: Y= Boolean algebra: Y=A B

Circuit Diagrams of logic gates
Table 1.1 Truth table for logic gates

INPUTS OUTPUTS
A B And Or Nand Nor Xor Xnor

0 0 0 0 1 1 0 1
0 1 0 1 1 0 1 0
1 0 0 1 1 0 1 0
1 1 1 1 0 0 0 1

GATE LEVEL:
VERILOG CODE :-
`timescale 1ns / 1ps
module logic_gates(
output And_op,Or_op,Nand_op,Nor_op,Xor_op,Xnor_op,
input a,b);

4
and a1(And_op,a,b);
xor a2(Xor_op,a,b);
nand a3(Nand_op,a,b);
or a4(Or_op,a,b);
nor a5(Nor_op,a,b);
xnor a6(Xnor_op,a,b);
endmodule

DATA FLOW:
VERILOG CODE :
`timescale 1ns / 1ps
module data( output y1,y2,y3,y4,y5,y6,y7,y8,
input a,b);
assign y1=a&b; //and gate
assign y2=~y1; //nand gate
assign y3=a|b; //or gate
assign y4=~y3; //nor gate
assign y5=a^b; //xor gate
assign y6=~y5; //xnor gate
assign y7=~a; //not gate
assign #100 y8=a; //buffer
endmodule

BEHAVIOR LEVEL :
VERILOG CODE:
module exp1
(input a,
input b,
output reg o1,
output reg o2,
output reg o3,
output reg o4,

5
output reg o5,
output reg o6);

always @(a or b)
case({a,b})
2'b00 : begin
o1 = 0;
o2 = 1;
o3 = 0;
o4 = 1;
o5 = 0;
o6 = 1;
end
2'b01 : begin
o1 = 0;
o2 = 1;
o3 = 1;
o4 = 0;
o5 = 1;
o6 = 0;
end
2'b10 : begin
o1 = 0;
o2 = 1;
o3 = 1;
o4 = 0;
o5 = 1;
o6 = 0;
end
2'b11 : begin

6
o1 = 1;
o2 = 0;
o3 = 1;
o4 = 0;
o5 = 0;
o6 = 1;
end
endcase
endmodule

RTL SCHEMATIC :

RTL View of logic gates

TEST BENCH :
module exp1test;
// Inputs
reg a;
reg b;
// Outputs
wire o1;
wire o2;

7
wire o3;
wire o4;
wire o5;
wire o6;
// Instantiate the Unit Under Test (UUT)
exp1 uut (
.a(a),
.b(b),
.o1(o1),
.o2(o2),
.o3(o3),
.o4(o4),
.o5(o5),
.o6(o6)
);
initial begin
// Initialize Inputs
a = 0;b = 0;
#100;
a = 0;b = 1;
#100;
a = 1;b = 0;
#100;
a = 1;b = 1;
#100;
// Wait 100 ns for global reset to finish
#100;
end
endmodule

8
OUTPUT :

Fig 1.7 Output waveform of logic gates

RESULT:- Different logic gates are implemented using gate level modeling and
operations are verified by simulation.

9
 DATE- 08/01/2018

EXPERIMENT NO 02
AIM: To design and simulate half and full adder, half and full subtractor using Verilog
HDL.

TOOLS: Xilinx ISE DESIGN SOFTWARE.

METHODOLOGY: Half adder is a circuit that adds single binary digits A and B. It has
two outputs sum(S) and carry(C). Sum represents the sum of two binary digits and is
represented by A xor B. Carry represents an overflow into the next digit of a multi-digit
addition . The value of sum in decimal system is 2C+S.
Half subtractor is a circuit that subtracts two bits. It has two inputs, the minuend A and
subtrahend B and two outputs the difference D and borrow out Bout. The borrow out signal is
set when the subtractor needs to borrow from the next digit in a multi-digit subtraction. That
is , Bout=1 when A<B. Since A and B are bits, Bout =1 if and only if A=0 and B=1.
Full adder adds binary numbers and accounts for values carried in as well as out. A one-bit
full adder adds three one-bit numbers, often written as A,B and Cin. A and B are the
operands, and Cin is a bit carried in from the previous less-significant stage. The full adder is
usually a component in a cascade of adders, which add 8,16,32 etc. bit binary number.
Full subtractor is a combinational circuit which is used to perform subtraction of three input
bits: the minuend A, subtrahend Y, and borrow Bin. The full subtractor generates two output
bits: the difference D and borrow out Bout. Bin is set when the previous digit borrow from A.
Thus, Bin is also subtracted from A as well as the subtrahend B. Or in symbol A-B-Bin. Like
the full subtractor generates a borrow out when it needs to borrow from the next digit. Since
we are subtracting A by B and Bin, a borrow out needs to be generated when A<B+Bin.
When a borrow out is generated, 2 is added in the current digit. Therefore D=A-B-
Bin+2Bout.

CIRCUIT DIAGRAM AND TRUTH TABLE:

S=A xor B
C=A and B

Fig 2.1 Gate representation of half adder

10
 Table 2.1 Truth table of half adder
Input A Input B Sum S Carry C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

S=A xor B xor Cin

Cout = AB+ Cin (A xor B)

Fig 2.2 Gate representation of full adder

Table 2.2 Truth table of full adder
Input A Input B Input Cin Sum S Carry Cout
0 0 0 0 1
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

D= A xor B
B = (not A) and B

Fig 2.3 Gate representation of half subtractor

11
 Table 2.3 Truth table of half subtractor
Input A Input B Difference D Borrow B
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

D= A xor B xor Borin

Borou= AB’+ Borin(A xor B)’

Fig 2.4 Gate representation of full subtractor

Table 2.4 Truth table of full subtractor
Input A Input B Input Borin Difference D Borrow Borou
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

HALF ADDER:
VERILOG CODE:
GATE LEVEL:
module ha1(
input a,
input b,
output s,
output c
);
xor(s,a,b);
and(c,a,b);
endmodule
DATA FLOW:
12
module ha2(
input a,
input b,
output s,
output c );
assign s=a^b;
assign c=a&b;
endmodule
BEHAVIOURAL LEVEL:
module ha3(
input a,
input b,
output reg s,
output reg c );
always@(a,b)
begin
case({a,b})
2'b00: begin s=0;c=0; end
2'b01: begin s=1;c=0; end
2'b10: begin s=1;c=0; end
2'b11: begin s=0;c=1; end
endcase
end
endmodule
RTL:

13
 Fig 2.5 RTL of half adder
TEST BENCH:
a = 0;b = 0;#100;
a = 0;b = 1;#100;
a = 1;b = 0;#100;
a = 1;b = 1;#100;
OUTPUT WAVEFORM:

Fig 2.8 Output waveform for half adder

HALF SUBTRACTOR:
VERILOG CODE:
GATE LEVEL:
module hs1(
input x,
input y,
output b,
output d
);
wire w;
xor(d,x,y);
not(w,x);
and(b,w,y);
endmodule
DATA FLOW LEVEL:
module hs2(

14
input x,
input y,
output b,
output d
);
assign d=x^y;
assign b=(!x)&y;
endmodule
BEHAVIOURAL LEVEL:
module hs3(
input x,
input y,
output reg b,
output reg d );
always@(x,y)
begin
case({x,y})
2'b00: begin b=0;d=0; end
2'b01: begin b=1;d=1; end
2'b10: begin b=0;d=1; end
2'b11: begin b=0;d=0; end
endcase
end
endmodule
RTL:

15
 Fig 2.9 RTL of half subtractor

TEST BENCH:
x = 0;y = 0;#100;
x = 0;y = 1;#100;
x = 1;y = 0;#100;
x = 1;y = 1;#100;
OUTPUT WAVEFORM:

Fig 2.12 Output waveform for half subtractor

FULL ADDER:
VERILOG CODE:
GATE LEVEL:
module fa1(
input a ,
input b,
input ci,
output s,
output c
);
wire p,q,r;
xor(p,a,b);
xor(s,p,ci);
and(q,p,ci);
and(r,a,b);
or(c,q,r);

16
endmodule
DATA FLOW:
module fa2(
input a,
input b,
input ci,
output s,
output c );
assign s=a^b^ci;
assign c=(ci&(a^b))|(a&b);
endmodule
BEHAVIOURAL LEVEL:
module ha3(
input a,
input b,
input ci,
output reg s,
output reg c
);
always@(a,b,ci)
begin
case({a,b,ci})
3'b000: begin s=0;c=0; end
3'b001: begin s=1;c=0; end
3'b010: begin s=1;c=0; end
3'b011: begin s=0;c=1; end
3'b100: begin s=1;c=0; end
3'b101: begin s=0;c=1; end
3'b110: begin s=0;c=1; end
3'b111: begin s=1;c=1; end
endcase
end

17
endmodule
RTL :

Fig 2.13 RTL of full adder for gate level

TEST BENCH:
a = 0;b = 0; ci = 0;#100;
a = 0;b = 0; ci = 1;#100;
a = 0;b = 1; ci = 0;#100;
a = 0;b = 1; ci = 1;#100;
a = 1;b = 0; ci = 0;#100;
a = 1;b = 0; ci = 1;#100;
a = 1;b = 1; ci = 0;#100;
a = 1;b = 1; ci = 1;#100;
OUTPUT WAVEFORM:

Fig 2.16 Output waveform of full adder

FULL SUBTRACTOR:
VERILOG CODE:
GATE LEVEL:
module fs1(
input x,

18
input y,
input z,
output d,
output b
);
wire p,q,r,s,t,m,n,u,v;
xor(p,y,z);
not(q,x);
not(r,p);
or(m,y,z);
and(n,y,z);
and(u,q,m);
or(b,u,n);
and(s,q,p);
and(t,x,r);
or(d,s,t);
endmodule
DATA FLOW:
module fs2(
input x,
input y,
input z,
output b,
output d );
assign b=((!x)&(y+z))+(y&z);
assign d=((!x)&(y^z))+(x&(!(y^z)));
endmodule
BEHAVIOURAL LEVEL:
module fs3(
input x,
input y,
input z,

19
output reg b,
output reg d
);
always@(x,y,z)
begin
case({x,y,z})
3'b000:begin b=0;d=0; end
3'b001:begin b=1;d=1; end
3'b010:begin b=1;d=1; end
3'b011:begin b=1;d=0; end
3'b100:begin b=0;d=1; end
3'b101:begin b=0;d=0; end
3'b110:begin b=0;d=0; end
3'b111:begin b=1;d=1; end
endcase
end
endmodule

RTL:

Fig 2.17 RTL of full subtractor

TEST BENCH:
x = 0; y = 0; z = 0; #100;
x = 0; y = 0; z = 1; #100;
x = 0; y = 1; z = 0; #100;
x = 0; y = 1; z = 1; #100;

20
x = 1; y = 0; z = 0; #100;
x = 1; y = 0; z = 1; #100;
x = 1; y = 1; z = 0; #100;
x = 1; y = 1; z = 1; #100;
OUTPUT WAVEFORM:

Fig 2.20 Output waveform of full subtractor

RESULT: Half adder, half subtractor, full adder and full subtractor was successfully
implemented using Xilinx.

21
 DATE- 15/01/2018
EXPERIMENT NO 03
AIM: Design and simulation of 4 bit parallel adder.
TOOLS: Xilinx ISE Design Software
METHODOLOGY: The full adder is capable of adding only two single digit binary
number along with a carry input. But in practical we need to add binary numbers which are
much longer than just one bit. To add two n-bit binary numbers we need to use the n-bit
previous full adder is connected to carry input of the next full adder. Therefore this method
can be used to design a 4 bit parallel adder that can add A and B each of 4 bit.

CIRCUIT DIAGRAM AND TRUTH TABLE:

Fig 3.1 Block diagram of 4 bit parallel adder

Table 3.1 Truth table for 4 bit parallel adder
A3 A2 A1 A0 B3 B2 B1 B0 C4 S3 S2 S1 S0
1 0 0 0 0 0 1 0 0 1 0 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0
1 0 1 0 1 0 1 1 1 0 0 1 0
1 1 1 0 1 1 1 1 1 1 0 1 0
1 0 1 0 1 1 0 1 1 0 1 1 1

VERILOG CODE:
GATE LEVEL:
module pa1(input [3:0]a, input [3:0]b, output [3:0]c, output cout, output [3:0]sum );

22
fa A0(a[0],b[0],0,sum[0],c[0]);
fa A1(a[1],b[1],c[0],sum[1],c[1]);
fa A2(a[2],b[2],c[1],sum[2],c[2]);
fa A3(a[3],b[3],c[2],sum[3],c[3]);
buf(cout,c[3]);
endmodule
module fa(
input a ,
input b,
input ci,
output s,
output c
);
wire p,q,r;
xor(p,a,b);
xor(s,p,ci);
and(q,p,ci);
and(r,a,b);
or(c,q,r);
endmodule

DATA FLOW LEVEL:

module pa2(input [3:0]a, input [3:0]b, output [3:0]c,output wire cout,output wire [3:0]sum
);
assign {c[0],sum[0]}=a[0]+b[0]+0;
assign {c[1],sum[1]}=a[1]+b[1]+c[0];
assign {c[2],sum[2]}=a[2]+b[2]+c[1];
assign {c[3],sum[3]}=a[3]+b[3]+c[2];
assign cout=c[3];
endmodule

BEHAVIOURAL LEVEL:

23
module exp3(
input [3:0] a,
input [3:0] b,
output [3:0] s,
output cout
);
wire w1, w2, w3;
fa i1(a[0],b[0],1'b0,s[0],w1);
fa i2(a[1],b[1],w1,s[1],w2);
fa i3(a[2],b[2],w2,s[2],w3);
fa i4(a[3],b[3],w3,s[3],cout);
endmodule

module fa(
input c,
input d,
input e,
output reg s,
output reg cy
);
always @(c or d or e)
case({c,d,e})
3'b000 : begin
s = 0;
cy = 0;
end
3'b001 : begin
s = 1;
cy = 0;
end

24
3'b010 : begin
s = 1;
cy = 0;
end
3'b011 : begin
s = 0;
cy= 1;
end
3'b100 : begin
s = 1;
cy = 0;
end
3'b101 : begin
s = 0;
cy = 1;
end
3'b110 : begin
s = 0;
cy = 1;
end
3'b111 : begin
s = 1;
cy= 1;
end
endcase
endmodule

RTL:

25
 Fig 3.2 RTL of 4 bit parallel adder

TEST BENCH:
module exp3test;
// Inputs
reg [3:0] a;
reg [3:0] b;
// Outputs
wire [3:0] s;
wire cout;
// Instantiate the Unit Under Test (UUT)
exp3 uut (
.a(a),
.b(b),
.s(s),
.cout(cout)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
// Wait 100 ns for global reset to finish
#100;

26
a = 4'b1000; b = 4'b1111;
#100;
a = 4'b1011; b = 4'b1011;
#100;
a = 4'b0000; b = 4'b1110;
#100;
a = 4'b1011; b = 4'b0111;
#100;
end
endmodule

OUTPUT WAVEFORM:

Fig 3.5 Output waveform of 4 bit parallel adder

RESULT: 4 bit parallel adder was successfully designed using Xilinx.

27
 DATE- 15/01/2018
EXPERIMENT NO 04
AIM: Design and simulation of a full adder using half adder.
TOOLS: Xilinx ISE Design Software
METHODOLOGY: Full adder is a digital circuit used to calculate the sum of three
binary bits which is the main difference between this and half adder. Full adders are complex
and difficult to implement when compared to half adders. Two of the three bits are same as
before which are A, the augend bit and B, the addend bit. The additional third bit is carry bit
from the previous stage and is called Carry – in generally represented by CIN. It calculates
the sum of three bits along with the carry. The output carry is called Carry – out and is
represented by COUT. A full adder can be formed by logically connecting two half adders.
The block diagram that shows the implementation of a full adder using two half adders is
shown below.

CIRCUIT DIAGRAM AND TRUTH TABLE:

VERILOG CODE:
BEHAVIOURAL LEVEL:
module exp4(
input a,

28
input b,
input c,
output s,
output cout
);
wire w1, w2,w3;
ha i1(a,b,w3,w1);
ha i2(w3,c,s,w2);
assign cout = (w1|w2);
endmodule

module ha(
input d,e,
output reg sum,
output reg cy
);
always @(d or e)
case({d,e})
2'b00 : begin
sum = 0;
cy = 0;
end
2'b01 : begin
sum = 1;
cy = 0;
end
2'b10 : begin
sum = 1;
cy = 0;
end

29
2'b11 : begin
sum = 0;
cy= 1;
end
endcase
endmodule

RTL:

RTL of a full adder

TEST BENCH:
module exp4test;
// Inputs
reg a;
reg b;
reg c;
// Outputs
wire s;
wire cout;
// Instantiate the Unit Under Test (UUT)
exp4 uut (
.a(a),
.b(b),

30
.c(c),
.s(s),
.cout(cout)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
c = 0;
// Wait 100 ns for global reset to finish
a = 0;b = 0;c = 0;
#100;
a = 0;b = 0;c = 1;
#100;
a = 0;b = 1;c = 0;
#100;
a = 0;b = 1;c = 1;
#100;
a = 1;b = 0;c = 0;
#100;
a = 1;b = 0;c = 1;
#100;
a = 1;b = 1;c = 0;
#100;
a = 1;b = 1;c = 1;
#100;
end
endmodule

OUTPUT WAVEFORM:

31
 Output waveform of a full adder

RESULT: A full adder was successfully designed using Xilinx.

32