CHAPTER 1: CMOS CIRCUITS - A BRIEF INTRODUCTION

CHAPTER 1: CMOS CIRCUITS - A BRIEF

INTRODUCTION

Over the past two decades, Complementary Metal Oxide

Silicon (CMOS) technology has played a very important role in
the global integrated circuit industry. Although the basic
principle of the MOS field-effect transistor was explained by J.
Lilienfeld in 1925, commercial success of MOS devices could
be ensured only during the 1960s with the invention of the
silicon planar process. Nevertheless, the nMOS devices,
fabricated by the nMOS-silicon-gate technology, came to be
used in the early 1970s, prior to which only single-polarity p-
channel transistors were in use. At the same time, P.K.
Weimer and F. Wanlass demonstrated the possibility of using
both polarity devices on the same substrate.

With the implementation of the CMOS inverter, NOR gate and

NAND gate, initially using discrete transistors however, the
CMOS concept took root, demonstrating the low power
dissipation characteristics. Initially, requirement of more
complex processing technology and larger silicon area
compared to the single polarity transistors led to limited
application of CMOS transistors to general system designs.
However, as CMOS technology rapidly improved to support
large chip sizes, and the issue of power consumption became
more and more critical, CMOS technology has firmly
established itself as the dominant VLSI technology.

This first chapter introduces the reader to CMOS logic

design and design representations.

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1.1 MOS Transistors and Switches

Silicon is predominantly used in the fabrication of

semiconductor devices and microcircuits. A MOS (Metal-
Oxide-Silicon) transistor structure is built by stacking several
layers of conducting, insulating and semiconductor materials.
This structure is produced involving a series of chemical
processing steps such as oxidation of silicon, diffusion of
impurities into silicon following etching of silicon oxide from
selected locations, and deposition and etching of aluminum
on silicon to provide connections with the external
environment of the transistor. The fabrication process is
carried out on a single crystal of silicon available as thin
circular wafers of diameter about 30 cm. CMOS technology
makes way for two kinds of transistors, namely nMOS (n-
channel) transistor and pMOS (p-channel) transistor built
by diffusing n-type impurities (rich in electrons) and
positively doped silicon (rich in holes) respectively. Some
of the distinct layers resulting after the fabrication of a MOS
transistor happen to be diffusion, polysilicon and metal
(aluminum), separated by insulating layers.

Figure 1.1 depicts the physical structures and circuit symbols

of an n-channel and a p-channel transistor. The structure of
the n-channel transistor is made of a p-type silicon substrate
accommodating two diffused islands of n-type silicon. Selected
areas of the p-substrate are altered by diffusion or
implantation of n-type impurities. On top of the area
separating the n-type islands lies a thin insulating layer of
silicon dioxide (SiO2) above which there is a conducting layer
(usually made of polycrystalline silicon) called the gate .

Diagrams are given on next page.

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Fig 1.1 : Physical structure and schematic representation of MOS transistors

A p-channel transistor, on the other hand, is made of an n-

substrate separating two diffused p-type islands. Like an n-
transistor, it too has a gate electrode. Apart from the gate
electrode, an nMOS transistor has two more terminals known
as the source and the drain  which connect the two n-
diffused regions (p-diffused regions in a pMOS transistor) with
the external environment of the device. The gate acts as a
control input, regulating the current flow between the source
and the drain. Although the source and the drain are
physically equivalent, the name source is reserved for the
terminal by which the current carriers enter the device,
whereas the drain refers to the terminal by which the carriers
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leave the device. As shown in Figure 1.1, the substrate (also

called the body) happens to be the fourth terminal of a MOS
transistor.

The voltage applied at the gate terminal regulates the flow of

current between the source and the drain. In this way, a MOS
transistor may be viewed as a simple on/off switch. 
Assume that '1' or POWER (PWR) or VDD denotes a high
voltage normally between 1.5 to 15 volts, and '0' or GROUND
(GND) or VSS  stands for a low voltage normally set to zero volt.
The "strength" of a signal denotes its ability to source or sink
current. The strength of '1' and '0' signal can vary.

The switch models of both nMOS and pMOS transistors are

depicted in Figure 1.2.(next page) As shown in Figure 1.2(a),
an nMOS switch is deemed closed or `ON' if the gate voltage
is at logic '1' voltage, or more precisely if the potential between
the gate and the source terminals, namely VGS happens to be
greater than a threshold voltage VT. A closed nMOS switch
implies the existence of a continuous channel between the
source and the drain terminals. On the other hand, an 'OFF'
or open nMOS switch indicates the absence of a connecting
channel between the source and the drain. Similarly, a pMOS
switch is considered 'ON' or closed if the potential VGS  is
smaller or more negative than the threshold voltage VT.
Threshold voltage and related issues will be dealt with in
detail in the next chapter.

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Figure 1.2 : Switch models of MOS transistors

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1.2 CMOS Logic

This section gives an overview of CMOS logic elements that
find use in different applications.

1.2.1: Inverter:

The inverter is universally accepted as the most basic logic

gate doing a Boolean operation on a single input variable.
Figure 1.3 depicts the symbol, truth table and a general
structure of a CMOS inverter. As shown, the simple structure
consists of a combination of an pMOS transistor at the top
and a nMOS transistor at the bottom.

Figure 1.3 : Symbol, circuit structure and truth table of a CMOS

inverter

Explanation:

The truth table of the inverter shows a logic '1' output

corresponding to a logic '0' in the input. This can be ensured
by the p-transistor whose source is connected to a logic '1'
source (VDD) and gate is provided a logic '0' stimulus. As in
this condition, the n-transistor is OFF (that is, there is no

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current path between the output node and ground node) and
the p-transistor channel is in the linear or resistive region of
operation, one obtains perfect logic �1' at the output node.
Similarly, a logic '0' output will result from a logic '1'input.
The nMOS transistor connected in the bottom realizes this
when its gate is given a logic '1' input and its source is
connected to logic '0' or ground (VSS). In this case, the nMOS
transistor channel acts like a wire resulting in logic '0' at the
output while the pMOS transistor channel is simply devoid of
any conductive channel.

The inverter can best be considered as the central part of

digital designs. A thorough understanding of its operation and
properties is required to design more complex structures like
NAND and NOR gates, adders and multipliers.

1.2.2 Combinational Logic

Combinational logic circuits, rather gates, perform Boolean

operations on multiple input variables and determine the
outputs as Boolean functions of the inputs. The basic two-
input AND and OR functions can be realized by series and
parallel combinations of nMOS and pMOS transistors as
shown in Figure 1.4.

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Figure 1.4 : Connection of series and parallel n-switches and p-switches

If two nMOS switches are in series to produce "AND"

function (which means here appearance of same voltage at
nodes A and B by simultaneous conduction of both
transistors) as shown in Figure 1.4(a), both of them should be
closed (or ON) by connecting their gates to logic '1'. Similarly,
to obtain a two-variable "AND" function by pMOS switches as
shown in Figure 1.4(b), the gates should be fed by logic '0'
signals. On the other hand, a two-input "OR"� function
(which means here appearance of same voltage in A and B by
conduction of one or both of the transistors) is realized by
placing two nMOS transistors (Figure 1.4(c)) or two pMOS
transistors (Figure 1.4(d)) in parallel. The OR switch by nMOS
transistors is closed if any one of the transistors is ON (that
is, if any input is at logic '1'). At the same time, the OR
function based on pMOS transistors is realized by placing
logic '0' at either input.

1.2.3 NAND and NOR Gates

Figure 1.5 depicts CMOS implementation of a two-input

NAND gate and its typical symbol. The pull-down sub-circuit
is made of a series combination of two nMOS transistors.
These are responsible for conducting logic '0' to the output
node when both of the gates are at logic '1'.

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Figure 1.5 : A two-input CMOS NAND gate and its symbol

The pull-up path on the other hand consists of a parallel

combination of two pMOS transistors. If either of the is at
logic `0', the output node assumes the value `1'. The two
symbols shown in Figure 1.5(b) for a two-input NAND gate is
due to the equivalence given by,

Figure 1.6 depicts CMOS implementation of a two-input NOR

gate and its typical symbol. The pull-up sub-circuit is made of
a series combination of two pMOS transistors. These are
responsible for conducting logic `1' to the output node when
both of the gates are at logic `0'.

The pull-down path on the other hand consists of a parallel

combination of two nMOS transistors. If either of the inputs is
at logic `1', the output node assumes the value `0'. The two
symbols shown in Figure 1.6(b) for a two-input NOR gate is
due to the equivalence

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Figure 1.6 : A two-input CMOS NOR gate and its symbol

1.2.4 Compound Gate and Multiplexers

Complex Boolean functions of multiple input variables can be

realized by simple extension of the circuit structures
developed for the basic NAND and NOR gates discussed
above.

Consider the boolean function  whose CMOS

implements is shown in fig 1.7.

The output node attains the logic `1' owing to the pMOS sub-
circuit. One can easily see that driving both the gate inputs
(labeled A  and B ) of the pMOS transistors or driving the
inputs (labeled C and D ) of the series pMOS transistors
achieves the output `1'. Due to the complementary nature of
the pMOS and nMOS transistors, any series combination of
transistors in the nMOS tree gets replaced by a parallel
connection in the pMOS tree and vice versa.

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To implement a multiplexer, one can use complementary

switches. Figure 1.8 depicts how to realize a 2-input
multiplexer in CMOS design style. The circuit shown in Figure
1.8(a) consists of two transmission gates, each consisting of
an nMOS and a pMOS transistors. Note that the upper
transmission gate allows input A to be passed to the output
when the gate control C is at logic '0'. Also, the lower
transmission gate transmits the input B to the output when
its gate control C  is at logic '1'. Thus both the transmission
gates are not simultaneously open for their respective input
signals to pass to the common output node. This in essence
constitutes a 2-input multiplexer with control input C and
two data inputs A and B. Figure 1.8(b) shows the commonly
used symbol for a 2-input multiplexer.

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Figure 1.8 : CMOS implementation of a 2-input multiplexer

1.2.5 Memory: Latch and Register

Semiconductor memory capable of storing large amount of

information are essential to all digital systems. In its simplest
form, a single-bit memory element can be realized as a latch
or a register. A latch is a level-sensitive  circuit for which the
state of the output depends on the level of the clock signal. It
passes the D input to the Q output when the clock signal is
high (for a positive latch  ) or when the clock is low (in case of
a negative latch  ). This latch is then said to be
in transparent mode. During the low state of the clock, for a
positive latch, the input data sampled at the falling edge of the
clock is held stable at the output; the latch is now said to be
in hold  mode. The input should be stable for a short period
around the falling edge of the clock to meet setup and hold
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requirements. Figure 1.9 depicts a positive level-sensitive

latch implemented using a 2-input multiplexer and two
inverters. It has a data input D, a clock input Clk, and two
outputs Q and Q. The output Q  follows the input D when
Clk=`1'. When Clk=`0', the D input is ignored, and the state of
output Q is retained. Similarly, a negative latch  passes the D
input to the Q output when the clock signal is low.

Figure 1.9 : A CMOS positive level-sensitive D latch

One can use a negative latch followed by a positive latch to

realize an edge-triggered  register, as shown in Figure 1.10.
When the clock signal is low, the output  of the first stage,
normally referred to as the master stage, follows the D input,
whereas, the output Q  of the second stage, commonly known
as the slave stage, retains the previous value. When a
transition 0 à 1 takes place in the clock input, the value of the
slave output Q  freezes at the value of D input existing just
before the rising edge of the clock. As the sampling of the
input takes place on a   clock transition, this register is
called a positive  edge-triggered  register. When the clock
remains at logic `1', the master stops sampling the D input
and stores the D value at the time of the clock transition.
Now, the slave latch allows the complement of the stored
master value  to pass to the output Q. The D input cannot
affect the output Q  as the master stage is disconnected from
the D input. When the clock makes a transition from `1' to `0',
the slave stage is disconnected from the master stage and gets
locked to its previous value due to the feedback loop. Also, the
master stage begins sampling the D input again.

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A negative edge-triggered  register is one in which during a 1

→ 0 transition, the value of the output Q  freezes at the value
of D input existing just before the falling edge of the clock. It
is realized by reversing the order of the two latches shown in
Figure 1.10.

Figure 1.10 : A CMOS positive edge-triggered D register

1.3 Circuit and System Representation - Behavioral,

Structural and Physical Representation

A complex digital system is broken down into component

gates and memory elements by splitting the system in a
hierarchical manner. A set of requirements is envisaged.
Guided by these, an initial design is developed and
subsequently tested against the requirements. Design has
to be improved in case the requirements are not met. The
Y-chart (first conceived by D. Gajski) shown in Figure 1.11
demonstrates a simplified design flow that is adopted for
the majority of logic chips, using the activities on three
different axes (domains) which resemble the letter "Y".

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The three domains of representation that make up the Y-

chart are the behavioral domain, the structural domain and
the physical layout domain. The behavioral view of a digital
system describes its function of the system with no regard
to its implementation. The structural view of a system
describes a system as an interconnection of components.
The physical view of a system is concerned with the
physical entities, namely the transistors that constitute the
circuit.

Physical Layout Domain

The design flow at the behavioral domain starts from the

algorithm that specifies the operation of the target chip. The
architecture of the corresponding processor in the
structural domain is envisaged. It is projected onto the chip
surface in the physical (geometrical) layout domain by floor-
planning.

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The next development along the axis of the behavioral domain

happens to be the finite state machines (FSMs) which are
realized at the structural plane by functional modules such as
registers, adders, multipliers and arithmetic logic units
(ALUs). The automatic placement and routing  of these
modules are then done on the physical plane with an objective
of minimizing the area occupied by the interconnects and
signal delay. Next phase of refinement on the behavioural level
is the behavioural description of the module. At the structural
level, the target chip is now described in terms of the logic
gates (or leaf cells  ) which can be placed and interconnected
using a cell placement and routing program. The last major
refinement at the behavioural plane is concerned with the
detailed Boolean description of the leaf cells followed by a
transistor level realization of the leaf cells and mask
generation . Actually, the leaf cells are pre-designed at the
transistor level in the standard-cell based design style, and
stored in a library for logic implementation.

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