NCNU_2013_DD_5_1

Chapter 5: Synchronous Sequential Logic

5.1 Introduction
5.2 Sequential Circuits
5.3 Storage Elements: Latches
5 4 Storage
5.4 S El
Elements: Flip­Flops
Fli Fl
5.5 Analysis of Clocked Sequential Circuits
5.7 State Reduction and Assignment
5 8 Design Procedure
5.8
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Introduction
• All digital systems contain memory components that can store information.
• Combinational circuits
– contains no memory elements
– the outputs depends on the inputs
• Sequential circuits, however, act as storage elements and have memory.
– to store, retain, and then retrieve information when needed at a later time.
• Block diagram of a sequential circuit:

– A combinational circuit with memory elements forming a feedback path.

– The binary information stored in memory defines the state.
– Outputs are determined by Inputs and present state.
state
– Next state is also determined by Inputs and present state.
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Synchronous vs. Asychronous

• There are two main types of sequential circuits: synchronous and asynchronous.
• The behavior of a synchronous sequential circuit can be defined from the
knowledge of its signals at discrete instants of time.
• The behavior of an asynchronous sequential circuit depends upon the input
signals at any instant of time and the order in which the inputs change.
change
• The storage elements commonly used in asynchronous sequential circuits are
time-delay devices. Thus, an asynchronous sequential circuit may be regarded as
a combinational
bi i l circuit
i i withi h feedback
f db k (no
( actuall storage elements
l used).
d)
• Asynchronous sequential circuit may become unstable at times, imposing many
difficulties on the designer, and will not be covered in this text.
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Clocked Sequential Circuits

• Synchronous sequential circuits affect the storage elements at only discrete
instants of time.
• A clock generator performs the synchronization, which provides a clock signal
having a periodic train of clock pulses, commonly denoted as clock or clk .
• The storage elements are affected only
onl with
ith the arrival
arri al of each clock pulse.
p lse
• In practice, the clock pulses determine when computational activity will occur
within the circuit, and other signals (external inputs and otherwise) determine
what changes will take place affecting the storage elements and the outputs.
• Synchronous sequential circuits that use clock pulses to control storage elements
are called clocked sequential circuits and are the type most frequently
encountered in practice; also called synchronous circuits because the activity
within the circuit and the resulting
g updating
p g of stored values is synchronized
y to
the occurrence of clock pulses.
• The design of synchronous circuits is feasible because they seldom manifest
instability problems and their timing is easily broken down into independent
discrete steps, each of which can be considered separately.
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Filp-Flops as Storage Elements

• Flip-flops (FF), 1-bit memory, are used as the storage elements.
• A sequential circuit may use many flip-flops to store as many bits as necessary.
• The
h output off a flip-flop
fli fl is i either
i h 0 or 1 (two
( states).
)
• The outputs (and next states) are combinational logic function of the inputs to the
circuit and/or the values stored in the flip
flip-flops.
flops.
• The new value is stored (updated) in flip-flop when the clock pulse occurs.
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Clock Synchronization
• The next value of the flip-flop must have reached a stable value before the
occurrence of the clock pulse, consequently, the combinational logic must
respond
p to a change
g in the state of the flip-flop
p p in time to be updated
p before the
next clock pulse arrives.
• Propagation delays of the combinational logic determines the minimum interval
between clock pulses to allow the circuit to operate correctly.
correctly
• The state of the flip-flops changes only by a clock pulse transition—for example,
when the value of the clock signals changes from 0 to 1 (positive edge).
• If the clock pulse is not active, the input and output of the flip-flop is effectively
isolated; flip-flop can be regarded as two gates controlled complementarily.
• Th
Thus, the
th ttransition
iti from
f one state
t t to
t the
th nextt occurs onlyl att predetermined
d t i d
intervals dictated by the clock pulses, that is so called synchronization.
• Storage
g elements that operate
p with signal
g levels ((rather than signal
g transitions)) are
referred to as latches; those controlled by a clock transition are flip-flops .
• Latches are said to be level sensitive devices; flip-flops are edge-sensitive ones.
• For
F ddesign
i simply
i l andd function
f i correctly,
l use flip-flops
fli fl as possible
ibl as you can.
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5-3 Latches
• The SR latch is a circuit with two cross-coupled NOR gates (or two cross-coupled
NAND gates) and two inputs labeled with S for set and R for reset.
• When output Q = 1 and Q Q’ = 0,
0 the latch is said to be in the set state,
state and Q = 0
and Q’ = 1, is in the reset state.
• Forbidden state:
– Inputs Q and Q’ are normally the complement of each other
– When both inputs are 1 at the same time result both outputs equal to 0
– If both
b th inputs
i t then
th change
h to
t 0 simultaneously,
i lt l the
th device
d i will
ill enter
t an
unpredictable or undefined state or a metastable state
– The next state will depend
p on the order in which S and R return to 0.
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SR Latch with NAND Gates

• Both inputs are normally at 1.
• Input 0 to the S (R) causes Q (Q’) to be 1, putting the latch in the set (reset) state.
• The
h forbidden
f bidd condition
di i isi both
b h inputs
i being
b i 0 at the
h same time.
i
• The NAND latch is low activated (active low).
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SR Latch with Enable

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D Latch (Transparent Latch)

• Ensure S and R are never equal to 1 at the same time to eliminate the undesirable
condition of the indeterminate state in the SR latch.
• As En is at 0,
0 the cross
cross-coupled
coupled SR latch has both inputs at 1 and the circuit
cannot change state regardless of the value of D .
• Transparent: as En = 1, Q (Q’) follows the change of D
• When En transits from 1 to 0, the binary information at D at the transition time is
retained (i.e., stored) at Q until En raises to 1 again.

• Characteristic
Ch i i equation:
i Q( 1) = D
Q(t+1)
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Trigger
• Trigger: a latch or flip-flop is switched by a change of the control input
– Level triggered – latches
– Edge triggered – flip-flops

• The transparent latch (level sensitive) may fail due to a race condition.
– The state of a latch changes as soon as the clock changes to 1, and the new
state
t t appears att the
th output
t t while
hil the
th clock
l k isi still
till active
ti (due
(d tto ttransparent).
t)
– This output may race through the combinational circuit to the latch input.
– If the clock is still active,
active the latch will respond to the new value again and a
new output state may occur resulting an unpredictable situation.
– To avoid such condition, the output of a latch cannot be applied directly or
through combinational logic to the input of the same or another latch when all
the latches are triggered by a common clock source.
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Master–slave D Flip-flop
• D flip-flop consists of two D latches and an inverter, the first latch is called the
master and the second the slave.
• Th
The two
t latches
l t h are controlled
t ll d ((enabled)
bl d) complementarily;
l t il they
th fli
flip and
d flop
fl
alternatively.
• Samples
p D and changes g Q only y at the negative
g edge
g of the clock (Clk),
( ), the
transition of the clock from 1 to 0.
• Positive edge triggered D flip-flop can also be constructed by adding an inverter
to the Clk input.
input
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D-type Positive-edge-triggered Flip-flop

• Two latches respond to the D (data) and Clk (clock) inputs, and the third latch
provides the outputs for the flip-flop.

(S R) = (0,
(S, (0 1): Q = 1
(S, R) = (1, 0): Q = 0
(S, R) = (1, 1): no operation
(S, R) = (0, 0): should be avoided
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Timing Parameters
• Setup time
– D input must be maintained at a constant value prior to the application of the
positive-edge
iti d off Clk pulse
l (rise)
(i )
– equal to the propagation delay through gates 4 and 1
– data to the internal latches
• Hold time
– D input must not changes after the application of the positive Clk pulse
– equal to the propagation delay of gate 3
– clock to the internal latch

Clk

setup hold
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Graphic Symbols

 Latch

 Edge-triggered D flip-flop
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JK Flip-Flop
• Edge-triggered D flip-flop requires the smallest number of gates, and is the most
economical and efficient flip-flop constructed in VLSI IC design.
• Other
Oth types
t off flip-flops
fli fl can be
b constructed
t t d byb D flip-flop
fli fl andd external
t l logic.
l i
• JK and T flip-flops are two other less used flip-flops.
• JK flip
flip-flop:
flop:

D = JQ’ + K’Q

• Characteristic equation: Q(t+1) = JQ’ + K’Q

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T Flip-Flop
• T (toggle) flip-flop can be obtained from a JK flip-flop with J and K tied together.
• Can also be constructed with a D flip-flop and an exclusive-OR gate.
D = T ⊕ Q = TQ’ + T’Q  Characteristic equation: Q(t+1) = TQ’ + T’Q
• Useful for designing binary counters.
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Asynchronous Inputs
• The state of the flip-flops is unknown when power is turned on.
• Asynchronous inputs are used to force the flip-flop to a known starting state
(initialization) independently of the clock.
clock
• Preset or direct set sets the flip-flop to 1.
• Clear or direct reset clears the flip
flip-flop
flop to 0.
• D flip-flop with asynchronous reset:

1
1
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5-5 Analysis of Clocked Sequential Ckts

• Analysis describes what a circuit will do under certain operating conditions.
• For clocked sequential circuits, the outputs and the next state are both a function
of the inputs and the present state.
• The analysis of a sequential circuit consists of obtaining a state table or a state
di
diagram for the time seq
sequence
ence of inp
inputs,
ts ooutputs,
tp ts and internal states
states.
• Boolean expressions can also describe the behavior of the sequential circuit.
• A logic
l i diagram
di is
i recognized
i d as a clocked
l k d sequential
i l circuit
i i if it
i includes
i l d flip-
fli
flops with clock inputs.
• The flip-flops
flip flops may be of any type,
type and the logic diagram may or may not include
combinational logic gates.
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State Equations
• Th
The behavior
b h i off a clocked
l k d sequentialti l circuit
i it can be
b described
d ib d algebraically
l b i ll by b
means of state equations; also called transition equations, specifies the next state
as a function of the present state and inputs.
• Example: 0-detector
two D flip-flops A and B
an input
i x and
d an output y

State equations:
A(t + 1) = A(t)x(t) + B(t)x(t)
B(t + 1) = A’(t)x(t)
t: Present
P t time
ti
t+1: Next time

Output:
y(t)) = [A(t)
y( [ ( ) + B(t)]x’(t)
( )] ( )
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State Table
• State table (also called a transition table) enumerates the time sequence of inputs,
outputs, and flip-flop states.
• The table consists of four labels: present state,
state input,
input next state,
state and output.
output
• List all possible binary combinations of present states and inputs.
State equations
S q are derived as:
A(t + 1) = Ax + Bx
B(t + 1) = A’x

Output equation:
y = (A + B)x
B)x’

Also can be expressed with flip-

flop input equations:
DA = Ax + Bx
DB = A’x
y = (A + B)x’
similar to a truth table
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Second Form of State Table

• In general, a sequential circuit with m flip-flops and n inputs needs 2m+n rows in
the state table.
• A secondd ffrom off state
t t table
t bl uses only
l three
th labels:
l b l presentt state,
t t nextt state,
t t andd
output; and the input conditions are enumerated under the next-state and output
sections.

similar to a K-map
p
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State Diagram
• Graphical representation of a state table
• Well matched with the second form of state table
• Each circle represents an assigned state
• Directed lines, indicate a state transition, are labeled with input/output
• In this example, every circle (state) has two outgoing directed lines to other circles
• A directed line connecting a circle with itself indicates that no change of state
occurs.

• The analysis steps are summarized as:

circuit  equations  state table  state diagram
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Analysis with D Flip-flops

• A sequential circuit with state equation: DA = A ⊕ x ⊕ y
DA: D flip-flop with output A; x and y: inputs; and no output given.
• For a D flip-flop, the state equation is the same as the input equation.
• One flip-flop has two states.
• Two
T o inputs
inp ts ha
havee fo
fourr possible combinations for each state.
state
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Analysis with JK Flip-flops

• The next-state values of JK or T flip-flops can be derived as follows:
1. Determine the flip-flop input equations in terms of the present state and input
variables.
variables
2. List the binary values of each input equation.
3. Use the corresponding flip-flop
flip flop characteristic table to determine the next
next-state
state
values in the state table.
• The flip-flop input equations
JA = B
KA = Bx’
JB = x’’
KB = A’x + Ax’ = A⊕ x
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JA = B, KA = Bx’
JB = x’, KB = A’x + Ax’ = A⊕ x

• The above equations determine the flip-flop inputs to derive the next state

• Or, derive the state equations using characteristic eq.

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Using Characteristic Equations

• Characteristic equation of JK FF: Q(t+1) = JQ’ + K’Q
• So for the two JK FFs A(t + 1) = JAA’ + KA’A, B(t + 1) = JBB’ + KB’B
• Substituting the values of JA, KA, JB, and KB JA = B, KA = Bx’

A(t + 1) = BA’ + (Bx’ )’ A = A’ B + AB’ + Ax JB = x’ , KB = A’x + Ax’ = A⊕ x

B( + 1) = x’’ B’ + (A ⊕ x)’
B(t )’ B = B’ x’’ + ABx
AB + A’ Bx’
B ’
The “Next state” can be derived from the above two equations.

• State diagram:
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Analysis with T Flip-flops

• Example: two T flip-flops A and B, one input x, and one output y
• Two input equations and an output equation:
TA = Bx
TB = x
y = AB
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• Input equations and an output equation:

TA = Bx,
B TB = x, y = AB
• Characteristic equation of T flip-flops: Q(t + 1) = T ⊕ Q = T’Q + TQ’
• The values for the next state
A(t + 1) = (Bx)’A + (Bx)A’ = AB’ + Ax’ + A’Bx
( + 1)) = x ⊕ B
B(t
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Finite State Machines (FSM)

• A sequential circuit has inputs, outputs, and internal states.
• Two commonly used finite state machine models of sequential circuits, the Mealy
model and the Moore model,
model differing only in the way the output is generated.
generated
• The outputs of Moore circuit are synchronized with the clock, depend only on
flip-flop outputs that are synchronized with the clock.
• The output of the Mealy machine is the value that is present immediately before
the active edge of the clock.
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5-7 State Reduction and Assignment

• The design (synthesis) of a sequential circuit starts from a set of specifications
and culminates in a logic diagram.
• Two sequential circuits may exhibit the same input–output behavior (function),
but have a different number of internal states in their state diagram.
• The current
c rrent section disc
discusses
sses certain properties of seq
sequential
ential circ
circuits
its that may
ma
simplify a design by reducing the number of gates and flip-flops it uses.
• In general, reducing the number of flip
flip-flops
flops reduces the cost of a circuit.
• State-reduction, reducing the number of states in a state table, while keeping the
external input–output requirements unchanged, can reduce the number of flip-
flops used in a sequential circuit.
• Since m flip-flops produce 2m states, a reduction in the number of states may (or
may not)
t) result
lt in
i a reduction
d ti in i the
th numberb off flip-flops.
fli fl
• Reducing the number of flip-flops sometimes results the equivalent circuit with
fewer flip
flip-flops
flops but more combinational gates to realize its next state and output
logic.
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State Reduction Example

• Two circuits are equivalent if identical input
sequences are applied to the two circuits and
identical outputs occur for all input sequences,
then one may be replaced by the other.
• State reduction reduces the number of states in
a sequential circuit without altering the input–
output relationships.
•O
Onlyl the
th input-output
i t t t sequences are important
i t t
in this example.
• Consider the input sequence 01010110100
starting from the initial state a.
• Complete
p q
the sequence g the follows:
to get
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• State table is more convenient for state reduction than a diagram.

• State reduction algorithm: “Two states are said to be equivalent if, for each
member of the set of inputs, they give exactly the same output and send the circuit
either to the same state or to an equivalent
q state.”
• When two states are equivalent, one of them can be removed without altering the
input–output relationships.
• Back to the example:
– States e and g both go to states a and f and have
outputs of 0 and 1 for x = 0 and x = 1,
1 respectively.
respectively
– States g and e are equivalent, and one of these states
can be removed.
– States f and d are also equivalent, so state f can be
removed and replaced by d.
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Original State Table

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Reduced State Diagram

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State Assignment
• States must be assigned with unique coded binary values to implement the
physical components.
• For a circuit with m states, the assigned codes must contain n bits, where 2n ≧ m.
• Unused states (codes) are treated as don’t-care conditions during the design.
• Don’t-care conditions usually help in obtaining a simpler circuit.
• The simplest way to code states is to use binary counting code or Gray code
without
ih guaranteeing
i a better
b result.
l
• One-hot assignment, uses one flip-flop per state, ensures only one bit is equal to 1
while all others are kept at 0,
0 usually leads to simpler decoding logic for the next
state and output, results a faster machines, and the silicon area required by the
extra flip-flops can be offset by the area saved by using simpler decoding logic.
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Binary Assignment
• A different assignment will result in a state table with different binary values for
the states.
• Th
The binary
bi form
f off the
th state
t t table
t bl is
i usedd to
t derive
d i the
th nextt state
t t andd output
t t --
forming combinational logic part of the sequential circuit.
• The complexity
p y of the combinational circuit depends
p on the binaryy state
assignment chosen.
• Sometimes, the name transition table is used for a state table with a binary
assignment.
assignment

a
b
c
d
e

A great many possible binary assignments may exist.

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5-8 Design Procedure

• A synchronous sequential circuit is made up of flip-flops and combinational
gates.
• The design of the circuit consists of choosing the flip-flops and then finding a
combinational gate structure that, together with the flip-flops, produces a circuit
which fulfills the stated specifications.
p
• The design steps for synchronous sequential circuits can be summarized as:
1. From the word description and specifications of the desired operation, derive a
state diagram for the circuit.
2. Reduce the number of states if necessary.
3 Assign
3. A i bibinary values
l to the
h states.
4. Obtain the binary-coded state table.
5 Choose the type of flip-flops to be used.
5. used
6. Derive the simplified flip-flop input equations and output equations.
7. Draw the logic
g diagram.
g
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Synthesis using D Flip-flops

• Example: detect a sequence of three or more consecutive 1’s in a string of bits
coming through an input line.

• Assign binary codes to the states and list the

state table.
• Two D FFs (A and B) represent the four
states, and one input x and one output y.

Si: i consecutive 11’ss is detected

S0: starting state
Moore FSM
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• The characteristic equation of the D flip-flop is Q(t + 1) = DQ

• The flip-flop input equations can be obtained directly from the next-state
columns of A and B and expressed in sum-of-minterms form as
(A B x) = (3,
A(t + 1) = DA(A,B, (3 55, 7)
B(t + 1) = DB(A,B, x) = (1, 5, 7)
y(
y(A,B, x)) = (6,
( 7))
• The Boolean equations are simplified by k-maps:
DA = Ax + Bx
DB = Ax + B’x
y = AB
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Logic Diagram of the Sequence Detector

DA = Ax + Bx
DB = Ax + B’x
y = AB
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Excitation Tables
• The advantage of designing with D FFs is that the Boolean equations describing
the inputs to the flip-flops can be obtained directly from the state table, the input
equations are obtained directly from the next state.
state This is not the case for the JK
and T types of flip-flops.
• A state diagram  flip
flip-flop
flop input functions
– straightforward for D flip-flops
– we need excitation tables for JK and T flip-flops
– a table that lists the required inputs for a given change of state.

+ +
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Synthesis using JK Flip-flops

+

• The same example

• The state table and JK flip-flop inputs
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K-Maps for JK Input Equations

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Logic Diagram with JK Flip-flops

JA = Bx’ KA = Bx JB = x KB = (A⊕x)’
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Synthesis using T Flip-flops

• Example: n-bit binary counter consists of n flip-flops that can count in binary
from 0 to 2n - 1.
• The state diagram of a 3-bit counter is shown below, the input is the clock and
the output is the state.
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• Binary
y counters are constructed most efficiently
y with T flip-flops.
p p
+
• Three flip-flops A2, A1, and A0 are used.
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Homework #5

• 5.6

• 5.8

• 5.10

• 5.12
5 12

• 5.16