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Metropolitan University, Sylhet

This document is the midterm examination for the Digital Logic Design course at Metropolitan University, Sylhet for the Computer Science and Engineering program. The exam contains 4 questions with multiple parts each. Students must answer any 3 of the 4 questions. The questions cover topics like differences between analog and digital signals, Boolean algebra, logic gates, simplifying logic circuits, De Morgan's theorem, adders, and don't care conditions.

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Jashon Roy
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0% found this document useful (0 votes)
40 views1 page

Metropolitan University, Sylhet

This document is the midterm examination for the Digital Logic Design course at Metropolitan University, Sylhet for the Computer Science and Engineering program. The exam contains 4 questions with multiple parts each. Students must answer any 3 of the 4 questions. The questions cover topics like differences between analog and digital signals, Boolean algebra, logic gates, simplifying logic circuits, De Morgan's theorem, adders, and don't care conditions.

Uploaded by

Jashon Roy
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Metropolitan University, Sylhet

Department of Computer Science and Engineering


Midterm Examination, Spring – 2018
Program: CSE, Batch: 38 (A & B)
Course Title: CSE-211::Digital Logic Design

Time: 1 Hour 30 minutes Full Marks: 30


(Answer any three questions)

1. a) Write down few differences between Analog and Digital signal. 4


b) Convert the following: 3
i) (A29C)16 = (?)8 ii) (5635.35)8 = (?)10
c) Define Universal gate. Explain NOR is an Universal gate. 3

2. a) Prove De Morgan’s theorem for three variables. 3


b) Find a simplified switching expression and logic network for the logic circuit in the 5
following figure.

c) What is SOP and POS 2

3. a) Design a logic circuit that controls an elevator door in a three story building. 4
b) What is adder? Construct a full adder logic circuit by using proper simplification. 4
c) Define Don’t care condition. 2

4. a) Simplifying the following equations using Boolean Rules and show the outputs in 6
basic gates.
i) A'B'C' + A'BC + ABC + AB'C' + AB'C
ii) ((A'+C ) (AB)')'
b) Simplify the expression F(W,X,Y,Z) = W´X´Y´ + X´YZ´ + W´XYZ´ + WX´Y´ 4

01750-175 077

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