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Experiment - 2: Aim: Study of Basic Gates

This document describes an experiment to design basic logic gates using a data flow model. The gates implemented are AND, OR, and NOT. Truth tables and output equations are provided for each gate. The gates are modeled using VHDL code with test benches. Simulation results and RTL views confirm that the gates were designed and function correctly as expected from their truth tables and equations. The conclusion is that all basic gates were successfully studied and implemented using Quartus II software.

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Jaspreet Singh Sidhu
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64 views2 pages

Experiment - 2: Aim: Study of Basic Gates

This document describes an experiment to design basic logic gates using a data flow model. The gates implemented are AND, OR, and NOT. Truth tables and output equations are provided for each gate. The gates are modeled using VHDL code with test benches. Simulation results and RTL views confirm that the gates were designed and function correctly as expected from their truth tables and equations. The conclusion is that all basic gates were successfully studied and implemented using Quartus II software.

Uploaded by

Jaspreet Singh Sidhu
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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5

Experiment - 2
Date of Performance: Roll No. :

Aim : Study of Basic Gates.

Objective : Designing of Basic Gates Using a Data Flow Model.

Truth Table :
library ieee;
use ieee.std_logic_1164.all;
INPUT OUTPUT
entity basic is A B Y
port(A, B:in std_logic; 0 0 0
Y:out std_logic); 0 1 0
AND Gate : 1 0 0
end basic;
1 1 1

architecture df of basic is
Output Equation :
begin
Y <= A and B;
Y=A.B
end df;
library ieee; Truth Table :
use ieee.std_logic_1164.all;
INPUT OUTPUT
entity basic is A B Y
port(A, B:in std_logic; 0 0 0
Program : Y:out std_logic); 0 1 1
OR Gate : 1 0 1
end basic;
1 1 1
architecture df of basic is
Output Equation :
begin
Y <= A or B; Y=A+B
end df;
library ieee;
use ieee.std_logic_1164.all; Truth Table :

entity basic is INPUT OUTPUT


port(A:in std_logic; A Y
Y:out std_logic); 0 1
NOT Gate : 1 0
end basic;

architecture df of basic is Output Equation :


begin
Y = Ā
Y <= not A;
end df;
AND Gate :

Simulation
Result :

Department of Electronics and Telecommunication Engineering, ACET, Nagpur


6

OR Gate :

NOT Gate :

AND Gate :

y~0
a
y
b

OR Gate :

y~0
RTL View : a
y
b

NOT Gate :

Result /
All the Basic Gates are studied and implemented successfully using Quartus II 15.0 software
Conclusion :
Roll No. :
Marks out of
Signature :
Sem-Section 7th Sem. B 10

Date of
Name of Faculty : Sufiyan Khan
Submssion

Department of Electronics and Telecommunication Engineering, ACET, Nagpur

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