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fully edited. Content may change prior to final publication. Citation information: DOI
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Double-Deck Buck-Boost Converter with Soft

Switching Operation
Erfan Maali Amiri, and Behrooz Vahidi, Senior Member, IEEE

 proposed for soft switching operation of the converters to

Abstract—This paper presents a novel two-stage buck-boost achieve minimum switching losses leading to more efficient
converter with soft switching operation. The proposed converter operations [1], [4]-[6]. Soft switching techniques utilizing the
is constructed of two identical buck-boost converters working in features of Zero Voltage Switching (ZVS) or Zero Current
parallel. The converter units are connected to each other by an
Switching (ZCS) substantially reduce the switching losses [7]-
inductor as a bridge. This inductor plays an important role in the
soft switching operation of the converter by maintaining the [10]. Some of these approaches include active clamps [11],
voltage applied to switches at zero at switching intervals. The passive, and active snubbers [12]-[14]. In some cases a
utilized method is called the zero-voltage switching. It is shown combination of ZVS and ZCS techniques has also been
that the structure of the proposed converter is significantly discussed [12], [15, 16].
efficient in the reduction of switching losses, leading to the Nowadays, interleaved converters are utilized in many
improvement of the converter efficiency. Moreover, because of
applications and provide many advantages such as increasing
the parallel operation of two identical converters, the output
voltage and the input current contain fewer ripples than those of efficiency, reducing the voltage and current ripple and
a single converter with the same specifications. Also, utilizing supplying more load power [17]-[20]. The ZVS operation of
only one inductor as an extra element to achieve this goal, makes the parallel boost converters has been investigated in [20]. The
the proposed converter more economical and reliable with inductor placed between two parallel converters is called the
simpler structure. The detailed analysis of the circuit operation is interleaved inductor and displaces the resonating current
provided in eight modes. The proposed method is implemented in
between two converters at the particular time intervals in order
a laboratory test circuit within the range of 100-220 W output
power validating the accuracy of the proposed converter. to perform the soft switching operation of the set [21]. The
operation procedure of this kind of converters is described in
Index Terms— Buck-boost converter, Interleaved inductor, two sets of symmetric scenarios depending on the situation of
Zero voltage switching. the resonating current.
In this paper, a double-deck buck-boost converter with an
effective ZVS technique is proposed. The operational
I. INTRODUCTION principles of the proposed converter are surveyed and
DC/DC converters are used for many purposes when the summarized in eight modes. It is shown that the switching
conversion between two DC voltage levels such as electrical process can perform with the minimum losses by applying the
vehicles, active filters, Power Factor Correction circuits gate signals at particular time intervals. A laboratory test
(PFC), Distributed Generations (DG), DC/DC regulated power circuit is designed and implemented to evaluate the
supplies, etc. is required [1]-[3]. These types of converters are applicability of the proposed converter. It is shown that the
divided into several types depending on the increase or converter efficiency increases substantially up to 93% in all
decrease of the output voltage level with respect to the input cases of the investigated load power from 100 W to 220 W.
voltage. This paper focuses on the buck-boost DC/DC Moreover, it is also concluded that utilizing of two converters
converters which can operate in either buck or boost modes, in parallel causes less ripple in the output load voltage. In
i.e. it can be used in both step-up and down applications. addition, the fact of using only one inductor as an extra
Another counterpart of these converters is the Cuk converter element to achieve the main goal of the paper suggests that the
with a large number of circuit elements in its structure. The proposed converter is more economical than the soft switched
main application of step-up/down converters is in regulated converters by adopting coupled inductors or transformers.
DC power supplies where the output negative polarity may be The paper is organized as follows: circuit configuration and
desired with respect to the common terminal of the input operation analysis are described in Section II. Circuit
voltage supply. mathematical analysis and design are discussed in Section III.
The efficiency of the DC/DC converters is an important The experimental results are presented in Section IV and
issue which has received great attention in literatures. In this finally, the paper is concluded in Section V.
regard, various control strategies and converter topologies are
II. CIRCUIT CONFIGURATION AND OPERATION ANALYSIS
E. Maali Amiri, B. Vahidi are with the Department of Electrical The configuration of the proposed converter is depicted in
Engineering, Amirkabir University of Technology, Tehran 1591634311, Iran, Fig. 1. It is composed of two identical buck-boost converters
(e-mail: [email protected], [email protected]).

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D1 CS1
iS1 i D1
DS1
S1 S1
LS D1 `

D2
CS2 LS i Ls
Ro Vo iS2 i D2
DS2 Ro Vo
S2
VDC
L1 L2 Co S2 D2
VDC I L1 I L2 Co
Fig. 2. Equivalent circuit diagram.
Fig. 1. Configuration of the parallel buck-boost converters.

depicted in Fig. 4. Meanwhile, iS1 increases linearly

working in parallel. The source and the output capacitor Co are simultaneous with the iLs increment. As the iLs reaches to zero,
shared between two converters. The inductor Ls is placed in the current IL1 passes through switch S1. When iLs rises up to
parallel with two switches as shown in Fig. 1. This element IL2, iS1 reaches IL1+IL2. At the end, the freewheeling current of
plays an important role in main plot of the soft switching D2 reaches zero as shown in Fig. 4. On whole, VCS2 is
manner of the converter. It discharges the intrinsic considered to be constant and equal to VDC+VO in this process.
capacitances of the switches by creating a resonant circuit. Mode II— t1 < t < t2: this mode starts when the
Then, the switching could be done when the intrinsic freewheeling current of D2 reaching zero. Then, a resonant
antiparallel diodes of the switches conduct the negative half- circuit is formed between CS2 and LS. This resonating current
cycle of this resonating current and the voltage on the switches discharges the capacitor CS2 which was clamped on the
is clamped at zero. VDC+VO before entering this mode. After VCS2 decreases to
Two power MOSFETs S1 and S2 are adopted for high- zero, DS2 will be forward biases to conduct the resumption of
frequency switching with the same switching frequency. The the resonant current cycle. Now, both of the resonant current
duty ratio (D) for each of the switches is identical and slightly and the inductor current flow through the interleaved inductor
greater than 0.5 to create overlapping intervals. It is assumed LS; therefore, the iLs becomes a small bit larger than IL2 as
that the converters operate in Continuous Current Mode illustrated in Fig. 4. Fig. 3 (b), shows the equivalent circuit
(CCM). diagram of this mode.
The equivalent circuit shown in Fig. 2 is utilized to describe Mode III— t2 < t < t3: at the beginning of this mode, DS2
the procedure of the proposed converter operation. To simplify whose voltage was fixed at zero, begins to conduct a small
the analysis, it is considered that the currents of inductors L1 current reversely through switch S2. This current is the
and L2 and also the output current are constant and modeled by difference between iLs and IL2. Therefore, the voltage across
a constant current source as shown in Fig. 2. Moreover, the switch S2 which is the same as VCS2 becomes equal to zero as
output voltage assumed to be almost fixed because of the large shown in Fig. 4. Thus, it is a great opportunity to apply the
output capacitor Co. To describe how the ZVS is achieved, the gate signal of switch S2 as VGS2 during this interval. So switch
detailed models of the power MOSFETs are utilized. It S2 turns on at the zero voltage.
consists of the intrinsic antiparallel diode and capacitance in Mode IV— t3 < t < t4: at the beginning of this mode, the
parallel with an ideal switch. gating signal of switch S1 is removed and it is turned off.
The operation procedure of the converter can be presented Therefore, the intrinsic capacitor CS1 is charged rapidly to
in eight modes depending on the different statuses of the VDC+VO by the sum of currents IL2 and IL1. According to Fig.
switches. Because the two buck-boost converters are 4, along with an increase in the CS1 voltage, the current iLs
completely identical, all the circuit elements such as L1, L2, begins to decrease and reverse its direction towards to -IL1
CS1 and CS2 have the same values. In all stages, the forward because VCS1 is imposed on inductor LS. By applying a KVL to
voltage drops on diodes D1 and D2 and switches S1 and S2 are the end of this mode, the voltage of diode D1 becomes equal
considered negligible. The equivalent circuit of each mode is to zero. Thus, it begins to freewheel the load current. Due to
shown in Fig. 3. The elements which are conduct are the symmetry of the proposed converter, mode V to VIII could
distinguished with the elements that are not. The theoretical be summarized in similar scenarios for switch S1.
waveforms related to each mode are demonstrated in Fig. 4.
Mode I— t0 < t < t1: to describe the first mode, it is III. CIRCUIT MATHEMATICAL ANALYSIS AND DESIGN
considered that the diode D2 freewheels the load current (Io).
As it was mentioned in the previous section, the duty ratio
So according to Fig. 3 (a), the diode D2 current is equal to
of the switches must be considered slightly greater than 0.5.
IL1+IL2 and the current IL1 passes through the inductor LS,
Therefore, it causes a small overlap between the gating signals
reversely. Mode I begin when switch S1 is closed and D2
of the switches. But, the effective duty ratio is larger than that
freewheeling current is decreasing to zero. Therefore, the
of the duty ratio (D) of each of switches S1 and S2. For
voltage VDC+VO which was clamped on the capacitor CS2, is
instance, the conversion unit 1 is effectively turned on in mode
imposed on the inductor LS by the polarity depicted. Therefore,
I to III and also in mode VI to VIII a small negative current
the inductor current iLs increases linearly from -IL1 to IL2, as

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CS1 I II III IV V VI VII VIII

iS1 DS1
VG S1 , T S1
S1 i Ls D1
(VDC  Vo ) t

(VDC  Vo )
`

LS IO VGS2 , TS2
CS2
i D2
DS2 Ro Vo t
TC
S2 D2
VDC I L1 I L2 Co VDC  VO t
VCS1
(a)
VDC  VO t
VCS2
CS1
Io t
iS1 DS1 i D1
S1 i Ls D1
(VDC  Vo ) Io t
(VDC  Vo )

IO iD2
CS2
LS
Vo IL1  IL2 t
DS2 Ro i S1
S2 D2
I L2 Co IL1  IL2 t
VDC I L1 iS 2

t
(b) i LS I L2

t
CS1  I L1
iS1 DS1 i L1
S1 i Ls D1
` t
LS IO i L2
CS2
iS2 DS2 i D S2 Ro Vo
t
S2 D2 t0 t1 t 2 t 3t4 t5 t6 t 7t 8
VDC I L1 I L2 Co
Fig. 4. Theoretical waveforms of the key components.

passes through S1. Therefore, it is effectively turned off just in

(c)
mode V. Similarly, the conversion unit 2 is effectively turned
(VDC  Vo )
off in mode I. According to Fig. 4, since the effective turn off
CS1
i D1 interval is the commutation time of inductor LS, the effective
DS1 duty ratio DE can be represented as:
S1 i Ls D1
TS  TC
(VDC  Vo )

DE  (1)
`

LS IO
CS2 TS
iS2 DS2 Ro Vo
S2 where TS and TC are the switching and commutation times,
D2
respectively. As shown in Fig. 4, in the time interval TC, iLs
VDC I L1 I L2 Co
almost swings between the values of IL1 and IL2 and vice versa,
and because the voltage across the inductor LS is clamped at
(d)
Fig. 3. Equivalent circuit diagrams of different operation modes. (a) mode I, VDC+VO, the commutation time can be represented as follows:
(b) mode II, (c) mode III, (d) mode IV.
LS (IL1  IL2 ) LS Iin
TC   (2)
VDC  VO VDC  VO

On the other hand, the relation between the output and input

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values of a usual buck-boost converter in CCM is stated as iD

follows: iD
DE ID  IO / 2
VO  VDC (3) Q
1  DE
1  DE D E TS / 2
IO  Iin (4)
DE vC VO
VO
Therefore, inserting (3) and (4) in (2), the commutation time
TC can be represented in terms of the output current, input
voltage, and the inductance LS as bellows:
Fig. 5. Diode current and output voltage ripple across the output capacitance.

D E LS
TC  IO (5) Iin  IO V  VO
VDC  DC (9)
(1  DE )TS LS
Combining (1) with (5), the effective duty ratio of the
converter can be obtained as: Simplifying (9) by substituting (3) and (4), results in the value
of the inductance LS for a specified input DC voltage as
follows:
1 (6)
DE 
f S LS
1 IO (1  DE )VDC
VDC LS  (10)
f S IO
The voltage ratio of the converter can be obtained by
Inductances L1 and L2 are obtained by considerations the
inserting (6) in (3) in terms of switching frequency, load
magnitude of the iL1 and iL2 current ripples. The maximum
resistance, and the value of the inductance LS.
permissible current ripple should not exceed the rated output
current, so the converter could operate in the CCM. Thus,
R considering modes I and V, iL1 and iL2 are decreased due to
VO  VDC (7)
f S LS voltage -VO which is clamped at the inductances L1 and L2.
Therefore, the value of inductances L1 and L2 should meet the
Therefore, it can be concluded that the control over the output following constraint.
voltage could be possible by modifying the switching
frequency fS while not changing the duty ratio of the switches DE VDC
L1,2  (11)
like conventional buck-boost converters. fS IO
Since the effective turn off interval of the converter is just
in mode I and V, and also it is known that at these intervals the To determine the value of the output capacitor, it is
current of the interleaved inductor LS swings between values considered that the ripple and the average value of the
–IL1 and IL2, therefore, considering these intervals to be (1- converter output current flow to the output capacitor Co and
DE)TS, the following equation can be written for inductor LS. the load, respectively. On the other hand, the current of the
diode in the buck-boost converter can be considered equal to
di Ls I I V the output current. Therefore, the ripple of the diode current
 L1 L2  Ls (8)
dt (1  DE )TS LS causes the ripple in the output voltage across capacitance Co as
indicated in Fig. 5. Because the two conversion units work in
As it is indicated in Fig. 4, the voltage across the inductor LS is parallel, the average current of each diode can be assumed to
equal to VDC+VO at intervals I or V. Thus, if IL1 and IL2 are be half of the average current of the load as shown in Fig. 5.
considered equal, the variation of iLs can be assumed 2IL1. To achieve the amplitude of the output voltage ripple, the
According to Fig. 2, neglecting the ripple of inductors L1 and charge variation of capacitor Co could be easily calculated by
L2 current, the average value of iL1 is equal to half of the computing the surface ΔQ in half of the effective turn on
summation of the input and output currents. Therefore, (8) can period DETS as depicted in Fig. 5. Thus, the capacitance Co can
be represented as: be obtained as follows:

Q DE TS IO / 4 DE
CO    (12)
VO VO 4fS R (VO / VO )

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where ΔVO/VO is the relative output voltage ripple usually

considered to be less than 1 % of the output nominal voltage.
Finally, to achieve the efficiency of the proposed converter,
the switching losses should be calculated first. Fig. 4, shows
the voltage across the switch which is the same voltage of the
intrinsic capacitor and the current passes through it. According
to Fig. 4, the switching losses are existed only in modes IV
and VIII, and the current of the switches are negligible in
modes VI and II for S1 and S2, respectively. Considering the
losses equal for both of the switches, the switching loss for S1
is calculated and multiplied by 2. Assuming the current passes
through S1 constant in mode IV and equal to IL1+IL2, the total
Fig. 6. The experimental setup of the proposed converter.
switching loss can be represented as follows:
TABLE I
t4 CIRCUIT PARAMETERS
PLoss  2  (VDC  VO )t  (IL1  IL2 )dt (13) Circuit Parameters Value/Type
t3
Inductors L1 and L2 180 µH
Inductor LS 30 µH
As it is mentioned prior, IL1+IL2 can be represented as Iin+IO.
Capacitor CO 100 µF
Thus, according to (3) and (4), PLoss obtain as:
Power MOSFETs type IRF 640
t Diodes type BYV32
1 1 VDC Iin
PLoss  2 ( )VDC t  ( )Iin dt  t 2 (14)
0
1  DE DE DE (1  DE )

where, the term ∆t denotes the interval that the intrinsic

capacitor CS is charged in mode III and considered to be VGS1
CS1 (VDC  VO ) / ( I L1  I L 2 ) . Simplifying this term, PLoss is 0
obtained through (14). Therefore, the efficiency of the VGS 2
proposed converter is achieved as: 0
Fig. 7. The gate signals VGS1 and VGS2: 20 V/div, time: 2.5 µs.
PLoss C2 D V
 1  1  S1 E 3 ( DC ) 2 (15)
Pin (1  DE ) Iin voltage rather than the input voltage is directly dependent on
the selected switching frequency instead of D. Thus, the
1  DE switching frequency is selected to be approximately 133 kHz.
Substituting VDC/Iin equal to (VO / I O ) from (3) and (4), The experimental waveforms related to each of the converter
DE
elements are demonstrated in Figs. 8 and 9. Therefore, the
the efficiency could be represented as follows: adaptation between the experimental and theoretical
waveforms can be concluded.
2
PLoss CS1 To evaluate the impact of the utilized ZVS technique on the
 1 1 R2 (16) proposed converter efficiency, a comparative study should be
Pin DE (1  DE )
carried out. In this regard, one prototype single-bridge buck-
boost converter is considered with no soft switching
technique. Then, the output power is changed within the range
IV. EXPERIMENTAL RESULTS
of 100-220 W with steps of 30 W in both circuits. Both
A prototype test circuit of the proposed converter is converters are considered working in buck mode of operation
designed and implemented. The experimental setup is shown and the input voltage of the converters is assumed to be 30 V.
in Fig. 6. The values and types of the circuit elements are According to (7), the switching frequency in the proposed
listed in Table 1 according to previous considerations. The converter should alter from 300 kHz to 137 kHz to maintain
gate signals applied to the switches are depicted in Fig. 7. The the output voltage at 20 V. This is because the operation
duty ratios are considered slightly greater than 0.5. The first condition in both of the converters needs to be the same to
test is performed for a 100 W output power in the boost mode evaluate only the effect of the output power. Fig. 10, depicts
of operation of the converter, while the input and output the response of the output voltage and current due to 30 W
voltages are considered to be 20 V and 50 V, respectively. step changes in the output power. The calculated efficiencies
According to (7), it is obviously clear that for a specified in each of the investigated loads for both of the two-bridge
output power, the increment or decrement of the output proposed structure and single-bridge hard switched buck-boost

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VO

io 0 (Current)
i Ls 0

0 (Voltage)
Fig. 10. Variation of the output voltage and current due to a 30 W step change
in the output power (VO: 4 V/div, IO: 5 A/div).

iL1

iS1

iD 1

0
Fig. 11. The converter efficiency respect to change in the output power.
Fig. 8. Experimental waveforms of the inductor Ls and the key components of
the converter 1 in the proposed structure (iLS: 2 A/div, IL1: 1 A/div, iS1: 1
TABLE II
A/div, iD1: 1 A/div, time: 2.5 µs). COMPARISON WITH OTHER WORKS
Ref. [22], Ref. [23], Ref. [24],
Presented
Specifications April March February
Work
iL2 2011 2006 2014
Utilized
ZVS ZVS ZVS ZVS
method
Number of
0 2 1 1 2
converters
Best efficiency < 97 % < 95 % 98.5 % 97.7 %
iS 2 Output power
300 W 100 W 14 kW 220 W
(Max)
Output voltage
Boost Buck/Boost Buck/Boost Buck/Boost
mode
0
Interleaved
21 µH 4 mH 50 µH 30 µH
inductor
Switching
iD 2 frequency 40 kHz 100 kHz 62.5 kHz 300 kHz
(Max)
0 Number of
4 4 4 1
extra elements
Fig. 9. Experimental waveforms of the key components of the converter 2 in
the proposed structure (IL2: 1 A/div, iS2: 1 A/div, iD2: 1 A/div, time: 2.5 µs).
V. CONCLUSION
converter are indicated in Fig. 11. It could be inferred that the In this paper, a novel double-stage buck-boost converter
proposed converter develops significantly improvement in the with ZVS capability is proposed. The theoretical analysis and
converter efficiency whereas it is higher than 93% in all cases. design equations are described to achieve the soft switching
Table II contains a brief comparison between the proposed operation of the proposed converter. This goal could be
two stage structure and some of the recent publications. obtained by just an extra inductor placed between two units as
a bridge. Therefore, the reliability of the proposed converter
increases due to the simplicity of the proposed structure. It is
demonstrated that the output voltage of the converter could be
regulated by changing the switching frequency instead of the
duty ratio. A laboratory test circuit was designed and

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Nonsymmetric Multilevel Boost Converter,‖ IEEE Trans. Power [22] L. Kui-Jun, P. Byoung-Gun, K. Rae-young, H. Dong-seok, ―Nonisolated
Electronics, vol. 30, no. 3, pp. 1356-1372, March 2015. ZVT Two-Inductor Boost Converter with a Single Resonant Inductor for
[3] Qin Shibin S. T. Cady, A. D. Dominguez-Garcia, R. C. N. Pilawa- High Step-Up Applications,‖ IEEE Trans. Power Electronics, vol. 27,
Podgurski, ―A Distributed Approach to Maximum Power Point Tracking no. 4, pp. 1966 - 1973, April 2012.
for Photovoltaic Submodule Differential Power Processing,‖ IEEE [23] C. Jingquan, D. Maksimovic, R. W. Erickson, ―Analysis and Design of
Trans. Power Electronics, vol. 30, no. 4, pp. 2024-2040, April 2015. A Low-Stress Buck-Boost Converter in Universal-Input PFC
[4] Wang Yuxi, Liu Wei, Ma Hao, Chen Longyu, ―Resonance Analysis and Applications,‖ IEEE Trans. Power Electronics, vol. 21, no. 2, pp. 320 -
Soft-Switching Design of Isolated Boost Converter With Coupled 329, March 2006.
Inductors for Vehicle Inverter Application,‖ IEEE Trans. Power [24] M. Pavlovsky, G. Guidi, A. Kawamura, ―Buck/Boost DC-DC Converter
Electronics, vol. 30, no. 3, pp. 1383-1392, March 2015. Topology with Soft Switching in the Whole Operating Region,‖ IEEE
[5] C. Jiann-Jong, S. Pin-Nan, H. Yuh-Shyan, ―A High-Efficiency Positive Trans. Power Electronics, vol. 29, no. 2, pp. 851-862, Feb. 2014.
Buck Boost Converter with Mode-Select Circuit and Feed Forward
Techniques,‖ IEEE Trans. Power Electronics, vol. 28, no. 9, pp. 4240-
4247, Sept. 2013.
[6] M. Pavlovsky, G. Guidi, A. Kawamura, ―Buck/Boost DC-DC Converter
Topology with Soft Switching in the Whole Operating Region,‖ IEEE Erfan Maali Amiri was born in Behshahr, Iran, in July
Trans. Power Electronics, vol. 29, no. 2, pp. 851-862, Feb. 2014. 1989. He received his B.S. degree in electrical engineering
[7] C. Yie-Tone, S. Shin-Ming, L. Ruey-Hsun, ―Analysis and Design of a from the Noshiravani University, Babol, Iran, in 2011 and
Zero-Voltage-Switching and Zero-Current-Switching Interleaved Boost the M.S. degree in electrical engineering from Amirkabir
Converter,‖ IEEE Trans. Power Electronics, vol. 27, no. 1, pp. 161-173, University of Technology (Polytechnic), Tehran, Iran, in
Jan. 2012. 2013. Currently, hi is Ph.D. student at Amirkabir University
[8] K. Eung-Ho, K. Bong-Hwan, ―Zero-Voltage and Zero-Current of Technology (Polytechnic), since 2014.
Switching Full-Bridge Converter with Secondary Resonance,‖ IEEE His main fields of research are protection of microgrid and active
Trans. Industrial Electronics, vol. 57, no. 3, pp. 1017-1025, March distribution networks, FACTS, as well as signal processing.
2010.
[9] B. R. Lin, S. K. Chung, ―New Parallel ZVS Converter with Less Active
Switches and Smaller Output Inductance,‖ IEEE Trans. on Power Behrooz Vahidi (M’ 2000, SM’ 2004) was born in Abadan,
Electronics, vol. 29, no. 7, pp. 3297-3307, July 2014. Iran in 1953. He received the B.S. in electrical engineering
[10] Gu. Bing, J. Dominic, Chen Baifeng, Zhang Lanhua, Lai Jih-Sheng, from Sharif University of Technology, Tehran, Iran in 1980
―Hybrid Transformer ZVS/ZCS DC–DC Converter With Optimized and M.S. degree in electrical engineering from Amirkabir
Magnetics and Improved Power Devices Utilization for Photovoltaic University of Technology, Tehran, Iran in 1989. He also
Module Applications,‖ IEEE Trans. Power Electronics, vol.30, no.4, pp. received his Ph.D. in electrical engineering from UMIST,
2127-2136, April 2015. Manchester, UK in 1997. From 1980 to 1986 he worked in the
[11] Y. Jiao, S. Lu, F. C. Lee, ―Switching Performance Optimization of a field of high voltage in industry as chief engineer. From 1989 to present he
High Power High Frequency Three-Level Active Neutral Point Clamped has been with the department of electrical engineering of Amirkabir
Phase Leg,‖ IEEE Transon, Power Electronics, vol. 29, no. 7, pp. 3255- University of Technology where he is now a professor. He is selected by the
3266, July 2014. ministry of higher education of Iran and by IAEEE (Iranian Association of
[12] M. L. da S Martins, C. M. de O Stein, J. L. Russi, J. R. Pinheiro, H. L. Electrical and Electronics Engineers) as the distinguished researcher of Iran.
Hey, ―Zero-Current Zero-Voltage Transition Inverters with Magnetically Prof. Vahidi is Head of Power System group at Amirkabir University of
Coupled Auxiliary Circuits: Analysis and Experimental Results,‖ IET Technology. His main fields of research are high voltage, electrical insulation,
Power Electronics, vol. 4, no. 9, pp. 968-978, Nov. 2011. power system transient, lightning protection and pulse power technology. He
[13] L. Chen, H. Hu, Q. Zhang, A. Amirahmadi, I. Batarseh, ―A Boundary- has authored and co-authored 380 papers and 6 books on high voltage
Mode Forward Flyback Converter with an Efficient Active LC Snubber engineering and power system.
Circuit,‖ IEEE Trans. Power Electronics, vol. 29, no. 6, pp. 2944-2958,
June 2014.
[14] B. P. Divakar, K. W. E. Cheng, D. Sutanto, ―Zero-Voltage and Zero-
Current Switching Buck-Boost Converter with Low Voltage and Current
Stresses,‖ IET Power Electronics, vol. 1, no. 3, pp. 297-304, Sep. 2008.

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