ECE 554 – Digital Engineering Laboratory

FPGA Design Tutorial

Version 4.1 – Fall 2003

Matt King, Surin Kittitornkun and Charles R. Kime

Table of Contents

1. Introduction and Preparation………………………………………………………… 2

2. Design Entry…………………………………………………………………………. 3
3. Functional Simulation………………………………………………………………... 7
4. Design Synthesis……………………………………………………………………... 11
5. Post-Synthesis Simulation…………………………………………………………… 15
6. Design Implementation………………………………………………………………. 16
7. Timing (Post Implementation) Simulation…………………………………………… 21
8. Conclusion……………………………………………………………………………. 24
9. References…………………………………………………………………………….. 25
Appendixes
A. HDL Design Wizard and Language Assistant…………………………………………. 26
B. Syntax checking for HDL Synthesis vs. HDL Simulation……………………………... 29
C. Incremental Design Synthesis………………………………………………………….. 30

Changes to V.3.0
- Post-synthesis simulation has been added.
- Flow diagrams have been added.
Changes to V.3.1
- Design Synthesis: Adding Verilog cores (*.v) to FPGA Express instead of EDIF (*.edn)
- This can solve some unexpected synthesis problems when the design is more complex and help
identify the Warnings in FPGA Express.
Changes to V.4
- Updated for Xilinx Foundation 4.2i and Modelsim 5.6d
Changes to V.4.1
- Updated for Modelsim 5.7e
 1. Introductions and Preparation
The FPGA design flow can be divided into the following stages:
1. Design Entry
a) Performing HDL coding for synthesis as the target (Xilinx HDL Editor)
b) Using Cores (Xilinx Core Generator)
2. Functional Simulation of synthesizable HDL code (MTI ModelSim)
3. Design Synthesis (FPGA Express)
4. Design Implementation (Xilinx Design Manager)
5. Timing (Post Implementation) Simulation (MTI ModelSim)

This design flow is based on the assumption that the student:

1. Is familiar with HDL coding using either Verilog HDL or VHDL. See Appendix A: Design
Wizard and Language Assistant, and
2. Recognizes the difference between HDL coding for synthesis and for simulation. See Appendix
B: Syntax checking for HDL Synthesis vs. HDL Simulation.

The final ECE 554 project usually contains a big/complex subsystem, which takes a long time to
synthesize (>10 min.) and is unchanged or infrequently changed during the system debugging loop. See
Appendix C: Incremental Design Synthesis for further details.

Preparation
- Log on a Windows workstation (in 3628 Engineering Hall only).
- Create “I:\xilinx\tutorial\mac” and “I:\xilinx\tutorial\cores” directories
- Copy files from http://www.cae.wisc.edu/~ece554/s03/mac and
http://www.cae.wisc.edu/~ece554/s03/core respectively.
File name Detail
mltring.v The top most file contains the “mltring” module and other interfaces.
mac.v The top-level file contains “mac_test” module. (MAC = Multiply-ACcumulate)
mltring.ucf User constraint file contains port names and their corresponding pin location
assignments.
force.do Script file to simulate “mac.v” in ModelSim (functional)
timing_force.do Script file to simulate “mltring.v” in ModelSim (timing)
mult_4x4.* 4-by-4 bit multiplier core: .v for functional simulation, .edn for netlist
reg8b.* 8-bit register core: .v for functional simulation, .edn for netlist

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2. Design Entry

Verilog Coding Cores

HDE.exe Core generator

Design Entry

Functional Sim.
ModelSim

Verilog Synthesis
FPGA Express

Post-Syn. Sim.
ModelSim

Implementation
Design Mgr.

Timing Sim.
ModelSim

FPGA Prog.
GXSLoad

Since you’re required to do the projects in HDL (hardware description language) only, the HDL
editor is provided. All the keywords are highlighted depending on the file extension either “*.vhd” for
VHDL or “*.v” for Verilog HDL.
• Using HDL Editor
ƒ Open the HDL Editor by double clicking on the HDE icon on the desktop.
ƒ Open the top-level file: “mac.v” in “I:\xilinx\tutorial\mac” and try to understand the structure of
the multiply-accumulator. You must be able to draw a simple diagram with some useful details
described by this HDL code and show it to the instructor.
ƒ Open “mltring.v” in the same directory and find where the “mac_test” module is instantiated at a
specific line number. Show this to the instructor.
• Using Cores from Core Generator
The pre-designed functional units such as adder/subtractor, multiplier, divider, etc. are available in such a
way that they can be customized for a particular use. These functional units are called “cores.” They can
be customized and generated using “Xilinx Core Generator” which can be used in the following
procedure.
• Launch Core Generator:
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ƒ Select Start=>Programs=>Xilinx Foundation 4=>Accessories=>CORE Generator System
ƒ Select “Create a new project”
ƒ Create a new project in “I:\xilinx\tutorial\cores” as shown in the figure below and click OK.

ƒ Make sure that you read the message and Click OK

ƒ Double click on “Math Functions”=> “Adders & Subtracters”=> “Adder Subtracter” as shown.

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 ƒ Double Click “Adder Subtractor.” You will see the following display. Note that the core type
is called “logicore” version 5.0 and the vendor is Xilinx, Inc.

• Cores from other vendors are usually unavailable unless we pay for them.
• Customize and generate the core
ƒ Input the parameters exactly as shown above then click the “Generate” button.
ƒ Use the Windows Explorer to view the “I:\xilinx\tutorial\cores” directory. You should see the
following files: adder.edn, adder.veo, adder.v, adder.xco and adder.xcp as generated by Core
Generator System.
ƒ Click on the “Data Sheet” button to view information about this core.

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• Open “adder.veo” using the HDL Editor.

ƒ This file contains the instantiation template for the adder module.
ƒ Note that “adder” instantiation has already been put in “mac.v”.
• The “adder.v” is the behavioral model for the adder core to be used in functional simulation to be
performed next.
• Quit HDL Editor
ƒ File=>Exit

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3. Functional Simulation (ModelSim)

Verilog Coding Cores

HDE.exe Core generator

Design Entry

Functional Sim.
ModelSim

Verilog Synthesis
FPGA Express

Post-Syn. Sim.
ModelSim

Implementation
Design Mgr.

Timing Sim.
ModelSim

FPGA Prog.
GXSLoad

This step is equivalent to software debugging. The HDL simulator (debugger) is provided for
both functional and timing simulations. The HDL simulator is “ModelSim” from ModelTech,
Inc. It has both a graphic user interface (GUI) and scripting capability.
• Launch ModelSim.
ƒ Start=>Programs=>ModelSim SE 5.7e=>ModelSim
• Change the directory to the top-level of the design that we want to simulate.
ƒ File=>Change Directory and browse to “I:\Xilinx\tutorial\mac” then click Open.
• Create a library for simulation
ƒ File=>New=>Library and create a new library named “work”
• Compile all the design (source) files to the library you just created.
ƒ Compile=>Compile
ƒ Hold “Ctrl” key and click on “mltring.v”, and “mac.v” to compile all Verilog files
ƒ Make sure the “Library” is set to “work”
ƒ Click “Compile”

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• Compile “cores” generated by Core Generator
ƒ Navigate the “Compile HDL Source Files” window to “I:\xilinx\tutorial\cores”.
ƒ Select and compile the following files one by one or all together: “adder.v”, mul4x4.v”, and
“reg8b.v”. Click “Done” button after ModelSim finishes the compilations.
ƒ In the mean time, you should look at messages listed on the ModelSim main window. Some are
the actual commands reflecting what you did to the GUI and some are warning and error
messages.
• Load the top-level (mac_test) design for simulation
ƒ Simulate=>Simulate
ƒ Click on the “Libraries” tab
ƒ Click the “Add” button by search libraries and browse to “C:\Modeltech_5.7e\core_lib”

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ƒ Click “Open” to add the library.
ƒ Repeat to add the “unisim_lib” library.

ƒ Click on the “Design” tab

ƒ Expand the “work” library by clicking on the “+” next to it
ƒ Click on “mac_test” module and then click “OK” to load the “mac_test” module.

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• Create a simulation environment, and apply stimuli to “mac_test” module from a script file
“force.do”.
ƒ Tools=>Execute Macro=>force.do
ƒ Open “force.do” and understand what it does.
• Functional verification
ƒ The waveform in the “wave” window should look similar to the following figure.
ƒ To fit the waveform to the window, use the View=>Zoom=>Full command
ƒ The module just stimulated is a multiply-accumulator with two unsigned 4-bit inputs, B and C.
The product P gets added (accumulated) to the current register value S every positive clock edge.

• Quit the simulation

ƒ At ModelSim main window type “quit –sim” to quit the simulation only.
ƒ Minimize the main ModelSim window.

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4. Design Synthesis (FPGA Express)

Verilog Coding Cores

HDE.exe Core generator

Design Entry

Functional Sim.
ModelSim

Verilog Synthesis
FPGA Express

Post-Syn. Sim.
ModelSim

Implementation
Design Mgr.

Timing Sim.
ModelSim

FPGA Prog.
GXSLoad

After we get the correct functionality of our top-level (“mac_test”) module, we must convert these
top-level design files and all generated cores to the programming file for the FPGA. The first step is
called design synthesis. In ECE554, we use FPGA Express as our synthesis tool.
• Launch FPGA Express
ƒ Start=>Programs=>Xilinx Foundation 4=>Accessories=>FPGA Express Xilinx Edition
3.6.1
• Create a new project
ƒ File=>New Project (do not use DesignWizard if presented with the option)
ƒ Navigate to “I:\xilinx\tutorial\mac”
ƒ Type in the project name “synthesis” and click the “Create” button as shown below.
ƒ Note that the “synthesis” directory is created by FPGA Express to hold its project file
“synthesis.exp” as well as our synthesized hardware (netlist file: “*.edf”).

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• Add source (design) files to the “synthesis” project
ƒ Hold “Ctrl” key and select all “*.v” files in “I:\xilinx\tutorial\mac” directory and then click Open
as shown.

• Add more source files (cores)

ƒ Click on the “WORK” library symbol.
ƒ Synthesis=>Add Source Files
ƒ Navigate the window to “cores” directory
ƒ Hold “Ctrl” key and select the following files “adder.v”, “mult_4x4.v”, and “reg8b.v” as shown
below.

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 Now all the design (source) files have been entered and analyzed by the FPGA Express. The
check mark will appear to indicate that each file is correct according to the FPGA Express. If not, the
cross mark will appear instead. The next step is to synthesize the top most (“mltring”) module.
• Synthesize the top-level (“mltring”) module
ƒ Make sure that all the sources have a “check” mark.
ƒ Expand the “mltring.v” and select “mltring” module.
ƒ Synthesis=>Create Implementation
ƒ Fill in the following parameters as shown then click OK.
ƒ Note that the Target device is as follows:
‰ Family: VIRTEX (Xilinx Virtex FPGA)
‰ Device: V800HQ240 (800,000 gates and 240-pin package)
‰ Speed grade: -4

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• After the tool finishes synthesizing, you should get Check marks on both Chips (mltring and mltring-
Optimized). In this case, The Exclamation marks on both Chips denote the warnings that you have to
be aware of. Read the warnings on “mltring-Optimized” and ask the instructors if they are
negligible. Highlight a warning or error message and press the F1 key for a more detailed
description.
• View the schematic (optional).
ƒ Select “mltring-Optimized”
ƒ Synthesis=>View Schematic
• Export the netlist file (“mltring.edf”)
ƒ Select “mltring-Optimized”
ƒ Synthesis=>Export Netlist
ƒ Note that the output file is named “mltring.edf” in “I:\xilinx\tutorial\mac\synthesis\” directory as
shown.
ƒ Click OK

• Minimize the FPGA Express window.

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5. Post-synthesis Simulation

Verilog Coding Cores

HDE.exe Core generator

Design Entry

Functional Sim.
ModelSim

Verilog Synthesis
FPGA Express

Post-Syn. Sim.
ModelSim

Implementation
Design Mgr.

Timing Sim.
ModelSim

FPGA Prog.
GXSLoad

• In the same directory I:\xilinx\tutorial\mac\synthesis\, you should be able to locate “mltring.v”.

• Double-click on “mltring.v” to open by HDL Editor.
• The file header should contain the following statements.
// Synopsys FPGA Express automatically generated file
// This file will be overwritten by each chip export
// Author: Mking
// Program: FPGA Express
// Version: 3.6.1.6817
• This “mltring.v” was also generated by FPGA Express along with the “mltring.edf”.
• We can use this file for “post-synthesis” simulation.
• Launch ModelSim again and change the directory to “I:\xilinx\tutorial\mac\”.
• Note: If you create a new library for post-synthesis simulation you will need to recompile the core
generated modules into that library.
• Compile “I:\xilinx\tutorial\mac\synthesis\mltring.v” to the “work” library.
• Load “mltring” module for simulation and Execute Macro in “timing_force.do”.
• Compare the current waveforms to the ones from functional simulation.
• Let the TAs know whether they are the same.

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 6. Design Implementation (Design Manager)

Verilog Coding Cores

HDE.exe Core generator

Design Entry

Functional Sim.
ModelSim

Verilog Synthesis
FPGA Express

Post-Syn. Sim.
ModelSim

Implementation
Design Mgr.

Timing Sim.
ModelSim

FPGA Prog.
GXSLoad

The second step in producing the programming file for the FPGA is Design Implementation. In this
process, netlists (*.edf) are translated, followed by mapping, placement, and routing. Finally, the
corresponding hardware configuration bit stream (*.bit) for programming the FPGA is generated. Design
implementation is extremely important to the success of your project. Please pay careful attention to the
errors and warnings that show up, consult with the instructors to investigate the causes if necessary, and
perform the fixes needed.
• Launch Design Manager
ƒ Start=>Programs=> Xilinx Foundation 4=>Accessories=>Design Manager
• Create a new project
ƒ File=>New Project
ƒ Select “Input Design”=>Browse to “I:\xilinx\tutorial\mac\synthesis\mltring.edf”
ƒ Note that the “Working Directory” is “I:\xilinx\tutorial\mac\synthesis\xproj” and then click OK.
ƒ Xilinx Design Manager creates the “I:\xilinx\tutorial\synthesis\xproj” directory specified as the
“Working Directory”.

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• Add a Universal Constraint File (UCF).
ƒ In The “New Version” window that appears, change the Constraints File from “None” to
“Custom”

ƒ Set the constraints file (*.ucf) by browsing to “I:\xilinx\tutorial\mac\mltring.ucf”

ƒ Uncheck the “Copy the Constraints File” option.

ƒ Click “OK” to return to the “New Version” window and “OK” again to create the new revision.

WARNING: Failure to use this file or other specified files in every Xilinx FPGA design could cause
active outputs to be connected together and result in costly damage to the FPGAs or other lab
components!

• Specify implementation options.

ƒ Click on “rev1(New, OK)”
ƒ Click Design=>Options.

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 ƒ At “Program Options, Implementation” Click “Edit Options”.
ƒ Add the path to the core-generated *.edn files:
ƒ Select “Translate”=>Macro Search Path=>Browse to “I:\xilinx\tutorial\cores\,”. Click OK.

• Produce timing reports for performance estimation

ƒ Click on “Timing Reports”=>check “Produce Logic Level Timing Report”
ƒ Click “OK”

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• Specify simulation options to generate output file for the final timing simulation stage in order to
verify the functionality whether it meets the specification.
ƒ “Simulation”=>Choose “ModelSimVHDL”=>Click “Edit Options”

ƒ Click on “General”=>Check “Correlate Simulation Data to Input Design”

ƒ Note that the output file will be named “time_sim.vhd” according to the chosen “ModelSim
VHDL” choice.

• Start implementation when every parameter is set properly.

ƒ Select “rev1 (New, OK)”
ƒ Design=>Implement
ƒ The Flow Engine should run through five implementation steps: Translate, Map, Place & Route,
Timing (Sim), and Configure, which generates the configuration bit stream. Watch the log
window for warnings and errors.

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• View the report files
ƒ Click on Utilities=>Report Browser
ƒ In particular, examine the Pad Report for I/O pin assignments. Double check if the pins assigned
in “mltring.ucf” file correspond to those in “Pad Report” and make sure that no other pins have
been assigned.

• Examine the output files

ƒ Check if the following files are up to date: “mltring.bit”, “time_sim.vhd”, and “time_sim.sdf”.
ƒ Double Click on “Pad Report”.
ƒ Open “mltring.ucf” and compare if the pin assignments are matched. Don’t continue until you
show them to the instructor.

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 7. Timing (Post Implementation) Simulation (ModelSim)

Verilog Coding Cores

HDE.exe Core generator

Design Entry

Functional Sim.
ModelSim

Verilog Synthesis
FPGA Express

Post-Syn. Sim.
ModelSim

Implementation
Design Mgr.

Timing Sim.
ModelSim

FPGA Prog.
GXSLoad

Now, we will use ModelSim to run a full timing simulation using Xilinx’s Simprim libraries.
ModelSim reads the “time_sim.sdf” file that contains the timing information from the implementation
process and annotates the timing information into the “time_sim.vhd” file.
• Change the directory to where “time_sim.vhd” is.
ƒ File=>Change Directory=>Browse to “I:\xilinx\tutorial\mac\synthesis\”
• Create a new library for timing simulation
ƒ File=>New=>Library =>Timing

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• Compile the “time_sim.vhd” to the “timing” library
ƒ Compile=>Compile
• Load the top-level (“mltring”) module from “timing” library
ƒ Simulate=>Simulate
ƒ Click on the “Libraries” tab and remove all search libraries.
ƒ Click “SDF”=>”Add...”=>”SDF File”=>Browse ”I:\xilinx\tutorial\mac\synthesis\time_sim.sdf”

ƒ Click on “Design”=>mltring=>structure then click “OK”

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• Create the simulation environment and apply the stimuli.
ƒ Tools=>Execute Macro=>Browse=>”timing_force.do”
ƒ Open ”timing_force.do” and understand what it does.
• Functional verification: Verify if the results are correct and determine the propagation time of the 8-
bit register from the waveform produced by executing the “timing_force.do” macro.

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7. Conclusion
The final directory structure of the tutorial should be similar to this figure.

Directory Created by Purpose

cores Student To hold generated cores and the “Core Gen” project
file
mac Student To hold other files in the design hierarchy
mac\work ModelSim To hold compiled modules for functional simulation
mac\synthesis FPGA Express FPGA Express working directory
mac\synthesis\chips FPGA Express To hold information on the synthesized modules
mac\synthesis\files FPGA Express For internal use
mac\synthesis\timing ModelSim To hold compiled modules for timing simulation
mac\synthesis\workdirs FPGA Express For internal use
mac\synthesis\xproj Design Manager To hold several versions and revisions of
implementation

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8. References
a. ModelSim SE/EE User’s Manual
ModelSim=>Help=>SE/EE Documentation=>SE/EE Bookcase
b. FPGA Compiler II/FPGA Express VHDL Reference Manual
FPGA Express=>Help=>VHDL Reference Manual
c. FPGA Compiler II/FPGA Express Verilog HDL Reference Manual
FPGA Express=>Help=>HDL Reference Manual
d. Xilinx Foundation 4 On-line Documentation
Start=>Programs=>Xilinx Foundation 4.2i=>Documentation
e. Xilinx Design Manager On-line Help
Design Manager=>Help=> Help Topics

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Appendixes
A. HDL Design Wizard and Language Assistant
HDL Design Wizard is a GUI tool to help the designers visually declare the interfaces of an HDL
“module” (in Verilog) and “entity” (in VHDL). Input, output or bidirectional ports are defined.
• HDL Wizard
• Double Click on “HDE” icon on the desktop
• “Create new document”=> Select Use HDL Design Wizard => “OK”
• Click “Next>”
• Select “Verilog”
• Type in the file’s name to be saved: “mac_v1”
• Enter the following I/P ports: CLK, RST, B[3:0], C[3:0], and O/P port: S[7:0] as follows
• Click “New”
• Enter the port name
• Click Up/Down button appropriately to get the desired values
• Select the correct direction
• If there is no more I/O ports to enter, click “Finish” else go back to the beginning.

• For a registered I/O port, click on the “Advanced…” button to specify.

• After entering all the I/O ports, you should see a Verilog interface file similar to the
following. Note that “mac_v1” is used as both the module name and file name which is
not necessary, be convenient and helpful. In practice, the file name has no relationship
with the module name.

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 • Add the declarations and code as necessary.
• Language Assistant
• Tools=>Language Assistant

• The Language Assistant is composed of language, synthesis, and user templates. Both Verilog
and VHDL have its own set of templates.
• The Language templates provide most of the language constructs in alphabetical order:
always, case, …
• Select “always” so that you can see the explanation and example in the right window
• Click “Use” to paste the content into the HDL file at the location pointed to by the cursor.

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• The synthesis templates provide a set of synthesizable HDL components such as barrel
shifter, comparator, etc. However, for efficient and high-speed prototyping in the FPGA, the
Core Generator System is suggested since cores use the special features, such as high-speed
carry propagation, of the FPGA effectively.
• The user templates can be customized to keep any HDL code as on-line references.

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B. Syntax Checking for HDL Synthesis vs. HDL Simulation
Note that a syntactically correct HDL module may not be synthesizable by FPGA Express. Therefore,
before functional simulation, you MUST have FPGA Express check the syntax for synthesis. This is the
difference between syntax checking for HDL synthesis and HDL simulation. Please take a look at on-line
guide for HDL (Verilog) and VHDL coding for synthesis (see References section). The Language
Assistant in App. A also provides templates in both Verilog and VHDL.
• Copy a Verilog file “non_syn.v” at http://www.cae.wisc.edu/~ece554/s03/ to your
“I:\xilinx\tutorial\mac” directory.
• Let ModelSim check the syntax
• Change the current dir. of ModelSim to “I:\xilinx\tutorial\mac”.
• Compile “non_syn.v” to “work” library.
• You should see no error or warning messages.
• Let FPGA Express check the syntax
• Go back to FPGA Express
• Add a new source file “non_syn.v” to the current project “synthesis.” FPGA Express will
automatically perform syntax checking.
• This file will not pass this step because of the “initial” statement. Look at the error message. It
should be exactly like this.
VE-19 (1 Occurrence)
Error: Initial statement not supported near symbol "initial" on line 5 in file non_syn.v
• Delete “initial Q = 1’b1;” and update the source file again. It should pass the syntax checking by
FPGA Express.
• Note that this is just one of several non-synthesizable constructs in Verilog HDL. See one of the
references for either Verilog or VHDL.
• In addition, passing the FPGA Express syntax checker does NOT always mean that the HDL code
can be synthesized correctly since problems can arise later in the synthesis process. Also,
synthesis may work, but not produce useful results. For example, you have to search the output
schematic carefully to see whether latches are inferred by your incomplete “if” or “case”
statements.

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C. Incremental Design Synthesis
The final project is usually complicated and large. A simple rule of thumb is that more complex designs
require more time to execute the design flow. This is not only for functional simulation but also for design
synthesis and implementation. To save time, we can synthesize individual modules in the design
hierarchy just once, instead of every time the top level module is synthesized.
• Go back to FPGA Express
• Synthesize “mac_test” module (in the “mac.v” file) with the Check mark on “Do not insert I/O pads”
option.
o If you can recall the synthesis procedure shown earlier, this is left unchecked. The reason is
to let FPGA Express put “I/O pads” on all of the I/O ports.
o In this case, we don’t let FPGA Express do that because this module is not at the top of the
model hierarchy. No I/O pads are needed. Otherwise, error messages will show up during the
translation phase in the implementation. See section 5 Design Implementation.
• Export netlist file “mac_test.edf” to “I:\xilinx\tutorial\mac\synthesis\” with “Export Timing
Specifications” unchecked and bus type set to “%s[%d:%d]”
• Make sure that “mac_test.edf” is present in “I:\xilinx\tutorial\mac\synthesis\” directory.
• Add the new source file (“mac_test.edf”) to the current project.
• Delete the source file (“mac.v”) from the current project.
o Click on “mac.v” icon then “Edit=>Del”.

• FPGA Express will now use the previously synthesized “mac_test” module when synthesizing
modules above it in the design hierarchy.
• At this point, the “mltring-optimized” chip must be updated.
o Select “mltring-optimized” chip icon
o Synthesis=>Force Update
• Export the netlist file “mltring.edf” of “mltring-optimized” again for the future implementation.
• Don’t forget to specify where (which directory) this new netlist file is for Xilinx Design Manager.
Please refer to Section 6, Design Implementation for more details.

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