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EE668: Modeling of Interconnect (Wires) in VLSI Systems: 1 R, L, C Models

This document discusses modeling interconnect wires in VLSI systems using lumped RLC models. It describes calculating the resistance, capacitance, and inductance of each wire segment by solving Maxwell's equations. Resistance is obtained by applying 1V and measuring current. Capacitance is obtained by charging individual wires to 1V and measuring total charge. Inductance is calculated using partial inductances based on flux linkage between wire segments. The lumped RLC model can accurately model interconnect networks at low frequencies relevant for VLSI design.

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64 views4 pages

EE668: Modeling of Interconnect (Wires) in VLSI Systems: 1 R, L, C Models

This document discusses modeling interconnect wires in VLSI systems using lumped RLC models. It describes calculating the resistance, capacitance, and inductance of each wire segment by solving Maxwell's equations. Resistance is obtained by applying 1V and measuring current. Capacitance is obtained by charging individual wires to 1V and measuring total charge. Inductance is calculated using partial inductances based on flux linkage between wire segments. The lumped RLC model can accurately model interconnect networks at low frequencies relevant for VLSI design.

Uploaded by

Chiquita White
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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EE668: Modeling of Interconnect (Wires) in

VLSI Systems
Madhav P. Desai

An electronic system can be considered as an interconnection of a set of


devices with a network of wires. We are interested in modeling this network of
wires. In this context, we can make a few observations:
1. When modeling a network of wires, our guide is the electro-magnetic field
and wave theory (as outlined by Maxwell’s equations). By a full-wave
model, we mean a time-domain model which describes the space-time
relationships betweeen the electric and magnetic fields, and the charge
and current distributions complex to evaluate.
2. At low enough frequencies (if the frequencies of interest are such that
the dimensions of the wire (say L) are much smaller than the wave-
length of the electromagnetic wave) then the steady state (phasor form)
of Maxwell’s equations can be used with reasonable accuracy (that is, the
transmission delay of the wave over the extent of the wire can be ne-
glected). At VLSI dimensions, frequency dependent effects such as the
skin-effect are not a serious issue: hence an electro-static and magneto-
static analysis at “DC” is usually sufficient.
3. The wire-network can be modeled in a lumped manner if the devices con-
nected to the wire-network do not share energy with the wire-network
through linked EM fields.
Consequently, we argue that a lumped RLC (with mutual inductances and cou-
pling capacitances) model is likely to be accurate enough for our purposes. If
necessary, we will also consider the use of distributed lumped models.

1 R,L,C models
Consider the network of wires shown in Figure 1. We assume that external
devices will connect to the terminals A, B, C, D, E, F , and the wires themselves
will be modeled by lumped equivalents. Each wire is modeled by a single RLC
section of the form shown in Figure 2.
The resistance of a wire Ri is calculated in a straightforward manner as
follows:

1
B E

Figure 1: Wire network

R2 L2
C12 C D
C2
R1 L1 L12
A B
C1 C23 L23
L13

C13

E F
R3 L3
C3

Figure 2: Lumped wire network model

2
1. A potential of 1V is applied across its ends, and the current entering the
positive terminal is measured. The ratio gives the resistance. Numerically,
this experiment can be performed as follows. Suppose that the conductiv-
ity of the wire material is σ and that the permittivity of the wire material
is ǫ. Let φ be the potential inside the wire, J be the current density vector
function inside the wire, E be the electric field vector function inside the
wire, and D be the electric displacement vector function inside the wire.
Then the following equations describe the experiment that is performed.

∇.J = 0 in the interior


J = σE
E = −∇φ
D = ǫE
∇.D = 0 in the interior
φ specified on the boundary
Z
find J.dS on S
S

where S is a surface inside the wire that covers the positive terminal.
2. If the wire has more than two terminals, a resistance matrix (or conduc-
tance matrix) is calculated.
The capacitances associated with the set of wires are
1. The self-capacitance of wire i (connected between the wire and the refer-
ence at ∞) is denoted by Ci .
2. The capacitance between wires i and j is denoted by Cij and is termed
the coupling capacitance between wires i and j.
To find the capacitances, we can perform the following experiment: Choose one
of the wires, say wire i and raise it to a potential of 1V . The remaining wires
are kept at potential 0. Now measure the charge on each wire. The charge on
wire i will then be X
Ci + Cij
j6=i

and the charge on wire j (with j 6= i) will be

−Cij

Repeat this for each wire i to get the entire set of capacitances. Numerically,
this experiment can be performed by solving the following set of equations

∇.D = 0 in the dielectric


D = ǫE
E = −∇φ

3
∇.D = 0 in the interior
φ specified on the wire boundaries
Z
find D.dS on S
S

where S is a surface which encloses one of the wires (this integral gives the total
charge on the wire). For a practical implementation of a capacitance calculator
that calculates the capacitance matrix to a high degree of accuracy, see [2].
Finally the inductance: this is a slightly complicated issue, because the
classical definition of inductance is applicable only to loops of current. However,
the concept of partial inductance as proposed by Ruehli [1] helps to overcome this
technical difficulty. Using this concept, we can talk about self and mutual partial
inductances for a given set of wires. Knowledge of partial inductances gives us
complete information about loop inductances as well (partial inductances form
a basis for the loop inductances).
To understand this, suppose you are given two closed current loops in space,
with each carrying a circulating current of 1A. Suppose that the volume current
densities corresponding to the two loops are J1 and J2 respectively. From
energy considerations, the mutual inductance between loop i and loop j can be
expressed as
Z Z
µ0 Ji (u).Jj (v)
Lij = dφ(u)dφ(v)
4π u∈Ω v∈Ω k u − v k

The concept of partial inductance is a natural extension of this formula, if in-


stead of loops 1 and 2, we work with two wires 1 and 2. If partial inductances are
calculated for a set of conductors (for n conductors, there will n(n − 1)/2 partial
mutual inductances, and n partial self inductances), then these can be used to
calculate loop inductances for loops consisting of these conductors. Computa-
tionally, this is a very expensive operation. For more details about a practical
implementation of a related approach which relies on a flux-linkage based cal-
culation, see [1].

References
[1] A. E. Ruehli, “Inductance Calculations is a Complex Integrated Circuit
Environment”, IBM Journal of Research and Development, Vol. 16, No. 5,
pp. 470-481.
[2] M.P. Desai et.al. , “An efficient capacitance extractor using floating random
walks”, preprint.

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