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Assignment 1: EE 668

This document is an assignment for an electronics course. It instructs students to simulate inverters of different sizes in 180nm and 130nm process technologies using NGSPICE. For a reference inverter, students are asked to plot input/output voltages and delay, supply/ground currents, and estimate input capacitance using the delta Q over delta V method. The document notes that delay, current, and capacitance should scale as outlined in class. Contact information is provided for TAs to help with simulations or obtaining lab accounts.

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65 views2 pages

Assignment 1: EE 668

This document is an assignment for an electronics course. It instructs students to simulate inverters of different sizes in 180nm and 130nm process technologies using NGSPICE. For a reference inverter, students are asked to plot input/output voltages and delay, supply/ground currents, and estimate input capacitance using the delta Q over delta V method. The document notes that delay, current, and capacitance should scale as outlined in class. Contact information is provided for TAs to help with simulations or obtaining lab accounts.

Uploaded by

Chiquita White
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Assignment 1: EE 668

Madhav P. Desai
January 21, 2011

1 Assignment
For this assignment, use the two model files that are available on the course web-
page (180nm TSMC and 130nm IBM processes). Each process is characterized
by a minimum dimension λ which is 90nm in the case of the 180nm process,
and 65nm in the case of the 130nm process. The supply voltage Vdd is 1.8V
for the 180nm process and 1.2V for the 130nm process. You will need to use
NGSPICE (which is installed on most PC-lab machines and in the VLSI lab). A
mini-tutorial on the use of NGSPICE has also been put on the course web-page.

1. Repeat the following in the 180nm and the 130nm technologies.


(a) Take a chain of four inverters with each inverter being four times
the size of the inverter that is driving its input. The first inverter
in the chain is to be sized so that WN = 10λ, WP = 20λ. Drive
the first inverter by a pulse input 0 → Vdd → 0 with a pulse width
of 1.3ns, and with a rise-fall time of 0.3ns. The third inverter in
the chain will be called the reference inverter. For this reference
inverter, plot the input/output voltages and find the delay from the
50% point of the input to the 50% point of the output. Also, plot
the supply/ground currents for the reference inverter. In your SPICE
model, assume that for a transistor with width W , the perimeter of
the drain/source regions is P D = P S = 2W + 5λ, and the area of
the drain/source regions is AD = AS = 10W λ.
(b) Estimate the input capacitance of the reference inverter using the
∆Q/∆V method. Note that you will get two values of the capacitance
depending on whether you integrate the voltage/current during the
rising transition or during the falling transition. Why are these not
the same?
2. Confirm that the delay/supply-current/input-capacitance of the reference
transistor scale in the manner that we outlined in class.

Note that the reference inverter can be viewed as a representative CMOS


gate for a particular technology.

1
2 Resources
The TA’s for this course are
• Neha Karanjkar ([email protected])
• Pawan Moyade ([email protected])
• Sandeep M.
All students who already have VLSI or PC lab accounts should continue to
use them for this course. Those who do not have such an account should contact
the TAs to obtain one. For help in using NGSPICE, contact your TAs.

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