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    EE668: Electrical Scaling Trends in CMOS VLSI Systems: Madhav P. Desai

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    1. As CMOS VLSI technology scales over generations with a scaling factor S of approximately 0.7, the maximum frequency of interest scales by 1/S and increases by 1.4x, while power dissipation per unit area remains unchanged. 2. The average and peak current demands per unit area scale by 1/S, and the peak rate of change of current demand scales by 1/S2. This increases pressure on interconnects as technology scales. 3. Leakage current becomes a serious problem as it scales exponentially with 1-S due to thin oxide barrier tunneling. This has been partially addressed using high-K dielectrics which allow higher physical thickness for equivalent electrical thickness.

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    EE668: Electrical Scaling Trends in CMOS VLSI Systems: Madhav P. Desai

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    1. As CMOS VLSI technology scales over generations with a scaling factor S of approximately 0.7, the maximum frequency of interest scales by 1/S and increases by 1.4x, while power dissipation per unit area remains unchanged. 2. The average and peak current demands per unit area scale by 1/S, and the peak rate of change of current demand scales by 1/S2. This increases pressure on interconnects as technology scales. 3. Leakage current becomes a serious problem as it scales exponentially with 1-S due to thin oxide barrier tunneling. This has been partially addressed using high-K dielectrics which allow higher physical thickness for equivalent electrical thickness.

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    1. As CMOS VLSI technology scales over generations with a scaling factor S of approximately 0.7, the maximum frequency of interest scales by 1/S and increases by 1.4x, while power dissipation per unit area remains unchanged. 2. The average and peak current demands per unit area scale by 1/S, and the peak rate of change of current demand scales by 1/S2. This increases pressure on interconnects as technology scales. 3. Leakage current becomes a serious problem as it scales exponentially with 1-S due to thin oxide barrier tunneling. This has been partially addressed using high-K dielectrics which allow higher physical thickness for equivalent electrical thickness.

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    © All Rights Reserved
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    48 views3 pages

    EE668: Electrical Scaling Trends in CMOS VLSI Systems: Madhav P. Desai

    Uploaded by

    Chiquita White
    1. As CMOS VLSI technology scales over generations with a scaling factor S of approximately 0.7, the maximum frequency of interest scales by 1/S and increases by 1.4x, while power dissipation per unit area remains unchanged. 2. The average and peak current demands per unit area scale by 1/S, and the peak rate of change of current demand scales by 1/S2. This increases pressure on interconnects as technology scales. 3. Leakage current becomes a serious problem as it scales exponentially with 1-S due to thin oxide barrier tunneling. This has been partially addressed using high-K dielectrics which allow higher physical thickness for equivalent electrical thickness.

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    © All Rights Reserved
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    of 3

    EE668: Electrical Scaling Trends in CMOS VLSI

    systems
    Madhav P. Desai

    The evolution of CMOS VLSI technology follows a scaling trend in which


    dimensions and operating voltages are scaled by a factor S with every genera-
    tion. This factor S is approximately 0.7, and this scaling trend has lasted over
    a period of two decades. From this, we can infer the following:
    1. The device density (number of devices/unit area) doubles with every tech-
    nology generation (1/S 2 ).
    2. The transistor oxide capacitance (per unit area) increases by a factor 1/S
    with every technology generation.
    3. The CMOS inverter delay decreases by a factor of S with every technology
    generation.
    Now consider the potential voltage and current waveforms in a CMOS circuit.
    The output of a CMOS logic gate switches between low and high levels, with
    a transition-time tR . This transition-time scales by a factor of S with every
    technology generation. If we assume that a CMOS circuit acts as a first-order
    low pass RC filter, then tR can be related to the RC time constant τ . If t10,90
    R
    is the time needed by the output waveform to change from 10% to 90% of its
    final value, then
    t10,90
    R = τ ln(9)
    so that the the 3dB frequency of the CMOS circuit as a low-pass filter is ap-
    proximately 0.35/t10,90
    R , and this frequency increases by 1/S as technology is
    scaled.
    However, the switching current drawn by a CMOS circuit has higher fre-
    quency content. For this consider, a CMOS inverter charging a load capacitance
    CL from 0 to Vdd with output transition time tR . We observe that current is
    drawn from the supply only while the output is charging. Neglecting the leakage
    current and the cross-over current, the current drawn from the supply can be
    modeled as an isosceles triangle with base width tR and area CL Vdd 1 . Thus,
    1 This approximation is justified only when the input and output transition times are

    matched, which is usually the case.

    1
    every time the inverter charges the output, a triangular pulse with height
    2CL Vdd
    Ipeak =
    tR
    is drawn from the supply. The Fourier transform of this pulse if of the form

    sinc2 (ωtR /4)

    which has a main lobe of width 2/tR Hz.


    Thus, for example, if the transition time tR is 1ns, then the output wave-
    forms of CMOS gates have significant frequency content up to 350MHz, but the
    currents drawn have frequency content up to 2GHz.
    Now, consider the scaling of the magnitudes of the supply currents. For a
    fixed physical area of the circuit, we expect the total device width in that area
    to scale by 1/S. Thus, the charge in that unit area being switched at any instant
    is proportional to
    W × L × Vdd
    tox
    which will scale as 1/S ×S ×S/S = 1, thus essentially unchanged. Consequently,
    we expect that for the same circuit area Ipeak scales as 1/S and (dI/dt)peak scales
    as 1/S 2 .
    Finally, the average current that needs to be supplied per-unit-area of the
    VLSI system is Q × f where Q is the amount of charge being switched and f
    is the rate at which switching occurs. We have seen that Q essentially remains
    unchanged, but f scales by 1/S 2 , so that the average current needed per unit
    area scales by 1/S.
    Thus, to summarize, as technology scales,
    1. The maximum frequency of interest in the VLSI system scales by 1/S
    (that is, increases by 1.4X).
    2. The power dissipation per unit area is essentially unchanged.
    3. The average current demand per unit area scales by 1/S.
    4. The peak current demand per unit area scales by 1/S.
    5. The peak rate of change of the demanded current per unit area scales by
    1/S 2 .
    It follows that the pressure on the interconnect (wires) in a VLSI system in-
    creases as technology scales. The maximum stress is observed in the wires that
    supply current to the system. We need to first understand how wires are to
    be modeled, and then to study design strategies to handle the stress placed on
    wires in a VLSI system.
    2 For a synchronous circuit, the switching rate f is related to the clock period T
    clk , which
    should ideally scale by S. In practice, difficulties in clock distribution can limit the scaling of
    the clock period.

    2
    1 The leakage current problem
    An ideal static CMOS gate should not dissipate any energy when it is not
    switching. In reality, the drain current ID and gate current IG are not 0 when
    a device is OFF.
    Unfortunately, the per-unit-width gate leakage current IOF F = ID (VGS =
    0, VDS = VDD ) has an exponential dependence on VT (why?), and

    IOF F = ID (VGS = 0, VDS = VDD ) ∝ e−νVt

    where ν is a constant. It then follows (assuming that ν and the constant of


    proportionality do not scale) that

    IOF F = ID (VGS = 0, VDS = VDD ) scales as eν(1−S)

    Consequently, the leakage power dissipation per unit area will scale by at least
    eν(1−S) because the power dissipation due to drain leakage is Vdd × IOF F × W ,
    Vdd scales as S and W per unit area scales as 1/S. This is already a serious
    concern!
    The gate leakage current is essentially due to tunneling through the thin
    oxide barrier. This problem has been addressed to a certain extent by the use
    of high-K dielectrics (high-K implies same electrical thickness tox /K with higher
    physical thickness, hence less tunneling).

    2 Reading Assignment
    For further reading, you could start with the informative Wikipedia page
    http://en.wikipedia.org/wiki/MOSFET
    You can also use the excellent text by Streetman (Solid State Electronic De-
    vices) to get a basic informal introduction. Try to find answers to the following
    questions:
    • How is the threshold voltage of an MOS transistor scaled in practice (ie.,
    how is the MOSFET modified from one technology generation to another)?
    • How is the MOSFET current ID related to VGS and VDS when VGS < VT ?
    • What are short channel effects? In particular, what is channel-length
    modulation, drain-induced-barrier lowering?

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