Chapter 7

Basic processing Unit

Chapter Objectives
• How a processor executes instructions
• Internal functional units and how they are connected
• Hardware for generating internal control signals
• The micro programming approach
• Micro program organization

Fundamental Concepts
• Processor fetches one instruction at a time, and perform the operation specified.
• Instructions are fetched from successive memory locations until a branch or a jump
instruction is encountered.
• Processor keeps track of the address of the memory location containing the next
instruction to be fetched using Program Counter (PC).
• Instruction Register (IR)

Executing an Instruction
• Fetch the contents of the memory location pointed to by the PC. The contents of this
location are loaded into the IR (fetch phase).
IR ← [[PC]]
• Assuming that the memory is byte addressable, increment the contents of the PC by 4
(fetch phase).
PC ← [PC] + 4
• Carry out the actions specified by the instruction in the IR (execution phase).

Processor Organization
Internal processor
bus

Control signals

PC

Instruction
Address
decoder and
lines
MAR control logic

Memory
bus

MDR
Data
lines IR

Constant 4 R0

Select MUX

Add
A B
ALU Sub R ( n - 1 )
control ALU
lines
Carry-in
XOR TEMP

Figure 7.1. Single-bus organization of the datapath inside a processor.

• ALU and all the registers are interconnected via a single common bus.
• The data and address lines of the external memory bus connected to the internal
processor bus via the memory data register, MDR, and the memory address register,
MAR respectively.
• Register MDR has two inputs and two outputs.
• Data may be loaded into MDR either from the memory bus or from the internal
processor bus.
• The data stored in MDR may be placed on either bus.
• The input of MAR is connected to the internal bus, and its output is connected to the
external bus.
• The control lines of the memory bus are connected to the instruction decoder and
control logic.
• This unit is responsible for issuing the signals that control the operation of all the
units inside the processor and for increasing with the memory bus.
• The MUX selects either the output of register Y or a constant value 4 to be provided
as input A of the ALU.
• The constant 4 is used to increment the contents of the program counter.

Register Transfers
 • Instruction execution involves a sequence of steps in which data are transferred from one
register to another.
• For each register two control signals are used to place the contents of that register on the
bus or to load the data on the bus into register.(in figure)
• The input and output of register Riin and Riout is set to 1, the data on the bus are loaded
into Ri.
• Similarly, when Ri out is set to 1, the contents of register Ri are placed on the bus.
• While Riout is equal to 0, the bus can be used for transferring data from other registers.

Example
• Suppose we wish to transfer the contents of register R1 to register R4. This can be
accomplished as follows.
• Enable the output of registers R1 by setting R1out to 1. This places the contents of R1 on
the processor bus.
• Enable the input of register R4 by setting R4out to 1. This loads data from the processor
bus into register R4.
• All operations and data transfers with in the processor take place with in time periods
defined by the processor clock.
• The control signals that govern a particular transfer are asserted at the start of the clock
cycle.
Bus

D Q
1
Q
Riout

Ri in
Clock

Figure 7.3. Input and output g ating for one register bit.

Performing an Arithmetic or Logic Operation

• The ALU is a combinational circuit that has no internal storage.

• ALU gets the two operands from MUX and bus. The result is temporarily stored in
register Z.
• What is the sequence of operations to add the contents of register R1 to those of R2 and
store the result in R3?
o R1out, Yin
 o R2out, SelectY, Add, Zin
o Zout, R3in
• All other signals are inactive.
• In step 1, the output of register R1 and the input of register Y are enabled, causing the
contents of R1 to be transferred over the bus to Y.
• Step 2, the multiplexer’s select signal is set to Select Y, causing the multiplexer to gate
the contents of register Y to input A of the ALU.
• At the same time, the contents of register R2 are gated onto the bus and, hence, to input
B.
• The function performed by the ALU depends on the signals applied to its control lines.
• In this case, the ADD line is set to 1, causing the output of the ALU to be the sum of the
two numbers at inputs A and B.
• This sum is loaded into register Z because its input control signal is activated.
• In step 3, the contents of register Z are transferred to the destination register R3. This last
transfer cannot be carried out during step 2, because only one register output can be
connected to the bus during any clock cycle.

Fetching a Word from Memory

• The processor has to specify the address of the memory location where this information is
stored and request a Read operation.
• This applies whether the information to be fetched represents an instruction in a program
or an operand specified by an instruction.
• The processor transfers the required address to the MAR, whose output is connected to
the address lines of the memory bus.

Memory-bus Internal processor

data lines MDRoutE MDRout bus

MDR

MDRinE MDRin

Figure 7.4. Connection and control signalsgister

for re MDR.

• At the same time , the processor uses the control lines of the memory bus to indicate
that a Read operation is needed.
• When the requested data are received from the memory they are stored in register
MDR, from where they can be transferred to other registers in the processor.
 • The response time of each memory access varies (cache miss, memory-mapped
I/O,…).
• To accommodate this, the processor waits until it receives an indication that the
requested operation has been completed (Memory-Function-Completed, MFC).
• Move (R1), R2
MAR ← [R1]
Start a Read operation on the memory bus
Wait for the MFC response from the memory
Load MDR from the memory bus
R2 ← [MDR]
• The output of MAR is enabled all the time.
• Thus the contents of MAR are always available on the address lines of the
memory bus.
• When a new address is loaded into MAR, it will appear on the memory bus at the
beginning of the next clock cycle.(in fig)
• A read control signal is activated at the same time MAR is loaded.
• This means memory read operations requires three steps, which can be described
by the signals being activated as follows
R1out,MARin,Read
MDRinE,WMFC
MDRout,R2in
Step 1 2 3

Clock

MAR in

Address

Read

MR

MDR inE

Data

MFC

MDR out

Figure 7.5. Timing of a memory Read operation.

Storing a word in Memory

Writing a word into a memory location follows a similar procedure.

The desired address is loaded into MAR.

Then , the data to be written are loaded into MDR, and a write command is issued.
Example

Executing the instruction

Move R2,(R1) requires the following steps

1 R1out,MARin

2.R2out,MDRin,Write

3.MDRoutE,WMFC
Execution of a Complete Instruction

Add (R3), R1

Fetch the instruction

Fetch the first operand (the contents of the memory location pointed to by R3)

Perform the addition

Load the result into R1

Step Action

1 PCout , MAR in , Read,Select4,Add, Zin

2 Zout , PCin , Yin , WMFC
3 MDRout , IRin
4 R3out , MAR in , Read
5 R1out , Yin , WMF C
6 MDRout , SelectY,Add, Zin
7 Zout , R1in , End

Figure7.6. Control sequencefor executionof the instruction Add (R3),R1.

 Internal processor
bus

Control signals

PC

Instruction
Address
decoder and
lines
MAR control logic

Memory
bus

MDR
Data
lines IR

Y
Constant 4 R0

Select MUX

Add
A B
ALU Sub R( n - 1)
control ALU
lines
Carry-in
XOR TEMP

Figure 7.1. Single-bus organization of the datapath inside a processor.

Execution of Branch Instructions

• A branch instruction replaces the contents of PC with the branch target address, which is
usually obtained by adding an offset X given in the branch instruction.
• The offset X is usually the difference between the branch target address and the address
immediately following the branch instruction.
• Conditional branch
Figure 7.7. Control sequence for an unconditional branch instruction.

Multiple-Bus Organization
Bus A Bus B Bus C

Incrementer

PC

Re gister
file

Constant 4
MUX

ALU R

Instruction
decoder

IR

MDR

MAR

Memory b us Address
data lines lines

Figure 7.8. Three-b us or g anization of the datapath.

 Example : Add R4, R5, R6

Hardwired Control

• To execute instructions, the processor must have some means of generating the control
signals needed in the proper sequence.
• Two categories: hardwired control and micro programmed control
• Hardwired system can operate at high speed; but with little flexibility.

Control Unit Organization

n
Detailed Control design

CLK
Clock Control step Reset
counter

Step decoder

T 1 T2 Tn

INS1
External
INS2 inputs
Instruction
IR Encoder
decoder
Condition
codes
INSm

Run End

Control signals

Figure 7.11. Separation of the decoding and encoding functions.

Generating Zin

• Zin = T1 + T6 • ADD + T4 • BR + …
Generating End

• End = T7 • ADD + T5 • BR + (T5 • N + T4 • N) • BRN +…

Branch<0
Add Branch
N N

T7 T5 T4 T5

End

Figure 7.13. Generation of the End control signal.

A Complete Processor

Instruction Inte ger Floating-point

unit unit unit

Instruction Data
cache cache

Bus interf ace

Pr ocessor

System b us

Main Input/
memory Output

Figure 7.14. Block diagram of a complete processor .

Microprogrammed Control

• Control signals are generated by a program similar to machine language programs.

• Control Word (CW); microroutine; microinstruction

MDRout

WMFC
MAR in

Select
Read
PCout

R1out

R3out
Micro -

End
PCin

R1in
Add

Z out
IRin
Yin

Zin
instruction

1 0 1 1 1 0 0 0 1 1 1 0 0 0 0 0 0
2 1 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0
3 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0
4 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0
5 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0
6 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0
7 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1

Figure 7.15An example of microinstructions for Figure 7.6.

Step Action

1 PC out , MAR in , Read, Select4, Add, Z in

2 Z out , PC in , Y in , WMF C
3 MDR out , IR in

4 R3 out , MAR in , Read

5 R1 out , Y in , WMF C
6 MDR out , SelectY, Add, Z in
7 Z out , R1 in , End

Figure 7.6. Con trol sequence for execution of the instruction Add (R3),R1.
 Starting
IR address
generator

Clock µPC

Control
store CW

Figure 7.16. Basic organization of a microprogrammed control unit.

• The previous organization cannot handle the situation when the control unit is required to
check the status of the condition codes or external inputs to choose between alternative
courses of action.
• Use conditional branch microinstruction.
Microinstructions
• A straightforward way to structure microinstructions is to assign one bit position to each
control signal.
• However, this is very inefficient.
• The length can be reduced: most signals are not needed simultaneously, and many signals
are mutually exclusive.
• All mutually exclusive signals are placed in the same group in binary coding.
Microinstruction

F1 F2 F3 F4 F5

F1 (4 bits) F2 (3 bits) F3 (3 bits) F4 (4 bits) F5 (2 bits)

0000: No transfer 000: No transfer 000: No transfer 0000: Add 00: No action
0001: PC out 001: PC in 001: MAR in 0001: Sub 01: Read
0010: MDR out 010: IR in 010: MDR in 10: Write
0011: Z out 011: Z in 011: TEMP in
0100: R0 out 100: R0 in 100: Y in 1111: XOR
0101: R1 out 101: R1 in
0110: R2 out 110: R2 in 16 ALU
functions
0111: R3 out 111: R3 in
1010: TEMP out
1011: Offset out

F6 F7 F8

F6 (1 bit) F7 (1 bit) F8 (1 bit)

0: SelectY 0: No action 0: Continue

1: Select4 1: WMFC 1: End

Figure 7.19. An example of a partial format for field-encoded microinstructions.

Further Improvement

• Enumerate the patterns of required signals in all possible microinstructions. Each

meaningful combination of active control signals can then be assigned a distinct code.
• Vertical organization
• Horizontal organization

Micro program Sequencing

• If all micro programs require only straightforward sequential execution of

microinstructions except for branches, letting a µPC governs the sequencing would be
efficient.
• However, two disadvantages:
o Having a separate micro routine for each machine instruction results in a large
total number of microinstructions and a large control store.
o Longer execution time because it takes more time to carry out the required
branches.
• Example: Add src, Rdst
• Four addressing modes: register, autoincrement, autodecrement, and indexed (with
indirect forms).
Microinstructions with Next-Address Field

IR

External Condition
Inputs codes

Decoding circuits

µA R

Control store

Next address µIR

Microinstruction decoder

Control signals

Figure 7.22. Microinstruction-sequencing organization.

• The microprogram we discussed requires several branch microinstructions, which
perform no useful operation in the datapath.
• A powerful alternative approach is to include an address field as a part of every
microinstruction to indicate the location of the next microinstruction to be fetched.
• Pros: separate branch microinstructions are virtually eliminated; few limitations in
assigning addresses to microinstructions.
• Cons: additional bits for the address field (around 1/6)
Microinstruction

F0 F1 F2 F3

F0 (8 bits) F1 (3 bits) F2 (3 bits) F3 (3 bits)

Address of next 000: No transfer 000: No transfer 000: No transfer

microinstruction 001: PCout 001: PCin 001: MARin
010: MDRout 010: IRin 010: MDRin
011: Zout 011: Zin 011: TEMPin
100: Rsrcout 100: Rsrcin 100: Yin
101: Rdstout 101: Rdstin
110: TEMPout

F4 F5 F6 F7

F4 (4 bits) F5 (2 bits) F6 (1 bit) F7 (1 bit)

0000: Add 00: No action 0: SelectY 0: No action

0001: Sub 01: Read 1: Select4 1: WMFC
10: Write
1111: XOR

F8 F9 F10

F8 (1 bit) F9 (1 bit) F10 (1 bit)

0: NextAdrs 0: No action 0: No action

1: InstDec 1: ORmode 1: ORindsrc

Figure 7.23. Format for microinstructions in the example of Section 7.5.3.

Implementation of the Microroutine

Octal
address F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10

0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1 0 0 1 0 0 0 0 0 1 1 0 0 0 0
0 0 1 0 0 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0
0 0 2 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
1 2 1 0 1 0 1 0 0 1 0 1 0 0 0 1 1 0 0 1 0 0 0 0 0 1 1 0 0 0 0
1 2 2 0 1 1 1 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1

1 7 0 0 1 1 1 1 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0
1 7 1 0 1 1 1 1 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
1 7 2 0 1 1 1 1 0 1 1 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 7 3 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 7.24. Implementation of the microroutine of Figure 7.21 using a

next-microinstruction address field. (See Figure 7.23 for encoded signals.)
R15 in R15 out R0 in R0 out

Decoder

Decoder

IR Rsrc Rdst

InstDec out
External
inputs OR
Decoding mode
circuits
Condition OR indsrc
codes

µA R

Control store

Next address F1 F2 F8 F9 F10

Rdst out

Rdst in
Microinstruction
decoder
Rsrc out

Rsrc in

Other control signals

Figure 7.25. Some details of the control-signal-generating circuitry.

 Further Discussions

• Prefetching
• Emulation