Digital Pp03 - Unsa-1 587

17/04/2018
Introducción
Digital
Fundamentals
Nine Edition
Floyd
Chapter 3
© 2008 Pearson Education

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Estructura del tema Puertas lógicas
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Representación de una puerta lógica Tabla de verdad
Estructura del tema La puerta lógica NOT
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El indicador de negación Expresión lógica de la puerta NOT
Summary Summary
A X A X
The Inverter The Inverter
The inverter performs the Boolean NOT operation. When the Example waveforms:
input is LOW, the output is HIGH; when the input is HIGH,
A
the output is LOW.
X
Input Output
A X A group of inverters can be used to form the 1’s complement
LOW (0) HIGH (1)
of a binary number: Binary number
1 0 0 0 1 1 0 1
HIGH (1) LOW(0)
The NOT operation (complement) is shown with an overbar.

Thus, the Boolean expression for an inverter is X = A. 0 1 1 1 0 0 1 0
1’s complement
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La puerta lógica AND Expresión lógica de la puerta AND
Summary Summary
A A A A
X & X X & X
The AND Gate B The AND Gate B
B B
The AND gate produces a HIGH output when all inputs are Example waveforms:
HIGH; otherwise, the output is LOW. For a 2-input gate,
A
the truth table is Inputs Output
A B X
B
0 0 0 X
0 1 0
1 0 0 The AND operation is used in computer programming as a
1 1 1 selective mask. If you want to retain certain bits of a binary
number but reset the other bits to 0, you could set a mask with
The AND operation is usually shown with a dot between the
1’s in the position of the retained bits.
variables but it may be implied (no dot). Thus, the AND
operation is written as X = A .B or X = AB. If the binary number 10100011 is ANDed with
the mask 00001111, what is the result? 00000011
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Summary Puerta lógica OR

The AND Gate
A Multisim circuit is shown. XWG1 is a word generator set in
the count down mode. XLA1 is a logic analyzer with the
output of the AND gate connected to first (upper) line of the
analyzer. What signal do you expect to on this line?
The output (line 1) will be

HIGH only when all of the
inputs are HIGH.
Expresión lógica de la puerta OR Summary

A X A ≥1 X
The OR Gate
B B
The OR gate produces a HIGH output if any input is HIGH;
if all inputs are LOW, the output is LOW. For a 2-input gate,
the truth table is Inputs Output
A B X
0 0 0
0 1 1
1 0 1
1 1 1
The OR operation is shown with a plus sign (+) between the

variables. Thus, the OR operation is written as X = A + B.
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Summary Summary
A X A ≥1 X
The OR Gate The OR Gate
B B
Example waveforms: A Multisim circuit is shown. XWG1 is a word generator set
to count down. XLA1 is a logic analyzer with the output
A connected to first (top) line of the analyzer. The three 2-input OR gates act
as a single 4-input gate. What signal do you expect on the output line?
B
The output (line 1) will be
HIGH if any input is HIGH;
X
otherwise it will be LOW.
The OR operation can be used in computer programming to set certain
bits of a binary number to 1.
ASCII letters have a 1 in the bit 5 position for lower case letters
and a 0 in this position for capitals. (Bit positions are numbered
from right to left starting with 0.) What will be the result if you
OR an ASCII letter with the 8-bit mask 00100000?
The resulting letter will be lower case.
Puerta lógica NAND Puerta lógica NAND
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Expresión lógica de la puerta NAND Summary

A X A & X
The NAND Gate
B B
The NAND gate produces a LOW output when all inputs
are HIGH; otherwise, the output is HIGH. For a 2-input
gate, the truth table is Inputs Output
A B X
0 0 1
0 1 1
1 0 1
1 1 0
The NAND operation is shown with a dot between the

variables and an overbar covering them. Thus, the NAND
operation is written as X = A .B (Alternatively, X = AB.)
Summary Summary
A X A & X
The NAND Gate The NAND Gate
B B
Example waveforms: A Multisim circuit is shown. XWG1 is a word generator set in
the count up mode. A four-channel oscilloscope monitors the
A inputs and output. What output signal do you expect to see?
B
The output (channel D) will be
X LOW only when all of the
The NAND gate is particularly useful because it is a inputs are HIGH.
“universal” gate – all other basic gates can be constructed
from NAND gates.
How would you connect a 2-input NAND gate Inputs
to form a basic inverter?
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Puerta lógica NOR Puerta lógica NOR
Expresión lógica de la puerta NOR Summary

A X A ≥1 X
The NOR Gate
B B
The NOR gate produces a LOW output if any input is
HIGH; if all inputs are HIGH, the output is LOW. For a
2-input gate, the truth table is
Inputs Output
A B X
0 0 1
0 1 0
1 0 0
1 1 0
The NOR operation is shown with a plus sign (+) between
the variables and an overbar covering them. Thus, the NOR
operation is written as X = A + B.
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Summary Puerta lógica XOR

A X A ≥1 X
The NOR Gate
B B
Example waveforms:
A
B
X
The NOR operation will produce a LOW if any input is HIGH.
+5.0 V
When is the LED is ON for the circuit shown? 330 W
A
The LED will be on when any of B X
the four inputs are HIGH. C
D
Summary Summary
A X A X A X A X
The XOR Gate =1
The XOR Gate =1
B B B B
The XOR gate produces a HIGH output only when both Example waveforms:
inputs are at opposite logic levels. The truth table is
A
Inputs Output
A B X B
0 0 0
0 1 1 X
1 0 1 Notice that the XOR gate will produce a HIGH only when exactly one
1 1 0 input is HIGH.
The XOR operation is written as X = AB + AB. If the A and B waveforms are both inverted for the above
waveforms, how is the output affected?
Alternatively, it can be written with a circled plus sign
between the variables as X = A + B. There is no change in the output.
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Puerta lógica XNOR Puerta lógica XNOR
Expresión lógica de la puerta XOR y XNOR Summary

A X A X
The XNOR Gate =1
B B
The XNOR gate produces a HIGH output only when both
inputs are at the same logic level. The truth table is
Inputs Output
A B X
0 0 1
0 1 0
1 0 0
1 1 1
The XNOR operation shown as X = AB + AB. Alternatively,
the XNOR operation can be shown with a circled dot
between the variables. Thus, it can be shown as X = A . B.
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Summary Símbolos distintivos y rectangulares

A X A X
The XNOR Gate =1
B B
Example waveforms:
A
B
X
Notice that the XNOR gate will produce a HIGH when both inputs are the
same. This makes it useful for comparison functions.
If the A waveform is inverted but B remains the same, how is
the output affected?
The output will be inverted.
Summary Summary
Fixed Function Logic Fixed Function Logic
Some common gate configurations are shown.
Two major fixed function logic families are TTL and CMOS. VCC
14 13 12 11 10 9 8
VCC
14 13 12 11 10 9 8
VCC
14 13 12 11 10 9 8
VCC
14 13 12 11 10 9 8
A third technology is BiCMOS, which combines the first

two. Packaging for fixed function logic is shown. 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7
GND GND GND GND
0.335 – 0.334 in. '00 ' 02 '04 '08
0.740 – 0.770 in. 14 13 12 11 10 9 8
VCC VCC VCC VCC
14 13 12 11 10 9 8 14 13 12 11 10 9 8 14 13 12 11 10 9 8 14 13 12 11 10 9 8 14 13 12 11 10 9 8
0.250 ± 0.010 in. 0.228 – 0.244 in.
1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7
GND GND GND GND
1 2 3 4 5 6 7 '10 '11 '20 '21
Pin no.1 Lead no.1
identifiers identifier VCC VCC VCC VCC
14 14 13 12 11 10 9 8 14 13 12 11 10 9 8 14 13 12 11 10 9 8 14 13 12 11 10 9 8
1 14
1
DIP package SOIC package 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7

GND GND GND GND
'27 '30 '32 '86
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Summary Summary
Fixed Function Logic Fixed Function Logic
Logic symbols show the gates and associated pin numbers. Data sheets include limits and conditions set by the
VCC
manufacturer as well as DC and AC characteristics. For
(14) example, some maximum ratings for a 74HC00A are:
(1) MAXIMUM RATINGS
(3)
(2) Symbol Parameter Value Unit
(1) & (3)
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V V
(4) (2)
(6) V in DC InputVoltage (Referenced to GND) – 0.5 to VCC +0.5 V V
(4) (6)
(5) V out DC Output Voltage (Referenced to GND) – 0.5 to VCC +0.5 V V
(5)
(9) I in DC Input Current, per pin ± 20 mA
(8) (9)
(8) Iout DC Output Current, per pin ± 25 mA
(10) (10)
ICC DC Supply Current, VCC and GND pins ± 50 mA
(12)
(12) PD Power Dissipation in Still Air, Plastic or Ceramic DIP † 750 mW
(11) (13) (11)
(13) SOIC Package † 500
TSSOP Package † 450
Tstg Storage Temperature –65 to + 150 °C
(7) TL Lead Temperature, 1 mm from Case for 10 Seconds °C
GND Plastic DIP, SOIC, or TSSOP Package 260
Ceramic DIP 300
Summary Summary
Programmable Logic Programmable Logic
A Programmable Logic Device (PLD) can be programmed
In general, the required logic for a PLD is developed with
to implement logic. There are various technologies
the aid of a computer. The logic can be entered using a
available for PLDs. Many use an internal array of AND
Hardware Description Language (HDL) such as VHDL.
gates to form logic terms. Many PLDs can be programmed
Logic can be specified to the HDL as a text file, a
multiple times. A A B B
schematic diagram, or a state diagram.
SRAM SRAM SRAM SRAM
cell cell cell cell
A text entry for a programming a PLD in VHDL as a 2-input
NAND gate is shown for reference in the following slide. In
SRAM SRAM SRAM SRAM this case, the inputs and outputs are first specified. Then the
cell cell cell cell
X = AB signals are described. Although you are probably not familiar
with VHDL, you can see that the program is simple to read.
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Summary RESUMEN
Programmable Logic
entity NandGate is
port(A, B: in bit;
LED: out bit);
end entity NandGate;
architecture GateBehavior of NandGate is
signal A, B: bit;
begin
X <= A nand B;
LED <= X;
end architecture GateBehavior;

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17/04/2018

© 2008 Pearson Education

Estructura del tema Puertas lógicas

Representación de una puerta lógica Tabla de verdad

Estructura del tema La puerta lógica NOT

El indicador de negación Expresión lógica de la puerta NOT

The NOT operation (complement) is shown with an overbar.

La puerta lógica AND Expresión lógica de la puerta AND

Summary Puerta lógica OR

The output (line 1) will be

Expresión lógica de la puerta OR Summary

The OR operation is shown with a plus sign (+) between the

Puerta lógica NAND Puerta lógica NAND

Expresión lógica de la puerta NAND Summary

The NAND operation is shown with a dot between the

Puerta lógica NOR Puerta lógica NOR

Expresión lógica de la puerta NOR Summary

Summary Puerta lógica XOR

Puerta lógica XNOR Puerta lógica XNOR

Expresión lógica de la puerta XOR y XNOR Summary

Summary Símbolos distintivos y rectangulares

The output will be inverted.

A third technology is BiCMOS, which combines the first

0.250 ± 0.010 in. 0.228 – 0.244 in.

DIP package SOIC package 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7

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