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Chapter 5 8051 Addressing Modes: Spring'17 Twhou 8051

This document discusses addressing modes in 8051 microcontrollers. It covers immediate and register addressing modes which allow loading values directly into registers. It also discusses direct addressing of memory locations, SFR registers, and register indirect addressing using pointers in R0 and R1. Indexed addressing mode allows accessing data elements in lookup tables efficiently. Bit addressing allows manipulating individual bits in registers and memory. Finally, it mentions the extra on-chip RAM available in the 8052 microcontroller.

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孫協廷
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67 views33 pages

Chapter 5 8051 Addressing Modes: Spring'17 Twhou 8051

This document discusses addressing modes in 8051 microcontrollers. It covers immediate and register addressing modes which allow loading values directly into registers. It also discusses direct addressing of memory locations, SFR registers, and register indirect addressing using pointers in R0 and R1. Indexed addressing mode allows accessing data elements in lookup tables efficiently. Bit addressing allows manipulating individual bits in registers and memory. Finally, it mentions the extra on-chip RAM available in the 8052 microcontroller.

Uploaded by

孫協廷
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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成功大學工程科學系

Chapter 5 8051 Addressing Modes

Spring'17 TWHou 8051


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成功大學工程科學系

• 5.1 Immediate and Register Addressing Modes


• 5.2 Accessing Memory Using Various Addressing
Modes

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5.1 Immediate and Register Addressing Modes


MOV A, #25H; LOAD 25H INTO A
MOV R4,#62 ;LOAD THE DECIMAL 62 INTO R4
MOV B, #40H ;LOAD 40H INTO B
MOV DPTR, #4521H; DPTR=4512H

MOV DPTR, #2550H; IS THE SAME AS

MOV DPL, #50H;


MOV DPH, #25H;

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IMMEDIATE ADDRESSING MODE


• MOV DPTR, #68975; ILLEGAL VALUE

• COUNT EQU 30
• ……
• MOV R4, #COUNT; R4=1E (30=1EH)
• MOV DPTR,#MYDATA; DPTR=200H

• ORG 200H
• MYDATA: DB “AMERICA”

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Register addressing mode


• MOV A, R0
• MOV R2, A
• ADD A, R5
• ADD A, R7
• MOV R6,A

• MOV DPTR, A  ERROR


• MOV DPTR, #25F5H
• MOV R7, DPL
• MOV R6,DPH

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5.2 Accessing Memory using various addr modes


• Direct addressing mode
• RAM LOCATION: 00~1FH, (register bank)
• 20~2FH, (SFR, bit addr.)
• 30~7FH (byte addr.)
• MOV R0, 40H;save RAM 40H content in R0
• MOV 56H, A;save A content into RAM 56H
• MOV R4,7FH;move RAM 7FH content to R4

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• MOV A, 4; is same as
• MOV A, R4; which means copy R4 into A

• MOV A, 7; is same as
• MOV A,R7; Which means copy R7 into A

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• MOV R2, #5 ; R2 = 05
• MOV A, 2; copy R2 to A
• MOV B, 2; copy R2 to B
• MOV 7,2 ; copy R2 to R7
• ;since “MOV R7, R2” is invalid

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• SFR registers and their addresses


• MOV 0E0H, #55H
• MOV A, #55H; these two are the same

• MOV 0F0H,#25H
• MOV B, #25H; these two are the same.

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• Table 5-1
• Example 5-1
• Example 5-2

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Register indirect addressing mode


• Register as pointer to data
• Only R0 and R1 can hold address for RAM
locations. (with the @ sign)
• MOV A, @R0; move contents of RAM
• location whose address is
• held by R0 into A
• MOV @R1,B; move contents of B into RAM
• location whose address is
• held by R1

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• Example 5-3

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• Advantage of register indirect addressing mode


– Access data dynamic rather than static
– Example 5-4, example5-5

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• Limitation of register indirect addressing mode


– Only R0 and R1 can be used
– 16 bit pointer – only DPTR is used

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– Indexed addressing mode and on-chip ROM access


– Widely used in accessing data elements of look-up
table entries located in the program ROM.
– MOVC A, @A+DPTR
– Example 5-6
– Example 5-7

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Look-up table and indexed addressing mode


• Look-up table – allows access to elements of a
frequently used table with minimum operations
• Example 5-8,
• Example 5-9

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Sec 5.3 Bit addresses for I/O and RAM


• Bit addressable RAM- only 16bytes of 128 byte internal
RAM are bit addressable.
• 20H- 2FH (128bits)
• Fig. 5-1
• Table 5-2 Single bit instructions
• SETB bit
• CLR bit
• CPL bit
• JB bit, target
• JNB bit, target
• JBC bit, target

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• I/O port bit addresses


• SFR RAM addresses
• Bit memory map
• Using BIT directive, Using EQU directive
• Registers and bit-addressablility
– Only A, B, PSW, IP, IE, ACC, SCON and TCON are
bit addressable

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Section 5.4 Extra 128-byte on-chip RA in 8052


• Table 5-4: 80H-FFH (SFR)

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End of Chapter 5

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