This document provides a quick reference card for SystemC concepts including data types, channels, modules, clocks, and fixed point types. It lists common SystemC data types like sc_int and sc_uint, channel types for communication like sc_signal and sc_fifo, and syntax for defining SystemC modules with ports. It also shows how to define clocks using the sc_clock construct and specifies fixed point data types with attributes like word length and quantization mode.
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Systemc Refcard
This document provides a quick reference card for SystemC concepts including data types, channels, modules, clocks, and fixed point types. It lists common SystemC data types like sc_int and sc_uint, channel types for communication like sc_signal and sc_fifo, and syntax for defining SystemC modules with ports. It also shows how to define clocks using the sc_clock construct and specifies fixed point data types with attributes like word length and quantization mode.
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SystemC Quickreference Card
Goorseweg 5 7475 BB Markelo For Training: www.Transfer.nl Tel +31 547 367 367 email: [email protected]
sc_main Data Types Channels
Name Methods #include "systemc.h" Scalar sc_signal read(), write(), event() // include module declarations sc_int<length> variable_name, variable_name, ...; sc_signal_rv read(), event(), write() sc_uint<length> variable_name , variable_name, ...; For vectors,, allows multiple writers int sc_main(int argc, char *agv[ ]) sc_bigint<length> variable_name , variable_name, ...; sc_signal_resolved read(), event(), write() { sc_biguint<length> variable_name , variable_name, ...; For non vectors, allows multiple writers // Create channels ??length: specifies the number of elements in the array. sc_fifo read(), nb_read(), num_available(), write(), nb_write(), sc_signal<type> signal_name, signal_name, ...; ??Rightmost is LSB(0), Leftmost is MSB (length-1). num_free() // Create clock sc_bit variable_name, variable_name, ... ; Point to point communication , one reader, one writer per fifo sc_clock clock_name ("name", period, duty_cycle, start_time, positive_first ); ??Values: '0' , '1' sc_mutex kind(), lock(), trylock(), unlock() // Module instantiations sc_bv<length> variable_name, variable_name, ... ; Multipoint communication, only one writer/reader at the time module_name instance_name("name") ; ??length: specifies the number of elements in the array. sc_semaphore kind(), wait(), trywait(), get_value(), post() // Module port bindings ??Values: '0' , '1'. More than one bit represented by "0011". Limited concurrent access, specify number of concurrent users // By name binding, do for each port sc_logic variable_name, variable_name, … ; sc_buffer kind() instance_name.port_name (signal_name) ; ??Values: '0' , '1', 'X', 'Z' Like sc_signal, value_change_event() and default_event() are triggered on each write // By order port binding sc_lv<length> variable_name, variable_name, ... ; instance_name ( signal_name, signal_name, … ) ; ??length: specifies the number of elements in the array. // By order using stream ??Values: '0' , '1', 'X', 'Z' . More than one bit represented by "0011XXZZ". Resolved ports/signals instance_name << signal_name << signal_name, ...; // Clock generation Syntax: sc_start(value); Fixedpoint SC_MODULE ( module_name) { // ports return 0; sc_fixed<wl, iwl, q_mode, o_mode, n_bits> object_name, object_name, ... ; sc_in_rv<N> port_name, port_name,...; } sc_ufixed<wl, iwl, q_mode, o_mode, n_bits> object_name, object_name, ... ; sc_out_rv<N> port_name, port_name,...; sc_fixed_fast<wl, iwl, q_mode, o_mode, n_bits> object_name, object_name, ..; sc_inout_rv<N> port_name, port_name,...; sc_ufixed_fast<wl, iwl, q_mode, o_mode, n_bits> object_name, object_name. ; sc_signal_rv<N> signal_name,signal_name,. ; wl: total word length, number of bits used in the type Clock syntax iwl: integer word length, number of bits to the left of the binary point (.) // rest of module }; // N is the number of bits q_mode: quantization mode // Every bit can have either a 0, 1, X or Z value sc_clock clock_name ("name", period, duty_cycle, start_time, positive_first ) ; o_mode: overflow mode name: name type: char * n_bits: number of saturated bits, used for overflow mode period: clock period type: variable of type sc_time or constant of type uint64 sc_fix object_name (list of options) ; sc_signal channel methods duty_cycle: clock duty cycle type: double default value: 0.5 sc_fix_fast object_name (list of options) ; read() retunrs value of signal or port start_time: time of first edge type: variable of type sc_time or sc_ufix object_name (list of options) ; write() assigns value to signal or port constant of type uint64 sc_ufix_fast object_name (list of options) event() returns true or false if event on signal or port default value: 0 default_event() any change of value positive_first: first edge positive type: bool default value: true q_mode: SC_RND, SC_RND_ZERO, SC_RND_MIN_INF, SC_RND_INF, value_changed_event() any change of value SC_RND_CONV, SC_TRN, SC_TRN_ZERO posedge() returns true if 0 -> 1 transition ? o_mode: SC_SAT, SC_SAT_ZERO, SC_SAT_SYM, SC_WRAP, SC_WRAP_SM negedge() returns true if 1 -> 0 transition
Clock object methods: Data Operations/Functions
clock_name.name() returns the "name" Modules clock_name.period() returns the clock period Type sc_bit sc_bc sc_int, sc_uint sc_fixed, clock_name.duty_cycle() returns the clock duty cycle sc_bc sc_lv sc_bigint, sc_ufixed, sc_fix, // Header file Operation SC_MODULE(module_name) { clock_name.pos() Gives a reference to the positive edge of clk sc_lv sc_biguint sc_ufix // module port declarations usage: sensitive << clock_name.pos() Bitwise ~&^ | ~ & ^ | << >> ~ & ^ | << >> ~&^ | // signal variable declarations clock_name.neg() Gives a reference to the negative edge of clk Arithmetic +-*/% + - * / % >> << // data variable declarations usage: sensitive << clock_name.neg() Logical // process declarations // other method declarations Equality == != == != == != == != // module instantiations Relational > < <= >= SC_CTOR(module_name){ Clock functions Assignment = &= |= ^= = &= |= ^= = += -= *= /= %= &= |= ^= = += -= *= /= %= &= |= ^= // process registration & declarations of sensitivity lists // module instantiations & port connection declarations sc_start() Generate the waveforms for all sc_clock objects // global watching registration sc_stop() Stops simulations } sc_time_stamp() Returns the current simulation time as sc_time Increment ++ -- ++ -- Decrement }; sc_simulation_time() Returns the current simulation time as double Arithmetic if // Implementation file Concatenation , , , , void module_name::process_or_method_name() { Bitselect [x] [x] // process implementation Partselect range() range() // SC_THREAD and SC_CTHREAD has Reduction and_reduce // while(true) loop or_reduce } xor_reduce Transfer SystemC Quickreference Card Goorseweg 5 7475 BB Markelo For Training: www.Transfer.nl Tel +31 547 367 367 email: [email protected]
Scalar Syntax: Processes Style 2
// Header file // Header file SC_MODULE(module_name) { SC_MODULE(module_name) { SC_MODULE(module_name) { // ports // module port declarations // module port declarations // signal variable declarations sc_in<port_type> port_name, port_name,... ; // signal variable declarations sc_out<port_type> port_name, port_name,... ; // data variable declarations // data variable declarations // process declarations sc_inout<port_type> port_name, port_name,... ; // process declarations sc_port<channel_type<port_type>, connections > port_name, port_name,... ; // other method declarations void process_name_A(); module_name_A *instance_name_A; // module instantiation.. sc_port<channel_type<port_type>, connections > port_name, port_name,... ; void process_name_B(); sc_port<channel_type<port_type>, conections > port_name, port_name,... ; module_name_N *instance_name_N; // module instantiation void process_name_C(); SC_CTOR(module_name) // clock input (for SystemC 2.0 it is recommended to use sc_in<bool>) // other method declarations sc_in_clk clock_name; { // module instantiations instance_name_A = new module_name_A("name_A"), // clock output (for SystemC 2.0 is is recommended to use sc_out<bool>) SC_CTOR(module_name){ sc_out_clk clock_name; instance_name_N = new module_name_N("name_N") // process registration instance_name_A->port_1(signal_or_port); // signals SC_METHOD(process_name_A); sc_signal<signal_type> signal_name, signal_name, ...; instance_name_A->port_2(signal_or_port); // Sensitivity list (*instance_name_N)(signal_or_port, signal_or_port,...); // variables SC_THREAD(process_name_B); type variable_name, variable_name...; // process registration & declarations of sensitivity lists // Sensitivity list // global watching registration // rest of module}; SC_CTHREAD(process_name_C, clock_edge_reference); } //clock_name.pos() or clock_name.neg() }; // global watching registration Array Syntax: // no sensitivity list / module instantiations & port connection declarations Watching } SC_MODULE ( module_name) { }; // ports // Header file sc_in<port_type> port_name[size], port_name[size], ... ; SC_MODULE(module_name) { sc_out<port_type> port_name[size], port_name[size], ... ; Sensitivity list // module port declarations // signal variable declarations sc_inout<port_type> port_name[size], port_name[size], ...; Sensitive to any change on port(s) or signal(s) sc_port<channel_type <port_type>, connections >port_name[size], port_name[size], ... ; // data variable declarations sensitive(port_or_signal) // process declarations sc_port<channel_type <port_type>, connections >port_name[size], port_name[size], ... ; sensitive << port_or_signal << port_or_signal … ; sc_port<channel_type <port_type>, connections >port_name[size], port_name[size], ...; void process_name();// other method declarations Sensitive to the positive edge of boolean port(s) or signal(s) // module instantiations // signals sensitive_pos(port_or_signal) sc_signal<signal_type> signal_name [size], signal_name [size], ... SC_CTOR(module_name){ sensitive_pos << port_or_signal << port_or_signal … ; SC_CTHREAD(process_name, clock_edge_reference // global watching registration // variables Sensitive to the negative edge of boolean port(s) or signal(s) type variable_name[size], variable_name[size],...;; watching (reset.delayed() = = 1); // delayed() method required sensitive_neg(port_or_signal) } // rest of module sensitive_neg << port_or_signal << port_or_signal … ; }; Event Module instantiation sc_event my_event; // event sc_time t_zero (0,sc_ns); Module inheritance sc_time t(10, sc_ms); // variable t of type sc_time Style 1 // Header file Immediate: SC_MODULE( base_module ) SC_MODULE(module_name) { my_event.notify(); { // module port declarations notify(my_event); ... // signal variable declarations Delayed: // constructor // data variable declarations my_event.notify(t_zero); // next delta cycle SC_CTOR( base_module ) // process declarations notify(t_zero, my_event); // next delta cycle { ... } // other method declarations Timed: }; module_name_A instance_name_A; // module instantiation.. my_event.notify(t); // 10 ms delay class derived_module : public base_module module_name_N instance_name_N; // module instantiation notify(t, my_event); // 10 ms delay { // process(es) void proc_a(); SC_CTOR(module_name): instance_name_A("name_A"), Dynamic sensitivity SC_HAS_PROCESS( derived_module ); instance_name_N("name_N") // parameter(s) { wait for an event in a list of events: int some_parameter; // by name port binding wait(e1); // constructor instance_name_A.port_1(signal_or_port); wait(e1 | e2 | e3); derived_module( sc_module_name name_, int some_value ) // by order port binding wait( e1 & e2 & e3); : base_module( name_ ), some_parameter( some_value ) instance_name_N(signal_or_port, signal_or_port,...); wait for specific amount of time: { // process registration & declarations of sensitivity lists wait(200, sc_ns); SC_THREAD( proc_a ); // global watching registration wait on events with timeout: } } wait(200, sc_ns, e1 | e2 | e3); }; }; wait for number of clock cycles: wait(200); // wait for 200 clock cycles, only for SC_CTHREAD wait for one delta cycle: wait( 0, sc_ns ); // wait one delta cycle. wait( SC_ZERO_TIME ); // wait one delta cycle.