LM5170-Q1 Multiphase Bidirectional Current Controller: 1 Features 3 Description

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LM5170-Q1
SNVSAQ6 – NOVEMBER 2016
LM5170-Q1 Multiphase Bidirectional Current Controller

1 Features 3 Description
1• AEC-Q100 Qualified for Automotive Applications: The LM5170-Q1 controller provides the essential high
voltage and precision elements of a dual-channel
– Device Temperature Grade 1: –40°C to bidirectional converter for automotive 48-V and 12-V
+125°C Ambient Operating Range dual battery systems. It regulates the average current
– Device HBM ESD Classification Level 2 flowing between the high voltage and low voltage
– Device CDM ESD Classification Level C4B ports in the direction designated by the DIR input
signal. The current regulation level is programmed
• 100-V HV-Port and 65-V LV-Port Max Ratings through analog or digital PWM inputs.
• 1% Accurate Bidirectional Current Regulation
Dual-channel differential current sense amplifiers and
• 1% Accurate Channel Current Monitoring dedicated channel current monitors achieve typical
• 5-A Peak Half-Bridge Gate Drivers current accuracy of 1%. Robust 5-A half-bridge gate
• Programmable or Adaptive Dead-Time Control drivers are capable of driving parallel MOSFET
switches delivering 500 W or more per channel. The
• Programmable Oscillator Frequency With Optional
diode emulation mode of the synchronous rectifiers
Synchronization to External Clock prevents negative currents but also enables
• Independent Channel Enable Control Inputs discontinuous mode operation for improved efficiency
• Analog and Digital Channel Current Control Inputs with light loads. Versatile protection features include
cycle-by-cycle current limiting, overvoltage protection
• Programmable Cycle-by-Cycle Peak Current Limit
at both HV and LV ports, MOSFET failure detection
• HV and LV Port Overvoltage Protection and overtemperature protection.
• Diode Emulation Prevents Negative Current
An innovative average current mode control scheme
• Programmable Soft-Start Timer maintains constant loop gain allowing a single R-C
• MOSFET Failure Detect at Start-Up and Circuit network to compensate both buck and boost
Breaker Control conversion. The oscillator is adjustable up to 500 kHz
and can synchronize to an external clock. Multiphase
• Multiphase Operation Phase Adding or Dropping
parallel operation is achieved by connecting two
LM5170-Q1 controllers for 3 or 4-phase operation, or
2 Applications by synchronizing multiple controllers to phase-shifted
• Automotive Dual Battery Systems clocks for a higher number of phases. A low state on
• Super-Cap or Battery Backup Power Converters the UVLO pin disables the LM5170-Q1 in a low
current shutdown mode.
• Stackable Buck or Boost Converters
Device Information(1)
Simplified Application Circuit
PART NUMBER PACKAGE BODY SIZE (NOM)
HV-Port LV-Port
LM5170-Q1 TQFP (48) 6.00 mm × 6.00 mm
(48 V) (12 V)
(1) For all available packages, see the orderable addendum at
+10 V Bias the end of the data sheet.
HO1 SW1 LO1 PGND VCC

VIN CSA1 Channel Current Tracking ISETA Command
VINX CSB1
RAMP1 IOUT1
OVPA IOUT2
LM5170-Q1 IPK
OSC
RAMP2
SYNCOUT
ISETD AGND
SYNCIN
ISETA OVPB
DIR
EN1 CSB2
EN2 CSA2
HO2 SW2 LO2
Copyright © 2016, Texas Instruments Incorporated

1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5170-Q1
SNVSAQ6 – NOVEMBER 2016 www.ti.com
Table of Contents
1 Features .................................................................. 1 7.5 Programming........................................................... 37
2 Applications ........................................................... 1 8 Application and Implementation ........................ 39
3 Description ............................................................. 1 8.1 Application Information............................................ 39
4 Revision History..................................................... 2 8.2 Typical Application .................................................. 47
5 Pin Configuration and Functions ......................... 3 9 Power Supply Recommendations...................... 58
6 Specifications......................................................... 6 10 Layout................................................................... 59
6.1 Absolute Maximum Ratings ...................................... 6 10.1 Layout Guidelines ................................................. 59
6.2 ESD Ratings ............................................................ 6 10.2 Layout Examples................................................... 60
6.3 Recommended Operating Conditions....................... 6 11 Device and Documentation Support ................. 63
6.4 Thermal Information .................................................. 7 11.1 Device Support...................................................... 63
6.5 Electrical Characteristics........................................... 7 11.2 Receiving Notification of Documentation Updates 63
6.6 Typical Characteristics ............................................ 11 11.3 Community Resources.......................................... 63
7 Detailed Description ............................................ 14 11.4 Trademarks ........................................................... 63
7.1 Overview ................................................................. 14 11.5 Electrostatic Discharge Caution ............................ 63
7.2 Functional Block Diagram ....................................... 15 11.6 Glossary ................................................................ 63
7.3 Feature Description................................................. 16 12 Mechanical, Packaging, and Orderable
7.4 Device Functional Modes........................................ 32 Information ........................................................... 63
4 Revision History
DATE REVISION NOTES
November 2016 * Initial release.
2 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: LM5170-Q1

LM5170-Q1
www.ti.com SNVSAQ6 – NOVEMBER 2016
5 Pin Configuration and Functions
PHP Package
48-Pin TQFP
Top View
SYNCOUT
SYNCIN
ISETD
AGND
ISETA
IOUT2
IOUT1
OSC
EN2
EN1
DIR
DT
48
47
46
45
44
43
42
41
40
39
38
37
CSA2 1 36 CSA1
CSB2 2 35 CSB1
NC 3 34 BRKG
VINX 4 33 BRKS
NC 5 32 NC
VIN 6 31 VCCA
NC 7 30 IPK
RAMP2 8 29 OPT
OVPA 9 28 RAMP1
UVLO 10 27 nFAULT
COMP2 11 26 COMP1
SS 12 25 OVPB
13
14
15
16
17
18
19
20
21
22
23
24
SW2
HB2
HO2
NC
LO2
PGND
VCC
LO1
NC
HO1
HB1
SW1
Pin Functions
PIN
I/O (1) DESCRIPTION
NO. NAME
1 CSA2 I CH-2 differential current sense inputs. The CSA2 pin connects to the CH-2 power inductor. The CSB2 pin
connects to the circuit breaker or directly to the LV-Port if the circuit breaker is not used. The CH-2 current sense
2 CSB2 I resistor is placed between these two pins.
3 NC — No Connect
Internally connected to VIN pin through a cutoff switch. When the controller is shutdown, VINX is disconnected
from VIN, opening the current leakage path. When the controller is enabled, VINX is connected to VIN and
4 VINX O
serves as the pullup supply for the RC ramp generators at the RAMP1 and RAMP2 pins. VINX also pulls up the
OVPA pin through an internal 3-MΩ resistor.
5 NC — No Connect
The input pin connecting to the HV-Port line voltage. It supplies the BRKG pin through an internal 330-µA current
6 VIN I
source.
7 NC — No Connect
(1) Note: G = Ground, I = Input, O = Output, P = Power

Copyright © 2016, Texas Instruments Incorporated Submit Documentation Feedback 3
LM5170-Q1
Pin Functions (continued)

PIN
I/O (1) DESCRIPTION
NO. NAME
The inverting input of the CH-2 PWM Comparator. An external RC circuit tied between VINX, RAMP2, and
AGND forms the ramp generator producing a ramp signal proportional to the HV-Port voltage, thus achieving a
8 RAMP2 I
voltage feedforward function. The RAMP2 capacitor voltage is reset to AGND at the end of every switching
cycle.
Connected to the noninverting input of the HV-Port overvoltage comparator. An internal 3-MΩ pullup resistor and
an external resistor across the OVPA and AGND pins form a divider that senses the HV-Port voltage. When the
9 OVPA I
OVPA pin voltage is above the 1.185-V threshold, the SS capacitor is discharged and held low until the
overvoltage condition is removed.
The UVLO pin serves as the master enable pin. When UVLO is pulled below 1.25 V, the entire LM5170-Q1 is in
a low quiescent current shutdown mode. When UVLO is pulled above 1.25 V but below 2.5 V, the LM5170-Q1
enters the initialization stage in which the nFAULT pin is first pulled up to 5 V, while the rest of the LM5170-Q1 is
10 ULVO I kept in the OFF state. When UVLO is pulled above the 2.5 V, the LM5170-Q1 enters a MOSFET failure
detection stage. If no failure is detected, the circuit breaker gate driver (BRKS and BRKG) turns on, and the
LM5170-Q1 enables the oscillator and RAMP generator, and stands by until the EN1 and EN2 commands
enable the channel.
Output of the CH-2 trans-conductance (gm) error amplifier and the noninverting input of the CH-2 PWM
11 COMP2 O
comparator. A loop compensation network must be connected to this pin.
The soft-start programming pin. An external capacitor and an internal 25-μA current source set the ramp rate of
12 SS I the COMP pins voltage during soft start. If CH-2 is enabled after CH-1 completes soft start, the CH-2 turnon will
not be controlled by the SS pin.
CH-2 switch node. Connect to the CH-2 high-side MOSFET source, the low-side MOSFET drain, and the
13 SW2 I
bootstrap capacitor return terminal.
14 HB2 P CH-2 high-side gate driver bootstrap supply input.
15 HO2 I/O CH-2 high-side gate driver output.
16 NC — No Connect
17 LO2 I/O CH-2 low-side gate driver output.
18 PGND G Power ground connection pin for the low-side gate drivers and external VCC bias supply.
VCC bias supply pin, powering the drivers. An external bias supply between 9 V to 12 V must be applied across
19 VCC I/P
the VCC and PGND pins.
20 LO1 I/O CH-1 low-side gate driver output.
21 NC — No Connect
22 HO1 I/O CH-1 high-side gate driver output.
23 HB1 P CH-1 high-side gate driver bootstrap supply input.
CH-1 switch node. Connect to the CH-1 high-side MOSFET source, the low-side MOSFET drain, and the
24 SW1 I
bootstrap capacitor return terminal.
Connected to the noninverting input of the LV-Port overvoltage comparator. An internal 1-MΩ pullup resistor and
an external resistor across the OVPB and AGND pins form the divider that senses the LV-Port voltage. When
25 OVPB I the converter operates in Boost mode the OVPB pin status is ignored. In Buck mode, when the OVPB pin
voltage is above the 1.185-V threshold, the SS capacitor is discharged and held low until the overvoltage
condition is removed.
Output of the CH-1 trans-conductance (gm) error amplifier and the noninverting input of the CH-1 PWM
26 COMP1 O
comparator. A loop compensation network must be connected to this pin.
Fault flag pin or external shutdown pin. When a MOSFET drain-to-source short circuit failure is detected before
start-up, the nFAULT pin will be internally pulled low to report the short-circuit failure, and the LM5170-Q1 will
27 nFAULT I/O remain in a disabled state. The nFAULT pin can also be externally pulled low to shut down the LM5170-Q1,
serving as a forced shutdown pin. In forced shutdown, all gate drivers turn off, and nFAULT is latched low until
the UVLO pin is pulled below 1.25 V to release the latch and initiate a new start-up.
The inverting input of the CH-1 PWM comparator. An external RC circuit tied between VINX, RAMP1, and AGND
28 RAMP1 I forms the ramp generator producing a ramp signal proportional to the HV-Port voltage, thus achieving a voltage
feedforward function. The RAMP1 capacitor voltage is reset to AGND at the end of every switching cycle.
Multiphase configuration pin. Tied to either VCCA or AGND, the OPT pin sets the phase lag of the SYNCOUT
29 OPT I
signal corresponding to 4 phase or 3 phase operation, respectively.
30 IPK I A resistor connected between IPK and AGND sets the threshold for the cycle-by-cycle current limit comparator
Analog bias supply pin. Connect VCCA to VCC through an external 25-Ω resistor. A low-pass filter capacitor is
31 VCCA I/P
required from the VCCA pin to AGND.
32 NC — No Connect.

LM5170-Q1
Pin Functions (continued)

PIN
I/O (1) DESCRIPTION
NO. NAME
Connect to the common source of the circuit breaker MOSFET pair. When the circuit breaker function is
33 BRKS O
disabled, simply connect to AGND through a 20-kΩ resistor.
Connect to the gate pins of the circuit breaker MOSFET pair. Once the LM5170-Q1 is enabled, an internal 330-
34 BRKG O µA current source starts to charge the circuit breaker MOSFET gates. The BRKG to BRKS voltage is internally
clamped at 12 V.
35 CSB1 I CH-1 differential current sense inputs. The CSA1 pin connects to the CH-1 power inductor. The CSB1 pin
connects to the circuit breaker, or directly to the LV-Port if the circuit breaker is not used. The CH-1 current
sense resistor is placed between these two current sense pins. An internal 1-MΩ resistor is connected between
36 CSA1 I the CSB1 and OVPB pins through an internal cutoff switch. During operation, the cutoff switch is closed and this
internal resistor pulls up the OVPB pins. In shutdown mode, the internal resistor is disconnected by the cutoff
switch.
CH-1 inductor current monitor pin. A current source proportional to the CH-1 inductor current flows out of this
pin. Placing a terminating resistor and filter capacitor from IOUT1 to AGND produces a DC voltage representing
37 IOUT1 O
the CH-1 DC current level. An internal 25-µA offset DC current source at the IOUT1 pin raises the active signal
to be above the ground noise, thus improving the monitor noise immunity.
CH-2 inductor current monitor pin. A current proportional to the CH-2 inductor current flows out of this pin.
Placing a terminating resistor and filter capacitor from IOUT2 to AGND produces a DC voltage representing the
38 IOUT2 O
CH-2 DC current level. An internal 25-µA offset DC current source at the IOUT2 pin raises the active signal
above the ground noise, thus improving the monitor noise immunity.
CH-1 enable pin. Pulling EN1 above 2.4 V turns off the SS pulldown and allows CH-1 to begin a soft-start
39 EN1 I sequence. Pulling EN1 below 1 V discharges the SS capacitor and holds it low. The high- and low-side gate
drivers of both channels are held in the low state when SS is discharged.
Input for an external clock that overrides the free-running internal oscillator. The SYNCIN pin can be left open or
40 SYNCIN I
grounded when it is not used.
Clock output pin and fault check mode selector. SYNCOUT is connected to the downstream LM5170-Q1 in a 3-
or 4-phase configuration. It also functions as a circuit breaker selection pin during start-up. Placing a 10-kΩ
41 SYNCOUT O
resistor from the SYNCOUT to AGND pins disables the fault check. feature. If no resistor is connected from
SYNCOUT to AGND, the fault check is enabled.
The PWM current programming pin. The inductor DC current level is proportional to the PWM duty cycle. Use
42 ISETD I either ISETA or ISETD but not both for channel current programming. When ISETD is not used, short ISETD to
AGND.
CH-2 enable pin. Pulling EN2 above 2.4 V enables CH-2. Pulling EN2 below 1 V shuts down the HO2 and LO2
43 EN2 I
drivers.
Direction command input. Pulling DIR above 2 V sets the converter to the buck mode, which commands the
current to flow from the HV-Port to LV-Port. Pulling DIR below 1 V sets the converter to the boost mode, which
44 DIR I
commands the current to flow from the LV-Port to HV-Port. If the DIR pin is left open, the LM5170-Q1 detects an
invalid command and disables both channels with the MOSFET gate drivers in the low state.
The analog current programming pin. The inductor DC current is proportional to the ISETA voltage. Use either
45 ISETA I, O ISETA or ISETD but not both for channel current programming. When ISETA is not used, connect a 100-pF to
0.1-µF capacitor from ISETA to AGND.
Analog ground reference. AGND must connect to PGND externally through a single point connection to improve
46 AGND G
the LM5170-Q1 noise immunity.
47 OSC I The internal oscillator frequency is programmed by a resistor between OSC and AGND.
A resistor connected between DT and AGND sets the dead time between the high-side and low-side driver
48 DT I
outputs. Tie the DT pin to VCCA to activate the internal adaptive dead time control.
Exposed pad of the package. No internal electrical connections. Must be soldered to the large ground plane to
— EP —
reduce thermal resistance.

LM5170-Q1
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN MAX UNIT
VIN, VINX, to AGND –0.3 95
VIN, VINX, to AGND 50-ns Transient 100
VIN to VINX –0.3 95
VIN to VINX 50-ns Transient 100
SW1, SW2 to PGND –5 95
SW1, SW2 to PGND (20-ns Transient) 100
SW1, SW2 to PGND (50-ns Transient) –16
HB1 to SW1, HB2 to SW2 –0.3 14
HO1 to SW1, HO2 to SW2 –0.3 HB + 0.3
HO1 to SW1, HO2 to SW2 (20-ns Transient) –1.5
Voltage V
LO1, LO2 to PGND –0.3 VCC + 0.3
LO1, LO2 to PGND (20-ns Transient) –1.5
BRKG, BRKS, to PGND –0.3 65
CSA1, CSB1, CSA2, CSB2 to PGND –5 65
CSA1 to CSB1, CSA2 to CSB2 –0.3 0.3
BRKG to BRKS –0.3 14
EN1, EN2, DIR, IOUT1, IOUT2, IPK, ISETA, ISETD, nFAULT,
–0.3 7
OSC, OVPA, OVPB, SYNCIN, SYNCOUT, UVLO, to AGND
PGND to AGND –0.3 0.3
VCC to PGND, VCCA, DT, OPT, COMP1, COMP2, RAMP1,
–0.3 14
RAMP2, SS, to AGND
TJ Operating junction temperature –40 150 °C
Tstg Storage temperature –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) For soldering specs, see www.ti.com/packaging.
6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per AEC Q100-002 (1) ±2000
All pins ±500
V(ESD) Electrostatic discharge Charged-device model V
(CDM), per AEC Q100-011 Corner pins (1, 12, 13, 24, 25, 36, 37,
±750
and 48)
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) (1)
MIN NOM MAX UNIT
Buck mode 6 85
VIN, HV-Port V
Boost mode 6 85
Buck mode 0 60
LV-Port V
Boost mode 3 60
VVCC External voltage applied to VCC 9 12 V
(1) Recommended Operating Conditions are conditions under which the device is intended to be functional. For specifications and test
conditions, see the Electrical Characteristics.

LM5170-Q1
Recommended Operating Conditions (continued)

over operating free-air temperature range (unless otherwise noted)(1)
MIN NOM MAX UNIT
(2)
TJ Operating junction temperature –40 150 °C
FOSC Oscillator frequency 50 500 kHz
FEX_CLK Synchronization to external clock frequency (minimal 50 kHz) 0.8 × FOSC 1.2 × FOSC kHz
tDT Programmable dead time 15 200 ns
ISETD PWM frequency 1 100 kHz
SYNCIN pulse width 100 500 ns
(2) High junction temperatures degrade operating lifetime. Operating lifetime is de-rated for junction temperature greater than 125°C.
6.4 Thermal Information

LM5170-Q1
(1)
THERMAL METRIC PHP (TQFP) UNIT
48 PINS
RθJA Junction-to-ambient thermal resistance 29.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 14.3 °C/W
RθJB Junction-to-board thermal resistance 5.3 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
ψJB Junction-to-board characterization parameter 5.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.6 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics

FOSC = 100 kHz; VVCC = 10 V; VVIN = VHV-Port = 48 V and VLV-Port = 12 V, unless otherwise stated. (1)
PARAMETER TEST CONDITIONS MIN (2) TYP (3) MAX (2) UNIT
VIN SUPPLY (VIN, VINX)
ISHUTDOWN VIN pin current in shutdown mode VUVLO = 0 V 10 µA
VVCC > 9 V, VUVLO > 2.5 V, VEN1 = VEN2
ISTANDBY VIN pin current, no switching 1 mA
=0V
VIN to VINX disconnect switch VUVLO < 1 V or VVCC < 7.5 V 5 MΩ
VIN to VINX disconnect switch VUVLO > 2.6 V, VVCC > 9 V 100 Ω
VCC AND VCCA BIAS SUPPLIES
VCCUVLO VCC undervoltage detection VVCC falling 7.6 8 8.3 V
VCCHYS VCC UVLO hysteresis VVCC rising 8.1 8.5 8.9 V
IVCC_SD VCC sink current in shutdown mode VUVLO = 0 V 20 µA
IVCC_SB VCC sink current in standby: no switching VUVLO > 2.6 V, VEN1 = VEN2 = 0 V 10 mA
MASTER ON/OFF CONTROL (UVLO)
VUVLO_TH UVLO release threshold UVLO voltage rising 2.4 2.5 2.6 V
UVLO source current when VUVLO > 2.6
IHYS UVLO hysteresis current 21 25 29 µA
V
VSD UVLO shutdown threshold (IC shutdown) UVLO voltage falling 1 1.25 1.5 V
UVLO shutdown release UVLO voltage rising above VSD 0.15 0.25 0.35 V
tUVLO UVLO glitch filter time UVLO voltage falling 2.5 µs
UVLO internal pulldown current 1 µA
CHANNEL ENABLE INPUTS EN1 AND EN2
VIL Enable input low state Disabled the driver outputs 1 V
VIH Enable input high state Enable the driver outputs 2 V
(1) All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations and
applying statistical process control.
(2) Minimum and maximum limits apply over the –40°C to 125°C junction temperature range.
(3) Typical values correspond to TJ = 25°C.
LM5170-Q1
Electrical Characteristics (continued)

FOSC = 100 kHz; VVCC = 10 V; VVIN = VHV-Port = 48 V and VLV-Port = 12 V, unless otherwise stated.(1)
Internal pulldown impedance EN1, EN2 internal pulldown resistor 100 kΩ
EN glitch filter time (the rising and falling edges) 2 µs
DIRECTION COMMAND (DIR)
Command for current flowing from LV-Port to
VDIR Actively pulled low by external circuit 1 V
HV-Port (boost mode 12 V to 48 V)
Command for current flowing from HV-Port to
Actively pulled high by external circuit 2 V
LV-Port (buck mode 48 V to 12 V)
Standby (invalid DIR command) DIR neither active high nor active low 1.5 V
DIR glitch filter Both rising and falling edges 10 µs
ISET INPUT (ISETA, ISETD)
Regulated DC current sense voltage to ISETA
GISETA |VCSA – VCSB| = 50 mV 19.7 20 20.3 mV/V
voltage
ISETA internal pulldown resistor 170 kΩ
Conversion ratio of ISETA voltage to ISETD ISETD frequency = 10 kHz, Duty =
GISETD 30.63 31.25 31.88 mV / %
duty cycle 100%
VISETD _LO ISETD PWM signal low-state voltage 1 V
VISETD _HI ISETD PWM signal high-state voltage 2 V
ISETD internal pulldown resistor 100 kΩ
ISETD internal decoder filter resistor (tied to
100 kΩ
ISETA pin)
OUTPUT CURRENT MONITOR (IOUT1, IOUT2)
IOUT1 and IOUT2 versus channel current sense
GIOUT_BK1 |VCSA – VCSB| = 50 mV, VDIR > 2 V 4.9 5 5.1 μA/mV
voltage, in buck mode
IOUT1 and IOUT2 versus channel current sense
GIOUT_BST1 |VCSA – VCSB| = 50 mV, VDIR < 1 V 4.9 5 5.1 μA/mV
voltage, in boost mode
IOUT1 and IOUT2 versus channel current sense |VCSA – VCSB| = 10 mV, VDIR > 2 V, TJ =
GIOUT_BK2 4.91 5.18 5.43 μA/mV
voltage, in buck mode 25°C
IOUT1 and IOUT2 versus channel current sense |VCSA – VCSB| = 10 mV, VDIR < 1 V, TJ =
GIOUT_BST2 4.47 4.77 5.1 μA/mV
voltage, in boost mode 25°C
IOUT1 and IOUT2 DC offset currents |VCSA – VCSB| = 0 mV 22 25 28 µA
CURRENT SENSE AMPLIFIER (BOTH CHANNELS)
Amplifier output to current sense voltage in buck
GCS_BK1 |VCSA – VCSB| = 50 mV, VDIR > 2 V 49.25 50 50.75 V/V
mode
Amplifier output to current sense voltage in
GCS_BST1 |VCSA – VCSB| = 50 mV, VDIR < 1 V 49.25 50 50.75 V/V
boost mode
Amplifier output to current sense voltage in buck |VCSA – VCSB| = 10 mV, VDIR > 2 V, TJ =
GCS_BK2 49 52 55 V/V
mode 25°C
Amplifier output to current sense voltage in |VCSA – VCSB| = 10 mV, VDIR < 1 V, TJ =
GCS_BST2 45 48 51 V/V
boost mode 25°C
BWCS Amplifier bandwidth 10 MHz
TRANSCONDUCTION AMPLIFIER (COMP1, COMP2)
Gm Transconductance 1 mA/V
ICOMP Output source current limit VISETA = 2.5 V, |VCSA – VCSB| = 10 mV 2 mA
Output sink current limit VISETA = 0 V, |VCSA – VCSB| = 50 mV –2 mA
BWgm Amplifier bandwidth 4 MHz
PWM COMPARATOR
COMP to output delay 50 ns
COMP to PWM offset 1 V
TOFF(min) Minimum OFF time 150 200 250 ns
RAMP GENERATOR (RAMP1 AND RAMP2)
RAMP discharge device RDS(on) 15 Ω
Threshold voltage for valid ramp signal 0.6 V
PEAK CURRENT LIMIT (IPK)
IPK internal current source 22.5 25 27.5 µA

LM5170-Q1

Current sense voltage versus cycle-by-cycle
IPKBuck limit threshold voltage given at IPK pin, in buck RIPK = 40 kΩ, VDIR > 2 V 46 mV/V
mode
Current sense voltage versus cycle-by-cycle
IPKBoost limit threshold voltage given at IPK pin, in boost RIPK = 40 kΩ, VDIR < 1 V 48 mV/V
mode
OVERVOLTAGE PROTECTION (OVPA, OVPB)
OVP threshold OVP voltage rising 1.15 1.185 1.22 V
OVPHYS OVP hysteresis (falling edge) 100 mV
OVPA and OVPB glitch filter 5 µs
ROVPA Internal OVPA pullup resistor VINX to OVPA impedance 3 MΩ
CSB1 to OVPB impedance, VUVLO > 2.6
ROVPB Internal OVPB pullup resistor 1 MΩ
V
OSCILLATOR (OSC)
Oscillator frequency 1 ROSC = 40 kΩ, SYNCIN open 90 100 110 kHz
Oscillator frequency 2 ROSC = 10 kΩ, SYNCIN open 335 375 410 kHz
VOSC OSC pin DC voltage 1.25 V
SYNCIN
VSYNIH SYNCIN input threshold for high state 2 V
VSYNIL
SYNCIN input threshold for low state 1 V
SYNC
Internal pulldown impedance VSYNCIN = 2.5 V 100 kΩ

Delay to establish synchronization 0.8 × FOSC < FSYNCIN < 1.2 × FOSC 200 µs
SYNCOUT
VSYNOH SYNCOUT high state 2.5 V
VSYNOL SYNCOUT low state 0.4 V
Sourcing current when SYNCOUT in high state VSYNCOUT = 2.5 V 1 mA
SYNCOUT pulse width 240 300 370 ns
VOPT > 2 V 90
SYNCOUT phase delay configurations Degree
VOPT < 1 V 120
Use circuit breaker function and fault
OPEN
detection at start-up
RSYNCOUT Circuit breaker signature kΩ
Do not use circuit breaker function or
10
disable fault detection at start-up
BOOTSTRAP (HB1, HB2)
VHB-UV Bootstrap undervoltage threshold (VHB – VSW) voltage rising 5.7 6.5 7.3 V
VHB-UV-HYS Hysteresis 0.5 V
IHB-LK Bootstrap quiescent current VHB – VSW = 10 V, VHO – VSW = 0 V 50 µA
HIGH-SIDE GATE DRIVERS (HO1, HO2)
VOLH HO low-state output voltage IHO = 100 mA 0.1 V
VOHH HO high-state output voltage IHO = –100 mA, VOHH = VHB – VHO 0.15 V
HO rise time (10% to 90% pulse magnitude) CLD = 1000 pF 5 ns
HO fall time (90% to 10% pulse magnitude) CLD = 1000 pF 4 ns
IOHH HO peak source current VHB – VSW = 10 V 4 A
IOLH HO peak sink current VHB – VSW = 10 V 5 A
LOW-SIDE GATE DRIVERS (LO1, LO2)
VOLL LO low-state output voltage ILO = 100 mA 0.1 V
VOHL LO high-state output voltage ILO = –100 mA, VOHL = VVCC – VLO 0.15 V
LO rise time (10% to 90% pulse magnitude) CLD = 1000 pF 5 ns
LO fall time (90% to 10% pulse magnitude) CLD = 1000 pF 4 ns
IOHL LO peak source current 4 A
IOLL LO peak sink current 5 A

LM5170-Q1

INTERLEAVE PHASE DELAY FROM CH-2 To CH-1 (OPT)
VOPTL OPT input low state 1 V
VOPTH OPT input high state 2 V
HO2 on-time rising edge versus HO1 on-time VOPT > 2 V for 2, 4, 6, and 8 phases 175 180 185
rising edge, or LO2 on-time rising edge versus Degrees
LO1 on-time rising edge VOPT < 1 V for 3 phases 235 240 245
Internal pulldown impedance 1 MΩ

DEAD TIME (DT)
tDT LO falling edge to HO rising edge delay RDT = 7.5 kΩ 40 ns
tDT HO falling edge to LO rising edge delay RDT = 7.5 kΩ 40 ns
VDT DC voltage level for programming 1.25 V
DC voltage for adaptive dead time scheme only
VDT VCCA V
(short DT to VCCA)
HO-SW or LO-GND voltage threshold to enable VVCC > 9 V, (VHB – VSW) > 8 V, HO or
VADPT 1.5 V
cross output for adaptive dead time scheme LO voltage falling
tADPT LO falling edge to HO rising edge delay VDT = VVCC 36 ns
tADPT HO falling edge to LO rising edge delay VDT = VVCC 41 ns
SOFT START (SS)
ISS SS charging current source VSS = 0 V 25 µA
SS – PWM comparator noninverting
VSS-OFFS SS to PWM comparator offset 1 V
input
RSS SS discharge device RDS(on) VSS = 2 V 30 Ω
VSS_LOW SS discharge completion threshold Once it is discharged by internal logic 0.23 V
DIODE EMULATION
Current zero cross threshold Current sense voltage 0 mV
CKT BREAKER CONTROL (BRKG, BRKS)
nFAULT = 5 v, VVIN = 24 V, VBRKS = 12
IBRKG Sourcing current 275 330 375 µA
V
nFAULT= 5 V, VVIN = 48 V, VBRKS = 12
VBRK-CLP Voltage clamp 9 14 V
V
RBRK-SINK Sinking capability nFAULT = 0 V 20 Ω
BRKG to BRKS voltage threshold to indicate
VREADY Rising edge 6.5 8.5 V
readiness for operation
nFAULT= 5 V, VVIN – VBRKS = 0 V,
IBRKG-LEAK BRKG leakage current 10 µA
VBRKG – VBRKS = 10 V
FAULT ALARM (nFAULT)
In normal operation, no fault 4 5 V
Internal pull-up impedance for normal operation 30 kΩ
Internal pull-down FET RDS(on) after fault
125 Ω
detected
External pull-down voltage threshold for IC
1 V
shutdown
tFAULT External pul-ldown glitch filter 2 µs
Delay time of nFAULT pull-down below 1 V to
td1_FAULT 5 µs
(VBRKG – VBRKS) < 1.5 V
td2_FAULT Start-up fault detection duration VUVLO > 2.6 V, VVCC > 9 V 3 ms
THERMAL SHUTDOWN
TSD Thermal shutdown 175 ºC
TSD-HYS Thermal shutdown hysteresis 25 ºC

LM5170-Q1
6.6 Typical Characteristics

VVIN = 48 V, VVCC = 10 V, VUVLO = 3.3 V, TJ = 25°C, unless otherwise stated.
20 18
16
VCCA Quiescent Current (PA)

VIN Quiescent Current (PA)
15
14
10 12
10
5
8
± ƒ& 25°C 150°C ± ƒ& 25°C 150°C

0 6
0 10 20 30 40 50 60 70 80 90 100 4 6 8 10 12 14
Input Voltage (V) VCCA Voltage (V)
VUVLO = 0 V VUVLO = 0 V
Figure 1. VIN Shutdown IQ Figure 2. VCCA Shutdown IQ

7.95 8.8
7.9 8.6
VCCA Standby Current (mA)
VCC UVLO Threshold (V)
7.85 8.4
7.8 8.2
7.75 8
7.7 7.8
Falling
Rising
7.65 7.6
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Junction Temperature (°C) Junction Temperature (°C)
Figure 3. VCCA Standby Current vs Temperature Figure 4. VCC UVLO Threshold vs Temperature
105 6
IOUT1 Gain
IOUT1/2 Current Source Gain (PA/mV)
5.8 IOUT2 Gain

104
5.6
Oscillator Frequency (kHz)
103 5.4
5.2
102
5
101
4.8
100 4.6
4.4
99
4.2
98 4
-50 -25 0 25 50 75 100 125 150 0 10 20 30 40 50 60 70 80 90 100
Junction Temperature (°C) Current Sense Voltage (mV) D001
ROSC = 40.2 kΩ
Figure 5. Oscillator Frequency vs Temperature Figure 6. IOUT1/2 Current Monitor Accuracy vs VCS

LM5170-Q1
Typical Characteristics (continued)

100 50.75
Current Sense Voltage, V CS (mV)
50.5
Current Sense Voltage (mV)

80
50.25
60
50
40
49.75
20
49.5
0 49.25
0 1 2 3 4 5 -50 -25 0 25 50 75 100 125 150
Current Setting, VISETA (V) Junction Temperature (°C)
VISETA = 2.5 V
Figure 7. Regulated VCS Voltage vs ISETA Voltage Figure 8. Regulated VCS Voltage vs Temperature
600 280
500
278
IOUT1, IOUT2 (PA)
IOUT1, IOUT2 (PA)
400
276
300
274
200
272
100
IOUT1 (PA) IOUT1
IOUT2 (PA) IOUT2
0 270
0 20 40 60 80 100 -50 -25 0 25 50 75 100 125 150
Current Sense Voltage (mV) D001
Junction Temperature (°C)
VCS = 50 mV
Figure 9. IOUT1/2 Current Monitor vs VCS Voltage Figure 10. IOUT1/2 Current Monitor vs Temperature
25.2 1.19
OVP Rising Threshold Voltage (V)
25.1
1.188
25
Source Current (PA)
1.186
24.9
24.8
1.184
24.7
1.182
24.6
24.5 1.18
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Figure 11. IPK Current Source vs Temperature Figure 12. OVP Reference Voltage vs Temperature

LM5170-Q1
Typical Characteristics (continued)

3.1 1.01
OVPB Pull-up Resisitance (M:)

OVPA Pull-up Resisitance (M:)
3.05 1.005
3 1
2.95 0.995
2.9 0.99
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Figure 13. OVPA Pull-up Resistance vs Temperature Figure 14. OVPB Pull-up Resistance vs Temperature
140 80
120
Programmed Deadtime (ns)
60
Adaptive Deadtime (ns)
100
80
40
60
40
20
20 RDT = 25 k: HO to LO
RDT = 7.5 k: LO to HO
0 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
FSW = 100 kΩ VDT = VVCC
Figure 15. Programmed Dead-Time vs Temperature Figure 16. Adaptive Dead Time vs Temperature
14 450
Circuit Breaker Gate Current (PA)
12
390
10
VBRKS (V)
8
330
6
VBRKG
4
270
0 210
0 10 20 30 40 50 -50 -25 0 25 50 75 100 125 150
VVIN VCS1B (V) Junction Temperature (°C)
Figure 17. [VBRKG – VBRKS] vs [VVIN – VBRKG] Voltage Figure 18. Circuit Breaker Gate Current vs Temperature

LM5170-Q1
7 Detailed Description
7.1 Overview
The LM5170-Q1 device is a high performance, dual-channel bidirectional current controller intended to manage
current transfer between a Higher Voltage Port (HV-Port) and a Lower Voltage Port (LV-Port) like the 48-V and
12-V ports of automotive dual battery systems. It integrates essential analog functions that enable the design of
high power converters with a minimal number of external components. It regulates DC current in the direction
designated by the DIR pin input signal. The current regulation level is programmed by the analog signal applied
at the ISETA pin or the digital PWM signal at the ISETD pin. Independent enable signals activate each channel
of the dual controller.
The dual-channel differential current sense amplifiers and dedicated channel current monitors achieve typical
accuracy of 1%. The robust 5-A half-bridge gate drivers are capable of controlling parallel MOSFET switches
delivering 500 W or more per channel. The diode emulation mode of the buck or boost synchronous rectifiers
enables discontinuous mode operation for improved efficiency under light load conditions, and it also prevents
negative current. Versatile protection features include the cycle-by-cycle peak current limit, overvoltage protection
of both 48-V and 12-V battery rails, detection and protection of MOSFET switch failures, and overtemperature
protection.
The LM5170-Q1 uses average current mode control which simplifies compensation by eliminating the right-half
plane zero in the boost operating mode and by maintaining a constant loop gain regardless of the operating
voltages and load level. The free-running oscillator is adjustable up to 500 kHz and can be synchronized to an
external clock within ±20% of the free running oscillator frequency. Stackable multiphase parallel operation is
achieved by connecting two LM5170-Q1 controllers in parallel for 3 or 4 phase operation, or by synchronizing
multiple LM5170-Q1 controllers to external multiphase clocks for a higher number of phases. The UVLO pin
provides master ON/OFF control that disables the LM5170-Q1 in a low quiescent current shutdown state when
the pin is held low.
Definition of IC Operation Modes:
• Shutdown Mode: When the UVLO pin is < 1.25 V, or VCC < 8 V, or nFAULT < 1.25 V, the LM5170-Q1 is in
the shutdown mode with all gate drivers in the low state, all internal logic reset, and the VINX pin
disconnected from the VIN pin. When UVLO < 1.25 V, the IC draws < 20 µA through the VIN and VCC pins.
• Initialization Mode: When the UVLO pin is > 1.5 V but < 2.5 V, and VCC > 8.5 V, and nFAULT > 2 V, the
LM5170-Q1 establishes proper internal logic states and prepares for circuit operation.
• Standby Mode: When the UVLO pin is > 2.5 V, and VCC > 8.5 V, and nFAULT > 2 V, the LM5170-Q1 first
performs fault detection for 2 to 3 ms, during which the external power MOSFETs are each checked for drain-
to-source short-circuit conditions. If a fault is detected, the LM5170-Q1 returns to the shutdown mode and is
latched in shutdown until reset through UVLO or VCC pins. If no failure is detected, the LM5170-Q1 is ready
to operate. The circuit breaker MOSFETs are turned on and the oscillator and ramp generators are activated,
but the four gate drive outputs remain off until the EN1 or EN2 initiate the power delivery mode.
• Power Delivery Mode: When the UVLO pin > 2.5 V, VCC > 8.5 V, nFAULT > 2 V, EN1 and/or EN2 > 2 V,
DIR is valid (either > 2 V or < 1 V), and ISETA > 0 V, the SS capacitor is released and the LM5170-Q1
regulates the DC current at the level set at the ISETA pin.

LM5170-Q1
7.2 Functional Block Diagram
OPT OSC SYNCIN SYNCOUT
VIN VIN 3.125 V

OSCILLATOR AND CLK1 VCCA
2.5 V
SD PHASE SPLITTER BIAS
CLK2 1.5 V REGULATORS
VINX VINX
1.185 V
25 µA VCCUV
UVLO + ENABLE
2.5 V - nFAULT
CONTROL
+ RESET
1.5 V - LOGIC SD
300 uA
DIR_GOOD CIRCUIT BRKG
DIR DIR BREAKER
VALIDATION DIR 12 V
VIN CONTROL
FLIP BRKS
ISETA ISET DETECT
3.125 V SD
SS1 25 uA
100 K FAILURE
ISETD SS2 SS
DETECT
100K DISABLE1
DEAD OVER FLIP

DIR
TIME TEMP DETECT
DT VDT
CONTROL SD
CSB
3 MEG DIR 1
OVP 0
VINX 1 MEG
OVPA + + OVPB
1.185 V - - 1.185 V 1
VCC
PK LIMIT 25 uA
VCC + VCCUV VIPK IPK
8.5 V - PROGRAM
AGND COMMON CONTROL PGND
CH-1 CONTROL DIR CSB1

25 uA 5 mA/V
CSB1
IOUT1 Gm=1 mA/V
- +
ISET -
+
SS1 CS AMP
1V ERR AMP CSA1
A=50
COMP1 + -
+ PEAK VIPK
- HB1
RAMP1 PWM LIMIT
COMP
CLK1 PEAK ZERO DISABLE1 DELAY
VDT HO1
EMULATION
HOLD CROSS LOGIC

DIODE
+
- 0.6 V OVP LEVEL
DIR
SHIFT SW1
ADPT
EN1 SD LOGIC
CLK1 S Q VCC
1-D1
EN1 DISABLE1 VDT
D1 DELAY LO1
R Q
DISABLE1 LOGIC
CH-2 CONTROL DIR

5 mA/V
25 uA
Gm=1 mA/V CSB2
IOUT2
- +
+ -
SS2 ISET
CS AMP CSA2
1V ERR AMP
A=50
COMP2 + -
+ PEAK VIPK
- HB2
RAMP2 PWM LIMIT
COMP
CLK2 PEAK ZERO DISABLE2 DELAY
VDT HO2
EMULATION
HOLD ;¶,1* LOGIC

DIODE
+ OVP
- 0.6 V DIR LEVEL
SHIFT ADPT SW2
EN1 SD LOGIC
CLK2 S Q 1-D2 VCC
DISABLE2 VDT
EN2 D2 DELAY LO2
R Q
DISABLE2 LOGIC

LM5170-Q1
7.3 Feature Description

7.3.1 Bias Supply (VCC, VCCA)
The LM5170-Q1 requires an external bias supply of 9 V to 12 V at the VCC and VCCA pins to function. If an
external supply voltage is greater than 12 V, a 10-V LDO or switching regulator should be used to produce 10 V
for VCC and VCCA. Figure 19 shows typical connections of the bias supply. The VCC voltage is directly fed to
the low-side MOSFET drivers. A 1-µF to 2.2-µF ceramic capacitor must be placed between the VCC and PGND
pins to bypass the driver switching currents. The VCCA pin serves as the bias supply input for the internal logic
and analog circuits for which the ground reference is the AGND pin. VCCA should be connected to VCC through
a 25- to 50-Ω external resistor. A 0.1-µF to 1-µF bypass capacitor must be placed between the VCCA and AGND
pins to filter out possible switching noise.
The internal VCC undervoltage (UV) detection circuit monitors the VCC voltage. When the VCC voltage falls
below 8 V on the falling edge, the LM5170-Q1 is held in the shutdown state. For normal operation, the VCC and
VCCA voltages must be greater than 8.5 V on a rising edge.
25
Ext
9~12 Vdc Ext >12 Vdc
Driver
VCCA VCC 10 V
CVCCA
Analog
VCC LDO
Circuit
UV
CVCC
AGND PGND
LM5170-Q1
Figure 19. VCC Bias Supply Connections
7.3.2 Undervoltage Lockout (UVLO) and Master Enable or Disable

The UVLO pin serves as the master enable or disable pin. To use the UVLO pin to program undervoltage lockout
control for the HV-port, LV-port, or VCC rail, see Optional UVLO Programming for details.
There are two UVLO voltage thresholds. When the pin voltage is externally pulled below 1.25 V, the LM5170-Q1
is in shutdown mode, in which all gate drivers are in the OFF state, all internal logic resets, the VINX pin is
disconnected from VIN pin, and the IC draws less than 20 µA through the VIN, VCC and VCCA pins.
When the VCC voltage is above the 8.5 V and the UVLO pin voltage is pulled higher than 1.5 V but lower than
2.5 V, the LM5170-Q1 is in the initialization mode in which the nFAULT pin is pulled up to about 5 V, but the rest
of the LM5170-Q1 remain off.
When the UVLO pin is pulled higher than 2.5 V, which is the UVLO release threshold and the master enable
threshold, the LM5170-Q1 starts the MOSFET failure detection in a period of 2 to 3 ms (see Power MOSFET
Failure Detection and Failure Protection (nFAULT, BRKG, BRKS)). If no failure is detected, BRKG pin starts to
source a 330-µA current to charge the gates of the breaker MOSFETs.
When the BRKG to BRKS voltage is above 8.5 V, the LM5170-Q1 enters standby mode. In standby mode, the
VINX pin is internally connected to the VIN pin through an internal cutoff switch (see Figure 20), and the internal
1-MΩ OVPB pullup resistor is connected to the CSB1 pin through another internal cutoff switch (see Figure 36).
The oscillator and the RAMP1 and RAMP2 generators start to operate, and the SYNCOUT pin starts to send
clock pulses at the oscillator frequency, and the LM5170-Q1 is ready to operate. The LO1, LO2, HO1, and HO2
drivers remain off until the EN1, EN2, and DIR inputs command them to operate.
When a MOSFET gate-to-source short-circuit failure is detected, the LM5170-Q1 is latched off. The latch can
only be reset by pulling the VCC pin below 8 V, or by pulling the UVLO pin below 1.25 V. For details, see Power
MOSFET Failure Detection and Failure Protection (nFAULT, BRKG, BRKS).

LM5170-Q1
Feature Description (continued)

7.3.3 High Voltage Input (VIN, VINX)
Figure 20 shows the external and internal configuration for the VIN and VINX pins. Both are rated at 100 Vdc.
The VIN pin should be connected either directly to the voltage rail of the HV-Port, or through a small RC filter
consisting of 10- to 20-Ω resistor and 0.1-µF to 1-µF bypass capacitor. The internal 330-µA current source
supplying the BRKG pin is supplied by the VIN pin.
A cutoff switch connects and disconnects the VIN and VINX pins. When the UVLO pin voltage is greater than 2.5
V, and when the VCC voltage is greater than 8.5 V, the switch is closed and the VINX and VIN pins are
connected.
The VINX pin serves as the supply pin for the RAMP generators (see Figure 20 and the Ramp Generator section
for details). It is also the high-side terminal of the internal 3-MegΩ pullup resistor for the OVPA pin (see
Overvoltage Protection (OVPA, OVPB) for details). Moreover, it serves as the HV-Port voltage sense for internal
circuit use during operation.
HV-Port (48 V)
VIN
VINX
VINX
3 Meg
OVPA OVP RAMP1
+
COMP
1.185 V
-
AGND
RAMP2
LM5170-Q1
Figure 20. VIN and VINX Pins Configuration
7.3.4 Current Sense Amplifier

Each channel of the LM5170-Q1 has an independent bidirectional, high accuracy, and high-speed differential
current sense amplifier. The differential current sense polarity is determined by the DIR command. The amplifier
gain is 50, such that a smaller current sense resistor can be used to reduce power dissipation. The amplified
current sense signal is used to perform the following functions:
• Applied to the inverting input of the error amplifier for current loop regulation.
• Used to reconstruct the channel current monitor signal at the IOUT1 and IOUT2 pins.
• Monitored by the cycle-by-cycle peak current limit comparator for instantaneous overcurrent protection.
• Sensed by the current zero cross detector to operate the synchronous rectifiers in diode emulation mode.
The current sense resistor Rcs should be selected for 50-mV current sense voltage when the channel DC current
reaches the rated level. The CS1A, CS1B, CS2A, and CS2B pins should be Kelvin connected for accurate
sensing.
It is very important that the current sense resistors are non-inductive. Otherwise the sensed current signals will
be distorted even if the parasitic inductance is only a few nH. Such inductance may not affect the current
regulation during continuous conduction mode, but it does affect current zero cross detection, and hence the
performance of diode emulation mode under light load. As a consequence, the synchronous rectifier gate pulse
will be truncated much earlier than the inductor current zero crossing, causing the body diode of the synchronous
rectifier to conduct unnecessarily for a longer time. See the Diode Emulation section for details.
If the selected current sense resistor has parasitic inductance, see the Application Information section for
methods to compensate for this condition and achieve optimal performance.

LM5170-Q1

7.3.5 Control Commands
7.3.5.1 Channel Enable Commands (EN1, EN2)

These pins are two state function pins. Always use CH-1 if only single-channel operation is required. Note that
CH-2 can only be enabled when CH-1 is also enabled.
a. When the EN1 pin voltage is pulled above 2 V (logic state of 1), the HO1 and LO1 outputs are enabled
through soft start.
b. When the EN1 pin voltage is pulled below 1 V (logic state of 0), CH-1 controller is disabled and both HO1
and LO1 outputs are turned off.
c. Similar behaviors for EN2, HO2 and LO2 of CH-2, except that the EN2 pin does not affect the SS pin. Refer
to Soft Start for details.
d. When the EN1 and EN2 pins are left open, an internal 100-kΩ pulldown resistor sets them to the low state.
e. The built-in 2-µs glitch filters prevent errant operation due to the noise on the EN1 and EN2 signals.
7.3.5.2 Direction Command (DIR)

This pin is a triple function pin.
a. When the DIR pin is actively pulled above 2 V (logic state of 1), the LM5170-Q1 operates in buck mode, and
current flows from the HV-Port to the LV-Port.
b. When the DIR pin is actively pulled below 1 V (logic state of 0), the LM5170-Q1 operates in boost mode, and
current flows from the LV-Port to the HV-Port.
c. When the DIR pin is in the third state that is different from the above two, it is considered an invalid
command and the LM5170-Q1 remains in standby mode regardless of the EN1 and EN2 states. This tri-state
function prevents faulty operation when losing the DIR signal connection to the MCU.
d. When DIR changes state between 1 and 0 dynamically during operation, the transition causes the SS pin to
discharge first to below 0.23 V, then the SS pin pulldown is released and the LM5170-Q1 goes through a
new soft-start process to produce the current in the new direction. This eliminates surge current during the
direction change.
e. The built-in 10-µs glitch filter prevents errant operation by noise on the DIR signal.
7.3.5.3 Channel Current Setting Commands (ISETA or ISETD)

The LM5170-Q1 accepts the current setting command in the form of either an analog voltage or a PWM signal.
The analog voltage uses the ISETA pin, and the PWM signal uses the ISETD pin. There is an internal ISETD
decoder that converts the PWM duty ratio at the ISETD pin to an analog voltage at the ISETA pin. Owing to
possible ground noise impact, TI recommends users to remove EN1 signal to achieve no load (0 A).
Figure 21 and Figure 22 show the pin configurations for current programming with an analog voltage or a PWM
signal. The channel DC current is expressed in terms of resulted differential current sense voltage VCS_dc. When
ISETA is used, the ISETD pin can be left open or connected to AGND. When ISETD is used, place a ceramic
capacitor CISETA between the ISETA pin and AGND. CISETA and the internal 100-kΩ at the output of the ISETD
decoder forms a low-pass RC filter to attenuate the ripple voltage on ISETA. However, the RC filter delays the
ISETD dynamic change to be reflected on ISETA. To limit the delay not to exceed Tdelay_ISETD, the time constant
of the RC filter should satisfy Equation 1.
Tdelay_ISETD
100k: u CISETA d
4 (1)
Therefore, the maximum CISETA should be determined by Equation 2:
Tdelay_ISETD
CISETA d
4 u 100k: (2)
On the other hand, the time constant of the RC filter should be big enough for effective filtering. To attenuate the
ripple by 40 dB, the RC filter corner frequency should be at least two decade below FISETD, that is, Equation 3
1
d 0.01u FISETD
2S u 100k: u CISETA (3)

LM5170-Q1

Therefore the minimum ISETD signal frequency should be determined by Equation 4:
1 400
FISETD t t
2S u 1k: u CISETA 2S u Tdelay_ISETD (4)
For instance, if ISETA is required to settle down to the steady-state in 1 ms following an ISETD duty ratio step
change, namely Tdelay_ISETD < 1 ms, the user should select CISETA < 2.5 nF, and FISETD > 64 kHz. If Tdelay_ISETD <
0.1 ms, then CISETA < 250 pF, and FISETD> 640 kHz. Note that the feedback loop property causes additional delay
for the actual current to settle to the new regulation level.
Current Level LM5170-Q1 60.0

Command
VCS_dc (mV)
50.0
ISETA
+ ISETD
- AGND
0
0 2.5 3.0
ISETA (V)
Figure 21. Pin Configurations for Current Setting Using an Analog Voltage Signal
Current Level 62.5

LM5170-Q1
Command 50.0
VCS_dc (mV)
ISETD
FISETD=1~1000 kHz
ISETA
AGND
CISETA
100 pF~100 nF 0
0% 80% 100%
ISETD Duty (%)
Figure 22. Pin Configurations for Current Setting Using a PWM Signal
The ISETA pin is directly connected to the noninverting input of the error amplifier. By ISETA programming, the
channel DC current is determined by Equation 5:
VCS dc 0.02 u VISETA (5)
Or by Equation 6:
VCS_dc_
I_channel_dc
Rcs (6)
Or by Equation 7:
0.02 u VISETA
I_channel_dc
Rcs
where
• Rcs is the channel current sensing resistor value. (7)
When using ISETD, the produced VISETA by the internal decoder is equal to the product of the effective duty ratio
of the ISETD PWM signal (DISETD) and the 3.125-V internal reference voltage. The channel current is determined
by Equation 8:
IVISETA 3.125V u DISETD (8)

LM5170-Q1

Or by Equation 9:
VCS dc 0.0625V u DISETD (9)
Or by Equation 10:
0.0625V u DISETD
I_channel_dc
Rcs (10)
7.3.6 Channel Current Monitor (IOUT1, IOUT2)

The LM5170-Q1 monitors the real time inductor current in each channel at the IOUT1 and IOUT2 pins. The
channel current is converted to a small current source scaled by the factors seen in Equation 11 and
Equation 12:
VCSI
IOUT1 25PA
200: (11)
VCS2
IOUT2 25PA
200:
where
• VCS1 and VCS2 are the real time current sense voltage of CH-1 and CH-2, respectively
• the 25 µA is a DC offset current superimposed on to the IOUT signals (refer to Figure 23). (12)
The DC offset current is introduced to raise the no-load signal above the possible ground noise floor. Because
the monitor signal is in the form of current, an accurate reading can be obtained across a termination resistor
even if the resistor is located far from the LM5170-Q1 but close to the MCU, thus rejecting potential ground
differences between the LM5170-Q1 and the MCU. Figure 24 shows a typical channel current monitor through a
9.09-KΩ termination resistor and a 10-nF to 100-nF ceramic capacitor in parallel. The RC network converts the
current monitor signal into a DC voltage proportional to the channel DC current. For example, when the current
sense voltage DC component is 50 mVdc, namely VCS_dc = 50 mV, the termination RC network will produce a DC
voltage of 2.5 V. Note that the maximum IOUT pin voltage will be internally clamped to about 4 V.
275
IOUT (µA)
25
0
0 50
V_CS (mV)
Figure 23. Channel Monitor Current Source vs Current Sense Voltage
To MCU
Monitor
LM5170-Q1
IOUT2
9.09 k 10~100 nF
IOUT1
9.09 k
AGND 10~100 nF
Ground MCU Local

Impedance GND
Figure 24. Channel Current Monitor

LM5170-Q1

7.3.7 Cycle-by-Cycle Peak Current Limit (IPK)
The internal 25-µA current source and a single external resistor RIPK establishes a voltage at the IPK pin to
program the cycle-by-cycle current limit threshold. To set the inductor peak current limit value to IPK, RIPK should
satisfy Equation 13:
Rcs u IPK
RIPK
1.1PA (13)
IPK should be greater than the inductor peak current at full load, and lower than the inductor’s rated saturation
current Isat.
Note that when the IPK pin voltage is greater than 4.5 V, either owing to a very large RIPK value or the pin being
open or some other reason, an internal monitor circuit will shut down the switching, preventing the LM5170-Q1
from operating with erroneous peak current limit threshold.
7.3.8 Error Amplifier

Each channel of the LM5170-Q1 has an independent gm error amplifier. The output of the error amplifier is
connected to the COMP pin, allowing the loop compensation network to be applied between the COMP pins and
AGND.
The LM5170-Q1 control loop is the inner current loop of the bidirectional converter system, of which the outer
voltage loop can either be controlled by an MCU, a DSP, an FPGA, and so forth, or by an analog circuit.
Because the LM5170-Q1 employs the averaged current mode control scheme, the inner loop is basically a first
order system. As seen in Figure 25, a Type-II compensation network consisting of RCOMP, CCOMP, and CHF is
adequate to stabilize the LM5170-Q1 inner current loop. Refer to the Application Information section for details of
the compensation network selection criteria.
7.3.9 Ramp Generator

Refer to Figure 25 for the circuit block diagram of the ramp generator, gm error amplifier, PWM comparator, and
soft-start control circuit. The VINX pin serves as the supply pin for the ramp generator. Each ramp generator
consists of an external RC circuit (RRAMP and CRAMP) and an internal pulldown switch controlled by the clock
signal.

LM5170-Q1
HV-Port (48 V)
VIN
Shutdown
VINX
RRAMP1
RAMP1
CLK1
CRAMP1
-
1V PWM To Driver Logic
COMP1
+
RCOMP1 25 mA
Gm AMP
CHF1 SS From Current
-
Sense Amp
CCOMP1
Gm
CSS + ISET
AGND
COMP2
RRAMP2
To CH2 PWM
RAMP2
CLK2
CRAMP2
LM5170-Q1
Figure 25. Error Amplifier, Ramp Generator, Soft Start, and PWM Comparator
When the LM5170-Q1 is enabled, CRAMP1/2 is charged by the VINX pin through RRAMP1/2 at the beginning of each
switching cycle. The internal pulldown FET discharges CRAMP1/2 at the end of the cycle within a 200-ns internal,
then the pulldown is released, and CRAMP1/2 repeats the charging and discharging cycles. In general the RAMP
RC time constant is much greater than the period of a switching cycle. Therefore, the RAMP pin voltages are
sawtooth signals with a slope proportional to the HV-Port voltage. In this way the RAMP signals convey the line
voltage info. Being directly used by the PWM comparators to determine the instantaneous switching duty cycles,
the RAMP signals fulfill the line voltage feedforward function and enable the LM5170-Q1 to have a fast response
to line transients.
NOTE
TI recommends users to select appropriate RRAMP and CRAMP values by the following
equation such that the RAMP pins reach the peak value of about 5 V each cycle when
VIN is at 48 V.
9.6
RRAMP
Fsw u CRAMP (14)

LM5170-Q1

For instance, if Fsw = 100 kHz, and CRAMP1 = CRAMP2 = 1 nF, a resistor of about 96 kΩ should be selected for
RRAMP1 and RRAMP2.
Because CRAMP1/2 must be fully discharged every cycle through the 15-Ω channel resistor of the pulldown FET
within the 150-ns minimum discharging interval, CRAMP1/2 should be limited to be less than 2.5 nF nominal at
room temperature.
There is also a valid RAMP signal detection circuit for each channel to prevent the channel from errantly running
into the maximum duty cycle if RAMP goes away. It detects the peak voltage of the RAMP signal. If the peak
voltage is less than 0.6 V in consecutive cycles, it is considered an invalid RAMP and the channel will stop
switching by turning both HO and LO off until the RAMP signal recovers. This 0.6-V voltage threshold defines the
minimum operating voltage of the HV-Port to be about 5.76 V.
7.3.10 Soft Start

The soft-start feature helps the converter to gradually reach the steady-state operating point, thus reducing start-
up stresses and surge currents. With the LM5170-Q1, there are two ways to implement the soft start.
7.3.10.1 Soft-Start Control by the SS Pin

Place a ceramic capacitor CSS between the SS pin and AGND to program the soft-start time. When the EN1
voltage is <1 V, an internal pulldown switch holds the SS pin at AGND. When the EN1 pin voltage is >2 V, the
SS pulldown is released, and CSS is charged up slowly by the internal 25-µA current source, as shown in
Figure 25. The slow ramping SS voltage clamps the COMP1 and COMP2 pins through two separate clamp
circuits. Once the SS voltage exceeds the 1-V offset voltage, the PWM duty cycle starts to increase gradually
from zero.
When EN1 is pulled below 1 V, CSS is discharged by the internal pulldown FET. Once this pulldown FET is
turned on, it remains on until the SS voltage falls below 0.23 V, which is the threshold voltage indicating the
completion of SS discharge.
Note that the EN2 pin does not affect the SS pin. When EN1 and EN2 are enabled together, the CH-2 output will
follow CH-1 by going through the same soft-start process. If EN2 is enabled at a later time and CH-1 has already
completed soft start, CH-2 will not be affected by the SS pin. This allows the CH-2 current to ramp up quickly to
supply the increased load current. However, when SS is pulled low, both CH-1 and CH-2 are affected at the
same time.
7.3.10.2 Soft Start by MCU Through the ISET Pin

The MCU can control the soft start by gradually ramping up the ISETA voltage, or the ISETD PWM duty ratio,
whichever is applicable. When ISETA or ISETD is used to control the soft start, CSS should be properly selected
to a value such that it does not interfere with the ISETA/D soft start.
7.3.10.3 The SS Pin as the Restart Timer

The SS pin also fulfills the function of a restart timer in an OVP event or following a DIR command change:
(1) Restart Timer in OVP: When OVPA or OVPB catches an overvoltage event (refer to Overvoltage Protection
(OVPA, OVPB)), CSS is discharged immediately by the internal pulldown FET, and this FET remains ON as long
as the overvoltage condition persists. When the overvoltage condition is removed and after the SS voltage is
discharged to below 0.23 V, the SS pulldown is released, setting off a new soft-start cycle. The circuit may run in
retry or hiccup mode if the overvoltage condition reappears. The retry frequency is determined by the SS
capacitor as well as the nature of the overvoltage condition.
(2) Restart Timer: When DIR dynamically flips its state from 0 to 1, or 1 to 0 during operation, CSS is first
discharged to 0.23 V by the internal pulldown FET, then the pulldown is released to set off a new soft-start cycle
to gradually build up the channel current in the new direction. In this way, the channel current overshoot is
eliminated.

LM5170-Q1

7.3.11 Gate Drive Outputs, Dead Time Programming and Adaptive Dead Time (HO1, HO2, LO1, LO2, DT)
Each channel of the LM5170-Q1 has a robust 5-A (peak) half bridge driver to drive external N-channel power
MOSFETs. As shown in Figure 26, the low-side drive is directly powered by VCC, and the high-side driver by the
bootstrap capacitor CBT. During the on-time of the low-side driver, the SW pin is pulled down to PGND and CBT is
charged by VCC through the boot diode DBT. TI recommends selecting a 0.1-µF or larger ceramic capacitor for
CBT, and an ultra-fast diode of 1 A and 100-V ratings for DBT. TI also strongly recommends users to add a 2-Ω to
5-Ω resistor (RBT) in series with DBT to limit the surge charging current and improve the noise immunity of the
high-side driver.
RBT DBT
2
HB
VCC
HO CBT
Driver
SW
External VCCA
10V Supply
Internal LO
Driver
Logic
AGND Circuit PGND
LM5170-Q1
Figure 26. Bootstrap Circuit for High-Side Bias Supply
During start-up in buck mode, CBT may not be charged initially; the LM5170-Q1 then holds off the high-side driver
outputs (HO1 and HO2) and sends LO pulses of 200-ns width in consecutive cycles to pre-charge CBT. When the
boot voltage is greater than the 6.5-V boot UV threshold, the high-side drivers output PWM signals at the HO1
and HO2 pins for normal switching action.
During start-up in boost mode, CBT is naturally charged by the normal turnon of the low side MOSFET, therefore
there is no such 200-ns pre-charge pulse at the LO pins.
To prevent shoot-through between the high-side and low-side power MOSFETs on the same half bridge leg, two
types of dead time schemes can be chosen with the DT pin: the programmable dead time or built-in adaptive
dead time.
To program the dead time, place a resistor RDT across the DT and AGND pins as shown in Figure 27.
The dead time tDT as depicted in Figure 28 is determined by Equation 15:
ns
tDT RDT u 4 16ns
k: (15)
Note that this equation is valid for programming tDT between 20 ns and 250 ns. When the power MOSFET is
connected to the gate drive, its gate input capacitance CISS becomes a load of the gate drive output, and the HO
and LO slew rate are reduced, leading to a reduced effective tDT between the high- and low-side MOSFETs. The
user should evaluate the effective tDT to make sure it is adequate to prevent shoot-through between the high-
and low-side MOSFETs.
When the DT programmability is not used, simply connect the DT pin to VCC as shown in Figure 29, to activate
the built-in adaptive dead time. The adaptive dead time is implemented by real time monitoring of a driver’s
output (either HO or LO) by the other driver (LO or HO) of the same half bridge switch leg, as shown in Figure 29
and Figure 30. Only when a driver’s output voltage falls below 1.25 V does the other driver starts turnon. The
effectiveness of adaptive dead time will be greatly reduced if a series gate resistor is used, or if the PCB traces
of the gate drive have excessive impedance due to poor layout design.

LM5170-Q1
HV-Port (48 V)
RBT1/2 DBT1/2
VCC
LM5170-Q1 HB1/2
DLY HO1/2 CBT1/2

Driver
Logic
SW1/2
Adapt Logic
Level Level Shift
FROM Shift VCC
PWM DLY LO1/2
Driver
Logic
AGND DT PGND
RDT
Figure 27. Dead Time Programming With DT Pin (Only One Channel is Shown)
HO
tDT tDT
LO
Figure 28. Gate Drive Dead Time (Only One Channel is Shown)

LM5170-Q1
HV-Port (48V)
RBT1/2 DBT1/2
VCC
LM5170-Q1 HB1/2
CBT1/2
DLY HO1/2
Logic Driver
SW1/2
Adapt Logic
Level Level Shift
Shift VCC
FROM
PWM DLY LO1/2
Logic Driver
AGND DT PGND
Figure 29. Dead Time Programming With DT Pin (Only One Channel is Shown)
1.5 V
HO
Adaptive
tDT
LO
1.5 V
Figure 30. Adaptive Dead Time (Only One Channel is Shown)
7.3.12 PWM Comparator

Each channel of the LM5170-Q1 has a pulse width modulator (PWM) employing a high-speed comparator. It
compares the RAMP pin signal and the COMP pin signal to produce the PWM duty cycle. Note that the COMP
signal passes through a 1-V DC offset before it is applied to the PWM comparator, as shown in Figure 25. Owing
to this DC offset, the duty cycle can reduce to zero when the COMP pin or SS pin is pulled lower than 1 V. The
maximum duty cycle is limited by the 200-ns minimum off-time. Note that the programmed dead time may reduce
the maximum duty cycle because it is additional to the minimum off-time. Therefore, the available maximum duty
cycle, for both buck and boost mode operation, is determined by Equation 16.
DMAX 1 (200ns tDT ) u Fsw
where
• tDT is the dead time given by (15) or the adaptive dead time, whichever applicable. (16)
This maximum duty cycle limits the minimum voltage step-down ratio in buck mode operation, and the maximum
step-up ratio in boost mode operation.
Note that the maximum COMP voltage is clamped at about 1.5 V higher than the RAMP peak voltage. This
prevents the COMP voltage from moving too far above the RAMP voltage which could cause longer recovery
time during a large scale upward step load response.

LM5170-Q1

7.3.13 Oscillator (OSC)
The LM5170-Q1 oscillator frequency is set by the external resistor ROSC connected between the OSC pin and
AGND, as shown in Figure 31. The OSC pin must never be left open whether or not an external clock is present.
To set a desired oscillator frequency FOSC, ROSC is approximately determined by Equation 17:
40k: u 100 kHz
ROSC
FOSC (17)
ROSC must be placed as close as possible to the OSC and AGND pins. Take the tolerance of the external
resistor and the frequency tolerance indicated in the Electrical Characteristics table into account when
determining the worst case operating frequency.
The LM5170-Q1 also includes a Phase-Locked Loop (PLL) circuit to manage multiphase interleaving phase
angle as well as the synchronization to the external clock applied at the SYNCIN pin. When no external clock is
present, the converter operates at the oscillator frequency given by Equation 17. If an external clock signal of a
frequency within ± 20% of FSW is applied (see the Synchronization to an External Clock (SYNCIN, SYNCOUT)
section), the converter will switch at the frequency of the external clock FEX_CLK, namely Equation 18:
-° FOSC (in Standalone)
FSW ®
°̄FEX_CLK (in Synchronization)
(18)
Two internal clock signals CLK1 and CLK2 are produced to control the interleaving operation of CH-1 and CH-2,
respectively. The third clock signal is output at the SYNCOUT pin. All these three clock signals run at the same
frequency of FSW. The phase angles among these three clock signals are controlled by the state of the OPT pin.
See the Multiphase Configurations (SYNCOUT, OPT) section for details.
SYNCIN
CLK1
SYNCOUT
SYNCOUT
CLK2
10 k OSC OSC and CLK1

Phase Splitter
CLK2
ENABLE
AGND
Interleaving OPT
LM5170-Q1
Control
Figure 31. Oscillator and Interleaving Clock Programming
7.3.14 Synchronization to an External Clock (SYNCIN, SYNCOUT)

The LM5170-Q1 can synchronize to an external clock if FEX_CLK is within ±20% of FOSC. The SYNCIN clock pulse
width should be in the range of 100 ns to 500 ns, with a high voltage level >2 V and low voltage level <1 V.
FEX_CLK can be adjusted dynamically. However the LM5170-Q1 PLL takes about 500 µs to settle down to the
newly asserted frequency. During the PLL transient, the instantaneous FSW may temporarily drop by 25%. To
avoid overstress during the transient, TI recommends the user to reduce the load current to less than 50% by
lowering the ISETA voltage or ISETD duty, or to simply turn off the dual-channels by setting EN1=EN2=0 when
making an the external clock change.
LM5170-Q1

7.3.15 Diode Emulation
The LM5170-Q1 has a built-in diode emulation function. Each channel has a real time current zero crossing
detector to monitor instantaneous VCS. When VCS is detected to cross zero, the LM5170-Q1 turns off the gate
drive of the synchronous rectifier to prevent negative current. In this way, the negative current is prevented and
the light load efficiency is improved. Figure 32 shows key waveforms of a typical operation transiting into the
diode emulation mode.
CLK
Main FET
Turn-ON
Sync FET x x
Turn-ON
Diode Emulation
x x
Inductor
Current
0A
Figure 32. Diode Emulation Operation
To obtain optimal diode emulation performance, it requires the VCS signal to be accurate in real time. Any signal
distortion caused by parasitic inductances in the current sense resistor or sensing traces may lead to erroneous
zero crossing detection and cause non-optimal diode emulation operation, and the sync FET may be turned off
while the current is still high in the positive direction. See the Application Information section for coping with
current sense parasitic inductances for optimal diode emulation operation.
7.3.16 Power MOSFET Failure Detection and Failure Protection (nFAULT, BRKG, BRKS)
The LM5170-Q1 includes a circuit to detect a MOSFET switch short-circuit failure during start-up. If a MOSFET
drain and source are found shorted, the LM5170-Q1 pulls down the nFAULT pin to flag the fault, and the
controller remains in an OFF state. This feature prevents the LM5170-Q1 from starting with a short-circuit-failed
MOSFET, thereby preventing catastrophic failures.
The LM5170-Q1 also integrates a control circuit to control the circuit breaker. As shown in Figure 33, the circuit
breaker consists of a pair of back-to-back MOSFETs. When the breaker is off, the current path between the HV-
Port and LV-Port is cut-off so as to prevent possible catastrophic failures.
NOTE
The failure detection function must be deactivated if the circuit breaker is not present, or if
the circuit breaker FETs are not controlled by the LM5170-Q1.
7.3.16.1 Failure Detection Selection at the SYNCOUT Pin

Depending on application preference, the failure detection function can be activated or deactivated by the
SYNCOUT pin. During start-up, the LM5170-Q1 first detects the external resistor attached to the SYNCOUT pin.
To enable the failure detection function, do not place resistor between the SYNCOUT and AGND pins (refer to
Figure 33 or Figure 34).
To disable the failure detection function, place a 10-kΩ resistor between the SYNCOUT and AGND pins, as
shown in Figure 35, and the LM5170-Q1 skips the 2- to 3-ms interval of MOSFET failure detection. Instead, it will
activate the standby mode in about 300 µs after VCC is above 8.5 V and UVLO is greater than 2.5 V. If the
circuit breaker is not present or not controlled by the LM5170-Q1, do not leave the BRKG and BRKS pins
floating, but terminate the BRKG and BRKS pins with 20-kΩ resistors as shown in Figure 35.

LM5170-Q1

7.3.16.2 Nominal Circuit Breaker Function
If the failure detection function is enabled, which also implies the circuit breaker being controlled by the LM5170-
Q1, the LM5170-Q1 will perform a MOSFET failure detection during start-up. The detection starts after the UVLO
is pulled higher than 2.5 V and VCC above 8.5 V. The detection operation lasts for 2 to 3 ms. During the
detection, the LM5170-Q1 checks the high-side and low-side MOSFETs of both channels as well as the circuit
breaker MOSFETs to see if any of them has drain-to-source shorted. If no failure is detected, a 330-µA current
source at the BRKG pin is turned on to charge up the breaker MOSFET gates. When the BRKG to BRKS voltage
rises above 8.5 V, the LM5170-Q1 enters standby mode, waiting for the EN1 and EN2 commands to operate in
power delivery mode. The voltage across BRKG and BRKS is internally clamped to 12 V, preventing overvoltage
stress on the breaker MOSFET gates.
If a failure of any MOSFET is detected, the LM5170-Q1 immediately pulls the nFAULT pin low, and keeps the
LM5170-Q1 in a latched shutdown mode, thereby preventing catastrophic failure.
The nFAULT pin can also be externally pulled low during normal operation and the LM5170-Q1 immediately
turns off the circuit breaker and stays in a latched shutdown. There is a 2-µs glitch filter at the nFAULT pin to
prevent errant shutdown by possible noises at the nFAULT pin.
To release the nFAULT shutdown latch, it requires the UVLO pin to be externally forced below 1.25 V, or VCC is
below 8 V.
Figure 33 and Figure 34 show two ways to use the circuit breaker function. A TVS is recommended to prevent
surge voltage when the circuit breaker is turned off during operation.
The BRKG 330-µA current source is powered by the VIN pin, or the HV-Port. Therefore, the differential voltage
between the HV-Port and LV-Port should be greater than 10 V to ensure that BRKG to BRKS voltage can
establish >8.5 V and allow the LM5170-Q1 to enter power delivery mode. The BRKG to BRKS voltage is
internally clamped to 12 V if the differential voltage of the two ports is greater.
The load dump transient at the LV-Port may raise the rail voltage and reduce the differential voltage of the two
ports to below 10 V. To maintain the circuit breaker to be closed during the transient, TI recommends adding a 1-
nF to 10-nF capacitor across BRKG and BRKS to hold the gate voltage during the transient.
Note that the BRKG 330-µA current source will always be turned on once the LM5170 starts up. If the failure
detection mode is deactivated, the LM5170-Q1 will also skip checking the BRKG to BRKS votlage condition.
Therefore, the circuit breaker can still be controlled by the LM5170-Q1 even if the failure detection is deactivated.
If the steady-state differential voltage between the HV-Port and LV-Port is less than 10 V during power up, TI
does not recommend the user to activate the failure detection function. Also, if the differential voltage is less than
8 V, TI recommends not to use the LM5170-Q1's circuit breaker function at all.
HV-Port LV-Port
Lm Rcs
VIN HO SW LO CSA CSB BRKG BRKS

To MCU
SYNCOUT or
nFAULT
System
OPEN Monitor
LM5170-Q1
Figure 33. Controlling Dual-Channel Circuit Breaker for MOSFET Failure Protection

LM5170-Q1
HV-Port LV-Port
Lm Rcs
To SYNCIN of
the Next VIN HO SW LO CSA CSB
LM5170-Q1
BRKG
SYNCOUT
BRKS
OPEN To MCU or
nFAULT System
LM5170-Q1
Monitor
Figure 34. Controlling System Level Circuit Breaker for MOSFET Failure Protection
HV-Port LV-Port
Lm Rcs
20 k 20 k
VIN HO SW LO CSA CSB BRKG BRKS
SYNCOUT From MCU

nFAULT or System
10 k Monitor
LM5170-Q1
Figure 35. Circuit Breaker Function Disabled
7.3.17 Overvoltage Protection (OVPA, OVPB)

As shown in Figure 36 and Figure 37, the LM5170-Q1 includes the overvoltage protection function for both HV-
Port and LV-Port. Use the OVPA pin for the HV-Port protection, and the OVPB pin for the LV-Port protection. It
should be pointed out that the OVPB protection function is disabled during the boost operation mode, while the
OVPA function is always enabled in both buck or boost operation modes.
7.3.17.1 HV-V- Port OVP (OVPA)

A dedicated comparator monitors the HV-Port voltage through a resistor divider. The divider consists of an
internal 3-MegΩ pullup resistor between the VINX and OVPA pins, and an external pulldown resistor between
the OVPA pin and AGND. When the OVPA pin voltage exceeds the 1.185-V threshold, both HOs and LOs are
turned off. At the same time CSS is discharged, preparing for the restart through soft start when the OV alarm is
removed. See the Soft Start section for details.
7.3.17.2 LV-Port OVP (OVPB)

A dedicated comparator monitors the LV-Port voltage through a resistor divider. The divider consists of the
internal 1-MegΩ pullup resistor between the CSB1 and OVPB pins, and an external pulldown resistor between
the OVPB pin and AGND. When the OVPB pin voltage exceeds the 1.185-V threshold, both HOs and LOs are
turned off. At the same time the SS capacitor is discharged, preparing to restart through soft start when the OV
alarm is removed. See the Soft Start section for details.

LM5170-Q1

Note the hysteresis voltage of both OVPA and OVPB comparators is about 100 mV. There are 5-µs built-in glitch
filters for both OVPA and OVPB comparators. In addition, a small capacitor can be considered to place from the
OVP pins to AGND. All these will help prevent errant operation by possible noises on the OVPA and OVPB
signals.
HV-Port (48 V) LV-Port (12 V)
Converter Stage
CSA1 CSB1
VIN
BRKG 20 k
VINX Current
To Ramp BRKS 20 k
Sense
Generator
3 Meg 1 Meg
DIR 0
OVPA OVP
HV Sense, OVPB LV Sense,
+ +
To MCU COMP COMP 1 To MCU
COVPA ROVPA 1.185 V ROVPB COVPB
- -
1.185 V
AGND
SS SS
SYNCOUT CSS
LM5170-Q1
10 k
Figure 36. Overvoltage Protection: When Circuit Breaker Function is Not Used
HV-Port LV-Port
Converter Stage
CSA1 CSB1
VIN
BRKG
VINX Current
To Ramp Sense BRKS
Generator
3 Meg 1 Meg
DIR 0
OVPA OVP OVPB
HV Sense, + LV Sense,
+
To MCU COMP COMP 1 To MCU
COVPA ROVPA 1.185 V ROVPB COVPB
- -
1.185 V
AGND
SS SS
SYNCOUT CSS
Open LM5170-Q1
Figure 37. Overvoltage Protection: When Circuit Breaker Function is Used

LM5170-Q1
7.4 Device Functional Modes

7.4.1 Multiphase Configurations (SYNCOUT, OPT)
There are various options to make multiphase configurations.
7.4.1.1 Multiphase in Star Configuration

Each LM5170 synchronizes to an external clock, and the clock signals should have appropriate phase delays
among them for proper multiphase interleaving operation. The interleave angle between the two phases of each
LM5170-Q1 can be programmed to 180° or 240° by the OPT pin.Table 1 summarizes the settings of the external
clocks and the OPT pin state for multiphase configurations.
Table 1. Multiphase Configurations With Individual External Clock

PHASE SHIFT
NUMBER BETWEEN EXTERNAL NUMBER OF LM5170-
OPT LOGIC CH-2 PHASE NUMBER OF EXTERNAL
OF CLOCKS FOR Q1 CONTROLLERS
STATE (1) LAGGING VS CH-1 CLOCKS NEEDED
PHASES MULTIPHASE NEEDED
INTERLEAVING
2 180° 1 180° 1 1 or 0
3 120° 0 240° 2 2
4 90° 1 180° 2 2
6 60° or 120° 1 180° 3 3
8 45° 1 180° 4 4
2xN (180°/N) 1 180° N N
(1) OPT State = 0 when the pin connects to AGND, and 1 when the pin voltage is >2.5 V.
EN1 EN2 VCCA EN1 EN2 VCCA

0 Deg
SYNCIN
120 Deg SYNCIN
SYNCOUT OPT OPT
240 Deg SYNCOUT
U1 DIR U2
DIR OSC OSC
ISETD
ISETD AGND AGND
MCU
EN1 EN2 VCCA

SYNCIN
SYNCOUT OPT
U3
DIR OSC
ISETD AGND
Figure 38. Example of Six Phase Star Configuration

LM5170-Q1
7.4.1.2 Configuration of 2, 3, or 4 Phases in Master-slave Daisy Chain Configurations

This can be used to realize 1, 2, 3, or 4 phases without the need of external clock. Table 2 summarizes the OPT
settings for the daisy chain multiphase configurations. Figure 39 shows the daisy chain connections for
multiphase configurations.
Table 2. Multiphase Configurations With Built-In Daisy Chain Master-Slave Configuration

NUMBER CH-2 PHASE SYNCOUT PHASE NUMBER OF LM5170-
NUMBER OF EXTERNAL
OF OPT LOGIC STATE (1) LAGGING VS CH- LAGGING VS CH- Q1 CONTROLLERS
CLOCKS NEEDED
PHASES 1 1 NEEDED
2 1 180° 90° 1 0 or 1
3 0 240° 120° 2 0 or 1
4 1 180° 90° 2 0 or 1
(1) OPT State = 0 when the pin connects to AGND, and 1 when the pin voltage is >2.5 V.
MCU EN1 EN2 VCCA EN1 EN2 VCCA
SYNCIN OPT SYNCIN OPT
SYNCOUT OSC SYNCOUT OSC

AGND AGND
U1 U2
OPT=´1" 90 Degree Phase Delay

OPT=´0" 120 Degree Phase Delay
Figure 39. Three or Four Phases Interchangeable Configuration
7.4.1.3 Configuration of 6 or 8 Phases in Master-Slave Daisy Chain Configurations

To configure 6 or 8 phases, it requires two daisy chains shown in Figure 40 through Figure 43. Note that two
phase-shifted external clock signals are required for proper interleaving operation. When external clock signals
are not available, the 6-phase can be configured in 120° interleaving, and 8-phase in 90° interleaving by daisy
chain (refer to Figure 41 and Figure 43), in which two phases of the system are synchronized in phase.

LM5170-Q1

0 Deg

AGND AGND
MCU U1 U2
240 Degree Phase Delay

120 Degree
EN1 EN2 VCCA
SYNCIN OPT
SYNCOUT OSC
AGND
U3
Figure 40. Six Phases 60° Interleaving Configuration

0 Deg

AGND AGND
MCU U1 U2

EN1 EN2 VCCA
SYNCIN OPT
SYNCOUT OSC
AGND
U3
Figure 41. Six Phases 120° Interleaving Configuration

LM5170-Q1

0 Deg

AGND AGND
MCU U1 U2

45 Deg

AGND AGND
U3
Figure 42. Eight Phases 45° Interleaving Configuration

LM5170-Q1

0 Deg

AGND AGND
MCU U1 U2


AGND AGND
U3 U4
Figure 43. Eight Phases 90° Interleaving Configuration
7.4.2 Multiphase Total Current Monitoring

To minimize the number to signal lines, multichannel monitors can be combined into a total current monitor.
Figure 44 shows an example of total current monitor of a three phase system in which the unused fourth phase
monitor (U2-IOUT2) is grounded.
LM5170-Q1
IOUT1
IOUT2
U2
3-Phase
AGND Total Current
Monitor
LM5170-Q1
IOUT1
No Load: 0.23 V
Max Load: 2.48 V
IOUT2
U1
3.01 kW 10~100nF
AGND
Ground MCU Local

Impedance GND
Figure 44. 3-Phase Total Current Monitor

LM5170-Q1
7.5 Programming
7.5.1 Dynamic Dead Time Adjustment
In addition to a fixed dead time programming by RDT, the dead time can be dynamically adjusted either by
applying an analog voltage or a PWM signal as shown in Figure 45. Varying the analog voltage or the duty ratio
of the PWM signal will adjust the DT programming. For analog adjustment, a single stage RC filter is
recommended to filter out any possible noise. For PWM adjustment, a two-stage RC filter is recommended to
minimize the ripple voltage resulted on the DT pin.
RADJ2 RADJ1 LM5170-Q1

DT Adjust by 10 K
10 k
Analog Voltage
DT
VADJ
CADJ1 RDT
0.1 uF AGND
Time
(a) Adjustment by Analog Voltage
RADJ3 RADJ2 RADJ1 LM5170-Q1

DT Adjust by
4.99 k 4.99 k 10 K
PWM
DT
VHI
VLO CADJ2 CADJ1 RDT
DADJ 0.1 uF 0.1 uF AGND
FADJ=10~100 kHz
(b) Dynamic Dead Time Adjustment
Figure 45. Dynamic Dead Time Adjustment
When an analog voltage is applied, the resulted dead time is determined by Equation 19:
1
§ 1 1 0.8 u VADJ · ns
tDT (VADJ ) ¨ ¸ u4 16 ns
© RDT RADJ1 RAJD2 RADJ1 R ADJ2 ¹ k:
where
• VADJ is the analog voltage used to adjust the dead time (19)
When a PWM signal is applied, the resulted dead time is determined by Equation 20:
1
§ 1 1 0.8 u ¬ª VHI VLO u DADJ VLO ¼º · ns
tDT (D ADJ ) ¨ ¸ u4 16 ns
¨ RDT R ADJ1 R AJD2 R AJD3 R ADJ1 R ADJ2 R ADJ3 ¸ k:
© ¹
where
• VHI and VLO are the high and low voltage levels of the PWM signal, respectively,
• DADJ is the duty factor of the PWM signal. (20)
7.5.2 Optional UVLO Programming

The UVLO pin is the LM5170-Q1’s master enable pin. It can be directly controlled by an external control unit like
an MCU.

LM5170-Q1
Programming (continued)
Nevertheless, the UVLO pin can also fulfill the undervoltage lockout function of a particular power rail. The rail
can be either the HV-Port, or the LV-Port, or VCC. Use a resistor divider to set the UVLO threshold, as shown in
Figure 46. The divider should satisfy Equation 21:
RUVLO2
u VUVLO 2.5V
RUVLO1 RUVLO2 (21)
The UVLO hysteresis is accomplished with an internal 25-μA current source. When UVLO > 2.5 V, the current
source is activated to instantly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below the 2.5-
V threshold the current source is turned off, causing the voltage at the UVLO pin to fall. The UVLO hysteresis is
determined by Equation 22:
VHYS RUVLO1 u 25PA (22)
An optional ceramic capacitor CUVLO can be placed in parallel with RUVLO2 to improve the noise immunity. CUVLO
is usually between 1 nF to 10 nF. A large CUVLO may cause excessive delay to respond to a real UVLO event.
If Equation 22 does not provide adequate hysteresis voltage, the user can add RUVLO3 as shown in Figure 47.
The hysteresis voltage is thus given by Equation 23:
ª § RUVLO1 · º
VHYS «RUVLO1 RUVLO3 u ¨ 1 ¸ » u 25PA
«¬ © RUVLO2 ¹ »¼ (23)
HV-Port,
or LV-Port,
or VCC
RUVLO1 25 µA
MASTER
ENABLE UVLO
+ ENABLE
-
2.5 V
CUVLO RUVLO2 AGND +
- RESET
1.5 V
LM5170-Q1
Figure 46. UVLO Programming
HV-Port,
or LV-Port,
or VCC
RUVLO1 25 µA
MASTER RUVLO3
ENABLE UVLO
+ ENABLE
-
2.5 V
CUVLO RUVLO2 AGND +
- RESET
1.5 V
LM5170-Q1
Figure 47. UVLO With Additional Hysteresis Programming

LM5170-Q1
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information

The LM5170-Q1 is suitable for the bidirectional DC-DC converters for the automotive 48-V and 12-V dual battery
systems, and battery backup systems. It can also create stackable, high power, unidirectional buck or boost
converters with balanced power sharing among multiphases.
8.1.1 Typical Key Waveforms

The following describes the typical power up sequence of the LM5170-Q1 bidirectional converter in a 48-V to 12-
V dual battery system.

LM5170-Q1
Application Information (continued)

8.1.1.1 Typical Power-Up Sequence
Figure 48 shows key waveforms of power-up sequence.
Initializ
MODE Shutdown -ation Standby Power Delivery
10 V
VCC 0V
UVLO=2.5 V
UVLO UVLO=1.5 V
Fault Detection Interval
nFAULT
I(BRKG)
VGS_BRK 8.5 V
0V
INTERNAL(PWR_GD)
VIN
0V
VINX
OSCILLATOR
DIR
ISET
EN1,2
1.0 V
SS
‡‡‡‡‡‡
HO1
‡‡‡‡‡‡
LO1
‡‡‡‡‡‡
HO2
‡‡‡‡‡‡
LO2
Figure 48. Typical Turnon Sequence Key Waveforms

LM5170-Q1
Application Information (continued)

8.1.1.2 One to Eight Phase Programming
Figure 49 and Table 3 show a typical logic control signals and external clock requirements to run an eight phase
system
Table 3. Multiphase Programming

1Φ 2Φ 3Φ 4Φ 6Φ 8Φ
A7 0 0 0 0 0 1
A6 0 0 0 0 0 1
A5 0 0 0 0 1 1
A4 0 0 0 0 1 1
A3 0 0 0 1 1 1
A2 0 0 1 1 1 1
A1 0 1 1 1 1 1
A0 1 1 1 1 1 1
OPT (B0) 1 1 0 1 1 1
SYNC
— — — — 0° 0°
(C0)
(C1) — — — — 60° 45°
B0
A3
A2
A1
A0
0 Deg EN1 EN2 VCCA EN1 EN2 VCCA

C0 SYNCIN
SYNCIN
SYNCOUT OPT OPT
SYNCOUT
DIR DIR
OSC OSC
ISETD ISETD
AGND AGND
MCU
A7
A6
A5
A4
C1
SYNCIN SYNCIN
SYNCOUT OPT OPT
SYNCOUT
DIR OSC DIR OSC
ISETD AGND ISETD AGND
Figure 49. Eight Phase Configuration

LM5170-Q1
8.1.2 Inner Current Loop Small Signal Models

The following describes the inner current loop that is controlled by the LM5170-Q1. The outer voltage loop should
be managed by the MCU, or by an external analog circuit. The interface signals between the inner current loop
and outer voltage loop are basically the DIR and ISET signals, of which the DIR signal controls the current
direction, and the ISET signal carries the outer voltage loop's error information.
8.1.2.1 Small Signal Model

Figure 50 shows the current loop block diagram. The power plant transfer function from the error voltage (Vea) to
the channel inductor current (iLm) is determined by the following, regardless the current flow direction.
ILm
HV-Port
LV-Port
Lm Rcs
V48 V12
DIR
1 1 50X
DIR
0 0
D (1-D) D
PWM Vea
±
+ Gm
+ ISETA
± COMP
Ramp
Generator RCOMP
RAMP CHF Type II Compensator
Vramp
CCOMP
KFFV48
Figure 50. Control Loop Block Diagram

Öi 1 1
Lm
H(s) u
VÖ
ea KFF u (RCS RS )
su
Lm
1
RCS RS
where
• Lm is the power inductor,
• RCS the current sense resistor,
• RS the equivalent total resistance along the current path excluding RCS,
• KFF the ramp generator coefficient. When the RAMP signal is generated per Equation 14 , KFF = 0.104. (24)
8.1.2.2 Inner Current Loop Compensation

Equation 24 indicates that the power plant is basically a first-order system. A Type-II compensator as shown in
Figure 50 is adequate to stabilize the loop for both buck and boost mode operations.
Assuming the output impedance of the gm amplifier is RGM, the gain from the inductor to the output of gm
amplifier is determined by Equation 25:
VÖ ea
G(s) 50 u RCS u Gm u >RGM II ZCOMP (s)@
Öi
Lm
where
• the coefficient 50 is the current sense amplifier gain;
• Gm is the transconductance of the gm error amplifier, which is 1 mA/V;
• ZCOMP(s) is the equivalent impedance of the compensation network seen at the COMP pin, namely
Equation 26 (25)

LM5170-Q1
1 1 s u RCOMP u CCOMP
ZCOMP (s) u
CHF CCOMP § C u CCOMP ·
s u ¨ 1 s u RCOMP u HF ¸
© CHF CCOMP ¹ (26)
Usually CHF is << CCOMP. Thus Equation 26 can be simplified to Equation 27:
1 1 s u RCOMP u CCOMP
ZCOMP (s) u
CCOMP s u 1 s u RCOMP u CHF (27)
Because RGM is > 5 MegΩ, and the frequency range for loop compensation is usually above a few kHz, the
effects of RGM on the loop gain in the interested frequency range becomes negligible. Therefore, substituting
Equation 28 into Equation 25, and neglecting RGM, one can get the following:
VÖ ea 50 u RCS u Gm 1 s u RCOMP u CCOMP
G(s) u
Öi CCOMP s u (1 s u RCOMP u CHF )
Lm (28)
The total open-loop gain of the inner current loop is the product of H(s) and G(s):
Gtotal (s) H(s) u G(s) (29)
Or:
1 50 u RCS u Gm 1 s RCOMP u CCOMP
Gtotal (s) u u
KFF u CCOMP Lm s u (1 s u RCOMP u CHF )
su 1
RCS RS (30)
The poles and zeros of the total loop transfer function are determined by:
fp1 0 (31)
(RCS RS )
fp2
2S u Lm (32)
1
fp3
2S u RCOMP u CHF (33)
1
fz
2S u RCOMP u CCOMP (34)
To tailor the total inner current loop gain to cross over at fCO, select the components of the compensation
network according to the following guidelines, then fine tune the network for optimal loop performance.
1. The zero fz is placed at the power stage pole fp2,
2. The pole fp3 is placed at about two decade higher then fCO,
3. The total open-loop gain is set to unity at fCO, namely,
H(2i u S u fCO ) u G(2i u S u fCO ) 1 (35)
Therefore, the compensation components can be derived from the above equations, as shown in Equation 36.
-
°
° 1 KFF
°RCOMP u 2iuSufCO uLm (RCS RS )
50uRCS uGmu H(2iuSufCO 50uRCS uGm
°
® Lm
° CCOMP
° (RCS RS )uRCOMP
° CCOMP
° CHF
100
¯ (36)

LM5170-Q1
8.1.3 Compensating for the Non-Ideal Current Sense Resistor

TI strongly recommends employing a non-inductive resistor for RCS. Even a few nH of inductance will cause the
current sense signal to be remarkably distorted, as shown in Figure 51. The adversary consequences include
reduced peak current limit than actually programmed and false current zero-crossing detection well above 0 A.
The former may reduce the available maximum current to be delivered; and the latter will terminate the sync FET
gate early and the body diode will be used to conduct the remaining current, thereby reducing the efficiency as
well as the accuracies of the channel DC current regulation and IOUT monitors under light load.
When the current sense resistor has some parasitic inductance, it is necessary to compensate the effects of
inductance with an RC circuit, as shown in Figure 52. The user should place a 1-Ω resistor in each of the current
sense signal path, and the selection of CCS should satisfy Equation 37, assuming the inductance of the current
sense resistor is LCS:
LCS
CCS
2: u RCS (37)
For instance, if RCS =1 mΩ, LCS = 1 nH, the required compensation capacitor CCS should be about 0.5 µF.
Note that selecting CCS greater than the value given by Equation 37 would over compensate the inductance and
consequently defer the current zero crossing detection point to a negative current. Excessively larger capacitor
should not be used to prevent malfunction of the controller.
Main FET
Vgs
0
IL
Inductor Current
0
LCS dIL
False 0- dt
Crossing
VCS
xx
0
xx
xx xx
x
Sync FET
Vgs
0 x
time
Body Diode Used
Figure 51. Effects of Parasitic Inductance on the Current Sense Signal and Zero Crossing Detection

LM5170-Q1
ILm1 Lcs1 Rcs1

LV-Port
Lm1
V12
+
1: 1: ±
CCS1
CSA1 CSB1
LM5170-Q1
CSA2 CSB2
CCS2
1: 1:
Lm2
ILm2 Lcs2 Rcs2
Figure 52. Compensation Network to Compensate the Current Sense Resistor’s Parasitic Inductance
8.1.4 Outer Voltage Loop Control

The LM5170-Q1 serves as a current regulator that regulates the DC component of the power inductor current to
the value programmed at the ISETA pin. To regulate the output voltage, an outer voltage loop should be
employed. The outer voltage loop can be implemented with an analog circuit (see Figure 53) or a digital circuit
like an MCU (see Figure 54). The error voltage signal of the output voltage loop is the ISET command for the
inner current loop.TI advises that the outer voltage loop crossover frequency should be one decade below that of
the inner current loop crossover frequency fCO. Refer to the LM5170-Q1 Quick Start Calculator for the loop
compensation guidance.

LM5170-Q1
ILm
HV-Port(48 V) LV-Port (12 V)
Lm Rcs
DIR 1 1
0 0 DIR
D (1-D) D
Gm
PWM Vea ±
+
+ ISETA
± COMP
Vramp
kFF
FF Ramp
Generator
½ LM5170-Q1
± ISET ±
DIR REF + + REF

48 V Error Amp 12 V Error Amp
EN EN
BST SS
BK SS
Figure 53. Analog Outer Voltage Loop Control
HV-Port (48 V) LV-Port (12 V)
Lm Rcs
DIR 1 1
0 0 DIR
D (1-D) D
Gm
PWM Vea ±
+
+ ISETA
± COMP
Vramp
kFF
FF Ramp
Generator
½ LM5170-Q1
DIR
ISET
ADC
±
PID
Vout Set
+
Microcontroller
Figure 54. Digital Outer Voltage Loop Control

LM5170-Q1
8.2 Typical Application

8.2.1 60-A, Dual-Phase, 48-V to 12-V Bidirectional Converter
A typical application example is a 60-A, dual-phase bidirectional converter as shown in Figure 55. The HV-Port
voltage range is 32 V to 70 V and the LV-Port 0 V to 23 V. Each phase is able to deliver 30-Adc current through
the inductor.
Lm1 RCS1
4.7 µH
CHB1 1m
+ +
C1 QH1 0.22 µF C2
HV-Port LV-Port
- 100 µF 470 µF -
VCC QL2
PGND PGND
DHB1
PGND
22 24 23 20 18 36 35
SW1
HB1
LO1
PGND
HO1
CSA1
CSB1
VCC 6 VIN BRKG 34
RBRKG
RBRKS
10 k
+ 19 VCC BRKS 33
CVCC
+10Vdc RVCCA 10 k
- 2.2 µF 24.9
31 VCCA VINX 4
RRAMP1
C5 29 OPT 95.3 k
PGND RAMP1 28
1 µF CRAMP1
46 AGND RRAMP2
1 nF
ROSC 95.3 k
47 OSC RAMP2 8
CRAMP2
40.2 k
42 ISETD 1 nF
CCOMP1 RCOMP1 634

PGND AGND 40 SYNCIN
RSYNCO COMP1 26
LM5170-Q1
41 SYNCOUT 15 nF CHF1
10 k 1 nF
AGND
10 UVLO CCOMP2 RCOMP2 634
CMMD AND
COMP2 11
MONITOR 39 EN1
15 nF CHF2
ENABLE 43 EN2 1 nF
44 DIR RDT 10 k
DIR
DT 48
ISETA 45 ISETA CSS 10 nF
SS 12
27 nFAULT ROVPA 51.1 k
OVPA 25
IOUT1 37 IOUT1 ROVPB 54.9 k
CIOUT1 OVPB 9
RIOUT1
10 nF 9.09 k RIPK 40.2 k
IPK 30
IOUT2 38 IOUT2
CIOUT2
RIOUT2
AGND
CSA2
CSB2
SW2
10 nF 9.09 k
HO2
HB2
LO2
15 13 14 17 1 2
AGND
VCC
DHB2
CHB2
QH2 0.22 µF Lm2
RCS2
4.7 µH
1m
QL2
C8 C10
470 µF
100 µF
PGND PGND PGND
Figure 55. Schematic of the Example Dual-Phase Bidirectional Converter

LM5170-Q1
Typical Application (continued)

8.2.1.1 Design Requirements
Table 4 lists the design parameters for this example.
Table 4. Design Parameters

PARAMETER EXAMPLE VALUE NOTE
VLV_min 6V LV-Port minimum operating voltage
VLV_reg 14 V LV-Port nominal voltage
VLV_max 18 V LV-Port maximum operating voltage
VHV_min 32 V HV-Port minimum operating voltage
VHV_reg 48 V HV-Port nominal operating voltage
VHV_max 60 V HV-Port maximum operating voltage
FSW 100 kHz Switching frequency
Imax 30 A Maximum channel DC current, bidirectional
Itotal 60 A Total bidirectional DC at the LV-Port
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Determining the Duty Cycle

Obviously, the duty cycles are determined by through :
VLV_reg 14V
DBK_min 0.2
VHV max 70V (38)
VLV_reg 14V
DBK_max 0.438
VHV min 32V (39)
VHV_reg VLV_max 50V 23V
DBST_min 0.54
VHV_reg 50V (40)
VHV_reg VLV_min 50V 6V
DBST_max 0.88
VHV_reg 50V (41)
8.2.1.2.2 Oscillator Programming

To operate the converter at the desired switching frequency FSW, select the ROSC by satisfying Equation 17,
namely,
40k: u 100kHz
ROSC 40 k:
100 kHz (42)
Choose the closest standard resistor, that is, ROSC =40.2 kΩ.
8.2.1.2.3 Power Inductor, RMS and Peak Currents

The inductor current has a triangle waveform, as shown in Figure 51. TI recommends selecting an inductor such
that its peak-to-peak ripple current is less than 80% of the channel inductor full load DC current. Therefore, the
inductor should satisfy Equation 43:
VLV_reg u 1 DBK _ min 14V u (1 0.2)
Lm t 4.67 PH
80% u Imax u Fsw 0.8 u 30A u 100 kHz (43)
Select Lm = 4.7 µH.
Then, the actual inductor peak to peak inductor current is determined by Equation 44:
VLV_reg u (1 DBK_min ) 14V u (1 0.2)
Ipk pk 23.83 A
Lm u Fsw 4.7PH u 100 kHz (44)

LM5170-Q1
The peak inductor current is determined by Equation 45:

Ipk pk 23.83
Ipeak Imax 30A 41.9 A
2 2 (45)
Select an inductor that has a saturation current Isat at least 20% greater than Ipeak to ensure full power with
adequate margin. In this example, TI recommends selecting an inductor of Isat > 49 A.
The power inductor’s full load Root Mean Square (RMS) current ILM_RMS determines its conduction losses. The
RMS current is given by Equation 46:
2 1 2
ILm_RMS Imax u Ipk pk 30.8 A
12 (46)
8.2.1.2.4 Current Sense (RCS)

To achieve the highest regulation accuracy over wider load range, the user should target to create 50-mV of VCS
at full current. Therefore, RCS should be selected as Equation 47:
50mV 50mV
RCS d 1.667 m:
Imax 30A (47)
Ideally, a 1.5-mΩ current sense resistor should be chosen for this example. However, owing to availability, a
standard non-inductive 1-mΩ current sense resistor is selected, namely,
RCS 1.0 m: (48)
Because RCS conducts the same current as the power inductor, its power dissipation is also determined by
ILm_RMS.
If the selected RCS has parasitic inductance (assuming it is 1 nH), it should be compensated, and the
compensation capacitor CCS should satisfy Equation 37.
LCS 1nH
CCS 0.5 PF
2: u Rsn 2: u 1m: (49)
Select the closest standard capacitor, CCS = 0.47 µF.
For optimal performance, it is good practice to add a 100-pF ceramic capacitor at each current sense pin to filter
out common-mode noise, as shown in Figure 56.

LM5170-Q1
ILm1 Lcs1 Rcs1

LV-Port
Lm1
V12
+
1: 1: -
100 pF CCS1 100 pF
CSA1 CSB1
LM5170-Q1
CSA2 CSB2
100 pF 100 pF
CCS2
1: 1:
Lm2
ILm2 Lcs2 Rcs2
Figure 56. Current Sense With Compensation to Cancel the Effects of Parasitic Inductances
8.2.1.2.5 Current Setting Limits (ISETA or ISETD)

TI recommends setting a hard limit of the maximum current programming signal such that the converter cannot
be over driven by an errant current programming signal. Assume the converter is allowed up to 10% overloading
current. Refer to Equation 7, the analog current setting signal ISETA should be limited by the following voltage
level:
110% u Imax u RCS 110% u 30A u 1m:
VISETA_max d 1.55 V
0.02 0.02 (50)
Refer to Equation 10, the PWM current setting signal ISETD should be limited by the following duty cycle:
110% u Imax u RCS 110% u 30A u 1m:
DISETD_max d 52.8%
0.0625V 0.0625V (51)
8.2.1.2.6 Peak Current Limit

One purpose of the peak current limit is to protect the power inductor from saturation. Select RIPK such that the
peak current limit threshold is 5~10% greater than Ipeak. According to Equation 13, one gets:
RCS u 105% u Ipeak 1m: u 105% u 41.9A
RIPK 40 k:
1.1PA 1.1PA (52)
Select RIPK = 40.2 kΩ, which results in a nominal inductor peak current limit of 44.2 A per channel.

LM5170-Q1
8.2.1.2.7 Power MOSFETS

The power MOSFETs must be chosen with a VDS rating capable of withstanding the maximum HV-port voltage
plus transient spikes (ringing). In this example, the maximum HV-rail voltage is 70 V. Selecting the 80 V rated
MOSFETs will allow 10-V transient spikes.
When the voltage rating is determined, select the MOSFETs by making tradeoffs between the MOSFET Rds(ON)
and total gate charge Qg to balance the conduction and switching losses. For high power applications, parallel
MOSFETs to share total power and reduce the dissipation on any individual MOSFET, hence relieving the
thermal stress. The conduction losses in each MOSFET is determined by Equation 53.
1.8 u Rds(ON) 2
PQ_cond u IQ_RMS
N
where
• N is the number of MOSFETs in parallel
• 1.8 is the approximate temperature coefficient of the Rds(ON) at 125 °C
• and the total RMS switch current IQ_RMS is approximately determined by Equation 54 (53)
IQ_RMS | Dmax u Imax Dmax u Imax
where
• Dmax is the maximum duty cycle, either in the buck mode or boost mode. (54)
The switching transient rise and fall times are approximately determined by:
N u Qg
'trise |
4A (55)
N u Qg
't fall |
4A (56)
And the switching losses of each of the paralleled MOSFETs are approximately determined by:
1 2 1 Ipeak
PQ_sw u Coss u VHV u Fsw u u VHV u ('trise 't fall ) u Fsw
2 2 N
where
• Coss is the MOSFET’s output capacitance. (57)
The power MOSFET usually requires a gate-to-source resistor of 10 kΩ to 100 kΩ to mitigate the effects of a
failed gate drive. When using parallel MOSFETs, a good practice is to use 1- to 2-Ω gate resistor for each
MOSFET, as shown in Figure 57.
HV-Port To Inductor
100 K
100 K 100 K
100 K
1 1 1 1
HO SW LO PGND
LM5170-Q1
Figure 57. Paralleled MOSFET Configuration

LM5170-Q1
If the dead time is not optimal, the body diode of the power synchronous rectifier MOSFET will cause losses in
reverse recovery. Assuming the reverse recovery charge of the power MOSFET is Qrr, the reverse recovery
losses are thus determined by Equation 58:
PQ_rr Qrr u VHV_max u Fsw (58)
To reduce the reverse recovery losses, an optional Schottky diode can be placed in parallel with the power
MOSFETs. The diode should have the same voltage rating as the MOSFET, and it must be placed directly
across the MOSFETs drain and source. The peak repetitive forward current rating should be greater than Ipeak,
and the continuous forward current rating should be greater than the following Equation 59:
ISD_avg Ipk u tDT u Fsw (59)
8.2.1.2.8 Bias Supply

The LM5170-Q1 requires an external 10- to 12-V VCC bias supply to operate. If not available in the system, the
user can generate it from the LV-port using a buck-boost or SEPIC converter, or from the HV-port using a buck
converter. Refer to the Texas Instruments LM25118-Q1/LM5118-Q1 to implement a buck-boost converter, or
LM5001-Q1 to implement a SEPIC converter, or the LM5160-Q1/LM5161-Q1 to implement a buck converter.
The total load current of the bias supply is mainly determined by the total MOSFET gate charge Qg. Assume the
system employs multiple LM5170-Q1s to implement M number of phases, and each phase uses N number of
MOSFETs in parallel as one switch. There will be 2x N MOSFETs per phase to drive. Then the total current to
drive these MOSFETs through VCC bias supply is determined by Equation 60.
IVCC 2 u M u N u Qg u Fsw M u 5mA
where
• 5 mA is the worst case maximum current used by the control logic circuit of each phase. (60)
In an example of a four-phase system employing two parallelled MOSFETs for one switch, where M=4, N=2,
Qg=100 nC, and Fsw=100 KHz, the bias supply should be able to support at least the following total load current:
IVCC t 2 u 4 u 2 u 100nC u 100kHz 4 u 5mA 180 mA (61)
In an example of an eight-phase system employing the same parallel MOSFETs for one switch, the bias supply
should be able to support the following total load current:
IVCC_8ph 2 u 8 u 2 u 100nC u 100kHz 8 u 5mA 360 mA (62)
The VCC AC bypass ceramic capacitor CVCC = 1 ~ 2.2 µF, rated at least 16 V, must be placed close to the VCC
and PGND pins. Similarly, a ceramic capacitor CVCCA = 1 µF, rated at least 16 V, must be placed close to the
VCCA and AGND pins. Place a 24-Ω resistor between VCC and VCCA pins.
8.2.1.2.9 Boot Strap

Select a ceramic capacitor CHB1 = CHB2 =0.1 ~ 0.22 µF, placed close to the HB and SW pins. The fast switching
diode of the forward current rated at 1-A and reverse voltage not lower than VHV_max should be selected as the
boot strap diode, through which the boot capacitor CHB1 or CHB2 is charged by VCC. To reduce the noise caused
by the fast charging current, a 2-Ω to 5-Ω current limiting resistor must be placed in series with each boot diode.
8.2.1.2.10 RAMP Generators

According to Equation 14, the ramp generator should be selected such that a peak voltage of 5 V is produced
each cycle when the HV-port voltage is 48 V.
Select CRAMP1 = CRAMP2 = 1 nF. Therefore,
9.6 9.6
RRAMP 96 k:
Fsw u CRAMP 100kHz u 1nF (63)
Choose the closest standard resistor value, namely,
RRAMP1 = RRAMP2 = 95.3 kΩ.
For optimal performance, CRAMP1 and CRAMP2 should be ceramic capacitors with tolerance not greater than 10%.
Capacitors of the 5% or 1% C0G/NPO types are preferred.

LM5170-Q1
8.2.1.2.11 OVP
As shown in Figure 36 and Figure 37, the HV-Port and LV-Port overvoltage protection thresholds can be
programmed by ROVPA and ROVPB, respectively. These resistor values are determined by Equation 64 and
Equation 65.
1.185V 1.185V
ROVPA u 3000k: u 3000k: 51.66 k :
VOVPA th 1.185V 70V 1.185V (64)
1.185V 1.185V
ROVPB u 1000k: u 1000k: 54.3 k:
VOVPB th 1.185V 23V 1.185V (65)
Select the closest standard resistor values. In this example, ROVPA = 51.1 kΩ, and ROVPB = 54.9 kΩ.
8.2.1.2.12 Dead Time

To use the built-in adaptive dead time, the DT pin must be connected to VCCA pin.
To program the dead time, follow Equation 15 to select the resistor RDT. To dynamically adjust the dead time with
an external analog voltage signal, follow Equation 19. To dynamically adjust the dead time with an external PWM
signal, follow Equation 20.
In the example circuit, the nominal dead time is selected to be 55 ns. According to Equation 15, the programming
resistor should be:
ns
tDT RDT u 4 16ns
k: (66)
tDT 16ns k: 55 ns 16 ns k:
RDT u1 u1 9.75 k:
4 ns 4 ns (67)
Select the standard value, RDT = 10 kΩ.
8.2.1.2.13 IOUT Monitors

TI recommends making the following selections:
RIOUT1 = RIOUT2 = 9.09 kΩ (68)
CIOUT1 = CIOUT2 = 0.01 µF (69)
Then the monitors' delay is determined by the following time constant:
WIOUT RIOUT1 u CCIOUT1 9.09k:u 0.01PF 90.9 Ps (70)
At full load, the DC component of the monitor voltage is determined by:
§ Imax u RCS · § 30A u 1m: ·
VIOUT1 VIOUT2 ¨ 25PA ¸ u RIOUT1 ¨ 200: 25PA ¸ u 9.09k: 1.591 V
© 200: ¹ © ¹ (71)
Because the inductor ripple current is 23.8 A, according to Equation 11, the IOUT peak to peak ripple current will
be:
Ipk pk u RCS 23.8A u 1m:
'IOUT1 119 PA
200: 200: (72)
The RC filter corner frequency is thus given by:
1 1
FIOUT 1.75 kHz
6.28 u RIOUT u CIOUT 6.28 u 9.09k: u 10nF (73)
The resulting peak-to-peak monitor ripple voltage is approximately determined by:
§ F · § 100kHz ·
log¨ sw ¸ log¨ ¸
'VIOUT 'IOUT1u RIOUT u 10 © FIOUT ¹ 119PA u 9.09k: u 10 © 1.75kHz ¹ 19 mV (74)
Which is about 1.1% peak-to-peak ripple on top of the full load DC monitor voltage. Increasing CIOUT value will
further attenuate the ripple voltage, but also cause longer monitor delays.

LM5170-Q1
8.2.1.2.14 UVLO Pin Usage

The example circuit uses the UVLO pin as the LM5170-Q1’s master enable pin. However, the UVLO pin can also
fulfill the function of undervoltage lockout, either the 48-V rail UVLO, or 12-V rail UVLO, or VCC UVLO.
Assume the user implements the 48-V rail UVLO, and the low-side resistor RUVLO2 = 10 kΩ, the 48 V UVLO
release threshold VUVLO = 24 V, and UVLO hysteresis is VHYS =2.4 V. Referring to Figure 47 and Equation 21,
one can find that RUVLO1 is given by:
UUVLO 2.5V 24V 2.5V
RUVLO1 u RUVLO2 u 10k: 86 k:
2.5V 2.5V (75)
The final selection should select the closest standard resistor of RUVLO1 = 86.6 kΩ.
And RUVLO3 should satisfy Equation 23, namely,
VHYS 24V
RUVLO1 86.6k:
25PA 25PA
RUVLO3 0.973 k:
RUVLO1 86.6k:
1 1
RUVLO2 10k: (76)
Select the closest standard resistor, RUVLO1 = 976 Ω.
If the user chooses to add the capacitor CUVLO = 1 nF, it leads to a delay time constant of 10 µs to filter possible
noise at the at the UVLO pin.
8.2.1.2.15 VIN Pin Configuration

The VIN pin must always be connected to the HV voltage rail. It is good practice to add a small RC filter to
improve the VIN noise immunity, as shown in Figure 58. Usually the filter resistor selection is 10 to 20 Ω, and the
bypass capacitor is 0.1 µF to 1.0 µF.
HV-Port
RVIN
10
VIN
CVIN
0.1~1.0 µF AGND
LM5170-Q1
Figure 58. VIN Pin Configuration
8.2.1.2.16 Loop Compensation

Assuming the total resistance along the current path including the external power cables, PCB current tracks,
and battery internal impedances is 50 mΩ, according to Equation 36, the compensation network for the inner
current loop is determined by:
-
°
°
°RCOMP KFF
u 2iuSufCO uLm (RCS RS ) =
0.104
u 2iuSu10kHzu4.7 + P N
°° 50uRcs uGm 50u1m u P$ 9
® Lm 4.7 +
° CCOMP 147 nF
° (RCS RS )uRCOMP (50m P u N
° CCOMP
° CHF
100
1.47nF
°̄ (77)

LM5170-Q1
Selecting the closest standard values for the compensation network, namely,
RCOMP1 = RCOMP2 = 634 Ω
CCOMP1 = CCOMP2 = 150 nF
CHF1 = CHF2 = 1 nF
These initial component selections produce a total loop phase margin of 90°, which is larger than necessary.
Fine tune the loop compensation by reselecting CCOMP1 = CCOMP2 = 15 nF, then the phase margin will be 45° for
an optimal dynamic performance.
Figure 59 shows the Bode Plots of the power plant, the compensation gain, and the resulting total open loop.
60
Power Plant
40
Compensation
Total Loop
Gain (dB)
20
20
40
3 4 5 6
100 1u10 1u10 1u10 1u10
180
150
Phase (deg)
120
90
60
30
0
3 4 5 6
100 1u10 1u10 1u10 1u10
Frequency (Hz)
Figure 59. Bode Plots of the Example Converter
8.2.1.2.17 Soft Start

Soft start can be programmed with a ceramic capacitor CSS. Note that CSS also determines the retry frequency
when the converter is an under overvoltage condition (OVPA or OVPB). Because the soft start completes when
the SS pin voltage reaches about 5 V, the capacitor CSS can be chosen by Equation 78 to limit the full load start-
up time within ΔTSS = 2 ms:
25 PA u 'TSS 25 PA u 2ms
CSS 10 nF
5V 5V (78)

LM5170-Q1
Select the closest standard ceramic capacitor, that is, CSS = 10 nF.
8.2.1.2.18 ISET Pins

To control the current setting by an analog voltage, ground the ISETD pin. To control the current setting by a
PWM signal, there are two options to choose.
The first option is to use the built-in ISETD-to-ISETA decoder as shown in Figure 22. The PWM duty cycle to
ISETA voltage conversion ratio satisfies Equation 8. The selection of CISETA and FISETD should be constrained by
Equation 1 and Equation 4. The advantages of this option include convenience and current control accuracy. The
drawback is the delay it may cause.
Another option is to use an external two-stage RC filter to convert the PWM ISETD signal to a DC voltage
feeding the ISETA pin as shown in Figure 60. To achieve the same ISETA ripple voltage, this option only
requires CISETA =1.5 nF, and the delay time of this two-stage filter is only 10% of the built-in decoder, or 15 µs
versus the built-in decoder’s 150 µs. The drawback of this option is the conversion errors if the PWM signal
voltage levels are not well regulated. This option is more suitable for operation under a closed digital outer
voltage loop because the ISETD to ISETA conversion error can be readily compensated by the closed outer
voltage loop.
ISETD
PWM 10 k 10 k LM5170-Q1
ISETA
1.5 nF 1.5 nF
ISETD
AGND
Figure 60. Two-Stage RC Filter to Convert the PWM into an Analog Voltage at the ISETA Pin

LM5170-Q1
8.2.1.3 Application Curves
Figure 61. Channel Inductor Current and IOUT Tracking Figure 62. Diode Emulation Prevents Negative Current
ISETA Command
Figure 63. Channel Inductor Current and Monitor Figure 64. Start-Up Sequence Following UVLO Enable
Responses to Dynamic DIR Change
Figure 65. nFAULT Shutdown Latch Figure 66. Boot Capacitor Pre-Charge During Start-Up in
Buck Mode

LM5170-Q1
Figure 67. Dual=Channel Interleaving Operation: Buck Figure 68. Dual-Channel Interleaving Operation: Boost
Mode Mode
Figure 69. LV-Port OVP: Buck Mode Figure 70. HV-Port OVP: Boost Mode
9 Power Supply Recommendations

The LM5170-Q1-based converter is designed to operate with two differential voltage rails like the 48-V and 12-V
dual battery system, or a storage system having a battery on one end and the Super-Cap on the other end.
When operating with bench power supplies, each supply should be capable of sourcing and sinking the
maximum operating current. This may require to parallel an Electronic load (E-Load) with the bench power
supply (PS) to emulate the batteries, as shown in Figure 71.
It can also be used with a voltage source on one end and a load on the other end if the outer voltage control loop
is closed. The outer voltage loop can be implemented either with digital means like an MCU or with analog
circuit, as shown in Figure 53 and Figure 54.
V48 V12
LM5170-Q1
+ Bi-Directional +
- Converter -
RTN RTN
E-Load PS E-Load
PS
Figure 71. Emulated Dual Battery System With Bench Power Supplies and E-Loads

LM5170-Q1
10 Layout
10.1 Layout Guidelines

Careful PCB layout is critical to achieve low EMI and stable power supply operation as well as optimal efficiency.
Make the high frequency current loops as small as possible, and follow these guidelines of good layout practices:
1. For high power board design, use at least a 4-layer PCB of 2-oz or thicker copper planes. Make the first
inner layer a ground plane that is adjacent to the top layer on which the power components are installed, and
use the second inner layer for the critical control signals including the current sense, gate drive, commands,
and so forth. The ground plane between the signal and top layers helps shield switching noises on the top
layer away from affecting the control signals.
2. Optimize the component placements and orientations before routing any traces. Place the power
components such that the power flow from port to port is direct, straight and short. Avoid making the power
flow path zigzag on the board.
3. Identify the high frequency AC current loops. In the bidirectional converter, the AC current loop of each
channel is along the path of the HV-port rail capacitors, high-side MOSFET, low-side MOSFET, and back to
the HV-port rail capacitors’ return. Place these components such that the current flow path is short, direct
and the special area enclosed by the loop is minimized.
4. Place the power circuit symmetrically between CH-1 and CH-2. Split the HV-port rail capacitors and LV-port
rail capacitors evenly between CH-1 and CH-2.
5. If more than one LM5170-Q1 is used on the same PCB for multi phases, place the circuits of each LM5170-
Q1 in the similar pattern.
6. Use adequate copper for the power circuit, so as to minimize the conductions losses on high-current PCB
tracks. Adequate copper can also help dissipate the heat generated by the power components, especially the
power inductors, power MOSFETs, and current sense resistors. However, pay attention to the polygon of the
switch node, which connects the high-side MOSFET source, low-side MOSFET drain, power inductor, and
the controller SW pin. The switch node polygon sees high dv/dt during switching operation. To minimize the
EMI emission by the switch node polygon, make its size sufficient but not excessive to conduct the switched
current.
7. Use appropriate number of via holes to conduct current to, and heat through, the inner layers.
8. Always separate the power ground from the analog ground, and make a single point connection of the power
ground, analog ground, and the EP pad, at the location of the PGND pin.
9. Minimize current-sensing errors by routing each pair of CSA and CSB traces using a kelvin-sensing directly
across the current sense resistors. The pair of traces must be routed closely side by side for good noise
immunity.
10. Route sensitive analog signals of the CS, IOUT, COMP, OVPA, and OVPB pins away from the high-speed
switching nodes (HB, HO, LO, and SW).
11. Route the paired gate drive traces, namely the pairs of HO1 and SW1, HO2 and SW2, LO1 and return, and
LO2 and return, closely side by side. Route CH-1 gate drive traces in symmetry with CH-2’s.
12. Place the IC setting, programming and controlling components as close as possible to the corresponding
pins, including the following component: ROSC, RDT, RIPK, CRAMP1, CRAMP2, ROVPA, ROVPB, CISETA, CCOMP1,
RCOMP2, CCOMP1, CCOPM2, CHF1, and CHF2.
13. Place the bypass capacitors as close as possible to the corresponding pins, including CVIN, CVCC, CVCCA,
CHB1, CHB2, COPVA, COVPB, as well as the 100-pF current sense common-mode bypassing capacitors.
14. Flood each layer with copper to take up the empty areas for optimal thermal performance.
15. Apply heat sink to components as necessary according to the system requirements.

LM5170-Q1
10.2 Layout Examples

The following figures are some examples illustrating these layout guidelines. For the detailed PCB layout artwork
of the LM5170-Q1 Evaluation Module (LM5170EVM-BIDIR), please refer to the LM5170-Q1 EVM User's Guide
(SNVU543).
GND
S
GND
D
L
CH-1 AC
Loop
G
LV(+12 V)
HV(+48 V)
G
RCS
S
D
D
D
LV(+12 V)
S
LV-PORT
G Circuit
HV-PORT
TVS S G
Breaker GND
G
LV(+12 V) GND
S
G S
D
D
S
G
D
RCS
GND HV(+48 V)
CH-2 AC
LM5170-Q1 Loop
D
Controller L
G
Figure 72. A Layout Example of Dual-Channel Power Circuit Placement

LM5170-Q1
Layout Examples (continued)
D
L
CH-1
G
HV(+48 V)
D
HO1
SW1
To LM5170-Q1
S G
LO1
GND
PGND
PGND
GND
LO2 G S
SW2
HO2
HV(+48 V)
S
L
D
CH-2
G
Figure 73. A Layout Example of MOSFET Gate Drive Routing
RCS To LM5170-Q1
(a) Kelvin Contact of Resistor without Sense Pins
RCS To LM5170-Q1
(b) Kelvin Contact of Resistor with Sense Pins
Figure 74. A Layout Example of Current Sense Routing

LM5170-Q1
To AGND
From VCC
To CH-2
Current
Sense
From OPT
From nFAULT
OVPB
COMP1
nFAULT
RAMP1
OPT
IPK
VCCA
NC
BRKS
BRKG
CSB1
CSA1
From UVLO
IOUT1 SW1
IOUT2 HB1
Or System
HO1
Controller
EN1
To MCU
NC To CH-1
SYNCIN
MOSFETs
SYNCOUT LO1
LM5170-Q1 EP
ISETD VCC
To +10V Supply
EN2 PGND
DIR LO2
To CH-2
ISETA NC MOSFETs
AGND HO2
OSC HB2
DT SW2
COMP2
RAMP2
OVPA
UVLO
CSB2
CSA2
VINX
VIN
NC
NC
NC
SS
Single Point
Ground
Connection To CH-2
Current
Sense
To AGND
Figure 75. A Layout Example of LM5170-Q1 Critical Signal Routing

LM5170-Q1
11 Device and Documentation Support
11.1 Device Support

11.1.1 Development Support
For development support, see the following:
• LM25118-Q1
• LM5118-Q1
• LM5001-Q1
• LM5160-Q1
• LM5161-Q1
11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 23-Nov-2016
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
LM5170QPHPRQ1 ACTIVE HTQFP PHP 48 1000 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 150 LM5170Q1
& no Sb/Br)
LM5170QPHPTQ1 ACTIVE HTQFP PHP 48 250 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 150 LM5170Q1
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM5170QPHPTQ1 HTQFP PHP 48 250 180.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM5170QPHPTQ1 HTQFP PHP 48 250 213.0 191.0 55.0
Pack Materials-Page 2
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5 Pin Configuration and Functions

(1) Note: G = Ground, I = Input, O = Output, P = Power

Pin Functions (continued)

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Pin Functions (continued)

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6.2 ESD Ratings

6.3 Recommended Operating Conditions

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Recommended Operating Conditions (continued)

6.4 Thermal Information

6.5 Electrical Characteristics

Electrical Characteristics (continued)

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Electrical Characteristics (continued)

Internal pulldown impedance VSYNCIN = 2.5 V 100 kΩ

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Electrical Characteristics (continued)

Internal pulldown impedance 1 MΩ

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6.6 Typical Characteristics

VCCA Quiescent Current (PA)

± ƒ& 25°C 150°C ± ƒ& 25°C 150°C

Figure 1. VIN Shutdown IQ Figure 2. VCCA Shutdown IQ

VCC UVLO Threshold (V)

5.8 IOUT2 Gain

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Typical Characteristics (continued)

Current Sense Voltage (mV)

IOUT1, IOUT2 (PA)

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Typical Characteristics (continued)

OVPB Pull-up Resisitance (M:)

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7.2 Functional Block Diagram

OPT OSC SYNCIN SYNCOUT

VIN VIN 3.125 V

DEAD OVER FLIP

AGND COMMON CONTROL PGND

CH-1 CONTROL DIR CSB1

HOLD CROSS LOGIC

CH-2 CONTROL DIR

HOLD ;¶,1* LOGIC

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7.3 Feature Description