Product Datasheet

FL1100
PCI Express to 4-Port USB 3.0 Host Controller

Revision 1.10

August 2012

Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

Revision History
Revision Date Comment
0.20 30 Jun 2011 Preliminary release
0.21 10 Jul 2011 Change signal type to LVTTL of following pins: SMIN, ROMSDA, ROMSCL
Update features
Update support ambient temperature
Add Chapter 5 PCI Express Registers
0.50 31 Oct 2011 Update pins:
NC: B16, B39, A47,
AVCC12: A6, B10, B43, B50
Update Appendix A: reference footprint
Update section 4.6: power consumption data
Update Appendix A: update reference footprint from FL1009
Update Appendix C: add description in "long" and "hot" thermal profile recommendation.
1.00 15 Jan 2012 Update section 2.2: add pull up/down to below signals: PREST#, OVCN0-3, ROMSDA,
ROMSCL, ROMPRES.
Update section 3.6.2: Supplement HW LPM description.
Update section 3.2: description of xHCI controller.
Update Appendix A.1: Update POD from Amkor: exposure pad size change
1.10 15 Aug 2012
Update Appendix A.2: Update exposure pad footprint

Product Datasheet 1 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

Table of Contents
1. Introduction ................................................................................................................................................. 7
1.1 Features ..................................................................................................................................... 8
1.2 Applications ............................................................................................................................... 8
1.3 Ordering Information .................................................................................................................. 8
1.4 Top Marking ............................................................................................................................... 9
2. Signal Description ..................................................................................................................................... 10
2.1 Ballout Definition ....................................................................................................................... 11
2.2 Signal Descriptions .................................................................................................................. 12
2.2.1 PCI Express Interface ..................................................................................................... 12
2.2.2 USB Port 0 Interface ....................................................................................................... 12
2.2.3 USB Port 1 Interface ....................................................................................................... 12
2.2.4 USB Port 2 Interface ....................................................................................................... 13
2.2.5 USB Port 3 Interface ....................................................................................................... 13
2.2.6 Miscellaneous Signals .................................................................................................... 13
2.2.7 Power / Ground ............................................................................................................... 14
2.2.8 NC Pins ........................................................................................................................... 14
3. Function Description ................................................................................................................................. 15
3.1 Block Diagram ......................................................................................................................... 15
3.2 xHCI Controller ........................................................................................................................ 15
3.3 Root Hub and Root Ports ........................................................................................................ 16
3.4 USB Transceiver ...................................................................................................................... 16
3.5 PCI Express Transceiver ......................................................................................................... 16
3.6 Power Management ................................................................................................................ 17
3.6.1 USB Power States .......................................................................................................... 17
3.6.2 USB 2.0 Link Power Management (LPM) ....................................................................... 17
3.6.3 PCIe Power States .......................................................................................................... 17
4. Electrical Characteristics ........................................................................................................................... 19
4.1 Operating Conditions ............................................................................................................... 19
4.2 Absolute Maximum Ratings ..................................................................................................... 19
4.3 Power-up Sequence ................................................................................................................ 20
4.4 Power-down Sequence ........................................................................................................... 21
4.5 DC Electrical Specifications ..................................................................................................... 21
4.6 Power Consumption ................................................................................................................ 22
4.7 AC Characteristics ................................................................................................................... 23
4.8 USB Electrical Characteristics ................................................................................................. 23

Product Datasheet 2 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

4.9 PCIe Electrical Characteristics ................................................................................................ 26

5. PCI Express Registers .............................................................................................................................. 28
5.1 Register Types ......................................................................................................................... 28
5.2 PCI Express Configuration Register Map ................................................................................ 28
5.2.1 PCI Express Configuration Register Description ............................................................ 30
5.3 Memory-Mapped I/O Register Map ......................................................................................... 43
5.3.1 Host Controller Capability Registers ............................................................................... 43
5.3.2 Host Controller Operational Registers ............................................................................ 46
5.3.3 Host Controller Runtime Registers ................................................................................. 53

Product Datasheet 3 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

List of Figures
Figure 1-1 FL1100 Top Marking ........................................................................................................................... 9
Figure 2-1 FL1100 Ballout Map (Top view / Transparent View).......................................................................... 11
Figure 3-1 FL1100 block diagram ...................................................................................................................... 15
Figure 4-1 Power-up sequence ......................................................................................................................... 20
Figure 4-2 Power-down Sequence .................................................................................................................... 21

Product Datasheet 4 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

List of Tables
Table 1-1 Ordering Information ............................................................................................................................ 8
Table 2-1 Signal description of PCIe Interface .................................................................................................. 12
Table 2-2 Signal description of USB Port 0 Interface ........................................................................................ 12
Table 2-3 Signal description of USB Port 1 Interface ........................................................................................ 12
Table 2-4 Signal description of USB Port 2 Interface ........................................................................................ 13
Table 2-5 Signal description of USB Port 3 Interface ........................................................................................ 13
Table 2-6 Signal description of miscellaneous signals ...................................................................................... 13
Table 2-7 Power / ground signals ...................................................................................................................... 14
Table 2-8 Internal generate power supplies ...................................................................................................... 14
Table 2-9 No connection pin list......................................................................................................................... 14
Table 3-1 USB 3.0 Power State ......................................................................................................................... 17
Table 3-2 USB Link Power Management (Lx) States ........................................................................................ 17
Table 4-1 Operating Conditions ......................................................................................................................... 19
Table 4-2 Absolute Maximum Ratings ............................................................................................................... 19
Table 4-3 Power-up sequence parameters ....................................................................................................... 20
Table 4-4 Power-down sequence parameters ................................................................................................... 21
Table 4-5 LVTTL I/O DC Characteristic ............................................................................................................. 21
Table 4-6 FL1100 power consumption (preliminary typical corner measurement) ............................................ 22
Table 4-7 FL1100 operating current (preliminary typical corner measurement) ................................................ 22
Table 4-8 FL1100 Maximum operating current (preliminary typical corner measurement) ............................... 22
Table 4-9 Reference clock specification ............................................................................................................ 23
Table 4-10 Power noise specification ................................................................................................................ 23
Table 4-11 Electrical characteristic of SuperSpeed transmitter ......................................................................... 23
Table 4-12 Spread Spectrum Clocking (SSC) parameters ................................................................................ 24
Table 4-13 Electrical characteristics of LFPS .................................................................................................... 24
Table 4-14 Electrical characteristics of SuperSpeed receiver ........................................................................... 24
Table 4-15 Electrical characteristic of USB 2.0 High-speed .............................................................................. 25
Table 4-16 Electrical characteristic of USB 2.0 full-speed/low-speed ............................................................... 25
Table 4-17 Electrical characteristic of PCIe ....................................................................................................... 26
Table 5-1 Register Types ................................................................................................................................... 28
Table 5-2 PCIe Configuration Register Map ...................................................................................................... 28
Table 5-3 Host controller capability registers ..................................................................................................... 43
Table 5-4 Host controller operational registers .................................................................................................. 46
Table 5-5 Host controller runtime registers ........................................................................................................ 53

Product Datasheet 5 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

Product Datasheet 6 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

1. Introduction
The FL1100 is Fresco Logic’s single-chip PCI Express to USB 3.0 host controller. It fully integrates an
Extensible Host Controller Interface (xHCI) engine, a 4-port 5Gbps USB 3.0 transceiver, a PCI Express
endpoint controller and a 5Gbps PCI Express transceiver. FL1100 implements the Universal Serial Bus 3.0
Specification Revision 1.0 and the Extensible Host Controller Interface (xHCI) Specification Revision 1.0, and
complies with the PCI Express Rev 2.1 Specification at 5Gbps data rate, and is backward compatible to the
PCI Local Bus Specification Revision 2.2. FL1100 is compatible for operation with USB 2.0 and USB 1.1
devices.

The FL1100 controller features Fresco Logic’s patented GoXtream™ xHCI Accelerator Engine, which maps the
xHCI standard directly into a set of parallel functional units, providing acceleration of all xHCI operations while
maintaining compatibility with existing software driver models.

With its innovative architecture and high level of integration, FL1100 delivers exceptional performance, while
minimizing total system cost and providing the most straightforward usage model in the industry.

The FL1100 controller is available in the following package:

DRQFN, 116 pin, 9mm 9mm

Product Datasheet 7 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

1.1 Features

Compliant with USB 3.0 Specification Revision 1.0

Compliant with Extensible Host Controller Interface (xHCI) Specification Revision 1.0

4 downstream USB ports support SS/HS/FS/LS data rates (5Gbps/480Mbps/12Mbps/1.5Mbps)

Supports Battery Charging Specification Revision 1.2 for Charging Downstream Ports (CDP)

Supports USB charging via Chinese Telecom Standard YD/T 1591-2009

Single (x1) PCI Express Lane

Supports PCI Express Specification Revision 2.1 at 5GT/s

Supports PCI Express Card Revision 1.0

Supports PCI Bus Power Management Interface Specification Revision 1.2

3.3V/1.2V/1.05V power supply

Supports 12MHz crystal oscillator

Integrated SuperSpeed USB transceiver

Integrated PCI Express transceiver

WHQL certified driver support for Windows 7, Windows Vista and Windows XP

Linux xHCI support under Linux kernel version 2.6.31 and after

Supports UASP (USB Attached SCSI Protocol)

1.2 Applications

Motherboard

Notebook

Add-in card

Express card

DTV

Embedded PC

Any consumer product with PCIe interface

1.3 Ordering Information

Table 1-1 Ordering Information

Part Number Description Status

FL1100-1Q0 Major Revision 1, DRQFN 116-pin 9mm 9mm Production

Product Datasheet 8 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

1.4 Top Marking

Figure 1-1 FL1100 Top Marking

Figure 1-1 illustrates the top marking of FL1100 samples. The part number is composed of two portions:
“FL1100” is the part name, which tells the product family; the “1Q0” denotes the major stepping and the
package type as major revision 1 and DRQFN package respectively.

Product Datasheet 9 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

2. Signal Description
This chapter provides signal mapping and detailed description of each signal of FL1100. The following
notations are the signal type:

LVTTL Digital control signal

DIFF Analog Differential pair

ANA Analog I/O

OD Open Drain I/O

Product Datasheet 10 Fresco Logic CONFIDENTIAL

Product Datasheet

Figure 2-1 shows the ballout map of FL1100 from the top of the package view.

2.1 Ballout Definition

NC A17 A64 DVCC10

NC A18 A63 SSRXM3

DVCC10 B14 B52 AGND10
Figure 2-1 FL1100 Ballout Map (Top view / Transparent View)

AGND33 A19 A62 SSRXP3

AVCC33 B15 B51 AVCC10
AVCC25S A20 A61 SSTXM3
NC B16 B50 AVCC12
AVCC10 A21 A60 SSTXP3
PCIEREXT B17 B49 AVCC25
PCIERXP A22 A59 AVCC33
AGND10 B18 B48 U2DM3
PCIERXM A23 A58 U2DP3
AGND33 B19 B47 AGND33
AVCC25 A24 A57 DVCC10
11

PCIECKP B20 B46 AGND10

PCIECKM A25 A56 SSRXM2
AVCC10 B21 B45 NC
PCIETXP A26 A55 SSRXP2
PCIECAP B22 B44 AVCC10
PCIETXM A27 A54 SSTXM2

PCI Express to 4-port USB 3.0 Host Controller

AGND10 B23 B43 AVCC12
NC A28 A53 SSTXP2
WAKE# B24 B42 AVCC25
CLKREQ# A29 A52 AVCC33
Fresco Logic CONFIDENTIAL

PERST# B25 B41 U2DM2

ROMSDA A30 A51 U2DP2
ROMPRES B26 B40 AGND33
SMIN A31 A50 NC

ROMSCL A32 A49 NC

FL1100
 FL1100
PCI Express to 4-port USB 3.0 Host Controller

2.2 Signal Descriptions

This section contains detailed signal for each interface.

2.2.1 PCI Express Interface

Table 2-1 Signal description of PCIe Interface

Pin Name Ball# Type Dir. Description

WAKE# B24 OD O PCIe wakeup signal, active low
CLKREQ# A29 OD O Indicate when REFCLK is needed for express card, active low
PERST# B25 LVTTL I PCIe reset, active low, internal pull-up
PCIECKP B20 DIFF I PCIe differential clock (+), 100MHz
PCIECKM A25 DIFF I PCIe differential clock (-), 100MHz
PCIEREXT B17 ANA O Connect an external resistor (12kΩ ± 1%) to AGND33
PCIECAP B22 ANA O Connect an external capacitor 100nF to AGND33
PCIERXP A22 DIFF I The PCI Express differential inputs to the PHY (+)
PCIERXM A23 DIFF I The PCI Express differential inputs to the PHY (-)
PCIETXP A26 DIFF O The PCI Express differential outputs from the PHY (+)
PCIETXM A27 DIFF O The PCI Express differential outputs from the PHY (-)

2.2.2 USB Port 0 Interface

Table 2-2 Signal description of USB Port 0 Interface

Pin Name Ball# Type Dir. Description

XSCI A1 ANA I Crystal oscillator input 12MHz
XSCO B1 ANA O Crystal oscillator output 12MHz
U2DP0 B2 DIFF IO USB2.0 differential data (+).
U2DM0 A4 DIFF IO USB2.0 differential data (-).
SSTXP0 B4 DIFF O USB3.0 SuperSpeed differential output (+)
SSTXM0 B5 DIFF O USB3.0 SuperSpeed differential output (-)
SSRXP0 A7 DIFF I USB3.0 SuperSpeed differential input (+)
SSRXM0 A8 DIFF I USB3.0 SuperSpeed differential input (-)
PPWR0 B36 LVTTL O Vbus port power control (optional)
OVCN0 A41 LVTTL I Indicate over current occurs on VBus, active low, internal pull-up (optional)

2.2.3 USB Port 1 Interface

Table 2-3 Signal description of USB Port 1 Interface

Pin Name Ball# Type Dir. Description

U2DP1 B8 DIFF IO USB2.0 differential data (+).
U2DM1 A10 DIFF IO USB2.0 differential data (-).
SSTXP1 A12 DIFF O USB3.0 SuperSpeed differential output (+)
SSTXM1 A13 DIFF O USB3.0 SuperSpeed differential output (-)
SSRXP1 A14 DIFF I USB3.0 SuperSpeed differential input (+)
SSRXM1 A15 DIFF I USB3.0 SuperSpeed differential input (-)

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 FL1100
PCI Express to 4-port USB 3.0 Host Controller

PPWR1 A44 LVTTL O Vbus port power control (optional)

OVCN1 B34 LVTTL I Indicate over current occurs on VBus, active low, internal pull-up (optional)

2.2.4 USB Port 2 Interface

Table 2-4 Signal description of USB Port 2 Interface

Pin Name Ball# Type Dir. Description

U2DP2 A51 DIFF IO USB2.0 differential data (+).
U2DM2 B41 DIFF IO USB2.0 differential data (-).
SSTXP2 A53 DIFF O USB3.0 SuperSpeed differential output (+)
SSTXM2 A54 DIFF O USB3.0 SuperSpeed differential output (-)
SSRXP2 A55 DIFF I USB3.0 SuperSpeed differential input (+)
SSRXM2 A56 DIFF I USB3.0 SuperSpeed differential input (-)
PPWR2 B37 LVTTL O Vbus port power control (optional)
OVCN2 A42 LVTTL I Indicate over current occurs on VBus, active low, internal pull-up (optional)

2.2.5 USB Port 3 Interface

Table 2-5 Signal description of USB Port 3 Interface

Pin Name Ball# Type Dir. Description

U2DP3 A58 DIFF IO USB2.0 differential data (+).
U2DM3 B48 DIFF IO USB2.0 differential data (-).
SSTXP3 A60 DIFF O USB3.0 SuperSpeed differential output (+)
SSTXM3 A61 DIFF O USB3.0 SuperSpeed differential output (-)
SSRXP3 A62 DIFF I USB3.0 SuperSpeed differential input (+)
SSRXM3 A63 DIFF I USB3.0 SuperSpeed differential input (-)
PPWR3 A45 LVTTL O Vbus port power control (optional)
OVCN3 B35 LVTTL I Indicate over current occurs on VBus, active low, internal pull-up (optional)

2.2.6 Miscellaneous Signals

Table 2-6 Signal description of miscellaneous signals

Pin Name Ball# Type Dir. Description

XCKSEL0 A37 LVTTL I XCKSEL[1:0] is a 2-bit signal for selecting reference clock source
00: 12MHz crystal oscillator to XSCI/XSCO (default: internal pull-down)
XCKSEL1 B30 LVTTL I
Other states reserved.
XCK A46 LVTTL I Reference clock input (reserved)
SMIN A31 LVTTL O SMI interrupt output pin, active low, internal pull-up
ROMSDA A30 LVTTL IO External EEPROM interface. I2C data, internal pull-up (optional)
ROMSCL A32 LVTTL O External EEPROM interface. I2C clock, internal pull-up (optional)
ROMPRES B26 LVTTL I External EEPROM interface. ROM present, internal pull-down (optional)
VBus controllable, internal pull-up
PPWRCTL B28 LVTTL I 0: VBus is NOT controlled by FL1100 (connect a 4.7K resistor to GND)
1: VBus is controlled by FL1100 (default)
AUXDET A36 LVTTL I AUX power detection, internal pull-up

Product Datasheet 13 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

Connect a 4.7K resistor to DGND to disable remote wake-up from D3cold.

TESTN A39 LVTTL I Test pin, connect a 4.7K resistor to DVCC33

2.2.7 Power / Ground

Table 2-7 Power / ground signals

Pin Name Ball# Description

AVCC33 B3, B9, B15, A52, A59 Analog 3.3V power
AGND33 A3, A9, A19, B19, A48, B40, B47 Analog 3.3V ground
AVCC10 B6, B12, A21, B21, B44, B51 Analog 1.05V power
AGND10 B7, B13, B18, B23, B46, B52 Analog 1.05V ground
AVCC12 A6, B10, B43, B50 Analog 1.2V power
DVCC33 B27, B32, A43 Digital 3.3V power
DVCC10 B14, A33, A34, B29, A38, B33, B38, A57, A64 Digital 1.05V power
DGND Exposed Pad Digital ground

Table 2-8 Internal generate power supplies

Pin Name Ball# Description

AVCC25S A20 Analog 2.5V power output
AVCC25 A5, A11, A24, B42, B49 (connect to AVCC25S) Analog 2.5V power

2.2.8 NC Pins

Table 2-9 No connection pin list

NC Pin Ball#
A2, A16, A17, A18, A28, A35, A40, A47, A49, A50, B11,B16, B31, B39, B45

Product Datasheet 14 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

3. Function Description
3.1 Block Diagram

Figure 3-1 FL1100 block diagram

3.2 xHCI Controller

The FL1100 from Fresco Logic is a high-performance PCI Express-based xHCI host controller, which supports
all required functions of the xHCI Specification Revision 1.0. The FL1100 controller is highly integrated and
TM
features Fresco Logic’s patented GoXtream xHCI acceleration technology. Dedicated functional units provide
full hardware acceleration of all xHCI functionality, guaranteeing the best possible performance while
minimizing power.

The performance is enhanced by eliminating the inherent latencies and bottlenecks of hardware/software
hand-offs. The power is reduced by eliminating the overhead of the additional processors, components and
circuitry needed for software-based approaches. Additional benefits of this highly-integrated approach are
lower total system cost and a simpler deployment and usage model.

The FL1100 is fully integrated with PCI Express and USB transceivers and supports both USB 3.0 and USB 2.0

Product Datasheet 15 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

devices. The FL1100 features a Gen 2, x1 PCI Express lane and four USB 3.0 downstream ports.

The FL1100 supports the full capabilities of traversing the Scatter/Gather list to complete the DMA functions
called out by the xHCI Specification. The general interfaces described in the xHCI Specification include a Host
Configuration Space, a Memory- mapped IO space and a Host memory space. Chapter 5 contains the details
of these memory spaces within the FL1100 xHCI controller.

FL1100’s GoXtream™ engine furthers performance with an enhanced scheduler which manages simultaneous
data movement across all ports permitting maximum bandwidth utilization up to the limit of the system interface.
The built-in scheduler also protects the priority of Isochronous and Interrupt transfers over other types of traffic.

3.3 Root Hub and Root Ports

The FL1100 implements the Root Hub functionality described in the USB 3.0 Specification. FL1100 supports a
4 port configuration.

The root port provides USB-specified link functionality for SuperSpeed, high-speed, full-speed and low-speed
links. It communicates with the USB transceiver (PHY) to transfer the data onto the link. Each root port has
buffers to support the bandwidth requirements of its link.

Additionally, each port has its own power management and link negotiation capabilities, allowing individual
ports to power down separately. Link management is done in each of the root ports, which can be suspended
or reset by software without affecting overall xHCI controller operation.

3.4 USB Transceiver

FL1100 integrates a 4-port 5Gbps SuperSpeed USB transceiver which is fully compliant with USB 3.0
specification and backward compatible with all USB 2.0 speeds: High-speed, full-speed and low-speed. The
transceiver is equipped with adaptive receiver equalization, which enhances the receiving capability from
signal attenuation due to the channel or crosstalk noise. As to clock generation, the transceiver supports a
12MHz external crystal, and provides the generation of Spread Spectrum Clocking (SSC), as required by the
specification.

3.5 PCI Express Transceiver

FL1100 integrates a 5.0GT/s PCI Express transceiver which is fully compliant with the PCI Express
Specifications Revision 2.0. It is capable of transmitting and receiving data at a rate of 5Gbps.

Product Datasheet 16 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

3.6 Power Management

3.6.1 USB Power States

FL1100 supports all power modes defined in USB 3.0 Specification. Table 3-1 addresses the USB 3.0 power
modes.

Table 3-1 USB 3.0 Power State

Link State Description Characteristic Exit Latency Range

U0 Link active Link operational state N/A
U1 Link idle – fast exit RX and TX circuitry quiesced us
Clock generation circuitry may additionally
U2 Link idle – slower exit us – ms
be quiesced
U3 Link suspend Transceiver power is off ms

FL1100 supports remote wake from USB device.

3.6.2 USB 2.0 Link Power Management (LPM)

FL1100 is compliant with “USB 2.0 Link Power Management Addendum”, and supports both software and
hardware managed LPM L1 power management. Table 3-2 compares the LPM L1 states and Suspend (L2)
states.

Hardware LPM in FL1100 is a function to provide automatic power management of the USB2 link between the
host root port and the first connected device. It achieves link power savings at latencies at least 2 to 3 orders
of magnitude less than can by achieved by a typical host bus driver. Any bus idle that exceeds a
pre-programmed latency threshold will cause the host to initiate the USB2 L1 state. Hardware LPM is
schedule aware meaning the host will auto wake the device on any new transfer request or at periodic intervals
required for interrupt and/or Isochronous endpoints.

Table 3-2 USB Link Power Management (Lx) States

Link State Description Entry handshake Entry/Exit Latency

L0 Link active N/A N/A
Explicitly entered via LPM extended Entry: ~10us
L1 Link sleep
transaction Exit: ~70us to 1ms
Entry: ~3ms
L2 Suspend Implicitly entered via 3ma of link inactivity
Exit: > 30ms

3.6.3 PCIe Power States

Product Datasheet 17 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

FL1100 supports both PCI Power Management (PCIPM) and PCI Express Active State Power Management
(ASPM). The ASPM may be initiated by FL1100 or by system software. FL1100 supports D0, D1, D3hot and
D3cold states as well as ASPM L0s and L1 states.

Product Datasheet 18 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

4. Electrical Characteristics
4.1 Operating Conditions

Table 4-1 Operating Conditions

Symbol Parameters Min. Typ. Max. Unit

DVCC10 Digital core power supply 1.0 1.05 1.1 V
DVCC33 Digital IO power supply 2.97 3.3 3.63 V
AVCC10 Analog 1.0V power supply 1.0 1.05 1.1 V
AVCC12 Analog 1.2V power supply 1.13 1.19 1.25 V
AVCC33 Analog 3.3V power supply 3.15 3.3 3.45 V
TA Operating ambient temperature 0 70 C
TC Operating case temperature (TC = TA + P) 0 105 C

4.2 Absolute Maximum Ratings

Permanent damage of devices may occur if the absolute maximum ratings are exceeded. These are only
stress ratings, and the functional operations should be restricted within the conditions detailed in Table 4-2.
Exposure to the absolute maximum rating conditions may also affect the reliability of the devices. The input and
output negative voltage ratings may be exceeded if the input and output currents are not exceeded.

Table 4-2 Absolute Maximum Ratings

Symbol Description Rating Unit

DVCC10 Digital core power supply -0.5 ~ 1.4 V
DVCC33 Digital IO power supply -0.5 ~ 4.6 V
AVCC10 Analog 1.0V power supply -0.5 ~ 1.4 V
AVCC12 Analog 1.2V power supply -0.5 ~ 1.4 V
AVCC33 Analog 3.3V power supply -0.5 ~ 4.6 V
VIN3 Input voltage of LVTTL IOs -0.5 ~ 4.6 V
IIN DC input current 50 mA
IOUT DC output short circuit current 50 mA
TSTG Storage temperature -65 ~ 150 °C

Product Datasheet 19 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

4.3 Power-up Sequence

FL1100 has 1.05V and 3.3V voltage supplies for analog and digital functionalities respectively and also has 2
resets: PERST# and internal power-on reset. Please follow below power-up sequence including power
supplies, resets, and reference clocks.

1. Assert PERST#
2. All 3.3V including analog and digital supplies are stable
3. AVCC10/AVCC12 stable
4. DVCC10 stable. DVCC10 must NOT be earlier than AVCC10
5. PERST# de-assert after reference clock stable

Figure 4-1 Power-up sequence

Table 4-3 Power-up sequence parameters

Symbol Description Condition Min. Typ. Max. Unit

Time interval of 3.3V stable to
TPON33_A10 1 - - ms
AVCC10 stable
Time interval of AVCC10 stable to DVCC10 must NOT be earlier than
TPONA10_D10 0 ms
DVCC10 stable AVCC10
Time interval of DVCC10 stable to
TPOND10_PRST 100 ms
PERST# de-asserted
Time interval of PCIe reference
TPONCK_PRST clock stable to PERST# 100 us
de-asserted

Product Datasheet 20 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

4.4 Power-down Sequence

Figure 4-2 illustrates the power-down sequence requirement of FL1100. Please follow below power-down
sequence including power supplies, resets, and reference clocks.

1. Assert PERST#
2. Remove 3.3V supply after PERST# is asserted.
3. Remove PCIe reference clock after PERST# is asserted
4. Remove 1.05V and 1.2V supply no sooner than 3.3V supply is removed.

Figure 4-2 Power-down Sequence

Table 4-4 Power-down sequence parameters

Symbol Description Condition Min. Typ. Max. Unit

Time interval of removing 3.3V to 1.05V must not be removed earlier
TPDN33_10 0 ms
removing 1.05V supply. than 3.3V supply removed.

4.5 DC Electrical Specifications

The section defines the electrical specifications of digital signal pins which are defined as LVTTL in Chapter 2.

Table 4-5 LVTTL I/O DC Characteristic

Symbol Description Condition Min. Typ. Max. Unit

VIL Input low voltage 3.3V LVTTL 0.8 V
VIH Input high voltage 3.3V LVTTL 2.0 V
VOL Output low voltage 3.3V LVTTL 0.4 V
VOH Output high voltage 3.3V LVTTL 2.4 V
RPU Internal pull-up resistor 40 75 190 K
RPD Internal pull-down resistor 40 75 190 K
CIN Input capacitance 2.1 pF

Product Datasheet 21 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

4.6 Power Consumption

Table 4-6 FL1100 maximum power consumption

Symbol Condition Power Unit

PIDLE No device connected 300 mW
PIDLE-LP No device connected (low power mode) 80 mW
PUSB2-1P 1 USB 2.0 device connected 390 mW
PUSB3-1P 1 USB 3.0 device connected 450 mW
PUSB2-2P 2 USB 2.0 devices connected 480 mW
PUSB3-2P 2 USB 3.0 devices connected 600 mW
PUSB2-3P 3 USB 2.0 devices connected 570 mW
PUSB3-3P 3 USB 3.0 devices connected 750 mW
PUSB2-4P 4 USB 2.0 devices connected 670 mW
PUSB3-4P 4 USB 3.0 devices connected 920 mW
PU3HUB-4P 4 USB 3.0 Hub connected (maximum condition) 1320 mW
PSLEEP Host controller sleep with remote wake-up support 60 mW

Table 4-7 FL1100 operating current (typical corner measurement)

Current of power lines Total

Condition Unit
Symbol AVCC33 DVCC33 AVCC10 DVCC10 AVCC12 Current
IIDLE No device connected 47 0 43 68 0 158 mA
IIDLE-LP No device connected (low power mode) 3 0 24 13 0 40 mA

IUSB2-1P 1 USB 2.0 device connected 69 0 43 80 0 192 mA

IUSB3-1P 1 USB 3.0 device connected 59 0 80 82 43 264 mA

IUSB2-2P 2 USB 2.0 devices connected 91 0 43 92 0 226 mA
IUSB3-2P 2 USB 3.0 devices connected 72 0 117 97 87 373 mA
IUSB2-3P 3 USB 2.0 devices connected 114 0 43 104 0 261 mA
IUSB3-3P 3 USB 3.0 devices connected 85 0 153 110 131 479 mA
IUSB2-4P 4 USB 2.0 devices connected 136 1 44 116 0 297 mA
IUSB3-4P 4 USB 3.0 devices connected 98 1 188 125 174 586 mA
ISLEEP Sleep with remote wake-up support 3 0 13 13 0 29 mA

Table 4-8 FL1100 Maximum operating current (preliminary typical corner measurement)

Power Description Current Unit

I10VMAX Maximum total current of AVCC10 and DVCC10 400 mA
I12VMAX Maximum total current of AVCC12 200 mA
I33VMAX Maximum total current of AVCC33 and DVCC33 (including 2.5V internal generation) 200 mA

Product Datasheet 22 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

4.7 AC Characteristics
The section defines the requirement of reference clock source and the power supplies.

Table 4-9 Reference clock specification

Symbol Description Condition Min. Type Max. Unit

FXTAL_12 Frequency of 12MHz crystal -30ppm 12 +30ppm MHz
TDUTY Clock duty cycle 40 50 60 %
ESR Crystal ESR 2.4 40 Ω

Table 4-10 Power noise specification

Symbol Description Condition Min. Type Max. Unit

VNOISE33 Power noise on 3.3V supply 1 Hz ~ 100KHz 100 mVpp
VNOISE12 Power noise on 1.2V supply 1 Hz ~ 100KHz 50 mVpp
VNOISE10 Power noise on 1.0V supply 1 Hz ~ 100KHz 50 mVpp

4.8 USB Electrical Characteristics

Table 4-11 Electrical characteristic of SuperSpeed transmitter

Symbol Description Condition Min. Type Max. Unit

UI Unit Interval 199.94 200.00 200.06 ps
Differential peak-to-peak TX 2 * |VTXP – VTXN|, measured at TX
VTX-DIFF-PP 800 1200 mV
voltage swing near-end
Low-power differential 2 * |VTXP – VTXN|, measured at TX
VTX-DIFF-PP_LOW 400 1200 mV
peak-to-peak TX voltage swing near-end
VTX-DE-RATIO TX de-emphasis level 3.0 4.0 dB
RTX-DIFF-DC DC differential impedance 72 120 Ω
CAC-COUPLING AC coupling capacitor 75 200 nF
Including all jitter sources,
TTX-EYE Transmitter eye 0.625 UI
measured at the silicon pad.
Deterministic jitter only assuming
the Dual Dirac distribution,
TTX-DJ-NEAR Near-end TX deterministic jitter 0.205 UI
measured at the silicon pad by
using the CP0 pattern.
Deterministic jitter only assuming
TTX-DJ-FAR Far-end TX deterministic jitter the Dual Dirac distribution, 0.43 UI
measured at TP1
Measured at the silicon pad by
TTX-RJ-FAR Far-end TX random jitter -12 0.23 UI
using the CP1 pattern at 10 BER
Measured at the silicon pad (TJ =
TTX-TJ-FAR Far-end TX total jitter - - 0.66 UI
DJ + RJ)
TX input capacitance for return
CTX-PARASITIC - - - 1.25 pF
loss
Transmitter DC common-mode
RTX-DC - 18 - 30 Ω
impedance

Product Datasheet 23 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

VTX-DC-CM TX DC common-mode voltage - - 0.75 1.2 V

Absolute TX DC common-mode
VTX-DC-CM-U0-U1 voltage between the U0 and U1 - - 0.75 1.2 V
modes
The voltage change allowed during The total amount of voltage
VT-D-R - - 200 mV
the receiver detection change during TX-Detect-RX

Table 4-12 Spread Spectrum Clocking (SSC) parameters

Symbol Description Condition Min. Type Max. Unit

TSSC-MOD-RATE Modulation rate USB transceiver power 30 31.5 33 KHz
TSSC-FREQ-DEVIATION SSC deviation USB PLL power 0 4000 5000 ppm
TSSC-SLEW-RATE SSC slew rate USB transceiver power - - 10 ms/s

Table 4-13 Electrical characteristics of LFPS

Symbol Description Condition Min. Type Max. Unit

TPeriod Period of the LFPS signal - 20 - 100 ns
LFPS AC common-mode
VCM-AC-LFPS - - 0.75 1.2 V
voltage
Differential peak-to-peak LFPS 2 * |VTXP – VTXN|, measured at TX
VTX-DIFF-PP-LFPS 800 - 1200 mV
voltage swing near-end
Low-power differential
2 * |VTXP – VTXN|, measured at TX
VTX-DIFF-PP-LFPS-LP peak-to-peak LFPS voltage 400 - 1200 mV
near-end
swing
Rise/Fall time of the LFPS
TRISE-FALL-2080 - - - 4 ns
signal

Table 4-14 Electrical characteristics of SuperSpeed receiver

Symbol Description Condition Min. Type Max. Unit

UI Unit interval - 199.94 200.00 200.06 ps
Receiver common-mode
RRX-DC - 18 - 30 Ω
impedance
Receiver DC differential
RRX-DIFF-DC - 72 - 120 Ω
impedance
VRX-LFPSDET-DIFF-PP LFPS detect threshold - 100 - 300 mV
Differential RX peak-to-peak
VRX-DIFF-PP-POSTEQ - 30 - - mV
voltage
TRX-TJ Max RX inherent timing error - - - 0.45 UI
Max RX inherent deterministic
TRX-DJ - - - 0.285 UI
timing error
RX input capacitance for return
CRX-PARASITIC - - - 1.1 pF
loss
VRX-AC-CM RX AC common-mode voltage - - - 150 mV
RX AC common-mode voltage
VRX-AC-CM-U0-U1 - - - 200 mV
during the U0-to-U1 transition

Product Datasheet 24 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

Table 4-15 Electrical characteristic of USB 2.0 High-speed

Symbol Description Condition Min. Typ. Max. Unit

Driver characteristic
THSRDRATE High-speed TX data rate - 479.76 - 480.24 Mbps
THSRDRATE High-speed RX data rate - 479.76 - 480.24 Mbps
tHSR High-speed differential rise time - 500 - - ps
tHSF High-speed differential fall time - 500 - - ps
Input level of differential receiver
|VI(DP) – VI(DM)|, measured at the
High-speed differential input
VHSDIFF connection of an application 300 - - mV
sensitivity
circuit.
High-speed data signaling
VHSCM - −50 - 500 mV
common-mode voltage range
High-speed disconnection Disconnection detected 625 - - mV
VHSDSC
detection threshold No disconnection detected - - 525 mV
Output Level
High-speed idle level output
VHSOI - -10 - 10 mV
voltage (Differential)
High-speed low level output
VHSOL - -10 - 10 mV
voltage (Differential)
High-speed high level output
VHSOH - 360 400 440 mV
voltage (Differential)
VCHIRPJ Chirp-J output voltage (Differential) - 700 - 1100 mV
Chirp-K output voltage
VCHIRPK - -900 - -500 mV
(Differential)
IDP/DM Allowable output current of DP/DM The termination is 45 Ω ±10%. 14.55 17.78 21.79 mA
Resistance
Equivalent resistance used for the
RDRV Driver output impedance 40.5 45 49.5 Ω
internal chip
ZHSTERM Differential impedance - 76.5 90 103.5 Ω

Table 4-16 Electrical characteristic of USB 2.0 full-speed/low-speed

Symbol Description Condition Min. Typ. Max. Unit

Full-speed driver characteristic
TFSDRATE Full-speed TX data rate - 11.994 - 12.006 Mbps
TFSRDRATE Full-speed RX data rate - 11.97 - 12.03 Mbps
CL = 50 pF
tFR Rise time 4 - 20 ns
10% ~ 90% of |VOH – VOL|
CL = 50 pF
tFF Fall time 4 - 20 ns
90% ~ 10% of |VOH – VOL|
Differential rise/fall time matching Excluding the first transition from
tFRMA 90 - 110 %
(tFR/tFF) the idle mode
Excluding the first transition from
VCRS Output signal crossover voltage 1.3 - 2.0 V
the idle mode
Low-speed driver characteristic
TLSDRATE Low-speed TX data rate - 1.49925 - 1.50075 Mbps

Product Datasheet 25 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

TLSRDRATE Low-speed RX data rate - 1.49625 - 1.50375 Mbps

CL = 200 pF ~ 600 pF
tLR Rise time 75 - 300 ns
10% ~ 90% of |VOH – VOL|
CL = 200 pF ~ 600 pF
tLF Fall time 75 - 300 ns
90% ~ 10% of |VOH – VOL|
Differential rise/fall time matching Excluding the first transition from
tLRMA 80 - 125 %
(tLR/tLF) the idle mode
Excluding the first transition from
VCRS Output signal crossover voltage 1.3 - 2.0 V
the idle mode
Input level of differential receiver
VDI Differential input sensitivity |VI(DP) - VI(DM)| 0.2 - - V
VCM Differential common-mode voltage - 0.8 - 2.5 V
Equivalent resistance used for the
ZHSDRV Driver output resistance 40.5 45 49.5 Ω
internal chip
Equivalent resistance used for the
RPU1 Pull-up resistor during idle 900 - 1575 Ω
internal chip
Equivalent resistance used for the
RPU2 Driver output resistance 525 - 1515 Ω
internal chip
Equivalent resistance used for the
RPD Driver output resistance 14.25 - 24.8 kΩ
internal chip
Input level of single-ended receiver
VSE Single-ended receiver threshold - 0.8 - 2.0 V
Output level
VOL Low-level output voltage - 0 - 0.3 V
VOH High-level output voltage - 2.8 - 3.6 V

4.9 PCIe Electrical Characteristics

Table 4-17 Electrical characteristic of PCIe

Symbol Description Condition Min. Type Max. Unit

Input level
VRX-DIFF High speed differential input |VRX(DIP) – VRX(DIN)|, measured at
signals the connection of receiver’s near 87.5 - 600 mV
end.
TRX-EYE Receiver eye time opening Minimum eye time at Rx pins to
0.4 - - UI
yield a 10E-12 BER
VIDLE Electrical idle detect threshold IDLE detected - - 87.5 mV
Non IDLE detected 87.5 - mV
VRX-CM-AC RX and AC common-mode voltage Peak voltage - - 150 mV
Output levels
VTX-DIFF High speed differential output |VTX(DOP) – VTX(DON)|, measured at
signal the connection of transmitter’s 400 - 600 mV
near end.
TTX-EYE Transmitter eye time opening Minimum eye time at Rx pins to
0.75 - - UI
yield 10E-12 BER
VTX-IDLE-AC Electrical idle differential peak - - - 20 mV

Product Datasheet 26 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

output voltage
VT-D-R The amount of voltage change The total amount of voltage
- - 600 mV
allowed during receiver detection change during TX-Detect-RX
VTX_CM_AC Transmitter AC common-mode AC RMS value
- - 20 mV
voltage
VTX_DEM TX de-emphasis level -3 - -4 dB
FBEACON Frequency of beacon signaling - 2 - 150 MHz
Resistance
RRX Built-in receiver input impedance - 40 50 60 Ω
RTX Built-in driver output impedance - 40 50 60 Ω
Capacitance
CTX AC coupling capacitor - 75 - 200 nF

Product Datasheet 27 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

5. PCI Express Registers

5.1 Register Types

Table 5-1 Register Types

Register
Description
Attribute
Read-only
RO
Register bits are read-only and cannot be altered by software
Read-write
RW
Register bits are read-write and are permitted to be Set or Cleared by software
Write-1-to-clear status
RW1C Register bits indicate status when read. The status is cleared by writing 1b. Writing 0b
has no effect.
Write-1-toset status
RW1S Register bits indicate status when read. The status is set by writing 1b. Writing 0b has no
effect
Read-only, Sticky
ROS Register bits are read-only and cannot be altered by software. Bits are not be initialized
nor modified by hot reset or functional level reset (FLR)
Read-write, Sticky
RWS Register bits are read-write and are permitted to be Set or Cleared by software. Bits are
not initialized nor modified by hot reset or functional level reset (FLR)
Write-1-to-clear status, Sticky
Register bits indicate status when read. The status is cleared by writing 1b. Writing 0b
RW1CS
has no effect. Bits are not initialized nor modified by hot reset or functional level reset
(FLR)

5.2 PCI Express Configuration Register Map

FL1100 xHCI controller is a PCI-based xHC (extensible Host Controller) which is required to implement a PCI,
Type 0 PCI device header as Table 5-2. FL1100 also implements two Base Address Registers (BAR 0 and BAR
1) to enable 64-bit addressing. These Base Address Registers are used to point to the start of the host
controller’s memory-mapped Input/Output (MMIO) register spaces, as described in section 5.3.

Table 5-2 PCIe Configuration Register Map

Registers
Offset
31 0
Device ID Vendor ID 000h
Status Command 004h
Class Code Revision ID 008h
BIST Header type Latency Timer Cache Line Size 00Ch
Base Address Registers (BAR) 010h

Product Datasheet 28 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

014h
018h
01Ch
020h
024h
Reserved 028h
Subsystem ID Subsystem Vendor ID 02Ch
Reserved 030h
Reserved Capabilities Pointer 034h
Reserved 038h
Max_Lat Min_Gnt Interrupt Pin Interrupt Line 03Ch
Power Management Capability Next Capability Pointer PM Cap ID 40h
PM Data PMCSR_BSE Power Management Control/Status 44h
48h
Reserved
4Ch
MSI Message Control Next Capability Pointer MSI Cap ID 50h
MSI Message Address 54h
MSI Upper Message Address 58h
Reserved MSI Message Data 5Ch
Reserved FLADJ SBRN 60h
64h
Reserved 68h
6Ch
PCI Express Capability Register Next Capability Pointer PCI Express Cap ID 70h
Device Capabilities 74h
Device Status Device Control 78h
Link Capabilities 7Ch
Link Status Link Control 80h
84h
Reserved ^
90h
Device Capabilities 2 94h
Device Status 2 Device Control 2 98h
Link Capability 2 9Ch
Link Status 2 Link Control 2 A0h
A4h
Reserved A8h
ACh
MSI-X Message Control Next Item Pointer MSI-X Cap ID B0h
MSI-X Table Offset and BIR B4h
MSI-X PBA Offset and BIR B8h
BCh
Reserved
^
EEPROM Control F0h
Programmability Offset F4h
Programmability Data F8h

Product Datasheet 29 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

Reserved FCh

5.2.1 PCI Express Configuration Register Description

5.2.1.1 Vendor ID Register

Address Offset: 00h Attribute: RO
Default value: 1B73h Size: 16 bits

Bit Description Attribute

15:0 Vendor ID. A 16-bit value assigned to Fresco Logic Inc: 1B73h. RO

5.2.1.2 Device ID Register

Address Offset: 02h Attribute: RO
Default value: 1100h Size: 16 bits

Bit Description Attribute

15:0 Device ID. A 16-bit value assigned to FL1100: 1100h. RO

5.2.1.3 Command Register

Address Offset: 04h Attribute: RW, RO
Default value: 0000h Size: 16 bits

Bit Description Attribute

8 SERR# Enable RW
6 Parity Error Response RW
2 Bus Master Enable. Default value of this bit is 0b. RO
Other bits Reserved RO

5.2.1.4 Status Register

Address Offset: 06h Attribute: RW1C, RO
Default value: 0010h Size: 16 bits

Bit Description Attribute

RW1C (Read,
15 Detected Parity Error
Write 1 to Clear)
14 Signaled System Error RW1C
13 Received Master Abort RW1C
12 Received Target Abort RW1C
11 Signaled Target Abort RW1C
8 Master Data Parity Error RW1C
4 Capabilities List RO
3 Interrupt Status RO
Other bits Reserved RO

5.2.1.5 Revision ID Register

Address Offset: 08h Attribute: RO
Default value: 00h Size: 8 bits

Product Datasheet 30 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

Bit Description Attribute

7:0 Silicon Revision. FL1100-1Q0 is read 00h RO

5.2.1.6 Class Code Register

Address Offset: 09 Attribute: RO
Default value: 0C 0330h Size: 24 bits

Bit Description Attribute

Base Class Code (BASEC).
23:16 RO
0Ch = Serial Bus controller.
Sub-Class Code (SCC).
15:8 RO
03h = Universal Serial Bus Host Controller.
Programming Interface (PI).
7:0 RO
30h = USB 3.0 Host Controller that conforms to this specification

5.2.1.7 Cache Line Size Register

Address Offset: 0Ch Attribute: RW
Default value: 0h Size: 8 bits

Bit Description Attribute

This field is implemented by PCI Express devices as a read-write field for legacy
7:0 RW
compatibility purposes but not applied to FL1100 functionalities.

5.2.1.8 Latency Timer Register

Address Offset: 0Dh Attribute: RO
Default value: 0h Size: 8 bits

Bit Description Attribute

7:0 Not applied on FL1100. RO

5.2.1.9 Header Type Register

Address Offset: 0Eh Attribute: RO
Default value: 0h Size: 8 bits

Bit Description Attribute

7:0 FL1100 supports type 0 PCI header. RO

5.2.1.10 BIST
Address Offset: 0Fh Attribute: RO
Default value: 0h Size: 8 bits

Bit Description Attribute

7:0 Not applied on FL1100 RO

5.2.1.11 Base Address Register 0

Address Offset: 10h Attribute: RO, RW

Product Datasheet 31 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

Default value: 0000 0004h Size: 32 bits

Bit Description Attribute

31:4 Base address RW
3 Prefetchable RO
Memory Type. This field is read 10b to indicate the memory can be located anywhere
2:1 RO
in 64-bit space
0 Memory space indicator RO

5.2.1.12 Base Address Register 1

Address Offset: 14h Attribute: RW
Default value: 0000 0000h Size: 32 bits

Bit Description Attribute

31:0 Base address of upper 32 bit of the 64 bit memory address. RW

5.2.1.13 Base Address Register 2

Address Offset: 18h Attribute: RO, RW
Default value: 0000 0004h Size: 32 bits
Bit Description Attribute
31:4 Base address RW
3 Prefetchable RO
Memory Type. This field is read 10b to indicate the memory can be located anywhere
2:1 RO
in 64-bit space
0 Memory space indicator RO

5.2.1.14 Base Address Register 3

Address Offset: 1Ch Attribute: RW
Default value: 0000 0000h Size: 32 bits

Bit Description Attribute

31:0 Base address of upper 32 bit of the 64 bit memory address. RW

5.2.1.15 Base Address Register 4

Address Offset: 20h Attribute: RO, RW
Default value: 0000 0004h Size: 32 bits

Bit Description Attribute

31:4 Base address RW
3 Prefetchable RO
Memory Type. This field is read 10b to indicate the memory can be located anywhere
2:1 RO
in 64-bit space
0 Memory space indicator RO

5.2.1.16 Base Address Register 5

Address Offset: 24h Attribute: RW
Default value: 0000 0000h Size: 32 bits

Product Datasheet 32 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

Bit Description Attribute

31:0 Base address of upper 32 bit of the 64 bit memory address. RW

5.2.1.17 Subsystem Vendor ID (SVID)

Address Offset: 2Ch Attribute: RO
Default value: 1B73h Size: 16 bits

Bit Description Attribute

Defines the system manufacturer. This field should be chanced through
15:0 RO
programmability register.

5.2.1.18 Subsystem ID (SSID)

Address Offset: 2Eh Attribute: RO
Default value: 1100h Size: 16 bits

Bit Description Attribute

System Manufacturer defined Device ID. This field should be chanced through
15:0 RO
programmability register.

5.2.1.19 Capability Pointer

Address Offset: 34h Attribute: RO
Default value: 40h Size: 16 bits

Bit Description Attribute

15:0 Offset Pointer to PCIe configuration header. RO

5.2.1.20 Interrupt Line Register

Address Offset: 3Ch Attribute: RO
Default value: 00h Size: 8 bits

Bit Description Attribute

7:0 Interrupt line from FL1100 to issue interrupt to system software. RO

5.2.1.21 Interrupt Pin Register

Address Offset: 3Dh Attribute: RO
Default value: 01h Size: 8 bits

Bit Description Attribute

7:0 This field is read 01 to indicate FL1100 uses INTA. RO

5.2.1.22 Min_Gnt Register

Address Offset: 3Eh Attribute: RO
Default value: 00h Size: 8 bits

Bit Description Attribute

7:0 Not applied on FL1100 RO

Product Datasheet 33 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

5.2.1.23 Max_Lat Register

Address Offset: 3Fh Attribute: RO
Default value: 0000h Size: 8 bits

Bit Description Attribute

7:0 Not applied on FL1100 RO

5.2.1.24 PM Capability Identifier

Address Offset: 40h Attribute: RO
Default value: 01h Size: 8 bits

Bit Description Attribute

Capability ID, this register is read 01h to identify this address is PCI Power
7:0 RO
Management registers

5.2.1.25 Next Capability Pointer

Address Offset: 41h Attribute: RO
Default value: 50h Size: 8 bits

Bit Description Attribute

Next Item Pointer
7:0 RO
Offset to point to the next MSI capability registers.

5.2.1.26 Power Management Capability Register

Address Offset: 42h Attribute: RO
Default value: DBC3h Size: 16 bits

Bit Description Attribute

PME Support
15:11 RO
This field is read 11011b. FL1100 support D0, D1, D3hot and D3cold
D2 Support RO
10
This bit is read 0b to indicate FL1100 doesn’t support D2 state
D1 Support RO
9
This bit is read 1b to indicate FL1100 support D1 state
AUX current RO
8:6
This field is read 111b. FL1100 required 375mA AUX current
5 Device Specific Initialization (DSI) RO
4 Reserved RO
3 PME clock, tied 0 on PCIe device RO
PM Version RO
2:0 This field is read 011b to indicate FL1100 is compliant with PCI Power Management
Interface Specification Revision 1.2

5.2.1.27 Power Management Control/Status Register

Address Offset: 44h Attribute: RO, RWC, RW
Default value: 0000h Size: 16 bits

Product Datasheet 34 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

Bit Description Attribute

RWC (Read,
15 PME_Status
Write to clear)
14:13 Data_Scale, not supported by FL1100, read 00b RO
12:9 Data_Select, not supported by FL1100, read 0000b RO
8 PME# enable RW
7:4 Reserved RO
3 No_Soft_Reset RO
2 Reserved RO
PowerState
00b: D0
1:0 01b: D1 RW
10b: D2
11b: D3hot

5.2.1.28 MSI Capability Identifier

Address Offset: 50h Attribute: RO
Default value: 05h Size: 8 bits

Bit Description Attribute

7:0 Capability ID, this register is read 05h to identify this address is MSI RO

5.2.1.29 Next Capability Pointer

Address Offset: 51h Attribute: RO
Default value: 70h Size: 8 bits

Bit Description Attribute

Next Item Pointer
7:0 RO
Offset to point to the next PCI Express capability registers.

5.2.1.30 MSI Message Control Register

Address Offset: 52h Attribute: RO, RW
Default value: 0086h Size: 16 bits

Bit Description Attribute

15:9 Reserved RO
8 Per-vector masking capable RO
7 64 bit address capable RO
6:4 Multiple Message Enable RW
3:1 Multiple Message Capable RO
0 MSI enable RW

5.2.1.31 MSI Message Address Register

Address Offset: 54h Attribute: RO, RW
Default value: 0000 0000h Size: 32 bits

Product Datasheet 35 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

Bit Description Attribute

Message Address
31:2 RW
System-specified message address
1:0 Reserved RO

5.2.1.32 MSI Message Upper Address Register

Address Offset: 58h Attribute: RW
Default value: 0000 0000h Size: 32 bits

Bit Description Attribute

Message Address
31:0 RW
System-specified message upper address. Optional for 64-bit message address

5.2.1.33 MSI Message Data Register

Address Offset: 5Ch Attribute: RW
Default value: 0000h Size: 16 bits

Bit Description Attribute

Message Data
15:0 RW
System-specified message data.

5.2.1.34 SBRN (Serial Bus Release Number) Register

Address Offset: 60h Attribute: RO
Default value: 30h Size: 8 bits

Bit Description Attribute

Serial Bus Specification Release Number
7:0 30h = Release 3.0, FL1100 is compliance to USB 3.0 specification RO
All other combinations are reserved

5.2.1.35 FLADJ (Frame Length Adjustment) Register

Address Offset: 61h Attribute: RWS
Default value: 20h Size: 8 bits

Bit Description Attribute

7:6 Reserved
Frame Length Timing Value.
Each decimal value change to this register corresponds to 16 high-speed bit times.
The SOF cycle time (number of SOF counter clock periods to generate a SOF
microframe length) is equal to 59488 + value in this field. The default value is decimal
5:0 32 (20h), which gives a SOF cycle time of 60000 (125us). RO
Frame Length
FLADJ value
# HS bit times in decimal
decimal, (heximal)
59488 0 (00h)

Product Datasheet 36 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

59504 1 (01h)
59520 2 (02h)
^ ^
59984 31 (1Fh)
60000 (125us) 32 (20h)
^ ^
60480 62 (3Eh)
60496 63 (3Fh)

5.2.1.36 PCI Express Capability ID

Address Offset: 70h Attribute: RO
Default value: 10h Size: 8 bits

Bit Description Attribute

7:0 Return 10h to indicate this is a PCI Express Capability Structure RO

5.2.1.37 Next Capability Pointer

Address Offset: 71h Attribute: RO
Default value: B0h Size: 8 bits

Bit Description Attribute

Next Item Pointer
7:0 RO
Offset to point to the next MSI-X capability registers.

5.2.1.38 PCI Express Capability Register

Address Offset: 72h Attribute: RO
Default value: 0002h Size: 16 bits

Bit Description Attribute

15:14 Reserved
13:9 Interrupt Message Number RO
Slot Implemented
8 RO
Not applicable on FL1100, return 0.
Device/Port type
7:4 RO
FL1100 returns 0h to indicate a PCIe Express Endpoint
Capability version.
3:0 RO
FL1100 returns 2h to indicate compliant to PCIe Base R2.1

5.2.1.39 Device Capabilities Register

Address Offset: 74h Attribute: RO
Default value: 00288FC2h Size: 32 bits

Bit Description Attribute

31:29 Reserved RO
28 Function Level Reset Capability RO
27:26 Captured Slot Power Limit Scale RO

Product Datasheet 37 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

25:18 Captured Slot Power Limit Value RO

17:16 Reserved RO
15 Role-Based Error Reporting RO
14:12 Reserved RO
11:9 Endpoint L1 Acceptable Latency RO
8:6 Endpoint L0s Acceptable Latency RO
5 Extended Tag Field Supported RO
Phantom Function Supported
4:3 FL1100 returns 00b to advertise no function number bits are used for Phantom RO
Functions
Max Payload Size Supported
2:0 RO
FL1100 returns 010b to advertise 512 bytes max payload

5.2.1.40 Device Control Register

Address Offset: 78h Attribute: RW, RO
Default value: 2810h Size: 16 bits

Bit Description Attribute

15 Reserved RO
14:12 Max Read Request Size RW
11 Enable No Snoop RW
10 AUX Power PM Enable RW
9 Phantom Functions Enable RW
8 Extended Tag Field Enable RW
7:5 Max Payload Size RW
4 Enable Relaxed Ordering RW
3 Unsupported Request Reporting Enable RW
2 Fatal Error Reporting Enable RW
1 Non-Fatal Error Reporting Enable RW
0 Correctable Error Reporting Enable RW

5.2.1.41 Device Status Register

Address Offset: 7Ah Attribute: RO, RW1C
Default value: 0010h Size: 16 bits

Bit Description Attribute

15:6 Reserved RO
5 Transaction Pending RO
4 AUX Power Detected RO
RW1C (Read,
3 Unsupported Request Detected
Write 1 to Clear)
2 Fatal Error Detected RW1C
1 Non-Fatal Error Detected RW1C
0 Correctable Error Detected RW1C

Product Datasheet 38 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

5.2.1.42 Link Capabilities Register

Address Offset: 7Ch Attribute: RO
Default value: 0003 FC12h Size: 32 bits

Bit Description Attribute

31:24 Port Number RO
23:22 Reserved RO
21 Link Bandwidth Notification Capability RO
20 Data Link Layer Link Active Reporting Capable RO
19 Surprise Down Error Reporting Capable RO
18 Clock Power Management RO
L1 Exit Latency
17:15 RO
L1 Exit Latency of FL1100 is more than 64us (111b)
L0s Exit latency
14:12 RO
L0s Exit Latency of FL1100 is more than 4us (111b)
ASPM Support
11:10 RO
FL1100 returns 11b to support ASPM L0s and L1
Max Link Width
9:4 RO
FL1100 returns 000001b to indicate supporting of x1 link
Supported Link Speeds
3:0 RO
FL1100 returns 0010b to indicate supporting of 5GT/s and 2.5GT/s

5.2.1.43 Link Control Register

Address Offset: 80h Attribute: RW, RO
Default value: 0040h Size: 16 bits

Bit Description Attribute

15:12 Reserved RO
11 Link Autonomous Bandwidth Interrupt Enable RW
10 Link Bandwidth Management Interrupt Enable RW
9 Hardware Autonomous Width Disable RW
8 Enable clock power management RW
7 Extended Synch RW
6 Common Clock Configuration RW
5 Retrain Link RW
4 Link Disable RW
3 Read Completion Boundary (RCB) RW
2 Reserved
ASPM Control
00b: disable
1:0 01b: L0s enable RW
10b: L1 enable
11b: L0s and L1 enable

5.2.1.44 Link Status Register

Address Offset: 82h Attribute: RO, RW1C

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 FL1100
PCI Express to 4-port USB 3.0 Host Controller

Default value: 1012h Size: 16 bits

Bit Description Attribute

15 Link Autonomous Bandwidth Status RW1C
14 Link Bandwidth Management Status RW1C
13 Data Link Layer Link Active RO
12 Set Clock Configuration RO
11 Link Training RO
10 Reserved RO
Negotiated Link Width
9:4 RO
000001b: x1
Current Link Speed
3:0 0001: 2.5GT/s RO
0010: 5GT/s

5.2.1.45 Device Capabilities 2 Register

Address Offset: 94h Attribute: RO
Default value: 0000 0010h Size: 32 bits

Bit Description Attribute

31:24 Reserved RO
23:22 Max End-End TLP Prefixes RO
21 End-End TLP Prefix Supported RO
20 Extended Fmt Field Supported RO
13:12 TPH Completer Supported RO
11 LTR Mechanism Supported RO
10 No RO-enabled PR-PR Passing RO
9 128-bit CAS Completer Supported RO
8 64-bit AtomicOp Completer Supported RO
7 32-bit AtomicOp Completer Supported RO
6 AtomicOp Routing Supported RO
5 ARI Forwarding Supported RO
4 Completion Timeout Disable Supported RO
3:0 Completion Timeout Ranges Supported RO

5.2.1.46 Device Control 2 Register

Address Offset: 98h Attribute: RO
Default value: 0000h Size: 16 bits

Bit Description Attribute

15 End-End TLK Prefix Blocking RO
14:11 Reserved RO
10 LTR Mechanism Enable RO
9 IDO Completion Enable RO
8 IDO Request Enable RO
7 AtomicOp Egress Blocking RO

Product Datasheet 40 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

6 AtomicOp Requester Enable RO

5 ARI Forwarding Enable RO
4 Completion Timeout Disable RO
3:0 Completion Timeout Value RO

5.2.1.47 Device Status 2 Register

Address Offset: 9Ah Attribute: RO
Default value: 0000h Size: 16 bits

Bit Description Attribute

15:0 Reserved RO

5.2.1.48 Link Capabilities 2 Register

Address Offset: 9Ch Attribute: RO
Default value: 0000 0000h Size: 32 bits

Bit Description Attribute

31:0 Reserved RO

5.2.1.49 Link Control 2 Register

Address Offset: A0h Attribute: RWS, RO
Default value: 0002h Size: 16 bits

Bit Description Attribute

15:13 Reserved RO
12 Compliance De-emphasis RWS
11 Compliance SOS RWS
10 Enter Modified Compliance RWS
9:7 Transmit Margin RWS
6 Selectable De-emphasis RO
5 Hardware Autonomous Speed Disable RWS
4 Enter Compliance RWS
Target Link Speed
3:0 RWS
This field is read 0010b to indicate FL1100 support 5.0GT/s Target Link Speed

5.2.1.50 Link Status 2 Register

Address Offset: A2h Attribute: RO
Default value: 0001h Size: 16 bits

Bit Description Attribute

15:1 Reserved RO
Current De-emphasis Level
0 RO
1b: -3.5 dB; 0b:-6 dB

5.2.1.51 MSI-X Capability ID

Address Offset: B0h Attribute: RO
Default value: 11h Size: 8 bits

Product Datasheet 41 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

Bit Description Attribute

7:0 Return 11h to indicate this is a MSI-X Capability Structure RO

5.2.1.52 Next Capability Pointer

Address Offset: B1h Attribute: RO
Default value: 00h Size: 8 bits

Bit Description Attribute

Next Item Pointer
7:0 RO
Return 00h for the final item in the list.

5.2.1.53 MSI-X Message Control Register

Address Offset: B2h Attribute: RW, RO
Default value: 0007h Size: 16 bits

Bit Description Attribute

15 MSI-X Enable RW
14 Function Mask RW
13:11 Reserved RO
10:0 MSI-X Table Size RO

5.2.1.54 MSI-X Table Offset and BIR Register

Address Offset: B4h Attribute: RO
Default value: 0000 0002h Size: 32 bits

Bit Description Attribute

31:3 Table Offset RO
2:0 Table BIR (Bar Indicator Register) RO

5.2.1.55 MSI-X PBA Offset and BIR Register

Address Offset: B8h Attribute: RO
Default value: 0000 0004h Size: 32 bits

Bit Description Attribute

31:3 PBA (Pending Bit Array) Offset RO
2:0 PBA BIR RO

Product Datasheet 42 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

5.3 Memory-Mapped I/O Register Map

5.3.1 Host Controller Capability Registers

These registers specify the limits and capabilities of the FL1100 USB 3.0 host controller implementation. All
Capability Registers are Read-Only (RO). Please refer to section 5.3 of xHCI Specification Rev 1.0 for detail.

Table 5-3 Host controller capability registers

Base offset Base offset Default

Register Symbol Register Name
start end Value
CAPLENGTH Capability Registers Length 00h 00h 80h
HCIVERSION Host Controller Interface Version Number 02h 03h 0100h
HCSPARAMS1 Structural Parameters 1 04h 07h 08000820h
HCSPARAMS2 Structural Parameters 2 08h 0Bh 84000054h
HCSPARAMS3 Structural Parameters 3 0Ch 0Fh 00040001h
HCCPARAMS Capability Parameters 10h 13h 200073A1h
DBOFF Doorbell Offset 14h 17h 00003000h
RTSOFF Runtime Register Space Offset 18h 1Bh 00002000h

5.3.1.1 CAPLENGTH - Capability Registers Length

Address Offset: 0h Attribute: RO
Default value: 80h Size: 8 bits

Bit Description Attribute

7:0 Capability Registers Length (CAPLENGTH) RO

This register is modified and maintained by BIOS

5.3.1.2 HCIVERSION - Host Controller Interface Version Number

Address Offset: 02h Attribute: RO
Default value: 0100h Size: 16 bits

Bit Description Attribute

Host Controller Interface Version Number (HCIVERSION)
15:0 RO
FL1100 is compliant with xHCI version 1.0

This register is modified and maintained by BIOS

5.3.1.3 HCSPARAMS1 - Structural Parameters 1

Address Offset: 04h Attribute: RO
Default value: 0800 0820h Size: 32 bits

Bit Description Attribute

31:24 Number of ports (MaxPorts) RO
23:19 Reserved RO
18:8 Number of interrupters (MaxIntrs) RO

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 FL1100
PCI Express to 4-port USB 3.0 Host Controller

7:0 Number of device slots (MaxSlots) RO

This register is modified and maintained by BIOS

5.3.1.4 HCSPARAMS2 - Structural Parameters 2

Address Offset: 08h Attribute: RO
Default value: 8400 0054h Size: 32 bits

Bit Description Attribute

31:27 Max Scratchpad Buffers (MaxScratchpadBufs) RO
26 Scratchpad Restore (SPR) RO
25:8 Reserved RO
7:4 Event Ring Segment Table Max (ERSTMax) RO
3:0 Isochronous Scheduling Threshold (IST) RO

This register is modified and maintained by BIOS

5.3.1.5 HCSPARAMS3 - Structural Parameters 3

Address Offset: 0Ch Attribute: RO
Default value: 0004 0001h Size: 32 bits

Bit Description Attribute

31:16 U2 Device Exit Latency (U2DEL).
Worst case latency to transition a root hub Port Link Stat (PLS) from U2 to U0.
RO
Applies to all root hub ports.
FL1100 has default set as Less than 4us.
15:8 Reserved RO
7:0 U1 Device Exit Latency (U1DEL)
Worst case latency to transition a root hub Port Link Stat (PLS) from U2 to U0.
RO
Applies to all root hub ports.
FL1100 has default set as Less than 1us.

This register is modified and maintained by BIOS

5.3.1.6 HCCPARAMS - Capability Parameters

Address Offset: 10h Attribute: RO
Default value: 2000 73A1h Size: 32 bits

Bit Description Attribute

31:16 xHCI Extended Capabilities Pointer (xECP) RO
15:12 Maximum Primary Stream Array Size (MaxPSASize) RO
11:8 Reserved RO
7 No Secondary SID Support (NSS) RO
6 Latency Tolerance Messaging Capability (LTC) RO
5 Light HC Reset Capability (LHRC) RO
4 Port Indicators (PIND) RO
3 Port Power Control (PPC) RO

Product Datasheet 44 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

2 Context Size (CSZ) RO

1 BW Negotiation Capability (BNC) RO
0 64-bit Addressing Capability (AC64) RO

This register is modified and maintained by BIOS

5.3.1.7 DBOFF - Doorbell Offset

Address Offset: 14h Attribute: RO
Default value: 0000 3000h Size: 32 bits

Bit Description Attribute

31:2 Doorbell Array Offset (DBAO) RO
1:0 Reserved RO

5.3.1.8 RTSOFF - Runtime Register Space Offset

Address Offset: 18 Attribute: RO
Default value: 0000 2000h Size: 32 bits

Bit Description Attribute

31:5 Runtime Register Space Offset (RTRSO) RO
4:0 Reserved RO

Product Datasheet 45 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

5.3.2 Host Controller Operational Registers

This section defines the xHCI Operational Registers. All registers are multiples of 32 bits in length. Unless
otherwise stated, all registers should be accessed as a 32-bit width on reads using an appropriate software
mask, if needed. A software read/modify/write mechanism should be invoked for partial writes. Please refer to
section 5.4 of xHCI Specification Rev 1.0 for detail.

Table 5-4 Host controller operational registers

Base offset Base offset Default

Register Symbol Register Name
start end Value
USBCMD USB Command 80h 83h 00000000h
USBSTS USB Status 84h 87h 00000001h
PAGESIZE Page Size 88h 8Bh 00000001h
DNCTRL Device Notification Control 94h 97h 00000000h
CRCR_LO Command Ring Low 98h 9Bh 00000000h
CRCR_HI Command Ring High 9Ch 9Fh 00000000h
DCBAAP_LO Device Context Base Address Array Pointer Low B0h B3h 00000000h
DCBAAP_HI Device Context Base Address Array Pointer High B4h B7h 00000000h
CONFIG Configure B8h BBh 00000000h
PORTSC0(USB2) Port 0 Status and Control USB2 480h 483h 000002A0h
Port 0 Power Management Status and Control
PORTPMSC0(USB2) 484h 487h 00000000h
USB2
PORTSC1(USB2) Port 1 Status and Control USB2 490h 493h 000002A0h
Port 1 Power Management Status and Control
PORTPMSC1(USB2) 494h 497h 00000000h
USB2
PORTSC2(USB2) Port 2 Status and Control USB2 4A0h 4A3h 000002A0h
Port 2 Power Management Status and Control
PORTPMSC2(USB2) 4A4h 4A7h 00000000h
USB2
PORTSC3(USB2) Port 3 Status and Control USB2 4B0h 4B3h 000002A0h
Port 3 Power Management Status and Control
PORTPMSC3(USB2) 4B4h 4B7h 00000000h
USB2
PORTSC0(USB3) Port 0 Status and Control USB3 4C0h 4C3h 000002A0h
PORTPMSC0(USB3) Port 0 Power Management Status and Control 4C4h 4C7h 00000000h
PORTLI0 Port 0 Link Info 4C8h 4CBh 00000000h
PORTSC1(USB3) Port 1 Status and Control USB3 4D0h 4D3h 000002A0h
PORTPMSC1(USB3) Port 1 Power Management Status and Control 4D4h 4D7h 00000000h
PORTLI1 Port 1 Link Info 4D8h 4DBh 00000000h
PORTSC2(USB3) Port 2 Status and Control USB3 4E0h 4E3h 000002A0h
PORTPMSC2(USB3) Port 2 Power Management Status and Control 4E4h 4E7h 00000000h
PORTLI2 Port 2 Link Info 4E8h 4EBh 00000000h
PORTSC3(USB3) Port 3 Status and Control USB3 4F0h 4F3h 000002A0h
PORTPMSC3(USB3) Port 3 Power Management Status and Control 4F4h 4F7h 00000000h
PORTLI3 Port 3 Link Info 4F8h 4FBh 00000000h

Product Datasheet 46 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

5.3.2.1 USBCMD - USB Command

Address Offset: 80h Attribute: RW, RO
Default value: 0000 0000h Size: 32 bits

Bit Description Attribute

31:12 Reserved RO
11 Enable U3 MFINDEX Stop (EU3S) RW
10 Enable Wrap Event (EWE) RW
9 Controller Restore State (CRS) RW
8 Controller Save State (CSS) RW
7 Light Host Controller Reset (LHCRST) RW
6:4 Reserved RO
3 Host System Error Enable (HSEE) RW
2 Interrupter Enable (INTE) RW
1 Host Controller Reset (HCRST) RW
0 Run/Stop (RS) RW

5.3.2.2 USBSTS - USB Status

Address Offset: 84h Attribute: RO, RW1C
Default value: 0000 0001h Size: 32 bits

Bit Description Attribute

31:13 Reserved RO
12 Host Controller Error (HCE) RO
This bit is not preset in HC, this is deviation from xHCI 1.0 spec.
11 Controller Not Ready (CNR) RO
This is deviation from xHCI 1.0 spec.
10 Save/Restore Error (SRE) RW1C
9 Restore State Status (RSS) RO
8 Save State Status (SSS) RO
7:5 Reserved RO
4 Port Change Detect (PCD) RW1C
3 Event Interrupt (EINT) RW1C
2 Host System Error (HSE) RW1C
1 Reserved RO
0 HCHalted (HCH) RO

5.3.2.3 PAGESIZE - Page Size

Address Offset: 88h Attribute: RO
Default value: 0000 0001h Size: 32 bits

Bit Description Attribute

31:16 Reserved RO
15:0 Page Size (PAGESIZE) RO

Product Datasheet 47 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

5.3.2.4 DNCTRL - Device Notification Control

Address Offset: 94h Attribute: RO, RW
Default value: 0000 0000h Size: 32 bits

Bit Description Attribute

31:16 Reserved RO
15:0 Notification Enable (N0_N15) RW

5.3.2.5 CRCR_LO - Command Ring Low

Address Offset: 98h Attribute: RO, RW, RW1S
Default value: 0000 0000h Size: 32 bits

Bit Description Attribute

31:6 Command Ring Pointer (CRP) RW
5:4 Reserved RO
3 Command Ring Running (CRR) RO
2 Command Abort (CA) RW1S
1 Command Stop (CS) RW1S
0 Ring Cycle State (RCS) RW

5.3.2.6 CRCR_HI - Command Ring High

Address Offset: 9Ch Attribute: RW
Default value: 0000 0000h Size: 32 bits

Bit Description Attribute

31:0 Command Ring Pointer (CRP) RW

5.3.2.7 DCBAAP_LO - Device Context Base Address Array Pointer Low

Address Offset: B0h Attribute: RO, RW
Default value: 0000 0000h Size: 32 bits

Bit Description Attribute

31:6 Device Context Base Address Array Pointer (DCBAAP) RW
5:0 Reserved RO

5.3.2.8 DCBAAP_HI - Device Context Base Address Array Pointer High

Address Offset: B4h Attribute: RW
Default value: 0000 0000h Size: 32 bits

Bit Description Attribute

31:0 Device Context Base Address Array Pointer (DCBAAP) RW

5.3.2.9 CONFIG – Configure

Address Offset: B8h Attribute: RO, RW
Default value: 0000 0000h Size: 32 bits

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 FL1100
PCI Express to 4-port USB 3.0 Host Controller

Bit Description Attribute

31:8 Reserved RO
7:0 Max Device Slots Enabled (MaxSlotsEn) RW

5.3.2.10 PORTSCx(USB2) - Port 0~3 Status and Control (USB2)

Port 0: 480h
Port 1: 490h RO, RW, RWS, RW1S,
Address Offset: Attribute:
Port 2: 4A0h RW1CS, ROS,
Port 3: 4B0h
Default value: 0000 02A0h Size: 32 bits

Bit Description Attribute

31 Warm Port Reset (WPR) RW1S
30 Device Removable (DR) RO
29:28 Reserved RO
27 Wake on Over-current Enable (WOE) RWS
26 Wake on Disconnect Enable (WDE) RWS
25 Wake on Connect Enable (WCE) RWS
24 Cold Attach Status (CAS) RO
23 Port Config Error Change (CEC) RW1CS
22 Port Link State Change (PLC) RW1CS
21 Port Reset Change (PRC) RW1CS
20 Over-current Change (OCC) RW1CS
19 Warm Port Reset Change (WRC) RW1CS
18 Port Enabled Disabled Change (PEC) RW1CS
17 Connect Status Change (CSC) RW1CS
16 Port Link State Write Strobe (LWS) RW
15:14 Port Indicator Control (PIC) RWS
13:10 Port Speed (Port_Speed) ROS
This field identifies the speed of the attached USB Device. This field is only relevant if
a device is attached (CCS = ‘1’) in all other cases this field shall indicate Undefined
Speed.
1: Full-speed
2: Low-speed
3: High-speed
3: SuperSpeed
9 Port Power (PP) RWS
8:5 Port Link State (PLS) RWS
Read Value Meaning
0: Link is in the U0 State
1: Link is in the U1 State
2: Link is in the U2 State
3: Link is in the U3 State (Device Suspend)
4: Link is in the Disabled State
5: Link is in the RxDetect State
6: Link is in the Inactive State
7: Link is in the Polling State

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 FL1100
PCI Express to 4-port USB 3.0 Host Controller

8: Link is in the Recovery State

9: Link is in the Hot Reset State
10: Link is in the Compliance Mode State
11: Link is in the Test Mode State
12:14 Reserved
15 Link is in the Resume State
4 Port Reset (PR) RW1S
1: Port Reset signaling is asserted.
0: Port is not in Reset.
When software writes a ‘1’ to this bit (from a ‘0’) the bus reset sequence is initiated
3 Over-current Active (OCA) ROS
This port currently has an over-current condition. ‘0’ = This port does not have an
over-current condition. This bit shall automatically transition from a ‘1’ to a ‘0’ when
the over-current condition is removed.
2 Reserved RO
1 Port Enabled/Disabled (PED) RW1CS
Ports may only be enabled by the xHC. Software cannot enable a port by writing a ‘1’
to this flag. A port may be disabled by software writing a ‘1’ to this flag.
0 Current Connect Status (CCS) ROS
1: Device is present on port.
0: No device is present.

5.3.2.11 PORTPMSCx(USB2) - Port 0~3 Power Management Status and Control (USB2)
Port 0: 484h
Port 1: 494h
Address Offset: Attribute: RO, RWS, ROS
Port 2: 4A4h
Port 3: 4B4h
Default value: 0000 0000h Size: 32 bits

Bit Description Attribute

31:28 Port Test Control (PTC) RWS
27:17 Reserved RO
16 Hardware LPM Enable (HLE) RO
15:8 L1 Device Slot (L1DS) RWS
7:4 Host Initiated Resume Duration (HIRD) RWS
3 Remote Wake Enable (RWE) RWS
2:0 L1 Status (L1S) ROS

5.3.2.12 PORTSCx(USB3) - Port 0~3 Status and Control (USB3)

Port 0: 4C0h
Port 1: 4D0h RO, RWS, RW, RW1S,
Address Offset: Attribute:
Port 2: 4E0h RW1CS, ROS
Port 3: 4F0h
Default value: 0000 02A0h Size: 32 bits

Bit Description Attribute

31 Warm Port Reset (WPR) RW1S

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 FL1100
PCI Express to 4-port USB 3.0 Host Controller

30 Device Removable (DR) RO

29:28 Reserved RO
27 Wake on Over-current Enable (WOE) RWS
26 Wake on Disconnect Enable (WDE) RWS
25 Wake on Connect Enable (WCE) RWS
24 Cold Attach Status (CAS) RO
23 Port Config Error Change (CEC) RW1CS
22 Port Link State Change (PLC) RW1CS
21 Port Reset Change (PRC) RW1CS
20 Over-current Change (OCC) RW1CS
19 Warm Port Reset Change (WRC) RW1CS
18 Port Enabled Disabled Change (PEC) RW1CS
17 Connect Status Change (CSC) RW1CS
16 Port Link State Write Strobe (LWS) RW
15:14 Port Indicator Control (PIC) RWS
13:10 Port Speed (Port_Speed) ROS
This field identifies the speed of the attached USB Device. This field is only relevant if
a device is attached (CCS = ‘1’) in all other cases this field shall indicate Undefined
Speed.
1: Full-speed
2: Low-speed
3: High-speed
3: SuperSpeed
9 Port Power (PP) RWS
8:5 Port Link State (PLS) RWS
Read Value Meaning
0: Link is in the U0 State
1: Link is in the U1 State
2: Link is in the U2 State
3: Link is in the U3 State (Device Suspend)
4: Link is in the Disabled State
5: Link is in the RxDetect State
6: Link is in the Inactive State
7: Link is in the Polling State
8: Link is in the Recovery State
9: Link is in the Hot Reset State
10: Link is in the Compliance Mode State
11: Link is in the Test Mode State
12:14 Reserved
15 Link is in the Resume State
4 Port Reset (PR) RW1S
1: Port Reset signaling is asserted.
0: Port is not in Reset.
When software writes a ‘1’ to this bit (from a ‘0’) the bus reset sequence is initiated
3 Over-current Active (OCA) ROS
This port currently has an over-current condition. ‘0’ = This port does not have an
over-current condition. This bit shall automatically transition from a ‘1’ to a ‘0’ when

Product Datasheet 51 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

the over-current condition is removed.

2 Reserved RO
1 Port Enabled/Disabled (PED) RW1CS
Ports may only be enabled by the xHC. Software cannot enable a port by writing a ‘1’
to this flag. A port may be disabled by software writing a ‘1’ to this flag.
0 Current Connect Status (CCS) ROS
1: Device is present on port.
0: No device is present.

5.3.2.13 PORTPMSCx(USB3) - Port 0-3 Power Management Status and Control (USB3)
Port 0: 4C4h
Port 1: 4D4h
Address Offset: Attribute: RO, RWS, RW
Port 2: 4E4h
Port 3: 4F4h
Default value: 0000 0000h Size: 32 bits

Bit Description Attribute

31:17 Reserved RO
16 Force Link PM Accept (FLA) RW
15:8 U2 Timeout (U2TO) RWS
7:0 U1 Timeout (U1TO) RWS

5.3.2.14 PORTLIx - Port 0~3 Link Info (USB3)

Port 0: 4C8h
Port 1: 4D8h
Address Offset: Attribute: RO
Port 2: 4E8h
Port 3: 4F8h
Default value: 0000 0000h Size: 32 bits

Bit Description Attribute

31:16 Reserved RO
15:0 Link Error Count (LEC) RO

Product Datasheet 52 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

5.3.3 Host Controller Runtime Registers

This section defines the FL1100 xHCI Runtime Register space. All Runtime registers are multiples of 32 bits in
length. Unless otherwise stated, all registers should be accessed with Dword references on reads, using an
appropriate software mask if needed. A software read/modify/write mechanism should be invoked for partial
writes. Software should write registers containing a Qword address field using only Qword references. Please
refer to Section 5.5 of xHCI Specification Rev 1.0 for detail.

Table 5-5 Host controller runtime registers

Base offset Base offset Default

Register Symbol Register Name
start end Value
MFINDEX Microframe Index 2000 2003 00000000h
IMAN1 Interrupter 1 Management 2020 2023 00000000h
IMOD1 Interrupter 1 Moderation 2024 2027 00000FA0h
ERSTSZ1 Event Ring 1 Segment Table Size 2028 202B 00000000h
ERSTBA_LO1 Event Ring 1 Segment Table Base Address Low 2030 2033 00000000h
ERSTBA_HI1 Event Ring 1 Segment Table Base Address High 2034 2037 00000000h
ERDP_LO1 Event Ring 1 Dequeue Pointer Low 2038 203B 00000000h
ERDP_HI1 Event Ring 1 Dequeue Pointer High 203C 203F 00000000h
IMAN2 Interrupter 2 Management 2040 2043 00000000h
IMOD2 Interrupter 2 Moderation 2044 2047 00000FA0h
ERSTSZ2 Event Ring 2 Segment Table Size 2048 204B 00000000h
ERSTBA_LO2 Event Ring 2 Segment Table Base Address Low 2050 2053 00000000h
ERSTBA_HI2 Event Ring 2 Segment Table Base Address High 2054 2057 00000000h
ERDP_LO2 Event Ring 2 Dequeue Pointer Low 2058 205B 00000000h
ERDP_HI2 Event Ring 2 Dequeue Pointer High 205C 205F 00000000h
IMAN3 Interrupter 3 Management 2060 2063 00000000h
IMOD3 Interrupter 3 Moderation 2064 2067 00000FA0h
ERSTSZ3 Event Ring 3 Segment Table Size 2068 206B 00000000h
ERSTBA_LO3 Event Ring 3 Segment Table Base Address Low 2070 2073 00000000h
ERSTBA_HI3 Event Ring 3 Segment Table Base Address High 2074 2077 00000000h
ERDP_LO3 Event Ring 3 Dequeue Pointer Low 2078 207B 00000000h
ERDP_HI3 Event Ring 3 Dequeue Pointer High 207C 207F 00000000h
IMAN4 Interrupter 4 Management 2080 2083 00000000h
IMOD4 Interrupter 4 Moderation 2084 2087 00000FA0h
ERSTSZ4 Event Ring 4 Segment Table Size 2088 208B 00000000h
ERSTBA_LO4 Event Ring 4 Segment Table Base Address Low 2090 2093 00000000h
ERSTBA_HI4 Event Ring 4 Segment Table Base Address High 2094 2097 00000000h
ERDP_LO4 Event Ring 4 Dequeue Pointer Low 2098 209B 00000000h
ERDP_HI4 Event Ring 4 Dequeue Pointer High 209C 209F 00000000h
IMAN5 Interrupter 5 Management 20A0 20A3 00000000h
IMOD5 Interrupter 5 Moderation 20A4 20A7 00000FA0h
ERSTSZ5 Event Ring 5 Segment Table Size 20A8 20AB 00000000h
ERSTBA_LO5 Event Ring 5 Segment Table Base Address Low 20B0 20B3 00000000h

Product Datasheet 53 Fresco Logic CONFIDENTIAL

 FL1100
PCI Express to 4-port USB 3.0 Host Controller

ERSTBA_HI5 Event Ring 5 Segment Table Base Address High 20B4 20B7 00000000h
ERDP_LO5 Event Ring 5 Dequeue Pointer Low 20B8 20BB 00000000h
ERDP_HI5 Event Ring 5 Dequeue Pointer High 20BC 20BF 00000000h
IMAN6 Interrupter 6 Management 20C0 20C3 00000000h
IMOD6 Interrupter 6 Moderation 20C4 20C7 00000FA0h
ERSTSZ6 Event Ring 6 Segment Table Size 20C8 20CB 00000000h
ERSTBA_LO6 Event Ring 6 Segment Table Base Address Low 20D0 20D3 00000000h
ERSTBA_HI6 Event Ring 6 Segment Table Base Address High 20D4 20D7 00000000h
ERDP_LO6 Event Ring 6 Dequeue Pointer Low 20D8 20DB 00000000h
ERDP_HI6 Event Ring 6 Dequeue Pointer High 20DC 20DF 00000000h
IMAN7 Interrupter 7 Management 20E0 20E3 00000000h
IMOD7 Interrupter 7 Moderation 20E4 20E7 00000FA0h
ERSTSZ7 Event Ring 7 Segment Table Size 20E8 20EB 00000000h
ERSTBA_LO7 Event Ring 7 Segment Table Base Address Low 20F0 20F3 00000000h
ERSTBA_HI7 Event Ring 7 Segment Table Base Address High 20F4 20F7 00000000h
ERDP_LO7 Event Ring 7 Dequeue Pointer Low 20F8 20FB 00000000h
ERDP_HI7 Event Ring 7 Dequeue Pointer High 20FC 20FF 00000000h
IMAN8 Interrupter 8 Management 2100 2103 00000000h
IMOD8 Interrupter 8 Moderation 2104 2107 00000FA0h
ERSTSZ8 Event Ring 8 Segment Table Size 2108 210B 00000000h
ERSTBA_LO8 Event Ring 8 Segment Table Base Address Low 2110 2113 00000000h
ERSTBA_HI8 Event Ring 8 Segment Table Base Address High 2114 2117 00000000h
ERDP_LO8 Event Ring 8 Dequeue Pointer Low 2118 211B 00000000h
ERDP_HI8 Event Ring 8 Dequeue Pointer High 211C 211F 00000000h
3000, ..., 3003, ...,
DOORBELL1, ... 32 Door Bell 1, ..., 32 00000000h
307C 307F

5.3.3.1 MFINDEX - Microframe Index

Address Offset: 2000h Attribute: RO
Default value: 0000 0000h Size: 32 bits

Bit Description Attribute

31:14 Reserved RO
13:0 Microframe Index (MI) RO

5.3.3.2 IMANx - Interrupter x Management

There are 8 IMAN registers: x = 1, 2, 3, ^, 8.

x=1, 2020h-2023h
x=2, 2040h-2043h
Address Offset: x=3, 2060h-2063h Attribute: RO, RW, RW1C
^
x=8, 2100h-2103h
Default value: 0000 0000h Size: 32 bits

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Bit Description Attribute

31:2 Reserved RO
1 Interrupt Enable (IE) RW
0 Interrupt Pending (Interrupt Pending) RW1C

5.3.3.3 IMODx - Interrupter x Moderation

There are 8 IMOD registers: x = 1, 2, 3, ^, 8.

x=1, 2024h-2027h
x=2, 2044h-2047h
Address Offset: x=3, 2064h-2067h Attribute: RW
^
x=8, 2104h-2107h
Default value: 0000 0FA0h Size: 32 bits

Bit Description Attribute

31:16 Interrupt Moderation Counter (IMODC) RW
15:0 Interrupt Moderation Interval (IMODI) RW

5.3.3.4 ERSTSZx - Event Ring Segment Table Size x

There are 8 ERSTSZ registers: x = 1, 2, 3, ^, 8.

x=1, 2028h-202Bh
x=2, 2048h-204Bh
Address Offset: x=3, 2068h-206Bh Attribute: RW, RO
^
x=8, 2108h-210Bh
Default value: 00000000h Size: 32 bits

Bit Description Attribute

31:16 Reserved RO
15:0 Event Ring Segment Table Size (ERSTS) RW

5.3.3.5 ERSTBA_LOx - Event Ring Segment Table Base Address Low x

There are 8 ERSTBA_LO registers: x = 1, 2, 3, ^, 8.

x=1, 2030h-2033h
x=2, 2050h-2053h
Address Offset: x=3, 2070h-2073h Attribute: RW, RO
^
x=8, 2110h-2113h
Default value: 0000 0000h Size: 32 bits

Bit Description Attribute

31:6 Event Ring Segment Table Base Address Register (ERSTBA_LO) RW
5:0 Reserved RO

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5.3.3.6 ERSTBA_HIx - Event Ring Segment Table Base Address High x

There are 8 ERSTBA_HI registers: x = 1, 2, 3, ^, 8.

x=1, 2034h-2037h
x=2, 2054h-2057h
Address Offset: x=3, 2074h-2077h Attribute: RW
^
x=8, 2114h-2117h
Default value: 0000 0000h Size: 32 bits

Bit Description Attribute

31:0 Event Ring Segment Table Base Address (ERSTBA_HI) RW

5.3.3.7 ERDP_LOx - Event Ring Dequeue Pointer Low x

There are 8 ERDP_LO registers: x = 1, 2, 3, ^, 8.

x=1, 2038h-203Bh
x=2, 2058h-205Bh
Address Offset: x=3, 2078h-207Bh Attribute: RW, RW1C
^
x=8, 2118h-211Bh
Default value: 0000 0000h Size: 32 bits

Bit Description Attribute

31:4 Event Ring Dequeue Pointer (ERDP) RW
3 Event Handler Busy (EHB) RW1C
2:0 Dequeue ERST Segment Index (DESI) RW

5.3.3.8 ERDP_HIx - Event Ring Dequeue Pointer High x

There are 8 ERDP_HI registers: x = 1, 2, 3, ^, 8.

x=1, 203Ch-203Fh
x=2, 205Ch-205Fh
Address Offset: x=3, 207Ch-207Fh Attribute: RW
^
x=8, 211Ch-211Fh
Default value: 0000 0000h Size: 32 bits

Bit Description Attribute

31:0 Event Ring Dequeue Pointer (ERDP) RW

5.3.3.9 DOORBELLx - Door Bell Registers x

There are 32 DOORBELL registers: x = 1, 2, 3,^, 32

x=1, 3000h-3003h
Address Offset: x=2, 3004h-3007h Attribute: RW, RO
x=3, 3008h-300Bh

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^
x=32, 307Ch-307Fh
Default value: 0000 0000h Size: 32 bits

Bit Description Attribute

31:16 DB Stream ID (DBSID) RW
15:8 Reserved RO
7:0 DB Target (DBT) RW

Door Bell registers are an array of 64 registers, with 0 to 32 being used by the XHC and the rest being
reserved.

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Appendix A Mechanical
A.1 Package Outline
Please refer to the last page of this document.

A.2 Reference of Amkor PCB footprint

Figure 3

Refer to Figure 3, according to supplier Amkor’s recommendation; the land width (X) for both inner and outer
rows is needed. Based on history of single row QFN, a lead width (X) of 0.280mm was chosen for 0.500mm
pitch. Outer row land pattern dimension Z1Max is calculated using standard IPC methodology and expressed
in terms of nominal body size dimension:

Z1Max = DMin + 2 J T + C L2 + F 2 + P 2
CL
DMin = BODYSIZE −
2
Z1Max = BODYSIZE + 0.340mm

For G1Min and Z2Max values, a minimum clearance of 0.200 mm between inner and outer leads must be
maintained. For a 0.280 mm lead width and 0.650 mm row pitch, a spacing of 0.130 mm between the inner and
outer row leads must be maintained (i.e. 1/2 (G1Min - Z2Max) ≥ 0.13 mm). The nominal distance between
package leads is 0.250 mm. Thus the extra 0.120 mm space for toe and heel fillets must be partitioned
between the inner and outer leads. Because the toe fillet is more important to solder joint reliability, a design
rule of JT ≥ 2 JH is used (i.e. JT = 0.080 mm, JH = 0.040 mm). This results in the following:

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G1Max = BODYSIZE – 0.880 mm

Z2Max = BODYSIZE – 1.140 mm

For G2Min dimension, the heel fillet is limited to conserve space for inner row vias between the leads and the
thermal pad. A value similar to the toe fillet is chosen, JH = 0.080 mm. This results in the following:

G2Min = BODYSIZE − 2.260 mm

The individual lead dimensions derived from these values are:

Outer row leads: 0.280 x 0.610 mm

Inner row Lead: 0.280 x 0.560 mm

Figure 4 shows the land pattern in graphical format.

Figure 4 Land pattern of PCB for 0.5mm pitch DRQFN

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For some case, we can fine tune pad length for enough CLL value in layout. Here is a PCB pad footprint that
use on Fresco Logic’s ECB for reference as Figure 5.

1.37

1.12

Figure 5 PCB footprint of DRQFN

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Appendix B Moisture Sensitive Level

FL1100 is a MOISTURE SENSITIVE DEVICE and should meet LEVEL 3 requirements as following:

1. Calculated shelf life in sealed bag: 12 months at < 40 and < 90% RH.
2. After bag opened, devices that will be subjected to reflow solder or other high temperature process must
be:
a. Mounted within 168 hours of factory conditions ≦ 30 / 60% RH.
b. Stored at < 10% RH.
3. Reflow condition: Please refer to IPC / JEDEC J-STD-020.
4. Devices required baking, before mounting if:
a. Humidity indicator card is > 20% RH when read at 23 +/-5 , or
b. 2.a or 2.b is not met.
5. If baking is required, devices may be baked for 12 hours at 125+/-5 .

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Appendix C SMT Thermal Profile

Thermal Profile on Fresco Logic’s standard EVB add-in card.

The soldering and void control in QFN package:

Quad Flat No Leads (QFN) package designs got more and more popular in electronic industry nowadays. The
most challenges are in soldering and voiding control besides a number of benefits including (1) small size, such
as a near die-sized footprint, thin profile, and light weight; (2) easy PCB trace routing due to the use of
perimeter I/O pads; (3) reduced lead inductance; (4) easy PCB trace routing; and (5) good thermal and
electrical performance due to the adoption of exposed copper die-pad technology. There are some attentions
providing when using QFN package in design and SMT process to improve soldering and reduce voids.
1. QFN IC should by well packing due to it’s a MSL 3 moisture sensitive component as defined by JTD-020
standard. The cleanness and roughness of pad of QFN will impact soldering.
2. Before SMT, bare PCB baking by 120 +/- 5˚C will help.
3. PCB design:
3.1 Signal pad should use NSMD (Non Solder Mask Defined), die paddle should use SMD (Solder Mask
Defined)
3.2 Pad of PCB could be larger than pad of QFN, but limit is equal to.
3.3 Pad of die paddle should match the dimension.
4. Stencil opening:

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4.1 Stencil thickness often use 0.1/ 0.12/ 0.13 mm for pitch 0.5 mm.
4.2 Signal pad & die paddle of stencil opening should match the dimensions.
4.3 Die paddle of stencil opening should be web shape to force a similar volume of solder paste to be
deposited on all contacts for the QFN package. This is to prevent a stand-off situation where different
solder paste heights on the Die Paddle and the Signal Pad contacts causes failure of some or all of
the Signal Pad joints to form correctly.
5. Depends on PCB size, trace layout & component numbers and package type to fine tune SMT thermal
profile. And long hot SMT thermal profile will help improving soldering and reducing void issue.
5.1 Long: P2 (Solder Paste Dry area) should around 90 Sec, better > 90 Sec. refer to below
diagram.
5.2 Hot: P3 area should > 220°C around 60 Sec, better > 60 Sec. Peak temp ≥ 243°C
5.3 Use thermal pad to measure temperature on “IC surface” to get temperature profile. If use measure on
“bare PCB”, there are at least 5~10 lower compared with actual product board while with all
components.
5.4 Use Nitrogen process can improve SMT yield if available.

6. Solder cream (paste) type: high activity type will better.

7. Usage and storage of solder cream:
7.1 It should be well storage in 0~10˚C with well sealed.
7.2 Return to room temp should place 4 hrs before using.
7.3 When sealed is opened, the environment should controlled under 20~27˚C, 40~80%RH, within 1 hr.
Then should return to 0~10˚C.
7.4 Stir solder cream at least 5 minutes.
8. All vias must be fully tented, especially those in the die paddle area and those close to the Signal Pad
contacts.
9. Bow and warp spec of PCB should be careful defined.
10. Recommendations for QA engineering:
10.1 In-coming Inspection should pay special attention to the Bow and Warp characteristics of PCBs
using this package;
10.2 Normal 2D X-Ray inspection will detect alignment issues between the QFN package and the PCB
and can detect solder bridges easily and reliably. This technique will not adequately pick up solder

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deficiencies or improper wetting of solder pads. To find these types of defect, micro-sectioning of the
solder joints is the usual preferred analytical method.

10.3 During the first few months of introduction of this package type, frequent sampling and destructive
testing are strongly recommended to ensure good solder joints are being formed across normal
variations in the manufacturing process. This is of particular significance for the solder joints at the
corners of the package. Dependent upon facilities available, micro-sectioning along the center-lines of
both Signal Pad contacts is preferred, but a lower-cost solution is to break the package from the PCB
and visually inspect the joints with a microscope. This technique will pick up extreme failures, so
occasional micro-sectioning is still recommended.

Please refer to Fresco Logic’s “DRQFN package application reference” for more information.

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Legal Disclaimer
Information in this document is provided in connection with Fresco Logic, Inc. products. No
license, express or implied, by estoppels or otherwise, to any intellectual property rights is granted
by this document. Except as provided in Fresco Logic’s terms and conditions of sale for such
products, Fresco Logic assumes no liability whatsoever, and Fresco Logic disclaims any express or
implied warranty, relating to sale and/or use of Fresco Logic products, including liability or
warranties relating to fitness for a particular purpose, merchantability, or infringement of any
patent, copyright or other intellectual property right.

This document provides technical information for the user. Fresco Logic, Inc. reserves the right to
modify the information in this document as necessary. The customer should make sure that they
have the most recent datasheet version. Fresco Logic, Inc. holds no responsibility for any errors
that may appear in this document. Customers should take appropriate action to ensure their use of
the products does not infringe upon any patents. Fresco Logic, Inc. respects valid patent right of
third parties and does not infringe upon or assist others to infringe upon such rights.

All information contained herein is subject to change without notice.

Product Datasheet 65 Fresco Logic CONFIDENTIAL