Company Confidential 1

Company Confidential 2
Outline

Company Confidential 3
Company Confidential 4
Semiconductor Devices

https://www.toolingu.com/definition-460350-34802-diode.html

Company Confidential 5
Integrated Circuits ICs

Integrated Circuits Ics

Digital ICs Analog Ics Mixed Signal Ics

Microprocessors Sensors Data acquisition

DSPs Power management Clock/timing
Micro controllers Amplifiers

Contains Contains Contains

Logic Gates Amplification A/D converter

Flip-Flops Active filtering D/A converter
Multiplexers Demodulation Digital potentiometers
Mixing

Company Confidential 6
Logic Gate

Logic Gate

RTL-NPN_NOR Gate DTL-NAND Gate TTL NAND Gate

Company Confidential 7
Flip-Flops

Flip-Flops Circuits

Company Confidential 8
Amplifier

Amplifier Circuits

Company Confidential 9
Company Confidential 10
Introduction: ITRS MOSFETs

Company Confidential 11
Transistor Evolution: Overview

Company Confidential 12
Transistor Evolution: Overview

Company Confidential 13
Classical Transistor: Technology Scaling

Typical Scaling of MOSFET by a factor of S

Classical Transistor: Technology Scaling

Y Y

Sufficient with 1-D Electric Profile Required 2-D Electric Profile Consideration

 Short Channel Device-complicated by high electric fields ?

Classical Transistor: Technology Scaling

I3 I4

I1
I2
I6
I5

I1 – Substhreshold leakage
I2 – Reverse bias Jucntion leakage
I1, I5, I6 –Off State Leakage
I3 – Oxide Tunneling Current I2, I3 –Both ON & Off State Leakage
I4 – Hot Carrier Injection leakage
I5 – Gate Induce Drain Leakage I4 –Can occur in Off State, but typically
I6 – Punchthrough Current during Transistor Bias States in Transition
Classical Transistor: Technology Scaling

Company Confidential 17
Classical Transistor: Technology Scaling

Company Confidential 18
Classical Transistor: Technology Scaling

Company Confidential 19
Classical Transistor: Technology Scaling

Company Confidential 20
Classical Transistor: Technology Scaling

Company Confidential 21
Classical Transistor: Technology Scaling

Company Confidential 22
Classical Transistor: Technology Scaling

Company Confidential 23
Classical Transistor: Technology Scaling

Company Confidential 24
Classical Transistor: Technology Scaling

Company Confidential 25
Transistor Evolution

Company Confidential 26
Transistor Evolution: FDSOI

Company Confidential 27
Transistor Evolution: FDSOI

Company Confidential 28
Transistor Evolution: FinFET

Company Confidential 29
Transistor Evolution: FinFET

Company Confidential 30
Transistor Evolution: FinFET

Company Confidential 31
Company Confidential 32
Resistor

Resistor

Well Resistor N+/P+ Resistor Poly Resistor Metal Resistor

Characteristic Characteristic Characteristic Characteristic

-Good for large -Parasitic capacitance to -Good general resistor -The smallest Sheet
resistance substrate with low parasitic Resistance
-Large parasitic -Voltage dependent -Used for fuzzes and -Watch out for the current
-Voltage Dependent -Chip strain from mounting laser trimming limit.
-Could for Pinched -> Piezoresistance effect - X-FAB has 1kOhm/□ &
Resistor 6.7kOhm/□
- Typical N-Well
Resistor

- Consume large area on chip (compare to MOSFET & Capacitor)

- Large run to run variation (20% - 25% accuracy)
- Variable with temperature & voltage
- Generate Thermal noise
- Avoid if you can –at sensitive noise circuit. (transistor (in triode), switched-
capacitor circuits)
- Mainly use –Feedback networks, IC Filter, Reference Generators, A/D
Converter & Compensation Circuits.

Company Confidential 33
Resistor

Company Confidential 34
Well Resistor

Company Confidential 35
N+/P+ Resistor

Company Confidential 36
Poly Resistor

Company Confidential 37
Metal Resistor

Company Confidential 38
Company Confidential 39
 Capacitor

Capacitor

P-N Junction MOSFET Gate PIP MIM Metal Fringe

Characteristic Characteristic Characteristic Characteristic Characteristic

-By diffusion into Well -Very high capacitance -Relatively high -Good Matching -Good Linearity
-High Capacitance -Low Frequency Capacitance -Good Linearity -Low Capacitive density
-High Density -High Voltage Coefficient -Low frequency – -Smallest parasitic -Exploit 3rd dimension-
-Frequency sensitivity depletion layer capacitance don’t need extra
characteristic – -Poor Linearity -Better matching -Best at high processing steps.
restricted by depletion -Problem with Gate - Good linearity (but frequency -High Temperature
layer. Leakage MIM is better) -High Temperature Coefficient.
Coefficient

* Trench Capacitor, Poly-Diffusion Capacitor

Key parameter for Capacitor

- High Capacitance per area
- Withstand a given Voltage
- Be independent on the applied Voltage (Linearity)
- Match well with partner
- Low Temperature Coefficient

Company Confidential 40
Capacitor

Company Confidential 41
P-N Junction Capacitor

Company Confidential 42
MOSFER Gate Capacitor

Company Confidential 43
PIP Capacitor

Company Confidential 44
MIM Capacitor

MPL
MTP

VTP
VPL
CM5 MPL
MTP
M5 M5
VTP
V4 VPL V4
CM4 MPL MPL
MTP
M4 M4 M4 M4
VTP VPL
V3 V3 VPL V3 V3
CM3 CM2
MTP
Single MIM/MIMH M3 M3 M3 M3 M3 M3 M3 M3
V2 VTP V2 V2 V2
V2 V2 V2 V2
CM2 CM2 CM2 CM2 CM2
M2 M2 M2 M2 M2 M2 M2 M2 M2

V1 V1 V1 V1 V1 V1 V1 V1 V1

M1 M1 M1 M1 M1 M1 M1 M1 M1

M3 + METTHIN M2 + MTP M3 + MTP M4 + MTP M5 + MTP M3 + METTHK M3 + METTHK M4 + METTHK M5 + METTHK

XP018 only XC018, XP018 & XT018 Valid for all X*018 Valid for all X*018 Valid for all X*018 *XT018 only (after XT018A Q1'15 CR) XP018 only XP018 only XP018 only
*also known as
*XF60277, XF60595 & *also known as MM23/MIMH23
MM23/MIMH23: see DW
XF60874* - DW XF60051*
XF56517* for example

MPL
MTP

VTP VPL
MPL
MTP
M5 M5

VTP V4 VPL V4
MTP
M4 M4 M4 M4
VTP V3 V3 V3 V3
CM3 CM3 CM3 CM3 CM3
MTP
Double MIM/MIMH M3 M3 M3 M3 M3 M3
V2 V2 V2 V2 V2
V2 VTP
CM2 CM2 CM2 CM2 CM2
Not available
M2 for Not available
M2 for M2 M2 M2 M2 M2

3 metal
V1 layers 3 metal
V1 layers V1 V1 V1 V1 V1

M1 M1 M1 M1 M1 M1 M1

M3 + METTHIN M2 + MTP M3 + MTP M4 + MTP M5 + MTP M4 + METTHK M5 + METTHK

XP018 only XC018, XP018 & XT018 Valid for all X*018 Valid for all X*018 Valid for all X*018 XP018 only XP018 only
*METTHIN is to indicate the top
layer is intermidiate metal, not a
layer itself!

MPL
MTP

VTP VPL
MTP
M5 M5
VTP V4 V4
CM4 CM4 CM4
MTP
M4 M4 M4
V3 V3 V3
VTP
CM3 CM3 CM3
MTP
Triple MIM/MIMH M3 M3 M3 M3 M3
V2 V2 V2
V2 VTP V2
CM2 CM2 CM2
Not available
M2 for Not available
M2 for Not available
M2 for M2 M2 M2

3 metal
V1 layers 3 metalV1layers 4 metalV1layers V1 V1 V1

M1 M1 M1 M1 M1 M1

M3 + METTHIN M2 + MTP M3 + MTP M4 + MTP M5 + MTP M5 + METTHK

XP018 only XC018, XP018 & XT018 Valid for all X*018 Valid for all X*018 Valid for all X*018 XP018 only
*METTHIN is to indicate the top
layer is intermidiate metal, not a
layer itself!

Company Confidential 45
Metal Fringe Capacitor

Company Confidential 46
Poly-Diffusion Capacitor

Company Confidential 47
Trench Capacitor

Company Confidential 48
Company Confidential 49
Diode

Diode

P-N Junction Schottky Diode

P-N Junction Diode Schottky Diode

Avalanche Diode
Zener Diode
Tunnel Diode
Photo Diode
Protection Diode
Veractor Diode

Diode Characteristics
- Essentially acts as a one way switch controlled by voltage (Active Devices)
- Schottky Diode
: Metal to Semiconductor Contact
: Base on majority carrier –High Speed and reduce capacitance
> Has a much higher current density than an ordinary PN Junction
> Low Voltage drop (~0.15-0.4V) as compare no normal PN Diode (~0.6V)
> Suitable for Power Supply –less power is wasted & less heat to dissipated
: Faster switching speed than typical diode-High frequency applications

Company Confidential 50
PN Junction Diode

Company Confidential 51
Schottky Diode

Company Confidential 52
Company Confidential 53
Memory Classification

Semiconductor Memories

Read Only Memory Read / Write Memory

Non-Volatile Volatile Non-Volatile

Memory Memory Memory

1965 1971 1972 1969 1978 1988

PROM DRAM SRAM EEPROM Flash

Mask
Programed

Fujio Masuoka

NVRAM
NVM NVM

> The idea of integrating electronic circuits into a single device was born when the German physicist and engineer Werner Jacobi (de) developed and
patented the first known integrated transistor amplifier in 1949.
• Jack Kilby recorded his initial ideas concerning the integrated circuit in July 1958, successfully demonstrating the first working integrated example on
12 September 1958.
> The idea of using a floating gate (FG) device to obtain a nonvolatile memory device was suggested for the first time in 1967 by Kahng D and Sze SM at
Bell Labs
54
Memory Classification

Overview of emerging nonvolatile memory technologies, Jagan Singh Meena, Simon Min Sze, Umesh Chand and Tseung-Yuen Tseng*

55
Memory –Current Status

• Conventional MRAM – Commercially produced, in sizes upto 64 MB

• STT-MRAM - Prototype phase, size 2Mb or less. It is expected to reach Gbit

density

• FeRAM - produced in line widths of 350 nm at Fujitsu and 130 nm at Texas

Instruments. Texas Instruments has incorporated this memory in one family of its
microcontrollers

• Phase Change Memory – Samsung has presented 20nm 1.8V 8Gb PRAM,
Micron announced availability for mobile devices, which is the first PRAM solution in
volume production

• CBRAM/PMC – Developed by Arizona State University, has been licensed to

several companies. Adesto Technologies is commercially producing 1Mb chips

• ReRAM – Experimental phase; Panasonic has released an evaluation kit.

• Nano-RAM (NRAM) – It is a proprietary computer memory technology from
the company Nantero. Second generation of NRAM is currently in production.
Testing has been performed in space shuttles, and the technology has already been
licensed for U.S. government use.

• Millipede - Experimental stage; being worked upon by IBM.

Major obstacles for the new development is due to heavy investments(including specially designed fabs). However, once the conventional technologies
reach the limits of scalability, these new technologies will be utilized far more widely.
56
NVM Application

Various NVM applications in the electronics industry by market size in 2010.

Lu CY: International Symposium on Non-volatile Memory: the Technology Driver of the Electronics Industry. Volume 2. 1st edition. Singapore: World
Scientific; 2012.
57
Memory Performance

58
Company Confidential 59
Process Flow For XH035

Deep Well
CAPPOLY

LOCOS
SPACER

Well & Vt Adjust

Source Drain

GATE
SALICIDE

LDD Implant

BEOL

Company Confidential 60
Company Confidential 61
Semiconductor Devices

Company Confidential 62
Semiconductor Devices Structure

Current-in Current-out

Interconnect Structure

Company Confidential 63
Semiconductor Devices Structure

CMOS Structure

Company Confidential 64
Semiconductor Manufacturing Processes

Company Confidential 65
Semiconductor Manufacturing Processes

Wafer
Preparation Design

Thin Films Furnace

Photo-
lithography

Ion
Etch
Implantation

Cleaning Planarization

Test &
Assembly

> Semiconductor Manufacturing processes that not applicable in XFAB Sarawak

Company Confidential 66
Front-End Processes

Wafer
Design
Preparation

Thin Films Furnace

Photo-
lithography

Ion
Etch
Implantation

Cleaning Planarization

Test &
Assembly

Company Confidential 67
Photolithography

Wafer
Design
Preparation

Thin Films Furnace

Photo-
lithography

Ion
Etch
Implantation

Cleaning Planarization

Test &
Assembly

Company Confidential 68
Photoresist Coating Processes

photoresist
field oxide

p- epi

p+ substrate

Photoresists
Negative Photoresist *
Positive Photoresist *
Other Ancillary Materials (Liquids)
Edge Bead Removers *
Anti-Reflective Coatings *
Adhesion Promoters/Primers (HMDS) *
Rinsers/Thinners/Corrosion Inhibitors *
Contrast Enhancement Materials *
Developers
TMAH *
Specialty Developers *
Inert Gases
Ar
N2

Company Confidential 69
Exposure Processes

photoresist
field oxide

p- epi

p+ substrate

Expose
Kr + F2 (gas) *
Inert Gases
N2

Company Confidential 70
Ion Implantation

Wafer
Design
Preparation

Thin Films Furnace

Photo-
lithography

Ion
Etch
Implantation

Cleaning Planarization

Test &
Assembly

Company Confidential 71
Ion Implantation

phosphorus
junction (-) ions photoresist mask
depth

f ield oxide
n-w ell p- epi
p-channel transistor
p+ substrate

Process Conditions Gases

Flow Rate: 5 sccm Ar
Pressure: 10-5 Torr AsH3
Accelerating Voltage: 5 to 200 keV B11F3 *
He
N2
PH3
SiH4
SiF4
GeH4

Company Confidential 72
Etch

Wafer
Design
Preparation

Thin Films Furnace

Photo-
lithography

Ion
Etch
Implantation

Cleaning Planarization

Test &
Assembly

Company Confidential 73
Conductor Etch

source-drain areas Cluster Tool Etch

gate linew idth
Configuration Chambers
gate oxide
Wafers Transfer
n-w ell p-w ell Chamber
p-channel transistor n-channel transistor
p+ substrate Loadlock

Chemical Reactions
Silicon Etch: Si + 4 HBr  SiBr4 + 2 H2
RIE Chamber Gas Inlet
Aluminum Etch: Al + 2 Cl2  AlCl4

Polysilicon Etches Aluminum Etches Wafer

Transfer
HBr * BCl3 * Chamber
C2F6 Cl2 RF Power
SF6 * Diluents
NF3 * Ar
O2 He
N2
Exhaust

Company Confidential 74
 Dielectric Etch

Contact locations Cluster Tool Etch

Configuration Chambers

Wafers Transfer
Chamber
n-w ell p-w ell
p-channel transistor n-channel transistor Loadlock
p+ substrate

Chemical Reactions RIE Chamber Gas Inlet

Oxide Etch: SiO2 + C2F6  SiF4 + CO2 + CF4 + 2 CO
Wafer
Transfer
Plasma Dielectric Etches Diluents Chamber
CHF3 * CO2 Ar RF Power
CF4 O2 He
C2F6 SF6 N2
C3F8 SiF4
CO * Exhaust

Company Confidential 75
Cleaning

Wafer
Design
Preparation

Thin Films Furnace

Photo-
lithography

Ion
Etch
Implantation

Cleaning Planarization

Test &
Assembly

Company Confidential 76
 Critical Cleaning

Contact locations

n-w ell p-w ell

p-channel transistor n-channel transistor
p+ substrate

Process Conditions
1 2 3 4 5
Temperature: Piranha Strip is 180 degrees C.
1 Organics 2 Oxides 3 Particles 4 Metals 5 Dry
H2SO4 + HF + NH4OH + HCl + H2O or IPA +
H2O2 H2O H2O2 + H2O H2O2 + H2O N2
H2O Rinse H2O Rinse H2O Rinse H2O Rinse

RCA Clean Nitride Strip Dry Strip Solvent Cleans

SC1 Clean (H2O + NH4OH + H2O2) * H3PO4 * N2O NMP
* SC2 Clean (H2O + HCl + H2O2) * Oxide Strip O2 Proprietary Amines (liquid)
Piranha Strip HF + H2O * CF4 + O2 Dry Cleans
* H2SO4 + H2O2 * O3 HF
O2 Plasma
Alcohol + O3

Company Confidential 77
Thin Films

Wafer
Design
Preparation

Thin Films Furnace

Photo-
lithography

Ion
Etch
Implantation

Cleaning Planarization

Test &
Assembly

Company Confidential 78
Chemical Vapor Deposition (CVD) Dielectric

insulator layer 2 Metering Inert Mixing

Metal 1 Pump Gas
TEOS
Source

Vaporizer
n-w ell p-w ell Direct
p-channel transistor n-channel transistor Liquid Process Gas
p+ substrate Injection

LPCVD Gas Inlet

Chamber
Chemical Reactions
Si(OC2H5)4 + 9 O3  SiO2 + 5 CO + 3 CO2 + 10 H2O Transfer
Wafer
Process Conditions (ILD) Chamber
RF Power
Flow Rate: 100 to 300 sccm
Pressure: 50 Torr to Atmospheric
Exhaust
CVD Dielectric
O2
O3
TEOS *

Company Confidential 79
Chemical Vapor Deposition (CVD) Tungsten

titanium tungsten
Input
Cassette

Output
n-w ell p-w ell Cassette
p-channel transistor n-channel transistor
p+ substrate Wafer Wafers
Hander
Chemical Reactions
Multistation Sequential
WF6 + 3 H2  W + 6 HF
Deposition Chamber
Process Conditions
Flow Rate: 100 to 300 sccm Water-cooled
Pressure: 100 mTorr Showerheads
Temperature: 400 degrees C.
Resistively
CVD Tungsten Heated Pedestal
WF6 *
Ar
H2
N2

Company Confidential 80
Physical Vapor Deposition (PVD)

Physical
Cluster Tool Vapor
Configuration Deposition
Chambers
n-w ell p-w ell Wafers Transfer
p-channel transistor n-channel transistor Chamber
p+ substrate Loadlock

Process Conditions
Pressure: < 5 mTorr Reactive
PVD Chamber
Gases
Temperature: 200 degrees C. N S N

RF Power: Cryo Pump

Transfer e
-
+
Barrier Metals Chamber Wafer
SiH4
Ar
N2 Argon & Backside DC Power
N2 NitrogenHe Cooling Supply (+)
Ti PVD Targets *

Company Confidential 81
Planarization

Wafer
Design
Preparation

Thin Films Furnace

Photo-
lithography

Ion
Etch
Implantation

Cleaning Planarization

Test &
Assembly

Company Confidential 82
 Chemical Mechanical Planarization (CMP)

Platen
Head
Sweep Slide Polishing
Head
n-w ell p-w ell Load/Unload
Station Pad
p-channel transistor n-channel transistor
Conditioner
p+ substrate Wafer Handling Carousel
Process Conditions (Oxide) Robot & I/O
Flow: 250 to 1000 ml/min
Particle Size: 100 to 250 nm
Concentration: 10 to 15%, 10.5 to 11.3 pH
Process Conditions (Metal)
Flow: 50 to 100 ml/min
Particle Size: 180 to 280 nm Wafer
Carrier Polishing Pad
Concentration: 3 to 7%, 4.1 - 4.4 pH Slurry
Backing (Carrier) Film CMP (Oxide) Delivery
Polyurethane Silica Slurry * Wafer
Pad KOH *
Polyurethane NH4OH
H2O Platen
Pad Conditioner
Abrasive CMP (Metal)
Alumina *
FeNO3
Company Confidential 83
Test and Assembly

Wafer
Design
Preparation

Thin Films Furnace

Photo-
lithography

Ion
Etch
Implantation

Cleaning Planarization

Test &
Assembly

Company Confidential
84
 Electrical Test Probe

bonding pad
nitride
Metal 2

n-well p-well
p-channel transistor n-channel transistor
p+ substrate

Defective IC

Individual integrated circuits

are tested to distinguish good
die from bad ones.

Company Confidential 85
Die Cut and Assembly

Good chips are attached

to a lead frame package.

Company Confidential 86
Die Attach and Wire Bonding

lead frame gold wire

bonding pad

connecting pin

Company Confidential 87
Final Test

Chips are electrically

tested under varying
environmental conditions.

Company Confidential 88
Company Confidential 89
 PROCESS FLOW FOR XH035
ZL MASK (ISOMOS & THKOX)

Etch
Alignment
target
Special Notes:
1. ….
2. ….
3. ….
ZL mask (10200Å)

Oxide (500Å)
P-Epi

P-Silicon Substrate
 PROCESS FLOW FOR XH035
DW MASK (ISOMOS MODULE)

Implant Implant
DW mask DW mask DW mask
20kÅ 20kÅ 20kÅ

Special Notes:
1. ….
2. ….
Oxide (500Å)
3. …. P-Epi Lightly doped deep Lightly doped deep
N-Well N-Well

P-Silicon Substrate
 PROCESS FLOW FOR XH035
TW MASK (THKOX MODULE)

TW mask
20kÅ
Implant

Special Notes:
Oxide (500Å)
1. VP reticle is used P-Epi Lightly doped deep Lightly
Heavilydoped
doped deep
deep
2. …. N-Well N-Well

3. ….
P-Silicon Substrate
 PROCESS FLOW FOR XH035
DS MASK (HDPWELL MODULE)

20kÅ
Implant Implant

Special Notes:
Oxide (500Å)
1. …. P-Epi Deep P-Well Deep P-Well
2. …. Lightly doped deep
N-Well

P-Silicon Substrate
 PROCESS FLOW FOR XH035
AA MASK (CORE PROCESS)

AA mask
Etch
(7.7kÅ)

Oxide (500Å) Nitride (1.6kÅ)

P-Epi
Special Notes:
1. …. P-Silicon Substrate
2. ….
95Å Oxide
 PROCESS FLOW FOR XH035
FIELD OXIDE (CORE PROCESS)

Grow ~ 4550Å
Field Oxide

Special Notes:
1. ….
2. ….
 PROCESS FLOW FOR XH035
FIELD OXIDE (ISOMOS & THKOX MODULE)

Anneal

Special Notes:
Deep P-Well
1. …. Deep P-Well
Lightly doped deep
2. …. N-Well
 PROCESS FLOW FOR XH035
BN Mask (BURDIF MODULE)

Double Implant

10.2kÅ

Special Notes: Buried N Buried N

1. …. Deep P-Well

2. ….
 PROCESS FLOW FOR XH035
NW MASK (CORE PROCESS)

Triple Implant

NW Mask
20kÅ

Special Notes:
1. ….
2. ….

N-Well N-Well
 PROCESS FLOW FOR XH035
NF MASK (CORE PROCESS)

Double Implant

Special Notes:
1. …. NF Mask
2. …. 10.2kÅ

N-Well P-Well N-Well P-Well

 PROCESS FLOW FOR XH035
OC MASK (OC MODULE)
PROCESS NAME MASK LAYER
OC I-LINE PHOTO OC
OC IMPLANT
OC IMPLANT ASHING
OC IMPLANT SPM/APM
CLN

Implant Implant
OC mask OC mask
OC mask

P-Epi OC, N+
Lightly doped deep
OC, N+
Lightly doped deep
N-Well N-Well

P-Silicon Substrate
 PROCESS FLOW FOR XH035
VP MASK (THKOX MODULE)

Special Notes:
1. ….
2. …. PMOS Vt ADJUST Implant

10.2kÅ

Heavily doped deep

N-Well
 PROCESS FLOW FOR XH035
WN MASK (NMVMOS MODULE)

GRADED NMOS Implant

10.2kÅ

Special Notes:
GNDIFF GNDIFF
1. …. Deep P-Well

2. ….
 PROCESS FLOW FOR XH035
WP MASK (PMVMOS MODULE)

GRADED PMOS Implant

10.2kÅ

Special Notes:
GPDIFF GPDIFF
1. ….
Heavily doped deep
2. …. N-Well
 PROCESS FLOW FOR XH035
TG MASK (THKOX MODULE)

TG Implant
Wet Etch

10.2kÅ
Special Notes:
1. ….
2. …. N-Well P-Well Heavily doped deep
N-Well
 PROCESS FLOW FOR XH035
TG/Gate Oxide (CORE PROCESS)

TG Implant

Special Notes:
1. ….
2. …. N-Well P-Well N-Well P-Well
 PROCESS FLOW FOR XH035
UG Implant (HRPOLY Module)

UG Implant

10.2kÅ
Undope
Special Notes:
1. …. d Poly 1
2. …. Doped
Poly 1

N-Well P-Well N-Well P-Well

 PROCESS FLOW FOR XH035
UG Implant (CORE PROCESS)

Special Notes:
1. …. UG Implant
2. ….

Doped
Poly 1

N-Well P-Well N-Well P-Well

 PROCESS FLOW FOR XH035
PL1 (CORE PROCESS)

Etch

Special Notes:
1. …. 13.2kÅ
2. ….

N-Well P-Well N-Well P-Well

 PROCESS FLOW FOR XH035
NM Implant (CORE PROCESS)

NNM Mask
10.2kÅ
Special Notes:
1. …. Implant
2. ….

Poly
Field Ox N- N-
Field Ox

P-Well
 PROCESS FLOW FOR XH035
PM Implant (CORE PROCESS)

PPM Mask
10.2kÅ
Special Notes:
1. …. Implant
2. ….

Poly
Field Ox P- P-
Field Ox

N-Well
 PROCESS FLOW FOR XH035
CAP Poly (CAPPOLY Module)

Etch
CAP PL2 Implant

Special Notes:
1. ….
2. ….
 PROCESS FLOW FOR XH035
Spacer (CORE PROCESS)

Special Notes: Etch

1. ….
2. ….

Poly
Field Ox P- P-
Field Ox

N-Well
 PROCESS FLOW FOR XH035
NP Implant (CORE PROCESS)

NNM Mask
10.2kÅ

Implant
Special Notes:
1. ….
2. ….

Poly
Field Ox N+
N- N-
N+ Field Ox

P-Well
 PROCESS FLOW FOR XH035
PP Implant (CORE PROCESS)

PPM Mask
10.2kÅ

Implant
Special Notes:
1. ….
2. ….

Poly
Field Ox P+
P- P-
P+ Field Ox

N-Well
 PROCESS FLOW FOR XH035
SB (CORE PROCESS)

10.2kÅ

Etch
Clean

Special Notes:
1. ….
2. ….

Poly
Field Ox P+
P- P-
P+ Field Ox

N-Well
 PROCESS FLOW FOR XH035
SB (CORE PROCESS)

21nd
st RTA Anneal

Special Notes:
1. ….
2. ….

Poly
Field Ox P+
P- P-
P+ Field Ox

N-Well
 PROCESS FLOW FOR XH035
ILD (CORE PROCESS)

CMP

Special Notes:
1. ….
2. ….

Poly
Field Ox P+
P- P-
P+ Field Ox

N-Well
 PROCESS FLOW FOR XH035
CON (CORE PROCESS)

8.24kÅ

Special Notes:
1. ….
2. ….

Poly
Field Ox P+
P- P-
P+ Field Ox

N-Well
 PROCESS FLOW FOR XH035
M1/2/3 (CORE PROCESS)

13kÅ Anneal
Special Notes:
1. ….
2. ….

Poly Poly
N+ Field Ox Field Ox
N- N+
N- P+
P- P -P +
P-Well N-Well
 PROCESS FLOW FOR XH035
MiM DMiM (MiM/DMiM MODULE)

Etch
Anneal
13kÅ
Special Notes:
1. ….
2. ….

Poly Poly
N+ Field Ox Field Ox
N- N+
N- P+
P- P -P +
P-Well N-Well
 PROCESS FLOW FOR XH035
IMD1/2 (CORE PROCESS)

CMP

Special Notes:
1. ….
2. ….

Poly Poly
N+ Field Ox Field Ox
N- N+
N- P+
P- P -P +
P-Well N-Well
 PROCESS FLOW FOR XH035
Via 1/2 (CORE PROCESS)

CMP

10.2kÅ

Special Notes:
1. ….
2. ….

Poly Poly
N+ Field Ox Field Ox
N- N+
N- P+
P- P -P +
P-Well N-Well
 PROCESS FLOW FOR XH035
Pad (CORE PROCESS)

40kÅ

Special Notes: 6K
1. …. 10K 8K
2. ….
 PROCESS FLOW FOR XH035
POLYIMIDE (PIB MODULE)

PROCESS NAME MASK LAYER Develop

PI
O2 Ashing
PIPlasma
Bake
PRE-PI COAT O2 PLASMA
PI COAT
PIB I-LINE PHOTO PI PI Mask
RESIST STRIP
PI BAKE
PI BAKE ASHING
Company Confidential 125
Process Flow For XH035

Deep Well
CAPPOLY

LOCOS
SPACER

Well & Vt Adjust

Source Drain

GATE
SALICIDE

LDD Implant

BEOL

Company Confidential 126

1. Deep Well
Key: Deep Well Implant With Thick Screen Ox (500 A): New in KCH for 700Kev using Screen Oxide of 500A

1. ZL MASK (CORE PROCESS) 3. TW MASK (THKOX MODULE)

OXIDE/PHOTO/ETCH/STRIP HEAVILY DOPED DEEP N-WELL IMPLANT/STRIP
AND DEEP N-WELL DRIVE FOR ISOMOS/THKOX MODULE

1150C

2. DW MASK (ISOMOS MODULE) 4. DS MASK (HDPWELL MODULE)

LIGHTLY DOPED DEEP N-WELL IMPLANT/STRIP DEEP P-WELL IMPLANT/STRIP

Company Confidential 127

2. Locos Formation
Key: ZL Oxide 500A has been removed during Pad Oxide Pre-Clean

1. AA MASK (CORE PROCESS) 3. FIELD OXIDE(CORE PROCESS)

PAD OXIDE/NITRIDE DEP/PHOTO/ETCH Oxide Removal

2. FIELD OXIDE(CORE PROCESS) 4. FIELD OXIDE(CORE PROCESS)

Field Oxidation Nitride Removal

Grow on Nitride ~ 50A

Oxide Remain ~ 75A

Pre Sac target ~150A

Company Confidential 128

3. Well & Vt Adjust Implant
Key: Well & Vt Adjust Implant with Screen Oxide 200A

1. SCREEN OXIDE 3. NW MASK (CORE PROCESS)

SACRIFICAL OXIDE 200A/DEEP WELL DRIVE N-WELL IMP/N-WELL ANTI-PUNCH-THROUGH IMP/N-WELL Vt ADJUST IMP/STRIP

2. BN MASK (BURDIF MODULE) 4. NF MASK (CORE PROCESS)

BURIED-N IMPLANTS/RESIST STRIP/BURIED-N ANNEAL N-FIELD IMPLANT/N-FIELD Vt ADJUST IMPLANT/STRIP

Company Confidential 129

3. Well & Vt Adjust Implant 2
Key: Well & Vt Adjust Implant with Screen Oxide 200A

5. VP MASK (THKOX MODULE) 7. WP MASK (PMVMOS MODULE)

PMOS Vt ADJUST IMPLANT/STRIP GRADED PMOS IMPLANT/STRIP

6. WN MASK (NMVMOS MODULE) 8. Pre TG RTA Anneal

GRADED NMOS IMPLANT/STRIP

Company Confidential 130

4. Gate Formation
Key: Sacrificial Oxide has been removed during TG Oxide Pre-Clean (Target ~250A)

1. TG MASK (THKOX MODULE) 3. GATE OXIDE (CORE PROCESS)

THICK GATE OXIDE 380 A THIN GATE OXIDE 70 A

Thin Gate ~74A

Final Thick Gate ~385A

2. TG MASK (THKOX MODULE) 4. POLY DEPOSITION

TG MASK/IMPLANT/ETCH/STRIP POLY 1 DEP 3000A

After IMP TG WET ETCH 450A (TARGET)

Supposed to remove all of the Thick No Oxidation grow on Field
Oxide at open area

Company Confidential 131

4. Gate Formation 2
Key: Various Resistance Poly Formation with UG/NG Mask

5. UG MASK (HRPOLY MODULE) 7. POLY MASK (CORE PROCESS)

POLY MASK/ETCH/STRIP

6. POLY MASK (CORE PROCESS)

ANNEAL

Company Confidential 132

5. LDD Implant
Key: Oxide remain of 50A after Poly 1 Etch causing the final LDD Screen Oxide thickness of 128A

1. LDD OXIDATION (CORE PROCESS) 3. PM MASK (CORE PROCESS)

PPM MASK/P-LDD IMPLANT/STRIP

LDD Thickness on Monitor ~ 115A

Final LDD Screen OX ~128A

2. NM MASK (CORE PROCESS)

NNM MASK/N-LDD IMPLANT/STRIP

Company Confidential 133

6. CAPPOLY
Key: Remaining LDD Screen Oxide 128A plus LPTEOS deposition 145A make the final PIP Insulator

1. CAP LPTEOS DEPO (CAPPOLY MODULE) 3. CAP POLY IMP (CAPPOLY MODULE)
OXIDE DEP IMPLANT

LPTEOS Deposition ~ 145A

2. POLY 2 DEPO (CAPPOLY MODULE)

POLY DEP

Company Confidential 134

7. Spacer Formation
Key: Remaining LDD Screen Oxide & LPTEOS deposition ~ 260A plus Spacer Deposition 1700A

1. SPACER OXIDE (CORE PROCESS)

SPACER DEP0 1700A

2. SPACER (CORE PROCESS)

SPACER ETCH

Remove all Oxide on ACT

Company Confidential 135

8. S/D Formation
Key: SD Fur Oxidation 70A on monitor

1. SD OXIDATION (CORE PROCESS) 3. PP MASK (CORE PROCESS)

PPM MASK/P+ IMPLANT/STRIP
SD FUR OXIDATION 60 A

2. NP MASK (CORE PROCESS) 4. PP MASK (CORE PROCESS)

NNM MASK/N+ IMPLANT/STRIP ANNEAL NP & PP Activation

Company Confidential 136

9. Salicide Formation
Key: SD Fur Oxidation 70A on monitor remain

1. SB MASK (CORE PROCESS) 3. SB MASK (CORE PROCESS)

OXIDE DEPODITION 100A SBM MASK/ETCH/STRIP/CLEAN

2. SB MASK (CORE PROCESS) Oxide remain on ACT < ~50A

NITRIDE DEPODITION 210A

Company Confidential 137

9. Salicide Formation 2
Key: Oxide at the Salicide Formation area shall be remove during PRE TI/TIN CLN (Removal Target is 250A)

1. SB MASK (CORE PROCESS)

TITAINUM DEPOSITION 325A

2. SB MASK (CORE PROCESS)

ANNEAL/CLEAN/ANNEAL

Company Confidential 138

10. BEOL Scheme

BEOL

Company Confidential 139

Metal Depo & Etch

Anneal

Special Notes:
1. Metal Stack
: Ti/TiN/Al/Ti/TiN
Poly Poly
N+ Field Ox Field Ox
N- N+
N- P+
P- P -P +
P-Well N-Well

Company Confidential 140

 PROCESS FLOW FOR XH035
IMD & Via Formation
CMP

Special Notes:
1. Ti & TiN Depo
Prior to W Depo Poly Poly
N+ Field Ox Field Ox
N- N+
N- P+
P- P -P +
P-Well N-Well

Company Confidential 141

Pad (CORE PROCESS)

SIN
HDP

Special Notes:
1. Pad Formation
:Criteria
Al Loss > 500A
- penetrate both Top Metal Ti/TiN
layers
- Fab Control ~ 700A+/- 300A

Company Confidential 142

10. MIM Scheme

Company Confidential 143

Company Confidential 144
 Q-time disposition procedure flow

Lot trigger Q-time over

No Raise NCP by Fur PE/AE due to tool

Q-time over due to
issue/alarm and process issue
mis-planning?

Yes

Raise NCP by ME/LL

Failed
Result Scrap
Lot release to flow as normal
Passed
NCP close by PE
Raise full map E-test form after data review 5D/MRB report

Future hold at EBO to verify Etest result Ship out

Company Confidential 145

 Q-Time Alert

> Purpose : To prevent corrosion or mushroom defect issue due to Q-

time over.
> Examples of Specified Q-time duration:
> Avoid putting Future hold or Merge Hold for above steps

Start step End step Duration (hours)

Pad Etch Pad Etch Ashing 4
Pad Etch Ashing Polymer Remove/Solvent Clean 4
Polymer Remove/Solvent Clean Pad Alloy 12

Mushroom Defect

Company Confidential 146

Company Confidential 147
General Rule for Rework

Company Confidential 148

Company Confidential 149
Non Pro Bank

> Key Definition:

> Non Pro Bank – Non-production Bank. All lots that are not on the
> production floor will be given the status NonProBank to indicate
> that they are placed in the non production bank
> Non Pro Bank Fab – NPB fab located at Litho area. Lots in the
> production line are placed here in SMIF pods
> Non Pro Bank Test – NPB in the test area. Shippable excess
> wafers in the test area are placed here in vendor boxes only
> Logical NPB in – To change the status of a lot from OnHold to
> NPB in SiView
> Logical NPB out – To change the status of a lot from NPB to
> OnHold in SiView
> NPB extension – To extend the length of time that a lot is placed
> in the NPB (max 3 months, max extension time 1 month) .

Company Confidential 150

 NPB Rule

> NPB period < 1 month

Release the NPB hold. MPC Tech to send the physical lot to
destinated area at Fab area.
> NPB period > 1 month
Submit Scan Request Form to DM (Must get approval from
Supervisor and DM Manager.
Release the NPB hold, reclaim using EXSR with the scan request
serial number given by DM.

> NPB period is 3 months (maximum). If there is a need

> to NPB in more than 3 months, then NPB Extension is
> perform.

Company Confidential 151

Company Confidential 152
Special Work Request
SWR (Special Work Request) – special or different condition is being
applied to a registered Process or Product. For Engineer to tune the
process and confirm the new condition. For customer to apply different
condition to certain number of lots.
External SWR Internal SWR

• For P lots • For E lot, such as EF, EW (MPW) and

ET
• Record kept and managed by Quality
• Record kept and managed by
• Need approval from Quality, Technology
YE/Technology, Customer (depend on
the category), Manufacturing, and • Approval from route owner
Production Planning (CS & MPC) (Technology) and process owner
(Module)
• Request come from customer or
internal (YE / Technology or module) • No approval is needed from Quality
but information to PP/MPC if it affect
• SWR Datasheet in chart (inline/Etest) the delivery schedule
is needed before the shipment
• Request come from internal only
(R&D or Module)

• Report is needed to close the SWR

and not later than 3 months after lot
end or terminated
Company Confidential 153
Special Work Request Flow

Initiate SWR Request

(Requestor) X-Fab Sarawak Customer

Fill-up
SWR Form with
Dedicated Split Table
(Originator)

Route for internal approval

1
(Originator)

2
NO
Approve? STOP

YES

YES
Customer Notification/ YES Obtain customer approval/notify Approve?
Approval Required? (R&D/ CP/ YE)

NO NO
STOP
Flag in SiView & Future Hold
(Originator)

Execute SWR
(Originator/ Executor)

Company Confidential 154

Originator and Requestor’s responsibility

> Originator/Requestor to ensure:

> documentation in place : MUST acquire approval before

> execution

> Flag lot as SWR & correct Future Hold setting at right step

> module understand objective and split plan detail

> latest version of SWR posted/notified for execution

> right buddy for split plan’s verification

> complete updating of split plan upon execution

> timely submission of report / ECN to close the SWR.

Company Confidential 155

Company Confidential 156
 What is defect inspection?

> Defect scan to prevent defects in the production line or the

process itself.

Company Confidential 157

Tools for Defect Inspection

KLA AIT SCAN

Company Confidential 158

SEM (Scanning Electron Beam)

> Highest count of wafer will be send for SEM review to identify the
defect.

Company Confidential 159

Specification for Defect Inspection

0.35 Tech

Products with
>= 1000 dies

YES NO

Defective Die% Defect Count

< 10% > 10% < 200 > 200

Lot release Scrap Lot release Scrap

Company Confidential 160

Post E-test Step

Company Confidential 161

Company Confidential 162
 What is wafer backgrid?

> Wafer backgrid = Wafer thinning

> Process of grinding the backside of the wafer to the correct wafer
thickness prior to assembly.

> Wafer backgrinding has not always been necessary, but the drive to
make packages thinner and thinner has made it indispensable.

Company Confidential 163

XFAB-KCH Backgrind Process Flow

Company Confidential 164

Disco DFG8540 Back Grinder

Minimum thickness available: 270um

Thicknesses that are available online (um):
280, 290, 350, 360, 368, 370, 380, 420, 445,
480, 500, 540.

Company Confidential 165

Contactless Wafer Thickness and Geometry Gauge
(Eichhorn + Hausmann MX204-8-21V)

Number of wafers
Measurem Control
CL Spec. Size required for
ent Method
measurement

Avg +/- 7 21
+/- 20 um
Thickness um spots 2 wafers / lot (>12
wafers)
TTV <5 um < 8 um 1 spot SPC
1 wafer / lot (≤ 12
120 0 +/- 300 wafers)
BoW 1 spot
um um

Measurement to be carried out before

and after backgrind

Company Confidential 166

Automatic Visual Inspection

> For products with AVI, an addition OQA macro inspection step is
added to the process flow to cater for the bare eyes inspection for
wafer edge and wafer backside

> All complete dies within the wafers are scanned and reviewed by
OQA inspectors

> Control limit for the AVI is set at 95%. All products performed below
95% will be held and pending for Engineer’s disposition

> Defect map is provided for the shippable lots

Company Confidential 167

 OQA Inspection Tool

> Automatic Visual Inspection Tool & Method

 Perform for all COT products

 100% wafer and die level

Company Confidential 168

 OQA Reject Criteria
Control limit for AVI: <95%

Inspection Item Criteria

General  Etest result pass

 Wafer ID versus cassette slot correct
 Laser mark – clear and correct
 Edge exclusion <5mm
Wafer surface/ backside  Chipping (2mm x 1mm)/flaking, crack, scratch, broken, discoloration
Macro  Specifically for COT products, acceptable scratch is < 5cm
Wafer surface Micro  Embedded foreign material/ particle, foreign material/particle
(using 10X Objective) on wafer surface
Automatic Visual Inspection  Discoloration
 Contamination, polymer residue
 Voids
 Peeling or lifting
 Metal line missing or bridge, corrosion
 Probe marks not on good dies
 Oxide, passivation, poly defects
 Misalignment
Other  SWR
 5D/MRB

Company Confidential 169

 Control Plan and OCAP
OCAP for OQA Inspection Process

Legend:
OCAP: Out of Control Action Plan
OOS: Out of Specification

Company Confidential 170

 Lot Information (Maverick and SWR Form)

> Part of the inspection items are:

– Visual inspection for the lots/ wafers
 Conspicuous lot with defect map – Maverick
 Maverick Lot Information will be raised and “Maverick” will be checked in the
“Lot Information is attached” label

– E-test/PCM data buyoff

– Inline data buyoff

 Lot with SWR – SWR
 “SWR – referred to PCN” will be checked
in the “Lot Information is attached” label

Legend:
PCM: Process Control Monitor

Company Confidential 171

Lot Information (Material Waiver Form)

– OOS Product
– Lot will be disposed via Material Review Board (MRB) and only submit
to customer upon approval
 Material Waiver Form will be raised through online system
 Lot will be released for shipment ONLY after customer has approved

– Sample snap shot of Material Waiver Form

Company Confidential 172

Pre-packing and Final Inspection

> 2 types of packing

– Vertical SEP shipping box
 This is used for general production/ non backgrind wafers

– Horizontal wafer jar

 This is used for all the engineering/prototypes lots and backgrind wafers

Company Confidential 173

 NVM IP Test Strategy Workshop
Yield Analysis Strategy For XH018 NVRAM & eFlash

YE-NVM Team
11 Sep 2014

Company Confidential 174

Content

> Fab Process Monitoring & Limitation

> Fab Detection Overview
– Issues Overview By Technology
– Bin 3: ONO CAP SIN THK Issue
– Bin 6: Pre HTO CAP Etch Ash
> NVM Sort Test Strategy
– Sort Test Setup Approach
– Sort Test Monitoring
– Sort Test Yield Recovery
– Sort Test Yield Improvement
– Sort Yield Classification
– Sort Yield Analysis
> Fab Overall Analysis Strategy

Company Confidential 175

Content

> Fab Process Monitoring & Limitation

> Fab Detection Overview
– Issues Overview By Technology
– Bin 3: ONO CAP SIN THK Issue
– Bin 6: Pre HTO CAP Etch Ash
> NVM Sort Test Strategy
– Sort Test Setup Approach
– Sort Test Monitoring
– Sort Test Yield Recovery
– Sort Test Yield Improvement
– Sort Yield Classification
– Sort Yield Analysis
> Fab Overall Analysis Strategy

Company Confidential 176

Fab Process Monitoring & Limitation

Item Standard measurement Limitation Remark

1) Not all wafer/lot Cannot Detect

1 wafer/lot, 3 monitor wafers/lot Variation;
Inline THK 2) Not all sites/wafer
5 sites, 9 sites
3) Not all dies/wafer 1) Within Lot
1) Not all wafer/lot 2) Within Wafer
Inline CD 1 wafer/lot, 2 wafers/lot 3) Within Dies
2) Not all sites/wafer
Inline OLY 5 sites, 9 sites
3) Not all dies/wafer
Optical Inspection 4 wafers/lot 1) Not all wafer/lot Cannot Detect
Within Lot
Defect Inspection 2 wafers/lot 1) Not all wafer/lot Variation;

OQA Inspection
OQA Macro All wafers 1) Macro Inspection Macro Inspection
Inspection (AVI)

1) Not all sites/wafer Cannot Detect

PCM Standard All wafers, 5 sites/wafer 2) Not all dies/wafer Variation;
3) Primitive Devices
1) Within Wafer
1) Not all dies/wafer
Pre Bake Test 2) Within Dies
All wafers, Max 30 sites 2) Test Structure
Post Bake Test
(SLM)
1) All wafer, all Dies All dies & all IPs
Sort Test All wafers, All dies
2) Production IP

Company Confidential 177

Content

> Fab Process Monitoring & Limitation

> Fab Detection Overview
– Issues Overview By Technology
– Bin 3: ONO CAP SIN THK Issue
– Bin 6: Pre HTO CAP Etch Ash
> NVM Sort Test Strategy
– Sort Test Setup Approach
– Sort Test Monitoring
– Sort Test Yield Recovery
– Sort Test Yield Improvement
– Sort Yield Classification
– Sort Yield Analysis
> Fab Overall Analysis Strategy

Company Confidential 178

 Issues Overview By Technology

> Major issues for XH035 & XH018 categorize by Detection Methods.

Total: 23 Issues Total: 6 Issues

***Excluding 5 Defect Issues ***Excluding 13 Defect Issues

> Both XH035 & XH018 Technologies shows that Sort Test is the most affective
detection method.
> XH018 so far has two NVM issues; Both are detected through Sort Test
> Bin 3 :ONO CAP SIN Thickness issue
> Bin 11:PRE HTO CAP ETCH ASH

Company Confidential 179

 Bin 3: ONO CAP SIN THK Issue

> Bin 3 –Cannot be detect by PCM Test even though NVL parameters trigger.

Company Confidential 180

Bin 6: Pre HTO CAP Etch Ash

> Bin 6-also cannot be detect through PCM Test even though NVSA parameters
trigger.
Sort Data

Company Confidential 181

Content

> Fab Process Monitoring & Limitation

> Fab Detection Overview
– Issues Overview By Technology
– Bin 3: ONO CAP SIN THK Issue
– Bin 6: Pre HTO CAP Etch Ash
> NVM Sort Test Strategy
– Sort Test Setup Approach
– Sort Test Monitoring
– Sort Test Yield Recovery
– Sort Test Yield Improvement
– Sort Yield Classification
– Sort Yield Analysis
> Fab Overall Analysis Strategy

Company Confidential 182

Sort Test Setup Approach

Sort Test Program

Setup **NVM IP

Data Collection

NO
Control Limit
Sample > 20 lots

YES
Setup Control Limit

NO NO
Review Spec 1 Review Specification Review Spec 2
Sample > 40 lots Product > 20

YES YES
Revise Spec 1 Revise Spec 2

Generate Trend Chart

Daily Monitor Refer to

Sort Test Monitoring

Monthly Trend Chart

Review

Company Confidential 183

Sort Test Yield Monitoring

Daily Yield
Tracking

Generate Trend Chart

Monthly Trend
Chart
NO Review

Exist Lot/Wafer
Below Yield Target
Triggering Limit

YES

Trigger Yield Loss

Recovery

Company Confidential 184

Sort Test Yield Recovery

Identified Low Yield

Lot/Wafer

Define: Problem
Statement

Perform Analysis to
Identify possible root
cause

Process undergoing for

the root cause
identification

Feedback to FMEA to
prevent re occurrence

Go back to Yield
Monitoring

Company Confidential
Sort Test Yield Improvement

Yield Performance
below Target

Failure Identification

Analysis to Identify
area of improvement

NO Implement the yield

improvement action
plan

Any Improvement

YES
Proceed with CCB

Collect more NO Get Approval

data for for CCB
confirmation
YES
Implementation of
Process Change

Company Confidential 186

 • D0
• CRASH

• EXCURSION
–Cause: Process drift

–Cause: Random defect

–Financial impact: Low
–Financial impact: High
–Financial impact: High
• Ys (Systematic yield loss)
–Financial impact: Disaster

–Cause: Baseline marginality

–Difficulty to be solved: Easy

–Difficulty to be solved: High

–Difficulty to be solved: High

–Difficulty to be solved: High

–Phenomenon: Random yield loss
–Cause: Tool/Process variation/deviation
Sort Yield Classification

Company Confidential
–Phenomenon: Intermittent few lots/wafers very low yield
–Phenomenon: Constant fail pattern for almost all lots/wafers
–Phenomenon: Lots of lots fail same issues during certain period

100

100
0
20
40
60
80
100

0
20
40
60
80
0
20
40
60
80

100

0
20
40
60
80
Yield

Yield

Yield
Yield

Lot-20 Lot-20 Lot-20 Lot-20

Lot-21 Lot-21 Lot-21 Lot-21
Lot-22 Lot-22 Lot-22 Lot-22
Lot-23 Lot-23 Lot-23 Lot-23
Lot-24 Lot-24 Lot-24 Lot-24
Lot-25 Lot-25 Lot-25 Lot-25
Lot-26 Lot-26 Lot-26 Lot-26
Lot-27 Lot-27 Lot-27 Lot-27
Lot-28 Lot-28 Lot-28 Lot-28
Lot-29 Lot-29 Lot-29 Lot-29
Lot-30 Lot-30 Lot-30 Lot-30
Lot-31 Lot-31 Lot-31 Lot-31
Lot-32 Lot-32 Lot-32 Lot-32
Lot-33 Lot-33 Lot-33 Lot-33
Lot-34 Lot-34 Lot-34 Lot-34
Lot-35 Lot-35 Lot-35 Lot-35
Lot-36 Lot-36 Lot-36 Lot-36
Lot-37 Lot-37 Lot-37 Lot-37
Lot-38 Lot-38 Lot-38 Lot-38
Lot-39 Lot-39 Lot-39 Lot-39
Lot-40 Lot-40 Lot-40 Lot-40
Lot-41 Lot-41 Lot-41 Lot-41
Lot-42 Lot-42 Lot-42 Lot-42
Lot-43 Lot-43 Lot-43 Lot-43
Lot-44 Lot-44 Lot-44 Lot-44
Lot-45 Lot-45 Lot-45 Lot-45
Lot-46 Lot-46 Lot-46 Lot-46
Lot-47 Lot-47 Lot-47 Lot-47
Lot-48 Lot-48 Lot-48 Lot-48
Lot-49 Lot-49 Lot-49 Lot-49
Lot-50 Lot-50 Lot-50 Lot-50
Lot-51 Lot-51 Lot-51 Lot-51
Lot-52 Lot-52 Lot-52 Lot-52
Lot-53 Lot-53 Lot-53 Lot-53
187
Lot#

Lot#
Lot#

Lot#
Sort Yield Analysis

1) Pareto Bin
1) Sort maps study [ Select Sort Bins Chart] Data Level : Wafer
Duration : 2006-05-01 - 2006-12-12

- Zonal 100.00

90.00
100.0

90.0

- Spatial Sensitivity 80.00

70.00
80.0

70.0

- Chamber trend

Accumulated Frequency
60.00 60.0

Percentage
50.00 50.0

- Scatter Trend 40.00 40.0

30.00 30.0

20.00 20.0

2) Bin Analysis 10.00 10.0

0.00 0.0

- Stop-on-fail vs. Continue-on-fail

Bin19

Bin21
Bin26

Bin15

Bin11

Bin10

Bin22
Bin9

Bin20

Bin13

Bin23

Bin18

Bin8

Bin24

Bin30
Value Cumulative Percent

- Bin sequence swapping

2) Sort Map analysis
3) Test Analysis
- Shmoo (time/Vcc, soft/hard fail screening)
- Temperature effect
- Sort Parametric / Analog Data

4) Bitmap Analysis
4) Analysis

4) Bitmap analysis 3) Chamber Trend

Company Confidential 188

Content

> Fab Process Monitoring & Limitation

> Fab Detection Overview
– Issues Overview By Technology
– Bin 3: ONO CAP SIN THK Issue
– Bin 6: Pre HTO CAP Etch Ash
> NVM Sort Test Strategy
– Sort Test Setup Approach
– Sort Test Monitoring
– Sort Test Yield Recovery
– Sort Test Yield Improvement
– Sort Yield Classification
– Sort Yield Analysis
> Fab Overall Analysis Strategy

Company Confidential 189

Overall Fab Analysis Strategy

FA Sort yield Spatial Yield trend/

EMMI Sensitivity Distribution/Sign
PFA Bit map SIMS Yield
EFA Relative bin ature
Curve model
Trace Pareto
TEM D0
FIB Zonal Analysis
EDX Bin Analysis Ys
CD Lot to lot
XSEM Liquid Datalog
Comparison crystal Sort
Parametric Within
Construction Shmoo Wafer
Analysis Temp. Effect to wafer wafer(map)
Comparison Study Test Analysis Bitmap

Tool vs sort Defect

Yield Sensitive Parameters/ In-line to Sort
Tool Lot vs Tools Map
Window Study Correlation
Commonality Short loop Defect
study Zone test Trend
Time trend In-line
Chart / Signature
CCB/SWR Partitioning Database
Wafer position study ET to Sort
(POSITRACK) Site Correlation
Process Parameters KLA Lot to lot
In-line
Lot Operation Report record Wafer
ALR/5D AIT In-line to wafer ET Full-map
scan ET
OOC/OOS
Lot history D0 Parametric/In-line
Company Confidential 190
Thank you for your attention.
www.xfab.com

Company Confidential 191