# do pipemult2_run_msim_rtl_vhdl.

do
# if {[file exists rtl_work]} {
# vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility
2016.10 Oct 5 2016
# vmap work rtl_work
# Copying C:/intelFPGA/16.1/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
#
# vcom -93 -work work {C:/AlteraPrj/pipemultQP16_1/Schematic/pipemult.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5
2016
# Start time: 09:23:09 on Apr 14,2018
# vcom -reportprogress 300 -93 -work work
C:/AlteraPrj/pipemultQP16_1/Schematic/pipemult.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity pipemult
# -- Compiling architecture bdf_type of pipemult
# End time: 09:23:10 on Apr 14,2018, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# vcom -93 -work work {C:/AlteraPrj/pipemultQP16_1/Schematic/ram.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5
2016
# Start time: 09:23:10 on Apr 14,2018
# vcom -reportprogress 300 -93 -work work
C:/AlteraPrj/pipemultQP16_1/Schematic/ram.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity ram
# -- Compiling architecture rtl of ram
# End time: 09:23:10 on Apr 14,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work work {C:/AlteraPrj/pipemultQP16_1/Schematic/mult.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5
2016
# Start time: 09:23:10 on Apr 14,2018
# vcom -reportprogress 300 -93 -work work
C:/AlteraPrj/pipemultQP16_1/Schematic/mult.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity mult
# -- Compiling architecture SYN of mult
# End time: 09:23:11 on Apr 14,2018, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
#
vsim work.pipemult
# vsim work.pipemult
# Start time: 09:30:40 on Apr 14,2018
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading work.pipemult(bdf_type)
# Loading work.mult(syn)
# Loading ieee.std_logic_arith(body)
# Loading lpm.lpm_components
# Loading lpm.lpm_hint_evaluation(body)
# Loading lpm.lpm_mult(lpm_syn)
# Loading work.ram(rtl)
# ** Fatal: (vsim-3807) Types do not match between component and entity for port
"wraddress".
# Time: 0 ps Iteration: 0 Instance: /pipemult/b2v_inst1 File:
C:/AlteraPrj/pipemultQP16_1/Schematic/ram.vhd Line: 9
# FATAL ERROR while loading design
# Error loading design
vsim work.pipemult
# End time: 09:30:47 on Apr 14,2018, Elapsed time: 0:00:07
# Errors: 1, Warnings: 0
# vsim work.pipemult
# Start time: 09:30:47 on Apr 14,2018
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading work.pipemult(bdf_type)
# Loading work.mult(syn)
# Loading ieee.std_logic_arith(body)
# Loading lpm.lpm_components
# Loading lpm.lpm_hint_evaluation(body)
# Loading lpm.lpm_mult(lpm_syn)
# Loading work.ram(rtl)
# ** Fatal: (vsim-3807) Types do not match between component and entity for port
"wraddress".
# Time: 0 ps Iteration: 0 Instance: /pipemult/b2v_inst1 File:
C:/AlteraPrj/pipemultQP16_1/Schematic/ram.vhd Line: 9
# FATAL ERROR while loading design
# Error loading design
# End time: 09:30:48 on Apr 14,2018, Elapsed time: 0:00:01
# Errors: 1, Warnings: 0
vcom -93 -work work C:/AlteraPrj/pipemultQP16_1/Schematic/pipemult.vhd
# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5
2016
# Start time: 09:33:21 on Apr 14,2018
# vcom -reportprogress 300 -93 -work work
C:/AlteraPrj/pipemultQP16_1/Schematic/pipemult.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity pipemult
# -- Compiling architecture bdf_type of pipemult
# End time: 09:33:22 on Apr 14,2018, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
vsim work.pipemult
# vsim work.pipemult
# Start time: 09:33:33 on Apr 14,2018
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading work.pipemult(bdf_type)
# Loading work.mult(syn)
# Loading ieee.std_logic_arith(body)
# Loading lpm.lpm_components
# Loading lpm.lpm_hint_evaluation(body)
# Loading lpm.lpm_mult(lpm_syn)
# Loading work.ram(rtl)
add wave -position end sim:/pipemult/clk1
add wave -position end sim:/pipemult/wren
add wave -position end sim:/pipemult/dataa
add wave -position end sim:/pipemult/datab
add wave -position end sim:/pipemult/wraddress
add wave -position end sim:/pipemult/rdaddress
add wave -position end sim:/pipemult/q
add wave -position end sim:/pipemult/SYNTHESIZED_WIRE_0
add wave -position end sim:/pipemult/SYNTHESIZED_WIRE_1
force -freeze sim:/pipemult/clk1 1 0, 0 {50 ps} -r 100
add wave -position end sim:/pipemult/clk1
add wave -position end sim:/pipemult/wren
add wave -position end sim:/pipemult/dataa
add wave -position end sim:/pipemult/datab
add wave -position end sim:/pipemult/wraddress
add wave -position end sim:/pipemult/rdaddress
add wave -position end sim:/pipemult/q
add wave -position end sim:/pipemult/SYNTHESIZED_WIRE_0
add wave -position end sim:/pipemult/SYNTHESIZED_WIRE_1
force -freeze sim:/pipemult/clk1 1 0, 0 {50 ps} -r 100
force -freeze sim:/pipemult/wren 00000010 0
# ** Error: (vsim-4026) Value "00000010" does not represent a literal of the
enumeration type.
# ** Error: (vsim-4011) Invalid force value: 00000010 0.
#
force -freeze sim:/pipemult/wren 00000010 0
# ** Error: (vsim-4026) Value "00000010" does not represent a literal of the
enumeration type.
# ** Error: (vsim-4011) Invalid force value: 00000010 0.
#
force -freeze sim:/pipemult/datab 00000011 0
run
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result
will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /pipemult/b2v_inst/lpm_mult_component
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result
will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /pipemult/b2v_inst/lpm_mult_component
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result
will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /pipemult/b2v_inst/lpm_mult_component
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result
will be 'X'(es).
# Time: 0 ps Iteration: 1 Instance: /pipemult/b2v_inst/lpm_mult_component
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result
will be 'X'(es).
# Time: 0 ps Iteration: 1 Instance: /pipemult/b2v_inst/lpm_mult_component
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result
will be 'X'(es).
# Time: 50 ps Iteration: 0 Instance: /pipemult/b2v_inst/lpm_mult_component
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result
will be 'X'(es).
# Time: 50 ps Iteration: 0 Instance: /pipemult/b2v_inst/lpm_mult_component
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result
will be 'X'(es).
# Time: 100 ps Iteration: 0 Instance: /pipemult/b2v_inst/lpm_mult_component
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result
will be 'X'(es).
# Time: 100 ps Iteration: 0 Instance: /pipemult/b2v_inst/lpm_mult_component
add wave -position end sim:/pipemult/clk1
add wave -position end sim:/pipemult/wren
add wave -position end sim:/pipemult/dataa
add wave -position end sim:/pipemult/datab
add wave -position end sim:/pipemult/wraddress
add wave -position end sim:/pipemult/rdaddress
add wave -position end sim:/pipemult/q
add wave -position end sim:/pipemult/SYNTHESIZED_WIRE_0
add wave -position end sim:/pipemult/SYNTHESIZED_WIRE_1
add wave -position end sim:/pipemult/clk1
add wave -position end sim:/pipemult/wren
add wave -position end sim:/pipemult/dataa
add wave -position end sim:/pipemult/datab
add wave -position end sim:/pipemult/wraddress
add wave -position end sim:/pipemult/rdaddress
add wave -position end sim:/pipemult/q
add wave -position end sim:/pipemult/SYNTHESIZED_WIRE_0
add wave -position end sim:/pipemult/SYNTHESIZED_WIRE_1
force -freeze sim:/pipemult/clk1 00000010 0
# ** Error: (vsim-4026) Value "00000010" does not represent a literal of the
enumeration type.
# ** Error: (vsim-4011) Invalid force value: 00000010 0.
#
force -freeze sim:/pipemult/wren 00000010 0
# ** Error: (vsim-4026) Value "00000010" does not represent a literal of the
enumeration type.
# ** Error: (vsim-4011) Invalid force value: 00000010 0.
#
force -freeze sim:/pipemult/datab 00000011 0
run
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result
will be 'X'(es).
# Time: 150 ps Iteration: 0 Instance: /pipemult/b2v_inst/lpm_mult_component
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result
will be 'X'(es).
# Time: 150 ps Iteration: 0 Instance: /pipemult/b2v_inst/lpm_mult_component
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result
will be 'X'(es).
# Time: 200 ps Iteration: 0 Instance: /pipemult/b2v_inst/lpm_mult_component
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result
will be 'X'(es).
# Time: 200 ps Iteration: 0 Instance: /pipemult/b2v_inst/lpm_mult_component
quit
add wave -position end sim:/pipemult/clk1
add wave -position end sim:/pipemult/wren
add wave -position end sim:/pipemult/dataa
add wave -position end sim:/pipemult/datab
add wave -position end sim:/pipemult/wraddress
add wave -position end sim:/pipemult/rdaddress
add wave -position end sim:/pipemult/q
add wave -position end sim:/pipemult/SYNTHESIZED_WIRE_0
add wave -position end sim:/pipemult/SYNTHESIZED_WIRE_1
force -freeze sim:/pipemult/wren 1 0
force -freeze sim:/pipemult/dataa 00000010 0
restart -f
force -freeze sim:/pipemult/clk1 1 0, 0 {50 ps} -r 100
force -freeze sim:/pipemult/wren 1 0
force -freeze sim:/pipemult/dataa 00000010 0
force -freeze sim:/pipemult/datab 00000011 0
run
# GetModuleFileName: The specified module could not be found.
#
#
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result
will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /pipemult/b2v_inst/lpm_mult_component
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result
will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /pipemult/b2v_inst/lpm_mult_component
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result
will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /pipemult/b2v_inst/lpm_mult_component
run
run
run
run
run
force -freeze sim:/pipemult/wren 0 0
force -freeze sim:/pipemult/dataa 11111111 0
force -freeze sim:/pipemult/dataa 11111111 0
restart
force -freeze sim:/pipemult/clk1 1 0, 0 {50 ps} -r 100
force -freeze sim:/pipemult/wren 0 0
force -freeze sim:/pipemult/dataa 11111111 0
force -freeze sim:/pipemult/datab 00000011 0
run
# GetModuleFileName: The specified module could not be found.
#
#
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result
will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /pipemult/b2v_inst/lpm_mult_component
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result
will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /pipemult/b2v_inst/lpm_mult_component
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result
will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /pipemult/b2v_inst/lpm_mult_component
run
run
run
run
run
run
force -freeze sim:/pipemult/wren 1 0
run
run
run
run
force -freeze sim:/pipemult/datab 11111111 0
run
run
run