DIGITAL INTEGRATED CIRCUITS APPLICATIONS LAB 2018

EXPERIMENT
DESIGN 16x4 PRIORITY ENCODER USING 8x3 PRIORITY ENCODER

1 Objective
Design a 16X4 priority encoder using 8X3 priority encoders.

2 Aim
Test the functioning of the 16X4 priority encoder kit which is designed using two 8X3 priority encod

Board Design
a) Design objectives:
i. Use two 8X3 encoders
ii. Implement 16X 4 Encoder
iii. Indicate the binary output bits using LEDs
iv. Indicate Invalid output (When none of the inputs are active)
b) Components:
Technology: There are two choices for selecting the components i) TTL ii) CMOS.
Here TTL ICs are chosen forimplementing. Designs will depend on the technology
Requirement IC/Value Qnty Remark
i. 8X3 encoders 74LS148 2Nos 2X8X3 to 16X4 Encoder
ii. LED --- 5 1: Validity Indication
4: Binary output
iii. Driver for 74LS16 1 Each IC has 6 open Collector (No internal
LEDs collector load) Inverter Drivers
iv. Binary Output 74LS158 1 This IC has 4nos of 2to1 Multiplexers with
Selection common control to select which of the
binary outputs set from 74LS148s as
encoder output.
v. Diodes Any 2 For implementing AND gate (Explained
Switching later)
Diodes
vi. Resistors 220 Ohms 5 LED Current limiting
560 Ohms 1 Part of AND Gate design
Value Not Critical. Should help putting
diodes conducting when forward biased
vii. Shorting Links 2 Pin with 16 One unit for each input. When shorted it
Link provides logic ‘0’ to encoder input and
when open the status at the encoder input
is logic ‘1’ through pull up resistor
viii. Resistors SIP 2 Each SIP has 8 resistors of 10K each with
one end of all resistors connected together.
Please see the circuit for better
understanding

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DIGITAL INTEGRATED CIRCUITS APPLICATIONS LAB 2018

c) Component Details
i. 74LS148: 8 Line to 3 Line Priority Encoder
 Pin numbers are marked inside the chip
diagram
 Pin names are marked outside the chip
diagram
 A0, A1, A2 are binary outputs (A0 is LSB)
 EI is Enable input
 EO is Enable Output meaning outputs are
enabled
 GS is Group select: Meaning that this
indicates that at least one in inputs is active
 EO & GS are active low outputs
 0,1,2,3,4,5,6,7,8 are Encoder Inputs
 VCC .. Connected to5V
 GND … Connected to circuit common point

a) When EI is H, i.e. logic ‘1’, the encoder is disabled. Its outputs are HHH
(A2A1A0)
b) When EI is L, i.e. logic ‘0’, the encoder is enabled and none of the inputs (1-8)
are active (input = H) then also its outputs are HHH (A2A1A0)
c) When EI is L, i.e. logic ‘0’, the encoder is enabled and input ‘0’ is active (input =
L) then also its outputs are HHH (A2A1A0)
d) Hence it may be concluded that the above 3 conditions i.e. i) The chip is not
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enabled ii) none of the inputs active iii) ‘0’ input is active, the outputs shall be
understood along with other two outputs GS and EO
e) GS =EO = ‘1’ for chip not enabled;
f) GS = ‘1’ EO = ‘0’ for chip enabled but none of inputs is active
g) GS = ‘0’ EO = ‘1’ for chip enabled and at least one input is active and only for
this condition, the binary output bits are valid

ii. 74LS158

iii. 74LS16: HEX INVERTER WITH OPEN COLLECTOR

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iv. SIP Resistors

Each of the terminals 2,3,4,5,6,7,8 and 9 is one end of a
resistor. Pin 1 is a common to which the other end of all
resistors is connected. The connection details may be
checked from the circuit diagram
v. 2 Pin Connector and a plug used to short both pins

d) Design Basics:
The design concept is very simple. The design shall have 16 inputs and 4 binary
outputs corresponding to the active input. It shall indicate error state when none of the
inputs is active. The inputs are divided into two groups 1-8 and 9-16. Each group
drives one 8X3 priority encoder inputs. The encoder to which 1-8 inputs are connected
may be called as Enc-1 and the one to which 9-16 inputs are connected may be called
as Enc-2.

A) Choose 8X3 priority encoder that has enable input i.e. when the Encoder is
enabled, it gives following information:
i. A distinct state to indicate that none of the inputs is active
ii. A distinct state that indicates that at least one of the inputs is active

B) Since 8X3 encoder produces only 3 bit code (as it has only 8 inputs) and two such
Encoders are used, one Encoder which is connected to 1-8 inputs (Enc-2) is
always enabled. However Enc-1 is enabled only if none of the inputs of Enc-2 is
active.
C) Here there are two sets of encoded outputs available. One set belongs to Enc-1
and that produces 3 bit code when any of the 1-8 inputs are active and none of 9-
16 inputs are active. When any of the inputs of 9-16 is active, then the second set
of 3 bit code is available from Enc-2.
D) Since the total inputs are 16, the design shall produce 4 bit code and not 2 sets of
3 bit codes. Hence it is essential to design additional circuit that appends 4 th bit
appropriately. This 4th bit, MSB, shall be 0 if any of the 1-8 inputs is active and
hence 0 shall be appended to Enc-1 output. The 4th shall be ‘1’ when any of the 9-
16 inputs is active and hence ‘1’ shall be appended to Enc-2 output
E) The final output shall be only one of the above two 4 bit codes depending on the
active input belongs to Enc-1 or Enc-2.
e) Design:
The design may be divided into 5 sections
i) Input Connections to Enc-1 and Enc-2

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DIGITAL INTEGRATED CIRCUITS APPLICATIONS LAB 2018

ii) Inter Connections between Enc-1 and Enc-2 for appropriately enabling the
encoders
iii) Appending MSB bit and multiplexing the two Enc-1 and Enc-2 outputs to final
output
iv) Connecting LEDs to Mux output
v) Generating Valid / invalid indication

Details of Each of the Sections

i) Input Connections to Enc-1 and Enc-2
Any input will assume logic ‘0’or Logic ‘1’. VCC

The 74LS148 inputs are active LOW i.e’ ‘0’.

1
Hence the input shall normally be ‘1’ and
10K

whenever it is required to be put in active,

then it shall be made ‘0’. Following circuit

9
8
7
6
5
4
3
2
ensures the above.
When the connector terminals are open, then I0 10
D0 Q0
9
11 7
D1 Q1
D0 (Pin 1) will be Logic ‘1’ (Not Active).
12 6
13 D2 Q2
1 D3 15
2 D4 EO 14
When the connector terminals are short 3
4
D5
D6
GS

D7
circuited (by putting shorting link), D0 (Pin 1) 5
EI
U54
74148
will be at Logic ‘0’ (Active).

ii) Inter Connections between Enc-1 and Enc-2

As explained above Enc-2 is always active. When none of the inputs (9-16) is
selected, then Enc-1 shall be enabled. Enabling is done by connected EI input to
logic ‘0’. Following circuit ensures this.
Input-1 10 9 Input-9 10 9
Input-2 11 D0 Q0 7 Input-10 11 D0 Q0 7
Input-3 12 D1 Q1 6 Input-11 12 D1 Q1 6
Input-4 13 D2 Q2 Input-12 13 D2 Q2
Input-5 1 D3 15 Input-13 1 D3 15
Input-6 2 D4 EO 14 Input-14 2 D4 EO 14
Input-7 3 D5 GS Input-15 3 D5 GS
Input-8 4 D6 Input-16 4 D6
D7 Enc-1 D7 Enc-2
5 5
EI 74148 EI 74148

iii) Appending MSB bit and multiplexing

Each of the encoders produce binary output corresponds to its prioritized active
input, when it is enabled. i.e. if more than one input is active then it produces
output corresponding to its highest input. For ex. If input-2 and Input-5 are active at
the same time, then encoder produce binary output corresponds to Input-5 i.e.
(100). Assuming Input -5 is active on Enc-1 and later Input-13 is active on Enc-2,
then output code produced by both encoders is same (100) as the inputs are
actually connected to D4 on both ENC-1as well as Enc-2. However the required
code shall be (0100) when Input-5 is active and it shall be (1100) when Input-13 is
active. This additional MSB bit shall be produced externally.

Since each of the encoders produces their own 3 bit binary code, when enabled, it
is required to output the code only from the enabled encoder and then append the

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bit appropriately. This is achieved by using 4 nos of 2-1 multiplexers (74LS158)

and its circuit connections are shown below.

By examining MUS input lines, they are divided as ‘A” group and ‘B’ group, each
group has 4 inputs. The group is selected by A’/B select (address ) line. This select
line is driven by GS output of Enc-1. This pin is ‘0’ when the 3 bin binary output
corresponds to any of its is active. Otherwise GS output is ‘1’. So, when this GS is
10
11 D0 A0
9
7
2
5
‘0’ the Mux will select A group and
1A 1Y
4
7
12
13
1
D1
D2
D3
A1
A2
6

15
11
14 otherwise it selects the ‘B’ group inputs as
2A
3A
4A
2Y
3Y
4Y
9
12

2
3
D4
D5
EO
GS
14 3
6 Mux outputs. Hence all A group pins
1B
4 D6 10 2B

5
D7 Enc-1
VCC
13 (1A,2A,3A) are connected to Enc-1 outputs
3B
4B
EI 1
74148
15 (A0,A1,A2) and B group inputs (1B,2B,3B)
A/B
G 74LS158

are driven by Enc-2 outputs (A0,A1,A2)

10
D0 A0
9 correspondingly. Now the 4th bits to be
appended is that 4A shall be ‘0’ when Enc-
11 7
12 D1 A1 6
13 D2 A2

1 outputs are selected and 4B shall be ‘1’

1 D3 15
2 D4 EO 14
3 D5 GS
D6 Enc-2
4

5
D7 when Enc-2 outputs are selected to Mux
EI 74148
outputs. This done by connecting 4A to
GND (‘0’) ans 4B to VCC (‘1’) directly.

iv) Connecting LEDs to Mux output

The output bit status is indicated using LED and hence 4 bits are indicated by
means of 4 LEDs. Let us assume that when bit is = 0, then LED is OFF and when
the bit is ‘1’, the LED is ON. However since the available Binary code output bits
from 74LS148 are inverted, the LED states have to be inverted, meaning when
output bit is ‘0’, LED shall be ON and OFF when the bit is ‘1’. Considering that the
used LED driver is a NOT gate, the following circuit helps controlling the LED as
above.
220E
BInary BIT
VCC
7416
1

Binary 7416 LED Remark

Bit output status
0 1 OFF
No current flows
1 0 ON
Assuming the drop across the diode (LED) is
about 1V (Depend on the LED colour), and VCC
= 5V, the Current through the LED is
approximately = (5-1)/220 = 18mA.
Hence to represent 4 binary bits, 4 circuits as shown above, are required.

Each output of MUX is connected to a driver-inverter (74LS16). It is important to

note that the encoder produces inverted binary code.

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Binary Code Binary Code

Active Input Active Input
A2 A1 A0 A2 A1 A0
0 1 1 1 4 0 1 1
1 1 1 0 5 0 1 0
2 1 0 1 6 0 0 1
3 1 0 0 7 0 0 0

Futher MuX also inverts its inputs and hence MUX outputs are straight binary.

R13 4
2 4 7416
5 1A 1Y 7
11 2A 2Y 9
14 3A 3Y 12 R14
220E 5
Data 0
4A 4Y
3 U54 7416
6 1B
10 2B R15
220E 6
Data 0
13 3B 7416
4B
1
15 A/B R16
220E 7
Data 0
G 74LS158 7416

220E Data 0
VCC

v) Generating Valid / invalid indication

It may be noted that it is important to indicate that invalid state i.e. none of the 16
inputs are active. This is derived by considering GS outputs of both converters.

Inputs GS(1) GS(2) LED Remark

(Enc-1) (Enc-2) status
output output
None of 1-16 is active 1 1 ON Invalid output
At least one of 1-8 is active 0 1 OFF Valid Output
At least one of 9-16 is active 1 0 OFF Valid Output
At least one of 1-8 & 9-16 is 0 0 OFF Valid Output
active
The above table indicates that the function is only truth table of AND gate. The
AND gate and its LED drive is implemented as shown below.
560E 220E Validity
VCC VCC
7416
1

GS(1)

GS(2)

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f) Circuit Diagram
VCC

1
R5
10K
VCC
R9 R7
560E 220E Validity
13 U3F 12
VCC
2
3
4
5
6
7
8
9
7416
D7 D8
DIODE DIODE

I0 10
D0 A0
9 2
1A 1Y
4
11 7 5 7
I1 12 D1
D2
A1
A2
6 11 2A
3A
2Y
3Y
9
13 14 12
I2 1 D3
D4 EO
15 4A 4Y
2 14 3 U2
I3 3 D5 GS 6 1B

9
4 D6 10 2B
I4 D7
VCC
13 3B
4B
U3A U3B U53C U3D
5 U1 7416 7416 7416 7416
I5 EI 74148 1
A/B
15
I6 G 74LS158

8
I7
R1 R2 R3 R4
I8 10
D0 A0
9 220E 220E 220E 220E
11 7
I9 12 D1
D2
A1
A2
6
13
I10 1 D3
D4 EO
15
2 14
I11 3 D5
D6
GS
4
I12 D7 U4 Data 3 Data 2 Data 1 Data 0
5
I13 EI 74148

I14 VCC

I15
9
8
7
6
5
4
3
2

R6
10K
1

VCC

g) Operating Procedure:
The photograph of Kit’s front
plate is shown here. On to the
left 16 2-pin connectors are
placed into 2 groups. Top 8
(I0-I7) corresponding to (1-8)
mentioned in the text and
bottom 8 (I8-I15)
corresponding to (9-16)
mentioned in the text. When a
connector is open, then the
respective input is ‘1’. When
connector pins are shorted
using short link, then the
respective input is ‘0’.

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DIGITAL INTEGRATED CIRCUITS APPLICATIONS LAB 2018

i. When all connector are in open, the VALID LED is ON, indicating the output
is invalid.
ii. When any of the connector is shorted, Valid LED goes OFF indicating the
Output indicated by LED (0: OFF, 1: ON) is valid.
iii. Now place shorting links one more than on connector.
iv. Note that the data displayed on LEDs indicates the binary code of the
highest number of input for which the connector is shorted with shorting link.
v. Verify the binary code for each of the cases.

h) Conclusions: The design explained above is not unique. The design depends on
the chosen encoder and its functional pins. Even when CMOS Ics are employed,
74LS16 can still be employed to drive the LEDs as the 74LS16 inputs are
compatible with both TTL and CMOS. The current limiting resistors’ value
depends on the LED colour. The resistor value so chosen may vary and lower the
value higher the brightnessand vice versa. However higher the current will reduce
the LED life. Student may explore alternate design of interfacing the encoder
output sets to LEDs, instead of using MUX. Student shall study implementing the
same with 74147 instead of 74148 even though 74147 is not apt for this
experiment.

i) Viva Questions:

9 DESIGN & MANUAL: Dr. P. Sudhakara Rao [VMTW]