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Verilog Code and Testbench

This Verilog code defines a 4-input multiplexer module (mux4) that selects one of four input bits based on a 2-bit selector. A testbench module (mux_tb) is also defined to test the mux4 module by applying sample input and selector values and observing the output.

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Sourabh
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103 views1 page

Verilog Code and Testbench

This Verilog code defines a 4-input multiplexer module (mux4) that selects one of four input bits based on a 2-bit selector. A testbench module (mux_tb) is also defined to test the mux4 module by applying sample input and selector values and observing the output.

Uploaded by

Sourabh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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VERILOG CODE:

module mux4(i,s,o);

input[3:0] i;

input[1:0] s;

output o;

reg o;

always @(i or s)

begin

case(s)

2'b00:o=i[0];

2'b01:o=i[1];

2'b10:o=i[2];

2'b11:o=i[3];

default:o=0;

endcase

end

endmodule

VERILOG TESTBENCH:

module mux_tb;

reg[3:0] i;

reg[1:0] s;

wire o;

mux4 uut (.i(i),.s(s),.o(o));

initial begin

#10 i=4 'b0010;

#10 s=2 'b10;

end

endmodule

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