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University of Engineering & Technology Taxila Vlsi Lab Lab No. 3 Report By: Zubair Khalid (15-CP-41) To: Sir Waqar Dated: 5 April 2018

This lab report summarizes Zubair Khalid's work in VLSI Lab 3. The objectives were to implement CMOS logic circuits using transmission gates. Tasks included simulating a transmission gate XOR, 4x1 multiplexer, and 1-bit full adder. Code, logic diagrams, and simulations are provided for each circuit implemented using transmission gates at the switch level in Verilog HDL.

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32 views5 pages

University of Engineering & Technology Taxila Vlsi Lab Lab No. 3 Report By: Zubair Khalid (15-CP-41) To: Sir Waqar Dated: 5 April 2018

This lab report summarizes Zubair Khalid's work in VLSI Lab 3. The objectives were to implement CMOS logic circuits using transmission gates. Tasks included simulating a transmission gate XOR, 4x1 multiplexer, and 1-bit full adder. Code, logic diagrams, and simulations are provided for each circuit implemented using transmission gates at the switch level in Verilog HDL.

Uploaded by

MohammadZubairKhalid
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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University of Engineering & Technology

Taxila

VLSI LAB
Lab No. 3 Report

By: Zubair Khalid (15-CP-41)


To: Sir Waqar
Dated: 5th April 2018
INTRODUCTION
CMOS is the dominant digital logic family used with integrated circuits. By definition, CMOS is a
complementary connection of an NMOS and a PMOS transistor, MOS transistors can be
considered to be electronic switches that either conduct or are open. By specifying the
connections among MOS switches, the designer can describe a digital circuit constructed with
CMOS. This type of description is called switch-level modeling in Verilog HDL.

TRANSMISSION GATE
A transmission gate, or analog switch, is defined as an electronic element that will selectively
block or pass a signal level from the input to the output. This solid-state switch is comprised of a
pMOS transistor and nMOS transistor. The control gates are biased in a complementary manner
so that both transistors are either on or off.

When the voltage on node A is a Logic 1, the complementary Logic 0 is applied to node active-
low A, allowing both transistors to conduct and pass the signal at IN to OUT. When the voltage
on node active-low A is a Logic 0, the complementary Logic 1 is applied to node A, turning both
transistors off and forcing a high-impedance condition on both the IN and OUT nodes. This
high-impedance condition represents the third "state" (high, low, or high-Z).

OBJECTIVES
• Implementing CMOS logic circuits at switch level using transmission gates.

LAB TASKS
Performed Lab tasks and their results are shown below.

TASK 1: SIMULATE TRANSMISSION GATE BASED XOR


Code:

1
VLSI Lab Report 3 Zubair Khalid (15-CP-41)

CMOS Logic:

Simulation:

Code:

CMOS Logic:

2
VLSI Lab Report 3 Zubair Khalid (15-CP-41)

Simulation:

TASK 2: SIMULATE TRANSMISSION GATE BASED 4X1 MUX


Code:

Cmos Logic:

Simulation:

3
VLSI Lab Report 3 Zubair Khalid (15-CP-41)

TASK 3: SIMULATE TRANSMISSION GATE BASED 1-BIT FULL ADDER


Code:

Gate Logic:

Simulation:

SUMMARY
In this lab session, transmission gates were used to implement circuits at switch level using CMOS
logics.

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