FPGA and its applications

Prepared by:

Dr. Amit Joshi

Assistant Professor,
MNIT, Jaipur

3/30/2018 Digital System Design & FPGAs 1

 Outline
 Introduction to PLD

 Basics of PLD

 What is FPGA?

 FPGA basic structure

 FPGA Implementation

 FPGA Applications

 Summary

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 Introduction to PLD
 ASIC (Application Specific Integration Circuit)
Circuit)::
- Fixed functionality
- Digital IC 74
74xx
xx series

 Concept of PLD (Programmable Logic Device)

Device)::
 It is possible to manufacture chips that contain relatively large amounts of
logic circuitry with a structure that is not fixed means we can modify (to
some extent) according to our requirement
requirement..
 Such chips are introduced in 1970 and are called PROGRAMMABLE LOGIC
DEVICES..
DEVICES

 Evolution of PLD
- PROM ,PLA ,PAL, CPLD, FPGA
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 Advantages of PLD

 Advantage of PLD

– Ease of design changes

– Flexibility
– No ASIC re-re-spin risk
– Easy & faster design Implementation
– Shorter time to market

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 Types of PLD
 There are mainly four types of PLD
1) SPLD (Simple Programmable Logic Device)
2) CPLD (Complex Programmable Logic Device)
3) FPGA (Filed Programmable Gate Array)

- ASIC (Application Specific Integrated Circuit)

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 SPLD vs FPGA
 SPLD
- Most basic & least expensive form of programmable logic
- It contains several configurable logic gates, programmable
interconnection, FFs etc.

 FPGA
- Millions of gates
- Fast and reprogrammable
- Many things can be done parallel for real time
- Gate level programming

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 Outline
 Introduction to PLD

 Basics of PLD

 What is FPGA?

 FPGA basic structure

 FPGA Implementation

 FPGA Applications

 Summary

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 Programmable Logic Devices

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 Programmable Array Logic

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 Programmable Array Logic
w= ABC’ + A’B’CD’
X= A + BCD
Y=A’B + CD + B’D’
Z= ABC’ + A’B’CD’ + AC’D’ + A’B’C’D
= W + AC’D’ + A’B’C’D

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 Programmable Logic Array
F1= AB’ + AC +A’BC
F2= ( AC + BC )’

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 Why CPLD?
 CPLD (Complex Programmable Logic Devices)
Features:

 Low development cost

 Faster time to market
 Reduced PCB area
 Ease & Simple way to implement a design

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 Structure of CPLD

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 CPLD (Complex Programmable Logic Devices)
 Advantages :

- Simplified design process.

- Mostly standard architecture and easy to use.
- Low cost design and development tool
- Deterministic, uniform delays and predictable timing.

 Disadvantages :

- Low to moderate density

- Inflexible architecture

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 Outline
 Introduction to PLD

 Basics of PLD

 What is FPGA?

 FPGA basic structure

 FPGA Implementation

 FPGA Applications

 Summary

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 What is FPGA?
 FPGA stands for Field Programmable Gate Array
 More Gate count to support complex logic Circuit
 It does not contain AND and OR planes.
 They have
- Logic blocks which are arranged in 2-
2-D.
- Routing channels, programmable switches.
 Mostly LUT are there to implement logic.
 LUTs of various sizes can be created, they are limited by
number of inputs.

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 Purpose of FPGA
 FPGA is programmable ICs

 Configurable i.e. programmable

- Logic blocks

- Inter connects

 The term “Field programmable” means programming in the

particular field where device function can be modified as per
logic circuit

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 FPGA

 Inexpensive, easy realization of logic network in the form of

hardware.. Easy such as software !!!!!
hardware
 Hardware of FPGA contains Logic gates, RAM and others
(such DCM)
 Fast implementation where so many thing are working parallel
 Gate level working i.e. smallest level of circuit with building
complex systems

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 Vendors of FPGA
 Mainly Xilinx, Altera and Actel
 Differences of FPGA in terms of
- Physical means for implementation programmability
- Inter connection arrangement
- Basic function of logic blocks
- LUTs input

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 Outline
 Introduction to PLD

 Basics of PLD

 What is FPGA?

 FPGA basic structure

 FPGA Implementation

 FPGA Applications

 Summary

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 FPGA structure

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 Biggest FPGA producers are :
Company Percentage of Total Revenue
Total
Xilinx 49% 2.4 Billion $
Altera 40% 1 Billion $
Quick Logic 1% 26 Million $
Micri Semi 4% 207 Million $
Lattice Semi 6% 297 Million $

- Xilinx and Altera have 89% of the Market

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 FPGAs
Summary of Commercially Available FPGAs

Company General Logic Block Programming

Architecture Type Technology

Xilinx Symmetrical Array Look-up Table Static RAM

Actel Row-based Multiplexer-Based Anti-fuse

Altera Hierarchical-PLD PLD Block EPROM

Plessey Sea-of-Gates NAND-gate Static RAM

PLUS Hierarchical-PLD PLD Block EPROM
AMD Hierarchical-PLD PLD Block EEPROM
QuickLogic Symmetrical Array Multiplexer-Based Anti-fuse

Algotronix Sea-of-gates Multiplexers & Basic Gate Static RAM

Concurrent Sea-of-gates Multiplexers & Basic Gate Static RAM

Crosspoint Row-based Transistors Pairs & Anti-fuse

Multiplexers

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 XILINX FPGA
ARCHITECTURE

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 Elements of FPGA
 Various types of FPGA such as Virtex
Virtex--II, Sparten 3E, Sparten
3A, Sparten 6, Kintex 7, Artix 7 etc..

 All Xilinx FPGA contains

1) CLB (Configurable Logic Block)
2) IOB (Input output Buffer)
3) PI (Programmable Interconnection)
4) RAM blocks
5) Other Resources - three state buffers, Global clock buffers,
Dedicated Multiplier

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 Simplified CLB Structure

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 LUT--Based Logic Cells
LUT

1. LUT is a memory which contains the truth

truth--table of a function

2. LUT with n inputs can implement any n-bit function

3. Truth--table is placed in LUT during the FPGA programming

Truth

4. LUTs are implemented with SRAM

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 Example: 4-input AND
gate
A B C D O
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0 A,B,C and D are act as address pointer
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
Output can be present value or previous store
1 1 0 1 0 value
1 1 1 0 0
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1 1 1 1 1 Digital System Design & FPGAs
 Example:

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 Example
 x=(a & b)|((not b) & c);

Truth Table
SRAM Cell (LUT)

a b c x
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 1
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1 1 1 1 Digital System Design & FPGAs 30
 Programmability
 Three Methods
1. SRAM Based – Xilinx, Altera
2. Antifuse Technology - Actel
Actel,, Quicklogic
3. EPROM/EEPROM

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 SRAM BASED PROGRAMMING
 FPGA Connections –
1. Pass Transistors

2. Transmission Gates

3. Multiplexer

 Making or Breaking cross point connections.

 SRAM defines function of logic block.
 In programming, SRAM cells are arranged in shift register manner in
order to configure using Digital
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 SRAM Programming Technology
 Employs SRAM (Static RAM) cells to
control pass transistors and/or
transmission gates
 SRAM cells control the configuration of
logic block
 Volatile
 Needs an external storage

 Needs a power-
power-on configuration
mechanism
 In
In--circuit re-
re-programmable
 Lesser configuration time
 Occupies relatively larger area
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 Interconnection Network

SRAM CELL is used to

program 0 or 1 at FET
Level.
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 SRAM CELL is used to program 0 or
1 at inputs. So it decides function of
CLB

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 Antifuse Technology
 One Time Programming
 Invented at Stanford and developed by Actel
 Actel PLICE (Programmable Logic Interconnect Circuit Element)
structure
 Anti--fuse resides in a high
Anti high--impedance state. Can be programmed
into low impedance or "fused" state.
 Less expensive than the RAM technology

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 Comparison of two programming technology
Antifuse Technology SRAM technology

- It occupies less area - it has larger area

- Delay less , High Speed - Delay is high

Why to go for reprogramability !!!

To have interface between Microprocessor and DSP for
communication for different data rates

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 Arithmetic Resources in FPGA
1. Adder
2. Multiplier
3. Counter

 Special circuitry to speed up operation

 Dedicated Carry Logic/ XOR
 ASIC is faster compare to FPGA. FPGA has to speed
up for improvement therefore arithmetic resources

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 FPGA
 Advantage:----
Advantage: ----
- Ideal for customized design
- High complexity , density and reliability
- Low cost, power consumption, small physical size
- Fast time to market

 Disadvantage:----
Disadvantage:----
- long delay in design and testing

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 Comparison Of CPLD & FPGA
CPLD FPGA
 Logic gates are less in number  Several millions of gates

 Number of i/o pins are  Number of i/o pins are less

significantly higher than CPLD
 CPLD does not require any  It requires one or more PROM
external memory store depend on the size
program
 CPLD are smaller than FPGA  FPGA are larger than CPLD

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 FPGA (Field Programmable Gate Array)

 What are the limitations of FPGA?

 Existence of programmable switches.
 Of course they provide programmable feature to
user but, they consume lot of real estate on the chip.
 They make reduce the speed of operation.

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 Where do FPGA lies?
Types of IC

PLDs ASICs
-SPLD, CPLD - Gate Array, structured Array,
Standard cell, Full custom
- Features - Features
F No Reconfigurable,
Highly Reconfigurable,
P Time Consuming
Faster Design Time expensive
Don’t support complex logic G
Support complex logic
A
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 Introduction to Gate Array
 Gate array is a prefabricated silicon chip circuit.
circuit.

 Gate array is an IC chip on which gates are placed in

a matrix form

 Gate array contains basic cell as most important

element.. It contains (either CMOS,NAND,NOR or
element
any other active device).
device).

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 Gate Array

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 Gate Array Design

 Gate array implementation requires a two step manufacturing

process::
process
- The first phase, which is based on generic (standard) masks,
results in an array of uncommitted transistors on each GA
chip..
chip
- These uncommitted chips can be stored for later
customization, which is completed by defining the metal
interconnects between transistors of arrays
arrays..

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 Designing Approaches

VLSI design

Full custom (geometry &

Semi custom
placement of every transistor (such as std cell
design or FPGA)
can be optimized individually)

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Full custom design:
Requires longer time till design maturity
Adjustment flexibility of almost every aspect improves
the circuit performance
High performance but large cost in terms of design cycle
time.
Semi custom design:
Requires less time till design maturity
In early stage, performance is better to full custom
design because, some components are optimized. But, less
opportunity for improvement in the circuit performance.
Lesser performance but shorter design cycle time.

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 Outline
 Introduction to PLD

 Basics of PLD

 What is FPGA?

 FPGA basic structure

 FPGA Implementation

 FPGA Applications

 Summary
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 Xilinx ISE Design Flow

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 Introduction to Xilinx ISE
 ISE stands for Integrated Software Environment
 All tools are integrated as collection in one GUI
 Tools for Xilinx ISE:
a) HDL Complier/Simulator - Xilinx ISE sim sim,, Modelsim
b) Synthesis - XST
c) Core generator & Arch Wizard – Coregen
d) Pin out & Area Constraint Editor - PACE
e) Implementation – Translate/MAP/PAR
f) Device Configuration - IMPACT

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 Xilinx Design Flow
 Design Entry : (ISIM)
- Input file can be ..sch
sch,, .v, ..vhd
vhd
 Synthesis : (XST)
- Produces the net list file starting from an HDL/schematic file
description
- Converts .v,. vhd
vhd,, ..sch ---- .NGC file (netlist
sch ---- (netlist file with
constraint)
 Translate : (XST)
- Read all input design file then write result into on emerged file
that describes logic and constraint
- Converts .NGC file ---  .NGD (Native Generic Database)
---
file, this file describes logic design to Xilinx primitives

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 Xilinx Design Flow
 Mapping – (XST)
- maps logic on the device components
- Takes the netlist and logic elements into CLBs and IOBs
- Converts .NGD --  .NCD (Native Circuit Description) &
--
.PCF (Physical Constraint File)
- .NCD file represents the physical circuit (Which CLBs, IOBS
and interconnections) description of the input design as applied
to specific design
- . PCF has constraint according to device dependent

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 Xilinx Design Flow
 Place & Route – (XST)
- Determines the placement of cells and the routing between
cells

 Bit stream generation –

- Is a stream of data that contains the location information for
logic and devices
- Actual bit stream to be sent or to be load on FPGA

 Configuration/ Programming (IMPACT)

- Download a bit file into FPGA using JTAG port

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 Translation
Synthesis

Circuit netlist Timing Constraints

Constraint Editor
Electronic Design Native
Interchange Format Constraint
File
EDIF NCF UCF User Constraint File

Translation

NGD Native Generic Database file

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 Sample UCF File
NET "clock" LOC = "P8";
NET "control<0>" LOC = "K4";
NET "control<1>" LOC = "K3";
NET "control<2>" LOC = "K2";
NET "reset" LOC = "E11";
NET "segments<0>" LOC = "R10";
NET "segments<1>" LOC = "P10";
NET "segments<2>" LOC = "M11";
NET "segments<3>" LOC = "M6";
NET "segments<4>" LOC = "N6";
NET "segments<5>" LOC = "T7";
NET "segments<6>" LOC = "R7";
"R7";

set_property -dict { PACKAGE_PIN J15

IOSTANDARD LVCMOS33 } [get_ports
[get_ports { A
}]; #IO_L24N_T3_RS0_15 Sch
Sch=
=sw
sw[0]
[0]
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 Circuit netlist

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 Mapping
LU
T0
LU
T4
LU
T1 FF
LU 1
T5
LU
T2
FF
LU 2
T3

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 Placement: Select CLBs

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 FPGA

Placing CLB SLICES

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 Routing: Select path

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 FPGA Generic Flow
 Design Entry:
– Create your design files using:
• schematic editor or
• hardware description language (Verilog
(Verilog,,
VHDL)

 Design “implementation” on FPGA:

– Partition, place, and route to create bit-
bit-
stream file
–Converts HDL to format which FPGA
understands

 Design verification:
– Use Simulator to check function,
– Load onto FPGA device (cable connects PC
to development board)-
board)- Logic Analyzer

 check operation at full speed in real

environment.
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 FPGA Implementation
 Partition: Converts logic blocks into n –input CLB blocks
 Placement : Choosing the appropriate CLBs
 Routing : Interconnection of CLBs
 Translation : For design entry of 4 FFs logic to number of CLB
.i.e if CLB has two FFs then divide the logic in 2 CLBs

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 ASIC vs FPGA vs Microprocessor
Performance NREs Unit Cost Time To Market
(Speed) (TTM)
ASIC ASIC FPGA ASIC

FPGA FPGA Microprocessor FPGA

Microprocessor Microprocessor ASIC Microprocessor

Microprocessors are more complex than FPGAs

Microprocessors have fixed instructions while FPGAs
don’t

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 COMPARISION

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 FPGA Application
 In DSP ,software defined radio, defense system, aerospace
 Speech recognition/synthesis/Translator

 Computer hardware simulation

 Image/ Video processing

 Gate array prototyping

 Biomedical application/ healthcare

 Data Security algorithms

Many more

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 Outline
 Introduction to PLD

 Basics of PLD

 What is FPGA?

 FPGA basic structure

 FPGA Implementation

 FPGA Applications

 Summary
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 Latest 7 series FPGA Family
 There are mainly three 7 series family:
1) Artix 7: Lowest Price & power
2) Kintex 7: Best Price & Performance
3) Virtex 7: High Performance & Capacity
 Same CLB architecture structure
 High Speed and low power consumption
 Reduced power almost 50%

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 Comparison of 7 Series FPGA
Family

 Artix-7 cost is 320 USD, while Kintex 7 is

Artix-
1250 USD and Virtex 7000 USD, Zynq ???.
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 Xilinx 7 Series Family

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 Virtex 7 Series

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 Strong Focus on Power Reduction

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 7 Series FPGA Applications
 The Artix
Artix--7 family is ideally suited to demanding handheld
applications including portable ultrasound machines, digital
camera control and software-
software-defined radio.
radio.

 The low-
low-power, cost-
cost-effective Kintex
Kintex--7 family provides a perfect
balance of features and performance, making it ideal for wireless
LTE infrastructure equipment, LED backlit and 3D digital video
displays, medical imaging and avionics imaging systems
systems..

 The highest in system performance, the Virtex-

Virtex-7 family useful in
optical networks, radar and ASIC emulation.
emulation.
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7 Series FPGA Family Architecture

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 7 Series FPGA Family Layout

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 Clock Regions and I/O Banks

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 Clock Management

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 CLB Structure

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 Slices in CLB

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 Slice Resource

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 Block RAM

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 DSP Slice

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 Clocking Resources

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 XADC: Dual 12-
12-Bit 1-
1-MSPS
ADCs

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 I/O Composition

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 Zynq Board

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 FPGA Technology

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 Cost, Power and Performance

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 Where Can I Learn More?

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 References
 Xilinx website
 Advanced FPGA Design: Architecture,
Implementation, and Optimization by Steve Kilts
 Digital Systems Design with FPGAs and CPLDs
by Ian Grouts

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 THANK YOU

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