Data Sheet P2504BDG
Data Sheet P2504BDG
Data Sheet P2504BDG
D
PRODUCT SUMMARY
1. GATE
V(BR)DSS RDS(ON) ID
G 2. DRAIN
40V 25mΩ 12A 3. SOURCE
S
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted)
PARAMETERS/TEST CONDITIONS SYMBOL LIMITS UNITS
Junction-to-Case RθJc 3 °C / W
Junction-to-Ambient RθJA 75 °C / W
1
Pulse width limited by maximum junction temperature.
Duty cycle ≤ 1%
2
JAN-17-2005
1
NIKO-SEM N-Channel Logic Level Enhancement P2504BDG
Mode Field Effect Transistor ( Preliminary ) TO-252 (DPAK)
Lead-Free
DYNAMIC
Continuous Current IS 12
A
Pulsed Current 3 ISM 40
Forward Voltage1 VSD IS = IS, VGS = 0V 1.2 V
Reverse Recovery Time trr IF = 5 A, dlF/dt = 100A / µS 14.5 nS
Reverse Recovery Charge Qrr 7.2 nC
1
Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2%.
2
Independent of operating temperature.
3
Pulse width limited by maximum junction temperature.
JAN-17-2005
2
NIKO-SEM N-Channel Logic Level Enhancement P2504BDG
Mode Field Effect Transistor ( Preliminary ) TO-252 (DPAK)
Lead-Free
Body Diode Forward Voltage Variation with Source Current and Temperature
100
V GS = 0V
T A = 125°C
10
Is - Reverse Drain Current(A)
25°C
1
0.1 -55°C
0.01
0.001
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
VSD - Body Diode Forward Voltage(V)
JAN-17-2005
3
NIKO-SEM N-Channel Logic Level Enhancement P2504BDG
Mode Field Effect Transistor ( Preliminary ) TO-252 (DPAK)
Lead-Free
JAN-17-2005
4
NIKO-SEM N-Channel Logic Level Enhancement P2504BDG
Mode Field Effect Transistor ( Preliminary ) TO-252 (DPAK)
Lead-Free
mm mm
Dimension Dimension
Min. Typ. Max. Min. Typ. Max.
G 6 6.2 N
A
B
E
C
H G
L
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NIKOS
M
J
I
JAN-17-2005
5