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Sequential Circuit Design: Questions 1 - 3 Are Optional. Questions 4 - 10 Are Mandatory

This document contains instructions for a logic design assignment involving sequential circuit design using different types of flip flops. Students are asked to complete 10 problems designing counters and circuits from state diagrams using D, T, JK, and SR flip flops. The problems include designing a decade counter, odd value counter, and up/down counters with additional output conditions.

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0% found this document useful (0 votes)
95 views2 pages

Sequential Circuit Design: Questions 1 - 3 Are Optional. Questions 4 - 10 Are Mandatory

This document contains instructions for a logic design assignment involving sequential circuit design using different types of flip flops. Students are asked to complete 10 problems designing counters and circuits from state diagrams using D, T, JK, and SR flip flops. The problems include designing a decade counter, odd value counter, and up/down counters with additional output conditions.

Uploaded by

deena
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Second Year – SE

Course Teacher: Zareen Sadiq

CS-251 LOGIC DESIGN & SWITCHING THEORY

Sequential Circuit Design


Questions 1 – 3 are optional. Questions 4 -10 are mandatory.

1. Design sequential circuit for the following state diagram. Map all unused states to don’t cares. Use:
a. D flip flops
b. T flip flops

2. Design sequential circuit for the following state diagram using SR flip flops. Map all unused states to don’t cares.

3. Design decade counter. Map all unused states to don’t cares. Use:
a. T flip flops
b. JK flip flops

4. Design decade counter using JK flip flop. Map all unused states to 0.

5. Design odd value counter. Map all unused states to don’t cares. Use:
a. T flip flops
b. JK flip flops

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6. Design the following counter using T flip flops. Map all unused states to don’t cares.

7. Design the following counter using T flip flops.

8. Design a 3-bit up/down counter. Use any flip flop.

9. Design a 3-bit up/down even sequence counter. Use any flip flop.

10. Design a 2-bit up/down counter which produces an output 1 if the next/settled state is an even number and 0 otherwise.

___________________________________________ ☺ ______________________________________________________

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