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Experiment Number: 5: To Perform The Functional Verification of The CMOS Inverter Through Schematic Entry

The document describes an experiment on simulating and verifying a CMOS inverter circuit. The objectives are to draw the schematic using Cadence S-Edit, perform transient analysis to obtain the output waveform, and extract the SPICE code. Facilities required include Cadence S-Edit software. The procedures include drawing the schematic, simulation, and code extraction. Theory on CMOS inverter operation is provided. Schematic and output are shown verifying successful simulation and functionality of the CMOS inverter.

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rameshdurairaj
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92 views

Experiment Number: 5: To Perform The Functional Verification of The CMOS Inverter Through Schematic Entry

The document describes an experiment on simulating and verifying a CMOS inverter circuit. The objectives are to draw the schematic using Cadence S-Edit, perform transient analysis to obtain the output waveform, and extract the SPICE code. Facilities required include Cadence S-Edit software. The procedures include drawing the schematic, simulation, and code extraction. Theory on CMOS inverter operation is provided. Schematic and output are shown verifying successful simulation and functionality of the CMOS inverter.

Uploaded by

rameshdurairaj
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Dr NNCE ECE/VI-SEM VLSI DESIGN LAB-LM

Experiment Number: 5
Title of the experiment : CMOS INVERTER

Date of the experiment :

OBJECTIVE OF THE EXPERIMENT

To perform the functional verification of the CMOS Inverter through schematic entry.
FACILITIES REQUIRED AND PROCEDURE

a) Facilities required to do the experiment

S.No. SOFTWARE REQUIREMENTS Quantity


1 S-Edit using cadance Tool.

b) Procedure for doing the experiment

S.No Details of the step


1 Draw the schematic of CMOS Inverter using S-edit.
2 Perform Transient Analysis of the CMOS Inverter.
3 Obtain the output waveform from W-edit
4 Obtain the spice code using T-edit.

c) THEORY:
Inverter consists of nMOS and pMOS transistor in series connected between VDD and GND.
The gate of the two transistors are shorted and connected to the input. When the input to the inverter A =
0, Nmos transistor is OFF and pMOS transistor is ON. The output is pull-up to VDD. When the input A
= 1, nMOS transistor is ON and pMOS transistor is OFF. The Output is Pull-down to GND.

28
Dr NNCE ECE/VI-SEM VLSI DESIGN LAB-LM

SCHEMATIC DIAGRAM:

RESULT

Thus the functional verification of the CMOS Inverter through schematic entry.and the
output also verified successfully.

29
Dr NNCE ECE/VI-SEM VLSI DESIGN LAB-LM

Experiment Number: 6
Title of the experiment : UNIVERSAL GATES

Date of the experiment :

OBJECTIVE OF THE EXPERIMENT


To perform the functional verification of the universal gate through schematic entry.
FACILITIES REQUIRED AND PROCEDURE

a) Facilities required to do the experiment

S.No. SOFTWARE REQUIREMENTS Quantity


1 S-Edit using CadanceTool. 1

b) Procedure for doing the experiment

S.No Details of the step


1 Draw the schematic of CMOS Inverter using S-edit.
2 Perform Transient Analysis of the CMOS Inverter.
3 Obtain the output waveform from W-edit.
4 Obtain the spice code using T-edit

30
Dr NNCE ECE/VI-SEM VLSI DESIGN LAB-LM

NAND GATE

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Dr NNCE ECE/VI-SEM VLSI DESIGN LAB-LM

NORGATE

RESULT:

Thus the functional verification of the NAND& NOR Gate through schematic entry.and
the output also verified successfully

32
Dr NNCE ECE/VI-SEM VLSI DESIGN LAB-LM

Experiment Number: 7
Title of the experiment : DIFFERENTIAL AMPLIFIER
Date of the experiment :
OBJECTIVE OF THE EXPERIMENT

To calculate the gain, bandwidth and CMRR of a differential amplifier through schematic entry.

FACILITIES REQUIRED AND PROCEDURE

a) Facilities required to do the experiment

S.No. SOFTWARE REQUIREMENTS Quantity


1 S-Edit using CadanceTool. 1

b) Procedure for doing the experiment

S.No Details of the step


1 Draw the schematic of differential amplifier using S-edit and generate the
symbol.
2 Draw the schematic of differential amplifier circuit using the generated
symbol.
3 Perform AC Analysis of the differential amplifier.
4 Obtain the frequency response from W-edit.
5 Obtain the spice code using T-edit.

33
Dr NNCE ECE/VI-SEM VLSI DESIGN LAB-LM

SCHEMATIC DIAGRAM:

34
Dr NNCE ECE/VI-SEM VLSI DESIGN LAB-LM

RESULT

Thus the functional verification of the Differential Amplifier through schematic


entry.and the output also verified successfully

35
Dr NNCE ECE/VI-SEM VLSI DESIGN LAB-LM

Experiment Number: 8
Title Of The Experiment : LAYOUT OF CMOS INVERTER

Date of the experiment :

OBJECTIVE OF THE EXPERIMENT

To draw the layout of CMOS Inverter using L-Edit and extract the SPICE code.
FACILITIES REQUIRED AND PROCEDURE

a) Facilities required to do the experiment

S.No. SOFTWARE REQUIREMENTS Quantity


1 L-Edit using CadanceTool. 1
b) Procedure for doing the experiment

S.No Details of the step


1 Draw the CMOS Inverter layout by obeying the Lamda Rules using Ledit.
2 Poly - 2λ
ii. Active contact - 2 λ
iii. Active Contact – Metal - 1 λ
iv. Active Contact – Active region - 2 λ
v. Active Region – Pselect - 3 λ
vi. Pselect – nWell - 3λ
3 Check DRC to verify whether any region violate the lamda rule
4 Setup the extraction and extract the spice code using T-spice.

36
Dr NNCE ECE/VI-SEM VLSI DESIGN LAB-LM

CMOS INVERTER:

37
Dr NNCE ECE/VI-SEM VLSI DESIGN LAB-LM

RESULT:

Thus the layout of CMOS Inverter using L-Edit and extract the SPICE code.and the output
also verified successfully.

38

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