CSEE 3827: Fundamentals of Computer Systems,

Spring 2011

7. MIPS Instruction Set Architecture

Prof. Martha Kim ([email protected])

Web: http://www.cs.columbia.edu/~martha/courses/3827/sp11/
Outline (H&H 6.1-6.7.1)
• Introduction
• Assembly Language
• Machine Language
• Programming
• Addressing Modes
• Compiling, Assembling, and Loading
• Odds and Ends

2
Assembly Language

• To command a computer, you must understand its language.

• Instructions: words in a computer’s language

• Instruction set: the vocabulary of a computer’s language

• Instructions indicate the operation to perform and the operands to use.

• Assembly language: human-readable format of instructions

• Machine language: computer-readable format (1’s and 0’s)

Machine v. Assembly Code
(IGH LEVEL SWAPINT V;= INT K
LANGUAGE [INT TEMP
PROGRAM TEMP  V;K=
IN #

]
V;K=  V;K=
V;K=  TEMP (source code)

#OMPILER

!SSEMBLY SWAP
LANGUAGE MULI  

(assembly code)
PROGRAM ADD  
FOR -)03 LW  
LW  
SW  
SW  
JR 

!SSEMBLER

"INARY MACHINE 

(machine code)
LANGUAGE 
PROGRAM 
FOR -)03 




1, Ê£°ÎÊÊÊÊ
Ê«Àœ}À>“ÊVœ“«ˆi`ʈ˜ÌœÊ>ÃÃi“LÞʏ>˜}Õ>}iÊ>˜`Ê̅i˜Ê>ÃÃi“Li`ʈ˜ÌœÊLˆ˜>ÀÞÊ
“>V…ˆ˜iÊ >˜}Õ>}i°Ê !LTHOUGH THE TRANSLATION FROM HIGH LEVEL LANGUAGE TO BINARY MACHINE LANGUAGE IS
SHOWN IN TWO STEPS SOME COMPILERS CUT OUT THE MIDDLEMAN AND PRODUCE BINARY MACHINE LANGUAGE DIRECTLY
4HESE LANGUAGES AND THIS PROGRAM ARE EXAMINED IN MORE DETAIL IN #HAPTER  #OPYRIGHT Ú  %LSEVIER )NC
What is an ISA?
• An Instruction Set Architecture, or ISA, is an interface between the hardware
and the software.

• An ISA consists of:

• a set of operations (instructions)

• data units (sizes, addressing modes, etc.)

• processor state (registers)

• input and output control (memory operations)

• execution model (program counter)

5
Why have an ISA?
• An ISA provides binary compatibility across machines that share the ISA

• Any machine that implements the ISA X can execute a program encoded
using ISA X.

• You typically see families of machines, all with the same ISA, but with different
power, performance and cost characteristics.

• e.g., the MIPS family: MIPS 2000, 3000, 4400, 10000

6
MIPS Architecture

• MIPS = Microprocessor without Interlocked Pipeline Stages

• MIPS architecture developed at Stanford in 1984, spun out into MIPS

Computer Systems

• As of 2004, over 300 million MIPS microprocessors had been sold

• Used in many commercial systems, including Silicon Graphics, Nintendo, and

Cisco

• Once you’ve learned one architecture, it’s easy to learn others.

MIPS is a RISC Architecture

• RISC = Reduced Instruction Set Computer

• RISC is an alternative to CISC (Complex Instruction Set Computer) where

operations are significantly more complex.

• Underlying design principles, as articulated by Hennessy and Patterson:

• Simplicity favors regularity

• Make the common case fast

• Smaller is faster

• Good design demands good compromises

• MIPS (and other RISC architectures) are “load-store” architectures, meaning

all operations performed only on operands in registers. (The only instructions
that access memory are loads and stores)
What is an ISA?
• An Instruction Set Architecture, or ISA, is an interface between the hardware
and the software.

• An ISA consists of: (for MIPS)

• a set of operations (instructions)

arithmetic, logical,
conditional, branch, etc.

• data units (sized, addressing modes, etc.) 32-bit data word

• processor state (registers) 32, 32-bit registers
• input and output control (memory operations) load and store

• execution model (program counter) 32-bit program counter

9
An example Program in MIPS: Factorial(n)
int fact(int n) {
if (n < 1) return 1;
else return (n * fact(n - 1));
}
C code! fact:
addi $sp, $sp, -8 # adjust stack for 2 items
sw $ra, 4($sp) # save return address
sw $a0, 0($sp) # save argument
slti $t0, $a0, 1 # test for n < 1
beq $t0, $zero, L1
addi $v0, $zero, 1 # if so, result is 1
addi $sp, $sp, 8 # pop 2 items from stack
jr $ra # and return
L1: addi $a0, $a0, -1 # else decrement n
jal fact # recursive call
lw $a0, 0($sp) # restore original n
lw $ra, 4($sp) # and return address
addi $sp, $sp, 8 # pop 2 items from stack
mul $v0, $a0, $v0 # multiply to get result
jr $ra # and return
MIPS code

10
 An Program in MIPS
int fact(int n) {
if (n < 1) return 1;
else return (n * fact(n - 1));
}
C code! fact:
addi $sp, $sp, -8 # adjust stack for 2 items
sw $ra, 4($sp) # save return address
sw $a0, 0($sp) # save argument
Instructions slti
beq
$t0,
$t0,
$a0, 1
$zero, L1
# test for n < 1

(description of operation to addi $v0, $zero, 1 # if so, result is 1

be performed during a cycle) addi $sp, $sp, 8 # pop 2 items from stack
jr $ra # and return
L1: addi $a0, $a0, -1 # else decrement n
jal fact # recursive call
lw $a0, 0($sp) # restore original n
lw $ra, 4($sp) # and return address
addi $sp, $sp, 8 # pop 2 items from stack
mul $v0, $a0, $v0 # multiply to get result
jr $ra # and return
MIPS code

11
An Program in MIPS
int fact(int n) {
if (n < 1) return 1;
else return (n * fact(n - 1));
}
C code! fact:
addi $sp, $sp, -8 # adjust stack for 2 items
sw $ra, 4($sp) # save return address
sw $a0, 0($sp) # save argument
slti $t0, $a0, 1 # test for n < 1
beq $t0, $zero, L1

Registers addi $v0, $zero, 1 # if so, result is 1

addi $sp, $sp, 8 # pop 2 items from stack
jr $ra # and return
L1: addi $a0, $a0, -1 # else decrement n
jal fact # recursive call
lw $a0, 0($sp) # restore original n
lw $ra, 4($sp) # and return address
addi $sp, $sp, 8 # pop 2 items from stack
mul $v0, $a0, $v0 # multiply to get result
jr $ra # and return
MIPS code

12
An Program in MIPS
int fact(int n) {
if (n < 1) return 1;
else return (n * fact(n - 1));
}
C code! fact:
addi $sp, $sp, -8 # adjust stack for 2 items
sw $ra, 4($sp) # save return address
sw $a0, 0($sp) # save argument
slti $t0, $a0, 1 # test for n < 1
beq $t0, $zero, L1

Constants addi $v0, $zero, 1 # if so, result is 1

addi $sp, $sp, 8 # pop 2 items from stack
jr $ra # and return
L1: addi $a0, $a0, -1 # else decrement n
jal fact # recursive call
lw $a0, 0($sp) # restore original n
lw $ra, 4($sp) # and return address
addi $sp, $sp, 8 # pop 2 items from stack
mul $v0, $a0, $v0 # multiply to get result
jr $ra # and return
MIPS code

13
An Program in MIPS
int fact(int n) {
if (n < 1) return 1;
else return (n * fact(n - 1));
}
C code! fact:
addi $sp, $sp, -8 # adjust stack for 2 items
sw $ra, 4($sp) # save return address
sw $a0, 0($sp) # save argument

Access to
slti $t0, $a0, 1 # test for n < 1
beq $t0, $zero, L1

main memory addi $v0, $zero, 1 # if so, result is 1

addi $sp, $sp, 8 # pop 2 items from stack
jr $ra # and return
L1: addi $a0, $a0, -1 # else decrement n
jal fact # recursive call
lw $a0, 0($sp) # restore original n
lw $ra, 4($sp) # and return address
addi $sp, $sp, 8 # pop 2 items from stack
mul $v0, $a0, $v0 # multiply to get result
jr $ra # and return
MIPS code

14
 An Program in MIPS
int fact(int n) {
if (n < 1) return 1;
else return (n * fact(n - 1));
}
C code! fact:
addi $sp, $sp, -8 # adjust stack for 2 items

Control Labels
sw $ra, 4($sp) # save return address
sw $a0, 0($sp) # save argument

and “Jump”
slti $t0, $a0, 1 # test for n < 1
beq $t0, $zero, L1

Instructions addi $v0, $zero, 1 # if so, result is 1

addi $sp, $sp, 8 # pop 2 items from stack
jr $ra # and return
L1: addi $a0, $a0, -1 # else decrement n
jal fact # recursive call
lw $a0, 0($sp) # restore original n
lw $ra, 4($sp) # and return address
addi $sp, $sp, 8 # pop 2 items from stack
mul $v0, $a0, $v0 # multiply to get result
jr $ra # and return
MIPS code

15
Instruction Classes
• Memory Access: Move data to/from memory from/to registers

• Arithmetic/Logic: Perform (via functional unit) computation on data in

registers (store result in a register)

• Jump/Jump Subroutine: direct control to a different part of the program (not

next word in memory)

• Conditional branch: test values in registers. If test returns true, move control
to different part of program. Otherwise, proceed to next word

NB: These are functional classes. Later we will classify the

instructions according to their formats (R-type, I-type, etc.)

16
Arithmetic Instructions
• Addition and subtraction

• Three operands: two source, one destination

• add a, b, c # a gets b + c

• All arithmetic operations (and many others) have this form

Design principle:

Regularity makes implementation simpler

Simplicity enables higher performance at lower cost

17
Arithmetic Example 1

add t0, g, h # temp t0=g+h

add t1, i, j # temp t1=i+j
f = (g + h) - (i + j) sub f, t0, t1 # f = t0-t1
C code MIPS assembly

18
 Arithmetic Example 1 w. Registers

add t0, g, h # temp t0=g+h

add t1, i, j # temp t1=i+j
sub f, t0, t1 # f = t0-t1
MIPS assembly w.o registers

store: f in $s0, g in $s1, h in $s2, i in $s3, and j in $s4

add $t0, $s1, $s2

add $t1, $s3, $s4
sub $s0, $t0, $t1
MIPS assembly w. registers

19
 Memory Operands
• Main memory used for composite data (e.g., arrays, structures, dynamic data)

• To apply arithmetic operations

• Load values from memory into registers (load instruction = mem read)

• Store result from registers to memory (store instruction = mem write)

• Memory is byte-addressed (each address identifies an 8-bit byte)

• Words (32-bits) are aligned in memory (meaning each address must be a multiple
of 4)

• MIPS is big-endian (i.e., most significant byte stored at least address of the word)

20
 Memory Operands
• Main memory used for composite data (e.g., arrays, structures, dynamic data)

• To apply arithmetic operations

• Load values from memory into registers (load instruction = mem read)

• Store result from registers to memory (store instruction = mem write)

• Memory is byte-addressed (each address identifies an 8-bit byte)

• Words (32-bits) are aligned in memory (meaning each address must be a multiple
of 4)

• MIPS is big-endian (i.e., most significant byte stored at least address of the word)

21
Memory Operand Example 1

g = h + A[8]

C code

g in $s1, h in $s2, base address of A in $s3

index = 8 requires offset of 32 (8 items x 4 bytes per word)

offset base register

lw $t0, 32($s3) # load word

add $s1, $s2, $t0
MIPS assembly

22
Memory Operand Example 2

A[12] = h + A[8]

C code

h in $s2, base address of A in $s3

index = 8 requires offset of 32 (8 items x 4 bytes per word)
index = 12 requires offset of 48 (12 items x 4 bytes per word)

lw $t0, 32($s3) # load word

add $t0, $s2, $t0
sw $t0, 48($s3) # store word
MIPS assembly

23
 Registers v. Memory
• Registers are faster to access than memory

• Operating on data in memory requires loads and stores

• (More instructions to be executed)

• Compiler should use registers for variables as much as possible

• Only spill to memory for less frequently used variables

• Register optimization is important for performance

24
 Immediate Operands
• Constant data encoded in an instruction

addi $s3, $s3, 4

• No subtract immediate instruction, just use the negative constant

addi $s2, $s1, -1

Design principle: make the common case fast

Small constants are common

Immediate operands avoid a load instruction

25
The Constant Zero
• MIPS register 0 ($zero) is the constant 0

• $zero cannot be overwritten

• Useful for many operations, for example, a move between two registers

add $t2, $s1, $zero

26
Register Numbers

0RESERVED ON
.AME 2EGISTER NUMBER 5SAGE CALL
ZERO  4HE CONSTANT VALUE  NA
VnV n 6ALUES FOR RESULTS AND EXPRESSION EVALUATION NO
AnA n !RGUMENTS NO
TnT n 4EMPORARIES NO
SnS n 3AVED YES
TnT n -ORE TEMPORARIES NO
GP  'LOBAL POINTER YES
SP  3TACK POINTER YES
FP  &RAME POINTER YES
RA  2ETURN ADDRESS YES

&)'52%  -)03 REGISTER CONVENTIONS 2EGISTER  CALLED AT IS RESERVED FOR THE ASSEMBLER SEE
3ECTION   AND REGISTERS   CALLED K K ARE RESERVED FOR THE OPERATING SYSTEM 4HIS INFORMATION
Note: Register 1 ($at) is reserved for the assembler, and
IS ALSO FOUND IN #OLUMN  OF THE -)03 2EFERENCE $ATA #ARD AT THE FRONT OF THIS BOOK #OPYRIGHT Ú 
26-27
%LSEVIER )NC !LL ($k0-$k1) are reserved for the OS.
RIGHTS RESERVED

27
MIPS instructions to date

˜ÃÌÀÕV̈œ˜ œÀ“>Ì œ« Àà ÀÌ À` Å>“Ì v՘VÌ >``ÀiÃÃ

ADD , ä Ài} Ài} Ài} ä ÎÓÌi˜ ˜°>°
SUB ­ÃÕLÌÀ>VÌ® , ä Ài} Ài} Ài} ä Î{Ìi˜ ˜°>°
ADD IMMEDIATE  nÌi˜ Ài} Ài} ˜°>° ˜°>° ˜°>° Vœ˜ÃÌ>˜Ì
LW ­œ>`ÊܜÀ`®  ÎxÌi˜ Ài} Ài} ˜°>° ˜°>° ˜°>° >``ÀiÃÃ
SW ­Ã̜ÀiÊܜÀ`®Ê  {ÎÌi˜ Ài} Ài} ˜°>° ˜°>° ˜°>° >``ÀiÃÃ

1, ÊÓ°xÊ *-ʈ˜ÃÌÀÕV̈œ˜Êi˜Vœ`ˆ˜}°Ê)N THE TABLE ABOVE hREGv MEANS A REGISTER NUMBER BETWEEN
 AND  hADDRESSv MEANS A  BIT ADDRESS AND hNAv NOT APPLICABLE MEANS THIS lELD DOES NOT APPEAR IN THIS
FORMAT .OTENB:
THAT ADDreg = register
AND SUB INSTRUCTIONSnumber
HAVE THE SAMEbetween 0 and
VALUE IN THE OP 31;
lELD THE HARDWARE USES THE FUNCT
lELD TO DECIDE THE VARIANT OF THE OPERATION ADD  OR SUBTRACT   #OPYRIGHT Ú  %LSEVIER )NC !LL RIGHTS
RESERVED
address = 16-bit address

28
MIPS R-format Instructions

op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

• Instruction fields
• op: operation code (opcode)
• rs: first source register number
• rt: second source register number
• rd: register destination number
• shamt: shift amount (00000 for now)
• funct: function code (extends opcode)

29
R-format Example

op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

add $t0, $s1, $s2

special $s1 $s2 $t0 0 add

0 17 18 8 0 32

000000 10001 10010 01000 00000 100000

30
MIPS I-format Instructions

op rs rt constant
6 bits 5 bits 5 bits 16 bits

• Includes immediate arithmetic and load/store operations

• op: operation code (opcode)
• rs: first source register number
• rt: destination register number
• constant: offset added to base address in rs, or immediate operand

31
MIPS Logical Operations
• Instructions for bitwise manipulation

œ}ˆV>Êœ«iÀ>̈œ˜Ã
ʜ«iÀ>̜Àà >Û>ʜ«iÀ>̜Àà *-ʈ˜ÃÌÀÕV̈œ˜Ã
Ê -…ˆvÌʏivÌ   SLL
Ê -…ˆvÌÊÀˆ}…Ì   SRL
Ê ˆÌ‡LއLˆÌÊ
   ANDÊANDI
Ê ˆÌ‡LއLˆÌÊ", \ \ ORÊORI
Ê ˆÌ‡LއLˆÌÊ "/ ^ ^ NOR

1, ÊÓ°nÊ
Ê>˜`Ê>Û>ʏœ}ˆV>Êœ«iÀ>̜ÀÃÊ>˜`Ê̅iˆÀÊVœÀÀi뜘`ˆ˜}Ê*-ʈ˜ÃÌÀÕV̈œ˜Ã°Ê-)03
• Useful
IMPLEMENTSfor./4
inserting andWITH
USING A ./2 extracting
ONE OPERANDgroups
BEING ZEROof#OPYRIGHT
bits inÚa
word%LSEVIER )NC !LL RIGHTS
RESERVED
•

32
Shift Operations
• Shift left logical (op = sll)

• Shift left and fill with 0s

• sll by i bits multiplies by 2 i

• Shift right logical (op = srl)
• Shift right and fill with 0s

• srl by i bits divides by 2 i (for unsigned values only)

• shamt indicates how many positions to shift

• example: sll $t2, $s0, 4 # $t2 = $s0 << 4 bits

• R-format

0 0 16 10 4 0

33
Full Complement of Shift Instructions
• sll: shift left logical (sll $t0, $t1, 5 # $t0 <= $t1 << 5)
• srl: shift right logical (srl $t0, $t1, 5 # $t0 <= $t1 >> 5)
• sra: shift right arithmetic (sra $t0, $t1, 5 # $t0 <= $t1 >>> 5)

• Variable shift instructions:

• sllv: shift left logical variable
(sllv $t0, $t1, $t2 # $t0 <= $t1 << $t2)
• srlv: shift right logical variable
(srlv $t0, $t1, $t2 # $t0 <= $t1 >> $t2)
• srav: shift right arithmetic variable
(srav $t0, $t1, $t2 # $t0 <= $t1 >>> $t2)

34
Generating Constants
• 16-bit constants using addi:

// int is a 32-bit signed word

int a = 0x4f3c
# $s0 = a
C code addi $s0, $0, 0x4f3c
MIPS assembly
• 32-bit constants using load upper immediate (lui*) and ori *lui loads the
16-bit immediate into the upper half of the register and sets the lower half to
0.)

int a = 0xFEDC8765; lui $s0, 0xFEDC

ori $s0, $s0, 0x8765
C code MIPS assembly

*lui loads the 16-bit immediate into the upper half of the register and sets
the lower half to 0.

35
AND Operations

• example: and $t0, $t1, $t2 # $t0 = $t1 & $t2

• Useful for masking bits in a word (selecting some bits, clearing others to 0)

$t1: 0000 0000 0000 0000 0000 1101 1100 0000

$t2: 0000 0000 0000 0000 0011 1100 0000 0000

$t0: 0000 0000 0000 0000 0000 1100 0000 0000

36
OR Operations

• example: or $t0, $t1, $t2 # $t0 = $t1 | $t2

• Useful to include bits in a word (set some bits to 1, leaving others unchanged)

$t1: 0000 0000 0000 0000 0000 1101 1100 0000

$t2: 0000 0000 0000 0000 0011 1100 0000 0000

$t0: 0000 0000 0000 0000 0011 1101 1100 0000

37
NOT Operations

• Useful to invert bits in a word

• MIPS has 3 operand NOR instruction, used to compute NOT

• example: nor $t0, $t1, $zero # $t0 = ~$t1

$t1: 0000 0000 0000 0000 0000 1101 1100 0000

$t0: 1111 1111 1111 1111 1111 0010 0011 1111

38
Conditional Operations
• Branch to a labeled instruction if a condition is true

• Otherwise, continue sequentially

• Instruction labeled with colon e.g. L1: add $t0, $t1, $t2

• beq rs, rt, L1 # if (rs == rt) branch to instr labeled L1

• bne rs, rt, L1 # if (rs != rt) branch to instr labeled L1

• j L1 # unconditional jump to instr labeled L1

39
Compiling an If Statement

if (i == j) bne $s3, $s4, Else

f = g+h add $s0, $s1, $s2
else j Exit
f = g-h Else:
sub $s0, $s1, $s2
C code Exit:
MIPS assembly

• Where, f is in $s0, g is in $s1, and h is in $s2

• The assembler calculates the addresses corresponding to the labels

40
Compiling a Loop Statement

Loop:
sll $t1, $s3, 2
while (save[i] == k) add $t1, $t1, $s5
i += 1 lw $t0, 0($t1)
bne $t0, $s4, Exit
C code
addi $s3, $s3, 1
j Loop
Exit:
MIPS assembly

• Where, i is in $s3, k is in $s4, address of save in $s5

41
Basic Blocks
• A basic block is a sequence of instructions with

• No embedded branches except at the end

• No branch targets except at the beginning

• A compiler identifies basic blocks for optimization

• Advanced processors can accelerate execution of

basic blocks

42
More Conditional Operations
• Set result to 1 if a condition is true

• slt rd, rs, rt # (rs < rt) ? rd=1 : rd=0

• slti rd, rs, constant # (rs < constant) ? rd=1 : rd=0

• Use in combination with beq or bne

slt $t0, $s1, $s2 # if ($s1 < $s2)

bne $t0, $zero, L # branch to L

43
Branch Instruction Design
• Why not blt, bge, etc.?

• Hardware for <, >= etc. is slower than for = and !=

• Combining with a branch involves more work per instruction, requiring a

slower clock

• All instructions penalized because of this

• As beq and bne are the common case, this is a good compromise

44
Signed v. Unsigned
• Signed comparison: slt, slti

• Unsigned comparison: sltu, sltui

• Example:

$s0: 1111 1111 1111 1111 1111 1111 1111 1111

$s1: 0000 0000 0000 0000 0000 0000 0000 0001

slt $t0, $s0, $s1 # signed: -1 < 1 thus $t0=1

sltu $t0, $s0, $s1 # unsigned: 4,294,967,295 > 1 thus $t0=0

45
Procedure Calling
• Steps required:
“caller”

1. Place parameters in registers

1
2. Transfer control to procedure
2
3. Acquire storage for procedure “callee”

4. Perform procedure’s operations 3

6
4
5. Place result in register for caller
5
6. Return to place of call

46
Register Usage
• $a0-$a3: arguments

• $v0, $v1: result values

• $t0-$t9: temporaries, can be overwritten by callee

• $s0-$s7: contents saved *** must be restored by callee

• $gp: global pointer for static data

Note: There is nothing special about these
• $sp: stack pointer registers’ design, only their implied use!!!

e.g., could store return value in $sp if calling

• $fp: frame pointer and callee program both agreed to do this -
just beware of messing up the stack for all
• $ra: return address other programs if not properly restored

47
 Memory Layout
• Text: program code

• Static data: global variables

SP FFF FFFCHEX 3TACK

• e.g., static variables in C, constant arrays

and strings

$YNAMIC DATA
• $gp initialized to an address allowing +/-
offsets in this segment GP  HEX 3TATIC DATA
 HEX
4EXT
• Dynamic data: heap PC  HEX
2ESERVED

• e.g., malloc in C, new in Java
1, Ê Ó°£ÎÊ /…iÊ *-Ê “i“œÀÞÊ >œV>̈œ˜Ê vœÀÊ «Àœ}À>“Ê >˜`Ê `>Ì>°Ê
ONLY A SOFTWARE CONVENTION AND NOT PART OF THE -)03 ARCHITECTUREÊ 4HE STACK PO
FFF FFFCHEX AND GROWS DOWN TOWARD THE DATA SEGMENT !T THE OTHER END THE PROGRA
• Stack: automatic storage
AT  HEX 4HE STATIC DATA STARTS AT  HEX $YNAMIC DATA ALLOCATED
BY NEW IN *AVA IS NEXT )T GROWS UP TOWARD THE STACK IN AN AREA CALLED THE HEAP 4HE G
SET TO AN ADDRESS TO MAKE IT EASY TO ACCESS DATA )T IS INITIALIZED TO  HEX SO TH
 HEX TO  FFFFHEX USING THE POSITIVE AND NEGATIVE  BIT OFFSETS FROM 48 
Local Data on the Stack
• Local data allocated by the callee

• Procedure frame (activation record) used by compiler to manage stack

storage (IGH ADDRESS

FP FP

SP SP
FP 3AVED ARGUMENT
REGISTERS IF ANY
3AVED RETURN ADDRESS
3AVED SAVED
REGISTERS IF ANY

,OCAL ARRAYS AND

SP STRUCTURES IF ANY

,OW ADDRESS
A B C

1, ÊÓ°£ÓÊ ÕÃÌÀ>̈œ˜ÊœvÊ̅iÊÃÌ>VŽÊ>œV>̈œ˜Ê­>®ÊLivœÀi]Ê­L®Ê`ÕÀˆ˜}]Ê>˜`Ê­V®Ê>vÌiÀÊ̅iÊ

«ÀœVi`ÕÀiÊV>° 4HE FRAME POINTER FP POINTS TO THE lRST WORD OF THE FRAME OFTEN A SAVED ARGUMENT
• Cross-call register preservation
REGISTER AND THE STACK POINTER SP POINTS TO THE TOP OF THE STACK 4HE STACK IS ADJUSTED TO MAKE ROOM FOR
ALL THE SAVED REGISTERS AND ANY MEMORY RESIDENT LOCAL VARIABLES 3INCE THE STACK POINTER MAY CHANGE DURING
PROGRAM EXECUTION ITS EASIER*ÀiÃiÀÛi`
FOR PROGRAMMERS TO REFERENCE VARIABLESœÌÊ«ÀiÃiÀÛi`
VIA THE STABLE FRAME POINTER ALTHOUGH IT
COULD BE DONE JUST WITH THE STACK POINTER AND A LITTLE ADDRESS ARITHMETIC )F THERE ARE NO LOCAL VARIABLES ON THE
STACK WITHIN A PROCEDURE THE COMPILER WILL SAVE TIME BY/i“«œÀ>ÀÞÊÀi}ˆÃÌiÀÃ\ÊTqT
->Ûi`ÊÀi}ˆÃÌiÀÃ\ÊSqSÊ NOT SETTING AND RESTORING THE FRAME POINTER 7HEN A
FRAME POINTER IS-Ì>VŽÊ«œˆ˜ÌiÀÊÀi}ˆÃÌiÀ\ÊSPÊ
USED IT IS INITIALIZED USING THE ADDRESS IN SP ON A CALL AND SP IS RESTORED USING FP 4HIS

À}Փi˜ÌÊÀi}ˆÃÌiÀÃ\ÊAqAÊ
INFORMATION IS ALSO FOUND IN #OLUMN  OF THE -)03 2EFERENCE
,iÌÕÀ˜Ê>``ÀiÃÃÊÀi}ˆÃÌiÀ\ÊRA $ATA #ARD AT THE FRONT OF THIS BOOK #OPYRIGHT Ú
,iÌÕÀ˜ÊÛ>ÕiÊÀi}ˆÃÌiÀÃ\ÊVqV
 %LSEVIER )NC !LL RIGHTS RESERVED
-Ì>VŽÊ>LœÛiÊ̅iÊÃÌ>VŽÊ«œˆ˜ÌiÀ -Ì>VŽÊLiœÜÊ̅iÊÃÌ>VŽÊ«œˆ˜ÌiÀ

1, ÊÓ°££Ê 7…>ÌʈÃÊ>˜`Ê܅>ÌʈÃʘœÌÊ«ÀiÃiÀÛi`Ê>VÀœÃÃÊ>Ê«ÀœVi`ÕÀiÊV>°Ê)F THE SOFTWARE RELIES

ON THE FRAME POINTER REGISTER OR ON THE GLOBAL POINTER REGISTER DISCUSSED IN THE FOLLOWING SUBSECTIONS THEY
ARE ALSO PRESERVED #OPYRIGHT Ú  %LSEVIER )NC !LL RIGHTS RESERVED 49
Procedure Call Instructions
• Procedure call: jump and link

• jal ProcedureLabel

• Address of following instruction put in $ra

• Jumps to target address

• Procedure return: jump register

• jr $ra

• copies $ra to program counter

• can also be used for computed jumps (e.g., for case/switch statements)

50
Leaf Procedure Example

int leaf_example(int g,h,i,j) {

int f;
f = (g+h) - (i+j);
return f;
}
C code

• Arguments g, h, i, j in $a0 - $a3

• f will go in $s0 (so will have to save existing contents of $s0 to stack)

• result in $v0

51
Leaf Procedure Example 2
int leaf_example(int g,h,i,j) {
int f;
f = (g+h) - (i+j);
return f;
}
C code
leaf_example:
addi $sp, $sp, -4 save $s0 on stack
sw $s0, 0($sp)
add $t0, $a0, $a1
add $t1, $a2, $a2 procedure body
sub $s0, $t0, $t1
add $v0, $s0, $zero result
lw $s0, 0($sp)
restore $s0
addi $sp, $sp, 4
jr $ra return
MIPS assembly

52
Non-Leaf Procedures
• A non-leaf procedure is a procedure that calls another procedure

• For a nested call, the caller needs to save to the stack

• Its return address

• Any arguments and temporaries needed after the call

• After the call, the caller must restore these values from the stack

53
Non-Leaf Procedure Example
int fact(int n) {
if (n < 1) return 1;
else return (n * fact(n - 1));
}
C code

54
Non-Leaf Procedure Example 2
int fact(int n) {
if (n < 1) return 1;
else return (n * fact(n - 1));
}
C code! fact:
addi $sp, $sp, -8 # adjust stack for 2 items
sw $ra, 4($sp) # save return address
sw $a0, 0($sp) # save argument
slti $t0, $a0, 1 # test for n < 1
beq $t0, $zero, L1
addi $v0, $zero, 1 # if so, result is 1
addi $sp, $sp, 8 # pop 2 items from stack
jr $ra # and return
L1: addi $a0, $a0, -1 # else decrement n
jal fact # recursive call
lw $a0, 0($sp) # restore original n
lw $ra, 4($sp) # and return address
addi $sp, $sp, 8 # pop 2 items from stack
mul $v0, $a0, $v0 # multiply to get result
jr $ra # and return
MIPS assembly

55
Character Data
• Byte-encoded character sets

• ASCII: 128 characters (95 graphic, 33 control)

• Latin-1: 256 characters (ASCII, + 96 more graphic characters)

• Unicode: 32-bit character set

• Used in Java, C++ wide characters

• Most of the world’s alphabets, plus symbols

• UTF-8, UTF-16 are variable-length encodings

56
Byte/Halfword Operations
• Could use bitwise operations

• MIPS has byte/halfword load/store

• lb rt, offset(rs) # sign extend byte to 32 bits in rt

• lh rt, offset(rs) # sign extend halfword to 32 bits in rt

• lbu rt, offset(rs) # zero extend byte to 32 bits in rt

• lhu rt, offset(rs) # zero extend halfword to 32 bits in rt

• sb rt, offset(rs) # store rightmost byte

• sh rt, offset(rs) # store rightmost halfword

57
String Copy Example
void strcpy (char x[], char y[]) {
int i;
i = 0;
while ((x[i]=y[i]) != ‘\0’)
i += 1;
}
C code (naive)

• Null-terminated string

• Addresses of x and y in $a0 and $a1 respectively

• i in $s0

58
 String Copy Example 2
void strcpy (char x[], char y[]) {
int i;
i = 0;
while ((x[i]=y[i]) != ‘\0’)
i += 1;
}
C code (naive)
! strcpy :
addi $sp, $sp, -4 # adjust stack for 1 item
sw $s0, 0($sp) # save $s0
add $s0, $zero, $zero # i = 0
L1: add $t1, $s0, $a1 # addr of y[i] in $t1
lbu $t2, 0($t1) # $t2 = y[i]
add $t3, $s0, $a0 # addr of x[i] in $t3
sb $t2, 0($t3) # x[i] = y[i]
beq $t2, $zero, L2 # exit loop if y[i] == 0
addi $s0, $s0, 1 # i = i + 1
j L1 # next iteration of loop
L2: lw $s0, 0($sp) # restore saved $s0
addi $sp, $sp, 4 # pop 1 item from stack
jr $ra # and return
MIPS assembly
59
 32-bit constants
• Most constants are small, 16 bits usually sufficient

• For occasional, 32-bit constant:

lui rt, constant

• copies 16-bit constant to the left (upper) bits of rt

• clears right (lower) 16 bits of rt to 0

• example usage:

lui $s0, 61 $s0: 0000 0000 0111 1101 0000 0000 0000 0000

ori $s0, $s0, 2304 $s0: 0000 0000 0111 1101 0000 1001 0000 0000

60
Branch Addressing
• Branch instructions specify: opcode, two registers, branch target

op rs rt constant
6 bits 5 bits 5 bits 16 bits

• Most branch targets are near branch (either forwards or backwards)

• PC-relative addressing

• target address = PC + (offset * 4)

• PC already incremented by four when the target address is calculated

61
Jump Addressing
• Jump (j and jal) targets could be anywhere in a text segment, so, encode the
full address in the instruction

op address
6 bits 26 bits

• target address = PC[31:28] : (address * 4)

62
Target Addressing Example
• Loop code from earlier example

• Assume loop at location 80000

Loop: sll $t1, $s3, 2 80000 0 0 19 9 4 0

add $t1, $t1, $s5 80004 0 9 21 9 0 32
lw $t0, 0($t1) 80008 35 9 8 0
bne $t0, $s4, Exit 80012 5 8 20 2
addi $s3, $s3, 1 80016 8 19 19 1
j Loop 80020 2 20000
Exit: 80024

63
Addressing Mode Summary
 )MMEDIATE ADDRESSING
OP RS RT )MMEDIATE

 2EGISTER ADDRESSING
OP RS RT RD    FUNCT 2EGISTERS
2EGISTER

 "ASE ADDRESSING
OP RS RT !DDRESS -EMORY

2EGISTER  "YTE (ALFWORD 7ORD

 0# RELATIVE ADDRESSING
OP RS RT !DDRESS -EMORY

0#  7ORD

 0SEUDODIRECT ADDRESSING
OP !DDRESS -EMORY

0# 7ORD

1, ÊÓ°£nÊ ÕÃÌÀ>̈œ˜ÊœvÊ̅iÊwÛiÊ*-Ê>``ÀiÃȘ}ʓœ`ið 4HE OPERANDS ARE SHADED IN COLOR

4HE OPERAND OF MODE  IS IN MEMORY WHEREAS THE OPERAND FOR MODE  IS A REGISTER .OTE THAT VERSIONS OF LOAD
AND STORE ACCESS BYTES HALFWORDS OR WORDS &OR MODE  THE OPERAND IS  BITS OF THE INSTRUCTION ITSELF -ODES
 AND  ADDRESS INSTRUCTIONS IN MEMORY WITH MODE  ADDING A  BIT ADDRESS SHIFTED LEFT  BITS TO THE 0# AND 64
Branching Far Away
• If a branch target is too far to encode with a 16-bit offset, assembler rewrites
the code

• Example:

! beq $s0,$s1, L1 becomes bne $s0,$s1, L2

j L1
L2:! …

65
Assembler Pseudoinstructions
• Most assembler instructions represent machine instructions, one to one.

• Pseudoinstructions are shorthand. They are recognized by the assembler but

translated into small bundles of machine instructions.

becomes
move $t0,$t1 add $t0,$zero,$t1

blt $t0,$t1,L becomes slt $at,$t0,$t1

bne $at,$zero,L

• $at (register 1) is an “assembler temporary”

66
Programming Pitfalls
• Sequential words are not at sequential addresses -- increment by 4 not by 1!

• Keeping a pointer to an automatic variable (on the stack) after procedure

returns

67
Interpreting Machine Language Code
• Start with opcode
• Opcode tells how to parse the remaining bits
• If opcode is all 0’s
• R-type instruction
• Function bits tell what instruction it is
• Otherwise, opcode tells what instruction it is

Copyright © 2007 Elsevier

68
In conclusion: Fallacies
1. Powerful (complex) instructions lead to higher performance

• Fewer instructions are required

• But complex instructions are hard to implement. As a result implementation may

slow down all instructions including simple ones.

• Compilers are good at making fast code from simple instructions.

2. Use assembly code for high performance

• Modern compilers are better than predecessors at generating good assembly

• More lines of code (in assembly) means more errors and lower productivity

69
In conclusion: More Fallacies
3. Backwards compatibility means instruction set doesn’t change




.UMBER OF )NSTRUCTIONS









                
               
9EAR

1, Ê Ó°{ÎÊ ÀœÜÌ…Ê œvÊ ÝnÈÊ ˆ˜ÃÌÀÕV̈œ˜Ê ÃiÌÊ œÛiÀÊ Ìˆ“i°Ê 7HILE THERE IS CLEAR TECHNICAL VALUE TO
SOME OF THESE EXTENSIONS THIS RAPID CHANGE ALSO INCREASES THE DIFlCULTY FOR OTHER COMPANIES TO TRY TO BUILD
COMPATIBLE PROCESSORS #OPYRIGHT Ú  %LSEVIER )NC !LL RIGHTS RESERVED

70