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Static Memories - Computer

Organization Questions and
Answers
by Manish
4-5 minutes

This set of Computer Organization and Architecture Multiple

Choice Questions & Answers (MCQs) focuses on “Static
Memories”.

1. The duration between the read and the mfc signal is

______
a) Access time
b) Latency
c) Delay
d) Cycle time
View Answer

Answer: a
Explanation: The time between the issue of read signal and
the completion of it is called memory access time.

2. The minimum time delay between two successive

memory read operations is ______
a) Cycle time
b) Latency

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c) Delay
d) None of the mentioned
View Answer

Answer: a
Explanation: The Time taken by the cpu to end one read
operation and to start one more is cycle time.

3. MFC is used to _________

a) Issue a read signal
b) Signal to the device that the memory read operation is
complete
c) Signal the processor the memory operation is complete
d) Assign a device to perform the read operation
View Answer

Answer: c
Explanation: The MFC stands for memory Function
Complete.

4. __________ is the bootleneck, when it comes computer

performance.
a) Memory access time
b) Memory cycle time
c) Delay
d) Latency
View Answer

Answer: b
Explanation: The processor can execute instructions faster
than they’re fetched, hence cycle time is the bottleneck for
performance.

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5. The logical addresses generated by the cpu are mapped

onto physical memory by ____
a) Relocation register
b) TLB
c) MMU
d) None of the mentioned
View Answer

Answer: c
Explanation: The MMU stands for memory management
unit, which is used to map logical address onto phsical
address.

6. VLSI stands for ___________

a) Very Large Scale Integration
b) Very Large Stand-alone Integration
c) Volatile Layer System Interface
d) None of the mentioned
View Answer

Answer: a
Explanation: None.

7. The cells in a row are connected to a common line called

______
a) Work line
b) Word line
c) Length line
d) Principle diagonal
View Answer

Answer: b
Explanation: This means that the cell contents together

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form one word of instruction or data.

8. The cells in each column are connected to ______

a) Word line
b) Data line
c) Read line
d) Sense/ Write line
View Answer

Answer: d
Explanation: The cells in each column are connected to the
sense/write circuit using two bit lines and which is inturn
connected to the data lines.

9. The word line is driven by the _____

a) Chip select
b) Address decoder
c) Data line
d) Control line
View Answer

Answer: b
Explanation: None.

10. A 16 X 8 organisation of memory cells, can store upto

_____
a) 256 bits
b) 1024 bits
c) 512 bits
d) 128 bits
View Answer

Answer: d

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Explanation: It can store upto 128 bits as each cell can hold
one bit of data.

11. A memory organisation that can hold upto 1024 bits and
has a minimum of 10 address lines can be organised into
_____
a) 128 X 8
b) 256 X 4
c) 512 X 2
d) 1024 X 1
View Answer

Answer: d
Explanation: All the others require less than 10 address
bits.

12. Circuits that can hold their state as long as power is

applied is _______
a) Dynamic memory
b) Static memory
c) Register
d) Cache
View Answer

Answer: b
Explanation: None.

13. The number of external connections required in 16 X 8

memory organisation is _____
a) 14
b) 19
c) 15
d) 12

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View Answer

Answer: a
Explanation: In the 14, 8-data lines,4-address lines and 2
are sense/write and CS signals.

14. The advantage of CMOS SRAM over the transistor

one’s is _________
a) Low cost
b) High efficiency
c) High durability
d) Low power consumption
View Answer

Answer: d
Explanation: This is because the cell consumes power only
when it is being accessed.

15. In a 4M-bit chip organisation has a total of 19 external

connections.then it has _______ address if 8 data lines are
there.
a) 10
b) 8
c) 9
d) 12
View Answer

Answer: c
Explanation: To have 8 data lines and 19 external
connections it has to have 9 address lines(i.e 512 x 8
organisation).

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Computer Organisation and Architecture.

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Asynchronous DRAM - Computer

Organization Questions and
Answers
by Manish
3-4 minutes

This set of Computer Organization and Architecture Multiple

Choice Questions & Answers (MCQs) focuses on
“Asynchronous DRAM”.

1. The Reason for the disregarding of the SRAM’s is

________
a) Low Efficiency
b) High power consumption
c) High Cost
d) All of the mentioned
View Answer

Answer: c
Explanation: The reason for the high cost of the SRAM is
because of the usage of more number of transistors.

2. The disadvantage of DRAM over SRAM is/are _______

a) Lower data storage capacities
b) Higher heat descipation
c) The cells are not static

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d) All of the mentioned

View Answer

Answer: c
Explanation: This means that the cells wont hold their state
indefinetly.

3. The reason for the cells to lose their state over time is
a) The lower voltage levels
b) Usage of capacitors to store the charge
c) Use of Shift registers
d) None of the mentioned
View Answer

Answer: b
Explanation: Since capacitors are used the charge
descipates over time.

4. The capacitors lose the charge over time due to

a) The leakage resistance of the capacitor
b) The small current in the transistor after being turned on
c) The defect of the capacitor
d) None of the mentioned
View Answer

Answer: a
Explanation: The capacitor loses charge due to the
backward current of the transistro and due to the small
resistance.

5. _________ circuit is used to restore the capacitor value.

a) Sense amplify
b) Signal amplifier

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c) Delta modulator
d) None of the mentioned
View Answer

Answer: a
Explanation: The sense amplifier detects if the value is
above or below the threshlod and then restores it.

6. To reduce the number of external connections reqiured,

we make use of ______
a) De-multiplexer
b) Multiplexer
c) Encoder
d) Decoder
View Answer

Answer: b
Explanation: We multiplex the various address lines onto
fewer pins.

7. The processor must take into account the delay in

accessing the memory location, such memories are called
______
a) Delay integrated
b) Asynchronous memories
c) Synchronous memories
d) Isochronous memories
View Answer

Answer: b
Explanation: None.

8. To get the row address of the required data ______ is

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enabled.
a) CAS
b) RAS
c) CS
d) Sense/write
View Answer

Answer: b
Explanation: This makes the contents of the row required
refreshed.

9. In order to read multiple bytes of a row at the same time,

we make use of ______
a) Latch
b) Shift register
c) Cache
d) Memory extension
View Answer

Answer: a
Explanation: The latch makes it easy to ready multiple bytes
of data of the same row simulteneously by just giving the
consecutive column address.

10. The block transfer capability of the DRAM is called

________
a) Burst mdoe
b) Block mode
c) Fast page mode
d) Fast frame mode
View Answer

Answer: c

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Explanation: None.

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Synchronous DRAM - Computer

Organization Questions and
Answers
by Manish
3-4 minutes

This set of Computer Organization and Architecture Multiple

Choice Questions & Answers (MCQs) focuses on
“Synchronous DRAM”.

1. The difference between DRAM’s and SDRAM’s is/are

________
a) The DRAM’s will not use the master slave relationship in
data transfer
b) The SDRAM’s make use of clock
c) The SDRAM’s are more power efficient
d) None of the mentioned
View Answer

Answer: d
Explanation: The SDRAM’s make use of clock signals to
synchronise their operation.

2. The difference in address and data connection between

DRAM’s and SDRAM’s is
a) The usage of more number of pins in SDRAM’s

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b) The requirement of more address lines in SDRAM’s

c) The usage of buffer in SDRAM’s
d) None of the mentioned
View Answer

Answer: c
Explanation: The SDRAM uses buffered storage of address
and data.

3. A _______ is used to restore the contents of the cells.

a) Sense amplifier
b) Refresh counter
c) Restorer
d) None of the mentioned
View Answer

Answer: b
Explanation: The Counter helps to restore the charge on
the capacitor.

4. The mode register is used to

a) Select the row or column data transfer mode
b) Select the mode of operation
c) Select mode of storing the data
d) All of the mentioned
View Answer

Answer: b
Explanation: The mode register is used to choose between
burst mode or bit mode of operation.

5. In a SDRAM each row is refreshed every 64ms.

a) True

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b) False
View Answer

Answer: a
Explanation: None.

6. The time taken to transfer a word of data to or from the

memory is called as ______
a) Access time
b) Cycle time
c) Memory latency
d) None of the mentioned
View Answer

Answer: c
Explanation: The performance of the memory is measured
by means of latency.

7. In SDRAM’s buffers are used to store data that is read or

written.
a) True
b) False
View Answer

Answer: a
Explanation: In SDRAm’s all the bytes of data to be read or
written are stored in the buffer until the operation is
complete.

8. The SDRAM performs operation on the _______

a) Rising edge of the clock
b) Falling edge of the clock
c) Middle state of the clock

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d) Transition state of the clock

View Answer

Answer: a
Explanation: The SDRAM’s are edge-triggered.

9. DDR SDRAM’s perform fster data transfer by

a) Integrating the hardware
b) Transfering on both edges
c) Improving the clock speeds
d) Increasing the bandwidth
View Answer

Answer: b
Explanation: By transfering data on both the edges the
bandwidth is effectively doubled.

10. To improve the data retrieval rate

a) The memory is divided into two banks
b) The hardware is changed
c) The clock frequency is increased
d) None of the mentioned
View Answer

Answer: a
Explanation: The division of memory into two banks makes
it easy to access two different words at each edge of the
clock.

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Computer Organisation and Architecture.

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Large Memories - Computer

Organization Questions and
Answers
by Manish
3-4 minutes

This set of Computer Organization and Architecture Multiple

Choice Questions & Answers (MCQs) focuses on “Large
Memories”.

1. The chip can be disabled or cut off from external

connection using ______
a) Chip select
b) LOCK
c) ACPT
d) RESET
View Answer

Answer: a
Explanation: The chip gets enabled if the CS is set
otherwise the chip gets disabled.

2. To organise large memory chips we make use of ______

a) Integrated chips
b) Upgraded hardware
c) Memory modules

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d) None of the mentioned

View Answer

Answer: c
Explanation: The cell blocks are arranged and put in a
memory module.

3. The less space consideration as lead to the development

of ________ (for large memories).
a) SIMM’s
b) DIMS’s
c) SSRAM’s
d) Both SIMM’s and DIMS’s
View Answer

Answer: d
Explanation: The SIMM (single inline memory module) or
DIMM (dual inline memory module) occupy less space while
providing greater memory space.

4. The SRAM’s are basically used as ______

a) Registers
b) Caches
c) TLB
d) Buffer
View Answer

Answer: b
Explanation: The SRAM’s are used as caches as their
opeartion speed is very high.

5. The higher order bits of the address are used to _____

a) Specify the row address

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b) Specify the column address

c) Input the CS
d) None of the mentioned
View Answer

Answer: a
Explanation: None.

6. The address lines multiplexing is done using ______

a) MMU
b) Memory controller unit
c) Page table
d) Overlay geberator
View Answer

Answer: b
Explanation: This unit multiplexes the various address lines
to lesser pins on the chip.

7. The controller multiplexes the addresses after getting the

_____ signal.
a) INTR
b) ACK
c) RESET
d) Request
View Answer

Answer: d
Explanation: The controller gets the request from the device
needing the memory read or write operation and then it
multiplexes the address.

8. The RAS and CAS signals are provided by the ______

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a) Mode register
b) CS
c) Memory controller
d) None of the mentioned
View Answer

Answer: c
Explanation: The multiplexed signal of the controller is split
into RAS and CAS.

9. Consider a memory organised into 8K rows, and that it

takes 4 cycles to complete a read opeartion. Then the
refresh overhead of the chip is ______
a) 0.0021
b) 0.0038
c) 0.0064
d) 0.0128
View Answer

Answer: b
Explanation: The refresh overhead is calculated by taking
into account the total time for refreshing and the interval of
each refresh.

10. When DRAM’s are used to build a complex large

memory,then the controller only provides the refresh
counter.
a) True
b) False
View Answer

Answer: a
Explanation: None.

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RamBus Memory - Computer

Organization Questions and
Answers
by Manish
3 minutes

This set of Computer Organization and Architecture Multiple

Choice Questions & Answers (MCQs) focuses on “RamBus
Memory”.

1. RamBUS is better than the other memory chips in terms

of
a) Efficiency
b) Speed of operation
c) Wider bandwidth
d) All of the mentioned
View Answer

Answer: b
Explanation: The RAMBUS is much advanced mode of
memory storage.

2. The key feature of the RAMBUS tech is ________

a) Greater memory utilisation
b) Effeciency
c) Speed of transfer

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d) None of the mentioned

View Answer

Answer: c
Explanation: The RAMBUS was developed basically to
lessen the data transfer time.

3. The increase in operation speed is done by

a) Reducing the reference voltage
b) Increasing the clk frequency
c) Using enhanced hardware
d) None of the mentioned
View Answer

Answer: a
Explanation: The reference voltage is reduced from the
Vsupply about 2v.

4. The data is transfered over the RAMBUS as _______

a) Packets
b) Blocks
c) Swing voltages
d) Bits
View Answer

Answer: c
Explanation: By using voltage swings to transfer data,
transfer rate along with efficiency is improved.

5. The type of signaling used in RAMBUS is ______

a) CLK signalling
b) Differential signalling
c) Integral signalling

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d) None of the mentioned

View Answer

Answer: b
Explanation: The differential signaling basically means
using voltage swings to transmit data.

6. The special communication used in RAMBUS are

_________
a) RAMBUS channel
b) D-link
c) Dial-up
d) None of the mentioned
View Answer

Answer: a
Explanation: The special communication link is used to
provide the necessary deign and required hardware for the
transmission.

7. The original design of the RAMBUS required for

________ data lines.
a) 4
b) 6
c) 8
d) 9
View Answer

Answer: d
Explanation: Out of the 9 data lines, 8 were used for data
transmission and the one left was used for parity checking.

8. The RAMBUS requires specially designed memory chips

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similar to _____
a) SRAM
b) SDRAM
c) DRAM
d) DDRRAM
View Answer

Answer: c
Explanation: The special memory chip should be able to
transmit data on both the edges and is called as RDRAM’s.

9. A RAMBUS which has 18 data lines is called as _______

a) Extended RAMBUS
b) Direct RAMBUS
c) Multiple RAMBUS
d) Indirect RAMBUS
View Answer

Answer: b
Explanation: The direct RAMBUS is used to transmit 2
bytes of data at a time.

10. The RDRAM chips assembled into larger memory

modules called ______
a) RRIM
b) DIMM
c) SIMM
d) All of the mentioned
View Answer

Answer: a
Explanation: None.

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Read-Only Memory - Computer

Organization Questions and
Answers
by Manish
4-5 minutes

This set of Computer Organization and Architecture Multiple

Choice Questions & Answers (MCQs) focuses on “Read-
Only Memory”.

1. If the transistor gate is closed, then the ROM stores a

value of 1.
a) True
b) False
View Answer

Answer: b
Explanation: If the gate of the transistor is closed then, the
value of zero is stored in the ROM.

2. PROM stands for __________

a) Programmable Read Only Memory
b) Pre-fed Read Only Memory
c) Pre-required Read Only Memory
d) Programmed Read Only Memory
View Answer

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Answer: a
Explanation: It allows the user to program the ROM.

3. The PROM is more effective than ROM chips in regard to

_______
a) Cost
b) Memory management
c) Speed of operation
d) Both Cost and Speed of operation
View Answer

Answer: d
Explanation: The PROM is cheaper than ROM as they can
be programmed manually.

4. The difference between the EPROM and ROM circuitory

is _____
a) The usage of MOSFET’s over transistors
b) The usage of JFET’s over transistors
c) The usage of an extra transistor
d) None of the mentioned
View Answer

Answer: c
Explanation: The EPROM uses an extra transistor where
the ground connection is there in the ROM chip.

5. The ROM chips are mainly used to store _______

a) System files
b) Root directories
c) Boot files
d) Driver files
View Answer

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Answer: c
Explanation: The ROM chips are used to store boot files
required for the system start up.

6. The contents of the EPROM are earsed by ________

a) Overcharging the chip
b) Exposing the chip to UV rays
c) Exposing the chip to IR rays
d) Discharging the Chip
View Answer

Answer: b
Explanation: To erase the contents of the EPROM the chip
is exposed to the UV rays, which disipate the charge on the
transistor.

7. The disadvantage of the EPROM chip is _______

a) The high cost factor
b) The low efficiency
c) The low speed of operation
d) The need to remove the chip physically to reprogram it
View Answer

Answer: d
Explanation: None.

8. EEPROM stands for Electrically Erasable Programmable

Read Only Memory.
a) True
b) False
View Answer

Answer: a

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Explanation: The disadvantages of the EPROM led to the

development of the EEPROM.

9. The disadvantage of the EEPROM is/are ________

a) The requirement of different voltages to read,write and
store information
b) The Latency inread operation
c) The inefficient memory mapping schemes used
d) All of the mentioned
View Answer

Answer: a
Explanation: None.

10. The memory devices which are similar to EEPROM but

differ in the cost effectiveness is ______
a) Memory sticks
b) Blue-ray devices
c) Flash memory
d) CMOS
View Answer

Answer: c
Explanation: The flash memory functions similar to the
EEPROM but is much cheaper.

11. The only difference between the EEPROM and flash

memory is that the latter doesn’t allow bulk data to be
written.
a) True
b) False
View Answer

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Answer: a
Explanation: This is not permitted as the previous contents
of the cells will be over written.

12. The flash memories find application in ______

a) Super computers
b) Mainframe systems
c) Distributed systems
d) Portable devices
View Answer

Answer: d
Explanation: The flash memories low power requirement
enables them to be used in a wide range of hand held
devices.

13. The memory module obtained by placing a number of

flash chips for higher memory storage called as _______
a) FIMM
b) SIMM
c) Flash card
d) RIMM
View Answer

Answer: c
Explanation: None.

14. The flash memory modules designed to replace the

functioning of an harddisk is ______
a) RIMM
b) Flash drives
c) FIMM
d) DIMM

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View Answer

Answer: b
Explanation: The flash drives have been developed to
provide faster operation but with lesser space.

15. The reason for the fast operating speeds of the flash
drives is
a) The absence of any movable parts
b) The itegarated electronic hardware
c) The improved bandwidth connection
d) All of the mentioned
View Answer

Answer: a
Explanation: Since the flash drives have no movable parts
their access and seeks times are reasonably reduced.

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Memory Heirarchy - Computer

Organization Questions and
Answers
by Manish
3-4 minutes

This set of Computer Organization and Architecture Multiple

Choice Questions & Answers (MCQs) focuses on
“Heirarchy of Memory”.

1. The standard SRAM chips are costly as _________

a) They use highly advanced micro-electronic devices
b) They house 6 transistor per chip
c) They require specially designed PCB’s
d) None of the mentioned
View Answer

Answer: b
Explanation: As they require a large number of transistors,
their cost per bit increases.

2. The drawback of building a large memory with DRAM is

______________
a) The large cost factor
b) The inefficient memory organisation
c) The Slow speed of operation

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d) All of the mentioned

View Answer

Answer: c
Explanation: The DRAM’s were used for large memory
modules for a long time until a substitute was found.

3. To overcome the slow operating speeds of the secondary

memory we make use of faster flash drives.
a) True
b) False
View Answer

Answer: a
Explanation: To improve the speed we use flash drives at
the cost of memory space.

4. The fastest data access is provided using _______

a) Caches
b) DRAM’s
c) SRAM’s
d) Registers
View Answer

Answer: d
Explanation: The fastest data access is provided using
registers as these memory locations are situated inside the
processor.

5. The memory which is used to store the copy of data or

instructions stored in larger memories, inside the CPU is
called _______
a) Level 1 cache

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b) Level 2 cache
c) Registers
d) TLB
View Answer

Answer: a
Explanation: These memory devices are generally used to
map onto the data stored in the larger memories.

6. The larger memory placed between the primary cache

and the memory is called ______
a) Level 1 cache
b) Level 2 cache
c) EEPROM
d) TLB
View Answer

Answer: b
Explanation: This is basically used to provide effective
memory mapping.

7. The next level of memory hierarchy after the L2 cache is

_______
a) Secondary storage
b) TLB
c) Main memory
d) Register
View Answer

Answer: d
Explanation: None.

8. The last on the hierarchy scale of memory devices is

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______
a) Main memory
b) Secondary memory
c) TLB
d) Flash drives
View Answer

Answer: b
Explanation: The secondary memory is the slowest memory
device.

9. In the memory hierarchy, as the speed of operation

increases the memory size also increases.
a) True
b) False
View Answer

Answer: b
Explanation: As the speed of operation increases the cost
increases and the size decreases.

10. If we use the flash drives instead of the harddisks, then

the secondary storage can go above primary memory in the
hierarchy.
a) True
b) False
View Answer

Answer: b
Explanation: The flash drives will increase the speed of
transfer but still it wont be faster than primary memory.

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Computer Organisation and Architecture.

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Caches - Computer Organization

Questions and Answers
by Manish
4-5 minutes

This set of Computer Organization and Architecture Multiple

Choice Questions & Answers (MCQs) focuses on “Caches”.

1. The reason for the implementation of the cache memory

is ________
a) To increase the internal memory of the system
b) The difference in speeds of operation of the processor
and memory
c) To reduce the memory access and cycle time
d) All of the mentioned
View Answer

Answer: b
Explanation: This difference in the speeds of operation of
the system caused it to be inefficient.

2. The effectiveness of the cache memory is based on the

property of ________
a) Locality of reference
b) Memory localisation
c) Memory size

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d) None of the mentioned

View Answer

Answer: a
Explanation: This means that the cache depends on the
location in the memory that is referenced often.

3. The temporal aspect of the locality of reference means

a) That the recently executed instruction wont be executed
soon
b) That the recently executed instruction is temporarily not
referenced
c) That the recently executed instruction will be executed
soon again
d) None of the mentioned
View Answer

Answer: c
Explanation: None.

4. The spatial aspect of the locality of reference means

a) That the recently executed instruction is executed again
next
b) That the recently executed wont be executed again
c) That the instruction executed will be executed at a later
time
d) That the instruction in close proximity of the instruction
executed will be executed in future
View Answer

Answer: d
Explanation: The spatial aspect of locality of reference tells
that the nearby instruction is more likely to be executed in

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future.

5. The correspondence between the main memory blocks

and those in the cache is given by _________
a) Hash function
b) Mapping function
c) Locale function
d) Assign function
View Answer

Answer: b
Explanation: The mapping function is used to map the
contents of the memory to the cache.

6. The algorithm to remove and place new contents into the

cache is called _______
a) Replacement algorithm
b) Renewal algorithm
c) Updation
d) None of the mentioned
View Answer

Answer: a
Explanation: As the cache gets full, older contents of the
cache are swapped out with newer contents. This decision
is taken by the algorithm.

7. The write-through procedure is used

a) To write onto the memory directly
b) To write and read from memory simultaneously
c) To write directly on the memory and the cache
simultaneously
d) None of the mentioned

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View Answer

Answer: c
Explanation: When write operation is issued then the
corresponding operation is performed.

8. The bit used to signify that the cache location is updated

is ________
a) Dirty bit
b) Update bit
c) Reference bit
d) Flag bit
View Answer

Answer: a
Explanation: When the cache location is updated in order to
signal to the processor this bit is used.

9. The copy-back protocol is used

a) To copy the contents of the memory onto the cache
b) To update the contents of the memory from the cache
c) To remove the contents of the cache and push it on to
the memory
d) None of the mentioned
View Answer

Answer: b
Explanation: This is another way of performing the write
operation,wherein the cache is updated first and then the
memory.

10. The approach where the memory contents are

transfered directly to the processor from the memory is

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called ______
a) Read-later
b) Read-through
c) Early-start
d) None of the mentioned
View Answer

Answer: c
Explanation: None.

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Mapping Functions - Computer

Organization Questions and
Answers
by Manish
4-5 minutes

This set of Computer Organization and Architecture Multiple

Choice Questions & Answers (MCQs) focuses on “Mapping
Functions”.

1. The memory blocks are mapped on to the cache with the

help of ______
a) Hash functions
b) Vectors
c) Mapping functions
d) None of the mentioned
View Answer

Answer: c
Explanation: The mapping functions are used to map the
memory blocks on to their corresponding cache block.

2. During a write operation if the required block is not

present in the cache then ______ occurs.
a) Write latency
b) Write hit

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c) Write delay
d) Write miss
View Answer

Answer: d
Explanation: This indicates that the operation has missed
and it brings the required block into cache.

3. In ________ protocol the information is directly written

into main memory.
a) Write through
b) Write back
c) Write first
d) None of the mentioned
View Answer

Answer: a
Explanation: In case of the miss, then the data gets written
directly in main memory.

4. The only draw back of using the early start protocol is

_______
a) Time delay
b) Complexity of circuit
c) Latency
d) High miss rate
View Answer

Answer: b
Explanation: In this protocol, the required block is read and
directly sent to the processor.

5. The method of mapping the consecutive memory blocks

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to consecutive cache blocks is called ______

a) Set associative
b) Associative
c) Direct
d) Indirect
View Answer

Answer: c
Explanation: This method is most simple to implement as it
involves direct mapping of memory blocks.

6. While using the direct mapping technique, in a 16 bit

system the higher order 5 bits is used for ________
a) Tag
b) Block
c) Word
d) Id
View Answer

Answer: a
Explanation: The tag is used to identify the block mapped
onto one particular cache block.

7. In direct mapping the presence of the block in memory is

checked with the help of block field.
a) True
b) False
View Answer

Answer: b
Explanation: The tag field is usd to check the presence of a
mem block.

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8. In associative mapping, in a 16 bit system the tag field

has ______ bits.
a) 12
b) 8
c) 9
d) 10
View Answer

Answer: a
Explanation: The Tag field is used as an id for the different
memory blocks mapped to the cache.

9. The associative mapping is costlier than direct mapping.

a) True
b) False
View Answer

Answer: a
Explanation: In associative mapping all the tags have to be
searched to find the block.

10. The technique of searching for a block by going through

all the tags is ______
a) Linear search
b) Binary search
c) Associative search
d) None of the mentioned
View Answer

Answer: c
Explanation: None.

11. The set associative map technique is a combination of

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the direct and associative technique.

a) True
b) False
View Answer

Answer: a
Explanation: The combination of the efficiency of the
associative method and the cheapness of the direct
mapping, we get the set-associative mapping.

12. In set-associative technique, the blocks are grouped

into ______ sets.
a) 4
b) 8
c) 12
d) 6
View Answer

Answer: d
Explanation: The set-associative technique groups the
blocks into different sets.

13. A control bit called ____ has to be provided to each

blocj in set-associative.
a) Idol bit
b) Valid bit
c) Reference bit
d) All of the mentioned
View Answer

Answer: b
Explanation: The valid bit is used to indicate that the block
holds valid information.

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14. The bit used to indicate whether the block was recently
used or not is _______
a) Idol bit
b) Control bit
c) Refernece bit
d) Dirty bit
View Answer

Answer: d
Explanation: The dirty bit is used to show that the block was
recently modified and for replacement algorithm.

15. Data which is not up-to date is called as _______

a) Spoilt data
b) Stale data
c) Dirty data
d) None of the mentioned
View Answer

Answer: b
Explanation: None.

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Cache Miss & Hit - Computer

Organization Questions and
Answers
by Manish
3-4 minutes

This set of Computer Organization and Architecture Multiple

Choice Questions & Answers (MCQs) focuses on “Cache
Miss and Hit”.

1. The main memory is structured into modules each with

its own address register called ______
a) ABR
b) TLB
c) PC
d) IR
View Answer

Answer: a
Explanation: ABR stands for Address Buffer Register.

2. When consecutive memory locations are accessed only

one module is accessed at a time.
a) True
b) False
View Answer

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Answer: a
Explanation: In modular approach to memory structuring
only one module can be accessed at a time.

3. In memory interleaving, the lower order bits of the

address is used to
a) Get the data
b) Get the address of the module
c) Get the address of the data within the module
d) None of the mentioned
View Answer

Answer: b
Explanation: To implement parallelism in data access we
use interleaving.

4. The number successful accesses to memory stated as a

fraction is called as _____
a) Hit rate
b) Miss rate
c) Success rate
d) Access rate
View Answer

Answer: a
Explanation: The hit rate is a important factor in
performance measurement.

5. The number failed attempts to access memory, stated in

the form of fraction is called as _________
a) Hit rate
b) Miss rate
c) Failure rate

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d) Delay rate
View Answer

Answer: b
Explanation: The miss rate is key factor in deciding the type
of replacement algorithm.

6. In associative mapping during LRU, the counter of the

new block is set to ‘0’ and all the others are incremented by
one,when _____ occurs.
a) Delay
b) Miss
c) Hit
d) Delayed hit
View Answer

Answer: b
Explanation: Miss usually occurs when the memory block
requiered is not present in the cache.

7. In LRU, the refrenced blocks counter is set to’0′ and that

of the previous blocks are incremented by one and others
remain same, in case of ______
a) Hit
b) Miss
c) Delay
d) None of the mentioned
View Answer

Answer: a
Explanation: If the referenced block is present in the
memory it is called as hit.

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8. If hit rates are well below 0.9, then they’re called as

speedy computers.
a) True
b) False
View Answer

Answer: b
Explanation: It has to be above 0.9 for speedy computers.

9. The extra time needed to bring the data into memory in

case of a miss is called as _____
a) Delay
b) Propagation time
c) Miss penalty
d) None of the mentioned
View Answer

Answer: c
Explanation: None.

10. The miss penalty can be reduced by improving the

mechanisms for data transfer between the different levels of
hierarchy.
a) True
b) False
View Answer

Answer: a
Explanation: The extra time needed to bring the data into
memory in case of a miss is called as miss penalty.

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Single BUS Organisation -

Computer Organization Questions
and Answers
by Manish
3 minutes

This set of Computer Organization and Architecture Multiple

Choice Questions & Answers (MCQs) focuses on “Single
BUS Organisation”.

1. The CPU is also called as ________

a) Processor hub
b) ISP
c) Controller
d) All of the mentioned
View Answer

Answer: b
Explanation: ISP stands for Instruction Set Processor.

2. A common strategy for performance is making various

functional units operate parallely.
a) True
b) False
View Answer

Answer: a

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Explanation: By parallely accessing data we can have a

pipelined processor.

3. The PC gets incremented

a) After the instruction decoding
b) After the IR instruction gets executed
c) After the fetch cycle
d) None of the mentioned
View Answer

Answer: c
Explanation: The PC always points to the next instruction to
be executed.

4. Which register in the processor is single directional ?

a) MAR
b) MDR
c) PC
d) Temp
View Answer

Answer: a
Explanation: The MAR is single directional as it just takes
the address from the processor bus and passes it to the
external bus.

5. The transparent register/s is/are __________

a) Y
b) Z
c) Temp
d) All of the mentioned
View Answer

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Answer: d
Explanation: These registers are usually used to store
temporary values.

6. Which register is connected to the MUX ?

a) Y
b) Z
c) R0
d) Temp
View Answer

Answer: a
Explanation: The MUX can either read the operand from the
Y register or increment the PC.

7. The registers,ALU and the interconnecting path together

are called as ______
a) Control path
b) Flow path
c) Data path
d) None of the mentioned
View Answer

Answer: c
Explanation: None.

8. The input and output of the registers are governed by

__________
a) Transistors
b) Diodes
c) Gates
d) Switches
View Answer

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Answer: d
Explanation: None.

9. When two or more clock cycles are used to complete

data transfer it is called as ________
a) Single phase clocking
b) Multi-phase clocking
c) Edge triggered clocking
d) None of the mentioned
View Answer

Answer: b
Explanation: This is basically used in systems without edge-
triggered flip flops.

10. ________ signal is used to show complete of memory

operation.
a) MFC
b) WMFC
c) CFC
d) None of the mentioned
View Answer

Answer: a
Explanation: MFC stands for Memory Function Complete.

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sanfoundry.com

Computer Organization Questions

and Answers for Experienced
by mod2
3 minutes

This set of Computer Organization Questions and Answers

for Experienced people focuses on “Single BUS
Organisation-2”.

1. Is the below code segment correct, for the addition of two

numbers ?
R1in, Yin
R2out, Select Y, ADD , Zin
Zout, R3in
a) True
b) False
View Answer

Answer: a
Explanation: This is the gate transfer notation, which
indicates the usage of switches to control the flow of data.

2. The completion of the memroy operation is indicated

using ______ signal.
a) MFC
b) WMFC

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c) CFC
d) None of the mentioned
View Answer

Answer: a
Explanation: MFC stands for Memory Function Complete.

3. _________ signal enables the processor to wait for the

memory operation to complete.
a) MFC
b) TLB
c) WMFC
d) ALB
View Answer

Answer: c
Explanation: This signal stands for Wait For Memory
Function Complete.

4. The small extremly fast, RAM’s all called as ________

a) Cache
b) Heaps
c) Accumulators
d) Stacks
View Answer

Answer: b
Explanation: Cache’s are extremly essential in single BUS
organisation to achieve fast operation.

5. The main virtue for using single Bus structure is

a) Fast data transfers
b) Cost effective connectivity and speed

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c) Cost effective connectivity and ease of attaching

peripheral devices
d) None of the mentioned
View Answer

Answer: c
Explanation: None.

6. To extend the connectivity of the processor bus we use

______
a) PCI bus
b) SCSI bus
c) Controllers
d) Multiple bus
View Answer

Answer: a
Explanation: The PCI BUS basically is used to connect ot
memory devices.

7. The bus used to connect the monitor to the CPU is

a) PCI bus
b) SCSI bus
c) Memory bus
d) Rambus
View Answer

Answer: b
Explanation: The SCSI (Small Component System
Interconnect) is used to connect to display devices.

8. The ISA standard Buses are used to connect

___________

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a) RAM and processor

b) GPU and processor
c) Harddisk and Processor
d) CD/DVD drives and Processor
View Answer

Answer: c
Explanation: None.

9. ANSI stands for _____

a) American National Standards Institute
b) American National Standard Interface
c) American Network Standard Interfacing
d) American Network Security Interrupt
View Answer

Answer: a
Explanation: It is one of the standards of developing a BUS.

10. IBM developed a bus standard for their line of

computers ‘PC AT’ called
a) IB bus
b) M-bus
c) ISA
d) None of the mentioned
View Answer

Answer: c
Explanation: None.

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Multiple BUS Organistaion -

Computer Organization Questions
and Answers
by mod2
3-4 minutes

This set of Computer Organization and Architecture Multiple

Choice Questions & Answers (MCQs) focuses on “Multiple
BUS Organistaion”.

1. The general purpose registers are combined into a block

called as ______
a) Register bank
b) Register Case
c) Register file
d) None of the mentioned
View Answer

Answer: c
Explanation: To make the access of the registers easier, we
classify them into register files.

2. In ______ technology, the implementation of the register

file is by using an array of memory locations.
a) VLSI
b) ANSI

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c) ISA
d) ASCI
View Answer

Answer: a
Explanation: By doing so the access of the registers can be
made faster.

3. In a three BUS architecture, how many input and output

ports are there ?
a) 2 output and 2 input
b) 1 output and 2 input
c) 2 output and 1 input
d) 1 output and 1 input
View Answer

Answer: c
Explanation: That is enabling reading from two locations
and writting into one.

4. For a 3 BUS architecture, is the below code correct for

adding three numbers ?
PCout, R = B, MARin , READ, Inc PC
WMFC
MDRout, R = B, IRin
R4outa, R5outb, Select A, ADD, R6in, End
a) True
b) False
View Answer

Answer: a
Explanation: We have assumed the names of the three
BUSes has A, B and C.

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5. The main advantage of multiple bus organisation over

single bus is __________
a) Reduction in the number of cycles for execution
b) Increase in size of the registers
c) Better Connectivity
d) None of the mentioned
View Answer

Answer: a
Explanation: None.

6. CISC stands for _________

a) Complete Instruction Sequential Compilation
b) Computer Integrated Sequential Compiler
c) Complex Instruction Set Computer
d) Complex Instruction Sequential Compilation
View Answer

Answer: c
Explanation: The CISC machines are well adept at handling
multiple BUS organisation.

7. If the instruction Add R1,R2,R3 is executed in a system

which is pipelined, then the value of S is (Where S is term
of the Basic performance equation).
a) 3
b) ~2
C) ~1
d) 6
View Answer

Answer: c
Explanation: The value will be much lower in case of

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multiple BUS organisation.

8. In multiple BUS organisation __________ is used to

select any of the BUSes for input into ALU.
a) MUX
b) DE-MUX
c) En-CDS
d) None of the mentioned
View Answer

Answer: a
Explanation: The MUX can be used to either select the BUS
or to increment the PC.

9. There exists a seperate block consisting of various units

to decode an instruction.
a) True
b) False
View Answer

Answer: a
Explanation: This block is used to decode the instruction
and place it in the IR.

10. There exists a seperate block to increment the PC in

multiple BUS organisation.
a) True
b) False
View Answer

Answer: a
Explanation: None.

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Computer Organisation and Architecture.

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Hardwired Control - Computer

Organization Questions and
Answers
by mod2
3-4 minutes

This set of Computer Organization and Architecture Multiple

Choice Questions & Answers (MCQs) focuses on “”.

1. ________ are the different type/s of generating control

signals.
a) Micro-programmed
b) Hardwired
c) Micro-instruction
d) Both Micro-programmed and Hardwired
View Answer

Answer: d
Explanation: The above are used to generate control
signals in different types of system architectures.

2. The type of control signal are generated based on,

a) contents of the step counter
b) Contents of IR
c) Contents of condition flags
d) All of the mentioned

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View Answer

Answer: d
Explanation: Based on the information above the type of
control signal is decided.

3. What does the hardwired control generator consist of ?

a) Decoder/encoder
b) Condition codes
c) Control step counter
d) All of the mentioned
View Answer

Answer: d
Explanation: The CU uses the above blocks and IR to
produce the necessary signal.

4. What does the end instruction do ?

a) It ends the generation of a signal
b) It ends the complete generation process
c) It starts a new instruction fetch cycle and resets the
counter
d) It is used to shift the control to the processor
View Answer

Answer: c
Explanation: It is basically used to start the generation of a
new signal.

5. The Zin signal to the processor is generated using, Zin =

T1+T6 ADD + T4 .BR…
a) True
b) False

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View Answer

Answer: a
Explanation: The signal is generated using the logic of the
formula above.

6. What does the RUN signal do ?

a) It causes the termination of a signal
b) It causes a particular signal to perform its operation
c) It causes a particular signal to end
d) It increments the step counter by one
View Answer

Answer: d
Explanation: The RUN signal increments the step counter
by one for each clock cycle.

7. The name hardwired came because the sequence of

operations carried out are determined by the wiring.
a) True
b) False
View Answer

Answer: a
Explanation: In other words hardwired is another name for
Hardware Control signal generator.

8. The benefit of using this approach is

a) It is cost effective
b) It is highly efficient
c) It is very reliable
d) It increases the speed of operation
View Answer

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Answer: d
Explanation: None.

9. The disadvantage/s of the hardwired approach is

a) It is less flexible
b) It cannot be used for complex instructions
c) It is costly
d) less flexible & cannot be used for complex instructions
View Answer

Answer: d
Explanation: The more complex the instruction set less
applicable is hardwired approach.

10. The End signal is generated using, End = T7.ADD +

T5.BR + (T5.N+ T4.-N).BRN…
a) True
b) False
View Answer

Answer: a
Explanation: None.

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Computer Organization Problems -

Sanfoundry
by mod2
3-4 minutes

This set of Computer Organization Problems focuses on

“Microprogrammed Control”.

1. In micro-programmed approach, the signals are

generated by ______
a) Machine instructions
b) System programs
c) Utility tools
d) None of the mentioned
View Answer

Answer: a
Explanation: The machine instructions generate the signals.

2. A word whose individual bits represent a control signal is

______
a) Command word
b) Control word
c) Co-ordination word
d) Generation word
View Answer

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Answer: b
Explanation: The control word is used to get the different
types of control signals required.

3. A sequence of control words corresponding to a control

sequence is called _______
a) Micro routine
b) Micro function
c) Micro procedure
d) None of the mentioned
View Answer

Answer: a
Explanation: The micro routines are used to perform a
particular task.

4. Individual control words of the micro routine are called as

______
a) Micro task
b) Micro operation
c) Micro instruction
d) Micro command
View Answer

Answer: c
Explanation: The each instruction which put together
performs the task.

5. The special memory used to store the micro routines of a

computer is ________
a) Control table
b) Control store
c) Control mart

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d) Control shop
View Answer

Answer: b
Explanation: The control store is used as a reference to get
the required control routine.

6. To read the control words sequentially _________ is

used.
a) PC
b) IR
c) UPC
d) None of the mentioned
View Answer

Answer: c
Explanation: The UPC stands for Micro program counter.

7. Every time a new instruction is loaded into IR the output

of ________ is loaded into UPC.
a) Starting address generator
b) Loader
c) Linker
d) Clock
View Answer

Answer: a
Explanation: The starting address generator is used to load
the address of the next micro instruction.

8. The case/s where micro-programmed can perform well

a) When it requires to check the condition codes
b) When it has to choose between the two alternatives

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c) When it is triggered by an interrupt

d) None of the mentioned
View Answer

Answer: d
Explanation: None.

9. The signals are grouped such that mutually exclusive

signals are put together.
a) True
b) False
View Answer

Answer: a
Explanation: This is done to improve the efficiency of the
controller.

10. Highly encoded schemes that use compact codes to

specify a small number of functions in each micro
instruction is ________
a) Horizontal organisation
b) Vertical organisation
c) Diagonal organisation
d) None of the mentioned
View Answer

Answer: b
Explanation: None.

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Replacement Algorithms -
Computer Organization Questions
and Answers
by Manish
3-4 minutes

This set of Computer Organization and Architecture Multiple

Choice Questions & Answers (MCQs) focuses on
“Replacement Algorithms”.

1. The directly mapped cache no replacement algorithm is

required.
a) True
b) False
View Answer

Answer: a
Explanation: The position of each block is pre-determined in
the direct mapped cache, hence not need for replacement.

2. The surroundings of the recently accessed block is called

as ______
a) Neighbourhood
b) Neighbour
c) Locality of reference
d) None of the mentioned

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View Answer

Answer: c
Explanation: The locality of reference is a key factor in
many of the replacement algorithms.

3. In set associative and associative mapping there exists

less flexibility.
a) True
b) False
View Answer

Answer: b
Explanation: The above two methods of mapping the
descision of which block to be removed rests with the cache
controller.

4. THe algorithm which replaces the block which has not

been referenced for awhile is called _____
a) LRU
b) ORF
c) Direct
d) Both LRU and ORF
View Answer

Answer: a
Explanation: LRU stands for Least Recently Used first.

5. In associative mapping during LRU, the counter of the

new block is set to ‘0’ and all the others are incremented by
one, when _____ occurs.
a) Delay
b) Miss

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c) Hit
d) Delayed hit
View Answer

Answer: b
Explanation: Miss usually occurs when the memory block
requiered is not present in the cache.

6. The LRU provides very bad performance when it comes

to _________
a) Blocks being accessed is sequential
b) When the blocks are ramdomised
c) When the consecutive blocks accessed are in the
extremes
d) None of the mentioned
View Answer

Answer: a
Explanation: The LRU in case of the sequential blocks as to
waste its one cycle just incrementing the counters.

7. The algorithm which removes the recently used page first

is ________
a) LRU
b) MRU
c) OFM
d) None of the mentioned
View Answer

Answer: b
Explanation: In MRU it is assumed that the page accessed
now is less likely to be accessed again.

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8. The LRU can be improved by providing a little

randomness in the access.
a) True
b) False
View Answer

Answer: a
Explanation: None.

9. In LRU, the referenced blocks counter is set to’0′ and that

of the previous blocks are incremented by one and others
remain same, in case of ______
a) Hit
b) Miss
c) Delay
d) None of the mentioned
View Answer

Answer: a
Explanation: If the referenced block is present in the
memory it is called as hit.

10. The counter that keeps track of how many times a block
is most likely used is _______
a) Count
b) Reference counter
c) Use counter
d) Probable counter
View Answer

Answer: b
Explanation: None.

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Computer Organisation and Architecture.

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Caches Performance - Computer

Organization Questions and
Answers
by Manish
3-4 minutes

This set of Computer Organization and Architecture Multiple

Choice Questions & Answers (MCQs) focuses on
“Performance of Caches”.

1. The key factor/s in commercial success of a computer

is/are ________
a) Performance
b) Cost
c) Speed
d) Both Performance and Cost
View Answer

Answer: d
Explanation: The performance and cost of the computer
system is key decider in the commercial success of the
system.

2. The main objective of the computer system is

a) To provide optimal power operation
b) To provide best performance at low cost

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c) To provide speedy operation at low power consumption

d) All of the mentioned
View Answer

Answer: b
Explanation: An optimal system provides best performance
at low costs.

3. A common measure of performance is

a) Price/performance ratio
b) Performance/price ratio
c) Operation/price ratio
d) None of the mentioned
View Answer

Answer: a
Explanation: If this measure is less than one then the
system is optimal.

4. The performance depends on

a) The speed of execution only
b) The speed of fetch and execution
c) The speed of fetch only
d) The hardware of the system only
View Answer

Answer: b
Explanation: The performance of a system is decided by
how quick an instruction is brought into the system and
executed.

5. The main purpose of having memory hierarchy is to

a) Reduce access time

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b) Provide large capacity

c) Reduce propagation time
d) Reduce access time & Provide large capacity
View Answer

Answer: d
Explanation: By using the memory Hierarchy, we can
increase the performance of the system.

6. The memory transfers between two variable speed

devices is always done at the speed of the faster device.
a) True
b) False
View Answer

Answer: a
Explanation: None.

7. An effective to introduce parallelism in memory access is

by _______
a) Memory interleaving
b) TLB
c) Pages
d) Frames
View Answer

Answer: a
Explanation: Interleaving divides the memory into modules.

8. The performance of the system is greatly influenced by

increasing the level 1 cache.
a) True
b) False

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View Answer

Answer: a
Explanation: This is so because the L1 cache is onboard
the processor.

9. Two processors A and B have clock frequencies of 700

Mhz and 900 Mhz respectively. Suppose A can execute an
instruction with an average
of 3 steps and B can execute with an average of 5
steps.For the execution of the same instruction which
processor is faster
a) A
b) B
C) Both take the same time
d) Insufficient information
View Answer

Answer: a
Explanation: None.

10.If the instruction Add R1, R2, R3 is executed in a system

which is pipelined, then the value of S is (Where S is term
of the Basic performance equation)
a) 3
b) ~2
C) ~1
d) 6
View Answer

Answer: c
Explanation: Pipelining is a process of fetching an
instruction during the execution of other instruction.

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Virtual Memory - Computer

Organization Questions and
Answers
by mod2
3 minutes

This set of Computer Organization and Architecture Multiple

Choice Questions & Answers (MCQs) focuses on “Virtual
Memory”.

1. The physical memory is not as large as the address

space spanned by the processor.
a) True
b) False
View Answer

Answer: a
Explanation: This is one of the main reasons for the usage
of virtual memories.

2. The program is divided into operable parts called as

_________
a) Frames
b) Segments
c) Pages
d) Sheets

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View Answer

Answer: b
Explanation: The program is divided into parts called as
segments for ease of execution.

3. The techniques which move the program blocks to or

from the physical memory is called as ______
a) Paging
b) Virtual memory organisation
c) Overlays
d) Framing
View Answer

Answer: b
Explanation: By using this technique the program execution
is accomplished with usage of less space.

4. The binary address issued to data or instructions are

called as ______
a) Physical address
b) Location
c) Relocatable address
d) Logical address
View Answer

Answer: d
Explanation: The logical address is the random address
generated by the processor.

5. __________is used to implement virtual memory

organisation.
a) Page table

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b) Frame table
c) MMU
d) None of the mentioned
View Answer

Answer: c
Explanation: The MMU stands for Memory Management
Unit.

6. ______ translates logical address into physical address.

a) MMU
b) Translator
c) Compiler
d) Linker
View Answer

Answer: a
Explanation: The MMU translates the logical address into
physical address by adding an offset.

7. The main aim of virtual memory organisation is

a) To provide effective memory access
b) To provide better memory transfer
c) To improve the execution of the program
d) All of the mentioned
View Answer

Answer: d
Explanation: None.

8. The DMA doesn’t make use of the MMU for bulk data
transfers.
a) True

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b) False
View Answer

Answer: b
Explanation: The DMA stands for Direct Memory Access,in
which a block of data gets directly transferred from the
memory.

9. The virtual memory basically stores the next segment of

data to be executed on the _________
a) Secondary storage
b) Disks
c) RAM
d) ROM
View Answer

Answer: a
Explanation: None.

10. The asscociatively mapped virtual memory makes use

of _______
a) TLB
b) Page table
c) Frame table
d) None of the mentioned
View Answer

Answer: a
Explanation: TLB stands for Translation Look-aside Buffer.

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Secondary Storage - Computer

Organization Questions and
Answers
by mod2
3-4 minutes

This set of Computer Organization and Architecture Multiple

Choice Questions & Answers (MCQs) focuses on
“Secondary Storage – 1”.

1. The main reason for the discontinuation of semi

conductor based storage devices for providing large
storage space is _________
a) Lack of sufficient resources
b) High cost per bit value
c) Lack of speed of operation
d) None of the mentioned
View Answer

Answer: b
Explanation: In case of semi conductor based memory
technology, we get speed but the increase in the integration
of various devices the cost is high.

2. The digital information is stored on the hard disk by

____________

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a) Applying a suitable electric pulse

b) Applying a suitable magnetic field
c) Applying a suitable nuclear field
d) By using optic waves
View Answer

Answer: a
Explanation: The digital data is sorted on the magnetized
discs by magnetizing the areas.

3. For the synchronization of the read head, we make use

of a _______
a) Framing bit
b) Synchronization bit
c) Clock
d) Dirty bit
View Answer

Answer: c
Explanation: The clock makes it easy to distinguish
between different values red by head.

4. On of the most widely used schemes of encoding used is

_________
a) NRZ-polar
b) RZ-polar
c) Manchester
d) Block encoding
View Answer

Answer: c
Explanation: The Manchester encoding used is also called
as phase encoding and it is used to encode both clock and

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data.

5. The drawback of Manchester encoding is _________

a) The cost of the encoding scheme
b) The speed of encoding the data
c) The Latency offered
d) The low bit storage density provided
View Answer

Answer: d
Explanation: The space required to represent each bit must
be large enough to accommodate two changes in
magnetization.

6. The read/write heads must be near to disk surfaces for

better storage.
a) True
b) False
View Answer

Answer: a
Explanation: By maintaining the heads near to the surface
greater bit densities can be achieved.

7. _____ pushes the heads away from the surface as they

rotate at their standard rates.
a) Magnetic tension
b) Electric force
c) Air pressure
d) None of the mentioned
View Answer

Answer: c

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Explanation: Due to the speed of rotation of the discs air

pressure develops in the hard disk.

8. The air pressure can be countered by putting ______ in

the head-disc surface arrangement.
a) Air filter
b) Spring mechanism
c) coolant
d) None of the mentioned
View Answer

Answer: b
Explanation: The spring mechanism pushes the head along
the surface to reduce the air pressure effect.

9. The method of placing the heads and the discs in an air

tight environment is called as ______
a) RAID Arrays
b) ATP tech
c) Winchester technology
d) Fleming reduction
View Answer

Answer: c
Explanation: The Disks and the heads operate faster due to
the absence of the dust particles.

10. A hard disk with 20 surfaces will have _____ heads.

a) 10
b) 5
c) 1
d) 20
View Answer

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Answer: d
Explanation: Each surface will have its own head to perform
read/write operation.

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Computer Organization Interview

Questions and Answers for
Experienced
by mod2
3 minutes

This set of Computer Organization Interview Questions and

Answers for Experienced people focuses on “Secondary
Storage – 2”.

1. The disk system consists of which of the following:

i. Disk
ii. Disk drive
iii. Disk controller
a) i and ii
b) i ,ii and iii
c) ii and iii
d) i
View Answer

Answer: b
Explanation: None.

2. The set of corresponding tracks on all surfaces of a stack

of disks form a ______
a) Cluster

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b) Cylinder
c) Group
d) Set
View Answer

Answer: b
Explanation: The data is stored in the these sections called
as cylinders.

3. The data can be accessed from the disk using

_________
a) Surface number
b) Sector number
c) Track number
d) All of the mentioned
View Answer

Answer: d
Explanation: None.

4. The read and write operations usually start at ______ of

the sector.
a) Center
b) Middle
c) From the last used point
d) Boundaries
View Answer

Answer: d
Explanation: The heads read and write data from the ends
to the center.

5. To distinguish between two sectors we make use of

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________
a) Inter sector gap
b) Splitting bit
c) Numbering bit
d) None of the mentioned
View Answer

Answer: a
Explanation: This means that we leave a little gap between
each sectors to differentiate between them.

6. The _____ process divides the disk into sectors and

tracks.
a) Creation
b) Initiation
c) Formatting
d) Modification
View Answer

Answer: c
Explanation: The formatting process deletes the data
present and does the creation of sectors and tracks.

7. The access time is composed of __________

a) Seek time
b) Rotational delay
c) Latency
d) Both Seek time and Rotational delay
View Answer

Answer: d
Explanation: The seek time refers to the time required to
move the head to the required disk.

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‘
8. The disk drive is connected to the system by using the
_____
a) PCI bus
b) SCSI bus
c) HDMI
d) ISA
View Answer

Answer: b
Explanation: None.

9. _______ is used to deal with the difference in the transfer

rates between the drive and the bus.
a) Data repeaters
b) Enhancers
c) Data buffers
d) None of the mentioned
View Answer

Answer: c
Explanation: The buffers are added to store the data from
the fast device and to send it to the slower device at its rate.

10. _______ is used to detect and correct the errors that

may occur during data transfers.
a) ECC
b) CRC
c) Checksum
d) None of the mentioned
View Answer

Answer: a

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Explanation: ECC stands for Error Correcting Code.

Sanfoundry Global Education & Learning Series –

Computer Organisation and Architecture.

5 of 5 3/19/18, 2:08 PM