1991 Intel 8-Bit Embedded Controller Handbook PDF
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FLAVIO1991 Intel 8-Bit Embedded Controller Handbook PDF
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8-BIT
EMBEDDED CONTROLLER
HANDBOOK
1991
About Our Cover.'
Thinkers, inventors, and artists throughout history have breathed
life into their ideas by converting them into rough working sketches, models,
and products. This series of covers shows a few of these creations, along
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MCS® .. 48 Single Component
System
MCS® .. 48 Expanded
System
MCS® .. 48 Instruction Set
MCS® .. 48 Data Sheets
MCS® .. 51 Architectural
Overview
MCS® .. 51 Programmer's Guide
and Instruction Set
MCS® .. 51 Hardware
Description and Data Sheets
8XC51FX Hardware
Description and Data Sheets
8XF 51FC Hardware
Description and Data Sheets
83C152 Hardware
Description and Data Sheets
UPI .. 452 CHMOS
. Programmable 110 Processor
MCS® .. 51 Development
Support Tools
RUPITM .. 44 Family
RUPITM Development
Support Tools
MCS® .. 80/85 Family
Table of Contents
Alphanumeric Index ...................................................... . xiv
MCS®-48 FAMILY
Chapter 1
MCS®-48 Single Component System ....................................... . 1-1
Chapter 2
. MCS®-48 Expanded System ............................................... . 2-1
Chapter 3
MCS®-48 Instruction Set .................................................. . 3-1
Chapter 4
MCS®-48 DATA SHEETS
8243 MCS-48 Input/Output Expander ....................................... . 4-1
P87 48H/P87 49H/8048AH/8035AHLl8049AH/8039AHLl8050AH/8040AH L
HMOS Single Component 8-Bit Microcontroller ............................ . 4-8
D8748H/D8749H HMOS-E Single-Component 8-Bit Microcomputer ............ . 4-21
P8049KB HMOS Single-Component 8-Bit Microcontroller ..................... . 4-33
MCS-48 Express .......................................................... . 4-45
MCS®-51 FAMILY
Chapter 5
MCS-51 Family of Microcontrollers Architectural Overview ..................... . 5-1
Chapter 6
MCS-51 Programmer's Guide and Instruction Set ............................. . 6-1
Chapter 7
8051, 8052 and 80C51 Hardware Description ................................ . 7-1'
8XC52/54/58 Hardware Description ........................................ . 7-38
DATA SHEETS
MCS-51 8-Bit Control-Oriented Microcomputers 8031/8051/8031 AH/8051 AHI
8032AH/8052AH/8751 H/8751 H-8 ....................................... . 7-48
8051 AHP MCS-51 Family 8-Bit Control-Oriented Microcontroller with Protected
ROM ................................................................. . 7-62
8031 AH/8051AH/8032AH/8052AH/8751 H/8751 H-8 Express ................. . 7-72
8751 BH Single-Chip 8-Bit Microcomputer with 4K Bytes of EPROM Program
Memory ............................................................... . 7-74
8751 BH Express ......................................................... . 7-86
8752BH Single-Chip 8-Bit Microcomputer with 8K Bytes of EPROM Program
Memory ............................................................... . 7-88
8752BH Express ......................................................... . 7-100
8051 KB/8052KB MCS-51 Family 8-Bit Microcontroller ........................ . 7-102
80C51 BH/80C31 BH CHMOS Single-Chip 8-Bit Microcomputer ................. . 7-114
80C31 BH/80C51 BH Express .............................................. . 7-130
80C51 BHP CHMOS Single-Chip 8-Bit Microcomputer with Protected ROM ...... . 7-132
87C51 187C51-1 187C51-2 CHMOS Single-Chip 8-Bit Microcontroller with 4K Bytes
of EPROM Program Memory ............................................. . 7-146
87C51 Express ................................................... , ...... . 7-160
80C52/80C32 CHMOS Single-Chip 8-Bit Microcomputer ...................... . 7-163
80C52/80C32 Express ................................................... . 7-176
87C54/80C54 CHMOS Single-Chip 8-Bit Microcontroller with 16 Kbytes User
Programmable EPROM ................................................. . 7-178
87C54/80C54 Express ................................................... . 7-193
87C58/80C58 CHMOS Single-Chip 8-Bit Microcontroller with 32 Kbytes User
Programmable EPROM .......................... ~ ...................... . 7-195
87C58/80C58 Express ................................................... . 7-212
xi
Table of Contents (Continued)
Chapter 8
8XC51 FX Hardware Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8XC51GB Hardware Description..... ......... ..................... ......... 8-44
DATA SHEETS
83C51 FAl80C51 FA CHMOS Single-Chip 8-Bit Microcontroller ...... ............ 8-104
83C51 FAl80C51 FA Express.. ...... ..................... .................. 8-118
87C51 FA CHMOS Single-Chip 8-Bit Microcontroller 8K Byte User Programmable
EPROM ................................................... '. . . . . . . . . . . .. 8-120
87C51FAExpress ......................................................... 8-136
83C51 FB CH MOS Single-Chip 8-Bit Microcontroller ........................... 8-139
87C51 FB CHMOS Single-Chip 8-Bit Microcontroller ......................... ;. 8-152
87C51FB Express ......................................................... 8-168
87C51 FC/83C51 FC CHMOS Single-Chip 8-Bit Microcontroller 32K Bytes User
Programmable EPROM......................................... .. ....... 8-171
87C51 FC/83C51FC Express ............................................... 8-186
87C51 GB/80C51 GB CHMOS Single-Chip 8-Bit Microcontroller ........ . . . . . . . .. 8-188
87C51 GB/80C51 GB CHMOS Single-Chip 8-Bit Microcontroller Express. . . . . . . . .. 8-209
UCS51 ASIC Family of Enhanced 8-Bit Microcontrollers with User-Selectable
Peripheral Set and ROM/RAM Configurations .............................. 8-210
EV80C51 FB Evaluation Board Fact Sheet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-217
EV80C51 FC Evaluation Board Fact Sheet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-219
Chapter 9
8XF51 FC Hardware Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
DATA SHEETS
88F51 FC CHMOS Single-Chip 8-Bit Microcontroller 32 Kbytes User Programmable
Flash Memory .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-54
88F51 FC CHMOS Single-Chip 8-Bit Microcontroller 32 Kbytes User Programmable
Flash Memory Express............. ............................. ......... 9-75
Chapter 10
83C152 Hardware Description ....... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
DATA SHEETS
8XC152JAI JB/ JC/ JD Universal Communication Controller 8-Bit Microcontroller .. 10-71
8XC152JAI JB/ JC/ JD Universal Communication Controller 8-Bit Microcomputer
Express. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-88
Chapter 11
UPI-452 CHMOS Programmable I/O Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
Chapter 12
MCS®-51 DEVELOPMENT SUPPORT TOOLS
. 8051 Software Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
AEDIT Source Code and Text Editor... ................... ....... ............ 12-4
ICE-51 fPC In-Circuit Emulator. . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . .. . . . . . 12-6
ICE-51 00/252 In-Circuit Emulator ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... 12-11
ICE-51 00/452 In-Circuit Emulator ........................................... 12-15
THE RUPITM FAMilY
Chapter 13
The RUPI-44 Family: Microcontroller with On-Chip Communication Controller . . . . . 13-1
8044 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9
The RUPI-44 Serial Interface Unit ........................................... 13-19
8044 Application Examples. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-57
8044 DATA SHEET
8044AH/8344AH/8744AH High Performance 8-Bit Microcontroller with On-Chip
Serial Communication Controller .......................................... 13-131
xii
Table of Contents (Continued) -
Chapter 14
RUPITM DEVELOPMENT SUPPORT TOOLS
ICE-51 001044 In-Circuit Emulator ........................................ :.. 14-1
MCS®·80/85 FAMILY
Chapter 15
80/85 DATA SHEETS
8080Al8080A-1/8080A-2 8-Bit N-Channel Microprocessor. . . . . . . . . . . . . . . . . . . . . 15-1
8085AH/8085AH-2/8085AH-1 8-Bit HMOS Microprocessors ......... ,......... 15-11
8155H/8156H/8155H-2/8156H-2 2048-Bit Static HMOS RAM with 1/0 Ports and
Timer ........ -..................... ................................ ..... 15-31
8185/8185-21024 x 8-Bit Static RAM for MCS-85 ............................ , 15-45
8224 Clock Generator and Driver for 8080A CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15-50
8228 System Controller and Bus Driver for 8080A CPU. . . . . . . . . . . . . . . . . . . . . . . .. 15-55
8755A 16,384-Bit EPROM with 1/0.......................................... 15-59
xiii
Alphanumeric Index
8031AH/8051AH/8032AH/8052AH/8751 H/8751 H-8 Express........................ 7-72
8044 Application Examples ....................................................... 13-57
8044 Architecture ....................................................... '.' . . . . . . . 13-9
8044AH/8344AH/8744AH High Performance 8-Bit Microcontroller with On-Chip Serial
Communication Controller ...................................................... 13-131
8051 Software Packages ......................................................... 12-1
8051,8052 and 80C51 Hardware Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
8051AHP MCS-51 Family 8-Bit Control-Oriented Microcontroller with Protected ROM..... 7-62
8051 KB/8052KB MCS-51 Family 8-Bit Microcontroller..................... ........... 7-102
8080Al8080A-1 18080A-2 8"Bit N-Channel Microprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
8085AH/8085AH-2/8085AH-1 8-Bit HMOS Microprocessors. . . . . . . . . . . . . . . . . . . . . . . . .. 15-11
80C31BH/80C51BH Express ...................................................... 7-130
80C51 BHP CHMOS Single-Chip 8-Bit Microcomputer with Protected ROM .............. 7-132
80C51 BH/80C31 BH CHMOS Single-Chip 8-Bit Microcomputer. . . . . . . . . . . . . . . . . . . . . . .. 7-114
80C52/80C32 CHMOS Single-Chip 8-Bit Microcomputer.............................. 7-163
80C52/80C32 Express........... .............................. .................. 7-176
8155H/8156H/8155H-2/8156H-2 2048-Bit Static HMOS RAM with I/O Ports and Timer .. 15-31
8185/8185-2 1024 x 8-Bit Static RAM for MCS-85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15-45
8224 Clock Generator and Driver for 8080A CPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15-50
8228 System Controller and Bus Driver for 8080A CPU ............................... . 15-55
8243 MCS-48 Input/Output Expander ................... . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
83C152 Hardware Description ....... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
83C51 FAl80C51 FA CHMOS Single-Chip 8-Bit Microcontroller....... .................. 8-104
83C51FAl80C51 FA Express ...................................................... 8-118
83C51 FB CH MOS Single-Chip 8-Bit Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-139
8751 BH Express. . . . . . .. . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 7-86
8751 BH Single-Chip 8-Bit Microcomputer with 4K Bytes of EPROM Program Memory. . . . . 7-74
8752BH Express ................................... ,. ............................. 7-100
8752BH Single-Chip 8-Bit Microcomputer with 8K Bytes of EPROM Program Memory. . . . . 7-88
8755A 16,384-Bit EPROM with I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15-59
87C51 Express .................................................................. 7-160
87C51 187C51-1 187C51-2 CHMOS Single-Chip 8-Bit Microcontroller with 4K Bytes of
EPROM Program Memory .... ~............................... .................. 7-146
87C51 FA CHMOS Single-Chip 8-Bit Microcontroller 8K Byte User Programmable EPROM. 8-120
87C51FA Express ............................................................... 8-136
87C51 FB CHMOS Single-Chip 8-Bit Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-152
87C51FB Express ............................................................... 8-168
87C51FC/83C51 FC CHMOS Single-Chip 8-Bit Microcontroller 32K Bytes User
Programmable EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-171
87C51 FC/83C51 FC Express. . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-186
87C51 GB/80C51 GB CHMOS Single-Chip 8-Bit Microcontroller Express ................ 8-209
87C51GB/80C51GB CHMOSSingle-Chip 8-Bit Microcontroller ........................ 8-188
87C54/80C54 CHMOS Single-Chip 8-Bit Microcontroller with 16 Kbytes User
Programmable EPROM....................................... .................. 7-178
87C54/80C54 Express......................................... .................. 7-193
87C58/80C58 CHMOS Single-Chip 8-Bit Microcontro/ler with 32 Kbytes User
Programmable EPROM ......................................................... 7-195
87C58/80C58 Express........................................................... 7-212
88F51 FC CHMOS Single-Chip 8-Bit Microcontroller 32 Kbytes User Programmable Flash
Memory Express. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-75
88F51 FC CHMOS Single-Chip 8-Bit Microcontroller 32 Kbytes User Programmable Flash
Memory ...................................................................... 9-54
8XC152JAlJB/JC/JD Universal Communication Controller 8-Bit Microcontroller ......... 10-71
8XC152JAlJB/JC/JD Universal Communication Controller 8-Bit Microcomputer Express. 10-88
xiv
Alphanumeric Index (Continued)
8XC51 FX Hardware Description .................................................. . 8-1
8XC51 GB Hardware Description .................................................. . 8-44
8XC52/54/58 Hardware Description .............................................. . 7-38
8XF51 FC Hardware Description .................................................. . 9-1
AEDIT Source Code and Text Editor ............................................... . 12-4
D8748H/D8749H HMOS-E Single-Component 8-Bit Microcomputer ................... . 4-21
EV80C51 FB Evaluation Board Fact Sheet .......................................... . 8-217
EV80C51 FC Evaluation Board Fact Sheet .......................................... . 8-219
ICE-51 001044 In-Circuit Emulator ................................................. . 14-1
ICE-5100/252 In-Circuit Emulator ................................................. . 12-11
ICE-51 00/452 In-Circuit Emulator ................................................. . 12-15
ICE-51 IPC In-Circuit Emulator .................................................... . 12-6
MCS-48 Express ................................................................ . 4-45
MCS-51 8-Bit Control-Oriented Microcomputers 8031/8051/8031 AH/8051 AH/8032AHI
8052AH/8751 H/8751 H-8 ...................................................... . 7-48
MCS-51 Family of Microcontrollers Architectural Overview ........................... . 5-1
MCS-51 Programmer's Guide and Instruction Set ................................... . 6-1
MCS®-48 Expanded System ..................................................... . 2-1
MCS®-48 Instruction Set ......................................................... . 3-1
MCS®-48 Single Component System .............................................. . 1-1
P8049KB HMOS Single-Component 8-Bit Microcontroller ............................ . 4-33
P8748H/P8749H/8048AH/8035AHLl8049AH/8039AHL/8050AH/8040AHL HMOS
Single Component 8-Bit Microcontroller .......................................... . 4-8
The RUPI-44 Family: Microcontroller with On-Chip Communication Controller ........... . 13-1
The RUPI-44 Serial Interface Unit ................................................. . 13-19
UCS51 ASIC Family of Enhanced 8-Bit Microcontrollers with User-Selectable Peripheral
Set and ROM/RAM Configurations .............................................. . 8-210
UPI-452 CHMOS Programmable 1/0 Processor ..................................... . 11-1
xv
MCS® . .48 Single Component 1
System
THE SINGLE COMPONENT MCS®-48 SYSTEM
1.0 INTRODUCTION • Add With or Without Carry
• AND, OR, Exclusive OR
Sections 2 through 5 describe in detail the func- • IncremenUDecrement
tional characteristics of the S74SH and S749H EPROM, • Bit Complement
S04SAH/S049AH/SOSOAH ROM, and S03SAHLI • Rotate Left, Right
S039AHLlS040-AHL CPU only single component micro- • Swap Nibbles
computers. Unless otherwise noted, details within these • BCD Decimal Adjust
sections apply to all versions. This chapter is limited to
If the operation performed by the ALU results in a value
those functions useful in single-chip implementations of
represented by more than S bits (overflow of most sig-
the MCS®-4S. The Chapter on the Expanded MCS®-48
nificant bit), a Carry Flag is set in the Program Status
System discusses functions which allow expansion of
Word.
program memory, data memory, and input output capa-
bility.
ACCUMULATOR
2.0 ARCHITECTURE
The accumulator is the single most important data register
The following sections break the MCS-4S Family into in the processor, being one of the sources of input to the
functional blocks and describe each in detail. The follow- ALU and often the destination of the result of operations
ing description will use the S04SAH as the representative performed in the ALU. Data to and from 110 ports and
product for the family. See Figure 1. memory also normally passes through the accumulator.
2.1 Arithmetic Section 2.2 Program Memory
The arithmetic section of the processor contains the basic Resident program memory consists of 1024, 2048, or 4096
data manipulation functions of the S04SAH and can be words eight bits wide which are addressed by the program
divided into the following blocks: counter. In the S74SH and the S749H this memory is user
programmable and erasable EPROM; in the S04SAHI
• Arithmetic Logic Unit (ALU) S049AH/SOSOAH the memory is ROM which is mask
programmable at the factory. The S03SAHLlS039AHLI
• Accumulator 8040AHL has no internal program memory and is used
with external memory devices. Program code is com-
• Carry Flag pletely interchangeable among the various versions. To
access the upper 2K of program memory in the SOSOAH,
• Instruction Decoder and other MCS-4S devices, a select memory bank and a
JUMP or CALL instruction must be executed to cross the
In a typical operation data stored in the accumulator is 2K boundary.
combined in the ALU with data from another source on
the internal bus (such as a register or 110 port) and the There are three locations in Program Memory of special
result is stored in the accumulator or another register. importance as shown in Figure 2.
The following is more detailed description of the function LOCATION 0
of each block. Activating the Reset line of the processor causes the first
instruction to be fetched from 10cationO.
INSTRUCTION DECODER
LOCATION 3
The operation code (op code) portion of each program Activating the Interrupt input line of the processor (if
instruction is stored in the Instruction Decoder and con- interrupt is enabled) causes a jump to subroutine at lo-
verted to outputs which control the function of each of cation 3.
the blocks of the Arithmetic Section. These lines control
the source of data and the destination register as well as LOCATION 7
the function performed in the ALU. A timer/counter interrupt resulting from timer counter
overflow (if enabled) causes a jump to subroutine at loca-
ARITHMETIC LOGIC UNIT tion 7.
The ALU accepts S-bit data words from one or two sources Therefore, the first instruction to be executed after ini-
and generates an S-bit result under control of the Instruc- tialization is stored in location 0, the first word of an
tion Decoder. The ALU can perform the following external interrupt service subroutine is stored in location
functions: 3. and the first word of a timer/counter service routines
1-1
EXPANSION TO
MORE ItO AND
MEMORY
RESIDENT
EPROM ROM
."
ce'
e
ia en
~ Z
(XI C>
~ r-
(XI m
::r o
CO PORT 1
o
....CI
(XI
BUS
BUFFER 3:
o"
AND
::r LATCH
CO Z
..... ~ m
ro ~ Z
::r -i
CO REGISTER 3:
CI
U1 o
REGISTER en
~ TESTa @
::r REGISTER
....
I
TEST 1 REGISTER
III co
o INT
REGISTER en
~ -<
w
c REGISTER
FLAG 0 c en
c Vee .. PROGRAM SUPPLY CONDITIONAL ~ ~ REGISTER -i
iir POWER V BRANCH FLAG 1 c
8 LEVEL STACK
m
CQ SUPPLY { ...EB... +5V (LOW POWER STANDBY) , LOGIC TIMER (VARIABLE LENGTH) 3:
iii
~GND
FLAG
3 CARRY
OPTIONAL SECOND
REGISTER BANK
ACC
DATA STORE
ACCBIT
TEST
RESIDENT
RAM ARRAY
INTERRUPT PROM{ CPU! OSCILLATOR ADDRESS PROGRAM SINGLE READ
EXPANDER MEMORY XTAl LATCH MEMORY STEP WRITE
STROBE SEPARATE STROBE ENABLE STROBES
INITIALIZE CYCLE
CLOCK
SINGLE COMPONENT MCS®-48 SYSTEM
is stored in location 7. Program memory can be used to registers in place of locations 0-7 and arc then directly
store constants as well as program instructions. Instruc- addressable. Th,is second bank of working registers may
tions such as MOVP and MOVP3 allow easy access to be used as an extension of the first bank or reserved for
data' 'lookup" tables. use during interrupt service subroutines allowing the reg-
isters of Bank 0 used in the main program to be instantly
"saved" by a Bank Switch. Note that if this second bank
is not used, locations 24-31 are still addressable as general
purpose RAM. Since the two RAM pointer Registers RO
'"T=J
'204B~~SELMB1
and R I are a part of the working register array, bank
switching effectively creates two more pointer registers
(ROland RII) which can be used with RO and Rl to easily
access up to four separate working areas in RAM at one
time. RAM locations (8-23) also serve a dual role in that
they contain the program counter stack as explained in
2047~ j SELMBO Section 2.6. These locations are addressed by the Stack
Pointer during subroutine calls as well as by RAM Pointer
J:
< Registers RO and R I. If the level of subroutine nesting is
0
.,"'
0
1024
10231"'
r-~::::=-':::::::::::=I less than 8, all stack registers are not required and can be
0.. used as general purpose RAM locations. Each level of
i() subroutine nesting not used provides the user with two
additional RAM locations.
Z
0
. .,..
J:
<
m
0
00
J:
<
0
0.. 00
LOCATION 7 -
i 0..
U i B~____________~- ~~~~~~;ERRUPT 63
z u (127)
0 z 6 PROGRAM HERE
0 5 «255))
4 ~~~::~~~ 3 - USER RAM
32" B
3 t--------------i
-f--INTERRUPT
(96" B)
2 VECTORS
«224" B))
PROGRAM HERE
1~~~~~-r~~ 32
o7 1 6 1 5 1 4 1 31 2 11 1 0 -RESET VECTORS 31 BANK 1 I
ADDRESS PROGRAM HERE WORKING DIRECTLY
REGISTERS ADDRESSABLE
B"B WHEN BANK 1
-----Rl'- - - - IS SELECTED
Figure 2. Program Memory Map 24
23
-- --AO' - - - -
. I
2.3 Data Memory 8 LEVEL STACK
OR
ADDRESSED
INDIRECTLY
USER RAM THROUGH
Resident data memory is organized as 64, 128, or 256 by 16" B R1 OR RO
8-bits wide in the 8048AH, 8049AH and 8050AH. All (RO' OR R1')
locations are indirectly addressable through either of two B
RAM Pointer Registers which reside at address 0 and I 7 BANKO I
of the register array. In addition, as shown in Figure 3, WORKING DIRECTLY
REGISTERS ADDRESSABLE
the first 8 locations (0-7) of the array are designated as
8"B WHEN BANK 0
working registers and are directly addressable by several ------R1- - - -
IS SELECTE1D
instructions. Since these registers are more easily ad- ----------
RO
0
dressed, they are usually used to store frequently accessed
intermediate results. The DJNZ instruction makes very
efficient use of the working registers as program loop IN ADDITION RO OR R1 (RO' OR R1')
MAY BE USED TO ADDRESS 256 ( ) B049AH, B749H,
counters by allowing the programmer to decrement and WORDS OF EXTERNAL RAM, « )) B050AH
test the register in a single instruction.
By executing a Register Bank Switch instruction (SEL
RB) RAM locations 24-31 are designated as the working Figure 3. Data Memory Map
1-3
SINGLE COMPONENT MCS®-48 SYSTEM
VCC
VCC
Q
INTERNAL
BUS D
D 1/0
FLIP PIN
FLOP PORTl
LOW AND2
IMPEDANCE
PULLDOWN
CLK Q
WRITE
PULSE
-=-
IN
MAX
-500
-400
10H -300 _ _ __
(MAl -200
4V OV 2V 4V
VOL
LOW IMPEDANCE PULLUP HIGH IMPEDANCE PULLUP LOW IMPEDANCE PULLDOWN
These graphs are for informational purposes only and are not guaranteed minimums or maximums.
Figure 4. "Quasi-bidirectional" Port Structure
1-4
SINGLE COMPONENT MCS®-48 SYSTEM
2.4 Input/Output statically latched output port or non-latching input port.
Input and output lines on this port cannot be mixed
The 8048AH has 27 lines which can be used for input or however.
output functions. These lines are grouped as 3 ports of 8
lines each which serve as either inputs, outputs or bidi- As a static port, data is written and latched using the OUTL
rectional ports and 3 "test" inputs which can alter pro- instruction and inputted using the INS instruction. The
gram sequences when tested by conditional jump INS and OUTL instructions generate pulses on the cor-
instructions. responding RD and WR output strobe lines; however, in
the static port mode they are generally not used. As a
PORTS 1 AND 2 bidirectional port the MOVX instructions are used to read
and write the port. A write to the port generates a pulse
Ports I and 2 are each 8 bits wide and have identical on the WR out~ line and output data is valid at the
characteristics. Data written to these ports is statically trailing edge of WR. A read of the port generates a pulse
latched and remains unchanged until'rewritten. As input on the RD output line and input data must be valid at the
ports these lines are non-latching, i.e., inputs must be trailing edge of RD. When not being written or read, the
present until read by an input instruction. Inputs are fully BUS lines are in a high impedance state. See also sections
TTL compatible and outputs will drive one standard TTL 7 and 8 in the Expanded MCS-48 System chapter.
load.
2.5 Test and INT Inputs
The lines of ports I and 2 are called quasi-bidirectional Three pins serve as inputs and are testable with the con-
because of a special output circuit structure which allows ditional jump instruction. These are TO, TI, and INT.
each line to serve as an input, and output, or both even These pins allow inputs to cause program branches without
though outputs are statically latched. Figure 4 shows the necessity to load an input port into the accumulator,
the circuit configuration in detail. Each line is continu- The TO, TI, and INT pins have other possible functions
ously pulled up to VCC through a resistive device of as well. See the pin description in Section 3.
relatively high impedance.
2.6 Program Counter and Stack
This pullup is sufficient to provide the source current for
a TTL high level yet can be pulled low by a standard TTL The Program Counter is an independent counter while the
gate thus allowing the same pin to be used for both input Program Counter Stack is implemented suing pairs of reg-
and output. To provide fast switching times in a "0" to isters in the Data Memory Array. Only 10, II, or 12 bits
"I" transition a relatively low impedance device is of the Program Counter are used to address the 1024,
switched in momentarily (= 115 of a machine cycle) when- 2048, or 4096 words of on-board program memory of the
ever a "I" is written to the line. When a "0" is written 8048AH, 8049AH, or 80S0AH, while the most significant
to the line a low impedance device overcomes the light bits can be used for external Program Memory fetches.
pullup and provides TTL current sinking capability. Since See Figure 5. The Program Counter is initialized to
the pulldown transistor is a low impedance device a " I " zero by activating the Reset line.
must first be written to any line which is to be used as an
input. Reset initializes all lines to the high impedance' 'I "
state.
It is important to note that the ORL and the ANL are read! 1~IAWI~I~I~I~I~I~I~I~I~I~1
write operations. When executed, the f,LC "reads" the I
I
I
port, modifies the data according to the instruction, then Conventional Program Counter
"writes" the data back to the port. The "writing" (es- • Counts OOOH to 7FFH
• Overflows 7FFH to OOOH
sentially an OUTL instruction) enables the low impedance
pull-up momentarily again even if the data was unchanged
from a "I." This specifically applies to configurations
that have inputs and outputs mixed together on the same Figure 5. Program Counter
port. See also section 8 in the Expanded MCS-48 System
chapter.
An interrupt or CALL to a subroutine causes the contents
BUS
of the program counter to be stored in one of the 8 register
Bus is also an 8-bit port which is a true bidirectional port pairs of the Program Counter Stack as shown in Figure
with associated input and output strobes. If the bidirec- 6. The pair to be used is determined by a 3-bit Stack
tional feature is not needed, Bus can serve as either a Pointer which is part of the Program Status Word (PSW).
1-5
SINGLE COMPONENT MCS®-48 SYSTEM
the word. The Program Status Word is actiIally a collection
of flip-flops throughout the machine which can be read or
POIN TER written as a whole. The ability to write to PSW allows
R23
111 for easy restoration of machine stalUs after a power down
22 sequence.
21
110 --"-
20 SAVED IN STACK
,
STACK POINTER
101
· 19
I
18 So
.17 MSB LSB
100
·
--"-
16 CY
AC
CARRY
AUXILIARY CARRY
: 15 FO FLAG 0
011
· 14
BS REGISTER BANK SELECT
-; 13
Figure 7. Program Status Word (PSW)
010
· 12
001
·• 11
10
The upper four bits of PSW are stored in the Program
Counter Stack with every call to subroutine or interrupt
vector and .are optionally restored upon return with the
psw PCS-ll 9
000 RETR instruction. The RET return instruction does not
PC4-7 PCO-3 RS update PSW.
MSB LSB
The PSW bit definitions are as follows:
Bits 0:-2: Stack Pointer bits (So' SI, S2)
Figure 6. Program Counter Stack
Bit 3: Not used (" 1" level when read)
Data RAM locations 8-23 are available as stack registers
and are used to store the Program. Counter and 4 bits of Bit 4: Working Register Bank Switch Bit (BS)
PSW as shown in Figure 6. The Stack Pointer .when a Bank a
initialized to 000 points to RAM locations 8 and 9. The 1 = Bank 1
first subroutine jump or interrupt results in the program
counter contents being transferred to locations 8 and 9 of Bit 5: Flag a bit .(Fa) user controlled flag which can
the RAM array. The stack pointer is then incremented by be complemented or cleared, and tested with
one to point to locations 10 and 11 in anticipation of the conditional jump instruction JFO.
another CALL. Nesting of subroutines wihtin subroutines
can continue up to 8 times without overflowing the stack. Bit 6: Auxiliary Carry (AC) carry bit generated by
If overflow does occur the deepest address stored (loca- an ADD instruction and used by the decimal
tions 8 and 9) will be overwritten and lost since the stack adjust instruction DAA .
. pointer overflows from III to 000. It also underflows from
000 to 111. Bit 7: Carry (CY) carry flag which indicates that the
previous operation has resulted in overflow of
The end of a subroutine, which is signalled by a return the accumulator.
instruction (RET or RETR), causes the Stack Pointer to
be decremented and the contents of the reSUlting r~gister 2.8 Conditional Branch Logic
pair to be transferred to the Program Counter.
The conditional branch logic within the processsor enables
2.7 Program Status Word several conditions internal and external to the processor
to be tested by the users program. By using the conditional
An 8-bit status word which can be loaded to and from the jump instruction the conditions that are listed in Table
accumulator exists called the Program Status Word I can effect a change in the sequence of the program
(PSW). Figure 7 shows the information available in execution.
1-6
SINGLE COMPONENT MCS®-48 SYSTEM
Table 1
abled by the users program. An interrupt request must be
Jump Conditions removed before the RETR instruction is executed upon
Device Testable (Jum On) return from the service routine otherwise the processor
will re-enter the service routine immediately. Many pe-
not all ripheral devices prevent this situation by resetting their
Accumulator All zeros zeros interrupt request line whenever the processor accesses
Accumulator Bit - I (Reads or Writes) the peripherals data buffer register. If
Carry Flag 0 I the interrupting device does not require access by the
User Flags (FO. FI) - I processor. 'one output line of the 8048AH may be des-
Timer Overflow Flag - I ignated as an "interrupt acknowledge" which is activated
Test Inputs (TO •...!.!) 0 I by the service subroutine to reset the interrupt request.
Interrupt Input (lNT) 0 - The INT pin may also be tested using the conditional jump
instruction IN!. This instruction may be used to detect the'
2.9 Interrupt presence of a pending interrupt before interrupts are en-
abled. If interrupt is left disabled. INT may be used as
An interrupt sequenc~ is initiated by applying a low "0" another test input like TO and T! .
level input to the INT pin. Interrupt is level triggered and
active low to allow "WIRE ORing" of several interrupt 2.10 Timer/Counter
sources at the input pin. Figure 8 shows the interrupt
logic of the 8048AH. The Interrupt line is sampled every The 8048AH contains a counter to aid the user in counting
instruction cycle and when detected causes a "call to external events and generating accurate time delays with-
subroutine" at location 3 in program memory as soon as out placing a burden on the processor for these functions.
all cycles of the current instruction are complete. On 2- In both modes the counter operation is the same. the only
cycle instructions the interrupt line is sampled on the 2nd difference being the source of the input to the counter.
cycle only. INT must be held low for at least 3 machine The timer/event counter is shown in Figure 9.
cycles to ensure proper interrupt operations. As in any
CALL to subroutine. the Program Counter and Program COUNTER
Status word are saved in the stack. For a description of
this operation see the previous section. Program Counter The 8-bit binary counter is presettable and readable with
and Stack. Program Memory location 3 usually contains two MOY instructions which transfer the contents of the
an unconditional jump to an interrupt service subroutine accumulator to the counter and vice versa. The counter
elsewhere in program memory. The end of an interrupt content may be affected by Reset and should be initialized
service subroutine is signalled by the execution of a Return by software. The counter is stopped by a Reset or STOP
and Restore Status instruction RETR. The interrupt system TCNT instruction and remains stopped until started as a
is single level in that once an interrupt is detected all timer by a START T instruction or as an event counter
further interrupt requests are ignored until execution of an by a START CNT instruction. Once started the counter
RETR reenables the interrupt input logic. This occurs at will increment to this maximum count (FF) and overflow
the beginning of the second cycle ofthe RETR instruction. to zero continuing its count until stopped by a STOP TCNT
This sequence holds true also for an internal interrupt instruction or Reset.
generated by timer overflow. If an internal timer/counter
generated interrupt and an external interrupt are detected . The increment from maximum count to zero (overflow)
at the same time. the external source will be recognized. results in the setting of an overflow flag flip-flop and in
See the following Timer/Counter section for a ·descriptkm tite generation of an interrupt request. The state of the
of timer interrupt. If needed. a second external interrupt overflow flag is testable with the conditional jump instruc-
can be created by enabling the timer/counter interrupt. tion JTF. The flag is reset by executing a JTF or by Reset.
loading FFH in the Counter (ones less than terminal The interrupt request is stored in a latch and then ORed
count). and enabling the event counter mode. A "I" to with the external interrupt input INT. The timer interrupt
"0" transition on the T! input will then cause an interrupt may be enabled or disabled independently of external in-
vector to location 7. terrupt by the EN TCNT! and DIS TCNT! instructions.
If enabled. the counter overflow will cause a subroutine
INTERRUPT TIMING call to location 7 where the timer or counter service routine
may be stored.
The interrupt input may be enabled or disabled under
Program Control using the EN I and DIS I instructions. If timer and external interrupts occur simultaneously. the
Interrupts are disabled by Reset and remain so until en- external source will be recognized and the Call will be to
1-7
SINGLE COMPONENT MCS®-48 SYSTEM
S CONDITIONAL
JUMP LOGIC
TIMER
FLAG INTERRUPT
JTF CALL
EXECUTED----~~~_+--~ EXECUTED
RESET R
CLR EXTERNAL
0 Q INTERRUPT
RECOGNIZED
~I:E~RFLOW ----------<~-l S Q
TIMER
OVERFLOW TIMER
FF Q INTERRUPT
TIMER INT
CLK RECOGNIZED
RECOGNIZED ~----~R
EXECUTED
RESET
S Q
INTERRUPT
IN
PROGRESS
S Q FF
TIMER R
INT
ENABLE
DIS TCNTI ___~~
EXECUTED ~----~ R Q
RESET
INT~ ____________ ~
0
PIN
INT RESET
FF
RETR
EXECUTED
Q
CLK
ALE----...
LAST CYCLE 1----------'
OFINST.
ENI S Q
EXECUTED.
1. WHEN INTERRUPT IN PROGRESS FLIp· FLOP IS SET
INT . ALL FURTHER INTERRUPTS ARE LOCKED OUT
ENABLE INDEPENDENT OF STATE OF EITHER INTERRUPT
DISI
EXECUTED ENABLE FLIP·Fl.OP.
R
RESET -----L-.J' 2. WHILE TIMER INTERRUPTS ARE DISABLED TIMER
OVERFLOW fli WILL NOT STORE ANY OVERFLOW
THAT OCCURS. TIMER FLAG WILL BE SET, HOWEVER.
Figure 8. Interrupt logic
1·8
SINGLE COMPONENT MCS®-48 SYSTEM
PRESCALER
XTAL 715
LOAD OR READ
CLEARED ON START TIMER
JUMPON
START
TIMER FLAG
TIMER
START
COUNTER
EDGE 8 BIT TIMER/
DETECTOR EVENT COUNTER
o
STOPT
INT
ENABLE--------~L___~
Figure 9. Timer/Event Counter
location 3. Since the timer interrupt is latched it will re- olution less than I count an external clock can be applied
main pending until the external device is serviced and to the Tl input and the counter operated in the event
immediately be recognized upon return from the service counter mode. ALE divided by 3 or more can serve as
routine. The pending timer interrupt is reset by the Call this external clock. Very small delays or "fine tuning"
to location 7 or may be removed by executing a DIS of larger delays can be easily accomplished by software
TCNTl instruction. delay loops.
AS AN EVENT COUNTER Often a serial link is desirable in an MCS-48 family mem-
ber. Table 2 lists the timer counts and cycles needed
Execution of a START CNT instruction connects the Tl for a specific baud rate given a crystal frequency.
input pin to the counter input and enables the counter.
The Tl input is sampled at the beginning of state 3 or in 2.11 Clock and Timing Circuits
later MCS-48 devices in state time 4. Subsequent high to
low transitions on Tl will cause the counter to increment. Timing generation for the 8048AH is completely selfcon-
Tl must be held low for at least I machine cycle to insure tained with the exeception of a frequency reference which
it won't be missed. The maximum rate at which the can be XT AL, ceramic resonator, or external clock source.
counter may be incremented is once per three instruction The Clock and Timing circuitry can be divided into the
cycles (every 5.7 J-Lsec when using an 8 MHz crystal) -- following functional blocks.
there is no minimum frequency. TI input must remain
high for at least \15 machine cycle after each transition. OSCILLATOR
The on-board oscillator is a high gain parallel resonant
AS A TIMER circuit with a frequency range of 1 to II MHz. The XI
external pin is the input to the amplifier stage while X2
Eexcution of a START T instruction connects an internal is the output. A crystal or ceramic resonator connected
clock to the counter input and enables the counter. The . between X I and X2 provides the feedback and phase shift
internal clock is derived bypassing the basic machine cycle required for oscillation. If an accurate frequency reference
clock through a -;- 32 prescaler. The prescaler is reset is not required, ceramic resonator may be used in place
during the START T instruction. The resulting clock in- of the crystal.
crements the counter every 32 machine cycles. Various
delays from 1 to 256 counts can be obtained by presetting For accurate clocking, a crystal should be used. An ex-
the counter and detecting overflow. Times longer than 256 ternally generated clock may also be applied to XI-X2
counts may be achieved by accumulating multiple over- as the frequency source. See the data sheet for more
flows in a register under software control. For time res- information.
1-9
SINGLE COMPONENT MCS®-48 SYSTEM
Table 2. Baud Rate Generation
Frequency Tcy TO Prr(1/5 Tcy) Timer Prescaler
(MHz) (32 Tcy)
4 3.75f-Ls 750ns 120f-LS
6 2.50f-Ls 500ns 80f-LS
8 1.88f-Ls 375ns 60.2f-Ls
11 1.36f-Ls 275ns 43.5f-LS
Baud 4 MHz 6 MHz 8 MHz 11 MHz
Rate Timer Counts + Timer Counts + Timer Counts + Timer Counts +
Instr. Cycles Instr. Cycles Instr. Cycles Instr. Cycles
110 75 + 24 Cycles 113 + 20 Cycles 151 + 3 Cycles 208 + 28 Cycles
.01% Error .01 % Error .01% Error .01% Error
300 27 + 24 Cycles 41 + 21 Cycles 55 + 13 Cycles 76 + 18 Cycles
.1% Error .03% Error .01% Error .04% Error
1200 6 + 30 Cycles 10 + 13 Cycles 12 + 27 Cycles 19 + 4 Cycles
.1% Error .1 % Error .06% Error .12% Error
1800 4 + 20 Cycles 6 + 30 Cycles 9 + 7 Cycles 12 + 24 Cycles
.1% Error .1 % Error .17% Error .12% Error
2400 3 + 15 Cycles 5 + 6 Cycles 6 + 24 Cycles 9 + 18 Cycles
.1% Error .4% Error .29% Error .12% Error
4800 1 + 23 Cycles 2 + 19 Cycles 3 + 14 Cycles 4 + 25 Cycles
1.0% Error .4% Error .74% Error .12% Error
STATE COUNTER power supply is within tolerance. Only 5 machine cycles
(6.8 f-LS @ II MHz) are required if power is already on
The output of the oscillator is divided by 3 in the State and the oscillator has stabilized. ALE and PSEN (if EA
Counter to create a clock which defines the state times of = 1) are active while in Reset.
the machine (CLK). CLK can be made available on the
external pin TO by executing an ENTO CLK instruction. Reset performs the following functions:
The output of CLK on TO is disabled by Reset of the
processor. I) Sets program counter to zero.
CYCLE COUNTER 2) Sets stack pointer to zero.
CLK is then divided by 5 in the Cycle Counter to pro- 3) Selects register bank O.
vide a clock which defines a machine cycle consisting
of 5 machine states as shown in Figure 10. Figure 11 4) Selects memory bank O.
shows the different internal operations as divided into
the machine states. This clock is called Address Latch 5) Sets BUS to high impedance state (except when
Enable (ALE) because of its function in MCS-48 sys- EA = 5V).
terns with external memory. It is provided continuous-
lyon the ALE output pin. 6) Sets Ports 1 and 2 to input mode.
2.12 Reset 7) Disables interrupts (timer and external).
The reset input provides a means for initialization for the 8) Stops timer.
processor. This Schmitt-trigger input has an internal pull-
up device which in combination with an external I J.L fd 9) Clears timer flag.
capacitor provides an internal reset pulse of sufficient
length to guarantee all circuitry is reset, as shown in Figure 10) Clears FO and F I.
12. If the reset pulse is generated externally the RESET
pin must be held low for at least 10 milliseconds after the II) Disables clock output from TO.
1-10
SINGLE COMPONENT MCS®-48 SYSTEM
JUMP ON
TEST = lOR 0
.273 psec (3.67 MHz)
DIAGRAM OF 8048AH CLOCK UTILITIES
. 1.36 psec CYCLE .
I S5 Sl
INPUT
S2 S3
1 S4
1 S5 Sl
I INST.
DECODE
OUTPUT
EXECUTION INPUT
INC. PC
ADDRESS J
I ~ I I I I
INSTRUCTION CYCLE
(1 BYTE, 2 CYCLE INSTRUCTION ONLY)
PREVIOUS CYCLE-... _Ir-.. . . . . - - - 1 S T CYCLE----cl... -tI-.. _ - - - 2 N D CYCLE---"'~I
STATE TIME:
S2 I S3 I S4 I S5 1 Sl 1 S2 1 S3"1 S4 S5 1 Sl S5 1 Sl 1 S2
(02)**TO
ALE ~~--------~~~---------~~-------
PSEN' - - - - - - - - - ,
RD,WR ________________________________________
'EXTERNAL MODE
"IF ENABLED
8048AH/8049AH TIMING
Figure 10. MCS"'-48 Timing Generation and Cycle Timing
2.13 Single-Step half of Port 2. The user can therefore follow the program
through each of the instruction steps. A timing diagram,
This feature, as pictured in Figure 13, provides the showing the interaction between output ALE and input
user with a debug" capability in that the processor can be SS, is shown. The BUS buffer contents are lost during
stepped through the program one instruction at a time. single step; however, a latch may be added to reestablish
While stopped, the address of the next instruction to be the lost I/O capability if needed. Data is valid at the leading
fetched is available concurrently on BUS and the lower edge of ALE.
1-11
CYCLE 1 CYCLE 2
INSTRUCTION 51 52 53 54 55 51 52 53 54 55
INA,P
FETCH INCREMENT
INSTRUCTION PROGRAM COUNTER - 'INCREMENT
TIMER - - READ
PORT
- . - -
oun P,A FETCH INCREMENT
INSTRUCTION PROGRAM COUNTER
- 'INCREMENT
TIMER
OUTPUT
TO PORT
- - - - -
ANL P, =DATA FETCH INCREMENT
INSTRUCTION PROGRAM COUNTER - 'INCREMENT
TIMER
READ PORT
FETCH
IMMEDIATE DATA
- INCREMENT
PROGRAM COUNTER
'OUTPUT
TO PORT
-
ORL P, =DATA FETCH INCREMENT
INSTRUCTION PROGRAM COUNTER - 'INCREMENT
TIMER
READ PORT' FETCH
IMMEDIATE DATA - INCREMENT
PROGRAM COUNTER
'OUTPUT
TO PORT
-
'"11
cD' FETCH INCREMENT INCREMENT READ
~
c: INSA,BUS
INSTRUCTION PROGRAM COUNTER
- TIMER
- - PORT
- - - Z
C)
iii r-
........ OUTL BUS, A
FETCH INCREMENT
INSTRUCTION PROGRAM COUNTER
- INCREMENT
TIMER
OUTPUT
TO PORT
- - - - - m
CD FETCH INCREMENT 'INCREMENT FETCH INCREMENT 'OUTPUT o
0 ANL BUS, =DATA INSTRUCTION PROGRAM COUNTER
- TIMER
READ PORT
IMMEDIATE DATA
- PROGRAM COUNTER TO PORT
- , o
~
s::
~
:J:
ORL BUS, =DATA FETCH INCREMENT
INSTRUCTION PROGRAM COUNTER
- 'INCREMENT
TIMER
READ PORT
FETCH
IMMEDIATE DATA
- INCREMENT
PROGRAM COUNTER
'OUTPUT
TO PORT -I o"
iii FETCH INCREMENT OUTPUT RAM INCREMENT OUTPUT
- - - - Z
.... 0
~
MOVX@R,A
INSTRUCTION PROGRAM COUNTER ADDRESS TIMER DATA TO RAM
-
m
~ ~ MOVXA,@R
FETCH INCREMENT OUTPUT RAM INCREMENT
- - READ
- - -
Z
-I
:J: INSTRUCTION PROGRAM COUNTER ADDRESS TIMER DATA
s::
5"
!!l.
MOVDA,PI
FETCH INCREMENT
INSTRUCTION PROGRAM COUNTER
OUTPUT
OPCODE/ADDRESS
INCREMENT
TIMER
- - READ P2
LOWER
- - - oVJ
... ®
c:
2- MOVD Pi,A
FETCH INCREMENT
INSTRUCTION PROGRAM COUNTER
OUTPUT
OPCODE/ADDRESS
INCREMENT
TIMER
OUTPUT DATA
TO P2 LOWER
- - - - - ~
I
0' CO
:::I ANLD P,A
FETCH INCREMENT
INSTRUCTION PROGRAM COUNTER
OUTPUT
OPCODE/ADDRESS
INCREMENT
TIMER
OUTPUT
DATA
- - - - - VJ
-I -<
VJ
,
3' ORLD P,A FETCH INCREMENT
INSTRUCTION PROGRAM COUNTER
OUTPUT
OPCODE/ADDRESS
INCREMENT
TIMER
OUTPUT
DATA
- - - - - -I
5' m
ea J(CONDITIONAL)
FETCH INCREMENT
INSTRUCTION PROGRAM COUNTER
SAMPLE
CONDITION
'INCREMENT
SAMPLE - FETCH
IMMEDIATE DATA - UPDATE
PROGRAM COUNTER
,
- - s::
C
iii' STRTT FETCH INCREMENT START
ea STRT CNT INSTRUCTION PROGRAM COUNTER
- - COUNTER
Dl
3 FETCH INCREMENT , STOP
STOP TCNT
INSTRUCTION PROGRAM COUNTER
- - COUNTER
FETCH INCREMENT ' ENABLE
ENI
INSTRUCTION PROGRAM COUNTER
- INTERRUPT
- 'VALID INSTRUCTION ADDRESSES ARE OUTPUT
AT THIS TIME IF EXTERNAL PROGRAM MEMORY IS
DISI
FETCH INCREMENT
INSTRUCTION PROGRAM COUNTER
- ' DISABLE
INTERRUPT - BEING ACCESSED,
(1) IN LATER MCS·48 DEVICES 11 IS SAMPLED IN S4.
FETCH INCREMENT • ENABLE
ENTO CLK
INSTRUCTION PROGRAM COUNTER CLOCK
-
SINGLE COMPONENT MCS®-4S SYSTEM
clear input. ALE should be buffered since the clear input
EXTERNAL RESET
of an SN7474 is the equivalent of 3 TTL loads. The
processor is now in the stopped state. The next instruction
Vec is initiated by clock~ a "I" into the flip-flop. This" I"
will not appear on SS unless ALE is high removing clear
from the flip-flop. In response to SS going high the pro-
cessor be~s an instruction fetch which brings ALE low
ACTIVE resetting SS through the clear input and causing the pro-
PULLUP
cessor to again enter the stopped state.
2.14 Power Down Mode
POWER ON RESET (S048AH, S049AH, 8050AH,
S039AHL, S035AHL, 8040AHL)
Extra circuitry has been added to the 8048AH/8049AHI
80S0AH ROM version to allow power to be removed from
all but the data RAM array for low power standby oper-
ation. In the power down mode the contents of data RAM
can be maintained while drawing typically 10% to 15%
of normal operating power requirements.
Figure 12. vcc serves as the SV supply pin for the bulk of circuitry
while the VDO pin supplies only the RAM array. In normal
operation both pins are a SV while in standby, Vcc is at
TIMING ground and Voo is maintained at its standby value. Ap-
plying Reset to the processor through the RESET pin
The 8048AH operates in a single-step mode as follows: inhibits any access to the RAM by the processor and
guarantees that RAM cannot be inadvertently altered as
I) The processor is requested to stop by applying a low power is removed from Vcc.
level on SS.
A typical power down sequence (Figure 14) occurs as
2) The processor responds by stopping during the address follows:
fetch portion of the next instruction. If a double cycle
instruction is in progress when the single step com- I). Imminent power supply failure is detected by user de-
mand is received, both cycles will be completed before fined circuitry. Signal must be early enough to allow
stopping. 8048AH to save all necessary data before Vcc falls
3) The processor acknowledges it has entered the stopped below normal operating limits.
state by raising ALE high. In this state (which can be
maintained indefinitely) the address of the next instruc- 2) Power fail signal is used to interrupt processor and
tion to be fetched is present on BUS and the lower vector it to a power fail service routine.
half of port 2.
4) SS is then raised high to bring the processor out of the 3) Power fail routine saves all important d<lta and machine
stopped mode allowing it to fetch the next instruction. status in the internal data RAM array. Routine may
The exii from stop is indicated by the processor bring- also initiate transfer of backup supply to the V 00 pin
ing ALE low. and indicate to external circuitry that power fail routine
is complete.
5) To stop the processor at the next instruction SS must
be brought low again soon after ALE goes low. If SS
4) Reset is applied to guarantee data will not be altered
is left high the processor remains in a "Run" mode.
as the power supply falls out of limits. Reset must be
A diagram for implementing the single-step function of held low until Vcc is at ground level.
the 8748H is shown in Figure 13. D.:!}'pe flip-flop with
preset and clear is used to generate SS. In the run mode Recovery from the Power Down mode can occur as any
SS is held high by keeping the flip-flop preset (preset has other power-on sequence with an external capacitor on
precedence over the clear input). To enter single step, the Reset input providing the necessary delay. See the
preset is removed allowing ALE to bring SS low via the previous section on Reset.
1-13
SINGLE COMPONENTMCS®-48 SYSTEM
+5V
+5V SINGLE 10K
STEP
MOMENTARY
PUSHBUTTON 10K
~U~N--~-----------~
PRESET
+5V D a SS
+5V
,--------(> CLOCK
10K
DEB OUNCE
LATCH
1/27400
ALE
SINGLE STEP CII;ICUIT
I 53 I 54 Iss I S1 I S2 I 53
I . I S3 I 54 I 55 I I S2 I
ALE~
SS
n
BUS PC 0-7
; C
P20-23 1/0 PC 8-11
5
; 110
SINGLE STEP TIMING
Figure 13. Single Step Operation
1-14
SINGLE COMPONENT MCS®-48 SYSTEM
reset the prescaler and time state generators. TO may then
be brought down with the rising edge of X I. Two clock
cycles later, with the rising edge of X I, the device enters
into Time State I, Phase 1, SS' is then brought down to
POWER - - - - . . . . . . . . .
SUPPLY PROCESSOR ~ 5 volts 4 clocks later after TO. RESET' is allowed to go
INTERRUPTED high 5 tCY (75 clocks) later for normal execution of code.
/
See Figure 15.
POWER ~ I ~g:~:~N
~~I~P~~NAL - - - - 1 - -1- - - SEQUENCE
_____~____,I FOLLOWS
RESET L, ___ _
~'--'--~-
DATA SAVE ACCESS TO
ROUTINE DATA RAM
EXECUTED INHIBITED
Figure 14. Power Down Sequence
2.15 External Access Mode
Normally the first IK (8048AH), 2K (8049AH). or 4K
(8050AH) words of program memory are automatically
fetched from internal ROM or EPROM. The EA input pin
however allows the user to effectively disable internal
program memory by forcing all program memory fetc~es
to reference external memory. The following chapter ex-
plains how access to external program memory is
accomplished.
The External Access mode is very useful in system test
and debug because it allows the user to disable his internal
applications program and substitute an external program
of his choice - a diagnostic routine for instance. In ad-
dition, the date sheet shows how internal program mem-
ory can be read externally, independent of the processor.
A "I" level on EA initiates the external accesss mode.
For proper operation, Reset should be applied while the
EA input is changed.
2.16 Sync Mode
The 8048AH, 8049AH, 8050AH has incorporated a new
SYNC mode. The Sync mode is provided to ease the
design of multiple controller circuits by allowing the de-
signer to force the device into known phase and state time.
The SYNC mode may also be utilized by automatic test
equipment (ATE) for quick, easy, and efficient synchro-
nizing between the tester and the OUT (device under test).
SYNC mode is enabled when SS' pin is raised to high
voltage level of + 12 volts. To begin synchronization, TO
is raised to 5 volts at least four clocks cycles after SS'.
TO must be high for at least four X I clock cycles to fully
1-15
SINGLE COMPONENT MCS®-48 SYSTEM
X1
PHASE 1- - - - - - - - - - -- - -
PHASE2------------- -
TIME STATE 2
55 1~~~r----------------------------------lL----------------------~-------
OV
5V
TO OV ---------------'
5V
5V
ALE OV--------------------------------------------~
RESET OV----------------------------------------------------------------~-----
SYNC MODE TIMING
Figure 15. Sync Mode Timing
3.0 PIN DESCRIPTION
The MCS-48 processors are packaged in 40 pin Dual In-
Line Packages (DIP's). Table 3 is a summary of the
functions of each pin. Figure 16 is the logic symbol
PORT for the 8048AH product family. Where it exists, the sec-
#1 ond paragraph describes each pin's function in an ex-
RESET panded MCS-48 system. Unless otherwise specified, each
PORT input is TIL compatible and each output will drive one
SINGLE STEP
#2 standard TIL load.
EXTERNAL 8048AH
MEM 8049AH
B050AH READ
TEST{
WRITE
PROGRAM
INTERRUPT
STORE ENABLE
ADDRESS
BUS LATCH ENABLE
Figure 16. 8048AH and 8049AH Logic Symbol
1-16
'SINGLE COMPONENT III!CS®·48 SYSTEM
, Table 3. Pin Description
Pin
Designation Number· Function
Vss 20 Circuit G N D potential
VDD 26 Programming power supply; 21 V during program for the 8748H18749H; + 5V during
operation for both ROM and EPROM. Low power standby pin in 8048AH and
8049AHl8050AH ROM versions.
Vee 40 Main power supply; +5V during operation and during 8748H and 8749H pro-
gramming.
PROG 25 Program pUlse; + 18V input pin during 8748H /8749H programming, Output strobe
for 8243 I/O expander.
P 10:"'P 17 27-34 8-bit quasi-bidirectional port. (Internal Pullup = 50K!!)
(Port I)
P20-P27 21-24 8-bit quasi-bidirectional port. (Internal Pullup = 50K!!)
(Port 2) 35-38
P20-P23 contain the four high order program counter bits during an external pro-
gram memory fetch and serve as a 4-bit I/O expander bus for 8243,
DO-D7 12-19 True bidirectional port which can be written or read synchronously using the RD.
(BUS) WR strobes. The port can also be statically latched.
Contains the 8 low. order program counter bits during an.external program mem~
ory fetch, and receives the addressed instruction under the control of PSEN. Also
contains the address and data during an external RAM data store instruction.
under control of ALE, RD, and W~.
TO I Input pin testable using the conditional transfer instructions JTO and J NTO. TO
can be designated as a clock output using ENTO CLK instruction. TO is also used
durin!! programming and sync mode.
Tl 39 Input pin testable using the JT I, and J NT I instructions. Can be designated the
event counter input using the STRI' CNT instruction. (See Section 2.10).
INT 6 Interrupt input. Initiates an interrupt if interrupt is enabled. Interrupt is disabled
after a reset. (Active low)
Interrupt must remain low for at least 3 machine cycles to ensure proper operation.
--
RD 8 Output strobe activated during'a BUS read. Can be used to enable data onto the
BUS from an external device. (Active low)
Used as a Read Strobe to External Data Memory.
RESET 4 . Input which is used to initialize the processor. Also used during EPROM programming
and verification. (Active low) (Internal pullup = 80K ll)
WR 10 Output strobe during a BUS write. (Active low) Used as write strobe to external
data memory.
ALE II Address Latch Enable. This signal occurs once during each cycle and is useful as
a clock output.
The negative edge of ALE strobes address into external data and program memory.
1-17
SINGLE COMPONENT MCS®-48 SYSTEM
Table 3. Pin Description (Continued)
Pin
Designation Number' Function
--
PSEN 9 Program Store Enable. This output occurs only during a fetch to external program
memory. (Active low)
- Single step input can be used in conjunction with;\ I.E to "single step" the processor
SS 5
through each instruction. (Active low) (Internal pull LIp ~. JOOKfl) +12V for sync
modes (See 2.16).
EA 7 External Access input which forces all program memory fetches to reference ex-
ternal memory. Useful for emulation and debug, and essential for testing and pro-
gram verification. (Active high) + 12V for 8048AH /8049AH /8050AH program
verification and + 18V for 8748H j 8749H program verification (Internal pullup =
10M!} on 8048AH /8049AH j8035AHL/8039AH Lj 8050AH /8040AHL)
XTALI 2 One side of crystal input for internal oscillator. Also input for external source.
XTAL2 3 Other side of crystal/external source input.
'Unless otherwise stated. inputs do not have internal pullup resistors. 8048AH, 8748H. 8049AH. 8050AH. 8040AHL
4.0 PROGRAMMING, VERIFYING AND 8748H AND 8749H ERASURE
ERASING EPROM CHARACTERISTICS
The internal Program Memory of the 8748H and the The erasure characteristics of the 8748H and 8749H are
8749H may be erased and reprogrammed by the user as such that erasure begins to occur when exposed to light
explained in the following sections. See also the 8748H with wavelengths shorter than approximately 4000 Angs-
and 8749H data sheets. troms (A). It should be noted that sunlight and certain
types of fluorescent lamps have wavelengths in the
4.1 ProgramminglVerification 3000--4000A range. Data show that constant exposure to
room level fluorescent lighting could erase the typical
In brief, the programming process consists of: activating 8748H and 8749H in approximately 3 years while it would
the program mode, applying an address, latching the ad- take approximately 1 week to cause erasure when exposed
dress, applying data, and applying a programming pulse. to direct sunlight. If the 8748H or 8749H is to be exposed
This programming algorithm applies to both the 8748H to these types of lighting conditions for extended periods
and 8749H. Each word is programmed completely before of time, opaque labels should be placed over the 8748H
moving on to the next and is followed by a verification window to prevent unintentional erasure.
step. The following is a list of the pins used for program-
ming and a descsription of their functions: When erased, bits of the 8748H and 8749H Program Mem-
ory are in the logic "0" state.
Pin Function
XTAL 1 Clock Input (3 to 4 MHz) The recommended erasure procedure for the 8748H and
Reset Initialization and Address Latching 8749H is exposure to shortwave ultraviolet light which
Test 0 Selection of Program (OV) or Verify has a wavelength of 2537 Angstroms (A) .. The integrated
(5V) Mode dose (i.e., UV intensity X exposure time) for erasure
Activation of Program/Verify Modes should be a minimum of 15W-sec/cm2. The erasure time
Address and Data Input Data Output with this dosage is approximately 15 to 20 minutes using
During Verify an ultraviolet lamp with a 12000jLW/cm2 power rating.
P20-1 Address Input for 8748H The 8748H and 8749H should be placed within one inch
P20-2 Address Input for 8749H from the lamp tubes during erasure. Some lamps have a
VDD Programming Power Supply filter in their tubes and this filter should be removed before
PROG Program Pulse Input erasure.
PIO-Pll Tied to ground (8749H only)
1-18
SINGLE COMPONENT MCS-48 SYSTEM
COMBINATION PROGRAMIVERIFY MODE (EPROM. ONLY)
18V /
EA 5V _ _ _ _- J
!.------IPROGRAM--------+--VERIFY--t·----PROGRAM-
I--tTW--1 ~----.......
TO
I"'----tww--
r-----------------~--------~
RESET
DBO-DB7 ==>--- DATA TO BE
PROGRAMMED VALID
LAST NEXT
P20-P22
ADDRESS ADDRESS
-- - - - - - =--...:-''------
VERIFY MODE (ROM/EPROM)
EA
'TO
RE~ET \ ' -_ _ _ _ _ _ _ _ ...J/ \'--_ _...-.J/
DBO-DB7 ==>--- ADDRESS
(0-7) VALID
---{ NEXT X
\.._..;.A;;:;D.;;.D.;.;R.;;.ES"-S;;.......J.
NEXTDATA}- __ _
. OUT VALID.
P20-P22 ADDRESS (8-10) VALID NEXT ADDRESS VALID
NOTES:
1. PROG MUST FLOAT IF EA IS LOW (I.E.," 18V).
'TO ON EPROM ONLY.
Figure 17. ProgramNerify Sequence for 8749H/8748H
1-19
MCS®,.48 Expanded
System.
2
EXPANDED MCS®-48 SYSTEM
1.0 INTRODUCTION 1) The contents of the 12-bit program counter will be
output on BUS and the lower half of port 2.
If the capabilities resident on the single-chip 8048AHf
2) Address Latch Enable (ALE) will indicate the time at
8748Hf8035AHLl8049AHf8749Hf8039AHL are not suf-
which address is valid. The trailing edge of ALE is
ficient for your system requirements, special on-board cir-
used to latch the address externally.
cuitry allows the addition of a wide variety of external
memory, 110, or special peripherals you may require. The 3) Program Store Enable (PSEN) indicates that an exter-
processors can be directly and simply expanded in the nal instruction fetch is in progress and serves to enable
foiIowing areas: the external memory device.
• Program Memory to 4K words 4) BUS reverts to input (floating) mode and the processor
accepts its 8-bit contents as an instruction word.
• Data Memory to 320 words (384 words with
8049AH)
• 110 by unlimited amount
• Special Functions using 8080/8085AH peripherals ALE J L
By using bank switching techniques, maximum capability
is essentially unlimited. Bank switching is discussed later PSEN
in the chapter. Expansion is accomplished in two ways:
FLOATING
~FLOATINGO' FLOATING
1) Expander 110 - A special 110 Expander circuit, the
8243, provides for the addition of four 4-bit InputJ BUS
Output ports with the sacrifice of only the lower half ADDRESS INSTRUCTION
(4-bits) of port 2 for inter-device communication. Mul-
tiple 8243's may be added to this 4-bit bus by gen-
erating the required "chip select" lines.
Figure 1. Instruction Fetch from
2) Standard 8085 Bus - One port of the 8048AH/ External Program Memory
8049AH is like the 8-bit bidirectional data bus of the
8085 microcomputer system allowing interface to the All instruction fetches, including internal addresses, can be
numerous standard memories and peripherals of the forced to be external by activating the EA pin of the 8048AHf
MCSIII>-80/85 microcomputer family. 8049AHf8050AH. The 8035AHl/8039AHl/8040AHL pro-
cessors without program memory always operate in the ex-
MCS-48 systems can be configured using either or both ternal program memory mode (EA = 5V).
of these expansion features to optimize system capabilities
to the application. 2.2 Extended Program Memory
Addressing (8eyond2K)
Both eJ>pander devices and standard memories and pe-
ripherals can be added in virtually any number and com- For programs of 2K words or less, the 8048AHf8049AH
bination required. addresses program memory in the conventional manner.
Addresses beyond 2047 can be reached by executing a
2.0 EXPANSION OF PROGRAM MEMORY program memory bank switch instruction (SEL MBO, SEL
MBI) followed by a branch instruction (JMP or CALL).
Program Memory is expanded beyond the resident IK or The bank switch feature extends the range of branch in-
2K words by using the 8085 BUS feature of the MCS®- structions beyond their normal 2K range and at the same
48. All program memory fetches from the addresses less time prevents the user from inadvertently crossing the 2K
than 1024 on the 8048AH and less than 2048 on the boundary.
8049AH occur internally with no external signals being
generated (except ALE which is always present). At ad- PROGRAM MEMORY BANK SWITCH
dress 1024 on the 8048AH, the processor automatically
initiates external program memory fetches. The switching of 2K program memory banks is accom-
plished by directly setting or resetting the most significant
2.1 Instruction Fetch Cycle (External) bit of the program counter (bit 11); see Figure 2. Bit
11 is not altered by normal incrementing of the program
As shown in Figure 1, for all instruction fetches from counter but is loaded with the contents of a special flip-
addresses of 1024 (2048) or greater, the following will flop each time a IMP or CALL instruction is executed.
occur: This special flip-flop is set by executing an SEL MBI
2-1
EXPANDED MCS®-48 SYSTEM
instruction and reset by SEL MBO. Therefore, the SEL counter is held at "0" during the interrupt service routine.
MB instruction may be executed at any time prior to the The end of the service routine is signalled by the execution
actual bank switch which occurs during the next branch of an RETR instruction. Interrupt service routines should
instruction encountered. Since all twelve bits of the pro- therefore be contained entirely in the lower 2K words of
gram counter, including bit II,' are stored in the stack, program memory. The execution of a SEL MBO or SEL
when a Cali is executed, the user may jump to subroutines MB I instruction within an interrupt routine is not rec-
across the 2K boundary and the proper bank will be re- ommended since it will not alter PC II while in the routine,
stored upon ret~. However, the bank switch flip-flop but will change the il!ternal "ip-f!op.
will not be altered on return.
2.3 Restoring 1/0 Port Information
I I r IAD I Although the lower half of Port 2 is used to output the
C
Alll Al0 Asl Asl A71 A61 A51
,
A4
• Counts OOOH to 7FFH
A31 A21 Al
Conventional pr~gram Counter
• Overflows 7FFH to OOOH .
JMP or CALL Instructions transfer contents
I
four most significant bits of address during an external
program memory fetch, the 110 information is still out-
puted during certain portions of each machine cycle. 110
information is always present on Port 2's lower 4 bits at
the rising edge of ALE and can be sampled or latched 'at
of internaflllpflop to All this time .
• Flipflop set by SEL MBl
.; Flipflop reset by SEL MBO
or by RESET
2.4 Expansion Examples
Durfng Interrupt service routine
All is forced to "0"
AII'12 bits are saved in stack Shown in Figure 3 is the addition of 2K words of
program memory using an 2716A 2K x S ROM to give
a total of 3K words of program memo!L..!!!. this case no
Figure 2. Program .Counter chip select decoding is required and PSEN enables the
memory directly through the chip select input. If the sys-
INTERRUPT ROUTINES tem.requires only 2K of program memory, the same con-
figuration cim be used with an S035AHL substituted for
Interrupts always vector the program counter to location the S04SAH. The S049AH would provide 4K of program
3 or 7in the first 2K bank, and bit 11 of the program memory with the same configuration.
3
PORT 20-22
'<; 7
"-
8048AH ALE 11 ) ADDRESS
74LS373 v 2716
rr=V
LATCH
EPROM
A
BUS I\, S DATA
OUT
PSEN CS
USING 2K x S EPROM
Figure 3. Expanding MCS<!>"48 Program Memory Using Standard Memory Products
2-2
EXPANDED MCS®-48 SYSTEM
Figure 4 shows how the 8755/8355 EPROM/ROM with
lIO interfaces directly to the 8048AH without the need
ALE
for an address latch. The 8755/8355 contains an internal
PSEN
8-bit address latch eliminating the need for an 8212 latch.
RD
In addition to a 2K x 8 program memory, the 8755/8355
WR lOW 2K, S also contains 16 lIO lines addressable as two 8-bit ports.
ROMI
8048AH RD lOR These ports are addressed as external RAM; therefore the
EPROM
8049AH
WITH 1/0 RD and WR outputs of the 8048AH are required. See the
BUS
AlDO_7 8~~1 following section on data memory expansion for more
S755 detail. The subsequent section on I/O expansion explains
P20-P23
the operation of the 16 I/O lines.
AS-A10, CS
3.0 EXPANSION OF DATA MEMORY
Data Memory is expanded beyond the resident 64 words
by using the 8085AH type bus feature of the MCS®-48.
TEST 1/0 3.1 Read/Write Cycle
INPUTS
All address and data is transferred over the 8 lines of
BUS. As shown in Figure 5, a read or write cycle
Figure 4. External Program Memory Interface occurs as follows:
ALE J 11...--_ _ _ _----' L
RD
BUS FLOATING ~_ _ _F_L_O_A_T_IN_G_ __
FLOATING
READ FROM EXTERNAL DATA MEMORY
ALE J L
BUS FLOATING FLOATING
WRITE TO EXTERNAL DATA MEMORY
Figure 5. External Data Memory Timings
2-3
EXPANDED MCS®-48 SYSTEM
I) The contents of register RO or Rl is outputed on BUS. 4.0 EXPANSION OF INPUT/OUTPUT
2) Address Latch Enable (ALE) indicates addresss is
valid. The trailing edge of ALE is used to latch the There are four possible modes of 110 expansion with the
address externally. 8048AH: one using a special low-cost expander, the 8243;
another using standard MCS-80/85 I/O devices; and a third
3) A read (RD) or write (WR) pulse on the corresponding using the combination memory liD expander devices the
output pins of the 8048AH indicates the type of data 8155, 8355, and 8755. It is also possible to expand using
memory access i~ogress. Output data is valid at the standard TTL devices.
trailing edge of WR and input data must be valid at
the trailing edge of RD. 4.1 1/0 Expander Device
4) Dat (8 bits) is transferred in or out over BUS.
The most efficient means· of I/O expansion for small sys-
3.2 Addressing External Data Memory tems is the 8243 liD Expander Device which requires only
External Data Memory is accessed with its own two-cycle 4 port lines (lower half of Port 2) for communication with
move instructions. MOVXA, @R and MOVX@R, A, the 8048AH. The 8243 contains four 4-bit liD ports which
which transfer 8 bits of data between the accumulator and serve as an extension of the on-chip liD and are addressed
the external memory location addressed by the contents as ports #4-7 (see Figure 13-7). The following operations
of one of the RAM Pointer Registers RO and R 1. This may be perfonned on these ports:
allows 2~6 locations to be addressed in addition to the
resident locations .. Additional pages may be added by • Transfer Accumulator to Port
"bank switching" with extra output lines of the 8048AH. • Transfer Port to Accumulator
• AND Accumulator to Port
3.3 Examples of Data Memory Expansion
• OR Accumulator to Port
Figure 6 shows how the 8048-AH can be expanded
using the 8155 memory and liD expanding device. Since A 4-bit transfer from a port to the lower half of the Ac-
the 8155 has an internal8-bit address latch, it can interface cumulator sets the most significant four bits to zero. All
directly to the 8048AH without the use of an external communication between the 8048AH and the 8243 occurs
latch. The 8155 provides an additional 256 words of static over Port 2 lower (P20--P23) with timing provided by an
data memory and also includes 22 liD lines and a 14-bit output pulse on the PROG pin of the processor. Each trans-
timer. See the following section on liD expansion and the fer consists of two 4~bit nibbles: The first containing the
8155 data sheet for more details on these additional "op code" and port address, and the second containing
features. the actual 4 bits of data.
BUS 8 ADO_7
v
ALE ALE 8155
22· 1/0
256' 8
8048AH WR WR RAM TIMER IN
RD AD TIMER OUT
PORT 101M
3 J J,;:JTS
18 ) 1/0
Figure 6. 8048AH Interface to 256 x 8 Standard Memories
2-4
EXPANDED MCS®-48 SYSTEM
CHIP SELECT CONNECTION IF MORE
THAN ONE EXPANDER IS USED
1/0
P4 4 1/0
PROG
TEST PS 4 1/0
80S0AH 2
INPUTS 8243
8049AH
8048AH
P6 4 1/0
P20-P23 4. DATA IN
P2
P7 4 1/0
EXPANDER INTERFACE
~OG
BITS 0, 1 BITS2,3
\ /
"'-.-----' 00,
01
10
J'
PORT
ADDRESS
OO}READ
01
10
WRITE
OR
,--<'-___.,X'-_~----»-----
11 11 AND
P20-P23
ADDRESS DATA (4-BITS)
ANDOPCODE
(4-BITS)
OUTPUT EXPANDER TIMING
Figure 7. 8243 Expander 1/0 Interface
Nibble I Nibble 2 4.2 1/0 Expansion with Standard
3 2 I a 3 2 I a Peripherals
II II IA IA I I did I did I Standard MCS-80/85 type 110 devices may be added to
the MCS®-48 using the same bus and timing used for Data
Instruction Port data
Code
Memory expansion. Figure 8 shows an example of how
Address
an 8048AH can be connected to an MCS-85 peripheral.
II AA 110 devices reside on the Data Memory bus and in the
data memor.y address space and are accessed with the same
00 Read 00 - Port #4
01Write 01 - Port #5 MOVX instructions. (See the previous section on data
100R 10 - Port #6 memory expansion for a description of timing.) The fol-
IIAND II - Port #7 lowing are a few of the Standard MCS-80 devices which
are very useful in MCS®-48 systems:
• 8214 Priority Interrupt Encoder
A high to low transition of the PROG line indicates that
address is present, while allow to high transition indicates • 8251 Serial Communications Interface
the presence of data. Additional 8243's may be added to • 8255 General Purpose Programmable 110
the four-bit bus and chip selected using additional output • 8279 Keyboard/Display Interface
lines from the 8048AH/8748H. • 8254 Interval Timer
1/0 PORT CHARACTERISTICS 4.3 Combination Memory and
1/0 Expanders
Each of the four 4-bit ports of the 8243 can serve as either As mentioned in the sections on program and data memory
input or output and can provide high drive capability in expansion, the 8355/8755 and 8155 expanders also contain
both the high and low state. 110 capability.
2-5
EXPANDED MCS®-48 SYSTEM
KEYBOARD
8 INPUTS
INT INT
P20 C/O
CNTL
8279
KEYBOARD SCAN
8048AH DISPLAY OUTPUTS
RD RD
(A) DISPLAY
WR WR OUTPUT
BUS DATA (B) DISPLAY
8
BUS OUTPUT
Cs
-
Figure 8. Keyboard/Display Interface
8355/8755: These two parts of ROM and EPROM equiv- port. These three registers and a Control/Status register
alents and therefore contain the same 110 structure. 1/0 are accessible as external data memory with the MOVX
consists of two 8-bit ports which nonnally reside in the instructions. The contents of the control register deter-
external data memory address space and are accessed with mines the mode of the three ports. The ports can be pro-
MOVX instructions. Associated with each port is an 8- grammed as input or output with or without associated
bit Data Direction Register which defines each bit in the handshake communication lines. In the handshake mode,
port as either an input or an output. The data direction lines of the six-bit port become input and output strobes
registers are directly addressable, thereby allowing the for the two 8-bit ports. Also included in the 8155 is a
user to define under software control each individual bit 14-bit programmable timer. The clock input to the timer
of the ports as either input or output. All outputs are and the. timer overflow output are available on external
statically latched and double buffered. Inputs are not pins. The timer can be programmed to stop on tenninal
latched. count or to continuously reload itself. A square wave or
8155/8156: 110 on the 8155/8156 is configured as two pulse output on tenninal count can also be specified.
8-bit programmable 1/0 ports and one 6-bit programmable
8048AH
PROGr-----------~~------~----~------------~------------~
Figure 9. Low Cost I/O Expansion
2-6
EXPANDED MCS®-48 SYSTEM
1/0 EXPANSION EXAMPLES Figure 10 shows the 8048AH interface to a standard
MCS®-80 peripheral; in this case, the 8255 Programmable
Figure 9 shows the expansion of I/O using multiple Peripheral Interface, a 40-pin part which provides three
8243's. The only difference from a single 8243 system is 8-bit programmable I/O ports. The 8255 bus interface is
the addition of chip selects provided by additional8048AH typical of programmable MCS®-80 peripherals with an
output lines. Two output liens and a decoder could also .8-bit bidirectional data bus, a RD and WR input for Read/
be used to address the four chips. Large numbers of8243's Write control, a CS (chip select) input used to enable the
would require a chip select decoder chip such as the 8205 ReadlWritecontrol logic and the address inputs used to
to save 110 pins. select various internal registers.
110. B255 P20 110 B255
A1 PROGRAM- PORT P21 A1 PROGRAM- PORT
MABLE A MABLE A
PERIPHERAL PERIPHERAL
PORT PORT
B04BAH ALE INTERFACE B04BAH. _ INTERFACE
B
RO RO B RO iffi
PORT WR WR PORT
C C
BUS 8 00-7
CS CS
OPTION #1 -=- OPTION #2 -=-
Figure 10. Interface to MCS®-80 Peripherals
Interconnection to the 8048AH is very straightforward addressing of the various memories and I/O ports. Note
with BUS, RD, and WR connecting directly to the cor- that in this configuration address lines AIO and All have
responding pins on the 8255. The only design consider- been ORed to chip select the 8355. This ensures that the
ation is the way in which the internal registers of the 8255 chip is active for all external program memory fetches in
are to be addressed. If the registers are to be addressed the IK to 3K range and is disabled for all other addresses.
as external data memory using the MOVX instructions, This gating has been added to allow the I/O port of the
the appropriate number of address bits (in this' case, 2) 8355 to be used. If the chip was left selected all the time,
must be latched on BUS using ALE as described in the there would be conflict between these ports and.the RAM
section on external data memories. If only a single device and I/O of the 8156. The NOR gate could be eliminated
is connected to BUS,. the 8255 may be continuously se- and All connected directly to the CE (instead of CE) input
iected by grounding CS. If multiple 8255's are used, ad- ofthe 8355; however, this would create a IK word "hole"
ditional address bits can be latched and used as chip in the program memory by causing the 8355 to be active
selects. in the 2K and 4K range instead of the normal IK to 3K
range.
A second addressing method eliminates externaJ,Iatches
and chip sclect decoders. by using output port lincs as ad- In this system the various locations are addressed as
dress and chip select lines directly. rhis method .. of follows:
coursc. requires the setting of an output port with address • Data RAM - Addresses 0 to 255 when Port 2 Bit
information prior to e.xccuting a MOYX instruction. o has been previously set = 1 and Bit 1 set = 0
• RAM I/O - Addresses 0 to 3 when Port 2 Bit 0 =
5.0 MULTI-CHIP MCS®-48 SYSTEMS 1 and Bit 1 = 1 '
Figure 11 shows the addition of two memory expanders • ROM I/O - Addresses 0 to 3 when Port 2 Bit 2 or
Bit 3 = 1
to the 8048AH, one 8355/8755 ROM and one 8156 RAM.
The main consideration in designing such a system is the See the memory map in Figure 12.
2-7
EXPANDED MCS81-48 SYSTEM
8156/8355
AB-l0
PORT
83551
8755
ROM
EPROM
P20-3 PORT
ALE t---f-+--' AOO-7
PSENI---++--' 101M
B04BAH ROI---++---f
WR t---++----I
TIMER
OUT
Figure 11. The Three-Component MCS®-48 System
6.0 MEMORY BANK SWITCHING Jumping to subroutines across the boundary should be
avoided when possible since the programmer must keep
Certain systems may require more than the 4K words of track of which bank to return to after completion of the
program memory which are directly addressable by the subroutine. If these subroutines are to be nested and ac-
program counter or more than the 256 data memory and cessed from either bank, a software "stack" should be
I/O locations directly addressable by the pointer registers implemented to save the bank switch bit just as if it were
RO and Rl. These systems can be achieved using "bank another bit of the program counter.
switching" techniques. Bank switching is merely the se-
lection of various blocks of "banks" of memory using From a hardware standpoint bank switching is very
dedicated output port lines from the processor. In the case straightforward and involves only the connection of an
of the 8048AH, program memory is selected in blocks of I/O line or lines as bank enable signals. These enables are
4K words at a time, while data memory and I/O are en- ANDed with normal memory and I/O chip select signals
abled 256 words at a time. to activate the proper bank.
The most important consideration in implementing two or
more banks is the software required to cross the bank 7.0 CONTROL SIGNAL SUMMARY
boundaries. Each crossing of the boundary requires that
the processor first write a control bit to an output port Table 1 summarizes the instructions which activate the
before accessing memory or I/O in the new bank. If pro- various control outputs of the MCS®-48 processors. Dur-
gram memory is being switched, programs should be or- ing all other instructions these outputs are driven to the
ganized to keep boundary crossings to a minimum. active state.
2-8
EXPANDED MCS®-48 SYSTEM
Table 1. MCS®-48 Control Signals
The latched mode (INS, OUTL) is intended for use in the
Control single-chip configuration where BUS is not begin used as
Signal When Active an expander port. OUTL and MOVX instructions can be
RD During MOVX, A, @R or INS Bus mixed if necessary. However, a previously latched output
will be destroyed by executing a MOVX instruction and
WR During MOVX @R, A or OUTL Bus BUS will be left in the high impedance state. INS does
ALE Every Machine Cycle not put the BUS in a high impedance state. Therefore,
PSEN During Fetch of external program mem- the use of MOVX after OUTL to put the BUS in a high
ory (instruction or immediate data) impedance state is necessary before an INS instruction
intended to read an external word (as opposed to the pre-
PROG During MOVD, A,P ANLD P,A MOVD viously latched value).
P,A ORLD P,A
OUTL should never be used in a system with external
8.0 PORT CHARACTERISTICS program memory, since latching BUS can cause the next
instruction, if external, to be fetched improperly.
8.1 BUS Port Operations
Thc BUS port can operate in three different modes: as a 8.2 Port 2 Operations
latchcd lJO port, as a bidirectional bus port, or as a pro-
gram memory address output when external memory is The lower half of Port 2 can be used in three different
used. The BUS port lines are either active high, active ways: as a quasi-bidirectional static port, as an 8243 ex-
low, or high impedance (floating). pander port, and to adddress external program memory.
PROGRAM MEMORY
SPACE
BFFH
MBl
8355
(2K)
EXTERNAL DATA
MEMORY SPACE
MBOI------i400H FI======11 8~g5
- - - - - - - - 300H
RESIDENT
r
1
I 8155
I 10
- - - - - - - 200H f - - - - - j RESIDENT DATA
(lK) MEMORY
- - - - - - - - 100H f - - - - - 11 (64)
'------'OOOH 1--------1
SECTION ADDRESS DESIGNATION
PROG. MEM OOO-BFF
DATA MEM 100-IFF
8155 PORTS 300 CMD/STATUS
301 PORTA
302 PORT B
303 PORT C
304 TIMER LOW
8355 PORTS 305 TIMER HI
400 PORT A
401 PORT B
402 DORA
403 DDR B
Figure 12. Memory Map for Three-Component MCS' -48 Family
2-9
EXPANDED MCS®-48 SYSTEM
In all cases outputs are driven low by an active device viously latched will be automatically removed temporarily
and driven high momentarily by a low impedance device while address is present, then retored when the fetch is
and held high by a high impedance device to vee. complete. However, if lower Port 2 is used to commu-
nicate with an 8243, previously latched I/O information
The port may contain latched I/O data prior to its usc in will be removed and not restored. After an input from the
another mode without affecting operation of either. If 8243. P20-3 will be left in the input mode (floating). After
lower Port 2 (P20-3) is used to output address for an an output to the 8243, P20-3 will contain the value written,
external program memory fetch. the I/Oinformation pre- ANDed, or ORed to the 8243 port.
1/0 1/0
8749H
8049AH
8048AH
8748H ,--_ _ _ _--' 0 0
8035AHL
8039AHL
1/0
=
=
Figure 13. MCS® -48 Expansion Capability
2-10
MCS®--48 Instruction Set . 3
MCS®-48 INSTRUCTION SET
1.0 INTRODUCTION 1.1 Data Transfers
The MCS®-48 instruction set is extensive for a machine As can be seen in Figure 1 the 8-bit accumulator is
of its size and has been tailored to be straightforward and the central point for all data transfers within the 8048.
very efficient in its use of program memory. All instruc- Data can be transferred between the 8 registers of each
tions are either one or two bytes in length and over 80% working register bank and the accumulator directly, i.e.,
are only one byte long. Also, all instructions execute in the source or destination register is specified by the in-
either one or two cycles and over 50% of all instructions struction. The remaining locations of the internal RAM
execute in a single cycle. Double cycle instructions in- array are referred to as Data Memory and are addressed
clude all immediate instructions, and alllJO instructions. indirectly via an address stored in either RO or R I of the
active register bank. RO and R I are also used to indirecly
The MCS-48 microcomputers have been designed to han- address external data memory when it is present. Transfers
dle arithmetic operations efficiently in both binary and to and from internal RAM require one cycle, while trans-
BCD as well as handle the single-bit operations required fers to external RAM require two. Constants stored in
in control applications. Special instructions have also been Program Memory can be loaded directly to the accumu-
included to simplify loop counters, table look-up routines, lator and to the 8 working registers. Data can also be
and N-way branch routines. transferred directly between the accumulator and the on-
i-------·---l
I PROGRAM DATA I
MEMORY MEMORY
(#DATA) MOV I
I WORKING REG
I ADD
MOV
MOV
ADD
MOV
ADD
I
MOVP ANL ANL
I MOVP3
ANL
ORL
XRL
ORL
XRL
I
ORL XCH XCH
XRL XCHD
EXPANDER EXTERNAL
MEMORY
~_~ PORTS '-.rr-'-'"---,-,/ '--_ _ _ ~-~-_.,..~---.,.,...-----..I V=..!.:::.!.-v' AND
PERIPHERALS
8749H
ANL
ORL 8048AH
8049AH
8748H I
8035AHL' , 'NO PROGRAM
MEMORY
Figure 1. Data Transfer Instructions
3-1
MCS®-48 INSTRUCTION SET
board timer counter or the accumulator and the Program 1.4 Flags
Status word (PSW). Writing to the PSW alters machine
status accordingly and provides a means of restoring status There are four user-accessible flags in the 8048AH:Carry,
after an interrupt or. of altering the stack pointer if Auxiliary Carry, FO and F I. Carry indicates overflow of
necessary. the accumulator, and Auxiliary Carry is used to indiate
overflow between BCD digits and is used during decimal-
1.2 Accumulator Operations adjust operation. Both Carry and Auxiliary Carry are ac-
cessible as part of the program status word and are stored
Immediate data, data memory, or the working registers on the stack during subroutines. FO and Fl are undedicated
can be added with or without carry to the accumulator. general-purpose flags to be used as the programmer de-
These sources can also be ANDed, ORed, or Exclusive sires. Both flags can be cleared or complemented and
ORed to the accumulator. Data may be moved to or from tested by conditional jump instructions. FO is also acces-
the accumulator and working registers or .data memory. sible via the Program Status word and is stored on the
The two values can also be exchanged in a single stack with the carry flags.
operation.
1.5 Branch Instructions
In addition, the lower 4 bits of the accumulator can be
'exchanged with the lower 4-bits of any of the internal The unconditional jump instruction is two bytes and allows
RAM locations. This instruction, along with an instruction jumps anywhere in the first 2K words of program memory.
which swaps the upper and lower 4-bit halves of the ac- Jumps to the second 2K of memory (4K words are directly
cumulator, provides for easy handling of 4-bit quantities, addressable) are made first by executing a select memory
including BCDnumbers. To facilitate BCD arithmetic, a bank instruction, then execlIting the jump instruction. The
Decimal Adjust instruction is included. This instruction 2K boundary can only he crossed via a jump or subroutine
is used to correct the result of the binary addition of two call instruction, i.e., the bank switch does not occur until
2-digit BCD numbers. Performing a decimal adjust on the a jump is executed. Once a memory bank has been selected'
result in the accumulator produces the required BCD all subsequent jumps will be to the selected bank until
result. another select memory bank instruction is executed. A
subroutine in the opposite bank can be accessed by a select
Finally, the accumulator can be incremented, decre- memory bank instruction followed by a call instruction.
mented, cleared, or complemented and can be rotated left Upon completion of the subroutine, execution will auto-
or right I bit at a time with or without carry. matically return to the original bank; however, unless the
original bank is reselected, the next jump instruction en-
Although there is no subtract instruction in the 8048AH, countered will again transfer execution to the opposite
this operation can be easily implemented with three single- bank.
byte single-cycle instructions.
Conditional jumps can test the following inputs and ma-
A value may be subtracted from the accumulator with the chine status:
result in the accumulator by: .
• TO Input Pin
• Complementing the accumulator • T1 Input Pin
• Adding the value to the accumulator • INT Input Pin
• Complementing the accumulator • Accumulator Zero
• Any bit of Accumulator
1.3 Register Operations • Carry Flag
The working registers can be accessed via the accumulator • FO Flag
as explained above, or can be loaded immediate with • FI Flag
constants from program memory. In addition, they can be
incremented or decremented or used as loop counters using Conditional jumps allow a branch to any address within
the decrement and jump, if not zero instruction, as ex- the current page (256 words) of execution. The conditions
plained under branch instructions. tested are the instantaneous values at the time the con-
ditional jump' is executed. For instance, the jump on ac-
All Data Memory including working registers can be ac- cumulator zero instruction tests the accumulator itself. not
cessed with indirect instructions via RO and RI and can an intermediate zero flag.
be incremented.
3-2
MCS®-48 INSTRUCTION SET
The ~crement register and jump if not zero instruction The working register bank switch instructions allow the
combines a decrement and a branch instruction to create programmer to immediately substitute a second 8-register
an instruction very useful in implementing a loop counter. working register bank for the one in use. This effectively
This instruction can designate anyone of the 8 working provides 16 working registers or it can be used as a means
registers as a counter and can effect a branch to any address of quickly saving the 'contents of the registers in response
within the current page of execution. to an interrupt. The user has the option to switch or not
to switch banks on interrupt. However, if the banks are
A single-byte indirect jump instruction allows the program switched, the original bank will be automatically restored
to be vectored to anyone of several different locations upon execution of a return and restore status instruction
based on the contents of the accumulator. The contents at the end of the interrupt service routine.
of the accumulator points to a location in program memory
which contains the jump address. The 8-bit jump address A special instruction enables an internal clock, which is
refers to the current page of execution. This instruction the XTAL frequency divided by three to be output on pin
could be used, for instance, to vector to anyone of several TO. This clock can be used as a general-purpose clock in
routines based on an ASCII character which has been the user's system. This instruction should'be used only to
loaded in the accumulator. In this way ASCII key inputs initialize the system since the clock output can be disabled
can be used to initiate various routines. only by application of system reset.
1.6 Subroutines 1.9 Input/Output Instructions
Subroutines are entered by executing a call instruction. Ports I and 2 are 8-bit static I/O ports which can be loaded
Calls can be made like unconditional jumps to any address to and from the accumulator. Outputs are statically latched
in a 2K word bank, and jumps across the 2K boundary but inputs are not latched and must be read while inputs
are executed in the same manner. Two separate return are present. In addition, immediate data from program
instructions determine whether or not status (upper 4-bits memory can be ANDed or ORed directly to Port 1 and
of PSW) is restored upon return from the subroutine. Port 2 with the result remaining on the port. This allows
"masks" stored in program memory to selectively set or
The return and restore status instruction also signals the reset individual bits of the 110 ports. Ports 1 and 2 are
end of an. interrupt service routine if one has been in configured to allow input on a given pin by first writing
progress. a "I" out to the pin.
1.7 Timer Instructions An 8-bit port calh;:d BUS can also be accessed via the
accumulator and can have. statically latched outputs as
The 8-bit on board timer/counter can be loaded or read well. It too can have immediate data ANDed or ORed
via the accumulator while the counter is stopped or while directly to its outputs, however, unlike ports 1 and 2, all
counting. The counter can be started as a timer with an eight lines of BUS must be treated as either input or output
internal clock source .or an event counter or timer with an at anyone time. In addition to being a static port, BUS
external clock applied to the Tl input pin. The instruction can be used as a true synchronous bi-directional port using
executed determines which clock source is used. A single the Move External instructions used to access external
instruction stops the counter whether it is operating with data memory. When these instructions are executed, a
an internal or an external clock source. In addition, two corresponding READ or WRITE pulse is generated and
instructions allow the timer interrupt to be enabled or data is valid only at 'that time. When data is not being
disabled. transferred, BUS is in a high impedance state. Note that
the OUTL, ANL, and the ORL instructions for the BUS
1.8 Control Instructions are for use with internal program memory only.
Two instructions allow the external interrupt source to be The basic three on-board IIO ports can be expanded via
enabled or disabled. Interrupts are initially disabled and a 4-bit expander bus using half of port 2. IIQ expander
are automatically disabled while an interrupt service rou- devices on this bus consist of four 4-bit ports which are
tines is in progress and re-enabled afterward. addressed as ports 4 through 7. These ports have their
own AND and OR instructions like the on-board ports as
There are four memory bank select instructions, two to well as move instructions to transfer data in or out. The
designate the active working register bank and two to expander AND and OR instructions, however, combine
control program memory banks. The operation of the pro- the contents of accumulator with the selected port rather
gram memory bank switch is explained in Section 2.2 than immediate data as is done with the on-board ports.
in the Expanded MCS-48 System chapter.
3-3
MCS®-48 INSTRUCTION SET
YO devices can also be added externally using the BUS The alphabetical listing includes the following
port as the expansion bus. In this case the YO ports become information.
"memory mapped", i.e., they are addressed in the same
• Mnemonic
way as external· data memory and exist in the external
data memory address space addressed by pointer register • Machine Code
RO or Rl. . • Verbal Description
• Symbolic Description
• Assembly Language Example
The machine code is represented with the most significant
2.0 INSTRUCTION SET DESCRIPTION bit (7) to the left and two byte instructions are represented
with the first byte on the left. The assembly language
The following pages describe the MCS~-48 instruction set
examples are formulated as follows:
in detail. The instruction set is first summarized with in-
structions grouped functionally. This summary page is Arbitrary
followed by a detailed description listed alphabetically by Label: Mnemonic, Operand;
mnemonic opcode.
Descriptive Comment
3-4
MCS®-48 INSTRUCTION SET
8048AH/87 48H/8049AH/8050AH/87 49H
Instruction Set Summary
Mnemonic Description Bytes Cycle Mnemonic Description Bytes Cycles
Accumulator Registers
ADD A, R Add register to A 1 1 INC R Increment register 1 1
ADDA,@R Add data memory to A 1 1 INC@R Increment data memory 1 1
ADD A, # data Add immediate to A 2 2 DECR Decrement register 1 1
ADDCA, R Add register with carry 1 1
Branch
ADDC A, Add data memory 1 1
@R with carry JMP addr Jump unconditional 2 2
ADDCA, Add immediate 2 2 JMPP@A Jump indirect 1 2
# data with carry DJNZ R, addr Decrement register 2 2
ANLA, R And register to A 1 1 and jump
ANLA,@R And data memory to A 1 1 JC addr Jump on carry = 1 2 2
ANL A, # data And immediate to A 2 2 JNC addr Jump on carry = 0 2 2
ORLA, R Or register to A 1 1 JZ addr Jump on A Zero 2 2
ORLA@R Or data memory to A 1 1 JNZ addr Jump on A not Zero 2 2
ORL A, # data Or immediate to A 2 2 JTO addr Jump on TO = 1 2 2
XRL A, R Exclusive Or register 1 1 JNTO addr Jump on TO = 0 2 2
to A JT1 addr Jump on T1 = 1 2 2
XRLA,@R Exclusive or data 1 1 JNT1 addr Jump on T1 = 0 2 2
memory to A JFO addr Jump on FO = 1 2 2
I
XRL, A, # data Exclusive or 2 2 JF1 addr Jump on F1 = 1 2 2
immediate to A
JTF"addr Jump on timer flag =1 2 2
INCA Increment A 1 1
JNI addr Jump on INT = 0 2 2
DECA Decrement A 1 1
JBb addr Jump on Accumulator 2 2
CLRA Clear A 1 1 Bit
CPLA Complement A 1 1
DAA Decimal adjust A 1 1 Subroutine
SWAP A Swap nibbles of A 1 1 CALL addr Jump to subroutine 2 2
RLA Rotate A left 1 1 RET Return 1 2
RLCA Rotate A left 1 1 RETR Return and restore 1 2
through carry status
RR A Rotate A right 1 1
Rotate A right 1 1 Flags
RRCA
through carry CLRC Clear Carry 1 1
CPLC Complement Carry 1 1
Input/Output
CLR FO Clear Flag 0 1 1
IN A, P Input port to A 1 2 CPL FO Complement Flag 0 1 1
OUTL P, A Output A to port 1 2 CLR F1 Clear Flag 1 1 1
ANL p, # data And immediate to port 2 2 CPL F1 Complement Flag 1 1 1
ORL P, # data Or immediate to port 2 2
'INS A, BUS Input BUS to A 1 2 Data Moves
'OUTL BUS, A Output A to BUS 1 2 MOV A. R Move register to A 1 1
'ANL BUS, And immediate to BUS 2 2 MOVA,@R Move data memory 1 1
# data to A
'ORL BUS, Or immediate to BUS 2 2 MOV A, # data Move immediate to A 2 2
# data MOV R, A Move A to register 1 1
MOVD A, P Input Expander port 1 2 MOV@R,A Move A to data 1 1
to A memory
MOVD P, A Output A to Expander 1 2 MOV R, # data Move immediate 2 2
port to register
ANLD P, A And A to Expander port 1 2 MOV@R, Move immediate to 2 2
ORLD P, A Or A to Expander port 1 2 # data data memory
MOV A. PSW Move PSWtoA 1 1
MOVPSW,A Move A to PSW 1 1
Mnemonics copyright Intel Corporation 1983"
'For use with internal memory only"
3-5
MCS®-4S INSTRUCTION SET
S04SAH/S74SH/S049AH/S050AH/8749H
Instruction Set Summary (Con't)
Mnemonic Description Bytes Cycle' Mnemonic Description Bytes Cycle
Data Moves Control
(Cont'd) EN I Enable external 1 1
XCH A, R Exchange A and 1 1 Interrupt
register DIS I Disable external 1 1
XCHA,@R Exchange A and 1 1 Interrupt
data memory SEL RBO Select register bank 0 1 1
XCHDA,@R Exchange nibble of A 1 1 SEL RB1 Select register bank 1 1 1
and register SEL MBO Select memory bank 0 1 1
MOVXA,@R Move external data 1 2 SEL MB1 Select memory bank 1 1 1
memory to A
ENTOCLK Enable clock output 1 1
MOVX@R,A Move A to external 1 2 on TO
data memory
MOVPA,@A Move to A from 1 2 NOP No Operation 1 1
current page
MOVP3A,@A Move to A from Page 3 1 2
Timer/Counter
MOVA, T Read Timer/Counter 1 1
MOVT,A Load Timer/Counter 1 1
STRTT Start Timer 1 1
STRTCNT Start Counter 1 1
STOP TCNT Stop Timer/Counter 1 1
EN TCNTI Enable Timer/Counter 1 1
Interrupt
DIS TCNTI Disable Timer/Counter 1 1
Interrupt
Mnemonics copyright Intel Corporation 1983,
3-6
MCS®-48 INSTRUCTION SET
Symbols and Abbreviations Used
A Accumulator
AC Auxiliary Carry
addr 12-Bit Program Memory Address
Bb Bit Desig nator (b = 0-7)
BS Bank Switch
BUS BUS Port
C Carry
ClK Clock
CNT Event Counter
CRR Conversion Result Register
D Mnemonic for 4-Bit Digit (Nibble)
data 8-Bit Number or Expression
DBF Memory Bank Flip-Flop
FO, F1 Flag 0, Flag 1
I Interrupt
P Mnemonic for "in-page!' Operation
PC Program Counter
Pp . Port Designator (p = 1, 2 or 4-7)
PSW Program Status Word
Ri Data memory Pointer (i = 0, or 1)
Rr Register Designator (r = 0-7)
SP Stack Pointer
T Timer
TF Timer Flag
TO, T1 Test 0, Test 1
X Mnemonic for External RAM
# Immediate Data Prefix
@ Indirect Address Prefix
$ Current Value of Program Counter
(X) Contents of X
((X) ) Contents of location Addressed by X
Is Replaced by
Mnemonics copyright Intel Corporation 1983.
3-7
· MCS®-48 INSTRUCTION SET
ADD A,R r Add Register Contents to Accumulator
Encoding: I0 1 1 0 I1 r r rI 68H-6FH
Description: The contents of register 'r' are added to the accumulator. Carry is
affected.
Operation: (A) - (A) + (Rr) r = 0-7
Example: ADDREG: ADD A,R6 ;ADD REG 6 CONTENTS
;TO ACC
ADD A,@R 1 Add Data Memory Contents to Accumulator
Encoding; I0 1 1 0 I0 0 0 i ] 60H-61H
Description: The contents of the resident data memory location addressed by register 'i' bits
0-5** are added to the accumulator. Carry is affected.
Operation: (A) - (A) + ((Ri)) i =0-1
Example: ADDM: MOV RO, #01 FH ;MOVE '1 F' HEX TO REG 0
ADD A, @RO ;ADD VALUE OF LOCATION
;31 TO ACC
ADD A,#data Add Immediate Data to Accumulator
Encoding: I0 0 0 0 I 0 0 1 1 I 1 d7 d6 d5 d4 1d3 d2 d1 dO 1 03H
Description: This is a 2-cycle instruction. The specified data is added to the accumulator.
Carry is affected.
Operation: (A) - (A) + data
Example: ADDID: ADD A,#ADDER: ;ADD VALUE OF SYMBOL
;ADDER' TO ACC
ADDC A,R r Add Carry and Register Contents to Accumulator
Encoding: I0 1 1 1 11 r r r I 78H-7FH
Description: The content of the carry bit is added to. accumulator location a and the carry
bit cleared. The contents of register 'r' are then added to the accumulator.
Carry is affected.
Operation: (A) - (A) + (Rr) + (C) r = 0-7
Example: ADDRGC: ADDC A,R4 ;ADD CARRY AND REG 4
;CONTENTS TO ACC
•• 0-5 in 8048AH/8748H
0-6 in 8049AH/8749H
0-7 in 8050AH
3-8
MCS®-48 INSTRUCTION SET
ADDC A,@R i Add Carry and Data Memory Contents to Accumulator
Encoding: I0 1 1 1 I 0 0 0 i I 70H-71H
Description: The content of the carry bit is added to accumulator location 0 and the carry bit
cleared. Then the contents of the resident data memory location addressed by
register 'i' bits 0-5** are added to the accumulator. Carry is affected.
Operation: (A) - (A) + ((R i)) + (C) i= 0-1
Example: ADDMC: MOV R1 ,#40 ;MOVE '40' DEC TO REG 1
ADDC A,@R1 ;ADD 'CARRY AND LOCATION 40
;CONTENTS TO ACC
ADDC A,@data Add Carry and Immediate Data to Accumulator
Encoding: 10 0 0 1 I0 0 1 1 1 Id 7 d6 d 5 d4 Id3 d2 d1 dO I 13H
Description: This is a 2-cycle instruction. The content of the carry bit is added to
accumulator location 0 and the carry bit cleared. Then the specified data is
added to the accumulator. Carry is affected.
Operation: (A) - (A) + data + (C)
Example: ADDC A,#225 ;ADD CARRY AND '225' DEC
;TO ACC
ANL A,R r logical AND Accumulator with Register- Mask
Encoding: 10 1 0 1 11 r r r I 58H-5FH
Description: Data in the accumulator is logically ANDed with the mask contained in
working register 'r'.
Operation: (A) - (A) AND (Rr) r =0-7
Example: ANDREG: ANL A,R3 ;'AND' ACC CONTENTS WITH MASK
;IN REG 3
ANL A,@Ri Logical AND Accumulator with memory Mask
Encoding: I0 1 0 1 I0 0 0 i I 50H-51H
Description: Data in the accumulator is logically ANDed with the mask contained in the
data memory location referenced by register 'i' bits 0-5".
Operation: (A) - (A) AND ((Ri)) i = 0-1
Example: ANDDM: MOV RO,#03FH ;MOVE '3F' HEX TO REG 0
ANL A, @RO ;'AND' ACC CONTENTS WITH
;MASK IN LOCATION 63
•• 0-5 in 8048AH/8748H
0-6 in 8049AH/8749H
0-7 in 8050AH
3-9
MCS®-48 INSTRUCTION SET
ANL A,#data Logical AND Accumulator with Immediate Mask
Encoding: lo 1 0 1 1 0 0 1 1 1 53H
Description: This is a 2-cycle instruction. Data in the accumulator is logically ANDed
with an immediately-specified mask.
Operation: (A) - (A) AND data
Examples: ANDID: ANL A,#OAFH,. ;'AND' ACC CONTENTS
;WITH MASK 10101111
ANL A,#3 + X/Y ;'AND' ACC CONTENTS
;WITH VALUE OF EXP
;'3 + XY/Y'
ANL BUS,#data* Logical AND BUS with Immediate Mask
Encoding: 11 0 0 1 11 0 0 0 1 98H
Description: This is a 2-cycle instruction. Data on the BUS port is logically ANDed
with an immediately-specified mask. This instruction assumes prior
specification of an 'OUTL BUS, A' instruction.
Operation: (BUS) - (BUS) AND data
Example: ANDBUS: ANL BUS,#MASK ;'AND' BUS CONTENTS
;WITH MASK EQUAL VALUE
;OF SYMBOL 'MASK'
ANL Pp,#data Logical AND Port 1-2 with Immediate Mask
Encoding: 11 0 0 1 11 0 P P I 99H-9AH
Description: This is a 2-cycle instruction. Data on port 'p' is logically ANDed with an
immediately-specified mask.
Operation: (Pp) - (Pp) AND DATA p = 1-2
Example: ANDP2: ANL P2,#OFOH ;'AND' PORT 2 CONTENTS
;WITH MASK 'FO' HEX
;(CLEAR P20-23)
• For use with internal program memory ONLY.
3·10
MCS®-48 INSTRUCTION SET
ANLD Pp,A Logical AND Port 4-7 with Accumulator Mask
Encoding: 11 0 0 1 J1 1 P P J 9CH-9FH
Description: This is a 2-cycle instruction. Data on port 'p' is logically ANDed with the
digit mask contained in accumulator bits 0-3.
Operation: (Pp) - (Pp) AND (AO-3) P = 4-7
Note: The mapping of port 'p' to opcode bits 0-1 is as follows:
1 0 Port
00 4
01 5
10 6
11 7
Example: ANDP4: ANLD P4,A ;'AND' PORT 4 CONTENTS
;WITH ACC BITS 0-3
CALL address Subroutine Call
Encoding: Ia10 a9 as 1 I0 1 0 0 I Ia7 a6 a5 a4 Ia3 a2 a1 aO I
Page Hex Op Code
o 14
1 34
2 54
3 74
4 94
5 B4
6 D4
7 F4
Description: This is a 2-cycle instruction. The program counter and PSW bits 4-7 are
saved.in the stack. The stack pointer (PSW bits 0-2) is updated. Program
control is then passed to the location specified by 'address'. PC bit 11 is
determined by the most recent SEL MB instruction.
A CALL cannot begin in locations 2046-2047 or 4094-4095. Execution
continues at the instruction following the CALL upon return from the
su brouti ne.
Operation: ((SP)) - (PC), (PSW4-7)
(SP) - (SP) + 1
(PC S- 10 ) - (add rS_10)
( PC O-7) - ( addr O_7)
(PC 11 ) - DBF
3-11
MCS®-48 INSTRUCTION SET
Example: Add three groups of two numbers. Put subtotals in locations 50,51 and
total in location 52.
MOV RO,#50 ;MOVE '50' DEC TO ADDRESS
;REG 0
BEGADD: MOV A,R1 ;MOVE CONTENTS OF REG 1
;TO ACC
ADD A,R2 ;ADD REG 2 TO ACC
CALL SUBTOT ;CALL SUBROUTINE 'SUBTOT'
AD DC A R3 ;ADD REG 3 TO ACC
ADDC A,R4 ;ADD REG 4 TO ACC
CALL SUBTOT ;CALL SUBROUTINE 'SUBTOT'
AD DC A,R5 ;ADD REG 5 TO ACC
AD DC A,R6 ;ADD REG 6 TO ACC
CALL SUBTOT ;CALL SUBROUTINE 'SUBTOT'
SUBTOT: MOV @RO,A ;MOVE CONTENTS OF ACC TO
;LOCATION ADDRESSED BY
;REGO
INC RO ;INCREMENT REG 0
RET ;RETURN TO MAIN PROGRAM
CLR A Clear Accumulator
Encoding: 10 0 1 0 1 0 1 11 27H
Description: The contents of the accumulator are cleared to zero.
Operation: A - 0
CLR C Clear Carry Bit
Encoding: 11 0 0 1 1 0 1 11 97H
Description: During normal program execution, the carry bit can be set to one by the
ADD, ADDC, RLC, CPL C, RRC, andDAA insructions. This instruction
resets the carry bit to zero.
Operation: C - 0
CLR F1 Clear Flag 1
Encoding: 11 0 1 0 1 0 1 0 1 1 ASH
Description: Flag 1 is cleared to zero.
Operation: (F1) - 0
3-12
MCS®-48 INSTRUCTION SET
CLR FO Clear Flag 0
Encoding: 11 0 0 0 1 0 1 0 1 I 85H
Description: Flag 0 is cleared to zero.
Operation: (FO) - 0
CPL A Complement Accumulator
Encoding: 10 0 1 1 10 1 1 1 I 37H
Description: The contents of the accumulator are co~plemented. This is strictly a one's
complement. Each one is changed to zero and vice-versa.
Operation: (A) - NOT (A)
Example: Assume accumulator contains 01101010.
CPLA: CPL A ;ACC CONTENTS ARE COMPLE-
;MENTED TO 10010101
CPL C Complement Carry Bit
Encoding: 11 0 1 0 1 0 1 1 1 1 A7H
Description: The setting of the carry bit is complemented; one is changed to zero, and
zero is changed to one.
Operation: (C) - NOT (C)
Example: Set C to one; current setting is unknown.
CT01: CLR C ;C IS CLEARED TO ZERO
CPL C ;C IS SET TO ONE
CPL FO Complement Flag 0
Encoding: 11 0 0 1 1 0 1 0 11 95H
Description: The setting of flag 0 is complemented; one is changed to zero, and zero is
changed to one.
Operation: FO - NOT (FO)
CPL F1 Complement Flag 1
Encoding: 11 0 1 1 10 1 0 11 85H
Description: The setting of flag 1 is complemented; one is changed to zero, and zero is
changed to one.
Operation: (F1) - NOT (F1)
3-13·
MCS®-48 INSTRUCTION SET
DA A Decimal Adjust Accumulator
Encoding: I0 1 01 10 1 111 57H
Description: The 8-bit accumulator value is adjusted to form two 4-bit Binary Coded
Decimal (BCD) digits following the binary addition of BCD numbers.
The carry bit C is affected. If the contents of bits 0-3 are greater than nine,
or if AC is one, the accumulator is incremented by six.
The four high-order bits are then checked. If bits 4-7 exceed nine, or if
C is one, these bits are increased by six. If an overflow occurs, C is set
to one.
Example: Assume accumulator contains 10011011.
DA A ;ACC Adjusted to 00000001
;WITH C SET
C AC 7 4 3 0
o 0 100 1 1 011
00000110 ADD SIX TO BITS 0-7
o 10100001
o1 1 0 ADD SIX TO BITS 4-7
o 000 0 0 0 0 1 OVERFLOW TO C
DEC A Decrement Accumulator
Encoding: 10 0 0 0 10 1 1 1 1 07H
Description: The contents of the accumulator are decremented by one. The carry flag
is not affected.
Operation: (A) - (A) -1
Example: Decrement contents of external data memory location 63.
MOV RO,#3FH ;MOVE '3F' HEX TO REG 0
MOVX A, @RO ;MOVE CONTENTS OF
;LOCATION 63 TO ACC
DECA . ;DECREMENT ACC
MOVX@RO,A ;MOVE CONTENTS OF ACC TO
;LOCATION 63 IN EXPANDED
;MEMORY
DEC Rr Decrement Register
Encoding: 11 1 0 0 11 r r r I C8H-CFH
Description: The contents of working register 'r' are decremented by one.
Operation: (Rr) - (Rr) -1 r = 0-7
Example: DECR1: DEC R1 ;DECREMENT CONTENTS OF REG 1
3-14
MCS®-48 INSTRUCTION SET
DIS I External Interrupt
Encoding: I 0 0 0 1 I0 1 0 1 I 15H
Description: . External interrupts are disabled. A low signal on the interrupt input pin has
no effect.
DIS TCNTI Disable Timer/Counter Interrupt
Encoding: 10 0 1 1 1 0 1 0 1 1 35H
Description: Timer/counter interrupts are disabled. Any pending timer interrupt request
is cleared. The interrupt sequence is not initiated by an overflow, but the
timer flag is set and time accumulation continues.
DJNZ Rr • address Decrement Register and Test
Encoding: 11 1 1 0 11 r r r 1 1 a7 a6 a5 a4 1a3 a2 a1 aO I E8H-EFH
Description: This is a 2-cycle instruction. Register 'r' is decremented, then tested for
zero. If the register contains all zeros, program control falls through to the
next instruction. If the register contents are not zero, control jumps to the
specified 'address'.
The address in this case must evaluate to 8-bits, that is, the jump must be
to a location within the current 256-location page.
Example: (Rr) - (Rr) -1 r = 0-7
If Rr not 0
(PCO-7) - addr
Note: A 12-bit address specification does not cause an error if the
DJNZ instruction and the jump target are on the same page. If the DJNZ
instruction begins in location 255 of a page, it must jump to a target
address on the following page.
Example: Increment values in data memory locations 50-54.
MOV RO,#50 ;MOVE '50' DEC TO ADDRESS
;REG 0
MOV R3,#5 ;MOVE '5' DEC TO COUNTER
;REG3
INCRT: INC @RO . ;INCREMENT CONTENTS OF
;LOCATION ADDRESSED BY
;REGO
INC RO ;INCREMENT ADDRESS IN REG 0
DJNZ R3, INCRT ;DECREMENT REG 3 - JUMP TO
;'INCRT' IF REG 3 NONZERO
NEXT - ;'NEXT' ROUTINE EXECUTED
;IF R3 IS ZERO
3-15
MCS®-48 INSTRUCTION SET
EN I Enable External Interrupt
Encoding: 10 0 0 0 I0 1 0 1 I 05H
Description: External interrupts are enabled. A low signal on the interrupt input pin
initiates the interrupt sequence.
EN TCNTI Enable Timer/Counter Interrupt
Encoding: 10 0 1 0 I0 1 0 1 I 25H
Description: Timer/counter interrupts are enabled. An overflow of the timer/counter
initiates the interrupt sequence.
ENTO ClK Enable Clock Output
Encoding: 10 1 1 1 I0 1 0 1 I 75H
Description: The test 0 pin is enabled to act as the clock output. This function is
disabled by a system reset.
Example: EMTSTO: ENTO ClK ;ENABlE TO AS CLOCK OUTPUT
IN A,Pp Input Port or Data to Accumulator
Encoding: 10 0 0 0 11 0 P pi 09H-OAH
Description: This is a 2-cycle instruction. Data present on port 'p' is
transferred (read) to the accumulator.
Operation: (A) - (Pp) p = 1-2
INP12: IN A,P1 ;INPUT PORT 1 CONTENTS TO ACC
MOV R6,A ;MOVEACC CONTENTS TO REG 6
INA,P2 ;INPUTPORT 2 CONTENTS TO ACC
MOV R7,A ;MOVE ACC CONTENTS TO REG 7
INC A Increment Accumulator
Encoding: 10 0 0 1 1 0 1 1 11 17H
Description: The contents of the accumulator are incremented by one. Carry is not
affected.
Operation. (A) - (A) +1
3-16
MCS®-48 INSTRUCTION SET
, Example: Increment contents of location 100 in external data memory.
INCA: MOV RO,#100 ;MOVE '100' DEC TO ADDRESS REG 0
MOVX A,@RO ;MOVE CONTENTS OF LOCATION
;tOOTO ACC
INC A ;INCREMENT A
MOVX @RO,A ;MOVE ACC CONTENTS TO
;LOCATION 101
INC Rr Increment Register
Encoding: 10 0 0 1 11 r r r 1 18H-1 FH
Description: The contents of working register 'r' are incremented by one.
Operation: (Rr) - (Rr) + 1 r = 0-7
Example: INCRO: INC RO ;INCREMENT CONTENTS OF REG 0
INC @R 1 Increment Data Memory Location
Encoding: 10 0 0 1 1 0 0 0 i 1 10H-11H
Description: The contents of the resident data memory location addressed by register 'i' bits
0-5** are incremented by one.
Operation: ((Ri)) - ((Ri)) + 1 i = 0-1
Example: INCDM: MOV R1 ,#03FH ;MOVE ONES TO REG 1
INC @R1 ;INCREMENT LOCATION 63
INS A,BUS· Strobed Input of BUS Data to Accumulator
Encoding: 10 0 0 0 I1 0 0 0 I 08H
Description: This is a 2-cycle instruction. Data present on the BUS port is transferred
(read) to the accumulator when the RD pulse is dropped. (Refer to section
on programming memory expansion for details.)
Operation: (A) - (BUS)
Example: INPBUS: )NS A,BUS ;INPUT BUS CONTENTS TO ACC
* For use with internal program memory ONLY.
** 0-5 in 8048AH/8748H
0-6 in 8049AH/8749H
0-7 in 8050AH
3-17
MCS®-48 INSTRUCTION SET
JBb address Jump If Accumul,ator Bit Is Set
Accumulator Bit Hex Op Code
o 12
1 32
2· 52
3 72
4 92
,5 B2
6 D2
7 F2
Description: This is a 2.-cycle instruction. Control passes to the specified address if
accumulator bit 'b' is setto one.
Operation: b = 0-7
(PCO-7) - addr If Bb = 1
(PC) = (PC) + 2 If Bb =0
Example: JB4IS1: JB4 NEXT ;JUMP TO 'NEXT' ROUTINE
;IF ACC BIT 4 = 1
JC address Jump If Carry Is Set
Encoding: 11 1 11 1 0 1 1 0 I 1a7 a6 a5 a4 Ia3 a2 a1 aO I F6H
Description: This is a 2-cycle instruction. Control passes to the specified address if the
carry bit is set to one,
Operation: (PCO-7) - addr If C = 1
(PC) = (PC) + 2 IfC=O
Example: JC1: JC OVFLOW ;JUMP TO 'OVFLOW' ROUTINE
;IF C = 1
JFO address Jump If Flag 0 Is Set
Encoding: 11 0 1 1 I 0 1 1 0 I Ia7 a6 a5 a4 Ia3 a2 a1 aO 1 B6H
Description: This is a 2-cycle instruction. Control passes to the specified address if
flag 0 is set to one. '
Operation: (PCO-7) - addr If FO = 1
(PC) =(PC) + 2 If FO = 0
Example: JFOIS1: JFO TOTAL ;JUMP TO 'TOTAL' ROUTINE IF FO = 1
3-18
MCS®-4B INSTRUCTION SET
Encoding: 10 1 1 1 I0 1 1 0 I 76H
Description: This is a 2-cycle instruction. Control passes to the specified address if
flag 1 is set to one.
Operation: (PCO-7) - addr If F1 = 1
(PC) =(PC + 2) If F1 = 0
Example: JF1IS1: JF1 FILBUF ;JUMP TO 'FILBUF'
;ROUTINE IF F1 = 1
JMP address Direct Jump within 2K Block
Encoding: Ia10 ag a8 01 0 1 0 01
Page Hex Op Code
0 04
1 24
2 44
3 64
4 84
5 A4
6 C4
7 E4
Description: This is a 2-cycle instruction. Bits 0-10 of the program counter are replaced
with the directly-specified address. The setting of PC bit 11 is
determined by the most recent SELECT MB instruction.
Operation:· (PC 8- 10) - addr 8-10
(PC O- 7 ) - addr 0-7
(PC11) - DBF
Example: JMP SUBTOT ;JUMP TO SUBROUTINE 'SUBTOT
JMP $-6 ;JUMP TO INSTRUCTION SIX
;LOCATIONS BEFORE CURRENT
;LOCATION
JMP 2FH ;JUMP TO ADDRESS '2F' HEX
JMPP @A Indirect Jump within Page
Encoding: 11 0 1 1 I0 0 1 1 I B3H
Description: This is a 2-cycle insruction. The contents of the program memory location
pointed to by the accumulator are substituted for the 'page' portion of the
program counter (PC bits 0-7).
3-19
MCS®-48 INSTRUCTION SET
Operation: (PCO- 7) - ((A)).
Example: Assume accumulator contains OFH.
JMPPAG: JMPP @A ;JUMP TO ADDRESS STORED IN
;LOCATION 151N CURRENT PAGE
JNC address Jump If Carry Is Not Set
Encoding: 11 1 1 0 1 0 1 1 0 1 'I a7 a6 a5 a41 a3 a2 a1 aO 1 E6H
Description: This is a 2-cycle instruction. Control passes to the specified address if
the carry bit is not set, that is, equals zero. I
Operation: (PCO-7) - addr If C = 0
(PC) = (PC) + 2 If C = 1
Example: JCO: JNC NOV FLO ;JUMP TO 'NOVFLO' ROUTINE
;IF C = 0
JNI address Jump If Interrupt Input Is Low
Encoding: 11 0 0 0 1 0 1 1 0 I' 1a7 a6 a5 a41 a3 a2 a1 aO 1 86H
Description: This is a 2-cycle instruction. Control passes to the specified address if the
interrupt input signal is low (= 0), th,at is, an external interrupt has been
signaled. (This signal initiates an interrupt service sequence if the external
interrupt is enabled.)
Operation: (PCO-7) - addr If I = 0
(PC) = (PC) + 2 1f1=1
Example: LOC 3: JNI EXTINT ;JUMP TO 'EXTINT' ROUTINE
;IF I = 0
JNTO address Jump If Test 0 is Low
Encoding: 1 0 01 0 1 0 1 1 0 1 1a7 a6 a5 a41 a3 a2 a1 aO 1 26H
Description: This is a 2-cycle instruction. Control passes to the specified address, if the
test 0 signal is low. .
Operation: (PCO-7) - addr IfTO = 0
(PC) = (PC) + 2 If TO = 1
Example: JTOLOW: JNTO 60 ;JUMP TO LOCATION 60 DEC
;IF TO = 0
3·20
MCS®-48 INSTRUCTION SET
JNT1 address Jump If Test 1 Is Low
Encoding: 10 1 0 0 10 1 1 0 1 Ia7 as a5 a4 Ia3 a2 81 aO I 4SH
Description: This is a 2-cycle instruction. Control passes to the specified address, if
the test 1 signal is low.
Operation: (PC O- 7) - addr IfT1 = 0
(PC) = (PC) + 2 IfT1 = 1
JNZ Address Jump If Accumulator Is Not Zero
Encoding: 11 00 1 1 0 1 1 0 1 1a7 as a5 a4 1a3. a-2 a1 aO I 9SH
Description: This is a 2-cycle instruction. Control passes to the specified address if the
accumulator contents are nonzero,at the time this instruction is executed.
Operation: (PC O':'7) - addr If A~ 0
(PC) = (PC) + 2 If A = 0
Example: JACCNO: JNZ OABH ;JUMP TO LOCATION 'AB' HEX
;IF ACC VALUE IS NONZERO
JTF address Jump If Timer Flag Is Set
Encoding: I0 0 0 1 I0 1 1 0 I 1a7 as a5 a4 1a3 a2 a1 aO I 1SH
Description: This "is a 2-cycle instruction. Control passes to the specified address ifthe
timer flag is set to one, that is, the timer/counter register has overflowed.
Testing the timer flag resets it to zero. (This overflow initiates an interrupt
service sequence if the timer-overflow interrupt is enabled.)
Operation: (PC O- 7) - addr . IfTF = 1
(PC) = (PC) + 2 IfTF = 0
Example: JTF1: JTF TIMER ;JUMP TO 'TIMER' ROUTINE
;IF TF = 1
JTO address Jump If Test 0 Is High
Encoding: 10 0 1 1 I 0 1 1 0I· Ia7 as a5 a41 a3 a2 a1 aO I 3SH
Description: This is a 2-cycle instruction. Control passes to the specified address if
the test 0 signal is high (= 1).
Operation: (PCO-7) - addr IfTO =1
(PC) = (PC) + 2 If TO =0
Example: JTOHI: JTO 53 ;JUMP TO LOCATION 53 DEC
;IF TO = 1
3·21
MCS®-48 INSTRUCTION SET
JT1 address Jump If Test 1 Is High
Encoding: 10·1 0 1 1 0 1 1 0 1 S6H
Description: This is a 2-cycle instruction. Control passes to the specified address if the
test 1 signal is high (= 1).
Operation: (PCO-7) - addr If T1 =1
(PC) = (PC) + 2 IfT1 =0
Example: JT1HI: JT1 COUNT ;JUMP TO 'COUNT' ROUTINE
;IF T1 = 1
JZ address Jump If Accumulator Is Zero
Encoding: 11 1 0 0 1 0 1 1 0 1 1a7 a6 as a4 1a3 a2 a1 aO 1 C6H
Description: This is a 2-cycle instruction. Control passes to the specified address if
the accumulator contains all zeros at the time this instruction is executed.
Operation: (PC O- 7) - addr If A =0
(PC) = (PC) + 2 If A,= 1
Example: JACCO: JZ OA3H ;JUMP TO LOCATION 'A3' HEX
;IF ACC VALUE IS ZERO
MOV A,#data Move Immediate Data to Accumulator
Encoding: I0 0 1 0 10 0 1 1 1 23H
Description: This is a 2-cycle instruction. The 8-bit value specified by 'data' is loaded
in the accumulator.
Operation: (A) - data
Example: MOV A,#OA3H ;MOVE 'A3' HEX TO ACC
MOV A,PSW Move PSW Contents to Accumulator
Encoding: 11 1 0 0 1 0 1 11 1 C7H
Description: The contents of the program status word are moved to the accumulator.
Operation: (A) - (PSW)
Example: Jump to 'RB1 SET' routine if PSW bank switch, bit 4, is set.
BSCHK: MOV A,PSW ;MOVE PSW CONTENTS TO ACC
JB4 RB1SET ;JUMP TO 'RB1SET' IF ACC BIT 4 = 1
3-22
MCS®-48 INSTRUCTION SET
MOV A,R r Move Register Contents to Accumulator
Encoding: 11 1 1 1 11 r r r 1 F8H-FFH
Description: 8-bits of data are removed from working register 'r' into the accumulator.
Operation: (A) - (Rr) r =0-7
Example: MAR: MOV A,R3 ;MOVE CONTENTS OF REG 3 TO ACC
MOV A,@R i Move Data Memory Contents to Accumulator
Encoding 11 1 1 1 10 0 0 i 1 FOH-F1H
Description: The contents of the resident data memory location addressed by bits 0-5** of
register 'i' are moved to the accumulator. Register 'i' contents are unaffected.
Operation: (A) - «Ri)) i = 0-1
Example: Assume R1 contains 00110110.
MADM: MOV A,@R1 ;MOVE CONTENTS OF DATA MEM
;LOCATION 54 TO ACC
MOV A,T Move Timer/Counter Contents to Accumulator
Encoding: 10 1 0 0 1 0 0 1 0 1 42H
Description: The contents of the timer/event-counter register are moved to the
accumulator.
Operation: (A) - (T)
Example: Jump to "EXIT" routine when timer reaches '64', that is, when bit 6 set-
assuming initialization 64,
TIMCHK: MOV A,T ;MOVE TIMER CONTENTS TO ACC
JB6 EXIT ;JUMP TO 'EXIT IF ACC BIT 6 = 1
MOV PSW,A Move Accumulator Contents to PSW
Encoding: /1 1 0 1 / 0 1 1 1 I D7H
Description: The contents of the accumulator are moved into the progam status word.
All condition bits and the stack pointer are affected by this move.
Operation: (PSW) - (A)
Example: Move up stack pointer by two memory locations, that is, increment the
pOinter by one.
IN,CPTR: MOV A,PSW ;MOVE PSW CONTENTS TO ACC
INC A ;INCREMENT ACC BY ONE
MOV PSW,A ;MOVE ACC CONTENTS TO PSW
.•• 0-5 in 8048AH/8748H
0-6 in 8049AH/8749H
0-7 in 8050AH
3-23
MCS®-48 INSTRUCTION SET
MOV Rr,A Move Accumulator Contents to Register
Encoding: 11 0 1 0 11 r r r 1 A8H-AFH
Description: The contents of the accumulator are moved to register 'r'.
Operation: (Rr) +- (A) r = 0-7
Example: MRA: MOV RO,A ;MOVE CONTENTS OF ACC TO REG 0
MOV Rr,#data Move Immediate Data to Register
Encoding: 11 0 1 J 11 r2 r1 rO 1 B8H-BFH
Description: This is a 2-cycle instruction. The 8-bit value specified by 'data' is moved to
register'r'.
Operation: (Rr) +- data r = 0-7
Examples: MIR4: MOV R4,#HEXTEN ;THE VALUE OF THE SYMBOL
;'HEXTEN' IS MOVED INTO REG 4
MIR S: MOV RS,#PI*(R*R) ;THE VALUE OF THE EXPRESSION
;'PI*(R*R)' IS MOVED INTO REG S
MIR 6: MOV R6, #OADH ;'AD' HEX IS MOVED INTO REG 6
MOV @ Ri,A Move Accumulator Contents to Data Memory
Encoding: \1 0 1 0 \ 0 0 0 i 1 AOH-A1H
Description: The contents of the accumulator are moved to the resident data memory
location whose address is specified by bits O-S** of register 'i'. Register 'i'
contents are unaffected.
Operation: ((Ri)) +- (A) i= 0-1
Example: Assume RO contains 00000111.
MDMA: MOV @RO,A ;MOVE CONTENTS OF ACC TO
;LOCATION 7 (REG 7)
MOV @ Ri,#data Move Immediate Data to Data memory
BOH-B1H
Description: This is a 2-cycle instruction. The 8-bit value specified by 'data' is moved
to the resident data memory location addressed by register 'i', bits O-S".
Operation: ((Ri)) +- data i = 0-1
Examples: Move the hexadecimal value AC3F to locations 62-63.
MIDM: MOV RO,#62 ;MOVE '62' DEC TO ADDH REG 0
MOV @RO,#OACH ;MOVE 'AC' HEX TO LOCATION 62
INC RO ;INCREMENT REG 0 to '63'
MOV @RO,#3FH ;MOVE '3F' HEX to LOCATION 63
•• 0-5 in B04BAH/B74BH
0-6 in B049AH/B749H
0-7 in B050AH
3-24
MCS®-48 INSTRUCTION SET
MOV T,A Move Accumulator Contents to Timer/Counter
Encoding: I0 1 1 0 I 0 0 1 0 I 62H
Description: The contents of the accumulator are moved to the timer/event-counter
register.
Operation: (T) 4- (A)
Example: Initialize and start event counter.
INITEC: CLR A ;CLEAR ACC TO ZEROS
MOVT,A ;MOVE ZEROS TO EVENT COUNTER
START CNT ;START COUNTER
MOVD A,Pp Move Port 4-7 Data to Accumulator
Encoding: 10 0 0 0 11 1 P P 1 OCH-OFH
Description: This is a 2-cycle instruction. Data on 8243 port 'p' is moved (read) to
accumulator bits 0-3. Accumulator bits 4-7 are zeroed.
Operation: (0-3) 4- (Pp) p = 4-7
(4-7) 4- 0
Note: Bits 0-7 of the opcode are used to represent ports 4-7. If you are
coding in binary rather than assembly language, the mapping is as
follows:
Bits 1 0 Port
00 4
01 5
10 6
11 7
Example: INPPT5: MOVD A,P5 ;MOVE PORT 5 DATA TO ACC
;BITS 0-3, ZERO ACC BITS 4-7
MOVD Pp,A Move Accumulator Data to Port 4-7
Encoding: / 0 0 1 1 /1 1 P P, 3CH-3FH
Description: This is a 2-cycle instruction. Data in accumulator bits 0-3 is moved
(written) to 8243 port 'p'. Accumulator bits 4-7 are unaffected. (See NOTE
above regarding port mapping.)
Operation: (Pp) 4- (AO-3) P = 4-7
Example: Move data in accumulator to ports 4 and 5.
OUTP45: MOVD P4,A ;MOVE ACC BITS 0-3 TO PORT 4
SWAP A ;EXCHANGE ACC BITS 0-3 and 4-7
MOVD P5,A ;MOVE ACC BITS 0-3 TO PORT 5
3-25
MCS®-48 INSTRUCTION SET
MOVP A,@A Move Current Page Data to Accumulator
Encoding: /1 0 1 0 / 0 0 1 1 / A3H
Description: The contents of the program memory location addressed by the
accumulator are moved to the accumulator. Only bits 0-7 of the program
counter are affected, limiting the program memory reference to the
current page. The program counter is restored following this operation.
Operation: (PCO-7) - (A)
(A) - ((PC))
Note: This is a 1-byte, 2-cycle instruction. If it appears in location 255 of a
program memory page, @A addresses a location in the following page.
Example: MOV128: MOV A,#128 ;MOVE '128' DEC TO ACC
MOVP A,@A ;CONTENTS OF 129th LOCATION IN
;CURRENT PAGE ARE MOVED TO ACC
MOVP3 A,@A Move Page 3 Data to Accumulator
Encoding: /1 1 1 0 / 0 0 1 1 / E3H
Description: This is a 2-cycle instruction. The contents of the program memory location
(within page 3) addressed by the accumulator are moved to the
accumulator. The program counter is restored following this operation.
Operation: (PCO-7) - (A)
(PC8-H) - 0011
(A) - ((PC))
Example: Look up ASCII equivalent of hexadecimal code in table contained at the
beginning of page 3. Note that ASCII characters are designated by a
7-bit code; the eighth bit is always reset.
TABSCH: MOV A,#OB8H ;MOVE 'B8' HEX TO ACC (10111000)
ANL A,#7FH ;LOGICAL AND ACC TO MASK BIT
;7 (00111000)
MOVP3 A,@A ;MOVE CONTENTS OF LOCATION '38'
;HEX IN PAGE 3 TO ACC (ASCII '8')
Access contents of location in page 3 labelled TAB1.
Assume current program location is not in page 3.
TABSCH: MOV A,#LOW TAB 1 ;ISOLATE BITS 0-7 OF LABEL
;ADDRESS VALUE
MOVP3 A,@A ;MOVE CONTENTS OF PAGE 3
;LOCATION LABELED 'TAB 1, TO ACC
3-26
MCS®-48 INSTRUCTION SET
MOVX A,@R j Move External-Data-Memory Contents to Accumulator
Encoding: 11 0 0 0 1 0 0 0 i J 80H-81 H
Description: This is a 2-cycle instruction. The contents of the external data memory
location addressed by register 'i' are moved to the accumulator. Register 'i'
contents are unaffected. A read pulse is generated.
Operation: (A) - ((Ri)) i = 0-1
Example: Assume R1 contains 01110110.
MAXDM: MOVX A,@R1 ;MOVE CONTENTS OF LOCATION
;118 TO ACC
MOVX @Rj,A Move Accumulator Contents to External Data Memory
Encoding: 11 0 0 1 1 0 0 0 i 1 90H-91 H
Description: This is a 2-cycle instruction. The contents of the accumulator are moved to
the external data memory location addressed by register 'i'. Register 'i'
contents are unaffected. A write pulse is generated.
Operation: ((Ri)) - A i = 0-1
Example: Assume RO contains 11000111.
MXDMA: MOVX @RO,A ;MOVE CONTENTS OF ACC TO
;LOCATION 199 IN EXPANDED
;DATA MEMORY
NOP The NOP Instruction
Encoding: 10 0 0 0 1 0 0 0 0 1 OOH
Description: No operation is performed. Execution continues with the following
instruction.
ORL A,R r Logical OR Accumulator With Register Mask
Encoding: 10 1 0 0 11 r r r 1 48H-4FH
Description: Data in the accumulator is logically ORed with the mask contained in
working register 'r'.
Operation: (A) - (A) OR (Rr) r = 0-7
Example: ORREG: ORL A,R4 ;'OR' ACC CONTENTS WITH
;MASK IN REG 4
3-27
MCS®-48 INSTRUCTION SET
----------------
ORL A,@R i Logical OR Accumulator With Memory Mask
Encoding: 10 1 0 0 10 0 0 i \ 40H-41H
Description: Data in the accumulator is logically ORed with the mask contained in the
resident data memory location referenced by register "i", bits 0-5**.
Operation: (A) - (A) OR ((Ri)) i = 0-1
Example: ORDM: MOV RO,#3FH ;MOVE '3F' HEX TO REG 0
ORL A,@RO ;'OR' AC CONTENTS WITH MASK
;IN LOCATION 63
ORL A,#data Logical OR Accumulator With Immediate Mask
Encoding: I0 1 0 0 I0 0 1 1 I 43H
Description: This is a 2-cycle instruction. Data in the accumulator is logically ORed with
an im,mediately-specified mask.
,Operation: (A) - (A) OR data
Example: ORID: ORL A,#'X' ;'OR' ACC CONTENTS WITH MASK
;01011000 (ASCII VALUE OF 'X')
ORL BUS,#data* Logical OR BUS With Immediate Mask
Encoding: \1 0 0 0 11 0 0 0 I 88H
Description: This is a 2-cycle instruction. Data on the BUS port is logically ORed with an
immediately-specified mask. This instruction assumes prior specification
on an 'OUTL BUS,A' instruction.
Operation: (BUS) - (BUS) OR data
Example: ORBUS: ORL BUS,#HEXMSK :'OR' BUS CONTENTS WITH MASK
;EQUAL VALUE OF SYMBOL 'HEXMSK'
ORL Pp, #data Logical OR Port 1 or 2 With Immediate Mask
Encoding: 11 0 0 0 11 0 P pi 89H-8AH
Description: This is a 2-cycle instruction. Data on port 'p' is logically ORed with an
immediately-specified mask.
Operation: (Pp) - (P'p) OR data p = 1-2
Example: ORP1: ORL P1, #OFFH ;'OR' PORT 1 CONTENTS WITH MASK
;'FF' HEX (SET PORT 1 TO ALL ONES)
• For use with internal program memory ONLY.
.. 0-5 in 8048AH/8748H
0-6 in 8049AH/8749H
0-7 in 8050AH
3-28
MCS®-48 INSTRUCTION SET
ORlD Pp,A logical OR Port 4-7 With Accumulator Mask
Encoding: 11 0 0 0 11 1 P P I 8CH-8FH
Description: This is a 2-cycle instruction. Data on port 'p' is logically ORed with the
digit mask contained in accumulator bits 0-3.
Operation: (Pp) - (Pp) OR (AO-3) p = 4-7
Example: ORP7: ORlD P7,A ;'OR' PORT 7 CONTENTS WITH ACC
;BITS 0-3
OUTl BUS,A* Output Accumulator Data to BUS
Encoding: 10 0 0 0 1 0 0 1 0 1 02H
Description: This is a 2-cycle instruction. Data residing in the
accumulator is transferred (written) to the BUS port and
latched. The latched data remains valid until altered by
another OUTl instruction. Any other instruction requiring
use of the BUS port (except INS) destroys the contents of
the BUS latch. This includes expanded memory operations
(such as the MOVX instruction). logical operations on
BUS data (AND, OR) assume the OUTl BUS,A instruction
has been issued previously.
Operation: (BUS) - (A)
Example: OUTlBP: OUTl BUS, A ;OUTPUT ACC CONTENTS TO BUS
OUTl Pp,A Output Accumulator Data to Port 1 or 2
Encoding: I0 0 1 1 11 0 P pi 39H-3AH
Description: This is a 2-cycle instruction. Data residing in the accumulator is transferred
(written) to port 'p' and latched.
Operation: (Pp) - (A) p = h2
Example: OUTlP: MOV A,R7 ;MOVE REG 7 CONTENTS TO ACC
OUTl P2,A ;OUTPUT ACC CONTENTS TO PORT 2
MOV A, R6 ;MOV REG 6 CONTENTS TO ACC
OUTl P1,A ;OUTPUT ACC CONTENTS TO PORT 1
• For use with internal program memory ONLY.
3-29
MCS®-48 INSTRUCTION SET
RET Return Without PSW Restore
Encoding: 11 0 0 0 I0 0 1 1 I 83H
Description: This is a 2-cycle instruction. The stack painter (pSW bits 0-2) is
decremented. The program counter is then restored from the stack. PSW
bits 4-7 are not restored.
Operation: (SP) - {SP)-1
. (PC)- ({SP))
RETR Return with PSW Restore
Encoding: 11 0 0 1 I0 0 1 1 I 93H
Description: This is a 2-cycle instruction. The stack painter is decremented. The
program counter and bits 4-7 of the PSW are then restored from the stack.
Note that RETR should be used to return from an interrupt, but should
not be used within the interrupt service routine as it signals the end of an
interrupt routine by resetting the Interrupt in Progress flip-flop.
Operation: (SP) - (SP)-1
(PC) - ({SP))
(pSW 4-7) - ({SP))
3-30
MCS®-48 INSTRUCTION SET
RL A Rotate Left without Carry
Encoding: 11 1 1 0 1 0 1 1 1 1 E7H
Description: The contents of the accumulator are rotated left one bit. Bit 7 is rotated
into the bit 0 position.
Operation: (An + 1) - (An)
(AO) - (A7) n = 0-6
Example: Assume accumulator contains 10110001.
RLNC: RL A ;NEW ACC CONTENTS ARE 01100011
RLC A Rotate Left through Carry
Encoding: 11 1 1 1 1 0 1 1. 1 I F7H
Description: The contents of the accumulator are rotated left one bit. Bit 7 replaces the
carry bit; the carry bit is rotated· into the bit 0 position.
Operation: (An + 1) - (An)
n = 0-6
(AO)- (C)
(C) - (A7)
Example: Assume accumulator contains a 'signed' number; isolate sign without
changing value
RLTC: CLR C ;CLEAR CARRY TO ZERO
RLC A ;ROTATE ACC LEFT, SIGN
;BIT(7) IS PLACED IN CARRY
RR A ;ROTATE ACC RIGHT - VALUE
;(BITS 0-6) IS RESTORED,
;CARRY UNCHANGED, BIT 7
;IS ZERO
RR A Rotate Right without Carry
Encoding: 10 1 1 1 1 0 1 1 1 1 77H
Description: The contents of the accumulator are rotated right one bit. Bit 0 is rotated
into the bit 7 position.
Operation: (An) - (An + 1) n = 0-6
(A7) - (AO)
Example: Assume accumulator contains 10110001.
RRNC: RR A ;NEW ACCCONTENTS ARE 11011000
3-31
MCS®-48 INSTRUCTION SET
RRC A Rotate Right through Carry
Encoding: 10 1 1 0 10 1 1 1 1 67H
Description: _The contents of the accumulator are rotated right one bit Bit 0 replaces the
carry bit; the carry bit is rotated into the bit 7 position.
'Operation:' (An) - (An + 1) n = 0-6
(A7) -(C)
(C) - (Ao)
Example: Assume carry is not set and accumulator contains 10110001.
RRTC: RRC A ;CARRY IS SET AND ACC
;CONTAINS 01011000
SEL MBO Select Memory Bank 0
Encoding: /1 1 1 0 I 0 '1 0 1 I E5H
Description: PC bit 11 is set to zero on next JMP or CALL instruction. All references to
program memory addresses fall within the range 0-2047.
Operation: (DBF) -:- 0
Example: Assume program counter contains 834 Hex.
SEL MBO ;SELECT MEMORY BANK 0
JMP $+20 ;JUMP TO LOCATION 58 HEX
SEL MB1 Select Memory Bank,1
Encoding: 11 1 1 1 1 0 1 0 1 1 F5H .
Description: PC bit 11 is set to one on next JMP or CALL instruction. All references to
program memory addresses fall within the range 2048-'4095.
Operation: (DBF) - 1
3-32
MCS®-48 INSTRUCTION SET
S~L RBO Select Register Bank 0
Encoding: 11 1 0 0 1 0 1 0 1 1 C5H
Description: PSW bit 4 is set to zero. References to working registers 0-7 address data·
memory locations 0-7. This is the recommended setting for normal
program execution.
Operation: (BS) - 0
SEL RB1 Select Register Bank 1
Encoding: 11 1 0 1 I0 1 0 1 I D5H
Description: PSW bit 4 is set to one. References to working registers 0-7 address data
memory locations 24-31. This is the recommended setting for interrupt service
routines, since locations 0-7 are left intact. The setting of PSW bit 4 in
effect at the time of an' interrupt is restored by the RETR instruction when
the interrupt service routine is completed.
Operation: (BS) - 1
Example: Assume an external interrupt has occurred, control has passed to program
memory location 3, arid PSW bit 4 was zero before the interrupt.
Operation: LOC3: JNI INIT ;JUMP TO ROUTINE 'INIT' IF
;INTERRUPT INPUT IS ZERO
INIT: MOV R7,A ;MOVE ACC CONTENTS TO
;LOCATION 7
SEL RB1 ;SELECT REG BANK 1
MOV R7,#OFAH ;MOVE 'FA' HEX TO LOCATION 31
SEL RBO ;SELECT REG BANK 0
MOV A,R7 ;RESTORE ACC FROM LOCATION 7
RETR ;RETURN - RESTORE PC AND PSW
STOP TCNT Stop Timer/Event-Counter
Encoding: 10 1 1 0 I0 1 0 1 I 65H
Description: This instruction is used to stop both time accumulation and event counting.
3-33
MCS®-48 INSTRUCTION SET
Example: Disable interrupt, but jump to interrupt routine after eight overflows and
stop timer. Count overflows in register 7.
START: DIS TCNTI ;DISABLE TIMER INTERRUPT
CLR A ;CLEAR ACC TO ZEROS
MOVT,A ;MOVE ZEROS TO TIMER
MOV R7,A ;MOVE ZEROS TO REG 7
STRTT ;START TIMER
MAIN: JTF COUNT ;JUMP TO ROUTINE 'COUNT'
;IF TF = 1 AND CLEAR TIMER FLAG
JMP MAIN ;CLOSE LOOP
COUNT: INC R7 ;INCREMENT REG 7
MOV A,R7 ;MOVE REG 7 CONTENTS TO ACC
JB31NT ;JUMP TO ROUTINE 'INT' IF ACC
;BIT 3 IS SET (REG 7 =8)
JMP MAIN ;OTHERWISE RETURN TO ROUTINE
;MAIN
INT: STOP TCNT ;STOP TIMER
JMP 7H ;JUMP TO LOCATION 7 (TIMER)
;INTERRUPT ROUTINE
STRT CNT Start Event Conter
Encoding: 10 1 0 0 I0 1 0 1 I 45H
Description: The test 1 (T1) pin is enabled as the event-counter input and the counter
is started. The event-counter register is incremented with each high-to-Iow
transition on the T1 pin.
Example: Initialize and start event counter. Assume overflow is desired with first T1
input.
STARTC: EN TCNTI ;ENABLE COUNTER INTERRUPT
MOV A,#OFFH ;MOVE 'FF'HEX (ONES) TO ACC
MOV T,A ;MOVES ONES TO COUNTER
STRT CNT ;ENABLE T1 AS C9UNTER
;INPUT AND START
3-34
MCS®-48 INSTRUCTION SET
STRT T Start Timer
Encoding: [ 1 0 1 I0 1 0 1 I 55H
Description: Timer accumulation is initiated in the timer register. The register is
incremented every 32 instruction cycles. The prescaler which counts the
32 cycles is cleared but the timer register is not.
Example: Initialize and start timer.
STARTT: CLR A ;CLEAR ACC TO ZEROS
MOV T,A ;MOVE ZEROS TO TIMER
EN TCNTI ;ENABLE TIMER INTERRUPT
STRTT ;START TIMER
SWAP A Swap Nibbles within Accumulator
Encoding: 10 1 0 0 10 1 1 1 I 47H
Description: Bits 0-3 of the accumulator are swapped with bits 4-7 of the accumulator.
Operation: (A 4- 7 ) ~ (AO-3)
Example: Pack bits 0-3 of locations 50-51 into location 50.
PCKDIG: MOV RO, #50 ;MOVE '50' DEC TO REG 0
MOV R1, #51 ;MOVE '51' DEC TO REG 1
XCHD A,@RO ;EXCHANGE BITS 0-3 OF ACC
;AND LOCATION 50
SWAP A ;SWAP BITS 0-3 AND 4~7 OF ACC
XCHD A,@R1 ;EXCHANGE BITS 0-3 OF ACC AND
;LOCATION 51
MOV @RO,A ;MOVE CONTENTS OF ACC TO
;LOCATION 50
XCH A,R r Exchange Accumulator-Register Contents
Encoding: ~ 1 0 11 r r r J 28H-2FH
Description: The contents of the accumulator and the contents of working register 'r'
are exchanged.
Operation: (A) ~ (Rr) r = 0-7
Example: Move PSW contents to Reg 7 without losing accumulator contents.
XCHAR7: XCH A,R7 ;EXCHANGE CONTENTS OF REG 7
;AND ACC
MOV A, PSW ;MOVE PSW CONTENTS TO ACC
XCH A,R7 ;EXCHANGE CONTENTS OFHEG 7
'AND ACC AGAIN
3-35
MCS®-48 INSTRUCTION SET
XCH A,@Ri Exchange Accumulator and Data Memory Contents
Encoding: 10 0 1 0 10 0 0 i 1 20H-21H
Description: The contents of the accumulator and the contents of the resident data
memory location addressed by bits 0-5** of register 'i' are exchanged.
Register 'i' contents are unaffected.
Operation: (A) ~ «Ri)) i =0-1
Example: Decrement contents of location 52.
DEC52: MOV RO;#52 ;MOVE '52' DEC TO ADDRESS REG 0
XCH A,@RO . ;EXCHANGE CONTENTS OF ACC
;AND LOCATION 52
DECA ;DECREMENT ACC CONTENTS
XCH A,@RO ;EXCHANGE CONTENTS OF ACC
;AND LOCATION 52 AGAIN
XCHD A,@Ri Exchange Accumulator and Data Memory 4-Bit Data
Encoding: 10 0 1 1 1 0 0 0 i 1 30H-31 H
Description: This instruction exchanges bits 0-3 of the accumulator with bits 0-3 of
the data memory location addressed by bits 0-5*~ of register 'i'. Bits 4-7 of
the accumulator, bits 4-7 of the data memory location, and the contents of
register 'i' are unaffected. .
Operation: (AO-3) ~ «RiO-3)) i = 0-1
Example: Assume program counter contents have been stacked in locations 22-23.
XCHNIB: MOV RO,#23 ;MOVE '23' DEC TO REG 0
CLRA ;CLEAR ACC TO ZEROS
XCHD A,@RO ;EXCHANGE BITS 0-3 OF ACC AND
;LOCATION 23 (BTS 8-11 OF PC ARE
;ZEROED, ADDRESS REFERS
:TO PAGE 0)
XRL A,R r Logical XOR Accumulator With Register Mask
Encoding: 11 1 0 1 11 r r' r I D8H-DFH
Description: Data- in the accumulator is EXCLUSIVE ORed with. the mask contained in
working register 'r'.
Operation: (A) -:- (A) XOR (Rr) r = 0-7
Example: XORREG: XRL A,R5 ;'XOR' ACC CONTENTS WITH
;MASK IN REG 5
** 0-5 in 8048AH/8748H
0-6 in 8049AHI8749H
0-7 in 8050AH
3-36
MCS®-48 INSTRUCTION SET
XRL A,@Ri Logical XOR Accumulator With Memory Mask
Encoding: 11 1 0 1 I0 0 0 i I DOH-D1H
Description: Data in the accumulator is EXCLUSIVE ORed with the mask contained in the
data memory location addressed by register 'i', bits 0-5.**
Operation: (A) 4- (A) XOR ((Ri)) i = 0-1
Example: XORDM: MOV R1 ,#20H ;MOVE '20' HEX TO REG 1
XRL A,@R1 ;'XOR' ACC CONTENTS WITH MASK
;IN LOCATION 32
XRL A,#data Logical XOR Accumulator With Immediate Mask
Encoding: 11 1 0 1 I0 0 1 1 I Id7 d6 d5 d4 I d3 d2 d1 dO I D3H
Description: This is a 2-cycle instruction. Data in the accumulator is EXCLUSIVE ORed
with an immediately-specified mask.
Operation: (A) 4- (A) XOR data
Example: XORID: XOR A,#HEXTEN ;XOR CONTENTS OF ACC WITH MASK
;EQUAL VALUE OF SYMBOL 'HEXTEN'
•• 0-5 in 8048AH/8748H
0-6 in 8049AH/8749H
0-7 in 8050AH
3-37
MCS® . .48 Data Sheets 4
8243
MCS®·48INPUT/OUTPUT EXPANDER
• O·C TO 70·C Operation
PORT4
P50 vee
P40 P51
PORTS
""1 P52
PI42 P53
PORT Z N3 P60
cs P61
PROG P62
P23 P63
PORT 6 P22 P73
P21 P72
, P20 P71
GND P70
270161-2
Figure 2. 8243 Pin
PORT'
Configuration
270161-1
Figure 1.8243 Block Diagram
October 1986,
4-1 Order Number: 270161-1)01
8243
Table 1. Pin Description
Symbol Pin No. Function
PROG 7 Clock Input. A high to low transition on PROG signifies that address
and control are available on P20-P23, and a low to high transition
signifies that data is available on P20-P23.
CS 6 Chip Select Input. A high on CS inhibits any change of output or
internal status.
P20-P23 11-8 Four (4) bit bi-directional port contains the address and control bits on
a high to low transition of PROG. During a low to high transition, P2
contains the data for a selected output port if a write operation, or the
. data from a selected port before the low to high transition if a read
operation.
GND 12 OV supply.
P40-P43 2-5 Four (4) bit bi-directionalllO ports.
P50-P53 1,23-21 May be programmed to be input (during read), low impedance latched
P60-P63 20-17 output (after write), or a tri-state (after read). Data on pins P20-P23
P70-P73 13-16 may be directly written, ANDed or ORed with previous data.
Vee 24 +5Vsupply.
FUNCTIONAL DESCRIPTION either high or low when power is applied. The first
high to low transition of PROG causes the device to
exit power on mode. The power on sequence is ini-
General Operation tiated if Vee drops below 1V.
Address Instruction
The 8243 contains four 4-bit I/O ports which serve P21 P20 P23 P22
Code Code
as an extension of theon-chip 110 and are ad-
dressed as Ports 4-7. The following operations may 0 0 Port 4 0 0 Read
be performed on these ports: 0 1 Port 5 0 1 Write
• Transfer Accumulator to Port. 0 Port 6 1 0 ORlD
• Transfer Port to Accumulator. 1 Port 7 1 ANlD
• AND Accumulator to Port.
• OR Accumulator to Port. Write Modes
All communication between the 8048 and the 8243 The device. has three write modes. MOVD Pi, A di-
occurs over Port 2 (P20-P23) with timing provided rectly writes new data into the selected port and old
by an output pulse on the PROG pin of the proces- data is lost. ORlD Pi, A takes new data, OR's it with
sor. Each transfer consists of two 4-bit nibbles: the old data and then writes it to the port. ANlD Pi,
A takes new data, AND's it with the old data and
The first containing the "op code" and port address then writes it to the port. Operation code and port
and the second containing the actual 4-bits of data. address are latched from the input Port 2 on the high
A high to low transition of the PROG line indicates to low transition of the PROG pin. On the low to high
that address is present while a low to high transition transition of PROG data on Port 2 is transferred to
indicates the presence of data. Additional 8243's the logic block of the specified output port.
may be added to the 4-bit bus and chip selected
using additional output lines from the After the logic manipulation is performed, the data is
8048/8748/8035. latched and outputed. The old data remains latched
until new valid outputs are entered.
Power On Initialization
Read Mode
Initial application of power to the device forces in-
put/ output Ports 4, 5, 6, and 7 to the tri-state and The device has one read mode. The operation code
Port 2 to. the input mode. The PROG pin may be and port address are latched from the input Port 2
4-2
inter 8243
on the high to low transition of the PROG pin. As Normally, a port will be in an output (write mode) or
soon as the read operation and port address are input (read mode). If modes are changed during op-
decoded, the appropriate outputs are tri-stated, and eration, the first read following a write should be ig-
the input buffers switched on. The read operation is nored; all following reads are valid. This is to allow
terminated by a low to high transition of the PROG the external driver on the port to settle after the first
. pin. The port (4, 5, 6 or 7) that was selected is read instruction removes the low impedance drive
switched to the tri-stated mode while Port 2 is re- from the 8243 output. A read of any port will leave
turned to the input mode. that port in a high impedance state.
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This data. sheet contains preliminary infor-
Ambient Temperature Under Bias ...... o·c to 70·C mation on new products in production. It is valid for
Storage Temperature .......... - 65·C to + 150·C the devices indicated in the revision history. The
specifications are subject to change without notice.
Voltage on Any Pin
with Respect to Ground .......... -0.5V to + 7V • WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
Power Dissipation ........................ 1 Watt These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and ex-
tended exposure beyond the "Operating Conditions"
may affect device reliability.
D.C. CHARACTERISTICS T A = O·C to 70·C, Vee = 5V ± 10%
Test
Symbol Parameter Min Typ Max Units
Conditions
VIL Input Low Voltage -0.5 0.8 V
VIH Input High Voltage 2.0 Vee + 0.5 V
VOL1 Output Low Voltage Ports 4-7 0.45 V IOL = 4.5 mAo
VOL2 Output Low Voltage Port 7 1 V IOL = 20mA
VOH1 Output High Voltage Ports 4-7 2.4 V IOH = 240/LA
IIL1 Input Leakage Ports 4-7 -10 20 /LA Vin = Vee toOV
11L2 Input Leakage Port 2, CS, PROG -10 10 /LA Vin = Vee to OV
VOL3 Output Low Voltage Port 2 0.45 V IOL = 0.6mA
Icc Vee Supply Current 10 20 mA (Note 1)
VOH2 Output Voltage Port 2 2.4 IOH = 100 /LA
IOL Sum of AIiIOL From 16 Outputs 72 mA 4.5 mA Each Pin
.. ..
'Refer to FIgure 3 for addItIonal Sink current capabIlity.
4-3
8243
A.C. CHARACTERISTICS TA = 'OOCto 70·C, vcc = 5V ± 10%
Symbol Parameter Min Max Units Test Conditions,
IA Code Valid before PROG 50 ns 80 pF Load
Ie Code Valid after PROG 60 ns 20pF Load
tc Data Valid before PROG 200 ns 80pF Load
tD Data Valid after PROG 20 ns' 20pF Load'
tH Floating after PROG 0 150 ns 20pF Load
tK PROG Negative Pulse Width 700 ns
les CS Valid before/after PROG 50 ns
tpo Ports 4-7 Valid after PROG 700 , ns 100 pF Load
tLP1 Ports 4-7 Valid before/after PROG 100 ns
tACC Port 2 Valid after PROG 650 ns 80pF Load
NOTE:
.1. Icc (-40·C to 85·C EXPRESS options) 15 mA typical/25 mA maximum.
Z.4 _ _ _
0.45
...,X:: > ,m_. <: x. ___ -
270161-3
A.C. Testing: Inputs arEi driven at 2.4V for a Logic "1" and 0.45V for a Logic "0". Output timing measurements are made a\2.0V for Logic "1"
and O.BV for a Logic "0".
4-4
infef 8243
WAVEFORMS
PROG
~ _________________ IK ________________ ~
PORT 2 FLOAT FLOAT
PORT2 ' ' 61
IpO
PORTS 4-1 PREVIOUS OUTPUT VALID
lIP
PORTS 4-7 INPUT VALID
ICS ICS
270161-4
4-5
inter 8243
125
100
C
!
':i
!}
..
~ 75
'
Z
II:
II: GUARANTEED WORST CASE
U". CURRENT SINKING CAPABILITIES
Z OF ANY 1/0 PORT PIN VI, TOTAL
in 50 SINK CURRENT OF ALL PINS
...
;!
0
.
25
2 4 11 12 13
MAXIMUM SINK CURRENT ON ANY PIN @ .45V
MAXIMUM 10L WORST CASE PIN (rnA)
270161-5
Figure 3. 8243 Current Sink Capability
Sink Capability NOTE:
A 10 to 50 Kn pullup resistor to + 5V should be
The 8243 can sink 5 mA @ 0.45V on each of its 16 added to 8243 outputs when drivingt6' 5V CMOS
1/0 lines simultaneously. 'If, however, all lines are directly.
not sinking simultaneously or all lines are not fully Example: This example shows how the use of the
loaded, the drive capability of any individual line in- 20 mA sink.capability of Port 7 affects the
creases as is shown by the accompanying curve. sinking capability of the other 1/0 lines.
For example, if only 5 of the 16 lines are to sink An 8243 will drive the following loads
simultaneously.
current at one time, the curve shows that each of
those 5 lines is capable of sinking 9 mA @ 0.45V (if 2 loads-20 mA @1V (Port 7 only)
any lines are to sink 9 mA the total IOL must not 8 10ads-4 mA @ 0.45V
exceed 45 mA or five 9 mA loads).
6 loads-3.2 mA @ 0.45V
Example: How many pins can drive 5 TTL loads
Is this within the specified iimits?
(1.6 mAl assuming remaining pins are un-
loaded? elOL = (2 x 20) + (8 x 4) + (6 x 3.2)
= 91.2 mA.
IOL = 5 x 1.6 mA = 8 mA
From the curve: for IOL = 4 mA, elOL ""
elOL = 60 mA from curve
93 mA. Since 91.2 mA < 93 mA the loads
# pins = 60 mA .;- B mA/pin = 7.5 = 7 are within specified limits.
In this case, 7 lines can sink 8 mA for a Although the 20 mA @ 1V loads are used
total of 56 mAo This leaves 4 mA sink cUr- in calculating elOL' it is the largest current
rent capability which can be divided in any required @ 0.45V which determines the
way among the remaining 8 1/0 lines of maximum allowable eIOL.
the 8243.
4-6
inter 8243
-::-
CS
110
P4 110
PROG PROG
TEST PS 110
INPUTS
8048 8243
P6 4 110
DATA IN
P2
P7 I/O
270161-6
Figure 4. Expander Interface
PROG ~'- _ _ _ _ _ --JI 81TS 3,2
00 } READ
01 WRITE
81TS1,O
00 } PORT
01
10 OR 10 ADDRESS
P20·P23 ---<'-_--"X"'-__-J)>--- 11 AND 11
ADDRESS 14·81TSI DATA 14·81TSI
270161-7
Figure 5. Output Expander Timing
PORT 1
11148
PORT 2
PROG~--------------~--------------~----------------~--------------~
270161-8
Figure 6. Using Multiple 8243'5
4-7
P8748H/P8749H
8048AH/8035AHL/8049AH/8039AHL/8050AH/8040AHL
HMOS SINGLE-COMPONENT 8-BIT
MICROCONTROLLER
• Interval
High Performance HMOS II
• Programmable ROMs Using 21V
• Two Single
Time/Event Counter
• Up to 1.36 J-Ls Instruction Cycle All
Easily Expandable Memory and I/O
• Single 5-VoltLevel Interrupts
• Instructions 1 or 2 Cycles
• Over 96 Instructions; 90% Single Byte
Supply
•
The Intel MCS®-48 family are totally self-sufficient, 8-bit parallel computers fabricated on Single silicon chips
using Intel's advanced N-channel silicon gate HMOS process.
The family contains 27 110 lines, an 8-bit timer/counter, and on-board oscillator/clock circuits. For systems
that require extra capability, the family can be expanded using MCS®-80/MCS®-85 peripherals.
These microcontrollers are available in both masked ROM and'ROMless versions as well as a new version,
The Programmable ROM. The Programmable ROM provides the user with the capability of a masked ROM
while providing the flexibility of a device that can be programmed at the time of requirement and to the desired
data. Programmable ROM's allow the user to lower inventory levels while at the same time decreasing delay
times and code risks.
These microcomputers are designed to be efficient controllers as well as arithmetic processors. They have
extensive bit handling capability as well as facilities for both binary and BCD arithmetic. Efficient use of
program memory results from an instruction set consisting of mostly single byte instructions and no instruc-
tions over 2 bytes in length.
Device Internal Memory RAM STANDBY
8050AH 4Kx8 ROM 256x8 RAM yes
8049AH 2Kx8 ROM 128 x8 RAM yes
8048AH 1Kx8ROM 64x8RAM yes
8040AHL None 256x8RAM yes
8039AHL None 128x8RAM yes
8035AHL None 64x8RAM yes
P8749H 2K x 8 Programmable ROM 128x8RAM no
P8748H 1K x 8 Programmable ROM 64x8RAM no
270053-1
Figure 1. Block Diagram
270053-2
Figure 2. Logic Symbol
August 1989
4-8 Order Number: 270053-003
infef MCS®-48
I~ I~
N
~ ~ ~ ~
~ ~ g
<.>
<.> <.>
z > ;::
"~ ~ ~
T. 1 Vee
XTAL 1 T1
XTAL 2 P21
RESET P2. iNT P2.4
55 P25 EA Pl.7
!NT P2' R5 P1.6
EA 8049AH/B039AHL
P11 PSEN P1.5
Ali P1. 8050AH/80.0AHL
PSEN P15 WR 44- PIN P1.4
PLee
ViR P1' Ne Ne
ALE P13
DB. ALE P1.3
P12
OB, 13 DBO P1.2
OB2 P1. DB1 Pl.1
Top View
OB3 VOO Looking down on PC Board
DB2 P1.0
DB. PAOG
OB5 P23 DB3 VDD
DB. P22
OB1
V55
270053-14
Figure 3. Pin Configuration Figure 4. Pad Configuration
Table 1. Pin Description
Pin
Symbol Function Device
No.
Vss 20 Circuit GND potential. All
Voo 26 + 5V during normal operation. All
low power standby pin. 8048AH
8035AHl
8049AH
8039AHl
8050AH
8040AHl
Programming power supply (+ 21V). P8748H
P8749H
Vee 40 Main power supply; + 5V during operation and programming. All
PROG 25 Output strobe for 8243 I/O expander. All
Program pulse ( + 18V) input pin During Programming. P8748H
P8749H
P10-P17 27-34 8-bit quasi-bidirectional port. All
Port 1
P20-P23 21-24 8-bit quasi-bidirectional port. P20-P23 contain the four high order All
P24-P27 35-38 program counter bits during an external program memory fetch and
Port 2 serve as a 4-bit I/O expander bus for 8243.
DBO-DB7 12-19 True bidirectional port which can be written or read synchronously All
BUS using the RD, WR strobes. The port can also be statically latched.
Contains the 8 low order program counter bits during an external
program memory fetch, and receives the addressed instruction under
the control of PSEN. Also contains the address and data during an
external RAM data store instruction, under control of ALE, RD, and
WR.
TO 1 Input pin testable using the conditional transfer instruction JTO and All
JNTO. TO can be designated as a clock output using ENTO ClK
instruction.
Used during programming. P8748H
P8749H
4-9
MCS®-48
Table 1. Pin Description (Continued)
Pin
Symbol Function Device
No.
T1 39 Input pin testable using the JT1, and JNT1 instructions. Can be All
designated the timer/counter input using the STRT CNT instruction.
INT 6 Interrupt input. Initiates an interrupt if interrupt is enabled. Interrupt is All
disabled after a reset. Also testable with conditional jump instruction.
(Active low) interrupt must remain low for at least 3 machine cycles for
proper operation.
RD 8 Output strobe activated during a BUS read. Can be used to enable All
data onto the bus from an external device.
Used as a read strobe to external data memory. (Active low)
RESET 4 Input which is used to initialize the processor. (Active low) (Non TIL All
VI H)
Used during power down. 8048AH
8035AHL
8049AH
8039AHL
8050AH
8040AHL
Used during programming. P8748H
P8749H
Used during ROM verification. 8048AH
P8748H
8049AH
P8749H
8050AH
WR 10 Output strobe during a bus .write. (Active low) All
. Used as write strobe to external data memory.
ALE 11 Address latch enable. This signal occurs once during each cycle and is All
useful as a clock output.
The negative edge of ALE strobes address into external data and
program memory.
PSEN 9 Program store enable. This output occurs only during a fetch to All
external program memory. (Active low)
SS 5 Single step input can be used in conjunction with ALE to "single step" All
the processor through each instruction. . .
(Active low) Used in sync mode. 8048AH
8035AHL
8049AH
8039AHL
8050AH
8040AHL
EA 7 External access input which forces all program memory fetches to All
reference external memory. Useful for emulation and debug. (Active
high)
Used during (18V) programming. P8748H
P8749H
Used during ROM verification (12V) .. 8048AH
8049AH
8050AH
XTAL1 2 One side of crystal input for internal oscillator. Also input for external All
source. (Non TTL VI H)
XTAL2 3 Other side of crystal input. All
4-10
infef MCS®-48
Table 2. Instruction Set
Accumulator Input/Output
Mnemonic Description Bytes Cycles Mnemonic Description Bytes Cycles
ADD A, R Add register to A 1 1 INA, P Input port to A 1 2
ADD A, @R Add data memory 1 1 OUTLP, A Output A to port 1 2
to A ANL P, #data And immediate to 2 2
ADDA, #data Add immediate to A 2 2 port
ADDCA, R Add register with ORL P, #data Or immediate to 2 2
carry port
ADDCA, @R Add data memory INSA, BUS Input BUS to A 1 2
with carry OUTL BUS, A Output A to BUS 1 2
ADDC A, #data Add immediate with 2 2 ANL BUS, #data And immediate to 2 2
carry BUS
ANLA, R And register to A ORL BUS, # data Or immediate to 2 2
ANLA, @R And data memory BUS
to A MOVDA, P Input expander port 2
ANLA, #data And immediate to A 2 2 toA
ORLA, R Or register to A 1 1 MOVDP, A Output A to 2
ORLA, @R Or data memory 1 expander port
toA ANLD P, A And A to expander 2
ORLA, #data Or immediate to A 2 2 port
XRLA, R Exclusive or register 1 ORLDP,A Or A to expander 2
toA port
XRLA,@R Exclusive or data
memory to A
XRLA, #data Exclusive or 2 2 Registers
immediate to A
Mnemonic Description Bytes Cycles
INCA Increment A
DECA Decrement A INCR Increment register 1 1
CLRA Clear A INC@R Increment data memory 1
CPLA Complement A DECR Decrement register
DAA Decimal adjust A
SWAP A Swap nibbles of A Branch
RLA Rotate A left
RLCA Rotate A left Mnemonic Description Bytes Cycles
through carry
JMP addr Jump unconditional 2 2
RRA Rotate A right
JMPP@A Jump indirect 1 2
RRCA Rotate A right DJNZ R, addr Decrement register 2 2
through carry
and skip
JC addr Jump on carry = 1 2 2
JNC addr Jump on carry = 0 2 2
JZ addr Jump on A zero 2 2
JNZ addr Jump on A not zero 2 2
JTO addr Jump on TO = 1 2 2
JNTO addr Jump on TO = 0 2 2
JT1 addr Jump on T1 = 1 2 2
JNT1 addr Jump on T1 = 0 2 2
JFO addr Jump on FO = 1 2 2
JF1 addr Jump on F1 = 1 2 2
JTF addr Jump on timer flag 2 2
JNI addr Jump on INT = 0 2 2
JBb addr Jump on accumulator 2 2
bit
4·11
intJ MCS®-48
Table 2. Instruction Set (Continued)
r---------------~------------~ .-----------------------------~
Subroutine Timer/Counter
Mnemonic Description Bytes Cycles Mnemonic Description Bytes Cycles
CALL addr Jump to subroutine 2 2 MOVA, T Read timer/counter 1 1
RET Return 1 2 MOVT,A Load timer/counter 1 1
RETR Return and restore 1 2 STRTT Start timer 1 1
status STRTCNT Start counter 1 1
STOP TCNT Stop timer/counter 1 1
EN TCNTI Enable timerl 1 1
Flags counter interrupt
DIS TCNTI Disable timerl
Mnemonic Description Bytes Cycles counter interrupt
CLRC Clear carry 1 1
CPLC Complement carry 1 1
Control
CLR FO Clear flag 0 1 1
CPLFO Complement flag 0 1 1
Mnemonic Description Bytes Cycles
CLR F1 Clear flag 1 1 1
CPL F1 Complement flag 1 1 1 EN I Enable external 1 1
interrupt
DISI Disable external
Data Moves interrupt
Mnemonic Description Bytes Cycles SELRBO Select register bank 0
SELRB1 Select register bank 1
MOVA,R Move register to A 1 1 SELMBO Select memory bank 0
MOVA,@R Move data memory 1 1 SELMB1 Select memory bank 1
toA
ENTOCLK Enable clock output
MOV A, #data Move immediate to 2 2
A onTO
MOVR,A Move A to register
MOV@R,A Move A to data Mnemonic Description Bytes Cycles
memory
MOV R, #data Move immediate to 2 2 NOP No operation 1 1
register
MOV @R, #data Move immediate to 2 2
data memory
MOVA, PSW MovePSWtoA
MOVPSW,A MoveAtoPSW
XCHA, R Exchange A and
register
XCHA,@R Exchange A and
data memory
XCHDA,@R Exchange nibble of 1
A and data memory
MOVXA, @R Move external data 2
memory to A
MOVX@R,A Move A to external 2
data memory
MOVPA,@A Move to A from 2
current page
MOVP3A,@/J:. Move to A from 2
page 3
4·12
inter
ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. The specifi-
cations are subject to change without notice.
Gase Temperature Under Bias ....... OOG to + 700G
* WARNING: Stressing the device beyond the "Absolute
Storage Temperature .......... - 65°G to + 1500G Maximum Ratings" may cause permanent damage.
Voltage on any Pin with Respect These are stress ratings only. Operation beyond the
to Ground ...................... - 0.5V to + 7V "Operating Conditions" is not recommended and ex-
tended exposure beyond the "Operating Conditions"
Power Dissipation .......................... 1.5W may affect device reliability.
D.C. CHARACTERISTICS TA = OOGto +70o G;Vee = VDD = 5V ±10%;Vss = ov
Limits
Symbol Parameter Unit Test Conditions Device
Min Typ Max
VIL Input Low Voltage (All -0.5 0.8 V All
Except RESET, X1, X2)
VIL1 Input Low Voltage -0.5 0.6 V All
(RESET, X1, X2)
VIH Input High Voltage 2.0 Vee V All
(All Except XT AL 1,
XTAL2, RESET)
VIH1 Input High Voltage 3.8 Vee V All
(X1, X2, RESET)
VOL Output Low Voltage 0.45 V IOL = 2.0 mA All
(BUS)
VOL1 Output Low Voltage 0.45 V IOL = 1.8 mA All
(RD, WR, PSEN, ALE)
VOL2 Output Low Voltage 0.45 V IOL = 1.0 mA All
(PROG)
VOL3 Output Low Voltage 0.45 V IOL = 1.6 mA All
(All Other Outputs)
VOH Output High Voltage 2.4 V IOH = - 400 p.A All
(BUS)
VOH1 Output High Voltage 2.4 V IOH = -100 p.A All
(RD, WR, PSEN, ALE)
VOH2 Output High Voltage 2.4 V IOH = -40 p.A All
(All Other Outputs)
4-13
MCS®-48
D.C. CHARACTERISTICS TA = O·C to + 70·C; Vee = Voo = 5V ± 10%; Vss =, OV (Continued)
Limits
Symbol Parameter Unit Test Conditions Device
Min Typ Max
1L1 Leakage Current ±10 IJ-A Vss :5: VIN :5: Vee All
(T1, INT)
IU1 Input Leakage Current -500 IJ-A Vss + 0.45 :5: VIN :~ Vee All
(P10-P17, P20-P27,
EA,SS)
IU2 Input Leakage Current -10 -300 IJ-A Vss :5: VIN :5: 3.S All
RESET
ILO Leakage Current , ±10 IJ-A Vss :5: VIN ~ Vee All
(BUS, TO) (High
Impedance State)
100 Voo Supply Current 3 5 rnA S04SAH
(RAM Standby) S035AHL
4 7 rnA S049AH
S039AHL
5 10 rnA S050AH
S040AHL
Ibo + Total Supply Current' 30 . 65 rnA S04SAH
Ice S035AHL
35 70 rnA S049AH
S039AHL
40 SO rnA S050AH
S040AHL
30 100 rnA PS74SH
50 110 rnA PS749H
Voo . RAM Standby Voltage 2.2 5.5 V Standby Mode Reset S04SAH
:5:VIL1 S035AH
2.2 5.5 V S049AH
S039AH
2.2 5.5 V S050AH
S040AHL
"ICC + 100 are measured WIth all outputs In their high Impedance state; RESET low; 11 MHz crystal applied; INT. 58, and EA floating.
4-14
inter MCS®-48
A.C. CHARACTERISTICS TA = O·Cto +70·C;Vcc = voo = 5V ±10%;Vss = OV
f (t) 11 MHz Conditions
Symbol Parameter Unit
(Note 3) Min Max (Note 1)
t Clock Period 1 /xtal freq 90.9 1000 ns (Note 3)
tLL ALE Pulse Width 3.5t-170 150 ns
tAL ' Addr Setup to ALE 2t-110 70 ns (Note 2)
tLA Addr Hold from ALE t-40 50 ns
tcC1 Control Pulse Width (RD, WR) 7.5t-200 480 ns
tCC2 Control Pulse Width (PSEN) 6t-200 350 ns
tow Data Setup before WR 6.5t-200 390 ns
two Data Hold after WR t-50 40 ns
tOR Data Hold (RD, PSEN) 1.5t-30 0 110 ns
tR01 RD to Data in 6t-170 375 ns.
tR02 PSEN to Data in 4.5t-170 240 ns
tAW Addr Setup to WR 5t-150 300 ns
tA01 Addr Setup to Data (RD) 10.5t-220 730 ns
tA02 Addr Setup to Data (PSEN) 7.5t-200 460 ns
tAFC1 Addr Float to RD, WR 2t-40 140 ns (Note 2)
tAFc2 Addr Float to PSEN 0.5t-40 10 ns (Note 2)
tLAFC1 ALE to Control (RD, WR) 3t-75 200 ns
tLAFC2 ALE to Control (PSEN) , 1.5t-75 60 ns
tCA1 Control to ALE (RD, WR, PROG) t-65 25 ns
tCA2 Control to ALE (PSEN) 4t-70 290 ns
tcp Port Control Setup to PROG 1.5t-80 50 ns
tpc Port Control Hold to PROG 4t-260 100 ns
tpR PROG to P2 Input Valid 8.5t-120 650 ns
tpF Input Data Hold from PROG 1.5t 0 140 ns
top Output Data Setup 6t-290 250 ns
tpo Output Data Hold 1.5t-90 40 ns
tpp PROG Pulse Width 10.5t-250 700 ns
tpL Port 2110 Setup to ALE 4t-200 160 ns
tLP Port 2110 Hold to ALE 0.5t-30 15 ns
tpv Port Output from ALE 4.5t+ 100 5.0 ns
tOPRR TO Rep Rate 3t 270 ns
tCY Cycle Time 15t 1.36 15.0 IJ.s
NOTES:
1. Control outputs: CL = 80 pF. BUS Outputs: CL = 150 pF.
2. BUS High Impedance Load 20 pF
3. f(t) assumes 50% duty cycle on X1, X2. Max clock period is for a 1 MHz crystal input.
4-15
inter MCS®-48
WAVEFORMS
INSTRUCTION FETCH FROM PROGRAM READ FROM EXTERNAL DATA MEMORY
MEMORY
270053-5
270053-4
WRITE TO EXTERNAL DATA MEMORY INPUT AND OUTPUT FOR A.C. TESTS
2.4V ---~
X 2.0"'TEST POINTS ... 2.0
O.4SY _ _ _~. ,D.'''' "'0.8.
x===
270053-7
A.C. testing inputs are driven at 2.4V for a logic "1" and 0.45V for
a logic "0". Output timing measurements are made at 2.0V for a
logic "1" and 0.8V for a logic "0".
270053-6
PORT 1/PORT 2 TIMING
1ST CYCLE I 2ND
CYCLE
ALE
PSEN - j_ _ _':"" I
P20-23 I
OUTPUT PCH PqRT 20-23 DATA NEW P20-23 DATA I PCH
P2t-27 I
- ~_~_~ ~~O,'~
OUTPUT --1[----;------------;-----.--' '---------'--_
lLP
EXPANDER
PORT
_;.---ILA --_.j. . o--
OUTPUT PCH
I ,.-------i.
~--------~I ~---~
EXPANDER
PORT j
INPUT PCH
PROG
270053-8
4.-16
inter MCS®-48
CRYSTAL OSCILLATOR MODE CERAMIC RESONATOR MODE
Cl Cl
t--______.-__2-1 XTALl
~
_ _--._ _---..._ _ _2::.j XTALl
~ '" J ;;;:
C3
It------'-i___T--L____ ---c-
3
XTAL2
~ I<~o~""f~
, C3
XTAL2
270053-9 270053-10
Cl ~ 5 pF ±% pF + (STRAY < 5 pF)
C2 ~ (CRYSTAL + STAY) < 8 pF
C3 ~ 20 pF ± 1 pF + (STRAY < 5 pF)
Crystal series resistance should be less than 30n at 11 MHz; less
lhan 75n at 6 MHz; less than 180n at 3.6 MHz.
DRIVING FROM EXTERNAL SOURCE
+5V
47011
»-*-------='-j XTALl
+5V
TTL OPEN
COLLECTOR
GATES 47011
L----'---=-i XTAL2
270053-11
For XTALl and XTAL2 define "high" as voltages above 1.6V and
"low" as voltages below 1.6V. The duty cycle requirements for
externally driving XTAL 1 and XTAL2 using the circuits shown
above are as follows: XTALl must be high 35-65% of lhe period
and XTAL2 must be high 35-65% of the period. Rise and fall times
must be faster than 20 ns.
4-17
inter MCS®·48
PROGRAMMING AND VERIFYING THE WARNING:
P8749H/48H PROGRAMMABLE ROM
An attempt to program a missocketed P8749H/48H
will result in severe damage to the part. An indication
Programming Verification of a properly socketed part is the appearance of the
ALE clock output. The lack of this clock may be
In brief, the programming process consists of: acti- used to disable the programmer.
vating the program mode, applying an address,
latching the address, applying data, and applying a The ProgramiVerify sequence is:
programming pulse. Each word is programmed com- 1. Voo SV, Clock applied or internal oscillator
pletely before moving on to the next and is followed operating, RESET = OV, TO = SV, EA = SV,
by a verification step. The following is a list of the BUS and PROG floating. P10 andP11 must be
pins used for programming and a description of their tied to ground.
functions:
2. Insert P8749H/48H in programming socket
3. TO = OV (select program mode)
Pin Function
4. EA = 18V (activate program mode)
XTAL1 Clock Input (3 to 4.0 MHz) S. Address applied to BUS and P20-22
XTAL2
6. RESET = SV (latch address)
RESET Initialization and Address Latching
TO Selection of Program or Verifying Mode 7. Data applied to BUS
EA Activation of ProgramiVerify Modes 8. Voo = 21V (programming power)
BUS Address and Data Input 9. PROG = Vee or float followed by one SO ms
Data Output During Verify pulse to 18V
P20-P22 Address Input 10. Voo = SV
Voo Programming Power Supply
11. TO = SV (verify mode)
PROG Program Pulse Input
12. Read and verify data on BUS
13. TO = OV
14. RESET = OV and repeat from step S
15. Programmer should be at conditions of step 1
when P8749H/48H is removed from socket.
NOTE:
Once programmed the P8749H/48H cannot be
erased.
4-18
MCS®-48
A.C. TIMING SPECIFICATION FOR PROGRAMMING P8748H/P8749H ONLY
TA = 25°C ±5°C; VCC = 5V ±5%; VOO = 21 ±0.5V
Symbol Parameter Min Max Unit Test Conditions
tAW Address Setup Time to RESET 4tCY
tWA Address Hold Time After RESET 4tCY
tow Data in Setup Time to PROG 4tCY
two Data in Hold Time After PROG 4tCY
tpH RESET Hold Time to Verify 4tCY
tvoow Voo Hold Time Before PROG 0 1.0 ms
tvoOH Voo Hold Time After PROG 0 1.0 ms
tpw Program Pulse Width 50 60 ms
tTW TO Setup Time for Program Mode 4tCY
tWT TO Hold Time After Program Mode 4tCY
too TO to Data Out Delay 4tCY
tww RESET Pulse Width to Latch Address 4tCY
tr, tf Voo and PROG Rise and Fail Times 0.5 100 }J-s
tCY CPU Operation Cycle Time 3.75 5 fLs
tRE RESET Setup Time before EA 4tCY
NOTE:
If Test 0 is high, tDO can be triggered by RESET.
D.C. CHARACTERISTICS FOR PROGRAMMING P8748H/P8749H ONLY
TA = 25°C ±5°C; VCC = 5V ±5%; VOO = 21 ±0.5V
Symbol Parameter Min Max Unit Test Conditions
VOOH Voo Program Voltage High Level 20.5 21.5 V
VOOL Voo Voltage Low Level 4.75 5.25 V
VPH PROG Program Voltage High Level 17.5 18.5 V
VPL PROG Voltage Low Level 4.0 Vcc V
VEAH EA Program or Verify Voltage High Level 17.5 18.5 V
100 Voo High Voltage Supply Current 20.0 mA
IpROG PROG High Voltage Supply Current 1.0 mA
lEA EA High Voltage Supply Current 1.0 mA
4-19
infef MCS®·48
SUGGESTED ROM VERIFICATION ALGORITHM FOR ROM DEVICE ONLY
INITIAL ROM DUMP CYCLE SUBSEQUENT ROM DUMP CYCLES
ALE
(NOTE 1) : (OUTPUT)
I
'12V I I
EA-.-J : (INPUT)
DB------I ADDRESS H ROM DATA
~~___A_D_D_R_E_S_S__~~---------------
'-----(IN-P-U-T-)--... (OUTPUT) (INPUT) (OUTPUT):
RESET _ _ _ _ _ _-'
,
: (INPUT)
P2~P23 _ _ _ _-L________A_D_D_R_E_S_S______~~L______A_D_D_R_E_S_S______Jr-----------------
I (INPUT)
I
270053-12
50H Vec ~ VOD ~ +5V
Vss ~ OV
Al0 ADDR
All AD DR
NOTE:
ALE is function of X1, X2 inputs,
COMBINATION PROGRAM/VERIFY MODE (PROGRAMMABLE ROMS ONLY)
EA
VEAH
~tRE1
b=rw-
Vee
PROGRAM --~------tl-'--VERIFY---+----PROGRAM-
Vee
TO
VIL1 IWW-
Vee
RESET
VIL1
tAW-t---+~+-IWA
~ r-~D~A=TA~T=O~B=E--~
DBo-OB7 ---..r- - - PROGRAMMED VALID
__ -{NE'KT ADDRX=
VALID
LAST NEXT
PZO-PZl ADDRESS
ADDRESS
VDDH - - -
VDD
Vee-----------------------
tDW
VPH --,--, --'-- -------t---+;-~
PROGVPL - ' - - - - - - - - - - - - - - -
270053-13
4-20
D8748H/D8749H
HMOS-E SINGLE-COMPONENT 8-BIT MICROCOMPUTER
• High Performance HMOS-E • Compatible with 8080/8085 Peripherals
• Interval TimerlEvent Counter • Easily Expandable Memory and 1/0
• Two Single Level Interrupts • Up to 1.35 JJ-s Instruction Cycle;
All Instructions 1 or 2 Cycles
• Single 5-Volt Supply
• Over 96 Instructions; 90% Single Byte
The Intel D8749H/D8748H are totally self-sufficient, 8-bit parallel computers fabricated on single silicon chips
using Intel's advanced N-channel silicon gate HMOS-E process.
The family contains 27 I/O lines, an 8-bit timer/counter, on-chip RAM and on-board oscillator/ciock circuits.
For systems that require extra capability, the family can be expanded using MCS®-80/MCS®-85 peripherals.
These microcomputers are designed to be efficient controllers as well as arithmetic processors. They have
extensive bit handling capability as well as facilities for both binary and BCD arithmetic. Efficient use of
program memory results from an instruction set consisting mostly of single byte instructions and no instruc-
tions over 2 bytes in length.
Device Internal Memory
D8749H 2KxBEPROM I 12BxB RAM
DB74BH 1KxB EPROM I 64xB RAM
PORT
1
D8748H PORT
RESET 2
D8749H
SINGLE
STEP
READ
WRITE
PROGRAM
STORE
EN...OLE
INTERRUPT ADDRESS
LATCH
ENABLE
BUS
PORT
EXPANDER
210983-1 STROBE
Figure 1. 210983-2
Block Diagram
Figure 2.
Logic Symbol
October 1987
4-21 Order Number: 210983-003
intJ 087 48H/087 49H
Vee
XTAL 1 T1
XTAL 2 P27
P26
P25
P2.
PI7
P16
PIS
P13
P12
P11
Pl0
VOD
PROG
P23
P22
P21
Vss
210983'-3
Figure 3. Pin Configuration
Table 1. Pin Description (40-Pin DIP)
Symbol Pin No. Function
Vss 20 Circuit GND potential.
VDD 26 + 5V during normal operation.
Programming power supply (+ 21 V).
Vee, 40 Main power supply; + 5V during operation and programming.
PROG 25 Output strobe for 8243 1/0 expander.
Program pulse (+ 18V) input pin during programming.
P10-P17 27-34 8-bit quasi-bidirectional port.
Port 1
P20-P23 21-24 8-bit quasi-bidirectional port. P20-P23 contain the four high order program
'counter bits during an external program memory fetch and serve as a 4-bit '
1/0 expander bus for 8243.
P24-P27 35-38
Port 2
DBO-DB7 12-19 True bidirectional port which can be written or read synchronously using the
BUS RD, WR strobes. The port can also be statically latched. Contains the 8 low
order program counter bits during an external program memory fetch, and
receives the addressed instruction under the control of PSEN. Also contains
the address and data during an external RAM data store instruction, under
control of ALE, RD, and WR.
TO 1 Input pin testable using the conditional transfer instructions JTO 'and JNTO.
TO can be designated as a clock output using ENIO CKL instruction.
Used during programming.
T1 39 , Input pin testable using the JT1, and JNT1 instructions. Can be designated
the timerlcounter input using the STRT CNT instruction.
INT 6 Interrupt input. Initiates an interrupt if interrupt is enabled. Interrupt is
disableq after a reset. Also testable with conditional jump instruction. (Active
low) interrupt must remain low for at least 3 machine cycles for proper
operation.
RD 8 Output strobe activated during a BUS read. Can be used to enable data onto
the bus from an external device.
Used as a read strobe to external data memory. (Active low)
4-22
D8748H/D8749H
Table 1 Pin Description (40-Pin DIP) (Continued)
Symbol Pin No. Function
RESET 4 Input which is used to initialize the processor. (Active low) (Non TTL VIH)
Used during programming.
WR 10 Output strobe during a bus write. (Active low)
Used as write strobe to external data memory.
ALE 11 Address latch enable. This signal occurs once during each cycle and is
useful as a clock output.
The negative edge of ALE strobes address into external data and program
memory.
PSEN 9 Program store enable. This output occurs only during a fetch to external
program memory. (Active low.)
5S 5 Single step input can be used in conjunction with ALE to "single step" the
processor through each instruction.
EA 7 External access input which forces all program memory fetches to reference
external memory. Useful for emulation and debug. (Active high.)
Used during (18V) programming.
XTAL1 2 One side of crystal input for internal oscillator. Also input for external source.
(Non TTL VIH.)
XTAL2 3 Other side of crystal input.
Table 2. Instruction Set
Mnemonic Description Bytes Cycles Mnemonic Description Bytes Cycles
ACCUMULATOR ACCUMULATOR (Continued)
ADD A, R Add register to A INCA IncrementA
ADDA,@R Add data DECA Decrement A
memory to A CLRA Clear A
ADD A, #data Add immediate 2 2 CPLA Complement A
toA DAA Decimal adjust A
ADDCA, R Add register with SWAP A Swap nibbles of
carry A
ADDCA,@R Add data RLA Rotate A left
memory with RLCA Rotate A left
carry through carry
AD DC A, # data Add immediate 2 2 RRA Rotate A right
with carry RRCA Rotate A right
ANLA, R And register to A through carry
ANLA,@R And data
memory to A INPUT/OUTPUT
ANLA, #data And immediate 2 2 INA,P Input port to A 1 2
to A OUTL P, A Output A to port 1 2
ORLA, R Or register to A ANL P, #data And immediate 2 2
ORLA,@R Or data memory to port
to A ORL P, #data Or immediate to 2 2
ORLA, #data Or immediate to 2 2 port
A INSA, BUS Input BUS to A 2
XRLA, R Exclusive or OUTL BUS, A Output A to BUS 2
register to A ANL BUS, #data And immediate 2 2
XRLA,@R Exclusive or to BUS
ORL BUS, #data Or immediate to 2 2
data memory to
A BUS
XRL A, #data Exclusive or 2 2 MOVDA, P Input expander 2
immediate to A port to A
4-23
inter 087 48H/087 49H ~OOrgILO~OOOb\OOW
Table 2. Instruction Set (Continued)
Mnemonic Description Bytes Cycles Mnemonic Description Bytes Cycles
INPUT/OUTPUT (Continued) DATA MOVES (Continued)
MOVDP,A Output A to 2 MOVR,A Move A to register
expander port MOV@R,A Move A to data
ANLDP,A And A to expander 2 memory
port MOV R, #data Move immediate to 2 2
ORLD P,A Or A to expander 2 register
port MOV @R, #data Move immediate to 2 2
data memory
REGISTERS
MOVA,PSW MovePSWtoA
INCR Increment register MOVPSW,A MoveAtoPSW
INC@R Increment data XCHA, R Exchange A and
memory register
DECR Decrement register XCHA,@R Exchange A and
BRANCH data memory
JMPaddr Jump unconditional 2 2 XCHDA,@R Exchange nibble
JMPP@A Jump indirect 1 2 of A and register
DJNZ R, addr Decrement register 2 2 MOVXA,@R Move external 2
and skip data memory to A
JCaddr Jump on carry = 1 2 2 MOVX@R,A Move A to external 2
JNCaddr Jump on carry = 0 2 2 data memory
JZ addr Jump on A zero 2 2 MOVPA,@A Move to A from 2
JNZaddr Jump on A not zero 2 2 current page
JTO addr Jump on TO = 1 2 2 MOVP3A,@A Move to A from 2
JNTOaddr Jump on TO = 0 2 2 page 3
JTl addr JumponTl = 1 2 2
TIMER/COUNTER
JNTI addr JumponTl = 0 2 2
MOVA,T Read
JFO addr Jump on FO = 1 2 2
timer I counter
JFl addr Jump on Fl = 1 2 2
MOVT, A Load
JTF addr Jump on timer flag 2 2
timer/counter
JNI addr Jump on INT = 0 2 2 STRTT Start timer
JBb addr Jump on 2 2 STRTCNT Start counter
accumulator bit STOP TCNT Stop timer/counter
EN TCNTI Enable timerl
SUBROUTINE counter interrupt
CALLaddr Jump to subroutine 2 2 DIS TCNTI Disable timer I
RET Return 2 counter interrupt
RETR Return and restore 2
CONTROL
status
ENI Enable external
interrupt
FLAGS DISI Disable external
CLRC Clear carry inferrupt
CPLC Complement carry SELR.BO Select register
CLR FO Clear flag 0 bank 0
CPLFO Complement flag 0 SELRBI Select register
CLR Fl Clear flag 1 bank 1
CPLFI Complement flag 1 SELMBO Select memory
DATA MOVES bank 0
MOVA,R Move register to A SELMBI Select memory
MOVA,@R Move data memory bank 1
toA ENTOCLK Enable clock
MOVA, #data Move immediate 2 2 output on TO
toA NOP No operation
4-24
087 48H/087 49H
ABSOLUTE MAXIMUM RATINGS* NOTICE: This data sheet contains preliminary infor-
mation on new products in production. The specifica-
Ambient Temperature Under Bias .... O°C to + 70°C tions are subject to change without notice.
Storage Temperature .......... -65°C to + 150°C • WARNING: Stressing the device beyond the "Absolute
Voltage On Any Pin With Respect Maximum Ratings" may cause permanent damage.
to Ground ...................... -0.5V to + 7V These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and ex-
Power Dissipation ....................... 1.0 Watt tended exposure beyond the "Operating Conditions"
may affect device reliability.
D.C. CHARACTERISTICS TA = O°Cto + 70°C', Vee = Voo = 5V +10%'VsS
- = OV
Limits
Symbol Parameter Unit Test Conditions Device
Min Typ Max
VIL, Input Low Voltage (All -0.5 0.8 V All
Except RESET, X1, X2)
VIL1 Input Low Voltage -0.5 0.6 V All
(RESET, X1, X2)
VIH Input High Voltage 2.0 Vee V All
(All Except XTAL 1,
XTAL2, RESET
VIH1 Input High Voltage 3.8 Vee V All
(X1, X2, RESET)
VOL Output Low Voltage (BUS) 0.45 V IOL = 2.0 mA All
VOL1 Output Low Voltage 0.45 V IOL = 1.8 rnA All
(RD, WR, PSEN, ALE)
VOL2 Output Low Voltage 0.45 V IOL = 1.0 mA All
(PROG)
VOL3 Output Low Voltage 0.45 V IOL = 1.6 mA All
(All Other Outputs)
VOH Output High Voltage (BUS) 2.4 V IOH = - 400 /LA All
VOH1 , Output High Voltage 2.4 V IOH = -100 /LA All
(RD, WR, PSEN, ALE)
VOH2 Output High Voltage 2.4 V IOH = -40/LA All
(All Other Outputs)
1L1 Leakage Current ±10 /LA VSS ~ VIN ~ Vee All
(T1, INT)
IU1 Input Leakage Current -500 /LA Vss + 0.45 ~ VIN ~ Vee All
(P1 0-P17, P20-P27,
EA, SS)
IU2 Input Leakage Current -10 -300 /LA VSS ~ VIN ~ 3.8V All
RESET
ILO Leakage Current ±10 /LA Vss ~ VIN ~ Vee All
(BUS, TO) (High
Impedance State)
100 + lee Total Supply Current' 80 100 mA 8748H
95 110 mA 8749H
NOTE:
'Icc + 100 is measured with all outputs disconnected; S8, RESET, and INT equal to Vee; EA equal to Vss.
4-25
inter D8748H/D8749H
A.C. CHARACTERISTICS TA = O·Cto +70·C;Vcc = voo = 5V ±10%;Vss =, ov
f(t) 11 MHz Conditions
Symbol Parameter Unit
(Note 3) Min Max (Note 1)
t Clock Period 1 /xtal freq 90.9 1000 ns (Note 3)
tLL ALE Pulse Width 3.5t - 170 150 ns
tAL Addr Setup to ALE 2t - 110 70 ns (Note 2)
tLA Addr Hold from ALE t - 40 50 ns
tCCl Control Pulse Width (RD, WR) 7.5t - 200 480 ns
tCC2 Control Pulse Width (PSEN) 6t - 200 350 ns
tow Data Setup before WR 6.5t - 200 390 ns
two Data Hold after WR t - 50 40 ns
tOR Data Hold (RD, PSEN) 1.5t - 30 0 110 ns
tROl RD to Data In 6t - 170 375 ns
tR02 PSEN to Data In 4.5t - 170 240 ns
tAW Addr Setup to WR 5t - 150 300 ns
tAOl Addr Setup to Data (RD) 10.5t - 220 730 ns
tA02 Addr Setup to Data (PSEN) 7.5t - 200 460 ns
tAFCl Addr Float to RD, WR 2t - 40 140 ns (Note 2)
tAFC2 Addr Float to PSEN 0.5t - 40 10 ns (Note 2)
tLAFCl ALE to Control (RD, WR) 3t- 75 200 ns
tLAFC2 ALE to Control (PSEN) 1.5t - 75 60 ns
tCAl Control to ALE (RD, WR, PROG) t - 65 25 ns
tCA2 Control to ALE (PSEN) 4t - 70 290 ns
tcp Port Control Setup to PROG 1.5t - 80 50 ns
tpc Port Control Hold to PROG 4t - 260 100 ns
tpR PROG to P2 Input Valid 8.5t - 120 650 ns
tpF Input Data Hold from PROG 1.5t 0 140. ns
top Output Data Setup 6t - 290 250 ns
tpo Output Data Hold 1.5t - 90 40 ns
tpp PROG Pulse Width 10.5t - 250 700 ns
tpL Port 2 I/O Setup to ALE 4t - 200 160 ns
tLP Port 2 110 Hold to ALE 0.5t - 3Q 15 ns
tpv Port Output from ALE 4.5t + 100 510 ns
tOPRR TO Rep Rate 3t 270 ns
tCY Cycle Time 15t 1.36 15.0 JLs
NOTES:
1. Control outputs CL = 80 pF; BUS outputs CL = 150 pF.
2. BUS High Impedance Load 20 pF.
3. I(t) assumes 50% duty cycle on Xl, X2. Max clock period is lor a 1 MHz crystal input.
4-26
087 48H/087 49H
WAVEFORMS
INSTRUCTION FETCH FROM PROGRAM
MEMORY WRITE TO EXTERNAL DATA MEMORY
I- ICy
I - ILL -IILAFC2i
'I
ALE. J L________~I~--~L .
ALE J L
IAFd2 1- ---I I-
ICC2 ICA2
WR
PSEN
ADDRESS
210983-6
210983-4
READ FROM EXTERNAL DATA MEMORY INPUT AND OUTPUT FOR A.C. TESTS
-.jILAFC1L
ALE Jr------,IL _....:'_ _ _ _- ' l 2.4V - - - - - - , ,..-_ __
ICA11- 0.45V---~. .O.S'"
X 2.0 ,. TEST POINTS ~2.0X
"'O.S. '-._ __
RD
210963-7
A.C. testing inputs are driven at 2.4V for a Logic "1" and 0.45V
for a Logic "0". Output timing measurements are made at 2.0V
for a Logic "1" and 0.8V for a Logic "0."
210983-5
4-27
inter D8748H/D8749H
PORT 1/PORT 2 TIMING
ALE
PSEN
P20-23
r---~--------~I,-----~--------,
I
PORT 20-23 DATA NEW P20-23 DATA
OUTPUT PCH ~ ____________ -JII PCH
P24-27 -r--~I------------~--~--~
P10-17 PORT 24-27, PORT 10-17 DATA NEW PORT DATA
I
OUTPUT
I ---l I - t_CA1
~ -tPL~
tLP
ItPD
EXPANDER
PORT
tAL--,.I.----tLA---O+!...
,top TO'
OUTPUT ~
PCH
______ _ _ _ _ _ _ _ _- J
I rp-O-R-T-20-_-23-D-A-T-A~1 IpORTCONTROL OUTPUT DATAl
I II
EXPANDER
PORT I II 1-1·--tPR--+l
r----------,.
INPUT PCH PORT 20-23 DATAl IPORT C9NTROL I
I-tcP+tPc~ I
r---
I
PROG
------------.;1
~'-----~'j
tPP -1;--- .
210983-8
CRYSTAL OSCILLATOR MODE CERAMIC RESONATOR MODE
C1
t----_--,----_ _-,--_---j2 XTAL 1
5~ ,·f·, TJ;~~ C1
2
f------r---=--t
~ I<~"~"~f
XTAL1
a
-l- LI-----'-i------!----c-I3 XTAL2
C3
210983-9 XTAL2
3
C3
C1 ~ 5 pF ±% pF + (STRAY < 5 pF)
C2 ~ (CRYSTAL + STRAY) < 8 pF 210983-10
C3 ~ 20pF ±1 pF(STRAY < 5pF)
Crystal series resistance should be less than 300 at 11 MHz; less
than 750 at 6 MHz; less than 1800 at 3.6 MHz.
4-28
inter D8748H/D8749H
DRIVING FROM EXTERNAL SOURCE WARNING
An attempt to program a missocketed 8749H
+5V
(8748H) will result in severe damage to the part. An
47011 indication of a properly socketed part is the appear-
}>--+---- XTAL 1
ance of the ALE clock output. The lack of this clock
+5V may be used to disable the programmer.
TTL OPEN
COLLECTOR
GATES
47011 The Program/Verify sequence is:
~---'~~ XTAL2 1) Voo = 5V, Clock applied or internal oscillator op-
210983-11
erating. RESET = OV, TEST 0 = 5V, EA = 5V,
For XTAL 1 and XTAL2 define "high" as voltages above 1.6V and BUS and PROG floating. P10 and P11 must be
"low" as voltages below 1.6V. The duty cycle requirements for tied to ground.
externally driving XTAL 1 and XTAL2 using the circuit shown
above are as follows: XTAL 1 must be high 35-65% of the period 2) Insert 8749H (8748H) in programming socket.
and XTAL2 must be high 36-65% of the period. Rise and fall "-
times must be faster than 20 ns.
3) TEST 0 = OV (select program mode)
4) EA = 18V (activate program mode)
5) Address applied to BUS and P20-22
PROGRAMMING, VERIFYING AND 6) RESET = 5V (latch address)
ERASING THE 8749H (8748H) EPROM 7) Data applied to BUS
8) Voo = 21V (programming power)
Programming Verification 9) PROG = Vee or float followed by one 50 ms
pulse to 18V
In brief, the programming process consists of: acti-
10) Voo = 5V
vating the program mode, applying an address,
latching the address, applying data, and applying a 11) TEST 0 = 5V (verify mode)
programming pulse. Each word is programmed com- 12) Read and verify data on BUS
pletely before moving on to the next and is followed 13) TEST 0 = OV
by a verification step. The following is a list of the
pins used for programming and a description of their 14) RESET = OV and repeat from step 5
functions: 15) Programmer should be at conditions of step 1
when 8749H (8748H)is removed from socket.
Pin Function
XTAL1 Clock Input (3 to 4.0 MHz)
XTAL2
RESET Initialization and Address Latching
TEST 0 Selection of Program or Verify Mode
EA Activation of Program/Verify Modes
BUS Address and Data Input
Data Output During Verify
P20-P22 Address Input
Voo Programming Power Supply
PROG Program Pulse Input
4-29
inter D8748H/D8749H
A.C. TIMING SPECIFICATION FOR PROGRAMMING 8748H/8749H
TA = 25'C ±5'C; vcc = 5V ±5%; voo = 21V ±0.5V
Symbol Parameter Min Max Unit Test Conditions
tAW Address Setup Time to RESET i 4tCY
tWA Address Hold Time after RESET i 4tCY
tow Data in Setup Time to PROG i 4tCY
two Data in Hold Time after PROG J., 4tCY
tpH RESET Hold Time to Verify 4tCY
tvoow Voo Hold Time before PROG i 0 1.0 ms
tVOOH Voo Hold Time after PROG J., 0 1.0 ms
tpw Program Pulse Width 50 60 ms
trw TEST 0 Setup Time for Program Mode 4tCY
tWT TEST 0 Hold Time after Program Mode 4tCY
too TEST 0 to Data Out Delay 4tCY
tww RESET Pulse Width to Latch Address 4tCY
t r, tf Voo and PROG Rise and Fall Times 0.5 100 /_tS
tCY CPU Operation Cycle Time 3.75 5 f-ls
tRE RESET Setup Time before EA i 4tCY
NOTE:
If TEST a is high, too can be triggered by RESET i.
D.C. SPECIFICATION FOR PROGRAMMING 8748H/8749H
TA = 25'C ±5'C; Vcc = 5V ±5%; Voo = 21V ±0.5V
Symbol Parameter Min Max Unit Test Conditions
VOOH VOO Program Voltage High Level 20.5 21.5 V
VOOL VOO Voltage Low Level 4.75 5.25 V
VPH PROG Program Voltage High .Level 17.5 18.5 V
VPL PROG Voltage Low Level 4.0 Vcc V
VEAH EA Program or Verify Voltage High Level 17.5 18.5 V
100 VDD High Voltage Supply Current 20.0 mA·
IpROG PROG High Voltage Supply Current 1.0 mA
lEA EA High Voltage Supply Current 1.0 mA
4-30
inter D8748H/D8749H
WAVEFORMS
COMBINATION PROGRAM/VERIFY MODE (EPROMs ONLY)
VEAH
EA
Vee
I-------PROGRAM -------f----VERIFY----I----PROGRAM-
ITW-I
Vee
TO
VIL1
Vee
RESET
VIL1
IAW+I-'---+-~+-I IWA
~ r-~D~A=TA~T=O~B=E--~
DBo-DB7 --F - - PROGRAMMED VALID
__ -{NEXT ADDRX=
VALID
LAST NEXT
ADDRESS ADDRESS
VDDH
tyD~W~
_ _ _ _ _ ___ tpw IVDDH
IWT
VDD
,~2~~~~~~-----------------~-D-~LV ~J-~-:-_-_-_--_--_-_---_--_-_-_-_-_--_-_-_-_-_-.
210983-12
VERIFY MODE
\~-----I/ \-----
DBO-DB7 =:)--- ADDRESS
(0-7) VALID
J NEXT X
- - ' , -__A_D_D_R_E..;;,SS,;........J
NEXT DATA
OUT VALID
>-
____-J)('-.;.....___ A_D_D_RE_S_S_(_8-_9_)V_A_L_ID_ _ _ -I)(~_______N_E_X_T_A_D_D_R_E_SS_V_A_L_ID______
210983-13
4-31
D8748H/D8749H
SUGGESTED EPROM VERIFICATION ALGORITHM FOR HMOS-E DEVICE ONLY
·INmAL EPROM DUMP CYCLE SUBSEQUENT EPROM DUMP CYCLES
ALE
(NOTE 1) : (OUTPUT)
I
EA -=:J I
I
: (INPUT)
I
I
I I
I I
I
DB------;L__ A_D~D~R~E~SS--..J~rR~O~M~D~A~TA~~r--7AD~D~R~E~S~S--'~~______________
(INPrU_T_)______
(O_U_T_P_UT_)..,: (INPUT) (OUTPUT):
TO, RESET - - - - - - - - - - - - ' !
I
I
(INPUT) ~!---------------
I
P20-P23 ______ i._______A_D_D_R_E_SS______....... H'--_____
I
AD_D_R_E_S_S____- - I t - - - - - - - - -
: (INPUT)
210983-14
48H 49H Vee - Voo - +SV
Vss - OV
A10 0 AD DR
A11 o o
NOTE:
ALE is function of Xl, X2 inputs.
4-32
P8049KB
HMOS SINGLE-COMPONENT 8-BIT
MICROCONTROLLER
• Interval
Four 10 mA LED Drivers
• Easily Expandable Memory and I/O
• Two Single
Time/Event Counter
• 1.87 /-Ls Instruction Cycle
1 to 8 MHz Operation
• Single 5V Supply
Level Interrupts
• 1 or 2 Cycle' Instructions
• Over 96 Instructions •
• • 2K128xx88ROM
• RAM
The Intel 8049KB is a totally self-sufficient, 8-bit parallel compl.lter fabricated on a single silicon chip using
Intel's advanced N-channel silicon gate HMOS process. This microcontroller is ~vailable in the masked ROM
version and runs at a maximum XTAL frequency of 8 MHz.
This microcomputer is designed to be an efficient controller as well as arithmetic processor. It has extensive
bit handling capability as well as facilities for both binary and BCD arithmetic. Efficient use of program memory
results from an instruction set consisting of mostly single byte instructions and no instruction over 2 bytes in
length.
PORT
I
PORT
RESET P80"9KB 2
SINGLE
STEP
READ
WRITE
PROGRA.M
STORE
ENABLE
INTERRUPT ADDRESS
LATCH
ENABLE
BU~
PORT
EXPANDER
STROBE
270790-1
Figure 1. Block Diagram 270790-2
Figure 2. Logic Symbol
February .1990
4-33 Order Number: 270790-002
intJ P8049KB
TO VCC
XTAL 1 Tl
XTAL 2 P27
RESET P26
S5 P2S
INT P24
EA P17
AD P16
PSEN P1S
, WR P14
ALE P13
DBO P12
DBl Pl1
DB2 Pl0
DB3 VDD
DB4 PROG
DBS P23
, DBS P22
DB7 P21
VSS P20
270790-12
Pin Configuration
Table 1. Pin Description
Pin
Symbol Function
No.
VSS '20 Circuit GND potential.
Voo 26 + 5V during normal operation.
low power standby pin.
Programming power supply (+ 21 V).
Vee 40 Main power supply; + 5V during operation and programming.
P10-P17 27-34 8-bit quasi-bidirectional port.
Port 1
P20-P23 21-24 8-bit quasi-bidirectional port. P20-P23 contain the four high order program
P24-P27 35-38 counter bits during an external program memory fetch and serve as a 4-bit
Port 2 1/0 expander bus for 8243.
DBO-DB7 12-19 True bidirectional port which can be written or read synchronously using the
BUS RD, WR strobes. The port can also be statically latched. Contains the 8 low
order program counter bits during an external program memory fetch, and·
receives the addressed instruction under the control of PSEN. Also contains
the address and data du!:!!!g an external RAM data store instruction, under
control of ALE, RD, and WR.
TO 1 Input pin testable using the conditional transfer instruction JTO and JNTO. TO
can be designated as a clock output using ENTO ClK instruction.
Used during programming.
infef PB049KB
Table 1. Pin Description (Continued)
Pin
Symbol Function
No.
T1 39 Input pin testable using the JT1. and JNT1 instructions. Can be designated
the timer/counter input using the STRT CNT instruction.
INT 6 Interrupt input. Initiates an interrupt if interrupt is enabled. Interrupt is
disabled after a reset. Also testable with conditional jump instruction. (Active
. low) interrupt must remain low for at least 3 machine cycles for proper
operation.
RD 8 Output strobe activated during a BUS read. Can be used to enable data onto
the bus from an external device.
Used as a read strobe to external data memory. (Active low)
RESET 4 Input which is used to initialize the processor. (Active low) (Non TIL VIH)
Used during power down.
Used during programming.
Used during ROM verification.
WR 10 Output strobe during a bus write. (Active low)
Used as write strobe to external data memory.
ALE 11 Address latch enable. This signal occurs once during each cycle and is
useful as a clock output.
The negative edge of ALE strobes address into external data and program
memory.
PSEN 9 Program store enable. This output occurs only during a fetch to external
program memory. (Active low)
SS 5 Single step input can be used in conjunction with ALE to "single step" the
processor through each instruction.
(Active low) Used in sync mode.
EA 7 External access input which forces all program memory fetches to reference
external memory. Useful for emulation and debug. (Active high)
Used during (18V) programming.
Used during ROM verification (12V).
XTAL1 2 One side Of crystal input for internal oscillator. Also input for external source.
(NonTILVIH)
XTAL2 3 Other side of crystal input.
4-35
intJ P8049KB
Table 2. Instruction Set
.------------------------------, .------------------------------,
Accumulator Input/Output
Mnemonic Description Bytes Cycles Mnemonic Description Bytes Cycles
ADDA, R Add register to A 1 1 INA, P Input port to A 1 2
ADDA, @R Add data memory OUTLP, A Output A to port 1 2
toA ANL P, #data And immediate to 2 2
ADD A, #data Add immediate to A 2 2 port
ADDC A, R Add register with ORL P, #data Or immediate to 2 2
carry port
ADDC A, @R. Add data memory INSA, BUS Input BUS to A 1 2
with carry OUTLBUS, A Output A to BUS 1 2
ADDC A, #data Add immediate with 2 2 ANL BUS, #data And immediate to 2 2
carry BUS
ANL A, R And register to A ORL BUS, #data Or immediate to 2 2
ANL A, @R And data memory BUS
toA MOVDA,P Input expander port 2
ANLA, #data And immediate to A 2 2 toA
ORLA, R Or register to A 1 1 MOVDP,A Output A to 2
ORLA, @R Or data memory expander port
toA ANLD P,A And A to expander 2
ORLA, #data Or immediate to A 2 2 port
XRLA, R Exclusive or register 1 ORLD P,A Or A to expander 2
toA port
XRLA, @R Exclusive or data
memory to A
XRLA, #data Exclusive or 2 2 Registers
immediate to A
Mnemonic Description Bytes Cycles
INCA Increment A
DECA Decrement A INCR Increment register 1 1
CLRA Clear A INC@R Increment data memory 1 1
CPLA Complement A DECR Decrement register
DAA Decimal adjust A
SWAP A Swap nibbles of A Branch
RLA Rotate A left
RLCA Rotate A left Mnemonic Description Bytes Cycles
through carry
JMP addr Jump unconditional 2 2
RRA Rotate A right
JMPP@A Jump indirect 1 2
RRCA Rotate A right DJNZ R, addr Decrement register 2 2
through carry
and skip
JC addr Jump on carry = 1 2 2
JNC addr Jump on carry = 0 2 2
JZ addr Jump on A zero 2 2
JNZ addr Jump on A not zero 2 2
JTO addr Jump on TO = 1 2 2
JNTO addr Jump on TO = 0 2 2
JT1 addr Jump on T1 = 1 2 2
JNT1 addr Jump on T1. = 0 2 2
JFO addr Jump on FO = 1 2 2
JF1 addr Jump on F1 = 1 2 2
JTF addr Jump on timer flag 2 2
JNI addr Jump on INT = 0 2 2
JBb addr Jump on accumulator 2 2
bit
4-36
P8049KB
Table 2. Instruction Set (Continued)
r---------------------------------~ r--------------------------------~
Subroutine Timer/Counter
Mnemonic Description Bytes Cycles Mnemonic Description Bytes Cycles
CALL addr Jump to subroutine 2 2 MOVA, T Read timer/counter 1 1
RET Return 1 2 MOVT,A Load timer/counter 1 1
RETR Return and restore 1 2 STRTT Start timer 1 1
status STRTCNT Start counter 1 1
STOP TCNT Stop timer/counter 1 1
EN TCNTI Enable timer/ 1 1
Flags counter interrupt
DIS TCNTI Disable timer/
Mnemonic Description Bytes Cycles counter interrupt
CLRC Clear carry 1 1
CPLC Complement carry 1 1
Control
CLRFO Clear flag 0 1 1
CPLFO Complement flag 0 1 1
Mnemonic Description Bytes Cycles
CLR F1 Clear flag 1 1 1
CPL F1 Complement flag 1 1 1 EN I Enable external 1 1
interrupt
DISI Disable external
Data Moves interrupt
Mnemonic Description Bytes Cycles SEL RBO Select register bank 0
SEL RB1 Select register bank 1
MOVA, R Move register to A 1 1 SEL MBO Select memory bank 0
MOVA,@R Move data memory 1 1 Select memory bank 1
SEL MB1
toA
ENTO CLK Enable clock output
MOV A, #data Move immediate to 2 2
A onTO
MOVR,A Move A to register
MOV@R,A Move A to data Mnemonic Description Bytes Cycles
memory
MOV R, #data Move immediate to 2 2 NOP No operation 1 1
register
MOV @R, #data Move immediate to 2 2
data memory
MOVA, PSW Move PSWtoA
MOVPSW,A Move A to PSW
XCH A, R Exchange A and
register
XCH A, @R Exchange A and
data memory
XCHDA,@R Exchange nibble of
A and data memory
MOVXA,@R Move external data 2
memory to A
MOVX@R,A Move A to external 2
data memory
MOVPA,@A Move to A from 2
current page
MOVP3A,@A Move to A from 2
page 3
4-37
P8049KB
ABSOLUTE MAXIMUM RATINGS* NOTICE: This data sheet contains preliminary infor-
mation on new products in production. The specifica-
Gase Temperature Under Bias ....... O·G to + 70·C . tions are subject to change without notice.
Storage Temperature .......... - 65·C to + 150·C • WARNING: Stressing the device beyond the "Absolute
Voltage on any Pin with Respect Maximum Ratings" may cause permanent damage.
to Ground ...................... - 0.5V to + 7V These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and ex-
Power Dissipation .......................... 1.5W tended exposure beyond the "Operating Conditions"
may affect device reliability.
D.C. CHARACTERISTICS TA = O·Cto +70·C;Vee = VDD = 5V ±10%;Vss = ov
Limits
Symbol Parameter Unit Test Conditions
Min Typ Max
VIL Input Low Voltage (All -0.5 0.8 V
Except RESET, X1, X2).
VIL1 Input Low Voltage -0.5 0.6 V
(RESET, X1, X2)
VIH Input High Voltage 2.0 Vee V
(All Except XTAL 1,
XTAL2, RESET)
VIH1 Input High Voltage 3.8 Vee V
(X1, X2, RESET)
VOL Output Low Voltage 0.45 V IOL = 2.0mA
(BUS)
VOL1 Output LowVoltage 0.45 V IOL = 1.8 mA
(RD, WR, PSEN, ALE)
VOL2 Output Low Voltage 0.45 V IOL = 1.0 mA
(PROG)
VOL3 Output Low Voltage 0.45 V IOL = 1.6 mA
(All Other Outputs)
VOL4 Output Low Voltage 0.45 V IOL = 10 mA
(Any Four Port Outputs)
VOH Output High Voltage 2.4 V IOH = -400/LA
(BUS)
VOH1 Output High Voltage 2.4 V IOH = -100 /LA
(RD, WR, PSEN, ALE)
VOH2 Output High Voltage 2.4 V IOH = -40/LA
(All Other Outputs)
4-38
inter P8049KB
D.C. CHARACTERISTICS TA = O·C to + 70·C; Vee = Voo = 5V ± 10%; Vss = OV (Continued)
Limits
Symbol Parameter Unit Test Conditions
Min Typ Max
1L1 Leakage Current ±10 JlA VSS s: VIN s: Vee
(T1, INT)
IU1 Input Leakage Current -500 JlA Vss + 0.45S: VIN s: Vee
(P10-P17, P20-P27,
EA, SS)
IU2 Input Leakage Current -10 -300 JlA VSS s: VIN s: 3.8
RESET
ILO Leakage Current ±10 JlA Vss s: VIN s: Vee
(BUS, TO) (High
Impedance State)
100 Voo Supply Current 3 5 rnA
(RAM Standby)
4 7 rnA
5 10 rnA
100 + . Total Supply Current· 30 65 rnA
lee 35 70 rnA
40 80 rnA
30 100 rnA
50 110 rnA
Voo RAM Standby Voltage 2.2 5.5 V Standby Mode Reset s: VIL 1
2.2 5.5 V
2.2 5.5 V
"Icc + 100 are measured with all outputs in their high impedance state; RESET low; 8 MHz crystal applied; IN'f, ss, and EA
floating.
tAny four Port Outputs can be loaded to a 10 mA maximum. Excessive heating and dissipation will result if more than four
outputs are loaded to 10 mA.
4-39
intJ P8049KB
A.C. CHARACTERISTICS TA = O·Cto +70·C;Vcc = voo = 5V±10%;Vss = ov
f (t) 8 MHz Conditions
Symbol Parameter Unit
(Note 3) Min Max (Note 1)
t Clock Period 1/xtal freq 125 1000 ns (Note 3)
tLL ALE Pulse Width , 3.5t-'-170 268 ns
tAL Addr Setup to ALE 2t-110 140 ns (Note 2)
tLA Addr Hold from ALE t-40 85 ns
tCC1 ' Control Pulse Width (RD, WR) 7.5t-200 675 ns
tCC2 Control Pulse Width (PSEN) 6t:-200 550 ns
tow Data Setup before WR 6.5t-200 613 ns
two' Data Hold after WR t-50 75 ns
tOR Data Hold (RD, PSEN) 1.5t-30 0 158 ns
tR01 RDto Data in 6t-170 580 ns
tRo2 PSEN to Data in 4.5t-170 393 ns
tAW Addr Setup to WR 5t-150 475 ns
tA01 Addr Setup to Data (RD) 10.5t-220 1093 ns
tAo2 Addr Setup to Data (PSEN) 7.5t-200 738 ns
tAFC1 Addr Float to RD, WR 2t-40 210 ns (Note 2)
tAFC2 Addr I=loat to PSEN 0.5t-40 23 ns (Note 2)
tLAFC1 ALE to Contro,1 (RD, WR) 3t-75 300 ns
tLAFC2 ALE to Control (PSEN) 1.5t-75 113 ns
tCA1 Control to ALE (RD, WR, PROG) t-65 60 ns
tCA2 Control to ALE (PSEN) 4t-70 430 ns
tcp Port Control Setup to PROG 1.5t-80 108 ns
tpc Port Control Hold to PROG 4t-260 240 ns
tpR PROG to P2 Input Valid 8.5t-120 943 ns
tpF Input Data Hold from PROG 1.5t 0 188 ns
top Output Data Setup 6t-290 460 ns
tpo Output Data Hold 1.5t-90 98 ns
tpp PROG Pulse Width 10.5t-250 1063 ns
tpL' Port 2 I/O Setup to ALE 4t-200 300 ns
tLP Port 2 I/O Hold to ALE 0.5t-30 33 ns
tpv Port Output from ALE 4.5t+ 100 663 ns
tOPRR TO Rep Rate 3t 375 ns
tCY Cycle Time 15t 1.87 28 p,s
NOTES:
1. Control outputs: CL = 80 pF. BUS Outputs: CL = 150 pF.
2. BUS High Impedance Load 20 pF
3. I(t) assumes 50% duty cycle on X1, X2. Max clock period is for a 1 MHz crystal input.
4-40
inter P8049KB
WAVEFORMS
INSTRUCTION FETCH FROM PROGRAM READ FROM EXTERNAL DATA MEMORY
MEMORY
ALE
--.1 .lAFC'i--
RO
270790-4
270790-3
WRITE TO EXTERNAL DATA MEMORY INPUT AND OUTPUT FOR A_C. TESTS
2.4V - - - - , .
X
2.0 ... TEST POINTS ... 2.0
D.4SV _ _ _...J. ,0.8.... "'0.8.
x==
270790-6
A.C. testing inputs are driven at 2.4V for a logic "1" and 0.45V for
a logic "0". Output timing measurements are made at 2.0V for a
logic "1" and 0.8V for a logic "0".
270790-5
PORT 1/PORT 2 TIMING
2ND
CYCLE
ALE
PSEN
P20-23 ,
OUTPUT PCH P,?RT 20-23 DATA NEW P20-23 DATA I PCH
P24~27
-+____~------------------~------___ L------------JI
P10-17 PORT 24-27. PORT 10-17 DATA NEW PORT 9ATA
OUTPUT
'lP
..'-
I f-'CA'
EXPANDER
PORT
-t----.• lA--~'+I i,op---n
OUTPUT
I r------'-
PCH
~--------~I ~ __ --J
EXPANDER
PORT I
INPUT PCH
I-.CP+'PC~ I I
PROG ------------:~~.PP_v____
270790-7
4-41
inter P8049KB
CRYSTAL OSCILLATOR MODE CERAMIC RESONATOR MODE
Cl Cl
'- 4_:;_~_!_ _ :2:_ 1ITALl
1 - -____-,-_ _--1
2 ITALl
-1 L,
_ILC_2_--'-L_-_ _
C3
3
XTAL2
270790-8
J I<~'-'~f'
C3
3
XTAU
270790-9
C1 = 5 pF ±y. pF + (STRAY < 5 pF)
C2 = (CRYSTAL + STAY) < 8 pF
C3 = 20 pF ±I pF + (STRAY < 5 pF)
Crystal series resistance should be less than son at 8 MHz; less
than 75n at 6 MHz; less than 180n at 3.6 MHz.
DRIVING FROM EXTERNAL SOURCE
>5V
47011
1-.-------1 XTALI
'5V
TTL OPEN
COLLECTOR
GATES 47011
L....._-'---_-;;-j XTAU
270790-10
For XTAL1 and XTAL2 deli.ne "high" as voltages above 1.6V end
"low" as voltages below 1.6V. The duty cycle requirements lor
externally driving XTAL1 and XTAL2 using the circuits shown
above are as lollows: XT AL 1 must be high 35-65% 01 the period
and XTAL2 must be high 35-65% 01 the period. Rise and lall times
must be laster than 20 ns.
4-42
infef P8049KB
VERIFYING THE 8049KB ROM WARNING:
An indication of a properly socketed part is the ap-
Programming Verification pearance of the ALE clock output. The lack of this
clock may be used to disable the programmer.
The following is a list of the pins used for verification
and a description of their functions: The Verify sequence is:
1. VDD = 5V, Clock applied or internal oscillator op-
Pin Function erating, RESET = OV, EA = 5V, BUS floating.
XTAL1 Clock Input (3 to 4.0 MHz) 2. Insert 8049KB in verify socket
XTAL2 3, EA = 12V (activate verify mode)
RESET Initialization and Address Latching 4. Address applied to BUS and P20-23
TO Selection of Program or Verifying Mode 5. RESET = 5V (latch address)
EA Activation Verify Modes
6. Read and verify Data on BUS
BUS Address and Data Output During Verify
P20-P22 Address Input 7. RESET = OV and repeat from step 4
8. Verify socket should be at conditions of step 1 for
removal from socket.
4-43
P8049KB
SUGGESTED ROM VERIFICATION ALGORITHM FOR ROM DEVICE ONLY
INITIAL ROM DUMP CYCLE SUBSEQUENT ROM DUMP CYCLES
ALE
(NOTE1) !(OUTPUT)
-12V I I
EA----.J : (INPUT)
DB--_"1._ _
A."DD."R","E"",S""S_...IH ROM DATA HL__A_D_D_R_E_SS_....J~r---------
(INPUT) (OUTPUT) : (INPUT) (OUTPUT):
RESET _ _ _ _ _ _....
I
I
I
(INPUT)
!
P2O,P23 ---1.____A_D_D_R_E_S_S_ _ _----4H. . ___A_D_D_R_E_S_S_ _ _J----------
I (INPUT)
I
270790-11
SOH Vee = VDD = +SV
A10 ADDR VSS = OV
A11 ADDR
NOTE:
ALE is function of X1, X2 inputs.
4-44
MCS®-48
EXPRESS
• O°C to 70°C Operation
• - 40°C to + 85°C Operation
• 168 Hr. Burn-In
• 8049AH/8039AHL • 8748H
8048AH/8035AHL
• 8050AH/8040AHL • 8243
• • 8749H
The new Intel EXPRESS family of single-component 8cbit microcomputers offers enhanced processing options
to the familiar 8048AH/8035AHL, 8748H, 8049AH/8039AHL, 8749H, 8050AH/8040AHL Intel components.
These EXPRESS products are designed to meet the needs of those applications whose operating require-
ments exceed commercial standards, but fall short of military conditions.
The EXPRESS options include the commercial standard and - 40°C to + 85'C operation with or without 168
± 8 hours of dynamic burn-in at 125°C per MIL-STD-883, method 1015. Figure 1 summarizes the option
marking designators and package selections.
For a complete description of 8048AH/8035AHL, 8748H, 8049AH/8309AHL, 8749H, 8040AHL and 8050AH
features and operating characteristics, refer to the respective standard commercial grade data sheet. This
document highlights only the electrical specifications which differ from the respective commercial part.
I Temp Range °C 0-70 -40-+85 0-70 -40-+85
I Burn In o I;Irs o Hrs 168 Hrs 168 Hrs
P8048AH TP8048AH QP8048AH LP8048AH
D8048AH TD8048AH QD8048AH LD8048AH
D8748H TD8748H QD8748H LD8748H
P8035AHL TP8035AHL QP8035AHL LP8035AHL
D8035AHL TD8035AHL QD8035AHL LD8035AHL
P8049AH TP8049AH QP8049AH LP8049AH
D8049AH TD8049AH QD8049AH LD8049AH
D8749H TD8749AH QD8749H LD8749AH
P8039AHL TP8039AHL QP8039AHL LP8039AHL
D8039AHL TD8039AHL QD8039AHL LD8039AHL
P8050AH TP8050AH QP8050AH LP8050AH
D8050AH TD8050AH QD8050AH LD8050AH
P8040AHL TP8040AHL QP8040AHL LP8040AHL
D8040AHL TD8040AHL QD8040AHL LD8040AHL
P8243 TP8243 QP8243 -
D8243 TD8243 QD8243 LD8243
.. Commercial Grade
P Plastic Package
D Cerdip Package
September 1987
4-45 Order Number: 270225-002
inter MCS®-48 EXPRESS
Extended Temperature Electrical Specification Deviations'
TP8048AH/TP8035AHL/LP8048AH/LP8035AHL
TD8048AH/TD8035AHL/LD8048AH/LD8035AHL
D.C. CHARACTERISTICS TA = -40°C to +85°C;Vec = Voo = 5V ±10%;Vss = OV
Limits
Symbol Parameter Unit Test Conditions
Min Typ Max
VIH Input High Voltage (All Except 2.2 Vee V
XT AL 1, XTAL2, RESET)
100 Voo Supply Current 4 8 mA
100 + lee Total Supply Current 40 80 mA
TP8049AH/TP8039AHLlLP8049AH/LP8039AHL
TD8049AH/TD8039AHL/LD8049AH/LD8039AHL
D.C. CHARACTERISTICS TA = -40°C to + 85°C; Vee = Voo = 5V ±10%;Vss = OV
Limits
Symbol Parameter Unit Test Conditions
Min Typ Max
VIH Input High Voltage (All Except 2.2 Vee V
XTAL 1, XTAL2, RESET)
100 Voo Supply Current 5 10 mA
100 + Ice Total Supply Current 50 100 mA
TP8050AH/TP8040AHL/LP8050AHL/LP8040AHL
TD8050AH/TD8040AHL/LD8050AH/LD8040AHL
D.C. CHARACTERISTICS TA = -40°C to + 85°C; Vee = VOD = 5V ± 10%; Vss = OV
Limits
Symbol Parameter Unit Test Conditions
Min Typ Max
VIH Input High Voltage (All Except 2.2 Vee V
XTAL1, XTAL2, RESET)
100 Voo Supply Current 10 20 rnA
100 + Ice Total Supply Current 75 120 rnA
4·46
infef MCS®·48 EXPRESS
Extended Temperature Electrical Specification Deviations'
TD8748H/LD8748H
D.C. CHARACTERISTICS TA = -40°C to + 85°C; Vee = Voo = 5V ±10%;Vss = OV
Limits
Symbol Parameter Unit Test Conditions
Min Typ Max
VIH Input High Voltage (All Except 2.2 Vee' V
XTAL 1, XTAL2, RESET)
100 + lee Total Supply Current 50 130 rnA
TD8749H/LD8749H
D.C. CHARACTERISTICS TA = -40°C to + 85°C; Vee = Voo = 5V ±10%;Vss = OV
Limits
Symbol Parameter Unit Test Conditions
Min Typ Max
VIH Input High Voltage (All Except 2.2 Vee V
XT AL 1, XT AL2, RESET)
100 + lee Total Supply Current 75 150 rnA
TP8743/TD8243/LD8243
D.C. CHARACTERISTICS TA = - 40°C to + 85°C; Vee = 5V ± 10%; Vss = OV
Limits
Symbol Parameter Unit Test Conditions
Min I Typ I Max
lee
..
Vee Supply Current I 15 I
'Refer to indIvIdual commercIal grade data sheet for complete operatIng characteristIcs.
25 rnA
4-47
MCS®-51 Architectural
Overview
5
September 1989
MCS®-51 Family of
Microcontrollers
Architectural Overview
Order Number: 270251-004
5-1
MCS®-51 FAMILY OF CONTENTS PAGE
MICROCONTROLLERS INTRODUCTION ......................... 5-3
ARCHITECTURAL CHMOS Devices ......................... 5-5
OVERVIEW MEMORY ORGANIZATION IN MCS®-51
DEVICES .............................. 5-5
Logical Separation of Program and Data
Memory ................................ 5-5
Program Memory ......................... 5-6
Data Memory ............................. 5-7
THE MCS®-51 INSTRUCTION SET ...... 5-8
Program Status Word ..............•...... 5-8
Addressing Modes ....................... 5-9
Arithmetic Instructions .................... 5-9
Logical Instructions ...................... 5-11
Data Transfers .......................... 5-11
Boolean Instructions .................... 5-13
Jump Instructions ....................... 5-15
CPU TIMING ............................ 5-16
Machine Cycles ......................... 5-17
Interrupt Structure ....................... 5-19
ADDITIONAL REFERENCES ........... 5-21
5-2
MCS®-51 ARCHITECTURAL OVERVIEW
INTRODUCTION
The 8051 is the original member of the MCS®-SI family, and is the core for all MCS-Sl devices. The features of the
8051 core are:
• 8-bit CPU optimized for control applications
• Extensive Boolean processing (single-bit logic) capabilities
• 64K Program Memory address space
.. 64K Data Memory address space
• 4K bytes of on-chip Program Memory
• 128 bytes of on-chip Data RAM
• 32 bidirectional and individually addressable I/O lines
• Two l6-bit timer/counters
• Full duplex UART
• 6-source/S-vcctor interrupt structure with two priority levels
• On-chip clock oscillator
The basic architectural structure of this 8051 core is shown in Figure 1.
EXTERNAL
INTERRUPTS
COUNTER
}
INPUTS
TXD RXD
PO P2 PI P3
ADDRESS/DATA
270251-1
Figure 1. Block Diagram of the 8051 Core
5-3
cl
Each device on the MCS-Sl family consists of all the core features plus some additional features. A feature comparison of all the MCS-Sl devices is shown in
Table I.
Table 1. The MCS®-S1 Family of Microcontrollers s:::
Programmable Serial Global
oen
8-Bit 16-Bit Interrupt @l
ROM less EPROM ROM RAM Counter Expansion Serial IDMA AID Power Down I
Device I/O Timer! UART Sources! <11
Version Version Bytes Bytes
Ports Counters
Array Port Channel Channels Channels
Vectors
and Idle Modes .....
(PCA) (SEP) (GSC) ):0
8051 8031 - 4K 128 4 2 6/5 ::u
8051AH 8031AH 8751H 4K 128 4 2
" 6/5
o
:::t
8751BH " =i
m
01
.;,.. 8052AH 8032AH 8752BH 8K 256 4 3
" 8/6
~
80C51BH 80C31BH 87C51 4K 128 4 2 6/5 c:
80C32 - 8K 256 4 3
" 8/6
" ::u
80C52
83C51FA 80C51FA 87C51FA 8K 256 4 3
" 14/7
" ):0
r
83C51FB 80C51FA 87C51FB 16K 256 4 3
" " 14/7
" o
<
83C152JA 80C152JA - 8K 256 5 2
" " 2 19/11
" m
::u
- 80C152JB - - 256 7 2
" " 2 19/11
" :s
" " " m
83C152JC 80C152JC - 8K 256 5 2
" " 2 19/11
" =E
- 80C152JD - - 256 7 2 2 19!11
80C452 87C452P 8K 256 5 2
"", " 9/8
" I
83C452 _. .. - -- - - --- - - _. - - - - - -
"
MCS®-51 ARCHITECTURAL OVERVIEW
PROGRAM MEMORY DATA MEMORY
(READ ONLY) (READ/WRITE)
r------------------------
FFFFH: . - - -...
---------------------------.
FFFFH:---"
EXTERNAL
EXTERNAL
[;\=0
EXTERNAL
[;\=1
INTERNAL 'Tm'!!r I
L--r-~- 0000 ~"-_ _..J 00 0000 L....,........,.....I
270251-2
Figure 2. MCS®-51 Memory Structure
CHMOS Devices MEMORY ORGANIZATION IN
MCS®-S1 DEVICES
Functional1y, the CHMOS devices (designated with
"C" in the middle of the device name) are all fully
compatible with the 8051, but being CMOS, draw less Logical Separation of Program and
current than an HMOS counterpart. To further exploit Data Memory -
the power savings available in CMOS circuitry, two re-
duced power modes are added: AI1 MCS-51 devices have separate address spaces for
• Software-invoked Idle Mode, during which the CPU Program and Data Memory, as shown in Figure 2. The
is turned off while the RAM and other on-chip logical separation of Program and Data Memory allows
peripherals continue operating. In this mode, cur- the Data Memory to be accessed by 8-bit addresses,
rent draw is reduced to about 15% of the current which can be more quickly stored and manipUlated by
drawn when the device is fully active. an 8-bit CPU. Nevertheless, 16-bit Data Memory ad-
dresses can also be generated through the DPTR regis-
• Software-invoked Power Down Mode, during which ter.
al1 on-chip activities are suspended. The on-chip
RAM continues to hold its data. In this mode the
Program Memory can only be read, not written to.
device typically draws less than 10 /loA.
There can be up to 64K bytes of Program Memory. In
Although the 80C51BH is functional1y compatible with the ROM and EPROM versions of these· devices the
its HMOS counterpart, specific differences between the lowest 4K, 8K or 16K bytes of Program Memory are
two types of devices must be considered in the design of provided on-chip. Refer to Table 1 for the amount of
. an application circuit if one wishes to ensure complete on-chip ROM (or EPROM) on each device. In the
interchangeability between the HMOS and CHMOS ROMless versions al1 Program Memory is external.
devices. These considerations are discussed in the Ap- The read strobe for external Program Memory is the
plication Note AP-252, "Designing with the signal PSEN (Program Store Enable).
80C5lBH".
For more information on the individual devices and
features listed in Table 1, refer to the Hardware De-
scriptions and Data Sheets of the specific device.
5-5
inter MCS®·51 ARCHITECTURAL OVERVIEW
Data Memory occupies a separate address space from The lowest 4K (or 8K or 16K) bytes of Program Mem-
Program Memory. Up to 64K bytes of ex~ernal RAM ory can be either in the on'chip ROM or in an external
can be addressed in the external Data Memor~ace. ROM. This selection is made by strapping the EA (Ex-
The CPU generates read and write signals, RD and ternal Access) pin to either Vee or Vss.
WR, as needed during external Data Memory accesses.
In the 4K byte ROM devices, if the EA pin is strapped
External Program Memory and external Data Memory to Vee, then program fetches ,to addresses OOOOH
may be combined if desired by applying the RD and through OFFFH are directed to the internal ROM. Pro-
PSEN signals to the inputs of an AND gate and using gram fetches to addresses lOOOH through FFFFH are
the output of the gate as the read strobe to the external directed to external ROM.
Program/Data memory.
In the XK byte ROM devices, EA = Vee selects ad-
dresses OOOOH through IFFFH to be internal, and ad-
Program Memory dresses 2000H through FFFFH to be external.
Figure 3 shows a map of the lower part of the Program In the 16K byte ROM devices, EA = Vee selects ad-
Memory. After reset, the CPU begins execution from dresses OOOOH through 3FFFH to be internal, and ad-
location OOOOH. dresses 4000H through FFFFH to be external.
As shown in Figure 3, each interrupt is assigned a fixed If thc EA pin is strapped to Vss, then all program
location in Program Memory. The interrupt causes the fetchcs are directed to external ROM. The ROMless
CPU to jump to that location, where it commences exe- parts must have this pin externally strapped to Vss to
cution of the service routine. External Interrupt 0, for enable them to execute properly.
example, is assigned to location 0OO3H. If External In-
terrupt 0 is going to be used, its· service routine must The read strobe to external ROM, PSEN, is used for all
begin at location 0003H. If the interrupt is not going to external program fetches. PSEN is not activated for in-
be used, its service location is available as general pur- ternal program fetches.
pose Program Memory.
<Il>
MCS -51 EPROM
0028H
0023H LATCH
INTERRUPT
0018H]
P21-_ _ _ _ _ _ _-v1
LOCATIONS
88YTES
0013H
0008H 270251-4
0003H Figure 4. Executing from External
RESET OOOOH
1..-._--' Program Memory
270251-3
The hardware configuration for external program exe-
Figure 3. MCS®·51 Program Memory cution is shown in Figure 4. Note that 16 I/O lines
(Ports 0 and 2) are' dedicated to bus functions during
The interrupt service locations are spaced at 8-byte in- external Program Memory fetches. ~ort 0 (PO in Figure
tervals: 0003H for External Interrupt 0, OOOBH for 4) serves as a multiplexed address/data bus. It emits
Timer 0, 0013H for External Interrupt I, OOIBH for the low byte of the Program Counter (PCL) as an ad-
Timer I, etc. If an interrupt service routine is short dress, and then goes into a float state awaiting the arriv-
enough (as is often the case in control applications), it alof the code byte from the Program Memory. During
can reside entirely within that 8-byte interval. Longer the time that the low byte of the Program Counter is
service routines can use a jump instruction to skip over valid on PO, the signal ALE (Address Latch Enable)
subsequent interrupt locations, if other interrupts are in clocks this byte into an address latch. Meanwhile, Port
use. 2 (P2 in Figure 4) emits the high byte of the Program
Counter (PCH). Then PSEN strobes the EPROM and
the code byte is read into the microcontroller.
5-6
MCS®-S1 ARCHITECTURAL OVERVIEW
Program Memory addresses are always 16 bits wide, Internal Data Memory is mapped in Figure 6. The
even though the actual amount of Program Memory memory space is shown divided into three blocks,
used may be less than 64K bytes. External program which are generally referred to as the Lower 128, the
execution sacrifices two of the 8-bit ports, PO and P2, to Upper 128, and SFR space.
the function of addressing the Program Memory.
Internal Data Memory addresses are always one byte
wide, which implies an address space of only 256 bytes.
Data Memory However, the addressing modes for internal RAM can
in fact accommodate 384 bytes, using a simple trick.
The right half of Figure 2 shows the internal and exter- Direct addresses higher than 7FH access one memory
nal Data Memory spaces available to the MCS-51 user. space, and indirect addresses higher than 7FH access a
different memory space. Thus Figure 6 shows the Up-
Figure 5 shows a hardware configuration for accessing per 128 and SFR space occupying the same block of
up to 2K bytes of external RAM. The CPU in this case addresses, 80Hthrough FFH, although they are physi-
is executing from internal ROM. Port 0 serves as a cally separate entities.
multiplexed address/data bus to the RAM, and 3 lines
of Port 2 are being used to page the RAM. The CPU
generates RD and WR signals as needed during exter- 7FH
nal RAM accesses.
BANK 2FH
SELECT T-ADDRESSABLE SPACE
BITS IN } BI
(B IT ADDRESSES 0-7F)
PSW~ 20H
11( lBH
lFH
17H
10( 4 BANKS OF
10H
B REGISTERS
OFH R0-R7
01 (
OBH
07H t- RESET VALUE OF
00 (
O STACK POINTER
270251-7
270251-5 Figure 7. The Lower 128 Bytes of Internal RAM
Figure 5. Accessing External Data Memory. The Lower 128 bytes of RAM are present in all
If the Program Memory is Internal, the Other MCS-51 devices as mapped in Figure 7. The lowest 32
Bits of P2 are Available as I/O. bytes are grouped into 4 banks of 8 registers. Program
instructions call out these registers as RO through R 7.
There can be up to 64K bytes of external Data Memo- Two bits in the Program Status Word (PSW) select
ry. External Data Memory addresses can be either 1 or which register bank is in use. This allows more efficient
2 bytes wide. One-byte addresses are often used in con- use of code space, since register instructions are shorter
junction with one or more other I/O lines to page the than instructions that use direct addressing.
RAM, as shown in Figure 5. Two-byte addresses can
also be used, in which case the high address byte is
emitted at Port 2. FFH
FFW--------r-----, FFH NO BIT-ADDRESSABLE
: ACCESSIBLE ACCESSIBLE SPACES
UPPER I BY INDIRECT BY DIRECT
128 I ADDRESSING ADDRESSING AVAILABLE AS STACK
SPACE IN DEVICES WITH
80H: ONLY
80H 256 BYTES RAM
7FH
ACCESSIBLE
LOWER \..- SPECIAL } PORTS NOT IMPLEMENTED IN B051
BY DIRECT
FUNCTION STATUS AND
12B AND INDIRECT
REGISTERS CONTROL BITS
ADDRESSING
TIMER
REGISTERS
BOH
STACK POINTER
ACCUMULATOR 270251-8
(ETC.)
270251-6 Figure 8. The Upper 128 Bytes of Internal RAM
Figure 6. Internal Data Memory
5-7
inter MCS®-51 ARCHITECTURAL OVERVIEW
I CY I AC I FO I RSq RSO I ov I I P I
PSW 7
,J L PSW 0
CARRY FLAG RECEIVES CARRY OUT PARITY OF ACCUMULATOR SET
FROM BIT 1 OF ALU OPERANDS BY HARDWARE TO 1 IF IT CONTAINS
AN ODD NUMBER OF 1S, OTHERWISE
IT IS RESET TO 0
PSW 6 PSW 1
AUXILIARY CARRY FLAG RECEIVES USER DEFINABLE FLAG
CARRY OUT FROM BIT 1 OF
ADDITION OPERANDS
PSW 5 PSW 2
GENERAL PURPOSE STATUS FLAG OVERFLOW FLAG SET BY
ARITHMETIC OPERATIONS
PSW 4 PSW 3
REGISTER BANK SELECT BIT 1 REGISTER BANK SELECT BIT 0
270251-10
Figure 10. PSW (Program Status Word) Register in MCS®-S1 Devices
The next 16 bytes above the register banks form a block Sixteen addresses in SFR space are both byte- and bit-
of bit-addressable memory space. The MCS-51 instruc-· addressable. The bit-addressable SFRs are those whose
tion set includes a wide selection of single-bit instruc- address ends in OOOD. The bit addresses in this area are
tions, and the 128 bits in this area can be directly ad- 80H through FFH.
dressed by these instructions. The bit addresses in this
area are DOH through 7FH.
THE MCS®-S1 INSTRUCTION SET
All of the bytes in the Lower 128 can be accessed by
either direct or indirect addressing. The Upper 128 All members of the MeS-51 family execute the same
(Figure 8) can only be accessed by indirect addressing. instruction set. The MCS-51 instruction set is opti-
. The Upper 128 bytes of RAM are not implemented in mized for 8-bit control applications. It provides a vari-
the 8051, but are in the devices with .256 bytes of RAM. ety of fast addressing modes for acceSsing the internal
(See Table I). RAM to facilitate byte operations on small data struc-
tures. The instruction set provides extensive support for
Figure.9 gives a brief look at the Special Function Reg- one-bit variables as a separate data type, allowing direct
ister (SFR) space. SFRs include the Port latches, tim- bit manipulation in control and logic systems that re-
ers, peripheral controls, etc. These registers can only be quire Boolean processing.
accessed by direct addressing. In general, all MCS-51
microcontrollers have the same SFRs as the 8051, and An overview of the MCS-51 instruction set is presented
at the same addresses in SFR space. However, enhance- below, with a brief description of how certain instruc-
ments to the 8051 have additional SFRs that are not tions might be used. References to "the assembler" in
present in the 8051, nor perhaps in other proliferations this discussion are to Intel's MCS-51 Macro Assembler,
of the family. ASM51. More detailed information on the instruction
set can be found in the MCS-51 Macro Assembler Us-
er's Guide (Order No. 9800937 for ISIS Systems, Order
No. 122752 for DOS Systems).
FFH :
: REGISTER-MAPPED PORTS
EOH ACC
0
ADDRESSES THAT END IN
OH OR 8H ARE ALSO
Program Status Word
BIT-ADDRESSABLE
The Program Status Word (PSW) contains several
BOH PORT 3
status bits that reflect the current state of the CPU. The
-PORT PINS
; -ACCUMULATOR PSW, shown in Figure 10, resides in SFR space. It con-
-PSW tains the Carry bit, the Auxiliary'Carry (for BCD oper-
AOH PORT 2 (ETC.)
ations), the two register bank select bits, the Overflow
flag, a Parity bit, and two user-definable status flags.
90H PORT 1
0 The Carry bit, other than serving the functions of a
BOH PORT 0
Carry bit in arithmetic operations, also serves as the
"Accumulator" for a number of Boolean operations.
270251-9
Figure 9. SFR Space
5-8
MCS®-51 ARCHITECTURAL OVERVIEW
The bits RSO and RS I are used to select one of the four IMMEDIATE CONSTANTS
register banks shown in Figure 7. A number of instruc·
tions refer to these RAM locations as RO through R7. The value of a constant can follow the opcode in Pro·
The selection of which of the four banks is being re· gram Memory. For example,
ferred to is made on the basis of the bits RSO and RS I
at execution time. MOY A, #100
The Parity bit reflects the number of Is in the Accumu· loads the Accumulator with the decimal number 100.
lator: P = I if the Accumulator contains an odd num· The same number could be specified in hex digits as
ber of Is, and P = 0 if the Accumulator contains an 64H.
even number of Is. Thus the number of Is in the Accu·
mulator plus P is always even.
INDEXED ADDRESSING
Two bits in the PSW are uncommitted and may be used Only Program Memory can be accessed with indexed
as general purpose status flags. addressing, and it can only be read. This addressing
mode is intended for reading look·up tables in Program
Memory. A 16·bit base register (either DPTR or the
Addressing Modes Program Counter) points to the base of the table, and
the Accumulator is set up with the table entry number.
The addressing modes in the MCS·S 1 instruction set
The address of the table entry in Program Memory is
are as follows:
formed by adding the Accumulator data to the base
pointer.
DIRECT ADDRESSING
Another type of indexed addressing is used in the "case
In direct addressing the operand is specified by an 8·bit jump" instruction. In this case the destination address
address field in the instruction. Only internal Data of a jump instruction is computed as the sum of the
RAM and SFRs can be directly addressed. base pointer and the Accumulator data.
INDIRECT ADDRESSING
Arithmetic Instructions
In indirect addressing the instruction specifies a register
The menu of arithmetic instructions is listed in Table 2.
which contains the address of the operand. Both inter·
nal and external RAM can be indirectly addressed. The table indicates the addressing modes that can be
used with each instruction to access the <byte> oper·
The address register for 8·bit addresses can be RO or and. For example, the ADD A, <byte> instruction can
be written as:
R 1 of the selected register bank, or the Stack Pointer.
The address register for 16~bit addresses can only be the
16·bit "data pointer" register, DPTR. ADD A,7FH (direct addressing)
ADD A,@RO (indirect addressing)
ADD A,R7 (register addressing)
REGISTER INSTRUCTIONS ADD A,# 127 (immediate constant)
The register banks, containing registers RO through R 7, The execution times listed in Table 2 assume a 12 MHz
can be accessed. by certain instructions which carry a clock frequency. All of the arithmetic instructions exe·
3·bit register specification within the opcode of the in· cute in· 1 /Ls except the INC DPTR instruction, which
struction. Instructions that access the registers this way takes 2 /Ls, and the Multiply and Divide instructions,
are code efficient, since this mode eliminates an address which take 4 /Ls.
byte. When the instruction is executed, one of the eight
registers in the selected bank is accessed. One of four Note that any byte in the internal Data Memory space
banks is selected at execution time by the two bank can be incremented or decremented without going
select bits in the PSW. through the Accumulator.
One of the INC instructions operates on the 16·bit·
REGISTER-SPECIFIC INSTRUCTIONS
Data Pointer. The Data Pointer is used to generate
Some instructions are specific to a certain register. For 16·bit addresses for external memory, so being able to
example, some instructions always operate on the Ac· increment it in one 16·bit operation is a useful feature.
cumulator, or Data Pointer, etc., so no address byte is
needed to point to it. The opcode itself does that. In· The MUL AB instruction multiplies the Accumulator
structions that refer to the A-ccumlator as A assemble by the data in theB register and puts the 16·bit product
as accumulator· specific opcodes. into the concatenated B and Accumulator registers.
5·9
inter MCS®-51 ARCHITECTURAL OVERVIEW
Table 2. A List of the MCS®-51 Arithmetic Instructions
Addressing Modes Execution
Mnemonic Operation
Dir Ind Reg Imm Time (/Ls)
ADD A, <byte> A = A + <byte> X X X X 1
ADDC A, < byte> A, = A + <byte> + C X X X X 1
SUBB A, <byte> A = A - <byte> - C X X X X 1
INC A A=A+1 Accumulator only 1
INC <byte> <byte> = <byte> + 1 X X X 1
INC DPTR DPTR = DPTR + 1 Data Pointer only 2
DEC A A=A-1 Accumulator only 1
DEC <byte> <byte> = <byte> - 1 X X X .1
MUL AB B:A = BxA ACC and B only 4
DIV AB A = Int [AlB] 4
ACC and B only
B = Mod [AlB]
DA A Decimal Adjust Accumulator only 1
The DIY AB instruction divides the Accumulator by completes the shift in 4 /Ls and leaves the B register
the data in the B register and leaves the g·bit quotient holding the bits t hat were shifted out.
in the Accumulator, and the g·bit remainder in the B
register. The DA A instruction is for BCD arithmetic opera-
tions. In BCD arithmetic, ADD and ADDC instruc-
Oddly enough, DIY AB finds less use in arithmetic tions should always be followed by a DA A operation,
"divide" routines than in radix conversions and pro- to ensure that the result is also in BCD. Note that DA
grammable shift operations. An example of the use of A will not convert a binary number to BCD. The DA
DIY AB in a radix conversion will be given later. In A operation produces a meaningful result only as the
shift operations, dividing a number by 2n shifts its n second step in the addition of two BCD bytes.
bits to the right. Using DIY AB to perform the division
Table 3. A List of the MCS®·51 Logical Instructions
Addressing Modes Execution
Mnemonic Operation
Dir Ind Reg Imm Time (/Ls)
ANL A, <byte> A = A .AND. <byte> X X X X 1
ANL <byte> ,A <byte> = <byte> .AND. A X 1
ANL <byte>,#data <byte> = <byte> .AND. #data X 2
ORL A,<byte> A = A .OR. <byte> X X X X 1
ORL <byte> ,A <byte> = <byte> .OR. A X 1
ORL < byte>, #data <byte> = <byte> .OR. #data X 2
XRL A, <byte> A = A .XOR. <byte> X X X X 1
XRL <byte>,A <byte> = <byte> .xOR. A X 1
XRL <byte>,#data <byte> = <byte> .XOR. #data X 2
CRL A A = OOH Accumulator only 1
CPL A A = .NOT.A Accumulator only 1
RL A Rotate ACC Left 1 bit Accumulator only 1
RLC A Rotate Left through Carry Accumulator only 1
RR A Rotate ACC Right 1 bit Accumulator only 1
RRC A Rotate Right through Carry Accumulator only 1
SWAP A Swap Nibbles in A Accumulator only 1
5-10
intJ MCS®-51 ARCHITECTURAL OVERVIEW
Logical Instructions The SWAP A instruction interchanges the high and
low nibbles within the Accumulator. This is a useful
Table 3 shows the list of MCS-5l logical instructions. operation in BCD manipulations. For example, if the
The instructions that perform Boolean operations Accumulator contains a binary number which is known
(AND, OR, Exclusive OR, NOT) on bytes perform the to be less than 100, it can be quickly converted to BCD
operation on a bit-by-bit basis. That is, if the Accumu- by the following code:
lator contains 0011010lB and <byte> contains
0l010011B, then MOV B,#1O
DlV AB
ANL A, <byte> SWAP A
ADD A,B
will leave the Accumulator holding 0OO10001B.
Dividing the number by 10 leaves the tens digit in the
The addressing modes that can be used to access the low nibble of the Accumulator, and the ones digit in the
<byte> operand are listed in Table 3. Thus, the ANL B register. The SWAP and ADD instructions move the
A, <byte> instruction may take any of the forms tens digit to the high nibble of the Accumulator, and
the ones digit to the low nibble.
ANL A,7FH (direct addressing)
ANL A,@Rl (indirect addressing)
ANL A,R6 (register addressing) Data Transfers
ANL A,#53H (immediate constant)
INTERNAL RAM
All. of the logical instructions that are Accumulator-
specific execute in IJLs (using a 12 MHz clock). The Table 4 shows the menu of instructions that are avail-
others take 2 JLs. able for moving data around 'within the internal memo-
ry spaces, and the addressing modes that can be used
Note that Boolean operations can be performed on any with each one. With a 12 MHz clock, all of these in-
byte in the lower 128 internal Data Memory space or structions execute in either 1 or 2 /Ls.
the SFR space using direct addressing, without having
to use the Accumulator. The XRL <byte>, #.data in- The MOV < dest >, < src > instruction allows data to
struction, for example, offers a quick and easy way to be transferred between any two internal RAM or SFR
invert port bits, as in locations without going through the Accumulator. Re-
member the Upper 128 byes of data RAM can be ac-
XRL Pl,#OFFH cessed only by indirect addressing, and SFR space only
by direct addressing.
If the operation is in response to an interrupt, not using
the Accumulator saves the time and effort to stack it in Note that in all MCS-5l devices,the stack resides in
the service routine. on-chip RAM, and grows upwards. The PUSH instruc-
tion first increments the Stack Pointer (SP), then copies
The Rotate instructions (RL A, RLC A, etc.) shift the the byte into the stack. PUSH and POP use only direct
Accumulator 1 bit to the left or right. For a left rota- addressing to identify the byte being saved or restored,
tion, the MSB rolls into the LSB position. For a right
rotation, the LSB rolls into the MSB position.
Table 4. A List of the MCS®·51 Data Transfer Instructions that Access Internal Data Memory Space
Addressing Modes Execution
Mnemonic Operation
Dlr Ind Reg Imm Time (/Ls)
MOV A,<src> A= <src> X X X X 1
MOV <dest>,A <dest> = A X X X 1
MOV <dest>, <src> <dest> = <src> X X X X 2
MOV DPTR,#data16 DPTR = 16-bit immediate constant. X 2
PUSH <src> INC SP: MOV "@SP",<src> X 2
POP <dest> MOV <dest>, "@SP" : DEC SP X 2
XCH A,<byte> ACC and < byte> exchange data X X X 1
XCHD A,@Ri ACC and @Ri exchange low nibbles X 1
5-11
MCS®-S1 ARCHITECTURAL OVERVIEW
but the stack itself is accessed by indirect addressing After the routine has been executed, the Accumulator
using the SP register. This means the stack can go into contains the two digits that were shifted out on the
the Upper 128, if they are implemented, but not into right. Doing the routine with direct MOVs uses 14 code
SFR space. bytes and 9 I-I-s of execution time (assuming a 12 MHz
clock). The same operation with XCHs uses less code
In devices that do not implement the Upper 128, if the and executes almost twice as fast.
SP points to the Upper 128, PUSHed bytes are lost, and
POPped bytes are indeterminate. To right-shift by an odd number of digits, a one-digit
shift must be executed. Figure 12 shows a sample of
The Data Transfer instructions include a 16-bit MOV code that will right-shift a BCD number one digit, us-
that can be used to initialize the Data Pointer (DPTR) ing the XCHD instruction. Again, the contents of the
for look-up tables in Program Memory, or for 16-bit registers holding the number and of the Accumulator
external Data Memory accesses. are shown alongside each instruction.
The XCH A, <byte> instruction causes the Accumu-
lator and addressed byte to exchange data. The XCHD
A,@Ri instruction is similar, but only the low nibbles MOV R1,#2EH
are involved in the exchange. MOV RO,#2DH
loop for R1 = 2EH:
To see how XCH and XCHD can be used to facilitate LOOP: MOV A,@R1 00 12 34 56 78 78
data manipulations, consider first the problem of shift- XCHD A,@RO 00 12 34 58 78 -76-
ing an 8-digit BCD number two digits to the right. Fig- SWAP A 00 12 34 58 78 67
ure 11 shows how this can be done using direct MOVs, MOV @R1,A 00 12 34 58 67 67
and for comparison how it can be done using XCH DEC R1 00 12 34 58 67 67
instructions. To _aid in understanding how the code DEC RO 00 12 34 58 67 67
works, the contents of the registers that are holding the CJNE R1,#2AH,LOOP
I ggl~~I~~I:;I~~1 ~~
BCD number and the content of the Accumulator are loop for R1 = 2DH:
shown alongside each instruction to indicate their loop for R1 = 2CH:
-status after the instruction has been executed. loop for R1 = 2BH: 08 01 23 45 67 01
_CLR A
XCH A,2AH 108101123145167100
00 01 23 45 67 08
2A 2B 2C 2D 2E ACC
MOV A,2EH 00 12 34 56 78 78 Figure 12. Sl'!ifting a BCD Number
MOV 2EH,2DH 00 12 34 56 56 78 One Digit to the Right
MOV 2DH,2CH 00 12 34 34 56 78
MOV 2CH,2BH 00 12 12 34 56 78 First, pointers RI and RO are set up to point to the two
MOV 2BH,#0 00 00 12 34 56 78
bytes containing the last four BCD digits. Then a loop
(a) Using direct MOVs: 14 bytes, 9 f.Ls is executed which leaves the last byte, location 2EH,
2A 2B 2C 2D 2E ACC holding the last two digits of the shifted number. The
CLR A 00 12 34 56 78 00 pointers are decremented, and the loop is repeated for
XCH A,2BH 00 00 34 56 78 12 location 2DH. The CINE instruction (Compare and
XCH A,2CH 00 00 12 56 78 34 Jump if Not Equal) is a loop control that will be de-
XCH A,2DH 00 00 12 34 78 56 scribed later.
XCH A,2EH 00 00 12 34 56 78
(b) Using XCHs: 9 bytes, 5 f.Ls The loop is executed from LOOP to CINE for RI
2EH, 2DH, 2CH and 2BH. At that point the digit that
Figure 11. Shifting a BCD Number was originally shifted out on the right has propagated
Two Digits to the Right to location 2AH. Since that location should be left with
Os, the lost digit is moved to the Accumulator.
5-12
MCS®-51 ARCHITECTURAL OVERVIEW
EXTERNAL RAM Table 6. The MCS®-51 Lookup
Table Read Instructions
Table 5 shows a list of the Data Transfer instructions
Execution
that access external Data Memory. Only indirect ad- Mnemonic Operation
Time (",s)
dressing can be used. The choice is whether to use a
MOVC A,@A+DPTR Read Pgm Memory 2
one-byte address, @Ri, where Ri can be either RO or
at (A+DPTR)
R I of the selcctcd register bank, or a two-byte address,
@DPTR. The disadvantage to using 16-bit addresses if MOVC A,@A+PC Read Pgm Memory 2
at (A+PC)
only a few K bytes of external RAM are involved is
that 16-bit addresses use all 8 bits of Port 2 as address
bus. On the other hand, 8-bit addresses allow one to The first MOVC instruction in Table 6 can accommo-
address a few K bytes of RAM, as shown in Figure 5, date a table of up to 256 entries, numbered 0 through
without having to sacrifice all of Port 2. 255. The number of the desired entry is loaded into the
Accumulator, and the Data Pointer is set up to point to
All of these instructions execute in 2 fLs, with a beginning of the table. Then
12 MHz clock.
Table 5. A List of the MCS®-51 Data MOVC A,@A+DPTR
Transfer Instructions that Access
copies the desired table entry into the Accumulator.
External Data Memory Space
Address Execution The other MOVC instruction works the same way, ex-
Mnemonic Operation
Width Time (",s) cept the Program Counter (PC) is used as the table
8 bits MOVXA,@Ri
Read external base, and the table is accessed through a subroutine.
RAM @Ri
2
First the number of the desired entry is loaded into the
Write external Accumulator, and the subroutine is called:
8 bits MOVX@Ri,A 2
RAM @Ri
Read external MOV A, ENTRY_NUMBER
16 bits MOVX A,@DPTR 2 CALL TABLE
RAM@DPTR
Write external
16 bits MOVX @DPTR,A 2 The subroutine "TABLE" would look like this:
RAM@DPTR
TABLE: MOVC A,@A+PC
Note that in all external Data RAM accesses, the Ac-
RET
cumulator is always either the destination or source of
the data.
The table itself immediately follows the RET (return)
instruction in Program Memory. This type of table can
The read and write strobes to external RAM are acti-
have up to 255 entries, numbered I through 255. Num-
vated only during the execution of a MOVX instruc-
ber 0 can not be used, because at the time the MOVC
tion. Normally these signals are inactive, and in fact if
instruction is executed, the PC contains the address of
they're not going to be used at all, their pins are avail-
the RET instruction. An entry numbered 0 would be
able as extra I/O lines. More about that later.
the RET opcode itself.
LOOKUP TABLES
Boolean Instructions
Table 6 shows the two instructions that are available
for reading lookup tables in Program Memory. Since MCS-51 devices contain a complete Boolean (single-bit)
these instructions access only Program Memory, the processor. The internal RAM contains 128 addressable
lookup tables can only be read, not updated. The mne- bits, and the SFR space can support up to 128 other
monic is MOVC for "move constant". addressable bits. All of the port lines are bit-address-
able, and each one can be treated as a separate single-
If the table access is to external Program Memory, then bit port. The instructions that access these bits are not
the read strobe is PSEN. just conditional branches, but a complete menu of
move, set, clear, complement, OR, and AND instruc-
tions. These kinds of bit operations are not easily ob-
tained in other architectures with any amount of byte-
oriented software.
5-13
inter MCS®-51 ARCHITECTURAL OVERVIEW
Table 7. A List of the MCS®-S1 Note that the Boolean instruction set includes ANL
Boolean Instructions and ORL operations, but not the XRL (Exclusive OR)
operation. An XRL operation is simple to implement in
Operation Execution software. Suppose, for example, it is required to form
Mnemonic
Time (J.Ls) the Exclusive OR of two bits:
ANL C,bit C = C .AND. bit 2
C = bitl .xRL bit2
ANL C,/bit C = C .AND ..NOT. bit 2
ORL C,bit C = C .OR. bit 2 The software to do that could be as follows:
ORL C,/bit C = C .OR .. NOT. bit 2
MOV C,bitl
MOV C,bit C = bit 1 JNB bit2,OVER
MOV bit,C bit = C 2 CPL C
OVER: (continue)
CLR C C=O 1
CLR bit bit = 0 1 First, bitl is moved to the Carry. If bit2 = 0, then C
SETB C C.= 1 1 now contains the correct result. That is, bit 1 .XRL. bit2
= bitl if bit2 = O. On the other hand, if bit2 = I C
SETB bit bit = 1 1 now contains the complement of the correct result. It
CPL C C = .NOT.C 1 need only be inverted (CPL C) to complete the opera-
CPL bit = .NOT. bit tion.
bit 1
JC rei Jump if C = 1 2 This code uses the JNB instruction, one of a series of
JNC rei JumpifC = 0 2 bit-test instructions which execute a jump if the ad-
dressed bit is set (JC, JB, JBC) or if the addressed bit is
JB bit,rel Jump if bit = 1 2 not set (JNC, JNB). In the above case, bit2 is being
JNB bit,rel Jump if bit = 0 2 tested, and if bit2 = 0 the CPL C instruction is jumped
JBC bit,rel Jump if bit = 1; CLR bit 2 over.
JBC executes the jump if the addressed bit is set, and
The instruction set for the Boolean processor is shown also clears the bit. Thus a flag can be tested and cleared
in Table 7. All bit accesses are by direct addressing. Bit in one operation.
addresses OOH through 7FH are in the Lower 128, and
bit addresses 80H through FFH are inSFR space. All the PSW bits are directly addressable, so the Parity
bit, or the general purpose flags, for example, are also
Note how easily an internal flag can be moved to a port available to the bit-test instructions.
pin: .
MOV C,FLAG RELATIVE OFFSET
MOV Pl.O,C
The destination address for these jumps is specified to
In this example, FLAG is the name of any addressable the assembler by a label or by an actual address in
bit in the Lower 128 or SFR space. An 1/0 line (the Program Memory. However, the destination address
LSB of Port I, in this case) is set or cleared depending assembles to a relative offset byte. This is a signed
on whether the flag bit is I or o. (two's complement) offset byte which is added to the
PC in two's complement arithmetic if the jump is exe-
The Carry bit in the PSW is used as the single-bit Accu- cuted.
mulator of the Boolean processor. Bit instructions that
refer to the Carry bit as C assemble as Carry-specific The range of the jump is therefore -128 to + 127 Pro-
instructions (CLR C, etc). The Carry bit also has a gram Memory bytes relative to the first byte following
direct address, since it resides in the PSW register, the instruction.
which is bit-addressable.
5-14
inter MCS®-51 ARCHITECTURAL OVERVIEW
Jump Instructions the Accumulator. Typically, DPTR is set up with the
address of a jump table, and the Accumulator is given
Table 8 shows the list of unconditional jumps. an index to the table. In a 5-way branch, for example,
an integer 0 through 4 is loaded into the Accumulator.
Table 8. Unconditional Jumps The code to be executed might be as follows:
in MCS®-S1 Devices
Execution MOV DPTR,#JUMP_TABLE
Mnemonic Operation MOV A,INDEX_NUMBER
Time ()Ls)
RL A
JMP addr Jump to addr 2
JMP @A+DPTR
JMP @A+OPTR Jump to A + OPTR 2
CALL addr Call subroutine at addr 2 The RL A instruction converts the index number (0
through 4) to an even number on the range 0 through 8,
RET Return from subroutine 2
because each entry in the jump table is 2 bytes long:
RET! Return from interrupt 2
NOP No operation 1 JUMP_TABLE:
AJMP CASE_O
AJMP CASE_l
The Table lists a single "JMP addr" instruction, but in AJMP CASE_2
fact there are three-SJMP, LJMP and AJMP-which AJMP CASE_3 .
differ in the format of the destination address. JMP is a AJMP CASE_4
generic mnemonic which can be used if the program-
mer does not care which way the jump is encoded. Table 8 shows a single "CALL addr" instruction, but
there are two of them-LCALL and ACALL-which
The SJMP instruction encodes the destination address differ in the format in which the subroutine address is
as a relative offset, as described above. The instruction given to the CPU. CALL is a generic mnemonic which
is 2 bytes long, consisting of the opcode and the relative can be used if the programmer does not care which way
offset byte. The jump distance is limited to a range of the address is encoded.
- 128 to + 127 bytes relative to the instruction follow-
ing the SJMP. The LCALL instruction uses the 16-bit address format,
and the subroutine can be anywhere in the 64K Pro-
The LJMP instruction encodes the destination address gram Memory space. The ACALL instruction uses the
as a 16-bit constant. The instruction is 3 bytes long, 11 -bit format, and the subroutine must be in the same
consisting of the opcode and two address bytes. The 2K block as the instruction following the ACALL.
destination address can be anywhere in the 64K Pro-
gram Memory space. In any case the programmer specifies the subroutine
address to the assembler in the same way: as a label or
The AJMP instruction encodes the destination address as a 16-bit constant. The assembler will put the address
as an 11 -bit constant. The instruction is 2 bytes long, into the correct format for the given instructions.
consisting of the opcode, which itself contains 3 of the
11 address bits, followed by another byte containing the Subroutines should end with a RET instruction, which
low 8 bits of the destination address. When the instruc- returns execution to the instruction following the
tion is executed, these 11 bits are simply substituted for CALL.
the low 11 bits in the PC. The high 5 bits stay the same.
Hence the destination has to be within the same 2K RETI is used to return from an interrupt service rou-
block as the instruction following the AJMP. tine. The only difference between RET and RET! is
that RETI tells the interrupt control system that the
In all cases the programmer specifies the destination interrupt in progress is done. If there is no interrupt in
address to the assembler in the same way: as a label or progress at the time RET! is executed, then the RET!
as a 16-bit constant. The assembler will put the destina- is functionally identical to RET.
tion address into the correct format for the given in-
struction. If the format required by the instruction will Table 9 shows the list of conditional jumps available to
not support the distance to the specified destination ad- the MCS-51 user. All of these jumps specify the desti-
dress, a "Destination out of range" message is written nation address by the relative offset method, and so are
into the List file. limited to a jump distance of -128 to + 127 bytes from
the instruction following the conditional jump instruc-
The JMP @A +' DPTR instruction supports case tion. Important to note, however, the user specifies to
jumps. The destination address is computed at execu- the assembler the actual destination address the same
tion time as the sum of the 16-bit DPTR register and way as the other jumps: as a label or a 16-bit constant.
5-15
inter MCS®-51 ARCHITECTURAL OVERVIEW
Table 9. Conditional Jumps in MCS®-S1 Devices
Addressing Modes Execution
Mnemonic Operation
Dir Ind Reg Imm Time (p.s)
JZ rei Jump itA = 0 Accumulator only 2
JNZ rei Jump it A*-O Accumulator only 2
DJNZ <byte> ,rei Decrement and jump it not zero X X 2
CJNE A, <byte> ,rei Jump it A *- <byte> X X 2
CJNE <byte>, # data, rei Jump it <byte> *- #data X X 2
There is no Zero bit in the PSW. The JZ and JNZ
instructions test the Accumulator data for that condi- <Ill
Mes -51
tion. HMOS
OR CHt.tOS
...--_--fXTAL2
The DJNZ instruction (Decrement and Jump if Not
Zero) is for loop control. To execute a loopN times, OUAR~ ~~~:1~~
RESONATOR
"c=
load a counter byte with N and terminate the loop with L-'-+-fXTAL1
a DJNZ to the beginning of the loop, as shown below
VSS
for N = 10: =L--__.....
270251-11
MOV COUNTER, # 10
LOOP: (begin loop) Figure 13. Using the On-Chip Oscillator
•
<R>
(end loop) Mes -51
HMOS
DJNZ COUNTER,LOOP OR CHtdOS
(continue) XTAL2
The CJNE instruction (Compare and Jump if Not EXTERNAL
Equal) can also be used for loop control as in Figure 12. CLOCK
SIGNAL
XTALl
Two bytes are specified in the operand field of the in- VSS
struction. The jump is executed only if the two bytes
are not equal. In the example of Figure 12, the two 270251-12
bytes were the data in RI and the constant 2AH. The A. HMOS or CHMOS
initial data in RI was 2EH. Every time the loop was
executed, Rl was decremented, and the looping was to <R>
MCS -51
continue until the RI data reached 2AH. HMOS
ONLY
EXTERNAL
CLOCK XTAL2
Another application of this instruction is in "greater SIGNAL
than, less than" comparisons. The two bytes in the op-
erand field are taken as unsigned integers. If the first is
XTALI
less than the second, then the Carry bit is set (I). If the
VSS
first is greater than or equal to the second, then the
Carry bit is cleared. 270251-13
B.HMOSOnly
CPU TIMING <R>
MCS -51
CHMOS
All MCS-51 microcontrollers have an on-chip oscillator ONLY
which can be. used if desired as the clock .source for the (NC) XTAL2
CPU. To use the on-chip oscillator, connect a crystal or
ceramic resonator between the XTALI and XTAL2 EXTERNAL
pins of the microcontroller, and capacitors to ground as CLOCK
SIGNAL
XTALI
shown in Figure 13. VSS
270251-14
C. CHMOS Only
Figure 14. Using an External Clock
5-16
MCS®-51 ARCHITECTURAL OVERVIEW
Examples of how to drive the clock with an external Machine Cycles.
oscillator are shown in Figure 14. Note that in the
HMOS devices (8051, etc.) the signal at the XTAL2 pin A machine cycle consists of a sequence of 6 states,
actually drives the internal clock generator. In the numbered S 1 through S6. Each state time lasts for two
CHMOS devices (80C5IBH, etc.) the signal at the oscillator periods. Thus a machine cycle takes 12 oscil-
XTAL I pin drives the internal clock generator. If only lator periods or 1 JLs if the oscillator frequency is
one pin is going to be driven with the external oscillator 12 MHz.
signal, make sure it is the right pin.
Each state is divided into a Phase 1 half and a Phase 2
The internal clock generator defines the sequence of half. Figure 15 shows the fetch/execute sequences in
states that make up the MCS-51 machine cycle.
05C.
I I I I I I I I I I I I I I
51 52 53
~~~~~~~~~~~~~~~~~~~~~~~~~~
54 55 56 51 52 53 54 S5 S6 51
(XTAL2)
ALE
_[ _R:~D NEXT OPCODE AGAIN.
- - - - - - ,--.1.--.---_.--_-.---'-----.-_---,._----,
______ ~~ _ _ _ L_ _ _ L_ _ ~ __ ~~
(A) 1·byte, 1-cycle instruction, e.g., INC A.
I
I READ OPCODE.
I
: _ [_R:~ NEXT OPCODE.
--------~~--_.--_r~._--~~
-- - - - - - - ~~-----'----'----'----'-------'
(8) 2-byte. I-cycle Instruction, e.g .• ADD A, #data
READ OPCODE.
READ NEXT
OPCODE (DISCARD).
_______ .~~ _ ____'__ __ ' __ __'___ _' _ _ _ _ J_ __ L_ _ ~ _ __'___ _ L_~ __ ~ _____ _
(C) t-byte, 2-cycle in.tucllon, e.g., INC DPTR.
I
READOPCODE
(MOVX). . NO
______ ___ L_ __ L_ __'___ _L_~_ __ L_ _~_ _~~L-~--~-----
l
L-~
ADDR DATA
(D) MOVX (I-byte. 2-cycle)
ACCESS EXTERNAL MEMORY
270251-15
Figure 15. State Sequences in MCS®-51 Devices
5-17
inter MCS®-51 ARCHITECTURAL OVERVIEW
states and phases for various kinds of instructions. Nor- The fetch/execute sequences are the same whether the
mally two program fetches are generated during each Program Memory is internal or external to the chip.
machine cycle, even if the instruction being executed Execution times do not depend on whether the Pro-
doesn't require it. If the instruction being executed gram Memory is internal or external.
doesn't need more code bytes, the. CPU simply ignores
the extra fetch, and the' Program Counter is not incre- Figure 16 shows the signals and timing involved in pro-
mented. gram fetches when the Program Memory is external. If
Program Memory is external, then the Program Memo-
Execution of a one-cycle instruction (Figure 15A and ry read strobe PSEN is normally activated twice per
B) begins during State 1 of the machine cycle, when the machine cycle, as shown in Figure l6(A).
opcode is latched into the Instruction Register. A sec-
ond fetch occurs during S4 of the same machine cycle. If an access to external Data Memory occurs, as shown
Execution is complete at the end of State 6 of this ma- in Figure 16(B), two PSENs are skipped, because the
chine cycle. address and data bus are being used for the Data Mem-
ory access.
The MOVX instructions take two machine cycles to
execute. No program fetch is generated during the sec- Note that a Data Memory bus cycle takes twice as
ond cycle of a MOVX instruction. This is the only time much time as a Program Memory bus cycle. Figure 16
program fetches are skipped. The fetch/execute se- shows the relative timing of the addresses being emitted
quence for MOVX instructions is shown in Figure at Ports 0 and 2, and of ALE and PSEN. ALE is used
l5(D). to latch the low address byte from PO into the address
latch.
ALE
PsEN
(A)
AD -------+--~------~---------4----------~----------~--- WITHOUT A
MOVX.
PO
I
, I
I ,I I
t.PCL OUT t.PCLOUT hCLOUT t.PCLOUT
VALID VALID VALID VALID
ALE
PSEN
RD --------~----------~----~
(8)
WITH A
MOVX.
t. PCLVALID
OUT t.PCLOUT
VALID
270251-16
Figure 16. Bus Cycles in MCS®-51 Devices Executing from External Program Memory
5-18
inter MCS®-51 ARCHITECTURAL OVERVIEW
When the CPU is executing from internal Program named IE (Interrupt Enable). This register also con-
Memory, PSEN is not activated, and program address- tains a global disable bit, which can be cleared to dis-
es are not emitted. However, ALE continues to be acti- able all interrupts at once. Figure 17 shows the IE reg-
vated twice per machine cycle and so is available as a ister for the 8051.
clock output signal. Note, however, that one ALE is
skipped during the execution of the MOVX instruction.
INTERRUPT PRIORITIES
Each interrupt source can also be individually pro-
Interrupt Structure grammed to one of two priority levels by setting or
clearing a bit in the SFR named IP (Interrupt Priority).
The 8051 core provides 5 interrupt sources: 2 external
Figure 18 shows the IP register in the 8051.
interrupts, 2 timer interrupts, and the serial port inter-
rupt. What follows is an overview of the interrupt
A low-priority interrrupt can be interrupted by a high-
structure for the 8051. Other MCS-51 devices have ad-
priority interrupt, but not by another low-priority inter-
ditional interrupt sources and vectors as shown in Ta-
rupt. A high-priority interrupt can't be interrupted by
ble I. Refer to the appropriate chapters on other devic-
any other interrupt source.
es for further information on their interrupts.
If two interrupt requests of different priority levels are
INTERRUPT ENABLES received simultaneously, the request of higher priority
level is serviced. If interrupt requests of the same priori-
Each of the interrupt sources can be individually en- ty level are received simultaneously, an internal polling
abled or disabled by setting or clearing a bit in the SFR sequence determines which request is serviced. Thus
within each priority level there is a second priority
structure determined by the polling sequence.
(MSB) (LSB)
IEA I - I - I ES I ET1 I EXl I ETO I EXO I Figure 19 shows, for the 8051, how the IE and IP regis-
Enable bit = 1 enables the interrupt. ters and the polling sequence work to determine which
Enable bit = 0 disables it.
if any interrupt will be serviced.
Symbol Position Function
EA 1E.7 disables all interrupts. If EA = 0, no
interrupt will be acknowledged. If EA ~~ ~~
= 1, each interrupt source is
individually enabled or disabled by
I- I - I - I PS I PTl I PXl IPTO I PXO I
Priority bit = 1 assigns high priority.
setting or clearing its enable bit. Priority bit = 0 assigns low priority.
1E.6 reserved*
Symbol Position Function
1E.5 reserved'"
ES IE.4 Serial Port Interrupt enable bit. IP.7 reserved'"
ETl 1E.3 Timer 1 Overflow Interrupt enable bit. IP.6 reserved*
EXl 1E.2 External Interrupt 1 enable bit. IP.5 reserved'"
ETO lE.l Timer 0 Overflow Interrupt enable bit. PS IP.4 Serial Port interrupt priority bit.
EXO IE.O External Interrupt 0 enable bit. PTl IP.3 Timer 1 interrupt priority bit.
'These reserved bits are used in other MCS-51 devices. PX1 IP.2 External Interrupt 1 priority bit.
PTO IP.l Timer 0 interrupt priority bit.
Figure 17_ IE (Interrupt Enable) PXO IP.O External Interrupt 0 priority bit.
'These reserved bits are used in other MCS-5l devices.
Register in the 8051
Figure 18. IP (Interrupt Priority)
Register in the 8051
5-19
MCS®-S1 ARCHITECTURAL OVERVIEW
HIGH PRIORITY
IP REGISTER ~-- INTERRUPT
~=>T-~~-l---W
I
I
I
I
TfO------+t--<Y ~>-t-___r-o-_a.__l_-~-+I INTERRUPT
POLLING
I SEQUENCE
I
I
~I =>-r-i<>"-o.+--I-.I
••
, •
!--
Tf1--------+f-<y o--o'"j (~-__r_o~J_I--~~
••
I
I
~-----M~~~--~~J-I-~_=~
RI
TI
INDIVIDUAL GLOBAL LOW PRIORITY
ENABLES DISABLE INTERRUPT
270251-17
Figure 19. 8051 Interrupt Control System
In operation, all the interrupt flags are latched into the pleted in less time than it takes other architectures to
interrupt control system during State 5 of every ma- commence them.
chine cycle. The samples are polled during the follow~
ing machine cycle. If the flag for an enabled interrupt is
found to be set (I), the interrupt system generates an SIMULATING A THIRD PRIORITY LEVEL IN
LCALL to the appropriate location in Program Memo- SOFTWARE
ry, unless some other condition blocks. the interrupt. Some applications require more than the two priority
Several conditions can block an interrupt, among them levels that are provided by on-chip hardware in
that an interrupt of equal or higher priority level is MCS-51 devices. In these cases, relatively simple soft-
already in progress. ware can be written to produce the same effect as a
third priority level.
The hardware-generated LCALL causes the contents of
the Program, Counter to be pushed onto the stack, a~d First, interrupts that are to have higher priority than 1
reloads the PC with,the beginning address of the service are assigned to priority 1 in the IP (Interrupt Priority)
routine. As previously noted (Figure 3), the service rou- register. The service routines for priority 1 interrupts
tine for each interrupt begins at a fixed location. that are supposed to be interruptible by "priority 2"
interrupts are written to include the following code:
Only the Program Counter is automatically pushed
onto the stack, not the PSW or any other register. Hav- PUSH IE
ing only the PC be automatically saved allows the p~o MOV IE,#MASK
grammer to decide how much time to spend saving CALL LABEL
which other registers. This enhances the interrupt re- *******
sponse time, albeit at the expense of increasing the pro- (execute service routine)
grammer's burden of responsibi!ity ..As a result, m~ny *******
interrupt functions that are tYPical In control applica- POP IE
tions-toggling a port pin, for example, or reloading a RET
timer, or unloading a serial buffer--can often be com- LABEL: RETI
5-20
inter MCS®-51 ARCHITECTURAL OVERVIEW
As soon as any priority 1 interrupt is acknowledged, ADDITIONAL REFERENCES
the IE (Interrupt Enable) register is re-defined so as to
disable all but "priority 2" interrupts. Then, a CALL to The following application notes are found in the
LABEL executes the RETI instruction, which clears Embedded Control Applications handbook. (Order
the priority 1 interrupt-in-progress flip-flop. At this Number: 270648)
point any priority 1 interrupt that is enabled can be 1. AP-69 "An Introduction to the Intel MCS®-51 Sin-
serviced, but only "priority 2" interrupts are enabled. gle-Chip Microcomputer Family"
POPping IE restores the original enable byte. Then a 2. AP-70 "Using the Intel MCS®-51 Boolean Process-
normal RET (rather than another RETI) is used to ing Capabilities"
terminate the service routine. The additional software
adds 10 /-Ls (at 12 MHz) to priority 1 interrupts.
5-21
MCS®..,51 Programmer's Guide 6
and Instruction Set
July 1989
MCS®-51 Programmer's Guide
and Instruction Set
Order Number: 270249-003
6-1
MCS®-51 PROGRAMMER'S CONTENTS PAGE
GUIDE AND INSTRUCTION MEMORY ORGANIZATION .............. 6~4
SET PROGRAM MEMORY .................... 6-4
Data Memory ............................. 6-5
INDIRECT ADDRESS AREA ............. 6-7
DIRECT AND INDIRECT ADDRESS
AREA .................................. 6-7
SPECIAL FUNCTION REGISTERS . ...... 6-9
WHAT DO THE SFRs CONTAIN JUST
AFTER POWER-ON OR A RESET .... 6-10
SFR MEMORY MAP .................... 6-11
PSW: PROGRAM STATUS WORD. BIT
ADDRESSABLE ...................... 6-12
PCON: POWER CONTROL REGISTER.
NOT BIT ADDRESSABLE ............ 6-12
INTERRUPTS .... ....................... 6-13
IE: INTERRUPT ENABLE REGISTER.
BIT ADDRESSABLE .................. 6-13
ASSIGNING HIGHER PRIORITY TO
ONE OR MORE INTERRUPTS ........ 6-14
PRIORITY WITHIN LEVEL ...... ........ 6-14
IP: INTERRUPT PRIORITY REGISTER.
BIT ADDRESSABLE .................. 6-14
TCON: TIMER/COUNTER CONTROL
REGISTER. BIT ADDRESSABLE ..... 6-15
TMOD: TIMER/COUNTER MODE
CONTROL REGISTER. NOT BIT
ADDRESSABLE ...................... 6-15
TIMER SET-UP ......................... 6-16
TIMER/COUNTER 0 .................... 6-16
TIMER/COUNTER 1 .................... 6-17
T2CON: TIMER/COUNTER 2 CONTROL
REGISTER. BIT ADDRESSABLE ..... 6-18
TIMER/COUNTER 2 SET-UP ........... 6-19
SCON: SERIAL PORT CONTROL
REGISTER. BIT ADDRESSABLE ..... 6-20
6-2
CONTENTS PAGE CONTENTS PAGE
SERIAL PORT SET·UP ................. 6-20 USING TIMER/COUNTER 2 TO
GENERATE BAUD RATES ........... 6-21
GENERATING BAUD RATES ........... 6-20
Serial Port in Mode 0 .................... 6-20 SERIAL PORT IN MODE 2 .............. 6-21
Serial Port in Mode 1 .................... 6-20 SERIAL PORT IN MODE 3 .............. 6-21
USING TIMER/COUNTER 1 TO MCS®·51 INSTRUCTION SET .......... 6-22
GENERATE BAUD RATES ........... 6-21
INSTRUCTION DEFINITIONS . .......... 6-29
6-3
MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET
The information presented in this chapter is collected from the MCS®-51 Architectural Overview and the Hardware
Description of the 8051, 8052 and 80C51 chapters of this book. The material has been selected and rearranged to
form a quick and convenient reference for the programmers of the MCS-5!. This guide pertains specifically to the
8051, 8052 and 80C5!.
MEMORY ORGANIZATION
PROGRAM MEMORY
The 8051 has separate address spaces for Program Memory and Data Memory. The Program Memory can be up to
64K bytes long. The lower 4K (8K for the 8052) may reside on-chip.
Figure 1 shows a map of the 8051 program memorY, and Figure 2 shows a map of the 8052 program memory.
"FFr---------------------~
60K
BYTES
EXTERNAL
64K
--OR----.~ BYTES
EXTERNAL
1000 '--____________________ ~
AND
4K BYTES
INTERNAL
°oooo"Fl________________ ~ 0000 L..... _ _ _ _ _ _ _ _ _ _;..I
270249-1
Figure 1. The 8051 Program Memory
6-4
inter MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
~FFr-------------~------~ FFFF r-----------------..,
56K
BYTES
EXTERNAL
14K
- - - OR ---i~" BYTES
EXTERNAL
2000 L...._ _ _ _ _ _ _ _....I
AND
1FFF r------------------....
8KBYTES
INTERNAL
~~------------------~ ~ ~-----------------~
270249-2
Figure 2. The 8052 Program Memory
Data Memory:
The 8051 can address up to 64K bytes of Data Memory external to the chip. The "MaYx" instruction is used to
access the external data memory. (Refer to the MeS-51 Instruction Set, in this chapter, for detailed description of
instructions).
The 8051 has 128 bytes of on-chip RAM (256 bytes in the 8052) plus a number of Special Function Registers (SFRs).
The lower 128 bytes of RAM can be accessed either by direct addressing (MaY data addr) or by indirect addressing
(MaY @Ri). Figure 3 shows the 8051 and the 8052 Data Memory organization.
6-5
intJ MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET
OFFFr-----------------------------------,
INTERNAL
FFr-------------------------------------~
64K
SFR. BYTES
DIRECT EXTERNAL
ADDRESSING
ONLY
80
7F~------------------------------------~ - - AND -----l.~
DIRECT.
INDIRECT
ADDRESSING
00'-----------'----...... oooo~--------~
270249-3
Figure 3a.The 8051 Data Memory
ffff ,.....------,--------------------------------.,
INTERNAL
INDIRECT
f ADDRESSING ONLY
8OHTO FFH
FFI
ffr-~--------_;
64K
SFR. BYTES
DIRECT
ADDRESSING
ONLY
-- EXTERNAL
--AND--..
801-________________________________.........---1
7F
DIRECT.
INDIRECT
ADDRESSING
oo~---------~ 0000 ~----------'
270249-4
Figure 3b. The 8052 Data Memory
6-6
inter MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET
INDIRECT ADDRESS AREA:
Note that in Figure 3b the SFRs and the indirect address RAM have the same addresses (80H-OFFH). Neverthe-
less, they are two separate areas and are accessed in two different ways.
For example the instruction
MOY 80H,#OAAH
writes OAAH to Port 0 which is one of the SFRs and the instruction
MOY RO,#80H
MOY @RO,#OBBH
writes OBBH in location 80H of the data RAM. Thus, after execution of both of the above instructions Port 0 will
contain OAAH and location 80 of the RAM will contain OBBH.
Note that the stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available
as stack space in those devices which implement 256 bytes of internal RAM.
DIRECT AND INDIRECT ADDRESS AREA:
The 128 bytes of RAM which can be accessed by both direct and indirect addressing can be divided into 3 segments
as listed below and shown in Figure 4.
1. Register Banks 0-3: Locations 0 through lFH (32 bytes). ASM-5l and the device after reset default to register
bank o. To use the other register banks the user must select them in the software (refer to the MCS-51 Micro
Assembler User's Guide). Each register bank contains 8 one-byte registers, 0 through 7.
Reset initializes the Stack Pointer to location07H and it is incremented once to start from location 08H which is the
first register (RO) of the second register bank. Thus, in order to use more than one register bank, the SP should be
intiaIized to a different location of the RAM where it is not used for data storage (ie, higher part of the RAM).
2. Bit Addressable Area: 16 bytes have been assigned for this segment, 20H-2FH. Each one of the 128 bits of this
segment can be directly addressed (0-7FH).
The bits can be referred to in two ways both of which are acceptable by the ASM-51. One way is to refer to their
addresses, ie. 0 to 7FH. The other way is with reference to bytes 20H to 2FH. Thus, bits 0-7 can also be referred to
as bits 20.0-20.7, and bits 8-FH are the same as 21.0-21.7 and so on.
Each of the 16 bytes in this segment can also be addressed asa byte.
3. Scratch Pad Area: Bytes 30H through 7FH are available to the user as data RAM. However, if the stack pointer
has been initialized to this area, enough number of bytes should be left aside to prevent SP data destruction.
6-7
MCS@·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
Figure 4 shows the different segments of the on-chip RAM.
__
11~~ -----------8~
78 7F
70 77
88 8F
60 87
SCRATCH
58 SF
PAD
50 57
AREA
48 4F
40 47
38 3F
30 37
28 .•• 7F 2F BIT
ADDRESSABLE
SEGMENT
20 0 ... 27
18 3 1F
10 2 .. 17 REGISTER
08 1 OF BANKS
00 0 07
270249-5
Figure 4.128 Bytes of RAM Direct and Indirect Addressable
6-8
inter MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
SPECIAL FUNCTION REGISTERS:
Table 1 contains a list of all the SFRs and their addresses.
Comparing Table 1 and Figure 5 shows that all of the SFRs that are byte and bit addressable are located on the first
column of the diagram in Figure 5.
Table 1
Symbol Name Address
*ACC Accumulator OEOH
'B B Register OFOH
*PSW Program Status Word ODOH
SP Stack Pointer 81H
DPTR Data Pointer 2 Bytes
DPL Low Byte 82H
DPH High Byte 83H
'PO Port 0 80H
'P1 Port 1 90H
*P2 Port 2 OAOH
*P3 Port 3 OBOH
*IP Interrupt Priority Control OB8H
*IE Interrupt Enable Control OA8H
TMOD Timer/Counter Mode Control 89H
'TCON Timer/Counter Control 88H
*+ T2CON Timer/Counter 2 Control OC8H
THO Timer/Counter 0 High Byte 8CH
TLO Timer/Counter 0 Low Byte 8AH
TH1 Timer/Counter 1 High Byte 8DH
TL1 Timer/Counter 1 Low Byte 8BH
+TH2 Timer/Counter 2 High Byte OCDH
+ TL2 Timer/Counter 2 Low Byte OCCH
+ RCAP2H T /C 2 Capture Reg. High Byte OCBH
+RCAP2L T /C 2 Capture Reg. Low Byte OCAH
'SCON Serial Control 98H
SBUF Serial Data Buffer 99H
PCON Power Control 87H
• = Bit addressable
+ = 8052 only
6-9
MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET
WHAT DO THE SFRs CONTAIN JUST AFTER POWER-ON OR A RESET?
Table 2 lists the contents of each SFR after power-on or a hardware reset.
Table 2. Contents of the SFRs after reset
Register Value in Binary
'ACC 00000000
'S 00000000
'PSW 00000000
SP 00000111
DPTR
DPH 00000000
DPL 00000000
'PO 11111111
'P1 11111111
'P2 11111111
'P3 11111111
*IP 8051 XXXOOOOO,
8052 XXOOOOOO
'IE 8051 OXXOOOOO,
8052 OXOOOOOO
TMOD 00000000
'TCON 00000000
*+ T2CON 00000000
THO 00000000
TLO 00000000
TH1 00000000
TL1 00000000
+TH2 00000000
+TL2 00000000
+ RCAP2H 00000000
+ RCAP2L 00000000
'SCON 00000000
SSUI:; Indeterminate
PCON HMOS OXXXXXXX
CHMOS OXXXOOOO
x = Undefined
• = Bit Addressable
+ = 8052 only
6-10
intJ MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
SFR MEMORY MAP
8 Bytes
F8 FF
FO B F7
EB EF
. EO ACC E7
DB OF
DO PSW 07
CB T2CON RCAP2L RCAP2H TL2 TH2 CF
CO C7
BB IP BF
BO P3 B7
A8 IE AF
AO P2 A7
98 SCON SBUF 9F
90 P1 97
88 TCON TMOD TLO TL1 THO TH1 8F
80 PO SP DPL DPH PCON 87
t Figure 5
Bit
Addressable
6-11
inter MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
Those SFRs that have their bits assigned for various fuhctions are listed in this section. A brief description of eaeh bit
is provided for quiek reference. For more detailed information refer to the Architecture Chapter of this book.
PSW: PROGRAM STATUS WORD. BIT ADDRESSABLE.
CY AC FO RS1 RSO OV P
CY PSW,7 Carry Flag.
AC PSW.6 Auxiliary Carry Flag.
FO psw.s , Flag 0 available to the user for general purpose.
RSI PSW.4 Register Bank selector bit 1 (SEE NOTE 1).
RSO PSW.3 Register Bank selector bit 0 (SEE NOTE 1).
OV PSW.2 Overflow Flag.
PSW.l User definable flag. '
P psw.o Parity flag. Set/cleared by hardware each instruction cycle to indicate ~ odd/even number of
'I' bits in the accumulator.
NOTE:
1. The value presented by RSO and RS1 selects the corresponding register bank.
RS1 RSO Register Bank Address
0 0 0 OOH-07H
0 1 1 OBH-OFH
1 0 2 10,H-17H
1 1 3 1BH-1FH
PCON: POWER CONTROL REGISTER. NOT BIT ADDRESSABLE.
SMOO GF1 GFO PO IOL 'j
SMOD Double baud rate bit. If Timer 1 is used to generate baud rate and SMOD = I, the baud rate is doubled
when the Serial Port is used in modes 1,2, or 3.
Not implemented, reserved for future use.'
Not implemented, reserved for future use.'
Not implemented, reserved for future use.'
GFI General purpose flag' bit.
GFO General purpose flag bit.
PD Power Down bit. Setting this bit activates Power Down operation in the 80CSIBH. (Available only in
CHMOS).
IDL Idle Mode bit. Setting this bit activates Idle Mode operation in the 80CSIBH. (Available only in CHMOS).
If Is are written to PD and IDL at the same time, PD takes precedence.
·User software should not write 1s to reserved bits. These bits may be used in, future MeS-51 products to invoke new
features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1.
6-12
inter MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET
INTERRUPTS:
In order to use any of the interrupts in the MCS-51, the following three steps must be taken.
1. Set the EA (enable all) bit in the IE register to 1.
2. Set the corresponding individual interrupt enable bit in the IE register to 1.
3. Begin the interrupt service routine at the corresponding Vector Address of that interrupt. See Table below.
Interrupt Vector
Source Address
lEO 0OO3H
TFO OOOBH
IE1 0013H
TF1 001BH
RI&TI 0023H
TF2 & EXF2 002BH
In addition, for external interrupts, pins INTO and INTI (P3.2 and P3.3) must be set to I, and depending on whether
the interrupt is to be level or transition activated, bits ITO or ITI in the TCON register may need to be set to 1.
ITx = a level activated
ITx = 1 transition activated
IE: INTERRUPT ENABLE REGISTER. BIT ADDRESSABLE.
If the bit is 0, the corresponding interrupt is disabled. If the bit is I, the corresponding interrupt is enabled.
EA ET2 ES ET1 EX1 ETO EXO
EA IE.7 Disables all interrupts. If EA = 0, no interrupt will be acknowledged. If EA = I, each interrupt
source is individually enabled or disabled by setting or clearing its enable bit.
IE.6 Not implemented, reserved for future use.'
ET2 IE. 5 Enable or disable the Timer 2 overflow or capture interrupt (8052 only).
ES IE.4 Enable or disable the serial port interrupt.
ETI IE. 3 Enable or disable the Timer I overflow interrupt.
EXI IE.2 Enable or disable External Interrupt 1.
ETO IE. I Enable or disable the Timer 0 overflow interrupt.
EXO IE.O Enable or disable External Interrupt O.
'User software should not write Is to reserved bits. These bits may be used in future MCS-51 products to invoke
new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1.
6-13
intJ MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET
ASSIGNING HIGHER PRIORITY TO ONE OR MORE INTERRUPTS:
In order to assign higher priority to an interrupt the corresponding bit in the IP register must be set to 1.
Remember that while an interrupt service is in progress, it cannot be i,nterrupted by a lower or same level interrupt.
PRIORITY WITHIN LEVEL:
Priority within level is only to resolve simultaneous requests of the same priority level.
From high to low, interrupt sources are listed below:
lEO
TFO
lEI
TFI
RI or TI
TF2 or EXF2
IP: INTERRUPT PRIORITY REGISTER. BIT ADDRESSABLE.
If the bit is 0, the corresponding interrupt has a lower priority and if the bit is I the corresponding interrupt has a
higher priority.
PT2 PS PT1 PX1 ,PTO PXO
IP. 7 Not implemented, reserved for future use.'
IP.6 Not implemented, reserved for future use.'
PT2 IP.5 Defines the Timer 2 interrupt priority level (8052 only).
PS IP.4 Defines the Serial Port interrupt priority level.
PTi IP.3 Defines the Timer I interrupt priority level.
PXI IP.2 Defines External Interrupt I priority level.
PTO IP. I °
Defines the Timer interrupt priority level.
PXO IP.O °
Defines the External Interrupt priority level.
'User software should not write Is to reserved bits. These bits may be used in future MeS-51 products to invoke
new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1.
6-14
inter MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
TCON: TIMER/COUNTER CONTROL REGISTER. BIT ADDRESSABLE.
TF1 TR1 TFO TRO IE1 IT1 lEO ITO
TFI TCON.7 Timer I overflow flag. Set by hardware when the Timer/Counter I overflows. Cleared by hard-
ware as processor vectors to the interrupt service routine.
TRI TCON. 6 Timer I run control bit. Set/cleared by software to turn Timer/Counter ION/OFF.
TFO TCON.5 Timer 0 overflow flag. Set by hardware when the Timer/Counter 0 overflows. Cleared by hard-
ware as processor vectors to the service routine.
TRO TCON.4 Timer 0 run control bit. Set/cleared by software to turn Timer/Counter 0 ON/OFF.
lEI TCON.3 External Interrupt 1 edge flag. Set by hardware when External Interrupt edge is detected.
Cleared by hardware when interrupt is processed.
ITI TCON. 2 Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered
External Interrupt.
lEO TCON. 1 External Interrupt 0 edge flag. Set by hardware when External Interrupt edge detected. Cleared
by hardware when interrupt is processed.
ITO TCON.O Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered
External Interrupt.
TMOD: TIMER/COUNTER MODE CONTROL REGISTER. NOT BIT
ADDRESSABLE.
I
\
GATE CIT M1 MO I
7\
GATE CIT M1 MO
7
I
TIMER 1 TIMER 0
GATE When TRx (in TCON) is set and GATE = 1, TIMER/COUNTERx will run only while INTx pin is high
(hardware control). When GATE = 0, TIMER/COUNTERx will run only while TRx = 1 (software
control).
cif Timer or Counter selector. Cleared for Timer operation (input from internal system clock). Set for Coun-
ter operation (input from Tx input pin).
MI Mode selector bit. (NOTE 1)
MO Mode selector bit. (NOTE I)
NOTE 1:
M1 ,",0 Operating Mode
o o o 13-bit Timer (MCS-48 compatible)
o 1 1 16-bit Timer/Counter
o 2 8-bit Auto-Reload Timer/Counter
3 (Timer 0) TLO is an 8-bit Timer/Counter controlled by the standard Timer 0
control bits, THO is an 8-bit Timer and is controlled by Timer 1 control bits.
3 (Timer 1) Timer/Counter 1 stopped.
6-15
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
TIMER SET-UP
Tables 3 through 6 give some values for TMOD which can be used to set up Timer 0 in different modes.
It is assumed that only one timer is being used at a time. If it is desired to run Timers 0 and I simultaneously, in any
mode, the value in TMOD for Timer 0 must be ORed with the value shown for Timer I (Tables 5 and 6).
For example, if it is desired to run Timer 0 in mode I GATE (external control), and Timer I in mode 2 COUNTER,
then the value that must be loaded into TMOD is 69H (09H from Table 3 ORed with 60H from Table 6).
Moreover, it is assumed that the user, at this point, is not ready to turn the timers on and will do that at a different
point in the program by setting bit TRx (in TCON) to I.
TIMER/COUNTER 0
AsaTimer:
Table 3
TMOD
TIMER 0 INTERNAL EXTERNAL
MODE
FUNCTION CONTROL CONTROL
(NOTE 1) (NOTE 2)
0 13-bit Timer OOH 08H
1 16-bit Timer 01H 09H
2 8-bit Auto-Reload 02H OAH
3 two 8-bit Timers 03H OSH
As a Counter:
Table 4
TMOD
COUNTER 0 INTERNAL EXTERNAL
MODE
FUNCTION CONTROL CONTROL
(NOTE 1) (NOTE 2)
0 13-bit Timer 04H OCH
1 16-bit Timer OSH OOH
2 8-bit Auto-Reload 06H OEH
3 one 8-bit Counter 07H OFH
NOTES:
1. The Timer is turned ON/OFF by setting/clearing bit TRO in the software.
2. The Timer is turned ON/OFF by the 1 to 0 transition on INTO (P3.2) when TRO =
(hardware control).
6-16
inter MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
TIMER/COUNTER 1
As a Timer:
Table 5
TMOD
TIMER 1 INTERNAL EXTERNAL
MODE
FUNCTION CONTROL CONTROL
(NOTE 1) (NOTE 2)
0 13-bit Timer OOH BOH
1 16-bit Timer 10H 90H
2 B-bit Auto-Reload 20H AOH
3 does not run 30H BOH
As a Counter:
Table 6
TMOD
COUNTER 1 INTERNAL EXTERNAL
MODE
FUNCTION CONTROL CONTROL
(NOTE 1) (NOTE 2)
0 13-bit Timer 40H COH
1 16-bit Timer 50H DOH
2 B-bit Auto-Reload 60H EOH
3 not available - -
NOTES:
1. The Timer is turned ON/OFF by selting/c1earing bit TR1 in the software.
2. The Timer is turned ON/OFF by the 1 to 0 transition on INT1 (P3.3) when TR1 = 1
(hardware control).
6-17
infef MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
T2CON: TIMER/COUNTER 2 CONTROL REGISTER. BIT ADDRESSABLE
8052 Only
I TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 I
TF2 T2CON.7 Timer 2 overflow flag set by hardware and cleared by software. TF2 cannot be set when
either RCLK = 1 or CLK = 1
EXF2 T2CON. 6 Timer 2 .externalflag set when either a capture or reload is caused by a negative transition on
T2EX, and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU
to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software.
RCLK T2CON. 5 Receive clock flag. When set, causes the Serial Port to use Timer 2 overflow pulses for its
receive clock in modes 1 & 3. RCLK = 0 causes Timer 1 overflow to be used for the receive
clock.
TLCK T2CON. 4 Transmit clock flag. When set, causes the Serial Port to use Timer 2 overflow pulses for its
transmit clock in modes 1 & 3. TCLK = 0 causes Timer 1 overflows to be used for the
transmit clock.
EXEN2 T2CON. 3 Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of
negative transition on T2EX if Timer 2 is not being used to clock the Serial Port.'
EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
TR2 T2CON.2 Software START/STOP control for Timer 2. A logic 1 starts the. Timer.
C/T2 T2CON. 1 Timer or Counter select.
o = Internal Timer.. 1 = External Event Counter (faIling edge triggered).
CP/RL2 T2CON.O Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if
EXEN2 = 1. When cleared, Auto-Reloads will occur either with Timer 2 overflows or'
negative transitions.at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1,
this bit is ignored and the Timer is forced to Auto-Reload on Timer 2 overflow.
6-18
infef MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET
TIMER/COUNTER 2 SET-UP
Except for the baud rate generator mode, the values given for T2CON do not include the setting of the TR2 bit.
Therefore, bit TR2 must be set, separately, to turn the Timer on.
As a Timer:
Table 7
T2CON
MODE INTERNAL EXTERNAL
CONTROL CONTROL
(NOTE 1) (NOTE 2)
16-bit Auto-Reload OOH OSH
16-bit Capture 01H 09H
BAUD rate generator receive &
transmit same baud rate 34H 36H
receive only 24H 26H
transmit only 14H 16H
As a Counter:
TableS
TMOD
MODE INTERNAL EXTERNAL
. CONTROL CONTROL
(NOTE 1) (NOTE 2)
16-bit Auto-Reload 02H OAH
16-bit Capture 03H OBH
NOTES:
1. Capture/Reload occurs only on Timer/Counter overflow.
2. Capture/Reload occurs on Timer/Counter overflow and a 1 to 0 transition on T2EX
(P1.1) pin except when Timer 2 is used in the baud rate generating mode.
6-19
intJ MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
SCON: SERIAL PORT CONTROL REGISTER. BIT ADDRESSABLE.
SMO SM1 SM2 REN TB8 RB8 TI RI
SMO SCON. 7 Serial Port mode specifier. (NOTE I).
SMI SCON.6 Serial Port mode specifier. (NOTE 1).
SM2 SCON. 5 Enables the multiprocessor communication feature in modes 2 & J. In mode 2 or 3, if SM2 is set
to 1 then RI will not be activated if the received 9th data bit (RBS) is O. In mode I, if SM2 = I
then RI will not be activated if a valid stop bit was not received. In mode 0, SM2 should be O.
(See Table 9).
REN SCON. 4 Set/Clean;d by software to Enable/Disable reception.
TBS SCON. 3 The 9th bit that will be transmitted in modes 2 & 3. Set/Cleared by software.
RB8 SCON. 2 In modes 2 & 3, is the 9th data bit that was received. In mode 1, if SM2 = 0, RBS is the stop'bit
that was received. In mode 0, RBS is not used. '
TI SCON. 1 Transmit interrupt flag. Set by hardware at the end of the Sth bit time in mode 0, or at the
beginning of the stop bit in the other modes. Must be cleared by software.
RI SCON.O Receive interrupt flag. Set by hardware at the end of the Sth bit time in mode 0, or halfway
through the stop bit time in the other modes (except see SM2). Must be cleared by software.
NOTE 1:
SMO SM1 Mode Description Baud Rate
o 0 0 SHIFT REGISTER Fosc.l12
o 1 1 8-Bit UART Variable
1 0 2 9-Bit UART Fosc.l64 OR
Fosc.l32
3 9-Bit UART Variable
SERIAL PORT SET-UP:
Table 9
MODE SeON SM2 VARIATION
0 10H
Single Processor
1 SOH
Environment
2 90H
(5M2 = 0)
~ DOH
0 NA
Multiprocessor
1 70H
Environment
2 BOH
(5M2 = 1)
3 FOH
GENERATING BAUD RATES
Serial Port in Mode 0:
Mode 0 has a fixed baud rate which is 1/12 of the oscillator frequency, To run the serial port in this mode none of
the Timer/Counters need to be set up. Only the SCON register needs to be defined.
Osc Freq
Baud Rate = --1-2-
Serial Port in Mode 1:
Mode 1 has a variable baud rate. The baud rate can be generated by either Timer 1 or Timer 2 (8052 only).
6-20
MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
USING TIMER/COUNTER 1 TO GENERATE BAUD RATES:
For this purpose, Timer 1 is used in mode 2 (Auto-Reload). Refer to Timer Setup section of this chapter.
d K x Oscillator Freq.
Bau Rate = 32 x 12 x [256 - (TH1)]
If SMOD = 0, then K = 1.
If SMOD = I, then K = 2. (SMOD is the PCON register).
Most of the time the user knows the baud rate and needs to know the reload value for TH1.
Therefore, the equation to calculate THI can be written as:
TH1 = 256 _ K x Osc Freq.
384 x baud rate
THI must be an integer value. Rounding offTHI to the nearest integer may not produce the desired baud rate. In
this case, the user may have to choose another crystal frequency.
Since the PCON register is not bit addressable, one way to set the bit is logical ORing the PCON register. (ie, ORL
PCON, # 80H). The address of PCON is 87H.
USING TIMER/COUNTER 2 TO GENERATE BAUD RATES:
For this purpose, Timer 2 must be used in the baud rate generating mode. Refer to Timer 2 Setup Table in this
chapter. If Timer 2 is being clocked through pin T2 (Pl.O) the baud rate is:
Baud Rate = Timer 2 Overflow Rate
16 '
And if it is being clocked internally the baud rate is:
. BuR te _ Osc Freq
a d a - 32 x [65536 - (RCAP2H. RCAP2L)]
To obtain the reload value for RCAP2H and RCAP2L the above equation can be rewritten as:
RCAP2H, RCAP2L = 65536 _ o~c F~e~
32 x au ate
SERIAL PORT IN MODE 2:
The baud rate is fixed in this mode and is '132 or '164 of the oscillator frequency depending on the value of the SMOD
bit in the PCON register.
In this mode none of the Timers are used and the clock comes from the internal phase 2 clock.
SMOD = I, Baud Rate = '132 Osc Freq.
SMOD = 0, Baud Rate = '/64 Osc Freq.
To set the SMOD bit: ORL PCON, # SOH. The address of PCON is 87H.
SERIAL PORT IN MODE 3:
The baud rate in mode 3 is variable and sets up exactly the same as in mode 1.
6-21
inter MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
MCS®-51 INSTRUCTION SET
Table 10. 8051 Instruction Set Summary
Interrupt Response Time: Refer to Hardware De- Oscillator
Mnemonic Description Byte
scription Chapter. Period
Instructions that Affect Flag Settings(1) ARITHMETIC OPERATIONS
ADD A,Rn Add. register to 12
Instruction Flag Instruction Flag Accumulator
C OV AC C OV AC ADD A,direct Add direct byte to 2 12
ADD X X X CLRC 0 Accumulator
ADDC X X X CPLC X ADD A,@Ri Add indirect RAM 12
SUSS X X X ANLC,bit X to Accumulator
MUL 0 X ANLC,/bit X ADD A,#data Add immediate 2 12
DIV 0 X ORLC,bit X data to
DA X ORLC,bit X Accumulator
RRC X MOVC,bit X AD DC A,Rn Add register to 12
RLC X CJNE X Accumulator
SETSC with Carry
(l)Note that operations on SFR byte address 208 or ADDC A,direct Add direct byte to 2 12
bit addresses 209-215 (i.e., the PSW or bits in the Accumulator
PSW) will also affect flag settings. with Carry
ADDC A,@Ri Add indirect 12
Note on instruction set and addressing modes: RAM to
Rn ,-- Register R 7 - RO of the currently se- Accumulator
lected Register Bank. with Carry
direct - 8-bit internal data location's address. AD DC A,#data Add immediate 2 12
This could be an Internal Data RAM data to Acc
location (0-127) or a SFR [i.e., I/O with Carry
port, control register, status register, SUSS A,Rn Subtract Register 12
etc. (128-255)]. from Acc with
@Ri - 8-bit internal data RAM location (0- borrow
255) addressed indirectly through reg- SUSS A,direct Subtract direct 2 12
ister RI or RO. byte from Ace
# data - 8-bit constant included in instruction. with borrow
#data 16 - 16-bit constant included in instruction. SUSS A,@Ri Subtract indirect 12
addr 16 - 16-bit destination address. Used by RAM from ACC
LCALL & UMP. A branch can be with borrow
anywhere within the 64K-byte Pro- SUSS A,#data Subtract 2 12
gram Memory address space. immediate data
addr 11 - ll-bit destination address. Used by from Acc with
ACALL & AJMP. The branch will be borrow
within the same 2K-byte page of pro- INC A Increment 12
gram memory as the first byte of the Accumulator
following instruction. INC Rn Increment register 1 12
rei - Signed (two's complement) 8-bit offset INC direct Increment direct 2 12
byte. Used by SJMP and all condition- byte
al jumps. Range is -128 to + 127 INC @Ri Increment direct 12
bytes relative to first byte of the fol- RAM
lowing instruction. DEC A Decrement 12
bit - Direct Addressed bit in Internal Data Accumulator
RAM or Special Function Register. DEC Rn Decrement 12
Register
DEC direct Decrement direct 2 12
byte
DEC @Ri Decrement 12
indirect RAM
Ali mnemonics copyrighted @Intel Corporation 1980
6-22
inter MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
Table 10. 8051 Instruction Set Summary (Continued)
Oscillator Oscillator
Mnemonic Description Byte Mnemonic Description Byte
Period Period
ARITHMETIC OPERATIONS (Continued) LOGICAL OPERATIONS (Continued)
INC DPTR Increment Data 24 RL A Rotate 12
Pointer Accumulator Left
MUL AB Multiply A & B 48 RLC A Rotate 12
DIV AB DivideAbyB 48 Accumulator Left
DA A Decimal Adjust 12 through the Carry
Accumulator RR A Rotate 12
LOGICAL OPERATIONS Accumulator
ANL A.Rn AND Register to 12 Right
Accumulator RRC A Rotate 12
ANL A,direct AND direct byte 2 12 Accumulator
to Accumulator Right through
ANL A,@Ri AND indirect 12 the Carry
RAM to SWAP A Swap nibbles 12
Accumulator within the
ANL A,#data AND immediate 2 12 Accumulator
data to DATA TRANSFER
Accumulator. MOV A,Rn Move 12
ANL direct,A AND Accumulator 2 12 register to
to direct byte Accumulator
ANL direct, # data AND immediate 3 24 MOV A.direct Move direct 2 12
data to direct byte byte to
ORL A,Rn OR register to 12 Accumulator
Accumulator MOV A,@Ri Move indirect 12
ORL A,direct OR direct byte to 2 12 RAM to
Accumulator Accumulator
ORL A,@Ri OR indirect RAM 12 MOV A,#data Move 2 12
to Accumulator immediate
ORL A,#data OR immediate 2 12 data to
data to Accumulator
Accumulator MOV Rn,A Move 12
ORL direct,A OR Accumulator 2 12 Accumulator
to direct byte to register
ORL direct, # data OR immediate 3 24 MOV Rn,direct Move direct 2 24
data to direct byte byte to
XRL A,Rn Exclusive·OR 12 register
register to MOV Rn,#data Move 2 12
Accumulator immediate data
XRL A,direct Exclusive·OR 2 12 to register
direct byte to MOV direct,A Move 2 12
Accumulator Accumulator
XRL A,@Ri Exclusive·OR 12 to direct byte
indirect RAM to MOV direct,Rn Move register 2 24
Accumulator to direct byte
XRL A,#data Exclusive·OR 2 12 MOV direct,direct Move direct 3 24
immediate data to byte to direct
Accumulator MOV direct,@Ri Move indirect 2 24
XRL direct,A Exciusive·OR 2 12 RAM to
Accumulator to direct byte
direct byte MOV direct, # data Move 3 24
XRL direct, # data Exciusive·OR 3 24 immediate data
immediate data to direct byte
to direct byte MOV @Ri,A Move 12
CLR A Clear 12 Accumulator to
Accumulator indirect RAM
CPL A Complement 12 All mnemonics copyrighted ©Intel Corporation 1980
Accumulator
6-23
inter MCS@·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
Table 10.8051 Instruction Set Summary (Continued)
Oscillator Oscillator
Mnemonic Description Byte Mnemonic Description Byte
Period Period
DATA TRANSFER (Continued) BOOLEAN VARIABLE MANIPULATION
MOV @Ri,direct Move direct 2 24 CLR C Clear Carry 1 12
byte to CLR bit Clear direct bit 2 12
indirect RAM SETB C Set Carry 1 ·12
MOV @Ri,#data Move 2 12 SETB bit Set direct bit 2 12
immediate CPL C Complement 12
data to Carry
indirect RAM CPL bit Complement 2 . 12
MOV DPTR,#datal6 Load Data 3 24 direct bit
Pointer with a ANL C,bit AND direct bit 2 24
IS-bit constant to CARRY
MOVC A,@A+DPTR Move Code 24 ANL C,Ibit AND complement 2 24
. byte relative to of direct bit
DPTRtoAcc to Carry
MOVC A,@A+PC Move Code 24 ORL C,bit OR direct bit 2 24
byte relative to to Carry
PCtoAcc ORL C,Ibit OR complement 2 24
MOVX A,@Ri Move 24 of direct bit
External to Carry
RAM (8·bit MOV C,bit Move direct bit 2 12
addr)to Acc to Carry
MOVX A,@DPTR Move 24 MOV bit,C Move Carry to 2 24
External direct bit
RAM (16·bit JC rei Jump if Carry 2 24
addr)toAcc is set
MOVX @Ri,A Move Acc to 24 JNC rei Jump if Carry 2 24
External RAM not set
(8·bit addr) JB bit,rel Jump if direct 3 24
MOVX @DPTR,A Move Accto 24 Bit is set
External RAM JNB bit,rel Jump if direct 3 24
(IS-bit addr) Bit is Not set
PUSH direct Push direct 2 24 JBC bit, rei Jump if direct 3 24
byte onto Bit is set &
stack clear bit
POP direct Pop direct 2 24 PROGRAM BRANCHING
byte from ACALL addrl1 Absolute 2 24
stack Subroutine
XCH A,Rn Exchange 12 Call
register with LCALL addr16 Long 3 24
Accumulator Subroutine
XCH A,direct Exchange 2 12 Call
direct byte RET Return from 24
with Subroutine
Accumulator RETI Return from 24
XCH A,@Ri Exchange 12 interrupt
indirect RAM AJMP addrll AbSolute 2 24
with Jump
Accumulator WMP addr16 Long Jump 3 24
XCHD A,@Ri Exchange low- 12 SJMP rei Short Jump 2 24
order Digit (relative addr)
indirect RAM All mnemonics copyrighted @Intel Corporation 1980
withAcc
6-24
inter MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
Table 10. 8051 Instruction Set Summary (Continued)
Oscillator Oscillator
Mnemonic Description Byte Mnemonic Description Byte
Period Period
PROGRAM BRANCHING (Continued) PROGRAM BRANCHING (Continued)
JMP @A+DPTR Jump indirect 24 CJNE Rn, #data,rel Compare 3 24
relative to the immediate to
DPTR register and
JZ rei Jump if 2 24 Jump if Not
Accumulator Equal
is Zero CJNE @Ri,#data,rel Compare 3 24
JNZ rei Jump if 2 24 immediate to
Accumulator indirect and
is Not Zero Jump if Not
CJNE A,direct,rel Compare 3 24 Equal
direct byte to DJNZ Rn,rel Decrement 2 24
Acc and Jump register and
if Not Equal Jump if Not
CJNE A, # data,rel Compare 3 24 Zero
immediate to DJNZ direct,rel Decrement 3 24
Acc and Jump direct byte
if Not Equal and Jump if
Not Zero
NOP No Operation 12
All mnemonics copyrighted © Intel Corporation 1980
6-25
intJ MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
Table 11. Instruction Opcodes In Hexadecimal Order
Hex Number Hex Num~er
Mnemonic Operands Mnemonic Operands
Code of Bytes Code of Bytes
00 1 NOP 33 1 RLC A
01 2 AJMP code addr 34 2 ADDC A,#data
02 3 LJMP code addr 35 2 ADDC A,data addr
03 1 RR A 36 1 ADDC A,@RO
04 1 INC A 37 1 ADDC A,@R1
05 2 INC data addr 38 1 AD DC A,RO
06 1 INC @RO 39 1 ADDC A,R1
07 1 INC @R1 3A 1 ADDC A,R2
08 1 INC RO 38 1 ADDC A,R3
09 1 INC R1 3C 1 ADDC A,R4
OA 1 INC R2 3D 1 ADDC A,R5
08 1 INC R3 3E 1 ADDC A,R6
OC 1 INC R4 3F 1 ADDC A,R7
00 1 INC R5 40 2 JC code addr
OE 1 INC R6 41 2 AJMP code addr
OF 1 INC R7 42 2 ORL data addr,A
10 3 J8C bit addr, code addr 43 3 ORL data addr,#data
11 2 ACALL code addr 44 2 ORL A,#data
12 3 ' LCALL code addr 45 2 ORL A,data addr
13 1 RRC A 46 1 ORL A,@RO
14 1 DEC A 47 1 ORL A,@R1
15 2 DEC data addr 48 1 ORL A,RO
16 1 DEC @RO 49 1 ORL A,R1
17 1 DEC @R1 4A 1 ORL A,R2
18 1 DEC RO 48 1 ORL A,R3
19 1 DEC R1 4C 1 ORL A,R4
1A 1 DEC R2 40 1 ORL A,R5
18 1 DEC R3 4E 1 ORL A,R6
1C 1 DEC R4 4F 1 ORL A,R7
10 1 DEC R5 50 2 JNC code addr
1E 1 DEC R6 51 2 ACALL code addr
1F 1 DEC R7 52 2 ANL dataaddr,A
20 3 J8 bit addr, code addr 53 3 ANL data addr, # data
21 2 AJMP codeaddr 54 2 ANL A,#data
22 1 RET 55 2 ANL A,dataaddr
23 1 RL A 56 1 ANL A,@RO
24 2 ADD A,#data 57 1 ANL A,@R1
25 2 ADD A,data addr 58 1 ANL A,RO
26 1 ADD A,@RO 59 1 ANL A,R1
27 1 ADD A,@R1 5A 1 ANL A,R2
28 1 ADD A,RO 58 1 ANL A,R3
29 1 ADD A,R1 5C 1 ANL A,R4
2A 1 ADD A,R2 50 1 ANL A,R5
28 1 ADD A,R3 5E 1 ANL A,R6
2C 1 ADD A,R4 5F 1 ANL A,R7
20 1 ADD A,R5 60 2 JZ code addr
2E 1 ADD A,R6 61 2 AJMP code addr
2F 1 ADD A,R7 62 2 XRL data addr,A
30 3 JN8 bit addr, code addr 63 3 XRL data addr, # data
31 2 ACALL codeaddr 64 2 XRL A,#data
32 1 RETI 65 2 XRL A,data addr
6-26
inter MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET
Table 11. Instruction Opcodesin Hexadecimal Order (Continued)
Hex Number Hex Number
,Mnemonic Operands Mnemonic Operands
Code of Bytes Code of Bytes
66 1 XRL A,@RO 99 1 SU88 A,R1
67 1 XRL A,@R1 9A 1 SUB8 A,R2
68 1 XRL A,RO 98 1 SU8B A,R3
69 1 XRL' A,R1 9C 1 SU8B A,R4
6A 1 XRL A,R2 90 1 SU8B A,R5
68 1 XRL A,R3 9E 1 SU88 A,R6
6C 1 XRL A,R4 9F 1 SU8B A,R7
60 1 XRL A,R5 AO 2 ORL , C,Ibit addr
6E 1 XRL A,R6 A1 2 AJMP codeaddr
6F 1 XRL A,R7 A2 2 MOV C,bitaddr
70 2 JNZ codeaddr A3 1 INC OPTR
71 2 ACALL codeaddr A4 1 MUL AB
72 2 CAL C,bitaddr A5 'reserved
73 1 JMP @A+OPTR A6 2 MOV @RO,dataaddr
74 2 MOV A,#data A7 2 MOV @R1,data addr
75 3 MOV data addr, # data A8 2 MOV RO,dataaddr
76 2 MOV @RO,#data A9 2 MOV R1,dataaddr
77 2 MOV @R1,#data AA 2 MOV R2,data addr
78 2 MOV RO;#data A8 2 MOV R3.data addr
79 2 MOV R1,#data AC 2 MOV R4,data addr
7A 2 MOV R2,#data AD 2 MOV R5,data addr
78 2 MOV R3,#data AE 2 MOV R6,data addr
7C 2 MOV R4,#data AF 2 MOV R7,data addr
70 2 MOV R5,#data 80 2 ANL C,/bitaddr
7E 2 MOV R6,#data 81 2 ACALL code addr
7F 2 MOV R7,#data 82 2 CPL bitaddr
80 2 SJMP codeaddr 83 1 CPL C
81 2 AJMP codeaddr 84 3 CJNE A,#data,code addr
82 2 ANL C,bitaddr 85 3 CJNE A,data addr,code addr
83 1 MOVC A,@A+PC 86 3 CJNE @RO,#data,codeaddr
84 1 OIV A8 87 3 CJNE @R1, # data,code addr
85 3 MOV data addr, data addr B8 3 CJNE RO, # data, code addr
86 2 MOV data addr,@RO B9 3 CJNE R1, # data,code addr
87 2 MOV data addr,@R1 8A 3 CJNE R2, # data,code addr
88 2 MOV data addr,RO 88 3 CJNE R3, # data, code addr
89 2 MOV data addr,R1 BC 3 CJNE R4, # data,code addr
8A 2 MOV data addr,R2 80 3 CJNE R5, # data, code addr
8B 2 MOV data addr,R3 8E 3 CJNE R6, # data,code addr
8C 2 MOV data addr,R4 8F 3 CJNE R7, #data,code addr
80 2 MOV data addr,R5 CO 2 PUSH data addr
8E 2 MOV data addr,R6 C1 2 AJMP code addr
8F 2 MOV data addr,R7 C2 2 CLR bitaddr
90 3 MOV OPTR,#data C3 1 CLR C
91 2 ACALL codeaddr C4 1 SWAP A
92 2 MOV bitaddr,C C5 2 XCH A,dataaddr
93 1 MOVC A,@A+OPTR C6 1 XCH A,@RO
94 2 SU88 A,#data C7 1 ' XCH A,@R1
95 2 SU8B A,dataaddr C8 1 XCH A,RO
96 1 SU88 A,@RO C9 1 XCH A,R1
97 1 SU8B A,@R1 CA 1 XCH A,R2
98 1 SU8B A,RO C8 1 XCH A,RS
6-27
intJ MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
Table 11 Instruction Opcodes in Hexadecimal Order (Continued)
Hex Number Hex Number
Mnemonic Operands. Mnemonic Operands
Code of Bytes Code of Bytes
CC 1 XCH A,R4 E6 1 MOV A,@RO
CD 1 XCH A,R5 E7 1 MOV A,@R1
CE 1 XCH A,R6 E8 1 MOV A,RO
CF 1 XCH A,R7 E9 1 MOV A,R1
DO 2 POP dataaddr EA 1 MOV A,R2
01 2 ACAll code addr EB 1 MOV A,RS
02 2 SETB bitaddr EC 1 MOV A,R4
OS 1 SETB C ED 1 MOV . A,R5
04 1 DA A EE 1 MOV A,R6
05 S ·DJNZ data addr,code addr EF 1 MOV A,R7
06 1 XCHD A,@RO FO 1 MOVX. .@DPTR,A
07 1 XCHD A,@R1 F1 2 ACAll codeaddr
08 2 DJNZ RO,code liddr F2 1 MOVX @RO,A
09 2 OJNZ R1,code addr FS 1 MOVX '@R1,A
OA 2 OJNZ R2,code addr F4 1 CPl A
DB 2 DJNZ RS,code addr F5 ' 2 MOV dataaddr,A
DC 2' OJNZ R4,code addr F6 1 MOV @RO,A
DO 2 DJNZ R5,code addr F7 1 MOV @R1,A
DE 2 DJNZ R6,code liddr F8 1 MOV RO,A
OF ·2 DJNZ R7,code addr F9
, 1 MOV R1,A
EO 1 MOVX A,@DPTR FA 1 MOV' R2,A
E1 2 AJMP code addr FB 1 MOV RS,A
E2 1 MOVX A,@RO FC 1 MOV R4,A
ES 1 MOVX A,@R1 FD 1 MOV R5,A
E4 1 ClF! A FE 1 MOV R6,A
E5 2 MOV A,dataaddr FF 1 MOV R7,A
6-28
intJ MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
INSTRUCTION DEFINITIONS
ACALL addr11
Function: Absolute Call
Description: ACALL unconditionally calls a subroutine located at the indicated address. The instruction
increments the PC twice to obtain the address of the following instruction, then pushes the
16-bit result onto the stack (low-order byte first) and incrementsthe Stack Pointer twice. The
destination address is obtained by successively concatenating the five high-order bits of the
incremented PC, opcode bits 7-5, and the second byte of the instruction. The subroutine called
must therefore start within the same 2K block of the prpgram memory as the first byte of the
instruction following ACALL. No flags are affected.
Example: Initially SP equals 07H. The label "SUBRTN" is at program memory location 0345 H. After
executing the instruction,
ACALL SUBRTN
at location 0123H, SP will contain 09H, internal RAM locations OSH and 09H will contain
25H and OlH, respectively, and the PC will contain 0345H.
Bytes: 2
Cycles: 2
Encoding: I a 10 a9 as 1 000 1 a7 a6 a5 a4 a3 a2 a1 aO
Operation: ACALL
(PC) ~ (PC) + 2
(SP) - , (SP) + 1
«SP)) ~ (PC7.0)
(SP) ~ (SP) + 1
«SP)) ~ (PClS-S)
(PCw_o) ~ page address
6-29
inter MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
ADD A, < src-byte >
Function: Add
Description: ADD adds the byte variable indicated to the Accumulator, leaving the result in the Accumula-
tor. The carry and auxiliary-carry flags are set, respectively, if there is a carry-out from bit 7 or
bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an
overflow occured.
OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not bit 6;
otherwise OV is cleared. When adding signed integers, OV indicates a negative number pro-
duced as the sum of two positive operands, or a positive sum from two negative operands.
Four source operand addressing modes are allowed: register, direct, register-indirect, or imme-
diate.
Example: The Accumulator holds OC3H (llOOOOllB) and register 0 holds OAAH (10 1010 iOB). The
instruction,
ADD A,RO
wi11leave 6DH (01 101 101B) in the Accumulator with the AC flag cleared and both the carry
flag and 0 V set to 1.
ADD A,Rn
Bytes:
Cycles:
Encoding: I 00 1 0 1 r r r
Operation: ADD
(A) +-- (A) + (Rn)
ADD A,direct
Bytes: 2
Cycles:
Encoding: I0 0 0 o1 0 1 direct address
Operation: ADD
(A) +-- (A) + (direct)
6-30
intJ MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
ADD A,@Ri
Bytes:
Cycles:
Encoding: I0 0 1 0 011
Operation: ADD
(A) - (A) + «Rj»
ADD A,#data
Bytes: 2
Cycles:
Encoding: I 00 1 0 o100 immediate data
Operation: ADD
(A) - (A) + # data
ADDC A, < src-byte >
Function: Add with Carry
Description: ADDC simultaneously adds the byte variable indicated, the carry flag and the Accumulator
contents, leaving the result in the Accumulator. The carry and auxiliary-carry flags are set,
respectively, if there is a carry-out from bit 7 or bit 3, and cleared otherwise. When adding
unsigned integers, the carry flag indicates an overflow occured.
OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not out of
bit 6; otherwise OV is cleared. When adding signed integers, OV indicates a negative number
produced as the sum of two positive operands or a positive sum from two negative operands.
Four source operand addressing modes are allowed: register, direct, register-indireCt, or imme-
diate.
Example: The Accumulator holds OC3H (J lOOOOllB) and register 0 holds OAAH (IOlOlOlOB) with the
carry flag set. The instruction,
ADDC A,RO
will leave 6EH (011011 lOB) in the Accumulator with AC cleared and both the Carry flag and
OV set to 1.
6-31
inter MCS@·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
ADDC A,Rn
Bytes:
Cycles:
Encoding: LI_o_o_1_--,-_1_r_r_r...J1
Operation: ADDC
(A) +- (A) + (C) + (Rn)
ADDC A,dlrect
Bytes: 2
Cycles:
Encoding: 1,--o_o_1_-,,-_0_1_0_1-.1 direct address 1
Operation: ADDC
(A) +- (A) + (C) + (direct)
ADDC A,@RI
Bytes:
Cycles:
Encoding: I0 0 1 1 0 1 1. i 1
Operation: ADDC
(A) +- (A) + (C) + «Rj})
ADDC A,#data
Bytes: 2
Cycles:
Encoding: 1001101001 immediate data 1
Operation: ADDC
(A) +- (A) + (C) + #data
6·32
inter MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
AJMP addr11
Function: Absolute Jump
Description: AJMP transfers program execution to the indicated address, which is formed at run-time by
concatenating the high-order five bits of the PC (after incrementing the PC twice), opcode bits
7-5, and the second byte of the instruction. The destination must therefore be within the same
2K block of program memory as the first byte of the instruction following AJMP.
Example: The label "JMPADR" is at program memory location 0123H. The instruction,
AJMP JMPADR
is at location 0345H and will load the PC with 0123H.
Bytes: 2
Cycles: 2
Encoding: I a10 a9 a8 0 0 0 0 1 a7 a6 a5 a4 a3 a2 a1 aO
Operation: AJMP
(PC) - (PC) + 2
(PClO-O) - page address
ANL < dest-byte > , < src-byte >
Function: Logical-AND for byte variables
Description: ANL performs the bitwise logical-AND operation between the variables indicated and stores
the results in the destination variable. No flags are affected.
The two operands allow six addressing mode combinations. When the destination is the Accu-
mulator, the source can use register, direct, register-indirect, or immediate addressing; when
the destination is a direct address, the source can. be the Accumulator or immediate data.
Note: When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.
Example: If the Accumulator holds OC3H (1 100001 IB) and register 0 holds 55H (OIOIOIOIB) then the
instruction,
ANL A,RO
will leave 41H (OlOOOOOlB) in the Accumulator.
When the destination is a directly addressed byte, this instruction will clear combinations of
bits in any RAM location or hardware register. The mask byte determining the pattern of bits
to be cleared would either be a constant contained in the instruction or a value computed in
the Accumulator at run-time. The instruction,
ANL Pl,#Olll0011B
will clear bits 7, 3, and 2 of output port 1.
6-33
MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
ANL A,Rn
Bytes:
Cycles: I
Encoding:
1 01
o1 1 r r r
Operation: ANL
(A) -- (A) II (Rn)
ANL A,direct
Bytes: 2
Cycles:
Encoding:
1 01
o1 o1 0 1 direct address
Operation: ANL
(A) -- (A) II (direct)
ANL A,@Ri
Bytes:
Cycles:
Encoding:
1 01
o1 011
Operation: ANL
(A) -- (A) II «Ri»
ANL A,#data
Bytes: 2
Cycles:
Encoding: I0 1 o 1 o1 0 0 immediate data
Operation: ANL
(A) -- (A) II #data
ANL direct,~
Bytes: 2
Cycles:
Encoding: 1 01
o1 001 0 direct address
Operation: ANL
(direct) -- (direct) II (A)
6-34
infef MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
ANL dlrect,#data
Bytes: 3
Cycles: 2
Encoding: I0 1 0 1 0 0 1 1 direct address immediate data
Operation: ANL
(direct) ~ (direct) A #data
ANL C,<src-bit>
Function: Logical-AND forbit variables
Description: If the Boolean value of the source bit is a logical 0 then clear the carry flag; otherwise leave the
carry flag in its current state. A slash ("I") preceding the operand in the assembly language
indicates that the. logical complement of the addressed bit is used as the source value, but the
source bit itself is not affected. No other flags are affected.
Only direct addressing is allowed for the source operand.
Example: Set the carry flag if, and only if, Pl.O = 1, ACC. 7 = 1, and Ov. = 0:
MOV C,Pl.O ;LOAD CARRY WITH INPUT PIN STATE
ANL C,ACC.7 ;AND CARRY WITH ACCUM. BIT 7
ANL C,/OV ;AND WITH INVERSE OF OVERFLOW FLAG
ANL C,bit
Bytes: 2
Cycles: 2
Encoding: I 1 000 001 0 bit address
Operation: ANL
(C) ~ (C) A (bit)
ANL C,/bit
Bytes: 2
Cycles: 2
. Encoding: I1 o1 000 0 bit address
Operation: ANL
(C) ~ (C)A -, (bit)
6-35
intJ MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
CJNE < dest-byte > ,<src-byte> , rei
Function: Compare and Jump if Not Equal.
Description: CJNE compares the magnitudes of the first two operands, and branches if their values are not
equal. The branch destination is computed by adding the signed relative-displacement in the
last instruction byte to the PC, after incrementing the PC to the slilrt of the next instruction.
The carry flag is set if the unsigned integer value of <dest-byte> is less than the unsigned
integer value of <src-byte>; otherwise, the carry is cleared. Neither operand is affected.
The first two operands allow four addressing mode combinations: the Accumulator may be
compared with any directly addressed byte or immediate data, and any indirect RAM location
or working register can be compared with an immediate constant.
Example: The Accumulator contains 34H. Register 7 contains 56H. The first instruction in the se-
quence,
CJNE R7,#60H, NOT_EQ
R7 = 60H.
JC IFR7 < 6OH.
R7> 60H.
sets the carry flag and branches to the instruction at label NOT_EQ. By testing the carry flag,
this instruction determines whether R7 is greater or less than 6OH. . .
If the data being presented to Port I is also 34H, then the instruction,
WAIT: CJNE A,PI,WAIT
clears the carry flag and continues with the next instruction in sequence, since the Accumula-
tor does equal the data read from Pl. (Ifsome other value was being input on PI, the program
will loop at this point until the PI data changes to 34H.)
CJNE A,direct,rel
Bytes: 3
Cycles: 2
Encoding: LI _1_0_1_1--,-_0_1_0_1-, direct address reI. address I,
Operation: (PC) - (PC) + 3
IF (A) < > (direct)
THEN
(PC) - (PC) + relative offtet
IF (A) < (direct)
THEN
(C)-I
ELSE
(C)-O
6-36
inter MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
CJNE A,#data,rel
Bytes: 3
Cycles: 2
Encoding: I1 0 1 1 0 1 0 0 immediate data reI. address
Operation: (PC) ~ (PC) + 3
IF (A) < > data
THEN
(PC) ~ (PC) + relative offset
IF (A) < data
THEN
(C)~ 1
ELSE
(C)~O
CJNE Rn,#data,rel
Bytes: 3
Cycles: 2
Encoding: I1 0 1 1 1 r r r immediate data reI. address
Operation: (PC) ~ (PC) + 3
IF (Rn) < > data
THEN
(PC) ~ (PC) + relative offset
IF (Rn) < data
THEN
(C)~ 1
ELSE
(C)~O
CJNE @Ri,#data,rel
Bytes: 3
Cycles: 2
Encoding: I1 0 1 1 0 1 1 immediate data reI. address
Operation: (PC) ~ (PC) + 3
IF «Ri» < > data
THEN
(PC) ~ (PC) + relative offset
IF «Ri» < data
THEN
(C)~ 1
ELSE
(C)~O
6-37
infef MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
CLR A
Function: Clear Accumulator
Description: The Accumulator is cleared (all bits set on zero). No flags are affected.
Example: The Accumulator contains SCH (0101 I IOOB). The instruction,
CLR A
will leave the Accumulator set to OOH (OOOOOOOOB).
Bytes:
Cycles:
Encoding: I1 1 0 0 1 0 0
Operation: CLR
(A) +- 0
CLR bit
Function: Clear bit
Description: The indicated bit is cleared (reset to zero). No other flags are affected. CLR can operate on the
carry flag or any directly addressable bit.
Example: Port 1 has previously been written with SDH (01011 IOlB). The instruction,
CLR P1.2
will leave the port set to S9H (OIOII00lB).
CLR C
Bytes:
,
Cycles:
Encoding: I1 0 0 0 0 1 1
Operation: CLR
(C) +- 0
CLR bit
Bytes: 2
Cycles:
Encoding: I1 1 0 0 0 0 1 0 bit address
Operation: CLR
(bit) +- 0
6-38
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
CPL A
Function: Complement Accumulator
Description: Each bit of the Accumulator is logically complemented (one's complement). Bits which previ-
ously contained a one are changed to a zero and vice-versa. No flags are affected.
Example: The Accumulator contains SCH (0101 I 100B). The instruction,
CPL A
will leave the Accumulator set to OA3H (lOIOOOIIB).
Bytes:
Cycles:
Encoding: LI_1__1_1--,-_0_1_0_0-,
Operation: CPL
(A) ~-, (A)
CPL bit
Function: Complement bit
Description: The bit variable specified is complemented. A bit which had been a one is changed to zero and
vice-versa. No other flags are affected. CLR can operate on the carry or any directly address-
able bit.
Note: When this instruction is used to modify an output pin, the value used as the original data
. will be read from the output data latch, not the input pin.
Example: Port I has previously been written with SBH (OlOlllOlB). The instruction sequence,
CPL Pl.l
CPL P1.2
will leave the port set to SBH (0101 101 lB).
CPL C
Bytes:
Cycles: 1.
Encoding: ,-1_1_0_1_-,-_0_0_1_1......
Operation: CPL
(C) ~-, (C)
6-39
inter MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
CPL bit
Bytes: 2
Cycles:
Encoding: I1 0 1 1 0 0 1 0 I' bit address
Operation: CPL
(bit) - .., (bit)
DA A
Function: Decimal-adjust Accumulator 'for Addition
Description: DA A adjusts the eight-bit value in the Accumulator resulting from the earlier addition of two
variables (each in packed-BCD format), producing two four-bit digits; Any ADD or ADDC
instruction may have been used to perform the addition.
If Accumulator bits 3-0 are greater than nine (xxxx1010-xxxxl 11 1), or if the AC flag is one,
six is added to the Accumulator producing the proper BCD digit in thc low-order nibble. This
internal addition would set the carry flag if a carry-out of the low-order four-bit field propagat-
ed through all high-order bits, but it would not clear the carry flag otherwise. '
Ifthe carry flag is now set, or ifthe four high-order bits now exceed nine (101Oxxxx-111xxxx),
these high-order bits are incremented by six, producing the proper BCD digit in the high-order
nibble. Again, this would set the carry flag if there was a carry-out of the high-order bits; but
wouldn't clear the carry. The carry flag thus indicates if the sum of the original two BCD
variables is greater than 100, allowing mUltiple precision decimal addition. OV is not affected.
All of this occurs dUring the one instruction cycle. Essentially, this instruction performs the
decimal conversion by adding OOH, 06H, 6OH, or 66H to the Accumulator, depending on
initial Accumulator and PSW conditions.
Note: DA A cannot simply convert a hexadecimal number in the Accumulator to BCD nota-
tion, nor does DA A apply to decimal subtraction.
6-40
inter MCS®-51.PROGRAMMER'S GUIDE AND INSTRUCTION SET
Example: The Accumulator holds the value 56H (010101IOB) representing thepacked BCD digits of the
decimal number 56. Register 3 contains the value 67H (OllOOlllB) representing the packed
BCD digits of the decimal number 67. The carty flag is set. The instruction sequence.
ADDC A,R3
DA A
will first perform a standard twos-complement binary addition, resulting in the value OBEH
(10111110) in the Accumulator. The carry and auxiliary carry flags will be cleared.
The Decimal Adjust instruction will then' alter the Accumulator to the v!llue 24H
(00 100 1OOB), indicating the packed BCD digits of the decimal number 24, the low-order two
digits of the decimal sum of 56, 67, and the carry-in. The carry flag will be set by the Decimal
Adjust instruction, indicating that a decimal overflow occurred. The true sum 56, 67, and 1 is
124.
BCD variables can be incremented or decremented by adding 0lH'or 99H. If the Accumulator
initially holds 30H (representing the digits of 30 decimal), then the instruction sequence,
ADD A,#99H
DA A
will leave the carry set and 29H in the Accumulator, since 30 + 99 = 129. The low-order
byte of the sum can be interpreted to mean 30 - 1 = 29.
Bytes:
Cycles:
Encoding: I1 1 0 1 0 1 0 0
Operation: DA
-contents of Accumulator are BCD
IF [[(A3-O) > 9] V [(AC) = 1]]
THEN(A3-O) +- (A3-0) + 6
AND
IF [[(A7-4) > 9] V [(C) = III
THEN (A7-4) +- (A7-4) + 6
6-41
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
DEC byte
Function: Decrement
Description: The variable indicated is decremented by I. An original value of OOH will underflow toOFFH.
No flags are affected. Four operand addressing modes are allowed: accumulator, register,
direct, or register-indirect.
Note: When this instruction is used tiimodify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.
Example: Register 0 contains 7FH (OIIIIIIIB). :Internal RAM locations 7EH and 7FH contain OOH
and 4OH, respectively. The instruction sequence,
DEC @RO
DEC RO
DEC @RO
will leave register 0 set to 7EH and internal RAM locations 7EH and 7FH set to OFFH and
3FH..
DEC A
Bytes:
Cycles:
Encoding: I0 0 0 1 I 0 1 0 0
Operation: DEC
(A) +- (A) - I
DEC Rn
Bytes:
Cycles:
Encoding: I0 0 0 1 1 r r r
Operation: DEC
(Rn)-(Rn) -
6-42
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
DEC direct
Bytes: 2
Cycles:
Encoding: ,--I--,0_0_0_-,---0_1_0_1-, direct address
Operation: DEC
(direct) +- (direct) - 1
DEC @RI
Bytes:
Cycles:
Encoding: 1 0 ° 0 0 1 1
Operation: DEC
«Ri)) +- «Ri)) - 1
DIY AB
Function: Divide
Description: DIV AB divides the unsigned eight-bit integer in the Accumulator by the unsigned eight-bit
integer in register B. The Accumulator receives the integer part of the quotient; register B
receives the integer remainder. The carry and OV flags will be cleared.
Exception: if B had originally contained OOH, the values returned in the Accumulator and B-
register will be undefined and the overflow flag will be set. The carry flag is cleared in any
case.
Example: The Accumulator contains 251 (OFBH or 111110 lIB) and B contains 18 (12H or 000 I00 lOB).
The instruction,
DIV AB
will leave 13 in the Accumulator (ODH 'or OOOOIIOIB) and the value 17 (llH or ooolooolB)
in B, since 251 = (13 X 18) + 17. Carry and OV will both be cleared.
Bytes:
Cycles: 4
Encoding: 1 1 0 0 0 0 1 0 0
Operation: DIV
(A}JS-8 +- (A)!(B)
(B)7-0
6-43
infef MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
DJNZ <byte>,<rel-addr>
Function: Decrement and Jump if Not Zero
Description: DJNZ decrements the location indicated by 1, and branches to the address indicated by the
second operand if the resulting value is not zero. An original value of OOH will underflow to
OFFH. No flags are affected. The branch destination would be computed by adding the signed
relative-displacement value in the last instruction byte to the PC, after incrementing the PC to
the first byte of the following instruction.
The location decremented may be a register or directly addressed byte.
Note: When this instruction is used to modify an output port, the value used as the original
poit data will be read from the output data latch, not the input pins.
Example: Internal RAM locations 40H, SOH, and 60H contain the values OIH, 70H, and ISH, respec-
tively. The instruction sequence,
DJNZ 40H,LABEL_I
DJNZ SOH,LABEL_2
DJNZ 60H,LABEL_3
will cause ajump to the instruction at label LABEL_2 with the values OOH, 6FH, and ISH in
the three RAM locations. The first jump was not taken because the result was zero.
This instruction provides a simple way of executing a program loop a given number of times,
or for adding a moderate time delay (from 2 to SI2 machine cycles) with a single instruction.
The instruction sequence, .
.MOV R2,#8
TOGGLE: . CPL PI.7
DJNZ R2,TOGGLE
will toggle PI.7eight times, causing four output pulses to.appear at bit 7 of output Port 1.
Each pulse will last three machine cycles; two for DJNZ and one to alter the pin.
DJNZ Rn,rel
Bytes: 2
Cycles: 2
Encoding: LI _1_1_0_1-,-_1_r_r_r-, reI. address
Operation: DJNZ
(PC) ~ (PC) + 2
(Rn) ~ (Rn) - 1
IF (Rn) > 0 or (Rn) < 0
THEN
(PC) ~ (PC) + rei
6-44
MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
DJNZ direct,rel
Bytes: 3
Cycles: 2
Encoding: I1 1 0 1 0 1 0 1 direct address reI. address
Operation: DJNZ
(PC) - (PC) + 2
(direct) - (direct) - 1
IF (direct) > 0 or (direct) < 0
THEN
(PC) - (PC) + rei
INC <byte>
Function: Increment
Description: INC increments the indicated variable by 1. An original value of OFFH will overflow to DOH.
No flags are affected. Three addressing modes are allowed: register, direct, or register-indirect.
Note: When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.
Example: Register 0 contains 7EH (011 11 11 lOB). Internal RAM locations 7EH and 7FH contain OFFH
and 4OH, respectively. The instruction sequence,
INC @RO
INC RO
INC @RO
will leave register 0 set to 7FH and internal RAM locations 7EH and 7FH holding (respective-
ly) DOH and 4tH.
INC A
Bytes:
Cycles:
Encoding: I0 0 0 0 I0 1 0 0
Operation: INC
(A)-(A) +
6-45
MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
INC Rn
Bytes:
Cycles:
Encoding: 1 0 0 0 0 1 1 r r r
Operation: INC
(Rn) ~ (Rn) + 1
INC direct
Bytes: 2
Cycles:
.Encoding: 1 0 000 1 o1 0 1 direct address
Operation: INC
(direct) ~.(direct) +
INC @Ri
Bytes:
Cycles:
Encoding: 1 0000 1 011
Operation: INC
«Ri» ~ «Ri» +
INC DPTR
Function: Increment Data Pointer
Description: Increment the 16-bit data pointer by 1. A 16-bit increment (modulo 2 16) is performed; an
overflow of the low-order byte of the data pointer (DPL) from OFFH to OOH will increment
the high-order byte (DPH). No flags are affected.
This is the only 16-bit register which can be incremented.
Example: Registers DPH and DPL contain 12H and OFEH, respectively. The instruction sequence,
INC DPTR
INC DPTR
INC DPTR
will change DPH and DPL to 13H and 01H.
Bytes:
Cycles: 2
Encoding: I· 1 0 1 0 1 0 0 1 1 1
Operation: INC
(DPTR) ~ (DPTR) + 1
6-46
inter MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
JB blt,rel
Function: Jump if Bit set
Description: If the indicated bit is a one, jump to the address indicated; otherwise proceed with the next
instruction. The branch destination is computed by adding the signed relative-displacement in
the third instruction byte to the PC, after incrementing the PC to the first byte of the next
instruction. The bit tested is not modified. No flags are affected.
Example: The data present at input port I is I 10010 lOB. The Accumulator holds 56 (010101 lOB). The
instruction sequence,
JB P1.2,LABELl
JB ACC.2,LABEL2
will cause program execution to branch to the instruction at label LABEL2.
Bytes: 3
Cycles: 2
Encoding: I0 0 1 0 0 0 0 0 bit address reh address
Operation: JB
(PC) -- (PC) + 3
IF (bit) = 1
THEN
(PC) -- (PC) + rei
JBC bit,rel
Function: Jump if Bit is set and Clear bit
Description: If the indicated bit is one, branch to the address indicated; otherwise proceed with the next
instruction. The bit will not be cleared if it is already a zero. The branch destination is comput-
ed by adding the signed relative-displacement in the third instruction byte to the PC, after
incrementing the PC to the first byte of the next instruction. No flags are affected.
Note: When this instruction is used to test an output pin, the value used as the original data
will be read from the output data latch, not the input pin.
Example: The Accumulator holds 56H (010101 lOB). The instruction sequence,
JBC ACC.3,LABELl
JBC ACC.2,LABEL2
will cause program execution to continue at the instruction identified by the label LABEL2,
with the Accumulator modified to 52H (OlOlOOIOB).
6-47
inter MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
Bytes: 3
Cycles: 2
Encoding: I0 0 0 1 0 0 0 0 bit address reI. address
Operation: JBC
(PC) ~ (PC) + 3
IF (bit) = I
THEN
(bit) ~ 0
(PC) ~ (PC) + rei
JC rei
Function: Jump if Carry is set
Description: If the carry flag is set, branch to the address indicated; otherwise proceed with the next
instruction. The branch destination is computed by adding the signed relative-displacement in
the second instruction byte to the PC, after incrementing the PC twice. No flags are affected.
Example: The carry flag is cleared. The instruction sequence,
JC LABELl
CPL C
JC LABEL 2
will set the carry and cause program execution to continue at the instruction identified by the
label LABEL2.
Bytes: 2
Cycles: 2
Encoding: I0 1 0 0 0 0 0 O. reI. address
Operation: JC
(PC) ~ (PC) + 2
IF (C) = 1
THEN
(PC) ~ (PC) + rei
6-48
intJ MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET
JMP @A+DPTR
Function: Jump indirect
Description: Add the eight-bit unsigned contents of the Accumulator with the sixteen-bit data pointer, and
load the resulting sum to the program counter. This will be the address for subsequent instruc-
tion fetches. Sixteen-bit addition is performed (modulo 2 16): a carry-out from the low-order
eight bits propagates through the higher-order bits. Neither the Accumulator nor the Data
Pointer is altered. No flags are affected.
Example: °
An even number from to 6 is in the Accumulator. The following sequence of instructions will
branch to one of four AJMP instructions in a jump table starting at JMP _TBL:
MOV DPTR,#JMP_TBL
JMP @A+DPTR
AJMP LABELO
AJMP LABELl
AJMP LABEL2
AJMP LABEL3
If the Accumulator equals 04H when starting this sequence, execution will jump to label
LABEL2. Remember that AJMP is a two-byte instruction, so the jump instructions start at
every other address.
Bytes:
Cycles: 2
Encoding: ,-I _0__1_1-,-_0_0_1_1.......
Operation: JMP
(PC) ~ (A) + (DPTR)
6-49
intJ MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
JNB bit,rel
Function: Jump if Bit Not set
Description: If the indicated bit is.a zero, branch to the indicated address; otherwise proceed with the next
instruction. The branch destination is computed by adding the signed relative-displacement in
the third instruction byte to the PC, after incrementing the PC to the first byte of the next
instruction. The bit tested is not modified. No flags are affected.
Example: The data present at input port I is I 100 10 lOB. The Accumulator holds 56H (010101 lOB). The
instruction sequence,
JNB P1.3,LABELI
JNB ACC.3,LABEL2
will cause program execution to continue at the instruction at label LABEL2.
Bytes: 3
Cycles: 2
Encoding: I0 0 1 1
~------~------~
0000 bit address rei. address
Operation: JNB
(PC)~ (PC) + 3
IF (bit) = 0
THEN (PC) ~ (PC) + reI.
JNC rei
Function: Jump if Carry not set
Description: If the carry flag. is a zero, branch to the address indicated; otherwise proceed with the next
instruction. The branch destination is computed by adding the signed relative-displacement in
the second instruction byte to the PC, after incrementing the PC twice to point to the next
instruction. The carry flag is not modified.
Example: The carry flag is set. The instruction sequence,
JNC LABELl
CPL C
JNC LABEL2
will clear the carry and cause program execution to continue at the instruction identified by
the label LABEL2.
Bytes: 2
Cycles: 2
Encoding: LI_o__0_1.........._0_0_0_0-, rei. address
Operation: JNC
(PC)~ (PC) + 2
IF (C) = °
THEN (PC) ~ (PC) + rei
6-50.
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
JNZ rei
Function: Jump if Accumulator Not Zero
Description: If any bit of the Accumulator is a one, branch to the indicated address; otherwise proceed with
the next instruction. The branch destination is computed by adding the signed relative-dis-
placement in the second instruction byte to the PC, after incrementing the PC twice. The
Accumulator is not modified. No flags are affected.
Example: The Accumulator originally holds DOH. The instruction sequence,
JNZ LABELl
INC A
JNZ LABEL2
will set the Accumulator to OIH and continue at label LABEL2.
Bytes: 2
Cycles: 2
Encoding: ,-I _0__1_1-,-_0_0_0_0-, reI. address
Operation: JNZ
(PC) - (PC) + 2
IF (A) "* °
THEN (PC) - (PC) + rel
JZ rei
Function: Jump if Accumulator Zero
Description: If all bits of the Accumulator are zero, branch to the address indicated; otherwise proceed with
the next instruction. The branch destination is computed by adding the signed relative-dis-
placement in the second instruction byte to the PC, after incrementing the PC twice. The
Accumulator is not modified. No flags are affected.
Example: The Accumulator originally contains OIH. The instruction sequence,
JZ LABELl
DEC A
JZ LABEL2
will change the Accumulator to DOH and cause program execution to continue at the instruc-
tion identified by the label LABEL2.
Bytes: 2
Cycles: 2
Encoding: 1 ° ° °°°°
1 1 reI. address
Operation: JZ
(PC) - (PC) + 2
IF (A) = °
THEN (PC) - (PC) + rei
6-51
intJ MCS@-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
LCALL addr16
Function: Long call
Description: LCALL calls a subroutine located at the indicated address. The instruction adds three to the
program counter to generate the address of the next instruction and then pushes the 16-bit
result onto the stack (low byte first), incrementing the Stack Pointer by two. The high-order
and low-order bytes of the PC are then loaded, respectively, with the second and third bytes of
the LCALL instruction. Program execution continues with the instruction at this address. The
subroutine may therefore begin anywhere in the full 64K-byte' program memory address space.
No flags are affected.
Example: Initially the Stack Pointer equals 07H. The label "SUBRTN" is assigned to program memory
location 1234H. After executing the instruction,
LCALL SUBRTN
at location OI23H, the Stack Pointer will contain 09H, internal RAM locations OSH and 09H
will contain 26H and OIH, and the PC will contain I 234H.
Bytes: 3
Cycles: 2
Encoding: ,-1_0_0_0_-,-_0_0_1_0-, addr15-addrB addr7 -addrO
Operation: LCALL
(PC) ~ (PC) + 3
(SP) <E:- (SP) + I
«SP» ~ (PC7-0)
(SP) ~ (SP) + I
«SP» ~ (PCI5_g)
(PC) ~ addft5-O
LJMP addr16
Function: Long Jump ,
Description: UMP causes an unconditional branch to the indicated address, by loading the high-order and
low-order bytes of the PC (respectively) with the second and third instruction bytes. The
destination may therefore be anywhere in the full 64K program memory address space. No
flags are affected.
Example: The label "JMPADR"is assigned to the instruction at program memory location 1234H. The
instruction,
UMP JMPADR
at location OI23H will load the program counter with I234H.
Bytes: 3
Cycles: 2
Encoding: 1 0 0 0 ° 1 0 0 1 0 addr15-addrB addr7 -addrO
Operation: UMP
(PC) ~ addft5_0
6-52
inter MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
MOV <dest-byte > , < src-byte >
Function: Move byte variable
Description: The byte variable indicated by the second operand is copied into the location specified by the
first operand. The source byte is not affected. No other register or flag is affected.
This is by far the most flexible operation. Fifteen combinations of source and destination
addressing modes are allowed.
Example: Internal RAM location 30H holds 4OH. The value of RAM location 40H is lOH. The data
present at input port 1 is IlOOIOlOB (OCAH).
MOV RO,#30H ;RO <= 30H
MOV A,@RO ;A <= 40H
MOV RI,A ;RI <= 40H
MOV B,@Rl ;B <= lOH
MOV @RI,Pl ;RAM (40H) < = OCAH
MOV P2,PI ;P2 #OCAH
leaves the value 30H in register 0, 40H in both the Accumulator and register I, lOH in register
B, and OCAH (llOOIOIOB) both in RAM location 40H and output on port 2.
MOV A,Rn
Bytes:
Cycles:
Encoding: I1 1 1 0 1 r r r
Operation: MOV
(A) +- (Rn)
'MOV A,direct
Bytes: 2
Cycles:
Encoding: I 1 110 o1 0 1 direct address
Operation: MOV
(A) +- (direct)
MOV A,ACC is not a valid instruction.
6-53
MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
MOV A,@Ri
Bytes:
Cycles:
Encoding: I1 1 1 0 o1
Operation: MOY
(A) +- «Ri»
MOV A,#data
Bytes: 2
Cycles:
Encoding:
1 01
1 1 o1 00 immediate data
Operation: MOY
(A) +- #data
MOV Rn,A
Bytes:
Cycles:
Encoding: I1 1 1 1 1 r r r
Operation: MOY
(Rn)+-(A)
MOV Rn,direct
Bytes: 2
Cycles: 2
Encoding: I 1 010 1 r r r I -I direct addr. I
Operation: MOY
(Rn) +- (direct)
MOV Rn,#data
Bytes: 2
Cycles:
Encoding: 101 1 1 r r r immediate data
Operation: MOY
(Rn) +- #data
6-54
intJ MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
MOV direct,A
Bytes: 2
Cycles:
Encoding: I1 1 1 o1 0 1 I direct address
Operation: May
(direct) +- (A)
MOV direct,Rn
Bytes: 2
Cycles: 2
Encoding: I 1 000 1 r r r direct address
Operation: MaV
(direct) +- (Rn)
MOV direct,direct
Bytes: 3
Cycles: 2
Encoding: I 1 o 00 o1 0 1 dir. addr. (src) dir. addr. (dest)
Operation: May
(direct) +- (direct)
MOV direct,@Ri
Bytes: 2
Cycles: 2
Encoding:
I 1 000 011 direct addr.
Operation: May
(direct) +- «Ri»
MOV direct, # data
Bytes: 3
Cycles: 2
Encoding:
1 01 o1 0 1 direct address immediate data
Operation: May
(direct) +- #data
6-55
inter MCS@·S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET
MOV @RI,A
Bytes:
Cycles:
Encoding: I1 1 1 011
Operation: MOV
«Ri» +- (A)
MOV @Ri,dlrect
Bytes: 2
Cycles: 2
Encoding: I 1 010 011 direct addr.
Operation: MOV
«Ri» +- (direct)
MOV @RI,#data
Bytes: 2
Cycles:
Encoding: 1 01 011 immediate data
Operation: MOV
«RI» +- #data
MOV < dest·blt > , < src-bit >
Function: Move bit data
Description: The Boolean variable indicated by the second operand is copied into the location specified by
the first operand. One of the operands must be the carry flag; the other may be any directly
addressable bit. No other register or flag is affected.
Example: The carry flag is originally set. The data present at input Port 3 is 11 000 10 I B. The data
previously written to output Port I is 35H (001 10 10 IB).
MOV PI.3,C
MOV C,P3.3
MOV PI.2,C
will leave the carry cleared and change Port 1 to 39H (OOIIIOOlB).
6-56
inter MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET
MOV C,bit
Bytes: 2
Cycles:
Encoding: I1 a1a aa1a bit address
Operation: MOV
(C) - (bit)
MOV bit,C
Bytes: 2
Cycles: 2
Encoding: I1 aa1 aa1a bit address
Operation: MOV
(bit) - (C)
MOV DPTR,#data16
Function: Load Data Pointer with a l6-bit constant
Description: The Data Pointer is loaded with the l6-bit constant indicated. The l6-bit constant is loaded
into the second and third bytes of the instruction. The second byte (DPH) is the high-order
byte, while the third byte (DPL) holds the low-order byte. No flags are affected.
This is the only instruction' which moves 16 bits of data at once.
Example: The instruction,
MOV DPTR,#1234H
wi1110ad the value l234H into the Data Pointer: DPH will hold 12H and DPL will hold 34H.
Bytes: 3
Cycles: 2
Encoding: I1 aa1 aaaa immed. data15-8 immed. data7-0
Operation: MOV
(DPTR) - #data15_0
DPH 0 DPL - #data15_8 0 #data7_o
6-57
intJ MCS@-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
MOVC A,@A+ <base-reg>
Function: Move Code byte
Description: The MOVC instructions load the Accumulator with a code byte, or constant from program
memory. The address of the byte fetched is the sum of the original unsigned eight-bit Accumu-
lator contents and the contents of a sixteen-bit base register, which may be either the· Data
Pointer or the PC. In the latter case, the PC is incremented to the address of the following
instruction before being added with the Accumulator; otherwise the base register is not al-
tered. Sixteen-bit addition is performed so a carry-out from the low-order eight bits may
propagate through higher-order bits. No flags are affected.
Example:. A value between 0 and 3 is in the Accumulator. The following instructions will translate the
value in the Accumulator to one of four values defined by the DB (define byte) directive.
REL_PC: INC A
MOVe A,@A+PC
RET
DB 66H
DB 77H
DB 88H
DB 99H
If the subroutine is called with the Accumulator equal to OIH, it will return with 77H in the
Accumulator. The INC A before the MOVC instruction is needed to "get around" the RET
instruction above the table. If several bytes of code separated the MOVC from the table, the
corresponding number would be added to the Accumulator instead.
MOVC A,@A+DPTR
Bytes: 1
Cycles: 2
Encoding: LI_1_0_0_1--,-_O_O_'_1....J
Operation: MOVe
(A) - «A) + (DPTR»
MOVC A,@A + PC
Bytes:
Cycles: 2
Encoding: I 1 °° ° 0 ° 1 1
Operation: MOVC
(PC) - (PC) + 1
(A) - «A) + (PC»
6-58
inter MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
MOVX < dest-byte > , < src-byte >
Function: Move External
Description: The MOVX instructions transfer data between the Accumulator and a byte of external data
memory, hence the "X" appended to MOV. There are two types of instructions, differing in
whether they provide an eight-bit or sixteen-bit indirect address'to the external data RAM.
In the first type, the contents of RO or R1 in the current register bank provide an eight-bit
address multiplexed with data on PO. Eight bits are sufficient for external I/O expansion
decoding or for a relatively small RAM array. For somewhat larger arrays, any output port
pins can be used to output higher-order address bits. These pins would be controlled by an
output instruction preceding the MOVX.
In the second type of MOVX instruction, the Data Pointer generates a sixteen-bit address. P2
outputs the high-order eight address bits (the contents of DPH) while PO multiplexes the low-
order eight bits (DPL) with data. The P2 Special Function Register retains its previous con-
tents while the P2 output buffers are emitting the contents of DPH. This form is faster and
more efficient when accessing very large data arrays (up to 64K bytes), since no additional
instructions are needed to set up the output ports.
It is possible in some situations to mix the two MOVX types. A large RAM array with its
high-order address lines driven by P2 can be addressed via the Data Pointer, or with code to
output high-order address bits to P2 followed by a MOVX instruction using RO or Rl.
Example: An external 256 byte RAM using multiplexed address/data lines (e.g., an Intel 8155 RAM/
I/O/Timer) is connected to the 8051 Port O. Port 3 provides control lines for the external
RAM. Ports 1 and 2 are used for normal I/O. Registers 0 and 1 contain 12H and 34H.
Location 34H of the external RAM holds the value 56H. The instruction sequence,
MOVX A,@R1
MOVX @RO,A
copies the value 56H into both the Accumulator and external RAM location 12H.
6-59
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
MOVX A,@RI
Bytes:
Cycles: 2
Encoding: 111101001il
Operatlon:MOVX
(A) - «Ri»
MOVX A,@DPTR
Bytes:
Cycles: 2
Encoding: 11110100001
Operation: MOVX
(A) - «DPTR»
MOVX @RI,A
Bytes:
Cycles: 2
Encoding: 1'1 1 1 1 1 0 0 1 i I
. ,
Operation: MOVX
«Ri» - (A)
MOVX @DPTR,A
Bytes:
Cycles: 2
Encoding: 11111100001
Operation: MOVX
(DPTR.) -(A)
6-60
intJ MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET
MUL AB
Function: Multiply
Description: MUL AB multiplies the unsigned eight-bit integers in the Accumulator and register B. The
low-order byte of the sixteen-bit product is left in the Accumulator, and the high-order byte in
B. If the product is greater than 255 (OFFH) the overflow flag is set; otherwise it is cleared.
The carry flag is always cleared.
Example: Originally the Accumulator holds the value 80 (50H). Register B holds the value 160 (OAOH).
The instruction, .
MUL AB
will give the product 12,800 (3200H), so B is changed to 32H (001 100 lOB) and the Accumula-
tor is cleared. The overflow flag is set, carry is cleared.
Bytes:
Cycles: 4
Encoding: 11010 0100
Operation: MUL
(Ah-O - (A) X (B)
(Bhs.g
NOP
Function: No Operation
Description: Execution continues at the following instruction. Other than the PC, no registers or flags are
affected.
Example: It is desired to produce a low-going output pulse on bit 7 of Port 2 lasting exactly 5 cycles. A
simple SETB/CLR sequence would generate a one-cycle pulse, so four additional cycles must
be inserted. This may be done (assuming no interrupts are enabled) with the instruction
sequence,
CLR P2.7 '
NOP
NOP
NOP
NOP
SETB P2.7
Bytes:
Cycles:
Encoding: 10 0 0 0 1 0 0 0 0
Operation: NOP
(PC)-(PC) +
6-61
inter MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET
ORL <dest-byte> <src-byte>
Function: Logical-OR for byte variables
Description: ORL performs the bitwise logical-OR operation between the indicated variables, storing the
results in the destination byte; No flags are affected. .
The two operands allow six addressing mode combinations. When the destination is the Aceu-
. mulator, the source can use register, direct, register-indirect, or immediate addressing; when
the' destination is a direct address, the source can be ihe AcCumulator or immediate data.
Note: When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.
Example: If the AcCumulator holds OC3H (11 0000 11 B) and RO holds 55H (OlOlOlOlB) then the in-
struction,
ORL A,RO
will leave the Accumulator holding the value OD7H (1 10101 1IB).
When the destination is a directly addressed byte, the instruction can set combinations of bits
in any RAM location or hardware register. The pattern of bits to be set is determined by a
mask byte, which may be either a constant data value in the instruction or a variable comp!1ted
in the Accumulator at run-time. The instruction,
ORL Pl,#OOl1OOIOB
will set bits 5, 4, and 1 of output Port 1.
ORL A,Rn
Bytes:
,Cycles: ,1
Encoding: I0 1 0 0 1 r r r
Operation: ORL
(A) +- (A) V (Rn)
6-62
intJ MCS®"51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
ORL A,direct
Bytes: 2
Cycles:
Encoding:
1 01 00 o1 0 1 direct address
Operation: ORL
(A) +- (A) V (direct)
ORL A,@Ri
Bytes:
Cycles:
Encoding: I0 1 00 011
Operation: ORL
(A) +- (A) V «Ri))
ORL A, # data
Bytes: 2
Cycles:
Encoding:
1 01 o0 o1 0 0 immediate data
Operation: ORL
(A) +- (A) V # data
ORL direct,A
Bytes: 2
Cycles:
Encoding:
1 01 o0 001 0 direct address
Operation: ORL
(direct) +- (direct) V (A)
ORL direct, # data
Bytes: 3
Cycles: 2
Encoding:
1 01 00 001 1 direct addr. immediate data
Operation: ORL
(direct) +- (direct) V #data
6-63
inter MCS@·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
ORL C,<src-bit>
Function: Logical-OR for bit variables
Description: Set the carry flag if the Boolean value is a logical 1; leave the carry in its current state
otherwise. A slash ("I") preceding the operand in the assembly language indicates that the
logical complement of the addressed bit is used as the source value, but the source bit itself is
not affected. No other flags are affected.
Example: Set the carry flag if and qnly if P1.0 = 1, ACC. 7 = 1, or OV = 0:
MOV C,P1.0 ;LOAD CARRY WITH INPUT PIN PIO
ORL C,ACC.7 ;OR CARRY WITH THE ACC. BIT 7
ORL C,/OV ;OR CARRY WITH THE INVERSE OF OV.
ORL C,bit
Bytes: 2
Cycles: 2
Encoding:
1 01 1 1 001 0 bit address
Operation: ORL
(C) +- (C) V (bit)
ORL C,/blt
Bytes: 2
Cycles: 2
Encoding: I1 o 1 0 o0 0 0 bit address
Operation: ORL
(C) +- (C) V (bit)
6-64
inter MCS®·51 PROGRAMMER'S GUIDE AND INStRUCTION SET
POP direct
Function: Pop from stack.
Description: The contents of the internal RAM location addressed by the Stack Pointer is read, and the
Stack Pointer is decremented by one. The value read is then transferred to the directly ad-
dressed byte indicated. No flags are affected.
Example: The Stack Pointer originally contains the value 32H, .and internal RAM locations 30H
through 32H contain the values 20H, 23H, and OIH, respectively. The instruction sequence,
POP DPH
POP DPL
will leave the Stack Pointer equal to the value 30H and the Data Pointer set to 0123H. At this
point the instruction,
POP SP
will leave the Stack Pointer set to 20H. Note that in this special case the Stack Pointer was
decremented to 2FH before being loaded with the value popped (20H).
Bytes: 2
Cycles: 2
Encoding: 11--1_1_0_1---,-_0_0_0_0---, direct address
Operation: POP
(direct) ~ «SP»
(SP) ~ (SP) - I
PUSH direct
Function: Push onto stack
Description: The Stack Pointer is incremented by one. The contents of the indicated variable is then copied
into the internal RAM location addressed by the Stack Pointer. Otherwise no flags are affect-
ed.
Example: On entering an interrupt routine the Stack Pointer contains 09H. The Data Pointer holds the
value 0123H. The instruction sequence,
PUSH DPL
PUSH DPH
will leave the Stack Pointer set to OBH and store 23H and OIH in internal RAM locations
OAH and OBH, respectively.
Bytes: 2
Cycles: 2
Encoding: 1 1 1 0 0 0 0 0 ° direct address
Operation: PUSH
(SP) ~ (SP) + I
«SP» ~ (direct)
6-65
intJ MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
RET
Function: Return from subroutine
Description: RET pops the high- and low-order bytes of the .PC successively from the stack, decrementing
the Stack Pointer by. two. Program execution continues at the resulting address, generally the
instruction immediately following an ACALL or LCALL. No flags are affected.
Example: .The Stack Pointer originally contains the value OBH. Internal RAM locations OAR and OBH
contain the values 23H and OIH, respectively. The instruction,
RET
will leave the Stack Pointer equal to the value 09H. Program execution will continue at
location 0123H.
Bytes:
Cycles: 2
Encoding: 100100010
Operation: RET
(PC15-S) +- «SP»
(SP) +- (SP) - I
(PC7-0) +- «SP»
(SP) +- (SP) - I
RETI
Function: Return from interrupt
Description: RETI pops the high- and low-order bytes of the PC successively from the stack, and restores
the interrupt logic to accept additional interrupts at the same priority level as the one just
processed. The Stack Pointer is left decremented by two. No other registers are affected; the
PSW is not automatically restored to its pre-interrupt status. Program execution continues at
the resulting address, which is generally the instruction immediately after the point at which
the interrupt request was detected. If a lower- or same-level interrupt had been pending when
the RETI instruction is executed, that one instruction will be executed before the pending
interrupt is processed.
Example: The Stack Pointer originally contains the value OBH. An interrupt was detected during the
instruction ending at location 0122H. Internal R5\,M locations OAH andOBH contain the
values 23H and OIH, respectively. The instruction,
RET!
will leave the Stack Pointer equal to 09H and return program execution to location 0123H.
Bytes:
Cycles: 2
Encoding: 100 1 001 0
Operation: RET!
(PC15-S) +- «SP»
(SP) +- (SP) - I
(PC7-0) +- «SP»
(SP) +- (SP) - I
6-66
MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET
RL A
Function: Rotate Accumulator Left
Description: The eight bits in the Accumulator are rotated one bit to the left. Bit 7 is rotated into the bit 0
position. No flags are affected.
Example: The Accumulator holds the value OC5H (I 1000 10 lB). The instruction,
RL A
leaves the Accumulator holding the value 8BH (IOOOlOllB) with the carry unaffected.
Bytes:
Cycles:
Encoding: 1 °° ° °°
1 1 1
Operation: RL
(An + I) +- (An) n = 0 - 6
(AO) +- (A7)
RLC A
Function: Rotate Accumulator Left through the Carry flag
. Description:
°
The eight bits in the Accumulator and the carry flag are together rotated one bit to the left. Bit
7 moves into the carry flag; the original state of the carry flag moves into the bit position. No
other flags are affected.
Example: The Accumulator holds the value OC5H (I 1000 101 B), and the carry is zero. The instruction,
RLC A
leaves the Accumulator holding the value 8BH (IOOOlOIOB) with the carry set.
Bytes:
Cycles:
Encoding: 1-1_0_0_1_-,-_0_0_1_1-1
Operation: RLC
(An + I) +- (An) n = 0 - 6
(AO) +- (C)
(C) +- (A7)
6-67
inter MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
RR A
Function: Rotate Accumulator Right
Description: The eight bits in the Accumulator are rotated one bit to the right. Bit 0 is rotated into the bit 7
position. No flags are affected.
Example: The Accumulator holds the value OC5H (1IoooI0IB). The instruction.
RR A
leaves the Accumulator holding the value OE2H (I 1I000 lOB) with the carry unaffected.
Bytes:
Cycles:
Enc9ding: 1 0 0 0 ° 1 0 0 1 1
Operation: RR
(An) +- (An + 1) n = 0 - 6
(A7) +- (AO)
RRC A
Function: Rotate Accumulator Right through Carry flag
Description: The eight bits in the Accumulator and the carry flag are together rotated one bit to the right.
Bit 0 moves into the carry flag; the original value of the carry. flag moves into the bit 7
position. No other flags are affected.
Example: The Accumulator holds the value OC5H (llooo101B). the carry is zero. The instruction.
RRC A
leaves the Accumulator holding the value 62 (Ol1ooolOB) with the carry set.
Bytes:
Cycles:
Encoding: 1,--0_0_0_..1.-0_0_1_1-'
Operation: RRC
(An) +- (An + 1) n = 0 - 6
(A7) +- (C)
(C) +- (AO)
6-68
MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
SETB <bit>
Function: Set Bit
Description: SETB sets the indicated bit to one. SETB can operate on the carry flag or any directly
addressable bit. No other flags are affected.
Example: The carry flag is cleared. Output Port 1 has been written with the value 34H (001101ooB). The
instructions,
SETB C
SETB P1.0
will leave the carry flag set to 1 and <;hange the data output on Port 1 to 35H (00110101B).
SETB C
Bytes:
Cycles:
Encoding: I1 1 0 1 001 1
Operation: SETB
(q-l
SETB bit
Bytes: 2
Cycles:
Encoding: I1 1 0 1 001 0 bit address
Operation: SETB
(bit) - 1
6·69
inter MCs®·S1' PROGRAMMER'S GUIDE AND INSTRUCTION SET
SJMP rei
Function: Short Jump
Description: Program control branches unconditionally to the address indicated. The branch destination is
computed by adding the signed displacement in the second instruction byte to the PC, after
incrementing the PC twice. Therefore, the range of destinations allowed is from 1,78 bytes
preceding this instruction to 127 bytes following it. '
Example: The label "RELADR" is assigned to an instruction at program memory location 0123H. The
instruction,
SJMP RELADR
will assemble into location OlooH. After the instruction is executed, the PC will contain the
value 0123H. .
(Note: Under the above conditions the instruction following SJMP will be at 102H. Thereforb.
the displacement byte of the instruction will be the relative offset (01 23R-OIQ2H)= 21H. Put
another way, an SJMP with a displacement ofOFER would be a one-instruction infinite loop.)
Bytes: 2
Cycles: 2
Encoding: I1 0 0 0 0 0 0 0 reI. address
Operation: SJMP
(PC) - (PC) + 2
(PC) - (PC) + rei
'6-70 .
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
SUBB A, < src-byte >
Function: Subtract with borrow
Description: SCBB subtracts the indicated variable and the carry flag together from the Accumulator,
leaving the result in the Accumulator. SUBB sets the carry (borrow) flag if a borrow is needed
for bit 7, and clears C otherwise. (If C was set before executing a SUBBinstruction, this
indicates that a borrow was needed for the previous step in a multiple precision subtraction, so
the carry is subtracted from the Accumulator along with the source operand.) AC is set if a
borrow is needed for bit 3, and cleared otherwise. OV is set if a borrow is needed into bit 6, but
not into bit 7, or into bit 7, but not bit 6.
When subtracting signed integers OV indicates a negative number produced when a negative
value is subtracted from a positive value, or a positive result when a positive number is
subtracted from a negative number.
The source operand allows four addressing modes: register, direct, register-indirect, or imme-
diate. .
Example: The Accumulator holds OC9H (llOOlOOlB), register 2 holds 54H.(OlOlOlOOB), and the carry
flag is set. The instruction,
SUBB A,R2
will leave the value 74H (Oll10100B) in the accumulator, with the carry flag and AC cleared
but OV set.
Notice that OC9H minus 54H is 75H. The difference between this and the above result is due
to the carry (borrow) flag being set before the operation. If the state of the carry is not known
before starting a single or multiple-precision subtraction, it should be explicitly cleared by a
CLR C instruction. . .
SUBB A,Rn
Bytes:
Cycles:
Encoding: ....
1_1_0_0_1--L._1_f_f_f..J
Operation: SUBB
(A) -- (A) - (C) - (Rn)
6-71
inter MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET
SUBB A,dlrect
Bytes: 2
Cycles:
Encoding: 11 0 0 1 0 1 0 1 direct address
Operation: SUBB
(A) ~ (A) - (C) ,.... (direct)
SUBB A,@Ri
Bytes:
Cycles:
Encoding: 11001011
Operation: SUBB
(A) ~ (A) - (C) - «Ri»
SUBB A,#data
Bytes: 2
Cycles:
Encoding: 11 00 1 0 1 0.0 immediate data
Operation: SUBB
(A) ~ (A) - (C) - #data
SWAP A
Function: Swap nibbles within the Accumulator
Description: SWAP A interchanges the low- and high-order nibbles (four-bit fields) of the Accumulator
(bits 3-0 and bits 7-4). The operation can also be thought of as a four-bit rotate instruction. No
flags are affected.
Example: . The Accumulator holds the value OCSH (llOOOlOlB). The instruction,
SWAP A
leaves the Accumulator holding the value SCH (OlOlll00B).
Bytes:
Cycles:
Encoding: 11 1 0 0 0 1 0 0
Operation: SWAP
(A3-0) Z (A7-4)
inter MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
XCH A,<byte>
Function: Exchange Accumulator with byte variable
Description: XCH loads the Accumulator with the contents of the indicated variable, at the same time
writillg the original Accumulator contents to the indicated variable. The source/destination
operand can use register, direct, or register-indirect addressing.
Example: RO contains the address 20H. The Accumulator holds the value 3FH (OOllllllB). Internal
RAM location 20H holds the value 75H (011 JO J01 B). The instruction,
XCH A,@RO
will leave RAM location 20H holding the values 3FH (OOl11111B) and 75H (01110JOlB) in
the accumulator.
XCH A,Rn
Bytes:
Cycles:
Encoding: I1 1 0 0 1 r r r
Operation: XCH
(A) ~ (Rn)
XCH A,dlrect
Bytes: 2
Cycles:
Encoding: I 1 100 o1 01 direct address
Operation: XCH
(A) ~ (direct)
XCH A,@Ri
Bytes:
Cycles:
Encoding: 11 100 011
Operation: XCH
(A) ~ «Ri»
6-73
inter MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET
XCHD A,@Ri
Function: Exchange Digit
Description: XCHD exchanges the low-order nibble of the Accumulator (bits 3-0), generally representing a
hexadecimal or BCD digit, with that of the internal RAM location indirectly addressed by the
specified register. The high-order nibbles (bits 7-4) of each register are not affected. No flags
are affected.
Example: RO contains the address 20H. The Accumulator holds the value 36H (001 101 lOB). Internal
RAM location 20H holds the value 75H (OlllOlOlB). The instruction,
XCHD A,@RO
will leave RAM location 20H holding the value 76H (011 101 lOB) and 35H (OOIIOlOlB) in the
Accumulator.
. Bytes:
Cycles:
Encoding: o1 1
Operation: XCHD
(A3-0) -;. «Ri3_0))
XRL < dest-byte > , <src-byte >
Function: Logical Exclusive-OR for byte variables
Description: . XRL performs the bitwise logical Exclusive-OR operation between the indicated variables,
storing the results in the destination. No flags are affected.
The two operands allow six addressing mode combinations. When the destination is the Accu-
mulator, the source can use register, -direct, register-indirect, or immediate addressing; when
the destination is a direct address, the source can be the Accumulator or immediate data.
(Note: When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.)
Example: If the Accumulator holds OC3H (llOOOOllB) and register 0 holds OAAH (1010 10 lOB) then
the instruction,
XRL A,RO
will leave the Accumulator holding the value 69H (OllOIOOlB).
When the destination is a directly addressed byte, this instruction can complement combina-
tions of bits in any RAM location or hardware register. The pattern of bits to be complement-
ed is then determined by a mask byte, either a constant contained in the instruction or a
variable computed in the Accumulator at run-time. The instruction,
XRL Pl,#OOllOOOlB
will complement bits 5, 4, and 0 of output Port 1.
6-74
inter MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
XRL A,Rn
Bytes:
Cycles:
Encoding:
1 01 1 0 1 r r r
Operation: XRL
(A) ~ (A) ¥ (Rn)
XRL A,direct
Bytes: 2
Cycles:
Encoding:
1 01 1 0 o1 0 1 direct address
Operation: XRL
(A) ~ (A) ¥ (direct)
XRL A,@Ri
Bytes:
Cycles:
Encoding: 1 01 1 0 o1 1 i
Operation: XRL
(A) ~ (A) ¥ «Ri»
XRL A,#data
Bytes: 2
Cycles:
Encoding:
1 01 1 0 o10 0 immediate data
Operation: XRL
(A) ~ (A) ¥ #data
XRL direct,A
Bytes: 2
Cycles:
Encoding: 01 1 0 001 0 direct address
1
Operation: XRL
(direct) ~ (direct) ¥ (A)
6-75
inter MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET
XRL dlrect,#data
Bytes: 3
Cycles: 2
Encoding: I0 1 1 0 0 0 1 1 direct address immediate data
Operation: XRL
(direct) +- (direct) ¥- #data
6-76
MCS®.-51 Hardware 7
Description and Data Sheets
September 1989
8051,8052 and 80C51
Hardware Description
Order Number: 270252-004
7-1
8051,8052 AND 80C51 CONTENTS PAGE
HARDWARE DESCRIPTION INTRODUCTION ......................... 7-4
Special Function Registers ............... 7-4
PORT STRUCTURES AND
OPERATION ........................... 7-7
1/0 Configurations ........................ 7-8
Writing to a Port .......................... 7-8
Port Loading and Interfacing .............. 7-9
Read-Modify-Write Feature .............. 7-10.
ACCESSING EXTERNAL MEMORy .... 7-10
TIMER/COUNTERS .............. ,...... 7-10
Timer 0 and Timer 1 ..................... 7-11
Timer 2 ................................. 7-13
SERIAL INTERFACE ................... 7-14
Multiprocessor Communications ......... 7-15
Serial Port Control Register .............. 7-15
Baud Rates ............................. 7-16
More About Mode 0 ..................... 7-18
More About Mode 1 ..................... 7-18
More About Modes 2 and 3 .............. 7-21
INTERRUPTS . ..... , .................... 7-24
Priority Level Structure .................. 7-25
How Interrupts Are Handled ............. 7-25
External Interrupts ....................... 7-26
Response Time ......................... 7-26
SINGLE-STEP OPERATION ............ 7-27
RESET . ................................. 7-27
POWER-ON RESET .................... 7-28
POWER-SAVING MODES OF
OPERATION ......................... 7-28
CHMOS Power Reduction Modes ........ 7-28
7-2
EPROM VERSiONS ..................... 7-30 THE ON-CHIP OSCiLLATORS ......... , 7-31
Exposure to Light ......... , .............. 7-30 HMOS Versions ......................... 7-31
Program Memory Locks ................. 7-30
CHMOS VERSiONS, .................... 7-33
ROM Protection ......................... 7-31
ONCE Mode ............................ 7-31 INTERNAL TIMING ..................... 7-34
7-3
805.1, 8052 AND 80C51
HARDWARE DESCRIPTION
INTRODUCTION • The EPROM versions of the SOSIAH, SOS2AH,
andSOCSIBH . .
This chapter presents a comprehensive description of
the on-chip hardware features of the MCS®-SI micro- The devices under consideration are listed in Table 1.
controllers. Included in this description are As it becomes unwieldy to be constantly referring to
each of these devices by their individual naines, we will
• The port drivers and how they function both as
ports and, for Ports 0 and 2, in bus operations adopt a convention of referring to them generically as
SOSls and SOS2s, unless a specific member of the group
• The Timer/Counters is being referred to, in which case it will be specifically
• The Serial Interface named. The "SOSls" include the SOSI, SOSIAH, and
SOC51BH, and their ROMless and EPROM versions.
• The Interrupt System
The "SOS2s" are the S052AH, S032AH, and S752BH.
• Reset
• The Reduced Power Modes in the CHMOS devices Figure 1 shows a functional block diagram of the SOSls
and SOS2s.
Table 1. The MCS-S1 Family of Microcontrollers
Device ROMle.ss EPROM ROM RAM 16-bit Ckt
Name Version Version Bytes Bytes Timers Type
8051 8031 (8751) 4K 128 2 HMOS
8051AH 8031AH 8751H 4K 128 2 HMOS
8052AH 8032AH 8752BH 8K 256 3 HMOS
80C51BH 80C31BH 87C51 4K 128 2 CHMOS
Special Function Registers
A map of the on-chip memory area called SFR (Special Function Register) space is shown in Figure 2. SFRs marked
by parentheses are resident in the S052s but not in the SOSls.
7-4
inter HARDWARE DESCRIPTION OFTHE 8051, 8052 AND 80C51
PO.O~PO.l P2.0-P2.7
r- --- - ---~tlI.:!::!, r'-J-..L..L..L..L......,------------,I
~
1
~ 1
= 1
I
I 1
1
1
1
1
I 1
1
I
1
1
1
I
1
1
1
1
1,.--""'---.,
I
1'-"== 1
1
1
1
1
1
1
1
1
1,.--_,--, 1
PSEN
ALE
1
EA I
RST
I
1
I
I
1
1
______ ..J'
-Resident in 8052/8032 only.
Pl.0·Pl.7 P3.0·P3.1
270252-1
Figure 1. MCS-51 Architectural Block Diagram
7-5
HAROWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
8 Bytes
FB FF
FO 8 F7
EB EF
EO ACC E7
DB OF
DO PSW 07
CB (T2CON) (RCAP2L) (RCAP2H) (TL2) (TH2) CF
CO C7
88 If> BF
80 P3 B7
AB IE AF
AO P2 A7
98 SCON SBUF 9F
90 P1 97
B8 TCON TMOO TLO TL1 THO TH1 8F
BO PO SP DPL OPH PCON B7
Figure 2. SFR Map. ( ... ) Indicates Resident in 8052s, not in 80518
Note that not all of the addresses are occupied. Unoc- to hold a 16-bit address. It may be manipulated as a
cupied addresses are not implemented on the chip. 16-bit register or as two independent S-bit registers.
Read accesses to these addresses will in general return
random data, and write accesses will have no effect. PORTS 0 TO 3
User software should not write Is to these unimple- PO, PI, P2 and P3 are the SFR latches of Ports 0, I, 2
mented locations, since they may be used in future and 3, respectively.
MCS-51 products to invoke new features. In that case
the reset or inactive values of the new bits will always SERIAL DATA BUFFER
be 0, and their active values will be 1.
The Serial Data Buffer is actually two separate regis-
The functions of the SFRs are outlined below. ters, a transmit buffer and a receive buffer register.
When data is moved to SBUF, it goes to the transmit
ACCUMULATOR buffer where it is held for serial transmission. (Moving
ACC is the Accuniulator register; The mnemonics for a byte to SBUF is what initiates the transmission.)
Accumulator-Specific instructions, however, refer to When data is moved from SBUF, it comes from the
the Accumulator silnply as A. receive butTer.
B REGISTER TIMER REGISTERS
The B register is used during mUltiply and divide oper- Register pairs (THO, TLO), (THI, TLl), and (TH2,
ations. For other instructions it can be treated as anoth- TL2) are the 16-bit Counting registers for Timer/Coun-
er scratch pad register. ters 0, I, and 2, respectively.
PROGRAM STATUS WORD CAPTURE REGISTERS
The PSW register contains program status information The register pair (RCAP2H, RCAP2L) are the Cap-
as detailed in Figure 3. ture registers for the Timer 2 "Capture Mode." In this
mode, in response to a transition at the S052's T2EX
STACK POINTER pin, TH2 and TL2 are copied into RCAP2H and
The Stack Pointer Register is S bits wide. It is incre- RCAP2L. Timer 2 also has a 16-bit auto-reload mode,
mented before data is stored during PUSH and CALL and RCAP2H and RCAP2L hold the reload value for
executions. While the stack may reside anywhere in on- this mode. More about Timer 2's features in a later
chip RAM, the Stack Pointer is initialized to 07H after section.
a reset. This causes the stack to begin at location OSH.
CONTROL REGISTERS
DATA POINTER
Special Function Registers IP, IE, TMOD, TCON,
The Data Pointer (DPTR) consists of a high byte T2CON, SCON, and PCON contain control and status
(DPH) and a low byte (OPt). Its intended function is bits for the interrupt system, the Timer/Counters, and
the serial port. They are described in later sections.
7-6
HARDWARE DESCRIPTION OF THE 8051; 8052 AND 80C51
(MSB) (LSB)
CY AC FO RSI RSO OV P
Symbol Position Name and Significance Symbol Position Name and Significance
CY PSW.7 Carry flag. OV PSW.2 Overflow flag.
AC PSW.6 Auxiliary Carry flag. PSW.l User definable flag.
(For BCD operations.) P PSW.O Parity flag.
FO PSW.5 Flag 0 Sett cleared by hardware each
(Available to the user for general instruction cycle to indicate an oddl
purposes.) even number of "one" bits in the
RSI PSW.4 Register bank select control bits 1. & Accumulator, i.e., even parity.
RSO PSW.3 O. Set/cleared by software to NOTE:
determine working register bank (see The. contents of (RS1, RSO) enable the working register banks as
follows:
Note).
(O.O)-Bank 0 (00H-07H)
(0.1 )-Bank 1 (OSH-OFH)
(1.0)-Bank 2 (10H-17H)
(1.1)-Bank 3 (ISH-1FH)
Figure 3. PSW: Program Status Word Register
ADDR/DATA READ
VCC LATCH
INT. BUS
INT. B,:::U::':S~+--l wAITE
TO
WRITE LATCH
TO
LATCH
READ
READ PIN
PIN
270252-3
270252-2
B. Port 1 Bit
A. Port 0 Bit ALTERNATE
OUTPUT
FUNCTION
ADDR
VCC READ
CONTROL LATCH
READ
LATCH
INT-BUS
INT. BUS WRITE
TO
WAITE LATCH
TO
LATCH
READ
PIN
ALTERNATE
INPUT
FUNCTION
270252-4
270252-5
c. Port 2 Bit D. Port 3 Bit
Figure 4. 8051 Port Bit Latches and 1/0 Buffers
'See Figure 5 for details of the internal pullup.
PORT STRUCTURES AND external memory address, time-multiplexed with the
OPERATION byte being written or read. Port 2 outputs the high byte
of the external memory address when the address is 16
All four ports in the 8051 are bidirectional. Each con- bits wide. Otherwise the Port 2 pins continue to emit
sists of a latch (Special Function Registers PO through the P2 SFR content.
P3), an output driver, and an input buffer.
All the Port 3 pins, and (in the 8052) two Port I pins
The output drivers of Ports 0 and 2, and the input buff- are multifunctional. They are not only port pins, but
ers of Port 0, are used in accesses to external memory. also serve the functions of various special features as
In this application, Port 0 outputs the low byte of the listed on the following page.
7-7
inter HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
Port Pin Alternate Function ADDR/DA TABUS). To be used as an input, the port
·P1.0 T2 (Timer/Counter 2 bit latch must contain a I, which turns off the output
external input) driver FET. Then, for Ports 1, 2, and 3, the pin is
·P1.1 T2EX (Timer/Counter 2
pulled high by the internal pullup, but can be pulled
low by an external source.
Capture/Reload trigger)
P3.0 RXD (serial input port) Port 0 differs in not having internal pullups. The pullup
P3.1 TXD '(serial output port) PET in the PO output driver (see Figure 4) is used only
P3.2 INTO (external interrupt) when the Port is emitting Is during external memory
P3.3 INT1 (external interrupt) accesses. Otherwise the pullup FET is off. Consequent-
P3.4 TO (Timer/Counter 0 external ly PO lines that are being used as output port lines are
input) open drain. Writing a I to the bit latch leaves both
P3.5 T1 (Timer/Counter 1 external output FETs off, so the pin floats. In that condition it
input)
can be used a high-impedance input.
. P3.6 WR (external Data Memory
Because Ports 1, 2, and 3 have fixed internal pullups
write strobe) they are sometimes called "quasi-bidirectional" ports.
P3.7 RD (external Data Memory . When configured as inputs they pull high and will
read strobe) source current (IlL, in the data sheets) when externally
pulled low. Port 0, on the other hand, is considered
·PI.O and PI. I serve these alternate functions only on "true" bidirectional, because when configured as an in-
the 8052. put it floats.
The alternate functions can only be activated if the cor- All the port latches in the 8051 have I s written to them
responding bit latch in the port SFR contains a I. Oth- by the reset function. If a 0 is subsequently written to a
erwise the port pin is stuck at O. port latch, it can be reconfigured as an input by writing
a I to it.
1/0 Configurations
Writing to a Port
Figure 4 shows a functional diagram of a typical bit
latch and I/O buffer in each of the four ports. The bit In the execution of an instruction that changes the val-
latch (one bit in the port's SFR) is represented as a ue in a port latch, the new value arrives at the latch
Type D flip-flop, which will clock in a value from the during S6P2 of the final cycle of the instruction. How-
internal bus in response to a "write to latch" signal ever, port latches are in fact sampled by their output
from the CPU. The Q output of the flip-flop is placed buffers only during Phase 1 of any clock period. (Dur-
on the internal bus in response toa "read latch" signal ing Phase 2 the output buffer holds. the value it saw
from the, CPU. The level ofthe port pin itself is placed during the previous Phase I). Consequently, the new
on the internal bus in response to a "read pin" signal value in the port latch won't actually appear at the
from the CPU. Some instructions that read a 'port acti- output pin until the next Phase I, which will be at SIP I
vate the. "read latch" signal, and others activate the of the next machine cycle. See Figure 39 in the Internal
"read pin" signal. More about that later. Timing section.
As shown in Figure 4, the output drivers of Ports 0 and If the change requires a O-to-I transition in Port I, 2; or
2 are switchable to an internal ADDR and ADDR/ 3, an additional pullup is turned on during SIPI and
DATA bus by an internal CONTROL signal for use in S 1P2 of the cycle in which the transition occurs. This is
external memory accesses. During external memory ac- done to increase the transition speed. The extra pullup
cesses, the P2 SFR remains unchanged, but the PO SFR can source about 100 times the current that the normal
gets Is written to it. pullup can. It should be noted that the internal pullups
are field-effect transistors, not linear resistors. The pull-
Also 'shown in Figure 4, is that if aP3 bit latch contains up arrangements are shown in Figure 5.
a 1; then the output levelis controlled by the signal
labeled· "alternate output function." The actual P3.x In HMOS versions of the 8051, the fixed part of the
pin level is always available to the pin's alternate input pullup is a depletion~mode transistor with the gate
function, if any. wired to the source. This transistor will allow the pin to
source about 0.25 mA when shorted to ground. In
Ports 1,2, and 3 have internal pullups, Port 0 has open parallel with the .fixed pullup is an enhancement-mode
drain outputs. Each I/O line can be independently used transistor, which is activated during S 1 whenever the
as an input or an output. (Ports 0 arid 2 may not be port bit does a O-to-l transition. During this interval, if
used as general pilrpose I/O when being used as the the port pin is shorted to ground, this extra transistor
will allow the pin to source an additional 30 mAo
7-8
inter HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
Vcc
2 OSC. PERIODS ENHANCEMENT MODE FET
aD t:L
270252-6
A. HMOS Configuration. The enhancement mode transistor
is turned on for 2 osc. periods after Q makes a O-to-1 transition.
Vcc Vcc Vcc
a
FROM PORT
LATCH
INPUTQ-_ _C
DATA
READ
PORT PIN
270252-7
B. CHMOS Configuration. pFET 1 is turned on for 2 osc. periods after Q
makes a O-to-1 transition. During this time, pFET 1 also turns on pFET 3
through the inverter to form a latch which holds the 1. pFET 2 is also on.
Figure 5. Ports 1 And 3 HMOS And CHMOS Internal Pullup Configurations.
Port 2 is Similar Except That It Holds The Strong Pullup On While Emitting
1s That Are Address Bits. (See Text, "Accessing External Memory".)
In the CHMOS versions, the pullup consists of three Port Loading and Interfacing
pFETs. It should be noted that an n-channel FET
(nFET) is turned on when a logical 1 is applied to its The output buffers of Ports 1, 2, and 3 can each drive 4
gate, and is turned off when a logical 0 is applied to its LS TTL inputs. These ports on HMOS versions can be
gate. A p-channe1 FET (pFET) is the opposite: it is on driven in a normal manner by any TTL or NMOS cir-
when its gate sees a 0, and off when its gate sees a 1. cuit. Both HMOS and CHMOS pins can be driven by
open-co\1ector and open-drain outputs, but note that 0-
pFETI in Figure 5 is the transistor that is turned on for to-l transitions will not be fast. In the HMOS device, if
2 oscillator periods after a O-to-l transition in the port the pin is driven by an open-collector output, a O-to-l
latch. While it's on, it turns on pFET3 (a weak pu\1- transition will have to be driven by the relatively weak
up), through the inverter. This inverter and pFET form depletion mode FET in Figure 5(A). In the CHMOS
a latch which hold the 1. device, an input 0 turns off pu\1up pFET3, leaving only
the very weak pu\1up pFET2 to drive the transition.
Note that if the pin is emitting a 1, a negative glitch on
the pin from some external source can turn off pFET3, In external bus mode, Port 0 output buffers can each
causing the pin to go into a float state. pFET2 is a very drive 8 LS TTL inputs. As port pins, they require exter-
weak pu\1up which is on whenever the nFET is off, in nal pu\1ups to drive any inputs.
traditional CMOS style. It's only about YlO the strength
of pFET3. Its function is to restore a 1 to the pin in the
event the pin had a 1 and lost it to a glitch.
7-9
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
Read-Modify-Write Feature Whenever a 16-bit address is used, the high byte of the
address comes out on Port 2, where it is held for the
Some instructions that read a port read the latch and duration of the read or write cycle. Note that the Port 2
others read the pin. Which ones do which? The instruc- drivers use the strong pullups during the entire time
tions that read the latch rather than the pin are the ones that they are emitting address bits that are Is. This is
that read a value, possibly change it, and then rewrite it during the execution of a MOYX @DPTR instruction.
to the latch. These are called "read-modify-write" in- During this time the Port 2 latch (the Special Function
structions. The instructions listed below are read-mod- Register) does not have to contain Is, and the contents
ify-write instructions. When the destination operand is of the Port 2 SFR are not modified. If the external
a port, or a port bit, these instructions read the latch memory cycle is not immediately followed by another
rather than the pin: external memory cycle, the undisturbed contents of the
ANL (logical AND, e.g., ANL PI, A) Port 2 SFR will reappear in the next cycle.
ORL (logical OR, e.g., ORL P2, A) If an 8-bit address is being used (MOYX @Ri), the
XRL (logical EX-OR, e.g., XRL P3, A) contents of the Port 2 SFR remain at the Port 2 pins
throughout the external memory cycle. This will facili-
JBC Gump if bit = 1 and clear bit, e.g., tate paging.
JBC Pl.1, LABEL)
CPL (complement bit, e.g., CPL P3.0) In any case, the low byte of the address is time-multi-
plexed with the data byte on Port o. The ADDRI
INC (increment, e.g., INC P2) DATA signal drives both FETs in the Port 0 output
DEC (decrement, e.g., DEC P2) buffers. Thus, in this application the Port 0 pins are not
DJNZ (decrement and jump if not zero, e.g., open-drain outputs, and do not require external pull-
DJNZ P3, LABEL) ups. Signal ALE (Address Latch Enable) should be
used to capture the address byte into an external latch.
MOY, PX.Y, C (move carry bit to bit Y of Port X) The address byte is valid at the negative transition of
CLR PX.Y (clear bit Y of Port X) ALE. Then, in a write cycle, the data byte to be written
SETB PX. Y (set bit Y of Port X) appears on Port 0 just before WR is activated, and re-
mains there until after WRis deactivated. In a read
It is not obvious that the last three instructions in this'
cycle, the incoming byte is accepted at Port 0 just be-
list are read-modify-write instructions, but they are. fore the read strobe is deactivated.
They read the port byte, all 8 bits, modify the addressed During any access to external memory, the CPU writes
bit, then write the new byte back to the latch. OFFH to the Port 0 latch (the Special Function Regis-
ter), thus obliterating whatever information the Port 0
The reason that read-modify-write instructions are di- SFR may have been holding. If the user writes to Port 0
rected to the latch rather than the pin is to avoid a during an external memory fetch, the incoming code
possible misinterpretation of the voltage level at the byte is corrupted. Therefore, do not write to Port 0 if
pin. For example, a port bit might be used to drive the external program memory is used.
base of a transistor. When a 1 is written to the bit, the
transistor is turned on. If the CPU then reads the same External Program Memory is accessed under two con-
port bit at the pin rather than the latch, it will read the ditions:
base voltage of the transistor and interpret it as a O. 1) Whenever signal EA is active; or
Reading the latch rather than the pin will return the
correct value of 1. 2) Whenever the program counter (PC) contains a
number that is larger than OFFFH (IFFFH for the
8052).
ACCESSING EXTERNAL MEMORY This requires that the ROMless versions have EA wired
low to enable the lower 4K (8K for the 8032) program
Accesses to external memory are of two types: accesses bytes to be fetched from external memory.
to external Program Memory and accesses to external
Data Memory. Accesses to external Program Memory When the CPU is executing out of external Program
use' signal PSEN (program store enable) as the read Memory, all 8 bits of Port 2 are dedicated to an output
strobe. Accesses to external Data Memory use RD or function and may not be used for general purpose I/O.
WR (alternate functions of P3. 7 and P3.6) to strobe the During external program fetches they output the high
memory. Refer to Figures 36 through 38 in the Internal byte of the PC. During this time the Port 2 drivers use
Timing section. the strong pullups to emit PC bits that are 1s.
Fetches from external Program Memory always use a
16-bit address. Accesses to external Data Memory can TIMER/COUNTERS
use either a 16-bit address (MOYX @DPTR) or an The 8051 has two 16-bit Timer/Counter registers: Tim-
8-bit address (MOYX @Ri). er 0 and Timer 1. The 8052 has these two plus one
7-10
infef HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
more: Tinier 2. All three can be configured to operate four operating modes, which are selected by bit-pairs
either as timers or event counters. (MI, MO) in TMOD. Modes 0, I, and 2 are the same'
for both Timer/Counters. Mode 3 is different; The four
In the "Timer" function, the register is incremented operating modes are described in the following text.
every machine cycle. Thus, one can think of it as count-
ing machine cycles. Since a machine cycle consists of 12
oscillator periods, the count rate is '/12 of the oscillator MODE 0
frequency.
Either Timer in Mode 0 is an 8-bit Counter with a
divide-by-32 prescaler. This 13-bit timer is Mcs-48
In the "Counter" function, the register is incremented
compatible. Figure 7 shows the Mode 0 operation as it
in response to a I-to-O transition at its corresponding
applies to Timer 1.
external input pin, TO, TI or (in the 8052) T2. In this
function, the external input is sampled during S5P2 of
In this mode, the Timer register is configured as a
every machine cycle. When the samples show a high in
13-Bit register. As the count rolls over from all Is to all
one cycle and a low in the next cycle, the count is incre-
Os, it sets the Timer interrupt flag TFI. The counted
mented. The new count value appears in the register input is enabled to the Timer when TRI = I and either
duringS3PI of the cycle following the one in which the
GATE = 0 or INTI = 1. (Setting GATE = I allows
transition was detected. Since it takes 2 machine cycles
the Timer to be controlled by external input INTI, to
(24 oscillator periods) to recognize a I-to-O transition,
facilitate pulse width measurements.) TRI is a control
the maximum count rate is '/24 of the oscillator fre-
bit in the Special Function Register TCON (Figure 8).
quency. There are no restrictions on the duty cycle of
GATE is in TMOD.
the external input signal; but to ensure that a given
level is sampled at least once before it changes, it
The 13-Bit register consists of all 8 bits ofTHI and the
should be held for at least one full machine cycle:
lower 5 bits of TL 1. The upper 3 bits of TL 1 are inde-
terminate and should be ignored. Setting the run flag
In addition to the "Timer" or "Counter" selection,
(TR I) does not clear the registers.
Timer 0 and Timer I have four operating modes from
which to select. Timer 2, in the 8052, has three modes
Mode 0 operation is the same for Timer 0 as for Timer
of operation: "Capture," "Auto-Reload" and "baud
1. Substitute TRO, TFO and INTO for the correspond-
rate generator."
ing Timer I signals in Figure 7. There are two different
GATE bits, one for Timer I (TMOD.7) and one for
Timer 0 (TMOD.3).
Timer 0 and Timer 1
These Timer/Counters are present in both the 8051 and MODE 1
the 8052. The "Timer" or "Counter" function is select-
ed by control bits clf in the Special Function Register Mode I is the same as Mode 0, except that the Timer
TMOD (Figure 6). These two Timer/Counters have register is being run with all 16 bits.
(LSB)
CIT M1 MO 1 GATE CIT I M1 MO J
•
Timer 1 Timer 0
GATE Gating control when set. Timer/Counter "x" is enabled M1 MO Operating Mode
only while "INTx" pin is high and "TRx" control pin is o o 8-bit Timer/Counter "THx" with "TLx" as S-bit
set. When cleared Timer "x" is enabled whenever prescaler.
"TRx" control bit is set. o 16-bitTimer/Counter,"THx" and "TLx" are
CIT Timer or Counter Selector cleared for Timer operation cascaded; there is no prescaler.
(input from internal system clock). Set for Counter o 8-bit auto-reload Timer/Counter "THx" holds a
operation (input from "Tx" input pin). value which is to be reloaded into "TLx" each
time it overflows.
(Timer 0) TLO is an 8-bit Timer/Counter
controlled by the standard Timer 0 control bits.
THO is an 8-bit timer only controlled by Timer 1
control bits.
(Timer 1) Timer/Counter 1 stopped,
Figure 6. TMOD: Timer/Counter Mode Control Register
7-11
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
clf=o
INTERRUPT
T1 PIN
______-'j -
cil' =1
TR1-----t
270252-9
Figure 7. Timer/Counter 1 Mode 0: 13-Slt Counter
(MSB) (LSB)
TF1 TR11 TFO TRO IE1 ITI lEO ITO
Symbol position Name and Significance Symbol POlltlon Name and Significance
TF1 ' TCON.7 Timer I overflow Flag. Set by lEI TCON.3' Interrupt I Edge flag. Set by hardware
hardware on Timer/Counter overflow. when 'external interrupt edge
Cleared by hardware when proc~ssor . detected. Cleared when interrupt
vectors to interrupt routine. processed.
TRI TCON.S Timer I Run control bit. Set!cleared ITI TCON.2 Interrupt I Type control bit. Set!
by software to tum Timer/Counter on/ cleared by software to, specify falling·
off. edgellow level triggered external
TFO TCON.S Timer 0 overflow Flag. Set by interrupts.
hardware on Timer/Counter overflow. lEO TCON.l Interrupt 0 Edge flag. Set by hardware
Cleared by hardware when processor when external interrupt edge
vectors to interrupt routine. detected. Cleared when interrupt
TRO TCON.4 Tim~r a Run control bit. Set!cleared processed.
by software to turn Timer/Counter on/ ITO TCON.O Interrupt a Type control b~. Set!
off. cleared by software to specify failing
edgellow level triggered external
interrupts.
Figure a.TCON: Timer/Counter Control Register
MODE 2 Timer 0, in Mode 3 establishes TLO and THO as two
separate counters. The logic for Mode 3 on Timer 0 is
Mode 2 configures the Timer register· as an 8-bit Coun- shown in Figure 10. TLO uses the Timer 0 control bits:
ter (TLl) with automatic reload, as shown in Figure 9. clf, GATE, TRO, INTO, and TFO. THO is locked into
Overflow fromTLl not only sets TFl; but also reloads a timer function (counting machine cycles) and takes
TLl with the contents of THI, which is preset by soft- over the use ofTRI and TFI from Timer 1. Thus, THO
ware. The reload leaves THI unchanged. now controls the "Timer I" interrupt.
Mode 2 operation is the same for Timer/Counter O. Mode 3 is provided for applications requiring an extra
8-bit timer or counter. With Timer 0 in Mode 3, an
8051 can look like it has three Timer/Counters, and an
MODE 3 8052, like it has four. When Timer 0 is in Mode 3,
Timer I in Mode 3 simply holds its count. The etTect is Timer I can be turned on and otT by switching it out of
the same as setting TRI = O. and into its own Mode 3, or can still be used by the
serial port as a bliud rate generator, or In fact, in any
application not requiring an interrupt.
7-12
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
INTERRUPT
270252-10
Figure 9. Timer/Counter 1 Mode 2: 8-Bit Auto-Reload
osc ~B- 1/12 lose
1/12 lose - - - - - - - ,
t----INTERRUPT
TO PIN - - - - - - - - '
CONTROL
TRO'-----t
GATE
INTO PIN
1112 lose -------------+1-1
_ ______
1·1 (:~~)
~~CONTROL
H. _TF_1~~ INTERRUPT
TR1 -
270252-11
Figure 10. Timer/Counter 0 Mode 3: Two 8-Bit Counters
Timer 2
Table 2. Timer 2 Operating Modes
Timer 2 is a 16-bit Timer/Counter which is present
only in the 8052. Like Timers 0 and I, it can operate RCLK + TCLK CP/RL2 TR2, Mode
either as a timer or as an event counter. This is selected 0 0 1 16-bit Auto-Reload
by bit C/T2 in the Special Function Register T2CON
0 1 1 16-bit Capture
(Figure II). It has three operating modes: "capture,"
"auto-load" and "baud rate generator," which are se- 1 X 1 Baud Rate Generator
lected by bits in T2CON as shown in Table 2. X X 0 (off)
7-13
intJ HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
(MSB) (LSB)
TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2
Symbol Position Name and Significance
TF2 T2CON.7 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software.
TF2 will not be set when either RCLK = 1 or TCLK = 1.
EXF2 T2CON.6 Timer 2 external flag set when either a capture or reloa.d is caused by a nagative
transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1
will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must ba
cleared by software.
RCLK T2CON.5 Receive clock flag. When set, causes the serial port to use Timer 2 overflow
pulses for its receive clock in Modes 1 and 3. RCLK = 0 causes Timer 1 overflow
to be used for the receive clock.
TCLK T2CON.4 Transmit clock flag. When set, causes ttie serial port to use Timer 2 overflow
pulses for its transmit clock in modes 1 and 3. TCLK = 0 causes Timer 1
overflows to be used for the transmit clock.
EXEN2 T2CON.3 Timer 2 external enable flag. When set, allows a capture or reload to occur as a
result of a negative transition on T2EX if Timer 2 is not being used to clock the
serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
TR2 T2CON.2 Start/stop control for Timer 2. A logic 1 starts the iimer.
C/i2 T2CON.l Timer or counter select. (Timer 2)
o = Internal timer (OSCI12)
1 = External event counter (falling edge triggered).
CP/RL2 T2CON.O 'Capture/Reload flag. When set, captures will occur on negative transitions at
T2EX if EXEN2 = 1. When cleared, auto-reloads will occur either with Timer 2
overflows or negative transitions at T2EX when EXEN2 = 1. When either RCLK
= 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on
Timer 2 overflow.
Figure 11. T2CON: Timer/Counter 2 Control Register
In the Capture Mode there are two options which are added feature that a I-to-O transition at external input
selected by bit EXEN2 in T2CON. If EXEN2 = 0, T2EX will also trigger the 16-bit reload and set EXF2.
then Timer 2 is a 16-bit timer or counter which upon
overflowing' sets bit TF2, the Timer 2 overflow bit, The auto-reload mode is illustrated in Figure 13.
which can be used to generate an interrupt. .If EXEN2
= I, then Timer 2 still does the above, but with the . The baud rate generator mode is selected by RCLK =
added feature that a I-to-O transition at external input 1 and/or TCLK ,,;, 1. It will be described in conjunc-
T2EX causes the current value in the Timer 2 registers, tion with the serial port.
TL2 and TH2, to be captured into registers RCAP2L
and RCAP2H, respectively. (RCAP2t and RCAP2H
are new Special Function Registers in the 8052,) In SERIAL INTERFACE
addition, the transition at T2EX causes bit EXF2 in
T2CON to be set, and EXF2, like TF2, can generate an The serial port is full duplex, meaning it can transmit
interrupt. and receive simultaneously. It is also receive-buffered,
meaning ·it can commence reception of a second byte
The Capture Mode is illustrated in Figure 12. before a previously received byte has been read from
the receive register.' (However, if the first byte still
In the auto-reload mode there are again two options, hasn't been read by·the time reception of the second
which are selected by bit EXEN2 in nCON. If byte is complete, one of the bytes will be lost). The
EXEN2 = 0, then when Timer 2 rolls over it not only serial port receive and transmit 'registers are bqth ac-
sets TF2 but also causes the Timer 2 registers to be cessed at Special Function Register SBUF, Writing to
reloaded with the 16-bit value in registers RCAP2L SBUF loads the transmit register, and reading SBUP
and RCAP2H, which are preset by software. IfEXEN2 accesses a physically separate receive register.
= I, then Timer 2 still does the a90ve, but with the
7-14
inter HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
nMER2
INTERRUPT
EXEN2
270252-12
Figure 12. Timer 2 in Capture Mode
The serial port can operate in 4 modes: Multiprocessor Communications
Mode 0: Serial data enters and exits through RXD. Modes 2 and 3 have a special provision for multipro-
TXD outputs the shift clock. 8 bits are transmitted/re- cessor communications. In these modes, 9 data bits are
ceived: 8 data bits (LSB first). The baud rate is fixed at received. The 9th one goes into RB8. Then comes a
1/12 the oscillator frequency. stop bit. The port can be programmed such that when
the stop bit is received, the serial port interrupt will be
Mode 1: 10 bits are transmitted (through TXD) or re- activated only if RB8 = 1. This feature is enabled by
ceived (through RXD): a start bit (0), 8 data bits (LSB setting bit SM2 in SCaN. A way to use this feature in
first), and a stop bit (1). On receive, the stop bit goes multiprocessor systems is as follows.
into RB8 in Special Function Register SCaN. The
baud rate is variable. When the master processor wants to transmit a block of
data to one of several slaves, it first sends out an ad-
Mode 2: 11 bits are transmitted (through TXD) or re- dress byte which identifies the target slave. An address
ceived (through RXD): a start bit (0), 8 data bits (LSB byte differs from a data byte in that the 9th bit is 1 in an
first), a programmable 9th data bit, and a stop bit (1). address byte and 0 in a data byte. With SM2 = 1, no
On Transmit, the 9th data bit (TB8 in SCaN) can be slave will be interrupted by a data byte. An address
assigned the value of 0 or 1. Or, for example, the parity byte, however, will interrupt all slaves, so that each
bit (P, in the PSW) could be moved into TB8. On re- slave can examine the received byte and see if it is being
ceive, the 9th data bit goes into RB8 in Special Functon addressed. The addressed slave will clear its SM2 bit
Register SCaN, while the stop bit is ignored. The baud and prepare to receive the data bytes that will be com-.
rate is programmable to either '/32 or '164 the oscillator ing. The slaves that weren't being addressed leave their
frequency. SM2s set and go on about their business, ignoring the
coming data bytes.
Mode 3: 11 bits are transmitted (through TXD) or re-
SM2 has no effect in Mode 0, and in Mode 1 can be
ceived (through RXD): a start bit (0), 8 data bits (LSB
used to check the validity of the stop bit. In a Mode 1
first), a programmable 9th data bit and a stop bit (1). In
reception, if SM2 = 1, the receive interrupt will not be
fact, Mode 3 is the same as Mode 2 in all respects
activated unless a valid stop bit is received.
except the baud rate. The baud rate in Mode 3 is vari-
able.
Serial .Port Control Register
In all four modes, transmission is initiated by any in-
struction that uses SBUF as a destination register. Re- The serial port control and status register is the Special
ception is initiated in Mode 0 by the condition RI = 0 Function Register SCaN, shown in Figure 14. This
and REN = 1. Reception is initiated in the other register contains not only the mode selection bits, but
modes by the incoming start bit if REN = 1. also the 9th data bit for transmit and receive (TB8 and
RB8), and the serial port interrupt bits (TI and RI).
7-15
intJ HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
TIMER 2
INTERRUPT
EXEN2
270252-13
Figure 13. Timer 2 in Auto-Reload Mode
(M8B) (LSB)
8MO 8Ml 8M2 REN TBB RBB TI RI
Where 8MO, 8Ml specify the serial port mode, as lollows: • TBB is the 9th data bit that will be
transmitted in Modes 2 and 3. 8et or
SMO
0
0
8Mt
0
t
0
Mode
0
2
Description
shift register
8-bHUART
9-bitUART
Baud Rate
1060/ 12
variable
. RB8
clear by software as desired.
in Modes 2 and 3, is the 9th data bit
that was received. In Mode I, if 8M2
lose/ 64
= 0, RBB Is the stop bit that was
or
received. In Mode 0, RBB is not used.
lose/32
3 9'bit UART variable • TI is transmH interrupt flag. 8et by
• 8M2 enables the multiprocessor hardware at the end of the 8th bit time
communication leature in Modes 2 in Mode 0, or at the beginning 01, the
and 3. In Mode 2 or 3, il 8M2 is set to stop bit in the other modes, in any
1 then RI will not be activated il the serial transmission. Must be cleared
received 9th data bit (RB8) is O. 'In by software.
Mode t, if 8M2 = t then RI will not
• RI is receive interrupt flag. Set by
be activated if a valid stop bit was not
received. In Mode 0, 8M2 should be hardware at the end of the 8th bit time
O. in Mode 0, or halfway through the stop
• REN enables serial reCeption. 8et by bH time in the other modes, in any
software to enable reception. Clear serial reception (except see 8M2).
by software to disable reception. Must be cleared by software.
Figure 14. SCON: Serial Port Control Register
Baud Rates
The baud rate in Mode 0 is fixed: 2 SMOD
Mode 2 Baud Rate = - - x (Oscillator Frequency)
, 64 '
Oscillator Frequency
Mode 0 Baud Rate = 12'
In the 80SI"the baud rates in Modes 1 and 3 are deter-
mined by the Timer 1 overflow nite. In the 8052, these
The baud rate in Mode 2 depends on the value of bit baud rates can,be determined by Timer I, or by Timer
SMOD in Special Function Register peON. If SMOD 2, or by both (one for transmit and the other for re-
= 0 (which is the value on reset), the baud rate '184 the ceive).
oscillator frequency. If SMOD = I, the baud rate is
'/32 the oscillator frequency.
7-16
HARDWARE DESCRIPTION OF THE 8051, 8052 AND80C51
Using Timer 1 to Generate Baud Rates mode (high nibble of TMOD = 00 lOB). In that case,
the baud rate is given by the formula
When Timer 1 is used as the baud rate generator, the
baud rates in Modes I and 3 are determined by the Modes I, 3 2SMOD Oscillator Frequency
Timer I overflow rate and the value of SMOD as fol- Baud Rate = - - - X ---::----...!....-~
32 12x [256 - (THI)l
lows:
Modes 1,3 2SMOD One can achieve very low baud rates with Timer I by
Baud Rate = - - - X (Timer I Overflow Rate) leaving the Timer I interrupt enabled, and configuring
32 the Timer to run as a 16-bit timer (high nibble of
TMOD = OOOIB), and using the Timer I interrupt to
The Timer 1 interrupt should be disabled in this appli- do a 16-bit software reload.
cation. The Timer itself can be configured for either
"timer" or "counter" operation, and in any of its 3 Figure 15 lists various commonly used baud rates and
running modes. In the most typical applications, it is how they can be obtained from Timer I.
configured for "timer" operation, in the auto-reload
Timer 1
Baud Rate fosc SMOD Reload
CIT Mode
Value
Mode 0 Max: 1 MHZ 12MHZ X X X X
Mode 2 Max: 375K 12MHZ 1 X X X
Modes 1, 3: 62.5K 12MHZ 1 0 2 FFH
19.2K 11.059 MHZ 1 0 2 FDH
9.6K 11.059 MHZ 0 0 2 FDH
4.BK 11.059 MHZ 0 0 2 FAH
2.4K 11.059 MHZ 0 0 2 F4H
1.2K 11.059 MHZ 0 0 2 EBH
137.5 11.986 MHZ 0 0 2 1DH
110 6MHZ 0 0 2 72H
110 12MHZ 0 0 1 FEEBH
Figure 15. Timer 1 Generated Commonly Used Baud Rates
Using Timer 2 to Generate Baud Rates II). Note then the baud rates for transmit and receive
can be simultaneously different. Setting RCLK and/or
In the 8052, Timer 2 is selected as the baud rate genera- TCLK puts Timer 2 into its baud rate generator mode,
tor by setting TCLK and/or RCLK in T2CON (Figure as shown in Figure 16.
nMER1
OVERFLOW
RX CLOCK
TX CLOCK
EXEN2
L NOTE AVAILABILITY OF ADDmoNAL EXTERNAL INTERRUPT
270252-14
Figure 16. Timer 2 in Baud Rate Generator Mode
7-17
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
The baud rate generator mode is similar to the auto-re- Transmission is initiated by any instruction that uses
load mode, in that a rollover in TH2 causes the Timer 2 SBUF as a destination register. The "write to SBUF"
registers to be reloaded with the 16-bit value in registers signal at S6P2 also loads a 1 into the 9th position of the
RCAP2H and RCAP2L, which are preset by software. transmit shift register and tells the TX .Control block to
commence a transmission. The internal timing is such
Now, the baud rates in Modes 1 and 3 are determined that one full machine cycle will elapse between "write
by Timer 2's overflow rate as follows: to SBUF," and activation of SEND.
Timer 2 Overflow Rate SEND enables the output of the shift register to the
Modes I, 3 Baud Rate = --------- alternate output function line of P3.0, and also enables
16
SHIFT CLOCK to the alternate output function line of
The Timer can be configured for either "timer" or P3. L SHIFT CLOCK is low during S3, S4, and S5 of
"counter" operation. In the most typical applications, it every machine cycle, and high during S6, SI and S2. At
is configured for "timer" operation (C/T2 = 0). "Tim- S6P2 of every machine cycle in which SEND is active,
er" operation is a little different for Timer 2 when it's the contents of the transmit shift register are shifted to
being used as a baud rate generator. Normally, as a the right one position.
timer it would increment every machine cycle (thus at As data bits shift out to the right, zeroes come in from
'1'2 the oscillator frequency). As a baud rate generator, the left. When the MSB of the data byte is at the output
however, it increments every state time (thus at % the
position of the shift register, then the 1 that was initial-
oscillator frequency). In that case the baud rate is given ly loaded into the 9th position, is just to the left of the
by the formula
MSB, and all positions to the left of that contain zeroes.
Modes I, 3 Oscillator Frequency This condition flags the TX Control block to' do one
Baud Rate = --,,--------'---..:..--- last shift and then deactivate SEND and set TI. Both of .
32x [65536 -(RCAP2H, RCAP2L)1 these actions occur at SIPI of the 10th machine cycle
after "write to SBUF."
where (RCAP2H, RCAP2L) is the content of
RCAP2H and RCAP2L taken as a 16-bit unsigned in- Reception is initiated by the condition REN = I and
teger. RI = O. At S6P2 of the next machine cycle, the RX
Control unit writes the bits 11111110 to the receive
Timer 2 as a baud rate generator is shown in Figure 16. shift register, and in the next clock phase activates RE-
This Figure is valid only if RCLK + TCLK = I in CEIVE.
T2CON. Note that a rollover in TH2 does not set TF2,
RECEIVE enables SHIFT CLOCK to the alternate
and will not generate an interrupt. Therefore, the Timer
2 interrupt does not have to be disabled when Timer 2 output function line of P3. L SHIFT CLOCK makes
transitions at S3PI and S6PI of every machine cycle.
is in the baud rate generator mode. Note too, that if
EXEN2 is set, a I.-to-O transition in T2EX will set At S6P2 of every machine cycle in which RECEIVE is
active, the contents of the receive shift register are shift-
EXF2 but will not cause a reload from (RCAP2H,
ed to the left one position. The value that comes in
RCAP2L) to (TH2, TL2). Thus when Timer 2 is in use
from the right is the value that was sampled at the P3.0
as a baud rate generator, T2EX can be used as an extra
pin at S5P2 of the same machine cycle.
external interrupt, if desired.
As data bits come in from the right, Is shift out to the
It should be noted that when Timer 2 is running (TR2 left. When the 0 that was initially loaded into the right-
= I) in "timer" function in the baud rate generator
most position arrives at the leftmost position in the shift
mode, one should not try to read or write TH2 or TL2.
register, it flags the RX Control block to do one last
Under these conditions the Timer is being incremented shift and load SBUF..At SIPI of the 10th machine
every state time, and the results of a read or write may
cycle after the write to SCaN that cleared RI, RE-
not be accurate. The RCAP registers may be read, but CEIVE is cleared and RI is set.
shouldn't be written to, because a write might overlap a
reload and cause write and/or reload errors. Tum the
Timer off (clear TR2) before accessing the Timer 2 or More About Mode 1
RCAP registers, in this case. Ten bits are transmitted (through TXD), or received
(through RXD): a start bit (0), 8 data bits (LSB first),
and a stop bit (I). On receive, the stop bit goes into
More About Mode 0
RB8 in SCaN. In the 8051 the baud rate is determined
Serial data enters and exits through RXD. TXD out- by the Timer 1 overflow rate. In the 8052 it is deter-
puts the shift clock. 8 bits are transmitted/received: 8 mined either by the Timer I overflow rate, or the Timer
data bits (LSB first). The baud rate is fixed at '/'2 the 2 overflow rate, or both (one for transmit and the other
oscillator frequency. . for receive).
Figure 17 shows a simplified functional diagram of the Figure 18 shows a simplified functional diagram of the
serial port in Mode 0, and associated timing. serial port in Mode I, and associated timings for trans-
mit receive.
7-18
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
WRITE
SBUF
TO ----r~=t~~:J~--~~----_,-.--------r RXD
P3.0ALT
OUTPUT
FUNCTION
56 --r------1
TXD
P3.1 ALT
OUTPUT
FUNCTION
~------~RXCLOCK
REN RX CONTROL SHIFT
Ri_........__J-----fSTART 1 1 1 1 1 1 1 0
RXD
P3.0ALT
INPUT
FUNCTION
REAO
SBUF
ALE
~WRITE TO SBUF
SENDLS6P2 I
SHIFT
RXD (DATA OUT) \ TRANSMIT
~ WRITE TO SCON (CLEAR RI)
~RII~~~====r=======================================================~'----
'!.ECEIVE
SHIFT
~
RECEIVE
RXD (DATA IN)---IJ7=--{}!!!---o~----{~c---.£r!::!----{)'!!:!...--Cf!'!!!.-~rc.....:..-
TXD (SHIFT CLOCK)
270252-15
Figure 17. Serial Port Mode 0
7-19
infef HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
TIMER 1 TIMER2
OVERFLOW OVERFLOW
WRIT:-E--,---==:jrot~~~
TO
SBUF
__~~____} -__-r~L-__~~
TXD
TRANSMIT
'-16 RESET
RECEIVE
1
---f:;~lOCk' n *!!l>TART BIl~
BIT DETECTOR SAMPLE TIMES
DO p. D' .3 .. os Pi 01 STOP BIT
SHIFT
______________________________________________________Jr----
~RLI
270252-16
Figure 18. Serial Port Mode 1. TCLK, RCLK and Timer 2 are Present in the 8052/8032 Only.
Transmission is initiated by any instruction that uses times are synchronized to the divide-by-16 counter, not
SBUF as a destination register. The "write to SBUF" to the "write to SBUF" signal).
signal also loads a 1 into the 9th bit position of the
transmit shift register and flags the TX Control unit The transmission begins with activation of SEND,
that a transmission is requested. Transmission actually which puts the start bit at TXD. One bit time later,
commences at SIP 1 of the machine cycle following the DATA is activated, which enables the output bit of the
next rollover in the divide-by-16 counter. (Thus, the bit transmit shift register to TXD. The first shift pulse oc-
curs one bit time after that.
infef HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
As data bits shift out to the right, zeroes are clocked in mit, the 9th data bit (TBS) can be assigned the value of
from the left. When the MSB of the data byte is at the o or 1. On receive, the 9th data bit goes into RBS in
output position of the shift register, then the 1 that was SCON. The baud rate is programmable to either '1.2 or
initially loaded into the 9th position is just to the left of 1/64 the oscillator frequency in Mode 2. Mode 3 may
the MSB, and all positions to the left of that contain have a variable baud rate generated from either Timer I
zeroes. This condition flags the TX Control unit to do or 2 depending on the state of TCLK and RCLK.
one last shift and then deactivate SEND and set TI.
This occurs at the 10th divide-by-16 rollover after Figures 19 and 20 show a functional diagram of the
"write to SBUF." serial port in Modes 2 and 3. The receive portion is
exactly the same as in Mode 1. The transmit portion
Reception is initiated by a detected I-to-O transition at differs from Mode I only in the 9th bit of the transmit
RXD. For this purpose RXD is sampled at a rate of 16 snift register.
times whatever baud rate has been established. When a
transition is detected, the divide-by-16 counter is imme- Transmission is initiated by any instruction that uses
diately reset, and IFFH is written into the input shift SBUF as a destination register. The "write to SBUF"
register. Resetting the divide-by-16 counter aligns its signal also loads TBS into the 9th bit position of the
rollovers with the boundaries of the incoming bit times. transmit shift register and flags the TX Control unit
that a. transmission is requested. Transmission com-
The 16 states of the counter divide each bit time into mences at SIPI of the machine cycle following the next
16ths. At the 7th, Sth, and 9th counter states of each bit rollover in the divide-by-16 counter. (Thus, the bit
time, the bit detector samples the value of RXD. The times are synchronized to the divide-by-16 counter, not
value accepted is the value that was seen in at least 2 of to the "write to SBUF" signal.)
the 3 samples. This is done for noise rejection. If the
value accepted during the first bit time is not 0, the The transmission begins with activation of SEND,
receive circuits are reset and the unit goes back to look- which puts the start bit at TXD. One bit time later,
ing for another I-to-O transition. This is to provide re- DATA is activated, which enables the output bit of the
jection of false start bits. If the start bit proves valid, it transmit shift register to TXD. The first shift pulse oc-
is shifted into the input shift register, and reception of curs one bit time after that. The first shift clocks a 1
the rest of the frame will proceed. (the stop bit) into the 9th bit position of the shift regis-
ter. Thereafter, only zeroes are clocked in. Thus, as
As data bits come in from the right, Is shift out to the data bits shift out to the right, zeroes are clocked in
left. When the start bit arrives at the leftmost position from the left. When TBS is at the output position of the
in the shift register, (which in mode 1 is a 9-bit regis- shift register, then the stop bit is just to the left of TBS,
ter), it flags the RX Control block to do one last shift, and all positions to the left of that contain zeroes. This
load SBUF and RBS, and set RI. The signal to load condition flags the TX Control unit to do one last shift
SBUF and RBS, and to set RI, will be generated if, and and then deactivate SEND and set TI. This occurs at
only if, the following conditions are met at the time the the 11th divide-by-16 rollover after "write to SBUF."
fmal shift pulse is generated.
Reception is initiated by a detected I-to-O transition at
1) RI = 0, and RXD. For this purpose RXD is sampled at a rate of 16
2) Either SM2 = 0, or the received stop bit = 1 times whatever baud rate lias been established. When a
transition is detected, the divide-by-16 counter is imme-
If either of these two conditions is not met, the received diately reset, and IFFH is written to the input shift
frame is irretrievably lost. If both conditions are met, register;
the stop bit goes into RBS, the S data bits go into
SBUF, and RI is activated. At this time, whether the 'At the 7th, Sth and 9th counter states of each bit time,
above conditions are met or not, the unit goes back to the bit detector samples the value of RXD. The value'
looking for a I-to-O transition in RXD. accepted is the value that was seen in at least 2 of the 3
samples. If the value accepted' during the first bit time
is not 0, the receive circuits are reset and the unit goes
More About Modes 2 and 3 back to looking for another 1-10-0 transition. If the
start bit proves valid, it is shifted into the input shift
Eleven bits are transmitted (through TXD), or received register, and reception of the rest of the frame will pro-
(through RXD): a star1 bit (0), S data bits (LSB first), a ceed.
programmable 9th data bit, and a stop bit (1).,On trans-
7-21
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
WRITE
TO
SBUF
TXD
PHASE 2 CLOCK
(~Io.c)
MODE2
TI
SMOD=1 SERIAL
PORT
INTERRUPT
SMOD=O
(SMOD IS PCON.7) '--..-_-'--1
LOAD
SBUF
RXD
~ D n q 0 I1--.J TRANSMIT
TxD\IT••TIIT/ DO I D1:::c:MJ D3 CJK.1:b5:~::;;tBiii8r=;I==S:;TO;;:P;:;;:BI;;T~=
TI
~---------------------------------- ____________________~r----
270252~17
Figure 19. Serial Port Mode 2
7-22
inter HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
TIMER 1 TIMER 2
OVERFLOW OVERFLOW
WRITE
SBUF
TO --~r-~===J~~~r---~~~---'~--~~L-~~~ TXD
TCLK - TXCONTROL
TI
RI LOAD
SBUF
SHIFT 1----------,
RXD
TX
_fLOC~~~~~~~~_~'_ _'~_J~__~~__- J ' L - _ J L -_ _~~_ _"'_~'L-___
-----1 WRITE TO SBUF
-----, SEND
DATA L SlP1 I
TRANSMIT
STOP BIT
I
~~~----------------------------~
~R~X~D~B~I~T~D~E~T~EC~Tf,O~R~I~n;A~RT~'~"~/~~~~~~:i~~:ii:~:i~~~==~---1-~
RECEIVE
1
SHIFT
~R~I
SAMPLE TIMES
____,L-__~L__ __ " , L -_ __",_ _ _ _~'_ _ _ _~L____~L____JL____~~_____
______________________________________ ~r-----
270252-18
Figure 20. Serial Port Mode 3. TCLK, RCLK, and Timer 2 are Present in the 805218032 Only.
7-23
inter HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
As data bits come in from the right, Is shift out to the was transition-activated. If the interrupt was level-acti-
left. When the start bit arrives at the leftmost position vated, then the external requesting source is what con-
in the shift register (which in Modes 2 and 3 is a 9-bit trols the request flag, rather than the on-chip hardware.
register), it flags the RX Control block to do one last
shift, load SBUF and RB8, and set RI. The signal to The Timer 0 and Timer I Interrupts are generated by
load SBUF and RB8, and to set RI, will be generated if, TFO and TFI, which are set by a rollover in their re-
and only if, the following conditions are met at the time spective Timer/Counter registers (except see Timer 0 in
the final shift pulse is generated: Mode 3). When a timer interrupt is generated, the flag
that generated it is cleared by the on-chip hardware
1) RI = 0, and when the service routine is vectored to.
2) Either SM2 = 0 or the received 9th data bit = 1
The Serial Port Interrupt is generated by the logical OR
If either of these conditions is not met, the received of RI and TI. Neither of these flags is cleared by hard-
frame is irretrievably lost, and RI is not set. If both ware when the service routine is vectored to. In fact;
conditions are met, the received 9th data bit goes into the service routine will normally have to determine
RB8, and the first 8 data bits go into SBUF. One bit whether it was RI or TI that generated the interrupt,
time later, whether the above conditions were met or and the bit will have to be cleared in software.
not, the unit goes back to looking for a I-to-O transition
at the RXD input. In ,the 8052, the Timer 2 Interrupt is generated by the
logical OR of TF2 and EXF2. Neither of these flags is
Note that the value of the received stop bit is irrelevant cleare,d by hardware when the service routine is vec-
to SBUF, RB8, or RI. toredto. In fact, the service routine may have to deter-
mine whether it was TF2 or EXF2 that generated the
interrupt, and the bit will have to be cleared in soft-
INTERRUPTS ware.
The 8051 provides 5 interrupt sources. The 8052 pro- All of the bits that generate interrupts can be set or
vides 6. These are shown in Figure 21. cleared by software, with the same result as though it
had been set or cleared by hardware. That is, interrupts
The External Interrupts INTO and INTlcan each be can be generated or pending interrupts can be canceled
either level-activated or transition-activated, depending in software.
on bits ITO and ITl in Register TCON. The flags that
actually generate these interrupts are bits lEO and lEI (MSB) (LSB)
in TCON. When an external interrupt is generated, the
flag that generated it is cleared by the hardware when 1~1-1~1~lml~I~I~1
Enable Bit = 1 enables the interrupt.
the service routine is vector~ to only if the interrupt Enable B~ = 0 disables ~.
Symbol Position Function
EA IE.7 disables all interrupts. II ~ = 0, no
interrupt will be acknowledged. II ~
= 1. each interrupt source is
individually enabled or disabled by
setting or clearing its enable bit.
1E.6 reserved.
~----------------. ET2 IE.5 Timer 2 interrupt enable bit.
ES IE.4 Serial Port interrupt enable b~.
ETI IE.3 Timer 1 interrupt enable bit
INTERRUPf
SOURCES EXI IE.2 External interrupt 1 enable b~.
ETO IE. 1 Timer 0 interrupt enable bit.
EXO lE.O External interrupt 0 enable bit.
DI--~------------·· User software should never write 1s to unimplemented bits, since
they may be used in luture MCS-51 products.
Figure 22. IE: Interrupt Enable Register
270252-19
Figure 21. MCS@)·51 Interrupt Sources
7-24
inter HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
Each of these interrupt sources can be individually en- ceived simultaneously, an internal polling sequence de-
abled or disabled by setting or clearing a bit in Special termines which request is serviced. Thus within each
Function Register IE (Figure 22). IE contains also a priority level there is a second priority structure deter-
global disable bit, EA, which disables all interrupts at mined by the polling sequence, as follows:
once.
Source Priority Within Level
Note in Figure 22 that bit position IE.6 is unimple- 1. lEO (highest)
mented. In the 8051s, bit position IE.5 is also unimple- 2. TFO
mented. User software should not write Is to these bit 3. IE1
positions, since they may be used in future MCS-51 4. TF1
products. 5. RI +TI
6. TF2 + EXF2 (lowest)
Priority Level Structure
Note that the "priority within level" structure is only
Each interrupt source can also be individually pro- used to resolve simultaneous requests of the same priori-
grammed to one of two priority levels by setting or ty level.
clearing a bit in Special Function Register IP (Figure
23). A low-priority interrupt can itself be interrupted The IP register contains a number of unimplemented
by a high-priority interrupt, but not by another low-pri- bits. IP.7 and IP.6 are vacant in the 8052s, and in the
ority interrupt. A high-priority interrupt can't be inter- 8051s these and IP.5 are vacant. User software should
rupted by any other interrupt source. not write Is to these bit positions, since they may be
used in future MCS-51 products.
(MSB) (LSB)
1-1-1~1~lml~I~I~1 How Interrupts Are Handled
Priority bit ~ 1 assigns high priority. The interrupt flags are sampled at S5P2 of every ma-
Priority bit ~ 0 assigns low priority.
chine cycle. The samples are polled during the follow-
Symbol PosItIon Function ing machine cycle. The 8052's Timer 2 interrupt cycle
IP.7 reserved is different, as described in the Response Time Section.
IP.6 reserved
If one of the flags was in a set condition at S5P2 of the
preceding cycle, the polling cycle will find it and the
PT2 IP.5 Timer 2 interrupt priority bit.
interrupt system will generate an LCALL to the appro-
PS IP.4 Serial Pori interrupt priority bit. priate service routine, provided this hardware-generat-
PTI IP.3 Timer 1 inlerrupt priority bit. ed LCALL is not blocked by any of the following con-
PXl IP.2 External interrupt 1 priority bit. ditions:
PTO IP.l Timer 0 interrupt priority bit 1. An interrupt of equal or higher priority level is al-
PXO IP.O External interrupt 0 priority bit.
ready in progress.
User software should never write 1s to unimplemented bits, since 2. The current (polling) cycle is not the final cycle in
they may be used in future MCS-51 products. the execution of the instruction in progress.
3. The instruction in progress is RETI or any write to
Figure 23. IP: Interrupt Priority Register the IE or IP registers.
If two requests of different priority levels are received Any of these three conditions will block the generation
simultaneously, the request of higher priority level is of the LCALL to the interrupt service routine. Condi-
serviced. If requests of the same priority level are re- tion 2 ensures that the instruction in progress will be
···• .. ··_--C1--.00+I...o - - - C 2 - -...+1---C3 I • C4--....-fI...- - C S - _ · · · · ·
ISSP21 56
········~''\----J..----=;11l-1----'----'1U:t-----'-----
INTERRUPT
~tINTERRUPT INTERRUPTS
ARE POLLED
LONG CALL TO
INTERRUPT
INTERRUPT ROUTINE
VECTOR ADDRESS
GOES LATCHED
ACTIVE
270252-20
This is the fastest possible response when C2 is the final cycle of an instruction other than RETI or an access to IE or IP.
Figure 24. Interrupt Response Timing Diagram
7-25
intJ HARDWARE D.ESCRIPTION OF THE 8051, 8052 AND 80C51
completed before vectoring to any service routine. Con- External Interrupts
dition 3 ensures that if the instruction in progress is
RET! or any access to IE or IP, then at least one more The external sources can be programmed to be level'ac-
instruction will be executed before any interrupt is vec- tivated or transitioncactivated by setting or clearing bit
tored to. ITI or ITO in Register TCON. If ITx = 0, external
interrupt x is triggered by a detected low at the INTx
The polling cycle is repeated with each machine cycle, . pin. If ITx = 1, external interrupt x is edge-triggered.
and the values polled are the values that were present at In this mode if successive samples of the INTx pin
S5P2 of the previous machine cycle. Note then that if show a high in one cycle and a low in the next cycle,
an interrupt flag is active but not being responded to for interrupt request flag lEx in TCON is set. Flag bit lEx
one of the above conditions, and is not still active when then requests the interrupt.
the blocking condition is removed, the denied interrupt
will not be serviced. In other worcis, the fact that the Since the external interrupt pins are sampled once each
interrupt flag was once active but not serviced is not machine cycle, an input high or low should hold for at
remembered. Every polling cycle is new. least 12 oscillator periods to ensure sampling. If the
external interrupt is transition-activated, the external
The polling cycle/LC~LL sequence is illustrated in source has to hold the request pin high for at least one
Figure 24. machine cycle, and then hold it low for at least one
machine cycle to ensure that the transition is seen so
Note that if an interrupt of higher priority level goes that interrupt request flag lEx will be set. lEx will be
active prior to S5P2 of the machine cycle labeled C3 in automatically cleared by the CPU when the service
Figure 24, then in accordance with the above rules it routine is called.
will be vectored to during C5 an,d_C6, without any in-
struction of the lower priority routine having been exe- If the external interrupt is level-activated, the external
cuted. source has to hold the request active until the requested
interrupt is actually generated. Then it has to deacti-
Thus the processor acknowledges an interrupt request vate the request before the interrupt service routine is
by executing a hardware-generated LCALL to the ap- completed, or else another interrupt will be generated.
propriate servicing routine. In some cases it also clears
the flag that generated the interrupt, and in other cases
it doesn't. It never clears the Serial Port or Timer 2 Response Time
flags. This has to be done in the user's software. It
The INTO and INTI levels are inverted and latched
clears an external interrupt flag (lEO or IE 1) only if it
into the interrupt flags lEO and IE 1 at S5P2 of every
was transition-activated. The hardware-generated
machine cycle. Similarly, the Timer 2 flag EXF2 and
LCALL pushes the contents of the Program Counter
the Serial Port flags RI and T! are set at S5P2. The
onto the stack (but it does not save the PSW) and re-
values are not actually polled by the circuitry until the
loads the PC with an address that depends on the
next machine cycle.
source of the interrupt being vectored to, as shown be-
low. The Timer 0 and Timer 1 flags, TFO and TF1, are set at
Vector S5P2 of the cycle in which the timers overflow. The
Source
Address values are then polled by the circuitry in the next cycle.
lEO 0003H However, the Timer 2 flag TF2 is set at S2P2 and is
TFO OOOBH polled in the same cycle in which the timer overflows.
IE1 0013H
If a request is active and conditions are right for it to be
TF1 001BH
acknowledged, a hardware subroutine call to the re-
AI + TI 0023H
quested service routine will be the next instruction to be
TF2 + EXF2 002BH executed. The call itself takes two cycles. Thus, a mini-
mum of three complete machine cycles elapse between
Execution proceeds from that location until the RET! activation of an external interrupt request and the be-
instruction is encountered. The RETI instruction'in- ginning of execution of the first instruction of the serv-
forms the processor that this interrupt routine is no ice routine. Figure 24 shows interrupt response timings.
longer in progress, then pops the top two bytes from the
stack and reloads the Program Counter. Execution of A longer response time would result if the request is
the interrupted program continues from where it left blocked by one of the 3 previously listed conditions. If
off. an interrupt of equal or higher priority level is already
in progress, the additional wait time obviously depends
Note that it simple RET instruction would also have on the nature of the other iiIterrupt's service routine. If
returned execution to the interrupted program, but it the instruction in progress is not in its final cycle, the
would have left the interrupt control system thinking additional wait time cannot be more than 3 cycles, since
an interrupt was still in progress. the longest instructions (MUL and DIV) are only 4
7-26
intJ HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
cycles long, and if the instruction in progress is RETI RESET
or an access to IE or IP, the additional wait time can-
not be more than 5 cycles. (a maximum of one more The reset input is the RST pin, which is the input to a
cycle to complete the instruction in progress, plus 4 Schmitt Trigger.
cycles to complete the next instruction if the instruction
is MUL or DIY). A reset is accomplished by holding the RST pin high
for at least two machine cycles (24 oscillator periods),
Thus, in a single-interrupt system, the response time is while the oscillator is running. The CPU responds by
always more than 3 cycles and less than 9 cycles. generating an internal reset, with the timing. shown in
Figure 25.
SINGLE-STEP OPERATION The external reset signal is asynchronous to the internal
clock. The RST pin is s;unpled during State 5 Phase 2
The 8051. interrupt structure allows single-step execu- of every machine cycle. The port pins will maintain
tion with very little software overhead. As previously their current activities for 19 oscillator periods after a
noted, an interrupt request will not be responded to logic 1 has been sampled at the RST pin; that is, for 19
while an interrupt of equal priority level is still in prog- to 31 oscillator periods after the external reset signal
ress, nor will it be responded to after RETI until at has been applied to the RST pin. .
least one other instruction has been executed. Thus,
once an interrupt routine has been entered, it cannot be While the RST pin is high, ALE and PSEN are weakly
re-entered until at least one instructiori of the interrupt- pulled high. After RST is pulled low, it will take 1 to 2
ed program is executed. One way to use this feature for machine cycles for ALE and PSEN to start clocking.
single-stop operation is to program one of the. external For this reason, other devices can not be synchronized
interrupts (say, INTO) to be level-activated. The service to the internal timiitgs of the 8051.
routine for the interrupt will terminate with the follow-
ing code: Driving the ALE and PSEN pins to 0 while reset is
active could cause the device to go into ail-indetermi-
JNB P3.2,$ ;Wait Here Till INTO Goes High
nate state.
JB P3.2,$ ;Now Wait Here Till it Goes Low
RETI :Go Back and Execute One Instruction The internal reset algorithm writes Os to all the SFRs
except the port latches, the Stack Pointer, and SBUF.
Now.ifthe INTO pin, which is also the P3.2 pin, is held The port latches are initialized to FFH, the Stack
normally low, the CPU will go right into the External Pointer to 07H, and SBUF is indeterminate. Table 3
Interrupt 0 routine and stay there until INTO is pulsed lists the SFRs and their reset values.
(from low to high' to low). Then it will execute RET!,
go back to the task program, execute one instruction, The internal R:AM is not affected by reset. On power
and immediately re-enter the External Interrupt 0 rou- up the RAM content is indeterminate.
tine to await the next pulsing of P3.2. One step of the
task program is executed each time P3.2 is pulsed.
r--12 OSC. PERIODS ~
I S5 I S6 I SI I S2 I S3 I S4 I S5 I S6 I SI I S2 I S3 I S4 I S5 I S6 I SI I S2 I S3 I S4 I
RST: / /
'-oJ
/ / / /
.
/ /
.
/ / f:
L.-J C INTERNAL RESET SIGNAL
SAMPLE RST SAMPLE RST
I I
ALE: I"-i'~_. . n. __. .
PSEN:
po:
I
. - 1 1 OSC. PERIODS - -.....- - - - - 1 9 OSC. PERIODS -----~.I
270252-33
Figure 25. Reset Timing
7-27
infef HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
Table 3. Reset Values of the SFRs POWER-ON RESET
SFRName Reset Value
Fot HMOS devices when Vee is turned on an automat-
PC OOOOH ic reset can be obtained by connecting the RST pin to
ACC OOH Vee through a 10 JLF capacitor and to VSS through an
B 8.2 K!l resistor (Figure 26). The CHMOS deviceS do
OOH
not require this resistor although its presence does no
PSW OOH harm.·In fact, for CHMOS devices the external resistor
SP 07H can be removed because they have an internal pulldown
DPTR OOOOH oli the RST pin. The capacitor value could then be re-
duced to I JLF.
PO-P3 FFH
IP (8051) XXXOOOOOB When power is turned on, the circuit holds the RST pin
IP (8052) high for an amount of time that depends on the capaci-
XXOOOOOOB
tor value and the rate at which it charges. To ensure a
IE (8051) OXXOOOOOB· valid reset the RST pin must be held high long enough
IE (8052) OXOOOOOOB to allow the oscillator to start up plus two machine
cycles.
TMOD OOH
TCON OOH On power up, Vee should rise within approximately
THO OOH ten milliseconds. The oscillator start-up time will de-
TLO pend on the oscillator frequency. For a 10 MHz crystal,
OOH
the start-up time is typically 1 ms. For a 1 MHz crystal,
TH1 OOH the start-up time is typically 10 ms.
TL1 OOH
TH2 (8052) With the given circuit, reducing Vee quickly to 0 caus-
OOH
es the RST pin voltage to momentarily fall below OV.
TL2 (8052) OOH However, this voltage is internally limited and will not
RCAP2H (8052) OOH harm the device.
RCAP2L (8052) OOH
NOTE:
SCON OOH The port pins will be in a random state until
SBUF Indeterminate the oscillator has started and the internal reset
PCON (HMOS) OXXXXXXXB algorithm has written Is to them.
PCON (CHMOS) OXXXOOOOB Powering up the device without a valid reset could
cause the CPU to start executing instructions from an
indeterminate location. This is because the SFRs, spe-
cifically the Program Counter, may not get properly'
vee
initialized.
+ POWER-5AVING MODES OF
10.'='=
vee - OPERATION
For applications where power consumption is critical
8051 the CHMOS version provides power reduced modes of
operation as a standard feature. The power down mode
in HMOS devices is no longer a standard feature and is,
RST being phased out.
8.2Kil
CHMOS Power Reduction Modes
YSS
CHMOS versions have two power-reducing modes,
~
Idle and Power Down. The input through which back-
270252-21 up power is supplied during these operations is VCC;
Figure 27 shows the internal circuitry which imple-
Figure 26. Power on Reset Circuit
ments these features. In the Idle mode (lDL = 1), the
oscillator continues to run and the Interrupt, Serial
Port, and Timer blocks continue to be clocked, but the
7-28
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
clock signal is gated off to the CPU. In Power Down
(MSB) (LSB)
(PD = 1), the oscillator is frozen, The Idle and Power
Down modes are activated by setting bits in Special SMOD GF1 GFO PD IDL
Function Register PCON. The address of this register
Symbol Position Name and Function
is 87H. Figure 26 details its contents.
SMOD PCON.7 Double Baud rate bit. When set to a 1
and Timer 1 is used to generate baud
In, the HMOS devices the PCON register only contains
rate, and the Serial Port is used in
SMOD. The other four bits are implemented only in modes 1, 2, or 3.
the CHMOS devices. User software should never write
PCON.6 (Reserved)
Is to unimplemented bits, since they may be used in
future MCS-5l products. PCON.5 (Reserved)
PCONA (Reserved)
GF1 PCON.3 General·purpose flag bit.
IDLE MODE
GFO PCON.2 General-purpose flag bit.
An instruction that sets PCON.O causes that to be the PD PCON.1 Power Down bit. Setting this bit
last instruction executed before going into the Idle activates power down operation.
mode. In the Idle mode, the internal clock signal is IDL PCON.O Idle mode bit. Setting this bit activates
gated off to the CPU, but not to the Interrupt, Timer, idle mode operation.
and Serial Port functions. The CPU status is preserved
If 1s are written to PD and IDL at the same time, PD takes
in its entirety: the Stack Pointer, Program Counter, precedence. The reset value of PCON is (OXXXOOOO).
Program Status Word, Accumulator, and all other reg- In the HMOS devices the PCON register only contains SMOD.
isters maintain their data during Idle. The port pins The other four bits are implemented only in the CHMOS devices.
User software should never write 1s to unimplemented bits, since
hold the logical states they had at the time Idle was
they may be used in future MCS-51 products.
activated. ALE and PSEN hold at logic high levels.
There are two ways to terminate the Idle. Activation of Figure 28. PCON: Power Control Register
any enabled interrupt will cause PCON.O to be cleared
by hardware, terminating the Idle mode. The interrupt The flag bits GFO and GFl can be used to give an
will be serviced, and following RETI the next instruc- indication if an interrupt occurred during normal oper-
tion to be executed will be the one following the in- ation or during an Idle. For example, an instruction
struction that put the device into Idle. that activates Idle can also set one or both flag bits.
When Idle is terminated by an interrupt, the interrupt
service routine can examine the flag bits.
~~
The other way of terminating the Idle mode is with a
hardware reset. Since the clock oscillator is still run-
ning, the hardware reset needs to be held active for only
XTAL 2 = XTAL 1 two machine cycles (24 oscillator periods) to complete
the reset.
INTERRUPT, The signal at the RST pin clears the IDL bit directly
I-_-C>SERIAL PORT, and asynchronously. At this time the CPU resumes
TIMER BLOCKS
program execution from where it left off; that is, at the
CPU instruction following the one that invoked the Idle
Mode. As shown in Figure 25, two or three machine
cycles of program execution may take place before the
internal reset algorithm takes control. On-chip hard-
270252-22
ware inhibits access to the internal RAM during this
time, but access to the port pins is not inhibited. To
Figure 27. Idle and Power Down Hardware
eliminate the possibility of unexpected outputs at the
port pins, the instruction following the one that invokes
Idle should not be one that writes to a port pin or to
external Data RAM.
POWER DOWN MODE
An instruction that sets PCON.l causes that to be the
last instruction executed before going into the Power
Down mode. In the Power Down mode, the on-chip
oscillator is stopped. With the clock frozen, all func-
7-29
intJ HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
Table 4. EPROM Versions of the 8051 and 8052
Device EPROM EPROM Ckt Time Required to
VPP
Name Version Bytes Type Program Entire Array
8051 (8751) 4K HMOS 21.0V 4 minutes
8051AH 8751H 4K HMOS 21.0V 4 minutes
80C51BH 87C51 4K CHMOS 12.75V 13 seconds
8052AH 8752BH 8K HMOS 12.75V 26 seconds
tions are stopped, but the on-chip RAM and Special Program Memory Locks
Function Registers are held. The port pins output the
values held by their respective SFRs. ALE and PSEN In some microcontroller applications it is desirable that
output lows. the Program Memory be secure from software piracy.
Intel has responded to this need by implementing a
The only exit from Power Down for the 80C51 is a Program Memory locking scheme in some of the MCS-
hardware reset. Reset redefines all the SFRs, but does 51 devices. While it is impossible for anyone to guaran-
not change the on-chip RAM. tee absolute security against all levels of technological
sophistication, the Program Memory locks in the MCS-
In the Power Down mode of operation, VCC can be 51 devices will present a formidable barrier against ille-
reduced to as low as 2V. Care must be taken, however, gal readout of protected software.
to ensure that VCC is not reduced before the Power
Down mode is invoked, and that VCC is restored to its
normal operating level, before the Power Down mode is One Lock Bit Scheme on 8751H
terminated. The reset that termin.ates Power Down also
The 8751H contains a lock bit which, once pro-
frees the oscillator. The reset should not be activated
grammed, denies electrical access by any external
before VCC is restored to its normal operating level,
means to the on-chip Program Memory. The effect of
and must be held active long enough to allow the oscil-
this lock bit is that while it is programmed the internal
lator to restart and stabilize (normally less than 10
Program Memory can not be read out, the device can
msec).
not be further programmed, ,and it can not execute ex-
ternal Program Memory. Erasing the EPROM array
deactivates the lock bit and restores the device's full
EPROM VERSIONS functionality. It can then be re-programmed.
The EPROM versions of these devices are listed in Ta-
ble 4. The 8751H programs at VPP = 21V using one The procedure for programming the lock bit is detailed
50 msec PROG pulse per byte programmed. This re- in the 8751H data sheet.
sults in a total programming time (4K bytes) of appro x-
imately 4 minutes. Two-Level Program Memory Lock Scheme
The 8752BH and 87C51 use the faster "Quick-Pulse" The 87C51 and 8752BH contain two Program Memory
programming™ algorithm. These devices program at locking schemes: Encrypted Verify and Lock Bits.
VPP = 12.75V using a series (If twenty-five 100 JLs
PROG pulses per byte programmed. This results in a Encrypted Verify: These devices implement a 32-byte
total programming time of approximately 26 seconds EPROM array that can be programmed by the custom-
for the 8752BH (8K bytes) and 13 seconds for the er, and which can then be used to encrypt the program
87C51 (4K bytes). code bytes during EPROM verification. The EPROM
verification procedure is performed as usual, except
Detailed procedures for programming and verifying that each code byte comes out X-NORed with one of
each device are given in the data sheets. the 32 key bytes. The key bytes are gone through in
sequence. Therefore, to read the ROM code, one has to
know the 32 key bytes in their proper sequence.
EXPOSURE TO LIGHT
It is good practice to cover the EPROM window with Unprogrammed bytes have the value FFH. Therefore,
an opaque label when the device is in operation. This is if the Encryption Array is left unprogrammed all the
not so much to protect the EPROM array from inad- key bytes have the value FFH. Sinc€; any code byte
vertent erasure, but to protect the RAM and other on- X-NORed with FFH leaves the code byte unchanged,
chip logic. Allowing light to impinge on the silicon die leaving the Encryption Array unprogrammed in effect
while the device is operating can cause logical malfunc- bypasses the encryption feature.
tion.
7-30
infef HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
Lock Bits: Also on the chip are two Lock Bits which ONCE Mode
can be left unprogrammed (U) or programmed (P) to
obtain the following features' The ONCE ("on-circuit emulation") mode facilitates
Bit2 Bit 1 Additional Features testing and debugging of systems using the device with-
out the device having to be removed from the circuit.
U U None The ONCE mode is invoked by:
U P • Externally fetched code can not 1. Pull ALE low while the device is in reset and PSEN
access internal Program Memory. is high;
• Further programming disabled. 2. Hold ALE low as RST is deactivated.
P U (Reserved for Future definition.) While the device is in ONCE mode, the Port 0 pins go
P P • Externally fetched code can not into a float state, and the other port pins and ALE and
access internal Program Memory. PSEN are weakly pulled high. The oscillator circuit
remains active. While the device is in this mode, "an
• Further programming disabled.
emulator or test CPU can be used to drive the circuit.
• Program verification is disabled. Normal operation is restored after a normal reset is
applied.
When Lock Bit I is programmed, the logic level at the
EA pin is sampled and latched during reset. If the de-
vice is powered up without a reset, the latch initializes THE ON-CHIP OSCILLATORS
to a random value, and holds that value until reset is
activated. It is necessary that the latched value of EA
be in agreement with the current logic level at that pin HMOS Versions
in order for the device to function properly.
The on-chip oscillator circuitry for the HMOS
(HMOS-I and HMOS-II) members of the MCS-Sl fam-
ROM Protection ily is a single stage linear inverter (Figure 29), intended
for use as a crystal-controlled, positive reactance oscil-
The 80S IAHP and 80CS IBHP are ROM Protected lator (Figure 30). In this application the crystal is oper-
versions of the 80SlAH and 80CSIBH, respectively. To ated in its fundamental response mode as an inductive
incorporate this Protection Feature, program verifica- reactance in parallel resonance with capacitance exter-
tion has been disabled and external memory accesses nal to the crystal.
have been limited to 4K. Refer to the data sheets on
these parts for more information.
XTALI
?
SUBST.
270252-23
"Figure 29. On-Chip Oscillator Circuitry in the HMOS Versions of the MCS®-51 Family
7-31
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
consulted for recommendations on the values of these
capacitors.
TO INTERNAL
nMINGCKTS In general, crystals used with these devices typically
have the following specifications:
VSS
ESR (Equivalent ~eries Resistance) see Figure 31
Co (Shunt Capacitance) 7.0pFmax.
._--1'-- QUARTZ CRYSTAL CL (Load Capacitance) 30pF ±3 pF
OR CERAMIC RESONATOR
Drive Level ImW
Frequency, tolerance and temperature range are deter-
C, mined by the system requirements.
270252-24
A more in-depth discussion of crystal specifications, ceo
Figure 30. Using the HMOS On-Chip Oscillator ramie resonators, and the selection of values for CI and
C2 can be found in Application Note AP-155, "Oscilla-
The crystal specifications and capacitance values (C 1 tors for Microcontrollers," which is included in the
and C2 in Figure 30) are not critical. 30 pF can be used Embedded Control Applications Handbook.
in these positions at any frequency with good quality
crystals. A ceramic resonator can be used in place of To drive the HMOS parts with an external clock
the crystal in cost·sensitive applications. When ace· source, apply the external clock signal to XTAL2, and
ramie resonator is used, CI and C2 are normally select· ground XTALl, as shown in Figure 32. A pullup resis-
ed to be of somewhat higher values, typically, 47 pF. tor may be used (to increase noise margin), but is op-
The manufacturer of the ceramic resonator should be tional ifVOH of the driving gate exceeds the VIH MIN
specification of XTAL2.
Vcc
500 8051
~ 400 EXTERNAL
:z:
o
.5 300
OSCILLATOR
SIGNAL
t
~-+----I XTAL2
XTALI
'"
12 200 TTL
GATE VSS
100 WITH
TOTEM-POLE
OUTPUT
4 8 12 16 270252-25
CRYSTAL FREQUENCY In MHz Figure 32. Driving the HMOS MCS®-S1
270252-34
Parts with an External Clock.Source
Figure 31. ESR vs Frequency
7-32
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
CHMOS VERSIONS The feedback resistor Rr in Figure 33 consists of paral-
leled n- and p- channel FETs controlled by the PD bit,
The on-chip oscillator circuitry for the 80C51BH, such that Rr is opened when PD = 1. The diodes DI
shown in Figure 33, consists of a single stage linear and D2, which act as clamps to VCC and VSS, are
inverter intended for use as a crystal-controlled, posi- parasitic to the Rr FETs.
tive reactance oscillator in the same maImer '.as the
HMOS parts. However, there are some important dif- The oscillator can be used with the same external com-
ferences. ponents as the HMOS versions, as shown in Figure 34.
Typically, CI = C2 = 30 pF when the feedback ele-
One difference is that the 80C51BH is able to tum off ment is a quartz crystal, and CI = C2 = 47 pF when a
its oscillator under software control (by writing a I to ceramic resonator is used.
the PD bit in PCON). Another difference is that in the
80C5lBH the internal clocking circuitry is driven by To drive the CHMOS parts with an external clock
the signal at XTALI, whereas in the HMOS versions it source, apply the external clock signal to XTALI, and
is by the signal at XTAL2. leave XTAL2 float, as shown in Figure 35.
VCC
TO INTERNAL
TIMING CKTS
01
4000 RI
XTAL1 XTAL2
02
r PO
270252-26
Figure 33. On-Chip OSCillator Circuitry in the CHMOS Versions of the MCS®-51 Family
7-33
HARDWARE DESCRIPTION OF rHE 8051, 8052 AND 80C51
Vee
TO INTERNAL
nMINGCKTS
VSS
XTAU------
1OC51
~-,.--QUARTZ CRYSTAL
OR CERAMIC
RESONATOR
270252-27
Figure.34_ Using the CHMOS On-Chip Oscillator
8OC51
INTERNAL TIMING
NC XTAU Figures 36 through 39 show when the various strobe
and port signals are clocked internally. The figures do
~"""'---i not show rise and fall times of the signals, nor do they
t
EXTERNAL XTALI
OSCILLATOR
SIGNAL show propagation delays between the XTAL signal and .
events at other pins.
CMOSGA11!
Rise and fall times are dependent on the external load-
270252-28 ing that each pin must drive. They are often taken to be
something in the neighborhood of 10 nsec, measured
Figure 35. Driving the CHMOS MCS®-51
between 0.8V and 2.0V.
Parts with an External Clock Source
Propagation delays are different for different pins. For
The reas~n for this change from the way the HMOS a given pin they vary with pin loading, temperature,
part is driven can be seen by comparing Figures 29 and VCC, and manufacturing lot. If the XTAL waveform is
33. In the HMOS devices the internal timing circuits taken as the timing reference, prop delays may vary
are driven by the signal at XTAL2. In the CHMOS from 25 to 125 nsec.
devices the internal timing circuits are driven by the
signal at XTALI. The AC Timings section of the data sheets do not refer-
.ence any timing to the XTAL waveform. Rather, they
relate the critical edges of control and input signals to
each other. The timings published in the data sheets
include the effects of propagation delays under the
specified test conditions.
7-34
inter HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
I ~I~ ~I~ ~I~ ~I~ ~I~
I
STATE '1 STATE 21 STATE 31 STATE 41 STATE 51 STATE 61 STATE' STATE 21
~I~ ~I~ ~I~
XTAL:
ALE:
PSEN: -.-J
--l
DATA
k-SAMPLED
L
PO:
P2:
I PCH OUT PCH OUT PCH OUT
270252-29
Figure 36. External Program Memory Fetches
I ~I~ ~I~
I
STATE 41 STATE 51 STATE 61 STATE' STATE 21 STATE' 31 STATE 41 STATE' 51
~I~ ~I~ ~I~ ~I~ ~I~ ~I~
XTAL:
ALE:
RD: PCL OUT IF
PROGRAM MEMORY
OATA SAMPLED
FLOAT
PO:
PCH OR PCH OR
P2: DPH OR P2 SFR OUT
P2 SFR P2 SFR
270252-30
Figure 37. External Data Memory Read Cycle
7-35
infef HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
I STATE 41 STATE 51 STATE
~I~ ~I~ ~I~
81 STATE 1
~I~
I
STATE 21 STATE 31 STATE 41 STATE
~I~ ~I~ ~I~ ~I~
51
XTAL:
ALE:
WR: PCL OUT IF
f_~·_M
IS EXTERNAL
-JUt ~
DPLORRI
PO: DATA OUT
OUT
P2 PCH OR PCH OR
DPH OR P2 SFR OUT
~SFR ~SFA
270252-31
Figure 38. External Data Memory Write Cycle
I
STATE 4\ STATE 5\ STATE
~I~ ~I~ ~I~
81 STATE 1 1STATE 21 STATE 31 STATE 41 STATE 5\
~I~ ~I~ ~I~ ~I~ ~I~
XTAL:
~ PO, P1, P2, P3
~
'P1.P2'P3
INPUTS SAMPLED:
RST =::rl.-AST
MOV POAT, SAC: OLD DATA NEW DATA
SERIAL PORT
SHIFT CLOCK
(MODE 0)
---I I-- RXD PIN SAMPLED AXD SAMPLED -+I f4-
270252-32
Figure 39. Port Operation
7-36
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
ADDITIONAL REFERENCES
The following application notes and articles are found in the Embedded Control Applications handbook.
(Order Number: 270535)
1. AP-125 "Designing Microcontroller Systems for Electrically Noisy Environments".
2. AP-155 "Oscillators for Microcontrollers".
3. AP-252 "Designing with the 80C5IBH".
4. AR-409 "Increased Functions in Chip Result in Lighter, Less Costly Portable Computer".
5. AR-517 "Using the 8051 Microcontroller with Resonant Transducers".
7-37
8XC52/54/58 HARDWARE DESCRIPTION
INTRODUCTION PIN DESCRIPTION
The 8XC52/54/58 is a highly integrated 8-bit micro- The 8XC5X pin-out is the same as the 80C51.The only
controller based on the MCS®-51 architecture. The key difference is the alternate function of pins P 1.0 and
features are an enhanced serial port for multi-processor Pl.l. P1.0 is the external clock input for Timer 2. Pl.l
communications and an up/down timer/counter. As is the Reload/Capture/Direction Control for Timer 2.
this product is CHMOS, it has two software selectable
reduced power modes: Idle Mode and Power Down
Mode. Being a member of the MCS-51 family, the DATA MEMORY
8XC52/54/58 is optimized for control applications.
The 8XC5X implements 256 bytes of on-chip RAM.
This document presents a comprehensive description of The upper 128 bytes occupy a parallel address space to
the on-chip hardware features of the 8XC52/54/58 as the Special Function Registers. That means they have
they differ from the 80C5IBH. It begins by describing the same addresses, but they are physically separate
how the I/O functions are different and then discusses from SFR space.
each of the peripherals as follows:
When an instruction accesses an internal location above
• 256 Bytes On-Chip RAM
address 7FH, the CPU knows whether the access is to
• Special Function Registers (SFR) the upper 128 bytes of RAM or the SFR space by the
• Timer 2 addressing mode used in the instruction. Instructions
that use direct addressing access SFR space. For exam-
Capture Timer/Counter
ple,
Up/Down Timer/Counter
Baud Rate Generator MOV OAOH, #data (Direct Addressing)
• Full-Duplex Programmable Serial Interface with
accesses the SFR at location OAOH (which is P2). In-
- F~aming Error' Detection structions that use indirect addressing access the upper
- Automatic Address Recognition 128 bytes of RAM. For example,
• 6 Interrupt Sources MOV @RO, #data (Indirect Addressing)
• Enhanced Power Down Mode
• Power Off Flag where RO contains OAOH, accesses the data byte at ad-
dress OAOH, rather than P2 (whose address is OAOH).
• ONCE Mode Note that stack operations are examples of indirect ad-
dressing, so the upper- 128 bytes of data RAM are avail-
The 8XC52/54/58 uses the standard 8051 instruction
able as stack space.
set and is pin-for-pin compatible with the existing
MCS-51 family of products. Table 1 summarizes the
product names and memory differences of the various
8XC52/54/58 products currently available. Through- SPECIAL FUNCTION REGISTERS
out this document, the products will generally be re- A map of the on-chip memory area called the Special
ferred to as the 8XC5X. Function Register (SFR) space is shown in Table 2.
Table 1. 8XC52154/58 Microcontrollers Note that not all of the addresses are occupied. Unoc-
ROM EPROM ROMless ROM/EPROM RAM cupied addresses may not be implemented on the chip.
Device Version Version Bytes Bytes Read accesses to these addresses will in general return
random data, and write accesses will have an indetermi-
80C52 - 80C32 8K 256 nate effect.
80C54 87C54 80C32 16K 256
80C58 87C58 80C32 32K 256 User software should not write Is to these unlisted lo-
cations, since they may be used in future MCS-51 prod-
ucts to invoke new features. In that case the reset or
For a description of the features that are the same as
inactive values of the new bits will always be O.
the 80C51, the reader should refer to the MCS-51 Ar-
chitectural Overview, MCS-51 Programmers Guide/
Instruction Set, and the Hardware Description of the
80C51 in the 8-Bit Embedded Controller Handbook
(Order #270645).
7-38 Order Number: 270783-002
inter 8XC52/54/58 HARDWARE DESCRIPTION
Table 2. 8XC5X SFR Map and Reset Values
OF8H OFFH
B
OFOH OF7H
00000000
OE8H OEFH
ACC
OEOH OE7H
00000000
OD8H ODFH
PSW
ODOH OD7H
00000000
T2CON T2MOD RCAP2L RCAP2H TL2 TH2
OC8H OCFH
00000000 XXXXXXXO 00000000 00000000 00000000 00000000
OCOH OC7H
IP SADEN
OB8H OBFH
XOOOOOOO 00000000
P3 'IPH
OBOH OB7H
11111111 XOOOOOOO
IE SADDR
OA8H OAFH
00000000 00000000
P2
OAOH OA7H
11111111
SCON SBUF
98H 9FH
00000000 XXXXXXXX
P1
90H 97H
11111111
TCON TMOD TLO TL1 THO TH1
88H 8FH
00900000 00000000 00000000 00000000 00000000 00000000
PO SP DPL DPH PCON
80H 87H
11111111 00000111 00000000 00000000 00000000
*SXC54/5S only
Timer Registers-Control and status bits are contained Interrupt Registers-The individual interrupt enable
in registers T2CON and T2MOD for Timer 2. The reg- bits are in the IE register. Two priorities can be set for
ister pair (RCAP2H, RCAP2L) are the Capture/Re- each of the 6 interrupt sources in the IP register. The
load registers for Timer 2 in 16-bit capture mode or 16- 8XC54 and 8XC58 allow four priorities.
bit auto-reload mode.
Serial Port Registers-Registers SADDR and SA- TIMER 2
DEN are used to define the Given and the Broadcast
addresses for the Automatic Address Recognition fea- Timer 2 is a 16-bit Timer/Counter which can operate
ture. either as a timer or an event counter. This is selectable
by bit C/T2 in the SFR T2CON (Table 3). It has three
7-39
8XC52/54/58 HARDWARE DESCRIPTION
operating modes: capture, auto-reload (up or· down tetnal input pin, T2. In this function, the external input
counting), and baud rate generator. The modes are se- is sampled during S5P2 of every machine cycle. When
lected by bits in T2CON as shown in Table 4. the samples show a high in one cycle and a low in the
next cycle, the count is incremented. The new count
Timer 2 consists of two 8-bit registers; TH2 and TL2. value appears in the register during S3Pl of the cycle
In the Timer function, the TL2 register is incremented following the one in which the transition was detected.
every machine cycle. Thus one can think of it as count- Since it takes 2 machine cycles (24 oscillator periods) to
ing machine cycles. Since a machine cycle consists of 12 recognize a I-to-O transition, the maximum count rate
oscillator periods, the count rate is '112 of the oscillator is '1.4 of the oscillator frequency. To ensure that a given
frequency. level is sampled at least once before it changes, it
should be held for at least one full machine cycle.
In the Counter function, the register is incremented in
response to a I-to-O transition at its corresponding ex-
Table 3. T2CON-Timer/Counter 2 Control Register
T2CON Address = OC8H Reset Value = 0000 OOOOB
Bit Addressable
Bit 7 6 5 4 3 2 o
Symbol Function
TF2 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2
will not be set when either RCLK = 1 or TCLK = 1.
EXF2 Timer 2 external flag set when either a capture or reload is caused by a negative
transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 =.1 will
cause the CPU to vector to the. Timer 2 interrupt routine. EXF2 must ·be cleared by
software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).
RCLK
I
Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses
for its receive clock in serial port Modes 1 and 3. RCLK = 0 causes Timer 1 overflow tQ
be used for the receive clock.
TCLK Transmit clOCk enable. When set, causes the serial port to use Timer 2 overflow pulses
for its transmit clock in serial port Modes 1 and 3. TCLK = 0 causes Timer 1 overflows
to be used for the transmit clock.
EXEN2 Timer 2 external enable. When set, allows a capture or reload to occur as a result of a
negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2
= 0 causes Timer 2 to ignore events at T2EX.
TR2 Start/Stop control for Timer 2. TR2 = 1 starts the timer.
C/T2 Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external
event counter (falling edge triggered).
CP/RL2 Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions
at T2EX if EXEN2 =1. CP/RL2 = 0 causes automatic reloads to occur when Timer 2
overflows or negative transitions occur at T2EX when EXEN2 = 1. When either RCLK
or TCLK = 1, this bit is ignored and the timer is !orced to auto-reload on Timer 2
overflow.
7-40
inter 8XC52/54/58 HARDWARE DESCRIPTION
Table 4. Timer 2 Operating Modes
RCLK + TCLK CP/RL2 TR2 MODE
0 0 1 16-Bit Auto-Reload
0 1 1 16-Bit Capture
1 X 1 Baud Rate Generator
X X 0 (Off)
CAPTURE MODE is invoked by a bit named DCEN (Down Counter En-
able) located in the SFR T2MOD (see Table 5). Upon
In the capture mode there are two options selected by reset the DCEN bit is set to 0 so that Timer 2 will
bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a default to count up. When DCEN is set, Timer 2 can
16-bit timer or counter which upon overflow sets bit count up or down depending on the value of the T2EX
TF2 in T2CON. This bit can then be used to generate pin.
an interrupt. If EXEN2 = I, Timer 2 still does the
above, but with the added feature that a I-to-O tran- Figure 2 shows Timer 2 automatically counting up
sition at external input T2EX causes the current value when DCEN = O. In this mode there are two options
in TH2 and TL2 to be captured into RCAP2H and selected by bit EXEN2 in T2CON. If EXEN2 = 0,
RCAP2L, respectively. In addition, the transition at Timer 2 counts up to OFFFFH and then sets the TF2
T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit upqn overflow. The overflow also causes the timer
bit, like TF2, can generate an interrupt. The capture registers to be reloaded with the 16-bit value in
mode is illustrated in Figure 1. RCAP2H and RCAP2L. The values in RCAP2H and
RCAP2L are preset by software. If EXEN2 = I, a
16-bit reload can be triggered either by an overflow or
AUTO~RELOAD (Up or Down Counter) by a l-to-O transition at external input T2EX. This
transition also sets the EXF2 bit. Both the TF2 and
Timer 2 can be programmed to count up or down when EXF2 bits can generate an interrupt if enabled.
configured in its 16-bit auto-reload mode. This feature
0-1 C/f2=1
T2 PIN
TRANSITION
DETECTION
T2EX PIN
270783-1
Figure 1. Timer 2 in Capture Mode
7-41
intJ 8XC52/54/58 HARDWARE DESCRIPTION
Table 5. T2MOD-Timer 2 Mode Control Register
T2MOD Address = OC9H Reset Value = XXXX XXXOB
Not Bit Addressable
DCEN
Bit 7 6 5 4 3 2 o
Symbol Function
Not implemented, reserved for future use.
DCEN When set, this bit allowsTirner 2 to be configured as an up/down counter.
·oJ ~.m~1 OVERFLOW
T2PIN
TIMER 2
INTERRUPT
TRANsmON
DETECTION
T2EX PIN
270783-2
Figure 2. Timer 2 Auto Reload Mode (DCEN = 0)
(DOWN COUNTING RELOAD VALUE)
TOGGLE
o-! C/f2=1
T2PIN
(UP COUNTING RELOAD VALUE) COUNT
DIRECTION
I=UP
O=DOWN
T2EX PIN
270783-3
Figure 3. Timer 2 Auto Reload Mode (DCEN = 1)
7-42
8XC52/54/58 HARDWARE DESCRIPTION
Setting the DCEN bit enables Timer 2 to count up or Timer 2 as a baud rate generator is shown in Figure 4.
down as shown in Figure 3. In this mode the T2EX pin This figure is valid only if RCLK or TCLK = 1 in
controls the direction of count. A logic 1 at T2EX T2CON. Note that a rollover in TH2 does not set TF2,
makes Timer 2 count up. The timer will overflow at and will not generate an interrupt. Note too, that if
OFFFFH and set the TF2 bit. This overflow also causes EXEN2 is set, a I-to-O transition in T2EX will set
the 16-bit value in RCAP2H and RCAP2L to be re- EXF2 but will not cause a reload from (RCAP2H,
loaded into the timer registers, TH2 and TL2, respec- RCAP2L) to (TH2, TL2). Thus when Timer 2 is in use
tively. as a baud rate generator, T2EX can be used as an extra
external interrupt, if desired.
A logic 0 at T2EX makes Timer 2 count down. Now
the timer underflows when TH2 and TL2 equal the It should be noted that when Timer 2 is running (TR2
values stored in RCAP2H and RCAP2L. The under- = 1) in "timer" function in the baud rate generator
flow sets the TF2 bit and 'causes OFFFFH to be reload- mode, one should not try to read or write TH2 or TL2.
ed into the tiiner. registers. Under these conditions the Timer is being incremented
every state time, and the results of a read or write may
The EXF2 bit toggles whenever Timer 2 overflows or lIot be accurate. The RCAP2 registers may be read, but
underflows. This bit can be used as a 17th bit of resolu- shouldn't be written to, because a write might overlap a
tion if desired. In this operating mode, EXF2 does not reload and cause write and/or reload errors. The timer
flag an interrupt. should be turned off (clear TR2) before accessing the
Timer 2 or RCAP2 registers.
BAUD RATE GENERATOR
UART
Timer 2 is selected as the baud rate generator by setting
TCLK and/or RCLK in T2CON (Table 3). Note that The UART in the 8XC5X operates identically to the
the baud rates for transmit and receive can be different. UART in the 80C51 except for the following enhance-
This is accomplished by using Timer 2 for the receiver ments. For a complete understanding of the 8XC5X
or transmitter and using Timer 1. for the other function. UART please refer to the description in the 80C51
Setting RCLK and/or TCLK puts Timer 2 into its Hardware Description chapter in the 8-bit Embedded
baud rate generator mode, as shown in Figure 4. Controller Handbook.
The baud rate generator mode is similar to the auto-re- Framing Error Detection-Framing Error Detection
load mode, in that a rollover in TH2 causes the Timer 2 allows the serial port to check for valid stop bits in
registers to be reloaded with the 16-hit value in registers modes I, 2, or 3. A missing stop bit can be caused, for
RCAP2H and RCAP2L, which are preset by software. example, by noise on the serial lines, or transmission by
twoCPUs simultaneously.
The baud rates in Modes 1 and 3 are determined by
Timer 2's overflow rate as follows: If a stop bit is missing a Framing Error bit (FE) is set.
The FE bit can be checked in software after each recep-
Timer 2 Overflow Rate tion to detect communication errors. Once set, the FE
Modes 1 and 3 Baud Rates = 16
bit must be cleared in software. A valid stop bit will not
clear FE.' .
The Timer can be configured for either "timer" or
"counter" operation. In most apE!!cations, it is config- The FE bit is located in SCON and shares the same bit
ured for "timer" operation (CP/T2 = 0). The "timer" address as SMO. Control bit SMODO in the PCON reg-
operation is different for Timer 2 when it's being used ister (location PCON.6) determines whether the SMO
as a baud rate generator. Normally, as a timer, it incre- or FE bit is accessed. If SMODO = 0, then accesses to
ments every machine cycle (thus at 1/12 the oscillator SCON.7'are to SMO. IfSMODO = I, then accesses to
frequency). As a baud rate generator, however, it incre- SCON.7 are to FE.
ments every state time (thus at '12 the oscillator fre-
quency). The baud rate formula is given below: Automatic Address Recognition-Automatic Address
Recognition reduces the CPU time required to service
Modes 1 and 3 _ Oscillator Frequency the serial port. Since the CPU is only interrupted when
Baud Rate 32 x [65536 - (RCAP2H, RCAP2L)] it receives its own address, the software overhead to
compare addresses is eliminated. With this feature en-
where (RCAP2H, RCAP2L) is the content of abled in one of the 9-bit modes, the Receive Interrupt
RCAP2H and RCAP2L taken as a 16-bit unsigned in- OU) flag will only get set when the received byte corre-
teger. . sponds to either a Given or Broadcast address.
7-43
intJ 8XC52/54/58 HARDWARE DESCRIPTION
TIMER 1 OVERFLOW
- - -51.1001
o-J' cjT2= 1
T2 PIN
TRANSITION
OITECTION
T2EX PIN TIMER 2
INTERRUPT
270783-4
Figure 4. Timer 2 in Baud Rate Generator Mode
A' way to use this feature in multiprocessor systems is A slave's individual address is specified in SADDR.
as follows: SADEN is a mask byte that defines don't-care bits to
form the Given Address. These don't-cares allow flexi-
When the master processor wants to transmit a block of bility in the user-dermed protocol to address one or
data to one of several slaves, it first sends out an ad- more slaves at a time. The following is an example of
dress byte which identifies the target slave. Remember, how the user could derme Given Addresses ~o selective-
an address byte has its 9th bit set to I, whereas a data ly address different slaves.
byte has its 9th bit set to O. All the slave processors
should have their SM2 bits set to I so they will only be Slave 1:
interrupted by an address byte. The Automatic Address
Recognition feature allows only the addressed slave to SADDR 1111 0001
be interrupted. In this mode, the address comparison SADEN 11111010
occurs in hardware, not software. (On the SOCSI serial GIVEN 11110XOX
port, an address byte interrupts all slaves for an address
comparison).
Slave 2:
The addressed slave then clears its SM2 bit and pre- SADDR 1111 0011
pares to receive the data bytes that will be coming. The SADEN 11111001
other slaves are unaffected by these data bytes as they
are still waiting to receive' an address byte. GIVEN 1111 OXX1
The feature works the same way in the S-bit mode The SADEN bits are selected such that each slave can
(Mode I) as in the 9-bit modes, except that the stop bit be addressed separately. Notice that bit 0 (LSB) is a
takes the place of the 9th data bit. If SM2 is set,the RI don't-care for Slave l's Given Address, but bit 0 = 1
flag is set only if the received byte matches the Given or for Slave 2. Thus, to selectively communicate with just
Broadcast Address and is terminated by a valid stop Slave 1 the master must send an address with bit 0 = 0
bit. Setting the SM2 bit has no effect on Mode O. (e.g., 1111 0000).
The master can selectively communicate with groups of Similarly, bit 1 = 0 for Slave 1, but is a don't-care for
slaves by using the Given Address. Addressing all Slave 2. Now to communicate with just Slave 2 an ad-
slaves at once is possible with the Broadcast Address. dress with bit I = 1 must be used (e.g., 1111 0111).
These addresses are defined for each slave by two Spe-
cial Function Registers: SADDR and SADEN.
'7-44
intJ 8XC52/54/58 HARDWARE DESCRIPTION
Finally, for a master to communicate with both slaves rupts (Timers 0, I, and 2), and the serial port interrupt.
at once the address must have bit 0 = 1 and bit I = O. These interrupts are all shown in Figure 5.
Notice, however, that bit 2. is a don't-care for both
slaves. This allows two different addresses to select Timer 2 Interrupt is generated by the logical OR of bits
both slaves (1111 0001 or 1111 0101). If a third slave TF2 and EXF2 in register T2CON. Neither of these
was added that required its bit 2 = 0, then the latter . flags is cleared by hardware when the service routine is
address could be used to communicate with Slave 1 and vectored to. In fact, the service routine may have to
2 but not Slave 3. determine whether it was TF2 or EXF2 that generated
the interrupt and that bit will have to be cleared in
The master can also communicate with all slaves at software.
once with the Broadcast Address. It is formed from the
logical OR of the SADDR and SADEN registers with The Timer 0 and Tirrier 1 flags, TFO and TFl, are set at
zeroes defined as don't-cares. The don't-cares also al- S5P2 of the cycle in which the timers overflow. The
low flexibility in defining the Broadcast Address, but in values are then polled by the circuitry in the next cycle.
most applications a Broadcast Address will be OFFH. However, the Timer 2 flag, TF2 is set at S2P2 and is
polled in the same cycle in which the timer overflows.
SADDR and SADEN are located at address OA9H and
OB9H, respectively. On reset, the SADDR and
SADENregisters are initialized to OOH which dermes . Interrupt Priority Structure (8XC54/58)
the Given and Broildcast Addresses as XXXX XXXX
(all don't-cares). This assures the 8XC5X serial port to On the 8XC54 and 8XC58, a second Interrupt Priority
be backwards compatible with other MCS®-51 prod- register (IPH) has been added, increasing the number
ucts which do not implement automatic address recog- of priority levels to four. Table. 6 shows this second
nition. register. The added register becomes the MSB of the
priority select bits and the existing IP register acts as
the LSB. This scheme maintains compatibility with the
INTERRUPTS rest of the MCS-51 family. Table 7 shows the bit values
and priority levels associated with each combination.
The 8XC5X has a total of 6 interrupt vectors: two ex-
ternal interrupts (INTO and INTI), three timer inter-
Table 6. IPH: Interrupt Priority High Register
IPH (8XC54/58 Only) Address = OB7H Reset Value = XOOO 0000
PPCH PT2H PSH PT1H PX1H PTOH PXOH
Bit 7 6 5 4 3 2 o
Symbol Function
- Not Implemented, reserved for future use.
PPCH PCA interrupt priority high bit.
PT2H Timer 2 interrupt priority high bit.
PSH Serial Port interrupt priority high bit.
PT1H Timer 1 interrupt priority high bit.'
PX1H External interrupt 1 priority high bit.
PTOH Timer 0 interrupt priority high bit.
PXOH External interru pt p riori ty hi g hbit.
7-45
infef 8XC52/54/58 HARDWARE DESCRIPTION
Table 7. Priority Level Bit Values With an external interrupt, INTO or INTI must be en-
(8XC54/58 Only) abled and configured as level-sensitive before entering
Power. Down. Holding the pin low restarts the oscilla-
Priority Bits tor and bringing the pin back high completes the exit.
Interrupt Priority Level
IPH.x IP.x After the RET! instruction is executed in the interrupt
service routine, the next instruction will be the one fol-
0 0 Level 0 (Lowest) lowing the instruction that put the device in Power
Down.
0 1 Level 1
1 0 Level 2
1 1 Level 3 (Highest) POWER OFF FLAG
The Power OfT Flag (POP) is set by hardware when
Vee rises from 0 to approximately 5V. POF can also be
POWER DOWN MODE set or cleared by software. This allows the user to dis-
tinguish between a "cold start" reset and a "warm
The 8XC5X can exit Power Down with either a hard- start" reset.
ware reset or external interrupt. Reset redefines all the
SFRs but does not change the on-chip RAM. An exter- A· cold start reset is one that is coincident with Vee
nal interrupt allows both. the SFRs (except PD in being turned on to the device after it was turned ofT. A
PCON) and the on-chip RAM to retain their values. warm start reset occurs while Vee is still applied to the
device and could be generated, for example, by an exit
from Power Down.
Immediately after reset, the user's software can check
the status of the POF bit. POF = 1 would indicate a
cold start. The software then clears POF and com-
mences its tasks. POF = 0 immediately after reset
would indicate a warm start.
Vee must remain above 3V for POF to retain a O.
TFO ---'-----------+~
Program Memory Lock
In some microcontroller applications it is desirable that
the Program Memory be secure from software piracy.
The 8XC54 and 8XC58 have varying degrees of pro-
gram protection depending on the device. Table 8 out-
lines the lock schemes available for each device.
TFl Encryption Array: Within the EPROM/ROM is an ar-
ray of encryption bytes that a,e initially unprogrammed
(all l's). For EPROM devices, the user can program
TI
RI D the encryption array to encrypt the program code bytes
during EPROM verification. For ROM devices, the
user submits the encryption array to be programmed by
TF2
EXF2 D 270783-5
the factory. If an encryption array is submitted, LBI
will also be programmed by the factory. The encryption
array is not available without the Lock Bit. Program
code verification is performed as usual except that each
Figure 5. Interrupt Sources code byte comes out exclusive-NOR'ed (XNOR) with
one of the key bytes. Therefore, to read the
To properly terminate Power Down the reset or exter- ROM/EPROM code, the user has to know the encryp-
nal interrupt should not be applied before Vee is re- tion key bytes in their proper sequence.
stored to its normal operating 'level and must be held
active long enough for the oscillator to restart and sta- Unprogrammed bytes have the value OFFH. If the En-
bilize (normally less than 10 msec). cryption Array is left unprogrammed, all the key bytes
have the value OFFH. Since any code byte XNOR'ed
7-46
inter 8XC52/54/58 HARDWARE DESCRIPTION
with OFFH leaves the byte unchanged, leaving the En- ONCETM MODE
cryption Array unprogrammed in effect bypasses the
encryption feature. The ON-Circuit Emulation (ONCETM) mode facili-
tates testing and· debugging of systems using the
Program Lock Bits: Also included in the Program 8XC5X without having to remove the device from the
Lock scheme are Lock Bits which can be enabled to circuit. The ONCE mode is invoked by either:
provide varying degrees of protection. Table 9 lists the 1. Pulling ALE low while the device is in reset and
Lock Bits and their corresponding influence on the mi- PSEN is high;
crocontroller. Refer to Table 8 for the Lock Bits avail-
able on the various products. The user is responsible for 2. Holding ALE low al! RESET is deactivated.
programming the Lock Bits on EPROM devices. On
ROM devices, LBI is automatically set by the factory While the device is in ONCE mode, the Port 0 pins go
when the encryption array is submitted. The Lock Bit into a float state, and the 'other port pins, ALE, and
is not available without the encryption array on ROM PSEN are weakly pulled high. The oscillator circuit
devices. remains active. While the device is in this mode, an
emulator or test CPU can be used to drive the circuit.
Erasing the EPROM also erases the Encryption Array
and the Lock Bits, returning the part to full functionali- Normal operation is restored aftllr a valid reset is ap-
ty. plied.
Table 8. Program Protection
ADDITIONAL REFERENCES
Device Lock Bits Encrypt Array
80C52 None None
The following application notes provide supplemental
, information to this document and can be found in the
80C54 LB1 64 Bytes
Embedded Control Applications handbook (Order No.
80C58 LB1 64 Bytes 270648).
87C54 LB1,LB2,LB3 64 Bytes
1. AP-125 "Designing Microcontroller Systems for
87C58 LB1,LB2,LB3 64 Bytes Electrically Noisy Environments"
2. AP-155 !'Oscillators for Microcontrollers"
3. AP-252 "Designing with the 80C51BH"
4. AP-410 "Enhanced Serial Port on the 83C5IFA";
Table 9. Lock Bits
Program
Lock Bits Protection Type
LB1 LB2 LB3
1 U U U No program lock features enabled. (Code verify will still be encrypted by the
encryption array if programmed.)
2 P U U MOVC instructions executed from external program memory are disabled from
fetching' code bytes from internal memory, EA is sampled and latched on
reset, and further programming of the EPROM is disabled.
3 P P U Same as 2, also verify is disabled.
4 P P P Same as 3, also external execution is disabled.
P = Programmed
U = Unprogrammed
Any other combination of Lock Bits is nol defined.
7-47
MCS®-51
8-BIT CONTROL-ORIENTED MICROCOMPUTERS
8031/8051
8031 AH/8051 AH
8032AH/8052AH
8751H/8751H-8
• High Performance HMOS Process
• Boolean Processor
• Internal Timers/Event Counters
• Bit-Addressable RAM
• 2-Level Interrupt Priority Structure
• Programmable Full Duplex Serial
• 32 I/O Lines (Four 8-Bit Ports) Channel
• 64KData
111 Instructions (64 Single-Cycle)
• 64K Program Memory Space
• Memory Space
• Security Feature Protects EPROM Parts
Against Software Piracy
The MCS®-51 products are optimized for control applications. Byte-processing and numerical operations on
small data structures are facilitated by a variety of fast addressing modes for accessing the internal RAM. The
instruction set provides a convenient menu of B-bit arithmetic instructions, including multiply and divide instruc-
tions. Extensive on-chip support is provided for one-bit variables as a separate data type, allowing direct bit
manipulation and testing in control and logic systems that require Boolean processing.
The 8051 is the original member of the MCS-51 family. The B051AH is identical to the 8051, but it is fabricated
with HMOS II technology.
The 8751H is an EPROM version of the 8051AH; that is, the on-chip Program Memory can be electrically
programmed, and can be erased by exposure to ultraviolet light. It is fully compatible with its predecessor, the
B751-8, but incorporates two new features: a Program Memory Security bit that can be used to protect the
EPROM against unauthorized read-out, and a programmable baud rate modification bit (SMOD). The B751 H-8
is identical to the B751 H but only operates up to 8 MHz.
The 8052AH is an enhanced version of the B051AH. It is backwards compatible with the B051AH and is
fabricated with HMOS II technology. The B052AH enhancements are listed in the table below. Also refer to this
table for the ROM, ROM less, and EPROM versions of each product.
Internal Memory Timersl
Device Interrupts
Event Counters
Program Data
8052AH 8KxB ROM 256x8 RAM 3 x 16-Bit 6
8051AH 4Kx.B ROM 12Bx8 RAM 2 x 16-Bit 5
B051 4Kx8 ROM 12B x8 RAM. 2 x 16-Bit 5
B032AH none 256xB RAM 3 x 16-Bit 6
8031AH none 12BxB RAM 2 x 16-Bit 5
8031 none 12Bx8 RAM 2 x 16-Bit 5
8751H 4KxB EPROM 12BxB RAM 2 x 16-Bit 5
B751 H-B 4KxB EPROM 12B x8 RAM 2 x 16-Bit 5
October 1990
7-4B Order Number: 270048-005
inter MCS®·51
PO,0-PO.7 P2.D-P2.7
'cc
,---------- -------------,
n'. I
- I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
HAL 1
·~w--------J
P1.0""".7 P3.D-PJ.7
270048-1
Figure 1. MCS®·51 Block Diagram
PACKAGES Port 0: Port 0 is an 8-bit open drain bidirectional 1/0
port. As an output port each pin can sink 8 LS TTL
Part Prefix Package Type inputs. .
8051AHI P 40-Pin Plastic DIP
8031AH D 40.Pin CERDIP Port 0 pins that have 1s written to them float, and in
N 44-Pin PLCC that state can be used as high-impedance inputs.
8052AHI P 40-Pin Plastic DIP
Port 0 is also the multiplexed low-order address and
8032AH D 40-Pin CERDIP
data bus during accesses to external Program and
N 44-Pin PLCC
Data Memory. In this application it uses strong inter-
8751HI D 40-Pin CERDIP nal pullups when emitting 1s and can source and
8751H-8 sink 8 LS TTL inputs.
Port 0 also receives the code bytes during program-
PIN DESCRIPTIONS ming of the EPROM parts, and outputs the code
bytes during program verification of the ROM and
Vee: Supply voltage. EPROM parts. External pullups are required during
program verification.
Vss: Circuit ground.
7-49
infef MCS®-51
[~n
805218032 ONLY
PI.O Vee
T2EX Pl.l PO.O ADO INDEX
Pl.2 PO.l ADl CORNER
Pl.l PO.2 AD2
P1.4 PO.l ADl L"'J t"'J L·J t1 l'"j l"J L:J L=J L!:J L;J' L~j
Pl.5 PO.4 AD4 Pl.S !:; :;! PO.• (AD4)
Pl.6 PO.5 AD5 Pl.6 :0:; ~~ PO.5 (ADS)
Pl.7 PO.6 A06 Pl.7
RST PO.7 AD7 RST !ti~ n~ PO.7 (AD7)
RXD Pl.O EAlVpp' (RXD) PJ.O ]!.:: D! EAlvpp·
TXD Pl.l AlE/PROG' Ne ~~~ [~ He
INTO Pl.2 PSEN (TXD)P3.1 ~~ ~ Di ALE/JSJRRI·
INTl Pl.3 P2.7 A15 (INTO) P3.2 ~~~ U~ PSEN
TO Pl.4 P2.6A14 (lNTl) Pl.l j~~ ~!t P2.7 (A15)
T1 P3.5 P2.5 All (TO) P3.4 !~; ~!~ PU (A14)
WR P3.6 P2.4 A12
(T2)Pl.S }!~ .. , n .. , .. , ...... n .. , ,. .. ,. ... ,..., r"~!! P2.5(A13)
Rii Pl.7 P2.3 All
XTAl2 P2.2 A10
:!': :~: :2: :;: ;: :~: :=: :~: ::(1: :le: :~: ::e:
XTAll P2.l A9
Vss P2.0 AS
Pin (DIP)
270048-3
Pad
(PLCC)
'EPROM only
Figure 2. MCS®-S1 Connections
Port 1: Port 1 is an 8-bit bidirectional 1/0 port with ing accesses to external Data Memory that use 8-bit
internal pullups. The Port 1 output buffers can sinkl addresses (MOVX @Ri), Port 2 emits the contents of
source 4 LS TIL inputs. Port 1 pins that have 1s the P2 Special Function Register.
written to them are pulled high by the internal pull-
ups, and in that state can be used as inputs. As Port 2 also receives the high-order address bits dur-
inputs, Port 1 pins that are externally being pulled ing programming of the EPROM parts and during
low will source current (IlL on the data sheet) be- program verification of the ROM and EPROM parts.
cause of the internal pullups.
Port 3: Port 3 is an 8-bit bidirectional 1/0 port with
Port 1 also receives the low-order address bytes internal pull ups. The Port 3 output buffers can sinkl
during programming of the EPROM parts and during source 4 LS TIL inputs. Port 3 pins that have 1s
program verification of the ROM and EPROM parts. written to them are pulled high by the internal pull-
ups, and in that state can be used as inputs. As
In the 8032AH and 8052AH, Port 1 pins P1.0 and inputs, Port 3 pins that are externally being· pulled
P1.1 also serve the T2 and T2EX functions, respec- low will source current (IlL on the data sheet) be-
tively. cause of the pullups.
Port 2: Port 2 is an 8-bit bidirectional 1/0 port with Port 3 also serves the functions of various special
internal pullups. The Port 2 output buffers can sinkl features of the MeS-51 Family, as listed below:
source 4 LS TIL inputs. Port 2 pins that have 1s
written to them are pulled high by the internal pull- Port
Alternative Function
ups, and in that state can be used as inputs. As Pin
inputs, Port 2 pins that are externally being pulled P3.0 RXD (serial input port)
low will source current (IlL on the data sheet) be- P3.1 TXD (serial output port)
cause of the internal pullups. P3.2 INTO (external interrupt 0)
P3.3 INT1 (external interrupt 1)
Port 2 emits the high-order address byte during P3.4 TO (Timer 0 external input)
fetches from external Program Memory and during P3.5 T1 (Timer 1 external input)
accesses to external Data Memory that use .16-bit P3.6 WR (external data memory write strobe)
addresses (MOVX @DPTR). In this application it P3.7 RD (external data memory read strobe)
uses strong internal pullups when emitting 1s. Dur-
7-50
inter MCS®-51
RST: Reset input. A high on this pin for two machine XTAL 1: Input to the inverting oscillator amplifier.
cycles while the oscillator is running resets the de-
vice. XTAL2: Output from the inverting oscillator amplifi-
er.
ALE/PROG: Address LatchEnable output pulse for
latching the low byte of the address during accesses
to external memory. This pin is also the program OSCILLATOR CHARACTERISTICS
pulse input (PROG) during programming of the
EPROM parts. XT AL 1 and XTAL2 are the input and output, respec-
tively, of an inverting amplifier which can be config-
In normal operation ALE is emitted at a constant ured for use as an on-chip oscillator, as shown in
rate of % the oscillator frequency, and may be used Figure 3. Either a quartz crystal or ceramic resonator
for external timing or clocking purposes. Note, how- may be used. More detailed information concerning
ever, that one ALE pulse is skipped during each ac- the use of the on-chip .oscillator is available in Appli-
cess to external Data Memory. cation Note AP-155, "Oscillators for Microcontrol-
lers."
PSEN: Program Store Enable is the read strobe to
external Program Memory. To drive the device from an external clock source,
XTAL1 should be grounded, while XTAL2 is driven,
When the device is executing code from external as shown in Figure 4. There are no requirements on
Program Memory, PSEN is activated twice each ma- the duty cycle of the external clock signal, since the
chine cycle, except that two PSEN activations are input to the internal clocking circuitry is through a
skipped during each access to external Data Memo- divide-by-two flip-flop, but minimum and maximum
ry. high and low times specified on the Data Sheet must
be observed.
EA/Vpp: External Access enable EA must be
strapped to Vss in order to enable any MCS-51 de-
vice to fetch code from external Program memory EXTERNAL
locations starting at OOOOH up to FFFFH. EA must OSCILLATOR ---~ XTAL2
be strapped to Vee for internal program execution. SIGNAL
Note, however, that if the Security Bit in the EPROM
devices is programmed, the device will not fetch
code from any location in external Program Memory.
r--- XTALI
This pin also receives the 21 V programming supply
voltage (VPP) during programming of the EPROM
parts. ...----1 vss
C2
270048-5
r--~I~-"'---4 XTAL2
Figure 4. External Drive Configuration
D
DESIGN CONSIDERATIONS
"'--~I~-+--~ XTALI If an 8751BH or 8752BH may replace an 8751H in a
Cl future design, the user should carefully compare
both data sheets for DC or AC Characteristic differ-
...-------~vss ences. Note that the VIH and IIH speCifications for
the EA pin differ significantly between the devices.
270048-4
Cl, C2 = 30 pF ± I 0 pF for Crystals
Exposure to light when the EPROM device is in op-
= 40 pF ± 10 pF for Ceramic Resonators eration may cause logic errors. For this reason, it is
suggested that an opaque label be placed over the
Figure .3. Oscillator Connections window when the die is exposed to ambient light.
7-51
inter MCS®-S1
ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. The specifi-
cations are subject to change without notice.
Ambient Temperature Under Bias ...... O°C to 70°C
'WARNING: Stressing the device beyond the "Absolute
Storage Temperature .......... - 65°C to + 150°C Maximum Ratings" may cause permanent damage.
Voltage on EAlVpp Pin to Vss ... -0.5V to + 21.5V These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and ex-
Voltage on Any Other Pin to Vss .... -0.5V to + 7V tended exposure beyond the "Operating Conditions"
Power Dissipation .......................... 1.5W may affect device reliability.
Operating Conditions: TA (Under Bias) = O°Cto + 70°C; Vee = 5V ±10%; Vss = OV
D.C. CHARACTERISTICS (Under Operating Conditions)
Symbol Parameter Min Max Units Test Conditions
VIL Input Low Voltage (Except EA Pin of -0.5 0.8 V
8751 H & 8751 H-8)
VIL1 Input Low Voltage to EA Pin of 0 0.7 V
8751 H & 8751 H-8
VIH Input High Voltage (Except XTAL2, RST) 2.0 Vee + 0.5 V
VIH1 Input High Voltage to XTAL2, RST 2.5 Vee + 0.5 V XTAL1 = Vss
VOL Output Low Voltage (Ports 1, 2, 3)* 0.45 V IOL = 1.6 mA
VOL1 Output Low Voltage (Port 0, ALE, PSEN)*
8751 H, 8751 H-8 0.60 V IOL = 3.2 mA
0.45 V IOL = 2.4 mA
All Others 0.45 V IOL = 3.2 mA
VOH Output High Voltage (Ports 1, 2, 3, ALE, PSEN) 2.4 V IOH = -80/LA
VOH1 Output High Voltage (Port 0 in 2.4 V IOH = - 400 )LA
External Bus Mode)
IlL Logical 0 Input Current (Ports 1, 2, 3,
RST) 8032AH, 8052AH -800 /LA VIN = 0.45V
All Others -500 /LA VIN = 0.45V
IIL1 Logical 0 Input Current to EA Pin of -15 mA VIN = 0.45V
8751 H & 8751 H-8 Only
IIL2 Logical 0 Input Current (XTAL2) -3.2 mA VIN = 0.45V
III Input Leakage Current (Port 0)
8751 H & 8751 H-8 ±100 /LA 0.45 ::;; VIN ::;; Vee
All Others ±10 /LA 0.45 ::;; VIN ::;; Vee
IIH Logical 1 Input Current to EA Pin of 500 /LA VIN = 2.4V
8751 H & 8751 H-8
IIH1 Input Current to RST to Activate Reset 500 /LA VIN < (Vee - 1.5V)
Icc Power Supply Current:
8031/8051 160 mA
8031 AH/8051 AH 125 mA All Outputs
8032AH/8052AH 175 mA Disconnected;
8751 H/8751 H-8 250 mA EA = Vee
CIO Pin Capacitance 10 pF Test freq = 1 MHz
'NOTE:
Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports 1
and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1-to-0
transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the ALE line may
exceed O.BV. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt
Trigger STROBE input.
7-52
inter MCS®·51
A.C. CHARACTERISTICS Under Operating Conditions;
Load Capacitance for Port 0, ALE, and PSEN = 100 pF;
Load Capacitance for All Other Outputs = 80 pF
12 MHz Oscillator Variable Oscillator
Symbol Parameter Units
Min Max Min Max
1/TCLCL Oscillator Frequency 3.5 12.0 MHz
TLHLL ALE Pulse Width 127 2TCLCL":'40 ns
TAVLL Address Valid to ALE Low 43 TCLCL-40 ns
TLLAX Address Hold after ALE Low 48 TCLCL-35 ns
TLLlV ALE Low to Valid Instr In
8751H 183 4TCLCL-150 ns
All Others 233 4TCLCL-100 ns
TLLPL ALE Low to PSEN Low 58 TCLCL-25 ns
TPLPH PSEN Pulse Width
8751H 190 3TCLCL-60 ns
All Others 215 3TCLCL-35 ns
TPLIV PSEN Low to Valid Instr In
8751H 100 3TCLCL-150 ns
All Others 125 3TCLCL-125 ns
TPXIX Input Instr Hold after PSEN 0 0 ns
TPXIZ Input Instr Float' after PSEN 63 TCLCL-20 ns
TPXAV PSEN to Address Valid 75 TCLCL-8 ns
TAVIV Address to Valid Instr In
8751H 267 5TCLCL-150 ns
All Others 302 5TCLCL-115 ns
TPLAZ PSEN Low to Address Float 20 20 ns
TRLRH RDPuise Width 400 6TCLCL-100 ns.
TWLWH WR Pulse Width 400 6TCLCL-100 ns
TRLDV RD Low to Valid Data In 252 5TCLCL-165 ns
TRHDX Data Hold after RD 0 0 ns
TRHDZ Data Float after RD 97 2TCLCL-70 ns
TLLDV ALE Low to Valid Data In 517 8TCLCL-150 ns
TAVDV Address to Valid Data In 585 9TCLCL-165 ns
TLLWL ALE Low to RD or WR Low 200 300 3TCLCL-50 3TCLCL+50 ns
TAVWL Address to RD or WR Low 203 4TCLCL-130 ns
TOVWX Data Valid to WR Transition
8751H 13 TCLCL-70 ns
All Others 23 TCLCL-60 ns
TOVWH Data Valid to WR High 433 7TCLCL-150 ns
TWHOX Data Hold after WR 33 TCLCL-50 ns
TRLAZ RD Low to Address Float 20 20 ns
TWHLH RD or WR High to ALE High
8751H 33 133 TCLCL-50 TCLCL+50 ns
All Others 43 123 TCLCL-40 TCLCL+40 ns
NOTE:
·This table does not include the 8751-8 A.C. characteristics (see next page).
7-53
inter MCS®·51
This Table Is only for the 8751H·8
A.C. CHARACTERISTICS Under Operating Conditions;
Load Capacitance for Port 0, ALE, and PSEN = 100 pF;
Load Capacitance for All Other Outputs = 80 pF
8 MHz Oscillator Variable Oscillator
Symbol Parameter Units
Min Max Min Max
1/TCLCL Oscillator Frequency 3.5 8.0 MHz
TLHLL ALE Pulse Width 210 2TCLCL-40 ns
TAVLL Address Valid to ALE Low 85 TCLCL-40 ns
TLLAX Address Hold after ALE Low 90 TCLCL-35 ns
TLLlV ALE Low to Valid Instr In 350 4TCLCL-150 ns
TLLPL ALE Low to PSEN Low 100 TCLCL-25 ns
TPLPH PSEN Pulse Width 315 3TCLCL-60 ns
TPLIV PSEN Low to Valid Instr In 225 3TCLCL-150 ns
TPXIX Input Instr Hold after PSEN 0 0 ns
TPXIZ Input Instr Float after PSEN 105 TCLCL-20 ns
TPXAV PSEN to Address Valid 117 TCLCL-8 ns
TAVIV Address to Valid Instr In 475 5TCLCL-150 ns
TPLAZ PSEN Low to Address Float 20 20 ns
TRLRH RD Pulse Width 650 6TCLCL-100 ns
TWLWH WR Pulse Width 650 6TCLCL-100 ns
TRLDV RD Low to Valid Data In 460 5TCLCL-165 ns
TRHDX Data Hold after RD 0 0 ns
TRHDZ Data Float after RD 180 2TCLCL-70 ns
TLLDV ALE Low to Valid Data In 850 8TCLCL-150 ns
TAVDV Address to Valid Data In 960 9TCLCL-165 ns
TLLWL ALE Low to RD or WR Low 325 425 3TCLCL-50 3TCLCL+50 ns
TAVWL Address to RD or WR Low 370 4TCLCL-130 ns
TQVWX Data Valid to WR Transition 55 TCLCL-70 ns
TQVWH Data Valid to WR High 725 7TCLCL-150 ns
TWHQX Data Hold after WR 75 TCLCL-50 ns
TRLAZ RD Low to Address Float 20 20 ns
TWHLH RD or WR High to ALE High 75 175 TCLCL-50 TCLCL+50 ns
7-54
intJ MCS®-51
EXTERNAL PROGRAM MEMORY READ CYCLE
ALE
PORTO
PORT 2
270048-6
7-55
infef MCS®-S1
EXTERNAL DATA MEMORY READ CYCLE
ALE
i-+-----TLLDV - - - - - I
.. TRLRH +----t~
PORTO
PORT 2 P2.0-P2.7 OR A8-A15 FROM OPH A8-A15 FROM PCH
270048-7
EXTERNAL DATA MEMORY WRITE CYCLE
TWHLH
ALE
TLLWL ---I~~t----TWLWH ------I~
TQVWX
1---1---1 I--I----TQVWH - - - - - I
PORTO DATA OUT
PORT 2 P2.0-P2.7 OR A8-A15 FROM DPH A8-A15 FROM PCH
270048-8
7-56
intJ MCS®-51
SERIAL PORT TIMING-SHIFT REGISTER MODE
TA = O°C to 70°C; VCC = 5V ± 10%; VSS = OV;
Test Conditions: Load Capacitance = 80 pF
12 MHz Oscillator Variable Oscillator
Symbol Parameter Units
Min Max Min Max
TXLXL Serial Port Clock Cycle Time 1.0 12TCLCL J-Ls
TOVXH Output Data Setup to Clock Rising 700 1OTCLCL -133 ns
Edge
TXHOX Output Data Hold after Clock 50 2TCLCL-117 ns
Rising Edge
TXHDX Input Data Hold after Clock Rising 0 0 ns
.Edge
TXHDV Clock Rising Edge to Input Data 700 1OTCLCL -133 ns
Valid
SHIFT REGISTER TIMING WAVEFORMS
\-m.. -1
----~
t.... 'OVIH . . . 1 ~TJ.HQI I
\ X X X~ __-JX~__~X~__-JX~__-JX~__-J7
~
• "IT£ TO S8Uf
I j
""D' - l I--""D•
t
sun
"""UTOA'"
ell::,,"AI
7-57
MCS®-51
EXTERNAL CLOCK DRIVE
Symbol Parameter Min Max Units
1/TClCl Oscillator Frequency (except 8751 H-8) 3.5 12 MHZ
8751 H-8 3.5 8 MHz
TCHCX High Time 20 ns
TClCX low Time 20 ns
TClCH Rise Time 20 ns
TCHCl Fall Time 20 ns
EXTERNAL CLOCK DRIVE WAVEFORM
~---------TCLCL----------~~
270048-10
A.C. TESTING INPUT, OUTPUT WAVEFORM
"=X
.
0.45
2.0
0.8
> TEST POINTS < . 2.0
0.8 x=
270048-11
A.C. Testing: Inputs are driven at 2.4V for a Logic "1" arid 0.45V
for a Logic "0". Timing measurements are made at 2.0V for a
Logic "1" and 0.8V for a Logic "0".
7-58
inter MCS®-51
EPROM CHARACTERISTICS
Table 3 EPROM Programming Modes
Mode RST PSEN ALE EA P2.7 P2.6 P2.5 P2.4
Program 1 0 O· VPP 1 0 X X
Inhibit 1 0 1 X 1 0 X X
Verify 1 0 1 1 0 0 X X
Security Set 1 0 O· VPP 1 1 X X
NOTE:
"1" = logic high for that pin "VPP" = +21V ±0.5V
"0" = logic low for that pin 'ALE is pulsed low for 50 ms.
"X" = "don't care"
Programming the EPROM Note that the EAIVPP pin must not be allowed to go
above the maximum specified VPP level of 21.5V for
To be programmed, the part must be running with a any amount of time. Even a narrow glitch above that
4 to 6 MHz oscillator. (The reason the oscillator voltage level can cause permanent damage to the
needs to be running is that the internal bus is being device. The VPP source should be well regulated
used to transfer address and program data to appro- and free of glitches.
priate internal registers.) The address of an EPROM
location to be programmed is applied to Port 1 and
pins P2.0-P2.3 of Port 2, while the code byte to be Program Verification
programmed into that location is applied to Port O.
If the Security Bit has not been programmed, the on-
The other Port 2 pins, and RST, PSEN, and EA
chip Program Memory can be read out for verifica-
should be held at the "Program" levels indicated in tion purposes, if desired, either during or after the
Table 3. ALE is pulsed low for 50 ms to program the
programming operation. The address of the Program
code byte into the addressed EPROM location. The Memory location to be read is applied to Port 1 and
setup is shown in Figure 5.
pins P2.0-P2.3. The other pins should be held at the
"Verify" levels indicated in Table 3. The contents of
Normally EA is held at a logic high until just before the addressed location will come out on Port O. Ex-
ALE is to be pulsed. Then EA is raised to + 21 V,
ternal pullups are required on Port 0 for this opera-
ALE is pulsed, and then EA is returned to a logic tion.
high. Waveforms and detailed timing specifications
are shown in later sections of this data sheet. The setup, which is shown in Figure 6, is the same
as for programming the EPROM except that pin P2.7
is held at a logic low, or may be used as an active-
+5V
low read strobe.
.sv
8751H
P2.0-
P2.3
P2.6 8751H
P2.7 P2.4
'--~-1 XTAL2 P2.5
P2.6 VIH
P2.7
'--....+-1 HALl
XTAl2
vss
XTAl1
270048-12 vss
Figure 5. Programming Configuration
270048-13
Figure 6. Program Verification
7-59
MCS®-51
EPROM Security + 5V
X ~ "DON'T CARE"
The security feature consists of a "locking" bit which
when programmed denies electrical access by any VCC
external means to the on-chip Program Memory.
The bit is programmed as shown in Figure 7. The
PO X
setup and procedure are the same as for normal P2.0-
EPROM programming, except that P2.6 is held at a B751H
logic high. Port 0, Port 1, and pins P2.0-P2.3 niay be
in any state. The other pins should be held at the P2.4 ALE
"Security" levels indicated in Table 3. P2.S
P2.6
Once the Security Bithas been programmed, it can P2.7 EA u.'VPP
be cleared only by full erasure of the Program Mem- XTAL2
ory. While it is programmed, the internal Program
RST VIHl
Memory can not be read out, the device can not be
XTAL1
further programmed, and it can not execute out of
external program memory. Erasing the EPROM, VSS
thus clearing the Security Bit, restores the device's
full functionality. It can then be reprogrammed.
270048-14
Figure 7. Programming the Security Bit
Erasure Characteristics
The recommended erasure procedure is exposure
Erasure of the EPROM begins to occur when the' to ultraviolet light (at 2537 Angstroms) to an integrat-
chip is exposed to light with wavelengths shorter ed dose of at least 15. W-secl cm 2. Exposing the
than approximately 4,000 Angstroms. Since sunlight
EPROM to an ultraviolet lamp of 12,000 fJ-W/cm2
and fluorescent lighting have wavelengths in this rating for 20 to 30 minutes, at a distance of about 1
range, exposure to these light sources over an ex- inch, should be sufficient.
tended time (about 1 week in sunlight, or 3 years in
room-level fluorescent lighting) could cause inadver- Erasure leaves the array in an all 1s state.
tent erasure. If an application subjects the device to
this type of exposure, it is suggested that an opaque
label be placed over the window.
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
TA = 21°C to 27"C; VCC = 5V ±10%; VSS = ov
Symbol Parameter Min Max Units
VPP Programming Supply Voltage 20.5 21.5 V
IPP Programming Supply Current 30 mA
1/TCLCL Oscillator Frequency 4 6 MHz
TAVGL Address Setup to PROG Low 48TCLCL
TGHAX Address Hold after PROG 48TCLCL
TDVGL Data Setup to PROG Low 48TCLCL
TGHDX Data Hold after PROG 48TCLCL·
TEHSH P2.7 (ENABLE) High to VPP 48TCLCL
TSHGL VPP Setup to PROG Low 10 fJ-s
TGHSL VPP Hold after PROG 10 fJ-s
TGLGH PROGWidth 45 55 ms
TAVOV Address to Data Valid 48TCLCL
TELOV ENABLE Low to Data Valid 48TCLCL
TEHOZ Data Float after ENABLE 0 48TCLCL
7-60
inter MCS®-51
EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
PROGRAMMING VERIFICATION
1.0--1'1.7
P2.0--1'2.3
ADDRESS ADDRESS
,
I
PORT 0 DATA IN
- _TAVQV
DATA OUT
TDVGL f-- -- I-- - TGHDX
LE/PROG
TAVGL ! I-- TGHAX
\W
TSHGL TGHSL
TGLGH
21V ± .SV
\
U./VPP ~ TTL HIGH TTL HIGH TTL HIGH
P2.7
TEHSH
I---- TELQV_
,
:-- - _TEHQZ
(ENABLE)
J J
270048-15
For programming conditions see Figure 5. For verification conditions see Figure 6.
DATA SHEET REVISION HISTORY
The following are the key differences between this and the -004 version of this data sheet.
1. Data sheet status changed from "Preliminary" to "Production".
2. LCC package offering deleted.
3. Maximum Ratings Warning and Data Sheet Revision History revised.
The following are the key differences between this and the -003 version of this data sheet:
1. Introduction was expanded to include product descriptions.
2. Package table was added.
3. Design Considerations added.
4. Test Conditions for 111l and IIH specifications added to the DC Characteristics.
5. Data Sheet Revision History added.
7-61
8051AHP
MCS®-51 FAMILY
8-BIT CONTROL-ORIENTED MICROCONTROLLER
WITH PROTECTED ROM
• High Performance HMOS Process • Bit-Addressable RAM
• Internal Timers/Event Counters • Programmable Full Duplex Serial
Channel .
• 2-Level Interrupt Priority Structure
• 32 I/O Lines (Four 8-Bit Ports) • 111 Instructions (64 Single-Cycle)
• 4K Program Memory Space • 4K Data Memory Space*
*Expandable to 64K
• Protection Feature Protects ROM Parts
Against Software Piracy • Available in 40 Pin Plastic and CERDIP
Packages
• Boolean Processor (See Packaging Outlines and Dimensions Order #231369)
The MCS®-51 products are optimized for control applications. Byte-processing and numerical operations on
small data structures are facilitated by a variety of fast addressing modes for accessing the internal RAM. The
instruction set provides a convenient menu of 8-bit arithmetic instructions, including multiply and divide instruc-
tions. Extensive on-chip support is provided for one-bit variables as a separate data type, allowing direct bit
manipulation and testing in control and logic systems that require Boolean processing.
MCS-51 HMOS Internal Memory Timersl
Interrupts
Family Device Event Counters
Program Data
8051AH 4Kx8 ROM 128x8 RAM 2 x 16-Bit 5
8051AHP 4Kx8 ROM 128x8 RAM 2 x 16-Bit 5
The 8051AHP is identical to the 8051AH with the exception of the Protection Feature. To incorporate this
Protection Feature, program verification has been disabled and external memory accesses have been limited
~« .
October 1990
7-62 Order Number: 270279-004
inl:ef 8051AHP
PO.O-PO 7 P2.o-P2.7
Vee
r---------- -------------~
Vss I
r.
I
I
I
I
PSEN z
0",
I
ALE ~~~ g;I~----~~~--~~--~-------~~----~~-~--J I
u ~U~----~~----------------------.-.-----~~--V I
AST --+ ~~ ~----~ I
I '----.-L-....I I
I I
I I
I I
I I
L..,-.,.:T~..,.J ________ )
L
XTAL 1
P1.0-P1.7 P3.0-P3.7
270279-1
Figure 1. MCS®-S1 Block Diagram
7-63
8051AHP
PACKAGES LS TTL inputs. Port 1 pins that have 1s written to
them are pulled high by the internal pullups, and in
Part Prefix Package Type that state can be used as inputs. As inputs, Port 1
a051AHP P 40-Pin Plastic DIP pins that are externally being pulled low will.source
D 40-Pin CERDIP current (IlL, on the data sheet) because of the inter-
nal pull ups.
Pl.0 vee Port 2
PO.O ADO
PO.l AOl
PO.2 AD2
Port 2 is an a-bit bidirectional liD port with internal'
Pl .• PO.3 AD3 pullups. The Port 2 output buffers can sinklsource 4
Pl.S
Pl.6
PO.' AD4 LS TTL inputs. Port 2 pins that have 1s written to
PO.S ADS
PO.6 AD6 them are pulled high by the internal pull ups, and in
PO.1 AD1 that state can be used as inputs. As inputs, Port 2
RXD P3.0 Eli pins that are externally being pulled low will source
TXD P3.1 ALE
INTO P3.2 PsEH current (IlL on the data sheet) because of the inter·
INTI P3.3 P2.1 nal pullups.
TO P3.' P2.6
T1 P3.S P2.S
\Vii P3.6 P2.' Port 2 emits the high-order address byte during
AD P3.1 P2.3 A11 fetches from external Program Memory and during
XTAL2 P2.2 Al0
XTALI P2.1 A9 accesses to external Data Memory that use 16-bit
vss addresses (MOVX @DPTR). In this application it
270279-2
uses strong internal pullups when emitting 1s. Bits
P2.4 through P2.7 are forced to 0, effectively limiting
Pin (PDIP, CERDIP)
external Data and Code space to 4K each in the
Figure 2. MCS®·51 Connections a051AHP during external accesses". During access-
es to external Data Memory that use a-bit addresses
(MOVX @Ri), Port 2 emits the contents of the P2
PIN DESCRIPTIONS Special Function Register.
VCC Port 3
Supply voltage. Port 3 is an a-bit bidirectional liD port with internal
,pullups. The Port 3 output buffers can sinklsource 4
LS TTL inputs. Port 3 pins that have 1s written to
Vss them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 3
Circuit ground. pins that are externally being pulled low will source
current (IlL on the data sheet) because of the pull-
ups.
Port 0
Port 3 also serves the functions of various special
Port 0 is an a-bit open drain bidirectional 110 port. As features of the MCS-51 Family, as listed below:
an output port each pin can sink a LS TTL inputs.
Port
Port 0 pins that have 1s written to them float, and in Alternative Function
that state can be used as high-impedance inputs. Pin
P3.0 RXD (serial input port)
Port 0 is also the multiplexed low-order address and P3.1 TXD (serial output port)
data bus during accesses to external Program and P3.2 INTO (external interrupt 0)
Data Memory. In this application it uses strong inter-
P3.3 INT1 (external interrupt 1)
nal pull ups when emitting 1s and can source and
sink a LS TTL inputs. P3.4 TO (Timer 0 external input)
P3.5 T1 (Timer 1 external input)
P3.6 WR (external data memory write strobe)
Port 1 P3.7 RD (external data memory read strobe)
Port 1 is an a-bit bidirectional liD port with internal
pullups. The Port 1 output buffers can sink source 4
• Protection feature
7-64
intJ 8051AHP
RST XTAL2
Reset input. A high on this pin for two machine cy- Output from the inverting oscillator amplifier.
cles while the oscillator is running resets the device.
OSCILLATOR CHARACTERISTICS
ALE
XT AL 1 and XTAL2 are the input and output, respec-
Address Latch Enable output pulse for latching the tively, of an inverting amplifier which can be config-
low byte of the address during accesses to external ured for use as an on-chip oscillator, as shown in
memory. Figure 3. Either a quartz crystal or ceramic resonator
may be used. More detailed information concerning
In normal operation ALE is emitted at a constant the use of the on-chip oscillator is available in Appli-
rate of % the oscillator frequency, and may be used cation Note AP-155, "Oscillators for Microcontrol-
for external timing or clocking purposes. Note, how- lers."
ever, that one ALE pulse.is skipped during each ac-
cess to external Data Memory. To drive the device from an external clock source,
XTAL 1 should be grounded, while XTAL2 is driven,
as shown in Figure 4. There are no requirements on
the duty cycle of the external clock signal, since the
Program Store Enable is the read strobe to external input to the internal clocking circuitry is through a
Program Memory. divide-by-two flip-flop, but minimum and maximum
high and low times specified on the Data Sheet must
When the device is executing code from external be observed.
Program Memory, PSEN is activated twice each ma-
chine cycle, except that two PSEN activations are
skipped during each access to external Data Memo- EXTERNAL
ry. OSCILLATOR -----t XTAL2
SIGNAL
External Access enable EA should be strapped to
Vee for internal program executions. EA must be r--- XTALt
strapped to VSS in order to enable any MCS-51 de-
vice to fetch code from external Program memory
locations starting at OOOOH up to FFFFH. .....---t vss
C2
270279-5
r---i~--+---I XTAL2
Figure 4. External Drive Configuration
o DESIGN CONSIDERATION
The 8051AHP cannot access external Program or
"'--I~-"""--I XTALt Data memory above 4K. This means that the follow-
Ct ing instructions that use the Data Pointer only read/
write data at address locations below OFFFH:
t-------~vss
MOVX A, @DPTR
MOVX @DPTR, A
270279-4
Ct. C2 ~ 30 pF ± to pF for Crystals
~ 40 pF ± to pF for Ceramic Resonators
When the Data Pointer contains an address above
the 4K limit, those locations will not be accessed.
Figure 3. Oscillator Connections
To access Data Memory above 4K, the MOVX, @Ri,
A or MOVX A, @Ri instructions must be used.
XTAL1
Input to the inverting oscillator amplifier.
7-65
intJ 8051AHP
ABSOLUTE MAXIMUM RATINGS· NOTICE: This is a production data sheet. The specifi-
cations are subject to change without notice.
Ambient Temperature Under Bias .... O°C to + 7rYC
• WARNING: Stressing the device beyond the "Absolute
Storage Temperature, .......•.. - 65°C to + 150°C Maximum Ratings" may cause permanent damage.
Voltage on EAivpp Pin to Vss ... -0.5V to + 21.5V These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and ex- '
Voltage on Any Other Pin to Vss .... -0.5V to + 7V tended exposure beyond the "Operating Conditions"
Power Dissipation ..................•..•.... 1.5W ma'yaffect device reliability. , .. .'
Operating Conditions: TA (Under Bias) = O°Cto + 70°C; Vcc ,,; 5V ± 10%; Vss = OV
D.C. CHARACTERISTICS (Under Operating Conditions)
Symbol Parameter Min Max Units Test Conditions
VIL Input Low Voltage .. -0.5 0.8 V
VIH Input High Voltage (Except XTAL2, RST) 2.0 Vee + 0.5 V
VIH1 Input High Voltage to XTAL2, RST 2;5 Vee + 0.5 V XTAL1 = Vss
VOL Output Low Voltage (Ports 1, 2, 3)' 0.45 V IOL = 1.6 mA
VOL1 Output Low Voltage (Port 0, ALE, PSEN)* 0.45 V IOL = 3.2mA
VOH Output High Voltage (Ports 1, 2, 3, ALE, PSEN) 2.4 V IOH = -80 p,A
VOH1 Output High Voltage (Port 0 in External Bus Mode) 2.4 V IOH = - 400 p,A
IlL Logical 0 Input Current -500 p,A VIN = 0.45V
11L2 Logical 0 Input Current (XTAL2) -3.2 mA VIN = 0.45V
III Input Leakage Current (Port 0) ±10, p,A 0.45,~ VIN~ Vcc
IIH Input Current to RST to Activate Reset 500 p,A VIN < (Vcc - 1.5V)
Icc Power Supply Current 125 mA All Outputs
Disconnected;
EA = VCC
CIO Pin Capacitance 10 pF Test freq = 1 MHz
°NOTE:
Capacitive loading on Ports 0 and' 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports 1
and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make Ho-O
transitions during bus operations. In the worst cases (capacitive loading> 100 pF), the noise pulse on the ALE line may
exceed O.BV. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt
Trigger STROBE input.
7-66
intJ 8051AHP
A.C. CHARACTERISTICS Under Operating Conditions;
Load Capacitance for Port 0, ALE, and PSEN = 100 pF;
Load Capacitance for All Other Outputs = 80 pF
12 MHz Oscillator Variable Oscillator
Symbol Parameter Units
Min Max Min Max
1/TCLCL Oscillator Frequency 3.5 12.0 MHz
TLHLL ALE Pulse Width 127 2TCLCL-40 ns
TAVLL Address Valid to ALE Low 43 TCLCL-40 ns
TLLAX Address Hold after ALE Low 48 TCLCL-35 ns
TLLlV ALE Low to Valid Instr In 233 4TCLCL-100 ns
TLLPL ALE Low to PSEN Low 58 TCLCL-25 ns
TPLPH PSEN Pulse Width 215 3TCLCL-35 ns
TPLIV PSEN Low to Valid Instr In 125 3TCLCL-125 ns
TPXIX Input Instr Hold after PSEN 0 0 ns
TPXIZ Input Instr Float after PSEN 63 TCLCL-20 ns
TPXAV PSEN to Address Valid 75 TCLCL-8 ns
TAVIV Address to Valid Instr In 302 5TCLCL -115 ns
TPLAZ PSEN Low to Address Float 20 20 ns
TRLRH RD Pulse Width 400 6TCLCL-100 ns
TWLWH WR Pulse Width 400 6TCLCL-100 ns
TRLDV RD Low to Valid Data In 252 5TCLCL-165 ns
TRHDX Data Hold after RD 0 0 ns
TRHDZ Data Float after RD 97 2TCLCL-70 ns
TLLDV ALE Low to Valid Data In 517 8TCLCL-150 ns
TAVDV Address to Valid Data In 585 9TCLCL-165 ns
TLLWL ALE Low to RD or WR Low 200 300 3TCLCL-50 3TCLCL+50 ns
TAVWL Address to RD or WR Low 203 4TCLCL-130 ns
TaVWX Data Valid to WR Transition 23 TCLCL-60 ns
TaVWH Data Valid to WR High 433 7TCLCL-150 ns
TWHaX Data Hold after WR 33 TCLCL-50 ns
TRLAZ RD Low to Address Float 20 20 ns
TWHLH RD or WR High to ALE High 43 123 TCLCL-40 TCLCL+40 ns
7-67
8051AHP
EXTERNAL PROGRAM MEMORY READ CYCLE
ALE
PORTO
PORT 2
270279-6
EXTERNAL DATA MEMORY READ CYCLE
ALE
I-----TLLDV----+j
--1.--- TRLRH +----+1
PORTO
PORT 2 P2.0-P2.7 DR AB-A15 FROM DPH AB-A15 FROM PCH
270279-7
7-68
B051AHP
EXTERNAL DATA MEMORY WRITE CYCLE
TWHLH
ALE
..
TLLWL ----~4..-.---TWLWH -------~
TQVWX
I--I-':';;;'~ I--+---TQVWH-----!
PORTO DATA OUT
PORT 2 P2.0-P2.7 OR A8-A 15 FROM DPH A8-A 15 FROM PCH
270279-8
7-69
8051AHP
SERIAL PORt TIMING-SHIFT REGISTER MODE
= ODC to +70DC; Vee = 5V ±10%; Vss = OV;
Test Conditions: TA Load Capacitance = 80 pF
12 MHz Oscillator Variable Oscillator
Symbol Parameter Units
Mil1 Max Min Max
TXLXL Serial Port Clock Cycle Time 1.0 12TCLCL p.s
TOVXH Output Data Setup to Clock Rising 700· 1OTCLCL -133 ns
Edge
TXHOX Output Data Hold after Clock 50 2TCLCL-117 ns
Rising Edge
TXHDX Input Data Hold after Clock Rising 0 0 ns
Edge
TXHDV Clock Rising Edge to Input Data 700 10TCLCL-133 ns
Valid
SHIFT REGISTER TIMING WAVEFORMS
l'4--flLXL~
. CLOCK
-------,
1. . 'OYXH ....t ~;.~a. I
\ X X XI...._--Jxl...._--Jx~_...JX~_...Jxl...._--J1
+--' I
".D' - - I
j I-".D. t
SEI'I
,
WRITE '0 seUf
t
S(TAI
ClE.......
270279-9
7-70
8051AHP
EXTERNAL CLOCK DRIVE
Symbol Parameter MIn Max UnIts
1/TClCl Oscillator Frequency 3.5 12 MHz
TCHCX High Time 20 ns
TClCX low Time 20 ns
TClCH Rise Time 20 ns
TCHCl Fall Time 20 ns
EXTERNAL CLOCK DRIVE WAVEFORM
I - - - - - - T C L C L -------i~
270279-10·
A.C. TESTING INPUT, OUTPUT WAVEFORM
DATA SHEET REVISION HISTORY
The following are the key differences between this
and the -003 version of the 8051AHP data sheet:
1. Data sheet status changed from "Preliminary" to
"Production".
270279-11
2. Revised Maximum Ratings Warning and Data
A.C. Testing: Inputs are driven at 2AV for a Logic "1" and OASV Sheet Status Notice.
for a Logic "0". Timing measurements are made at 2.0V for a
Logic "1" and O.SV for a Logic "0".
The following are the key differences between this
and the -002 version of 8051AHP data sheet:
1. Package Table was added.
Program Verification· 2. Added clearer explanation to DESIGN CONSID-
The program verification' test mode has been elimi- ERATION.
nated on the 8051 AHP. It is not possible to verify the 3. Data Sheet Revision History was added.
ROM contents using this mode, the way EPROM
programmers typically do. Also, the ROM contents
cannot be verified by a program executing out of
external program memory due to the restricted ad-
dressing on the 8051AHP.
7-71
8031 AH/8051 AH
8032AH/8052AH
8751H/8751H-8
EXPRESS
• Extended Temperature Range • Burn-In
The Intel EXPRESS system offers enhancements to the operational specifications of the MCS®-51 family of
microcontrollers. These EXPRESS products are designed to meet the needs of those applications whose
operating requirements exceed commercial standards.
The EXPRESS program includes the commercial standard temperature range with burn-in, and an extended
temperature range with or without burn-in.
With the commercial standard temperature range operational characteristics are guaranteed over the temper-
ature range of O°C to 70°C. With the extended temperature range option, operational characteristics are
guaranteed over the range of - 40°C to + 85°C.
The optional burn-in is dynamic, for a minimum time of 160 hours at 125°C with Vee = 5.5V ± 0.25V, following
guidelines in MIL-STD-883, Method 1015.
Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part number. The
prefixes are listed in Table 1.
For the extended temperature range option, this data sheet specifies the parameters which deviate from their
commercial temperature range limits. The commercial temperature range data sheets are applicable for all
parameters not listed here. This data sheet is valid in conjunction with the commercial data sheet, 270048-
005.
Electrical Deviations from Commercial Specifications for Extended Temperature
Range
D.C. and A.C. parameters not included here are the same as in the commercial temperature range data
sheets.
D.C. CHARACTERISTICS TA = -40°C to + 85°C; Vee = 5V ±10%; Vss = OV
Symbol Parameter Min Max Unit Test Conditions
VIL Input Low Voltage -0.5 0.75 V
VIH Input High Voltage (Except 2.1 Vee + 0.5 V
XTAL2, RST)
lee Power Supply Current:
8051AH,8031AH 135 mA All Outputs
8052AH, 8032AH 175 mA Disconnected;
8751 H, 8751 H-8 265 mA EA = Vee
IIL2 Logic 0 Input Current (XTAL2) -4.0 mA Vin = 0.45V
October 1990
7-72 Order Number: 270007-003
MCS®·51 EXPRESS
Table 1 Prefix Identification
Prefix Package Type Temperature Range Burn·ln
P plastic commercial no
D cerdip commercial no
C ceramic commercial no
N PLCC commercial no
TP plastic extended no
TO . cerdip extended no
TC ceramic extended no
QP plastic commercial yes
QD cerdip commercial yes
QC ceramic commercial yes
LP plastic extended yes
LD cerdip extended yes
LC ceramic extended yes
Please note:
• Commercial temperature range is O°C to 70°C. Extended temperature range is - 40°C to + 85°C.
• Burn-in is dynamic, for a minimum time of 160 hours at 125°C, Vee = 5.5V ±0.25V, following guidelines in
MIL-STD-883 Method 1015 (Test Condition D).
• The following devices are not available in ceramic packages:
8051AH, 8031AH
8052AH, 8032AH
• The following devices are not available in extended temperature range:
8751H,8751H-8
Examples: P8031AH indicates 8031AH in a plastic package and specified for commercial temperature range,
without burn-in. LD8051AH indicates 8051AH in a cerdip package and specified for extended temperature
range with burn-in.
DATA SHEET REVISION HISTORY
The following are the key differences between this and the -002 version of this Express Data Sheet.
1. Data sheet status changed from "Preliminary" to "Production".
2. LCC package offering deleted.
3. Data Sheet Revision History added.
7-73
8751BH
SINGLE-CHIP 8-BIT MICROCOMPUTER
WITH 4K BYTES OF EPROM PROGRAM MEMORY
• Program Memory Lock • Two 16-Bit Timer/Counters
• 128 Bytes Data Ram • 5 Interrupt Sources
• Quick Pulse Programming™ Algorithm • Programmable Serial Channel
• 12.75 Volt Programming Voltage • 64K External Program Memory Space
• Boolean Processor • 64K External Data Memory Space
• 32 Programmable I/O Lines
PO.O-PO.7 P2;O-P2.7
v~
r---------- ~~~~ -----------,I
Vss
-:F
~
AL£-6.~
RST
P1.0-P1.7 P3.0-P3.7
270248-1
Figure 1. 8751BH Block Diagram
October 1990
7-74 Order Number: 270248-004
intJ 8751BH
PACKAGES PIN DESCRIPTIONS
Part Prefix Package Type Vee: Supply voltage.
875iBH P 40-Pin Plastic DIP
Vss: Circuit ground.
N 44-Pin PLCC
Port 0: Port 0 is an 8-bit open drain bidirectional lID
port. As an output port each pin can sink 8 LS TTL
inputs. Port 0 pins that have 1s written to them float,
PI.O vee and in that state can be used as high-impedance
PI.I PO.O (ADO) inputs.
PI.2 PO.I (ADI)
PI.3 PO.2 (AD2)
Port 0 is also the multiplexed low-order address and
PI.4 PO.3 (AD3)
data bus during accesses to external Program and
PO.4 (AD4)
Data Memory. In this application it uses strong inter-
PI.S
nal pullups when emitting 1s, and can source and
PI.6 PO.S (ADS)
sink 8 LS TTL inputs.
PI.7 PO.6 (AD6)
RESET PO.7 (AD7) Port 0 also receives the code bytes during EPROM
(RXD) P3.0 EA/VPP programming, and outputs the code bytes during
(TXD) P3.1 ALE/PROG program verification. External pullups are required
(INTO) P3.2 PSEN during program verification.
(INTI) P3.3 P2.7 (AIS)
(TO) P3.4 P2.6 (AI4) Port 1: Port 1 is an 8-bit bidirectional lID port with
(TI ) P3.S P2.S (AI3) internal pullups. The Port 1 output buffers can sinkl
(ViR) P3.6 P2.4 (AI 2) source 4 LS TTL inputs. Port 1 pins that have 1s
(Ril) P3.7 P2.3 (All) written to them are pulled high by the internal pull-
XTAL2 P2.2 (AIO) ups, and in that state can be used as inputs. As
XTALI P2.1 (A9) inputs, Port 1 pins that are externally being pulled
VSS P2.0 (AS)
low will source current (IlL, on the data sheet) be-
cause of the internal pullups.
270248-2
Pin (DIP) Port 1 also receives the low-order address bytes
during EPROM programming and program verifica-
tion.
Port 2: Port 2 is an 8-bit bidirectional lID port with
internal pullups. The Port 2 output buffers can sinkl
source 4 LS TTL inputs. Port 2 pins that have 1s
PO.4 (AD4) written to them are pulled high by the internal pull-
PO.S (ADS) ups, and in that state can be used as inputs. As
PO.6 (AD6) inputs, Port 2 pins that are externally being pulled
RST PO.7 (AD7) low will source current (IlL, on the data sheet) be-
(RXD) P3.0 EA/Vpp cause of the internal pullups.
NC NC
(TXD) P3.1 ALE/PROG Port 2 emits the high-order address· byte during
(INTO) P3.2 PSEN fetches from external Program Memory and during
(INTI) P3.3 P2.7 (AIS) accesses to external Data Memory that use i6-bit
(TO) P3.4 P2.6 (AI4) addresses (MOVX @DPTR). In this application it
(TI) P3.S P2.S (AI3) uses strong internal pullups when emitting 1s. Dur-
ing accesses to external Data Memory that use 8-bit
addresses (MOVX @Ri), Port 2 emits the contents of
the P2 Special Function Register.
Port 2 also receives the high-order address bits dur-
270248-14 ing EPROM programming and program verification.
Pad (PLCC)
Figure 2. Pin Connections
7-75
8751BH
Port 3: Port 3 is an 8"bit bidirectional I/O port with XTAL2: Output from the inverting oscillator amplifi-
internal pullups. The Port 3 output buffers can sink/ er.
source 4 LS TTL inputs. Port 3 pins that have 1s
written to them are pulled high by the internal pull- OSCILLATOR CHARACTERISTICS'
ups, and in that state can be used as inputs. As
inputs, Port 3 pins that are externally being pulled XTAL 1 and XTAL2 are the input and output, respec-
low will source current (IlL, on the data sheet) be- tively, of an inverting amplifier which can be config-
cause of the pull ups. ' ured for use as an on-chip oscillator, as shown in
Figure 3. Either a quartz crystal or ceramic resonator
Port 3 also serves the functions of various special, may be used. More detailed information concerning
features of the MCS®-51 Family, as listed below: the use of the on-chip oscillator is available in Appli-
cations Note AP-155, "Oscillators for Microcontrol-
Port Pin Alternate Function lers."
P3.0 RXD (serial input port)
To drive the device from an external clock source,
P3.1 TXD (serial output port)
XTAL 1 should be grounded, while XTAL2 is driven,
P3.2 INTO (external interrupt 0) as shown in Figure 4. There are no requirements on
P3.3 INT1 (external interrupt 1) the duty cycle of the external clock signal, since the
P3.4 TO (Thner 0 external input) input to the internal clocking circuitry is through a
P3.5 Tt (Timer 1 external input) divide-by-two flip-flop, but minimum and maximum
P3.6 WR (external data memory write strobe) high and low times specified on the Data Sheet must
P3.7 RD (external data memory read strobe) be observed.
RST: Reset input. A high on this pin for two machine C2
cycles while the oscillator is running resets the de- 1 - -.....--1 XTAL2
vice.
ALE/PROG: Address Latch Enable output pulse for o
latching the low byte of the address during accesses 1--6---1 XTAL 1
to external memory. This pin is also the program
pulse input (PROG) during EPROM programming. ....-------1 vss
In normal operation ALE is emitted at Ii constant
270248-3
rate of 1/6 the oscillator frequency, and may be Cl, C2 = 30 pF ±10 pF for Crystals
used for external timing or clocking purposes. Note, = 40 pF ± 10 pF for Ceramic Resonators
however, that one ALE pulse is skipped during each
access to, external Data Memory. Figure 3. OSCillator Connections
PSEN: Program Store Enable is the Read strobe to
External Program Memory.
When the 8751 BH is executing code from external
EXTERNAL
OSCILLATOR
SIGNAL
-----I XTAL 2
Program Memory, PSEN is activated twice each ma-
chine cycle, except that two PSEN activations are , . . - XTAL·l
skipped during each access to External Data Memo-
ry.
EA/Vpp: External Access enable., EA must be
strapped to Vss in order to enable the device to 270248-4
fetch code from External Program Memory locations
starting at OOOOH up to FFFFH. Note, however, that Figure 4. External Clock Drive Configuration
if either of the Lock Bits are programmed, EA will be
internally latched on' reset.
DESIGN CONSIDERATIONS
EA should be strapped to Vee for internal program If an 8751 BH is replacing an 8751 H in an existing
executions.
design, the user should carefully compare both data
sheets for DC or AC Characteristic differences. Note
This pin also receives the 12.75V programming sup-
that the VIH and IIH specifications for the EA pin dif-
ply voltage (Vpp) during EPROM programming.
fer significantly between the 8751 Hand 8751 BH.
XTAL 1: Input to the inverting oscillator amplifier.
7-76
inter 8751BH
ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. The specifi-
cations .are subject to change without notice.
Ambient Temperature Under Bias .... 0·Cto + 70·C
• WARNING: Stressing the device beyond the "Absolute
Storage Temperature .......... - 6S·C to + 1S0·C Maximum Ratings" may cause permanent damage.
Voltage on EAlVppPin to Vss ... - O.SV to + 13.0V These are stress ratings only. Operation beyond the
Voltage on Any Other Pin to Vss .... -0.5V to + 7V "Operating Conditions" is not recommended and ex-
tended exposure beyond the "Operating Conditions"
Maximum IOL Per 1/0 Pin .......... : ....... 15 rnA may affect device reliability. '
Power Dissipation .......................... 1.5W
(based on PACKAGE heat transfer limitations, not
device power consumption)
Operating Conditions: T A (Under Bias) = o·C to + 70·C; Vee = sv ± 10%; Vss = ov
D.C. CHARACTERISTICS (Under Operating Conditions)
Symbol Parameter Min Max Unit Test Conditions
VIL Input Low Voltage (Except EA) -0.5 O.B V
VIL1 Input Low Voltage EA Vss 0.7 V
VIH Input High Voltage 2.0 Vee+ 0.5 V
(Except XTAL2, RST, EA)
VIH1 Input High Voltage XTAL2, RST 2.S Vee+ 0.5 V XTAL1 = VSS
VIH2 Input HighVoltage to EA 4.S 5.5 V
VOL Output Low Voltage (Note 3) 0.45 V IOL = 1.6 rnA (Note 1)
(Ports 1, 2 and 3)
VOL1 Output Low Voltage (Note 3) 0.45 V IOL = 3.2 rnA (Notes 1, 2)
(Port 0, ALE/PROG, PSEN)
VOH Output High Voltage 2.4 V IOH = -BOp.A
(Ports 1, 2, 3, ALE/PROG and PSEN)
VOH1 Output High Voltage 2.4 V IOH = -400 p.A
(Port 0 in External Bus Mode)
IlL Logical 0 Input Current -1 rnA VIN = O.4SV
(Ports 1, 2, 3 and RST)
hL1 Logical 0 Input Current (EA) -10 rnA VIN = VSS
IIL2 Logical 0 Input Current (XTAL2) -3.2 rnA VIN = 0.45 V XTAL1 = Vss
III Input Leakage Current (Port 0) ±10 p.A 0.45 < VIN < Vee
IIH Logical 1 Input Current (EA) 1 rnA 4.5V < VIN < 5.5V
IIH~ Input Current to RST 500 p.A VIN < (Vee - 1.5V)
to Activate Reset
Icc Power Supply Curr(;jnt 175 rnA All Outputs Disconnected
CIO Pin Capacitance 10 pF Test Freq =1 MHz
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE/PROG
and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins
make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the
ALE/PROG pin may exceed 0.8V. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address
latch with a Schmitt Trigger STROBE input.
2. ALE/PROG refers to a pin on the 8751 BH. ALE refers to a timing signal that is output on the ALE/PROG pin.
3. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port -
Port 0: 26 mA
Ports 1, 2, and 3: 15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
7-77
inter 8751BH
A.C. CHARACTERISTICS (Under Operating Conditions; Load Capacitance for Port 0, ALE/PROG,
= 100 pF; Load Capacitance for All Other Outputs = 80 pF)
and PSEN
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
12 MHzOsc Variable Osclilator
Symbol Parameter Units
Min Max Min Max
1/TCLCL Oscillator Frequency 3.5 12.0 MHz
tLHLL ALE Pulse Width 127 2TCLCL-40 ns
TAVLL Address Valid to ALE Low 43 TCLCL-40 ns
TLLAX Address Hold After ALE Low 48 TCLCL-35 ns
TLLlV ALE Low to Valid Instruction In 233 4TCLCL-100 ns
TLLPL ALE Low to PSEN Low 58 TCLCL-25 ns
TPLPH PSEN Pulse Width 215 3TCLCL-35 ns
TPLIV PSEN Low to Valid Instruction In 125 3TCLCL-125 ns
TPXIX Input Instr Hold After PSEN 0 0 ns
TPXIZ Input Instr Float After PSEN 63 TCLCL-20 ns
T~XAV PSEN to Address Valid. 75 TCLCL-8 ns
TAVIV Address to Valid Instruction In 302 5TCLCL-,115 ns
TPLAZ PSEN Low to Address Float 20 29 . ns
TRLRH AD Pulse Width 400 6TCLCL-100 ns
TWLWH WR Pulse Width 400 6TCLCL-100 ns
TRLDV RD Low to Valid Data In 252 5TCLCL-165 n$
TRHDX Data Hold After RD 0 0 ns
TRHDZ Data Float After RD 97 2TCLCL-70 ns
TLLDV ALE Low to Valid Data In 517 8TCLCL-150 ns
TAVDV Address to Valid Data In 585 9TCLCL-165 ns
TLLWL ALE Low to RD or WR Low 200 300 3TCLCL-50 3TCLCL+50 ns
TAVWL Address to RD or WR Low 203 4TCLCL-130 ns
TOVWX Data Valid to WR Transition 23 TCLCL-60 ns
TOVWH Data Valid to WR High , 433 7TCLCL-'-150 ns
TWHOX Data Held After WR 33 TCLCL-50 ns
TRLAZ RD Low to Address Float 0 0 ns
TWHLH RD or WR High to ALE High 43 123 TCLCL-40 . TCLCL+40 ns
7-78
inter 8751BH
ALE _ _J
PSEN _ _J
TPXAV
PORT a _ _J AO-A7
PORT 2 _ _ _J A8-A15
270248-5
External Program Memory Read Cycle
ALE
PSEN
f------TLLDV 'I
--*--- TRLRH ---~
PORTO INSTR. IN
. PORT2 __ -'l~ _ _ _P2.0-P2.7
__ ~
OR_
A8-A15________
~
FROM DPH J~ __ __
A8-A15 _PCH
FROM ~___
270248-6
External Data Memory Read Cycle
ALE
, I ~
-TLHLL- =t-TWHLH
~
-TLLWL
, TWLWH
j
.... TAVLL -TLLAX- ~ .... t-TWHOX
TOVWH
PORTO
~ FRol~i~R DPL DATA OUT K XAO-A7 FROM PCL INSTR. IN
TAVWL
PORT2 =:) P2.0-P2.7 OR A8-A 15 FROM DPH A8-A15 FROM PCH
270248-7
External Data Memory Write Cycle
7-79
infef 8751BH
SERIAL PORT TIMING - SHIFT REGISTER MODE
TEST CONDITIONS (T A ~ O°C to + 70°C; Vee = 5V ± 10%; VSS = OV; Load Capacitance = 80 pF)
12MHzOsc Variable Oscillator
Symbol Parameter Units
Min Max Min Max
TXLXL Serial Port Clock Cycle Time 1.0 12TCLCL /Ls
TQVXH Output Data Setup to 700 1OTCLCL -133 ns
Clock Rising Edge
TXHQX Output Data Hold After 50 2TCLCL-117 ns
Clock Rising Edge
TXHDX Input Data Hold After 0 0 ns
Clock Rising Edge
TXHDV Clock Rising Edge to 700 1OTCLCL - 133 ns
Input Data Valid
INSTRUCTION I o 2 3 4 5 6 7 8
ALE
CLOCK
OUTPUT DATA \-..;0;....:.1 1.._;"".:.1 \.--.;;......,X 3 X 4 X 5 X 6 X 7 "
\
WRITE TO SBUF SET TI
..
INPUT DATA -----'\.r.~.--w. ~ ~_.~~-_.r.'~~~~~~>=~,..._""V!~~""'~~
I t
CLEAR RI SET RI
270248-8
Shift Register Mode Timing Waveforms
270248-9
External Clock Drive Waveforms
7-80
8751BH
EXTERNAL CLOCK DRIVE AC TESTING INPUT/OUTPUT WAVEFORMS
Symbol Parameter
1/TClCl Oscillator Frequency
Min Max Units
3.5 12 MHz 2.4=>C 2~.
:
0.8
TEST POINTS
2~
0.8
)C
TCHCX High Time 20 ns 0.45 V
270248-10
TClCX low Time 20 ns AC inputs during testing are driven at 2.4V for a logic ·'1" and
0.45V for a logic "0". Timing measurements are made at 2.0V for
TClCH Rise Time 20 ns a logic ··1·· and 0.8V for a logic "0".
TCHCl Fall Time 20 ns
EPROM CHARACTERISTICS amount of time. Even a narrow glitch above that volt-
age level can cause permanent damage to the de-
vice. The Vpp source should be well regulated and
Programming the EPROM free of glitches.
To be programmed, the part must be running with a
4 to 6 MHz oscillator. (The reason the oscillator +5V
needs to be running is that the internal bus is being
used to transfer address and program data to appro-
priate internal registers.) The address of an EPROM
location to be programmed is applied to Port 1 and
pins P2.0 - P2.3 of Port 2, while the code byte to be
programmed into that location is applied to Port O.
The other Port 2 and 3 pins, and RST, PSEN, and
EAlVpp should be held at the "Program"levels indi- 8751 BH
cated in Table 1. AlE/PROG is pulsed low to pro-
gram the code byte into the addressed EPROM lo-
cation. The setup is shown in Figure 5.
Normally EAlVpp is held at a logic high until just
before AlE/PROG is to be pulsed. Then EAlVpp is
raised to Vpp, AlE/PROG is pulsed low, and then Vss
EAlVpp is returned to a valid high voltage. The volt-
age on the EAlVpp pin must be at the valid EAlVpp
270248-11
high level before a verify is attempted. Waveforms
and detailed timing specifications are shown in later Figure 5. Programming the EPROM
sections of this data sheet.
Note that the EAl\Ypp pin must not be allowed to go
above the maximum specified Vpp level for any
7-81
infef 8751BH
Table 1. EPROM Programming Modes
ALEI EAI
MODE RST PSEN P2.7 P2.6 P3.6 P3.7
PROG Vpp
Program Code Data 1 0 O· Vpp 1 0 1 1
Verify Code Data 1 0 1 1 0 .0 1 1
Program Encryption Table 1 0 O· Vpp 1 0 0 1
Use Addresses 0-1 FH
Program Lock x=1 1 0 O· Vpp 1 1 1 1
Bits (LBx) x=2 1 0 O· Vpp 1 1 0 0
Read Signature 1 0 1 1 0 0 0 0
NOTES:
"1" ~ Valid high for that pin
"0" ~ Valid low for that pin
"Vpp" ~ + 12.75V ±0.25V
• ALE/PROG is pulsed low for 100 uS for programming. (Quick· Pulse Programming™)
QUICK-PULSE PROGRAMMINGTM tents of the addressed location will come out on Port
ALGORITHM O. External pullups are required on Port 0 for this
operation. (If the Encryption Array in the EPROM
The 8751 BH can be programmed using the Quick- has been. programmed, the data present at Port 0
Pulse Programming Algorithni for microcontrollers. will be Code Data XNOR Encryption Data. The user
The features of the new programming method are a must know the Encryption Array contents to manual-
lower Vpp (12.75 volts as compared to 21 volts) and ly "unencrypt" the data during verify.)
a shorter programming pulse .. It is possible to pro-
gram the entire 4K Bytes of EPROM memory in less The setup, which is shown in Figure 6, is the same
than 13 seconds with this algorithm as for programming the EPROM except that pin P2.7
is held at a logic low, or may be used as an active
To program the part using the new algorithm, Vpp low read strobe.
must be 12.75 ±0.25 Volts. ALE/PROG is pulsed
low for 100 JLseconds, 25 times. Then, the byte just
programmed may be verified. After programming,
the entire array should be verified. The Program
Lock features are programmed using the same PGM DATA
method, but with the setup as shown in Table 1. The (USE 10K
PULLUPS)
only difference in programming Lock features is that
the Lock features cannot be directly verified. In-
stead, verification of programming is by observing
that their features are enabled. 87518H
VIH
PROGRAM VERIFICATION
If the Lock Bits have not been programmed, the on- VIH1
chip Program Memory can be read out for verifica-
tion purposes, if desired, either during or after the
programming operation. The address of the Program 270248-12
Memory location to be read is applied to Port 1 and
pins P2.0 - P2.3. The other pins should be held at Figure 6. Verifying the EPROM
the "Verify" levels indicated in Table 1. The con-
7-82
intJ 8751BH
PROGRAM MEMORY LOCK To ensure proper functionality of the chip, the inter-
nally latched value of the EA pin must agree with its
The two-level Program Lock system consists of 2 external state.
Lock bits and a 32-byte Encryption Array which are
used to protect the program memory against soft-
ware piracy. ERASURE CHARACTERISTICS
This device is in a plastic package without a window
Encryption Array and, therefore, cannot be erased.
Within the EPROM array are 32 bytes of Encryption
Array that are initially unprogrammed (all 1s). Ellery Reading the Signature Bytes
time that a byte is addressed during a verify, 5 ad-.
dress lines are used to select a byte of the Encryp- The signature bytes are read by the same procedure
tio." Array. This byte is then exclusive-NORed as a normal verification of locations 030H and 031H,
(XNOR) with the code byte, creating an Encrypted except that P3.6 and P3.7 need to be pulled to a
Verify byte. The algorithm, with the array in the un- logic low. the values returned are:
programmed state (all 1s), will return the code in its
original, unmodified form. (030H) = 89H indicates manufactured by Intel
(031 H) = 51 H indicates 8751 BH
It is recommended that whenever the Encryption Ar-
ray is used, at least one. of the Lock Bits be pro-
grammed as well.
Lock Bits
Also included in the EPROM Program Lock scheme
are two Lock Bits which function as shown in
Table 2.
Table 2. Lock Bits and their Features
Lock Bits
LogiC Enabled
LB1 LB2
U U Minimum Program Lock features
enabled. (Code Verify will still be
encrypted by the Encryption
Array)
P U MOVC instructions executed from
external program memory are
disabled from fetching code bytes
from internal memory, EA is
sampled and latched on reset,
and further programming of the
EPROM is disabled
P P Same as above, but Verify is also
disabled
U P Reserved for Future Definition
P = Programmed
U = Unprogrammed
7-83
8751BH
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
(TA= 21°C to 27°C, vee'~ 5.0V ±10%, vss = OV)
Symbol Parameter Min Max Units
Vpp Programming Supply Voltage 12.5 13.0 V
IPP Programming Supply Current 50 rnA
1/TCLCL . Oscillator Frequency 4 6 MHz
TAVGL Address Setup to PROG Low 48TCLCL
TGHAX Address Hold After PROG 48TCLCL
TDVGL, Data Setup to PROG Low 48TCLCL
TGHDX Data Hold After PROG 48TCLCL
TEHSH P2.7 (ENABLE) High to Vpp 48TCLCL
TSHGL Vpp Setup to PROG Low 10 JLsec
TGHSL Vpp Hold After PROG 10 JLsec
TGLGH PROGWidth 90 110 JLsec
TAVQV Address to Data Valid 48TCLCL
TELQV ENABLE Low to Data Valid '48TCLCL
TEHQZ Data Float After ENABLE 0 48TCLCL
TGHGL PROG High to PROG Low 10 . JLsec
PROGRAMMING VERifiCATION
Pl.0-Pl.7
P2.0-P2.3 ----~{=2AD~D~RE~S~S~~==r-----{=2AD~D~RE~S~S=:>----
-TAVQV
PORTO--------1~=~~~:~~~--~~---~JD~A~~~O~U~T::~------
TDVGL
ALEjPROG -------"'1
TGLGH
EA/Vpp ---..A vpp
----~-~::J-.-.TE-H-S-H------------~ TEHQZ
P2.7
----- ~----~
270248-13
EPROM Programming and Verification Waveforms
7-84
8751BH
DATA SHEET REVISION HISTORY
The following are the key differences between this and the -003 version of the 8751 BH data sheet:
1. Data sheet status changed from "Preliminary" to "Production".
2. Revised Maximum Ratings Warning and data sheet status notice.
The following are the key differences between this and the -002 version of 8751 BH data sheet:
1. Status went from ADVANCE INFORMATION to PRELIMINARY.
2. Package Table was added.
3. PLCC pin connections shown.
4. Design Considerations section replaced with reference to previous designs using the 8751 H.
5. Note 3 on maximum current specification was added to DC Characteristics.
6. Table 1 updated to show Read Signature Mode.
7. ERASING THE EPROM paragraph deleted.
.
8. ERASURE CHARACTERISTICS section changed to indicate plastic packages only.
,
9. Signature Bytes added.
10. Data Sheet Revision History was added.
7-85
8751BH
EXPRESS
• Extended Temperature Range • Burn-In
The Intel EXPRESS system offers enhancements to the operational specifications of the MCS®-51 family of
microcontrollers. These EXPRESS products are designed to meet the needs of those applications whose
operating requirements exceed commercial standards.
The EXPRESS program is an extended temperature range with or without burn-in.
With the commercial standard temperature range operational characteristics are guaranteed over the temper-
ature range of O·C to 70·C. With the extended temperature range option, operational characteristics are
guaranteed over the range of - 40·C to + 85·C.
The optional burn-in is dynamic, for a minimum time of 160 hours at 125·C with Vee = 5.5V ±0.25V, following
guidelines in MIL-STD-883, Method 1015.
Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part number. The
prefixes are listed in Table 1.
For the extended temperature range option, this data sheet specifies the parameters which deviate from their
commercial temperature range limits. The commercial temperature range data sheets are applicable for all
parameters not listed here. .
Electrical Deviations from Commercial
Specifications for Extended
Temperature Range
-n.C:-and A.C. parameters not included here are the
same as in the commercial temperature range data
sheets.
D.C. CHARACTERISTICS TA = -40°C to + 85·C; Vee = 5V ±10%;Vss = OV
Symbol Parameter Min Max Unit Test Conditions
VIH Input High Voltage (Except 2.1 Vee + 0.5 V
XTAL2, RST, EA)
January 1989
7-86 Order Number: 270708-001
8751BH EXPRESS
Table 1. Prefix Identification
Prefix Package Type Temperature Range Burn-In
P plastic commercial no
N PLCC commercial no
TP plastic extended no
TN PLCC extended no
LP plastic extended yes
Please note:
• Commercial temperature range is O°C to 70°C. Extended temperature range is - 40·C to + 85·C.
• Burn-in is dynamic, for a minimum time of 160 hours at 125·C, Vee = 5.5V ±0.25V, following guidelines in
MIL-STD-883 Method 1015 (Test Condition D).
Examples: N8751 BH indicates 8751 BH in a PLCC package and specified for commercial temperature range,
without burn-in. LP8751 BHindicates 8751 BH in a plastic package and specified for extended temperature
range with burn-in.
7-87
8752BH
SINGLE~CHIP 8~BIT MICROCOMPUTER
WITH 8K BYTES OF EPROM PROGRAM MEMORY
• 2-Bit Program Memory Lock • 6 Interrupt Sources
• 256 Bytes Data Ram • Prograriuriable Serial Channel
• Quick Pulse Programming™ Algorithm ill Separate Transmit/Receive Baud Rate
• 12.75 Volt Programming Voltage Capability
• Boolean Processor • 64K External Program Memory Space
• 32 Programmable I/O Lines • 64K External Qata Memory Space
• Three 16-Blt Timer/Counters
PO.O- PO.7 P2.0-P2.7
v' r - - - - - - - - - -
~ ~~~~
- - - - .- - - -
. ~ ~ ~ ,
Vss PORT 0 PORT 2
-t' DRIVERS ORIVERS
I'ml
ALE/PImll
EA/Vpp
RST
P1.0-P1.7 P3.0-P3.7
270429-1
Figure 1. Block Diagram
.October 1990
7·88 Order Number: 270429-003
intJ 8752BH
PACKAGES Port 0 is also the multiplexed low-order address and
data bus during accesses to external Program and
Part Prefix Package Type Data Memory. In this application it uses strong inter-
8752BH P 40-Pin Plastic DIP nal pullups when emitting 1s, and can source and
D 40-Pin CERDIP sink 8 LS TTL inputs.
N 44-Pin PLCC
Port 0 also receives the code bytes during EPROM
programming, and outputs the code bytes during
(12) P1.D program verification. External pull ups are required
(T2EX) Pl.! during program verification.
Pl.2 PO.I (ADI)
PI.3 PO.2 (AD2)
·PI .• PO.3 (AD3)
Port 1: Port 1 is an 8-bit bidirectional I/O port with
PI.S PO.-4 (AD4) internal pullups. The Port 1 output buffers can sink/
P1.6 7 . 34 PO.S (ADS) source 4 LS TTL fnputs. Port 1 pins that have 1s
PO.S (AD6)
PO.7 (AD7)
written to them are pulled· high by the internal pull-
fi./Vpp ups, and in that state can be used as inputs. As
AL.E/PROG inputs, Port 1 pins that are externally being pulled
PSEN
low will source current (IlL, on the data sheet) be-
P2.7 (AI5)
(TO) Pl.'" 27 P2.& (A.t-4) cause of the internal pullups.
(Tl) P3.S 26 P2.S (AI3)
(WR) P3.& 16 P2.4 (A12) Port 1 also receives the low-order address bytes
(iffi) Pl.7 17 P2.3 (~11)
P2.2 (AID)
during EPROM programming and program verifica-
)(TALI ·22 P2.1 (A9) tion.
21 P2.D (AS)
'-----' In addition, P1.0 and P1.1 serve the functions of the
270429-2
following special features of the MCS®-51 Family:
DIP
Port Pin Alternate Function
P1.0 T2 (Timer/Counter 2 External Input)
P1.1 T2EX (Timer/Counter 2
INDEX
CORNER Capture/Reload Trigger)
V':f-'t-"1-'t"';'-';~~~~
P1.5 PD ••
PI.S
Port 2: Port 2 is an 8-bit bidirectional I/O port with
internal pullups. The Port 2 output buffers can sink/
source 4 LS TTL inputs. Port 2 pins that have 1s
NC
written to them are pulled high by the internal pull~
(TXD) Pl.t ups, and in that state can be used as inputs. As
(iNTO) Pl.2 inputs, Port 2 phis that are externally being pulled
(iNfi) Pl.3
(TO) Pl ••
low will source current (IlL, on the data sheet) be-
(Tl) P3.5 cause of the internal pullups.
1819202122232-425262728
Port 2 emits the high-order address byte during
fetches from external Program Memory and during
accesses to external Data Memory that use 16-bit
270429-15 addresses (MOVX @DPTR). In this ·application it
PLCC uses strong internal pullups when emitting 1s. Dur-
ing accesses to external Data Memory that use 8-bit
Figure 2. Pin Connections addrE;!sses (MOVX @Ri), Port 2 emits the contents of
the P2 Special Function Register.
PIN DESCRIPTION Port 2 also receives the high·order address bits dur-
ing EPROM programming and program verification.
Vee: Supply voltage. ,
Port 3: Port 3 is an 8-bit bidirectional I/O port with
Vss: Circuit ground. internal pullups. The Port 3 output buffers can sink/
source 4 LS TTL inputs. Port 3 pins that have 1s
Port 0: Port 0 is an 8-bit open drain bidirectional I/O written to them are pulled high by the internal pull·
port. As an output port each pin can sink 8 LS TTL ups, and in that state can be used as inputs. As
inputs. Port 0 pins that have 1s written to them float, inputs, .Port 3 pins that are externally being pulled
and in that state can be used as high-impedance low will source current (IlL, on the data sheet) be-
inputs. cause of the pullups.
7-89
inter 8752BH
Port 3 also serves the functions of various special may be used. More detailed information concerning
features of the MCS®-51 Family, as listed below: the use of the on-chip oscillator is available in Appli-
cations Note AP-155, "Oscillators for Microcontrol-
Port Pin Alternate Function lers."
P3.0 RXD (serial input port)
P3.1 TXD (serial output port) To drive the device from an external clock source,
P3.2 INTO (external interrupt 0) XTAL 1 should be grounded, while XTAL2 is driven,
PS.S· INT1 (external interrupt 1) as shown in Figure 4. There are no requirements on
P3.4 TO (Timer 0 external input) the duty cycle of the external clock signal, since the
PS.5 I!JTimer 1 external input) input to the internal clocking circuitry is through .a
P3.S WR (external data memory write strobe) divide-by-two flip-flop, but minimum and maximum
PS.7 RD (external data memory read strobe) high and low times specified on the Data Sheet must
be observed.
RST: Reset input. A high on this pin for two machine
cycles while the oscillator is r!Jnning resets the de-
~
2
vice. . 0 XTAL2
ALE/PROG: Address Latch Enable output pulse for
Cl
latching the low byte of the address during accesses XTAL 1
to external memory. This pin is also the program
Vss
pulse input (PROG) during EPROM programming on
the 8752BH. 270429-3
C1. C2 = 30 pF ± 10 pF for Crystals
= 40 pF ± 10 pF for Ceramic Resonators
In .normal operation ALE is emitted at a constant
rate of 1/S the oscillator frequency, and may be Figure 3. Oscillator Connections
used for external timing or clocking purposes. Note,
however, that one ALE pulse is skipped during each
access to external Data Memory. EXTERNAL
OSCILLATOR - - - - I XTAL 2
PSEN: Program Store Enable is the Read strobe to SIGNAL
External Program Memory.
XTAL 1
When the device is executing code from external Vss
Program Memory, PSEN is activated twice each ma-
chine cycle, except that two PSEN activations are
270429-4
skipped during each access to External Data Memo-
ry. Figure 4. External Clock Drive Configuration
EA/Vpp: External Access enable. EA must be
strapped to Vss in order to enable the device to DESIGN CONSIDERATIONS
fetch code from External Program Memory locations
starting at OOOOH up to FFFFH. Note, however, that Exposure to light when the 8752BH is in operation
if either of the Lock Bits are programmed, EA will be may cause logic errors. For this reason, it is suggest-
internally latched on reset. ed that an opaque label be placed over the window
of the 8752BH when the die is exposed to ambient
EA should be strapped to Vee for internal program light.
executions.
Due to a timing problem in the Timer/Counter 2 in-
This pin also receives the 12.75V programming sup- terrupt circuitry, tlie device may vector to location
ply voltage (Vpp) during EPROM programming. OSH (External Interrupt 0 vector address). It happens
when· a low priority interrupt has been in progress for
XTAL 1: Input to the inverting oscillator amplifier.
either 1 or 2 machine cycles and Timer/Counter 2
XTAL2: Output from the inverting oscillator amplifi- generates a priority 1 interrupt. Therefore, Timer/
er. Counter 2 should only be assigned priority level 0..
. OSCILLATOR CHARACTERISTICS If an 8752BH is replacing an 8751 H in an existing
design, the user should carefully compare both data
XTAL1 and XTAL2 are the input and output, respec- sheets for DC or AC characteristic differences. Note
tively, of an inverting amplifier which can be config- that the VIH and IIH specifications for the EA pin dif-
ured for use as an on-chip oscillator, as shown in fer significantly between the 8751H and 8752BH.
Figure 3. Either a quartz crystal or ceramic resonator
7-90
8752BH
ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. The specifi-
cations are subject to change without notice.
AmbientTemperature Under Bias ...... O°C to 70°C
• WARNING: Stressing the device beyond the "Absolute
Storage Temperature .......... - 65°C to + 150°C Maximum Ratings" may cause permanent damage.
Voltage on EAlVpp Pin to Vss ... -0.5V to + 13.0V These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and ex-
. Voltage on Any Other Pin to Vss .... -0.5V to + 7V tended exposure beyond the "Operating Conditions"
Maximum IOL Per I/O Pin .................. 15 mA may affect device reliability.
Power Dissipation .......................... 1.5W
(based on PACKAGE heat transfer limitations, not
device power consumption)
Operating Conditions: T A (under Bias) = O°C to + 70°C; Vee = 5V ± 10%; VSS = ov
D.C. CHARACTERISTICS (Under Operating Conditions)
Symbol Parameter Min Max Units Test Conditions
VIL Input Low Voltage (Except EA) -0.5 O.S V
VIL1 Input Low Voltage EA Vss 0.7 V
VIH Input High Voltage 2.0 Vee+ 0.5 V
(Except XTAL2, RST, EA) ~
VIH1 Input High Voltage XTAL2, RST 2.5 Vce+ 0.5 V XTAL1 = Vss
VIH2 Input High Voltage to EA 4.5 5.5 V
VOL Output Low Voltage (Note 3) 0.45 V IOL = 1.6 mA (Note 1)
(Ports 1, 2 and 3)
VOl1 Output Low Voltage (Note 3) 0.45 V IOL = 3.2 mA (Note 1, 2)
(Port 0, ALE/PROG, PSEN)
VOH Output High Voltage 2.4 V IOH = -SO p-A
(Ports 1, 2, 3, ALE/PROG and PSEN)
VOH1 Output High Voltage 2.4 V IOH = -400 p-A
(Port 0 in External Bus Mode)
IlL Logical 0 Input Current -500 p-A VIN = 0.45V
(Ports 1. 2. 3 and RST)
IIL1 Logical 0 Input Current (EA) -10 mA VIN = Vss
500 p-A
IIL2 Logical 0 Input Current (XTAL2) -3.2 mA VIN = 0.45VXTAL1 = Vss
III Input Leakage Current (Port 0) ±10 p-A 0.45 < VIN < Vee
IIH Logical 1 Input Current (EA) 1 mA 4.5V < VIN < 5.5V
IIH1 Input Current to RST 500 p-A VIN < (Vee - 1.5V)
to activate Reset
Ice Power Supply Current 175 mA All Outputs Disconnected
CIO Pin Capacitance 10 pF Test freq = 1 MHz
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE/PROG
and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins
make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the
ALE/PROG pin may exceed O.SV. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address
latch with a Schmitt Trigger STROBE input.
2, ALE/PROG refers to a pin on the device. ALE refers to a timing signal that is output on the ALE/PROG pin.
3. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per S-bit port-
Port 0: 26 mA
Ports 1, 2. and 3: 15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
7-91
intJ 8752BH
EXPLANATION OF THE AC SYMBOLS L:Logic level LOW, or ALE
P:PSEN
Each timing symbol has 5 characters; The first char- Q:Output data
acter is always a 'T' (stands for time). The other R:RD signal
characters, depending on their positions, stand for T:Time
the name of a signal or the logical status of that V:Valid
signal. The following is a list of all the characters and W:WR signal
what they stand for. X:No longer a valid logic level
Z:Float
A:Address
C:Clock For example,
D:lnput Data
H:Logic level HIGH . TAVLL = Time from Address Valid to ALE Low.
1:lnstruction (program memory contents) TLLPL = Time from ALE Low to PSEN Low.
A.C. CHARACTERISTICS (Under Operating Conditions; Load Capacitance for Port 0, ALE/PROG,
and PSEN = 100 pF; Load Capacitance for All Other Outputs = 80 pF) ,
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
12MHzOsc Variable Oscillator
Symbol Parameter Units
Min Max Min Max
1ITCLCL Oscillator Frequency 3.5 12.0 MHz
TLHLL ALE Pulse Width 127 2TCLCL-40 ns
TAVLL Address Valid to ALE Low 43 TCLCL-40 ns
TLLAX Address Hold After ALE Low 48 TCLCL-35 ns
TLLlV ALE Low to Valid Instruction In 233 4TCLCL-100 ns
TLLPL ALE Low to PSEN Low 58 TCLCL-25 ns
TPLPH PSEN Pulse Width 215 3T.CLCL-35 ns
TPLIV PSEN Low to Valid Instruction In 125 3TCLCL-125 rlS
TPXIX Input Instr Hold After PSEN 0 0 ns
TPXIZ Input Instr Float After PSEN 63 TCLCL-20 ns
TPXAV PSEN to Address Valid 75 TCLCL-8 ns
TAVIV Address to Valid Instruction In 302 5TCLCL-115 ns
TPLAZ PSEN Low to Address Float. 20 20 ns
TRLRH RD Pulse Width 400 6TCLCL-100 ns
TWLWH WR Pulse Width 400 6TCLCL-100 ns
TRLDV RD Low to Valid Data In 252 5TCLCL-165 ns
TRHDX Data Hold After RD 0 0 ns
TRHDZ Data Float After RD 97 2TCLCL-70 ns
TLLDV ALE Low to Valid Data In 517 8TCLCL-150 ns
TAVDV Address to Valid Data In 585 9TCLCL-165 ns
TLLWL ALE Low to RD or WR Low 200 300 3TCLCL-50 3TCLCL+50 ns
TAVWL Address to RD or WR Low 203 4TCLCL-130 ns
TaVWX Data Valid to WR Transition 23 TCLCL-60 ns
TQVWH Data Valid to WR High 433 7TCLCL-150 ns
TWHQX Data Held After WR 33 TCLCL-50 ns
TRLAZ RD Low to Address Float 0 0 ns
TWHLH RD or WR High to ALE High 43 123 TCLCL-40 TCLCL+40 ns
7-92
8752BH
ALE
---'
PSEN
---' TPXAV
PORT 0 AO-A7
---'
PORT 2 _ _ _J AB - A15
270429-5
External Program Memory Read Cycle
ALE
PSEN
1 - - - - - - TLLDV 'I
--~--- TRLRH
RD
PORTO INSTR. IN
PORT2 __ n~ ______P2.0-P2.7 OR__
~~~
AB-A15__ ________
FROM DPH
~ ~ J~ ____________
AB-A15 FROM PCH _ _
270429-6
External Data Memory Read Cycle
ALE
, I /
-TLHLL- i==t-TWHLH
-TLLWL
, TWLWH
I
- TAVLL -TlLAX- ~
TOVWH
- -TWHOX
PORTO
~ FROJ'Wj'~~ DPL DATA OUT AO-A7 FROM PCl INSTR. IN
TAVWL
PORT2
~ P2.0-P2.7 OR AB-A 15 FROM DPH AB-A15 FROM PCH
270429-7
External Data Memory Write Cycle
7-93
8752BH
SERIAL PORT TIMING-SHIFT REGISTER MODE
TEST CONDITIONS TA = O'C to + 70'C; Vee = 5V ± 10%; Vss = OV; Load Capacitance = 80 pF
12 MHz Osc Variable Oscillator
Symbol Parameter Units
Min Max Min Max
TXLXL Serial Port Clock Cycle Time 1.0 12TCLCL f-Ls
TOVXH Output Data Setup to 700 1OTCLCL - 133 ns
Clock Rising Edge
TXHQX Output Data Hold After 50 2TCLCL-117 ns
Clock Rising Edge
TXHDX Input Data Hold After 0 0 ns
Clock Rising Edge
TXHDV Clock Rising Edge to 700 1OTCLCL - 133 ns
Input Data Valid
INSTRUCTION I 0 2 3 4 5 6 7 8
ALE
CLOCK
OUTPUT DATA X 3 X 4 X 5 X 6 X 7 7
I t
WRITE TO SBUF" SET TI
INPUT DATA
I
CLEAR RI
270429-8
Shift Register Mode Timing Waveforms
270429-9
External Clock Drive Waveforms
7-94
8752BH
EXTERNAL CLOCK DRIVE A.C. TESTING INPUT/OUTPUT WAVEFORMS
Symbol
TCHCX
Parameter
1/TClCl Oscillator Frequency 3.5
High Time
Min Max Units
20
12 MHz
ns
2.4=>(
0.45V
.
2.0
0.8 TEST POINTS
.2.0
0.8:
x= .'
270429-10
TClCX low Time 20 ns AC inputs during testing are driven at 2.4V for a logic "1" and
0,45V for a logic "0". Timing measurements are made at2.0V for
TClCH Rise Time 20 ns a logic "1" and 0.8V for a logic "0".
TCHCl Fall Time 20 ns
EPROM CHARACTERISTICS gram" levels indicated in Table 1. AlE/PROG is
pulsed low to program the code byte into the ad-
Table 1 shows the logic levels for programming the dressed EPROM location. The setup is shown in Fig-
Program Memory, the Encryption Table, and the ure 5.
lock Bits and for reading the signature bytes.
Normally EAlVpp is held at a logic high until just
before AlE/PROG is to be pulsed. Then EAlVpp is
Programming the EPROM raised to Vpp, AlE/PROG is pulsed low, and then
EAlVpp is returned to a valid high voltage. The volt-
To be programmed, the 8752BH must be running age on the EAlVpp pin must be at the valid EAlVpp
with a 4 to 6 MHz oscillator. (The reason the oscilla- high level before a verify is attempted. Waveforms
tor needs to be running is that the internal bus is and detailed timing specifications are shown in later
being used to transfer address and program data to sections of this data sheet.
appropriate internal registers.) The address of an
EPROM location to be programmed is applied to Note that the EAlVpp pin must not be allowed to go
Port 1 and pins P2.0 - P2.4 of Port 2, while the code above the maximum specified Vpp level for any
byte to be programmed into that location is applied amount of time. Even a narrow glitch above that volt-
to Port O. The other Port 2 and 3 pins, and RST, age level can cause permanent damage to .the de-
PSEN, and EAlVpp should be held at the "Pro- vice. The Vpp source should be well regulated and
free of glitches.
+5V
ALE/PROG 25 100 " . PULSES TO GNO
8752BH
.--_---1XTAL2
'--+-+--1XTAL 1
Vss
270429-11
Figure 5. Programming the EPROM
7-95
intJ 8752BH
Table 1. EPROM Programming Modes
ALEI EAt
MODE RST PSEN P2.7 P2.6 P3.6 P3.7
PROG Vpp
Program Code Data 1 0 O' Vpp 1 0 1 1
Verify Code Data 1 0 1 1 0 0 1 1
Program Encryption Table 1 0 O' Vpp 1 0 0 1
Use Addresses 0-1 FH
Program Lock x=1 1 0 O' Vpp 1 1 1 1
Bits (LBx) x=2 1 0 O· Vpp 1 1 0 0
Read Signature 1 0 1 1 0 0 0 0
NOTES:
"1" = Valid high for that pin
"0" = Valid low for that pin
"Vpp" = + 12.75V ±0.25V
*ALE/PROG is pulsed low for 100 uS for programming. (Quick-Pulse Programming™)
QUICK-PULSE PROGRAMMINGTM PROGRAM VERIFICATION
ALGORITHM
If the Lock Bits have not been programmed, the on-
The 8752BH can be programmed using the Quick- chip Program Memory can be read out for verifica-
Pulse Programming™ Algorithm for microcontrol- tion purposes, if desired, either during or after the
lers. The features of the new programming method programming operation. The address of the Program
are a lower Vpp (12.75 volts as compared to 21 Memory location to be read is applied to Port 1 and
volts) and a shorter programming pulse. It is possi- pins P2.0 - P2.4. The other pins should be held at
ble to program the entire 8K Bytes of EPROM mem- the "Verify" levels indicated in Table 1. The con-
ory in less than 25 seconds with this algorithm! tents of the addressed location will come out on Port
O. External pullups are required on Port 0 for this
To program the part using the new algorithm, Vpp operation. (If the Encryption Array in the EPROM
must be 12.75.. ± 0.25 Volts. ALE/PROG is pulsed has been programmed, the data present at Port 0
low for 100 p,seconds, 25 times as shown in Figure will be Code Data XNOR Encryption Data. The user
6. Then, the byte just programmed may be verified. must know the Encryption Array contents to manual-
After programming, the entire array should be veri- ly "unencrypt" the data during verify.)
fied. The Program Lock features are programmed
using the same method, but with the setup as shown The setup, which is shown in Figure 7, is the same
in Table 1. The only difference in programming Lock as for programming the EPROM except that pin P2.7
features is that the Lock features cannot be directly is held at a logic low, or may be used as an active
verified. Instead, verification of programming is by low read strobe.
observing that their features are enabled.
1 ~1'------25 PULSES
'I
·ALE/PROG:~-----wwr--
'------'
'- 10Jls M1N111••-~-:-1.::c00,=,J.I.~s==---_·1
~ :tl0Jls
-----:...,
ALE/PROG:
011-- _---'nL..-_---Inl---_ 270429-12
Figure 6. PROG Waveforms
7-96
inter 8752BH
270429-13
Figure 7. Verifying the EPROM
PROGRAM MEMORY LOCK Table 2. Lock Bits and their Features
Lock Bits
The two-level Program Lock system consists of 2 Logic Enabled
Lock bits and a 32-byte Encryption Array which are LB1 LB2
used to protect the program memory against soft-
ware piracy. U U Minimum Program Lock features
enabled. (Code Verify will still be
encrypted by the Encryption
Array)
ENCRYPTION ARRAY
P U MOVC instructions executed from
Within the EPROM array are 32 bytes of Encryption external program memory are
Array that are initially unprogrammed (all 1s). Every disabled from fetching code bytes
time that a byte is addressed during a verify, 5 ad- from internal memory, EA is
dress lines are used to select a byte of the Encryp- sampled and latched on reset,
tion Array. This byte is then exclusive-NORed and further programming of the
(XNOR) with the code byte, creating an Encrypted EPROM is disabled
Verify byte. The algorithm, with the array in the un-
programmed state (all 1s), will return the code in its P P Same as above, but Verify is also
original, unmodified form. disabled
U P Reserved for Future Definition
It is recommended that whenever the Encryption Ar-
ray is used, at least one of the Lock Bits be pro- P -- Programmed
U = Unprogrammed
grammed as well.
LOCK BITS READING THE SIGNATURE BYTES
Also included in the EPROM Program Lock scheme The signature bytes are read by the same procedure
are two Lock Bits which function as shown in Table as a normal verification of locations 030H and 031 H,
2. except that P3.6 and P3.7 need to be pulled to a
logic low. The values returned are:
Erasing the EPROM also erases the Encryption Ar- (030H) = 89H indicates manufactured by Intel
ray and the Lock Bits, returning the part to full un- (031 H)' = 52H indicates 8752BH
locked functionality.
To ensure proper functionality of the chip, the inter-
nally latched value of the EA pin must agree with its
external state.
7-97
infef 8752BH
ERASURE CHARACTERISTICS this type of exposure, it is suggested that an opaque
label be placed over the window.
Erasure of the EPROM begins to occur when the
8752BH is exposed to light with wavelengths shorter The recommended erasure procedure is exposure
than approximately 4,000 Angstroms. Since sunlight to ultraviolet light (at 2537 Angstroms) to an integrat-
and fluorescent lighting have wavelengths in this ed dose of at lease 15 W-sec/cm. Exposing the
range, exposure to these light sources over an ex- EPROM to an ultraviolet lamp of 12,000 p.W/cm rat-
tended time (about 1 week in sunlight, or 3 years in ing for 30 minutes, at a distance of about 1 inch,
room-level fluorescent lighting) could cause inadver- should be sufficient.
tent erasure. If an application subjects the device to
Erasure leaves the array in an all 1s state.
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
2rc, Vee = 5.0V ±10%, vss = OV)
(TA = 21°C to
Symbol Parameter Min Max Units
Vpp Programming Supply Voltage 12.5 13.0 V
Ipp Programming Supply Current 50 mA
1/TCLCL Oscillator Frequency 4 6 MHz
TAVGL Address Setup to PROG Low 48TCLCL
TGHAX Address Hold After PROG 48TCLCL
TDVGL Data Setup to PROG Low 48TCLCL
TGHDX Data Hold After PROG 48TCLCL
TEHSH P2.7 (ENABLE) High to Vpp 48TCLCL
TSHGL Vpp Setup to PROG Low 10 p.s
TGHSL Vpp Hold After PROG 10 p.s
TGLGH PROGWidth 90 110 p.s
TAVOV Address to Data Valid 48TCLCL
TELOV ENABLE Low to Data Valid 48TCLCL
TEHOZ Data Float After ENABLE 0 48TCLCL
TGHGL PROG High to PROG Low 10 p.s
PROGRAMMING VERIFICA nON
PLO-Pl.7
P2.0-P2.4 -----i=:!A~DD~RE~S~S~~=:)-----t=~AD~D~RE~SS=::>----
-TAVQV
PORTO--~--~=~~~:~~t------~~~C:l-------
TDVGl
AlE/PROG - - - - -....i
TEHQZ
}
270429-14
EPROM Programming and Verification Waveforms
7-98
8752BH
OATA SHEET REVISION HISTORY
The following are the key differences between this and the -002 version of the 8752BH data sheet.
1. Data sheet status changed from "Preliminary" to "Production".
2. Deleted LCC Package offering.
3. Revised Maximum Ratings warning and data sheet status notice.
The following are the key differences between this and the -001 version of the 8752BH data sheet.
1. PLCC pin connection diagram was added.
2. Package table was added.
3. Timer/Counter 2 Design Consideration was added.
4. Design Consideration was added referring to previous designs using the 8751 H.
5. Note 3 was added to DC Characteristics to explain the maximum current specification.
6. Signature Byte was corrected.
7. Data Sheet Revision History was added.
7-99
8752BH
EXPRESS
• Extended Temperature Range • Burn-In
The Intel EXPRESS system offers enhancements to the operational specifications of the MCS®-51 family of
microcontrollers. These EXPRESS products are designed to meet the needs of those applications whose
operating requirements exceed commercial standards.
The EXPRESS program includes the commercial standard temperature range with burn-in, and an extended
temperature range with or without burn-in.
With the commercial standard temperature range operational characteristics are guaranteed over the temper-
ature range of O·C to 70·C. With the extended temperature range option, operational characteristics are
guaranteed over the range of - 40·C to + 85·C.
The optional burn-in is dynamic, for a minimum time of 160 hours at 125·C with Vee = 5.5V ± 0.25V, following
guidelines in MIL-STD-883, Method 1015.
Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part number. The
prefixes are listed in Table 1.
For the extended temperature range option, this data sheet specifies the parameters which deviate from their
commercial temperature range limits. The commercial temperature range data sheets are applicable fOr all
parameters not listed here.
Electrical Deviations from Commercial
Specifications for Extended
Temperature Range
D.C. and A.C. parameters not included here are the
same as in the commercial temperature range data
sheets.
D.C. CHARACTERISTICS TA = -40·Cto + 85·C; Vee = 5V ±10%;Vss = ov
Symbol Parameter Min Max Unit Test Conditions
VIH Input High Voltage (Except 2.1 Vee + 0.5 V
XTAL2, RST, EA)
January 1989
7-100 Order Number: 270650-002
intJ 8752BH EXPRESS
Table.1. Prefix Identification
Prefix Package Type Temperature Range Burn-In
P plastic commercial no
D cerdip commercial no
N PLCC commercial no
R LCC commercial no
TD cerdip extended no
OP plastic commercial yes
LD cerdip extended yes
Please note:
• Commercial temperature range is O°C to 70°C. Extended temperature range is - 40°C to + 85°C.
• Burn-in is dynamic, for a minimum time of 160 hours at 125°C, Vee = 5.5V ± 0.25V, following guidelines in
MIL-STD-883 Method 1015 (Test Condition D).
Examples: N8752BH indicates 8752BH in a PLCC package and specified for commercial temperature range,
without burn-in. LD8752BH indicates 8752BH in a cerdip package and specified for extended temperature
range with burn-in.
DATA SHEET REVISION SUMMARY
The following are the key differences between this and the -001 version of the 8752BH Express data sheet:
1. VIH parameter changed to read "(Except XTAL2, RST, EA)".
2. OD option removed.
3. Data Sheet Revision Summary added.
7-101
8051 KB/8052KB
MCS®-51 FAMILY
8-BIT MICROCONTROLLER
• Four 15 mA LED Drivers
• Boolean Processor
• High Performance HMOS Process
• Bit-Addressable RAM
• Internal Timers/Event Counters
• Programmable -Full Duplex Serial
• 2-Level Interrupt Priority Structure
•
Channel
• 32 I/O Lines (Four 8-Bit Ports)
•
111 Instructions (64 Single-Cycle)
• 64K Program Memory Space 64K Data Memory Space
The MCS®-51 products are optimized for control applications. Byte-processing and numerical operations on
small data structures are facilitated by a variety of fast addressing modes for accessing the internal RAM. The
instruction set provides a convenient menu of 8-bit arithmetic instructions, including multiply and divide instruc-
tions. Extensive on-chip support is provided for one-bit variables as a separate data type, allowing direct bit
manipulation and testing in control and logic systems that require Boolean processing.
Internal Memory Timersl
Device Interrupts
Program Data Event Counters
8052KB 8Kx8ROM 256x8 RAM 3 x 16-Bit 6
8051KB 4Kx8 ROM 128x8 RAM 2 x 16-Bit 5
May 1990
7-102 Order Number: 270872-001
inter S051 KB/S052KB
PO,O-PO 7 P2.~P2.7
',:tf#Mtt;-- - - - ----- - - - - I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
PIE. ~
~E ~ ~~ljL__~~~~~________~~~~~____~
_ AND~;
... CONTROL ~ l;ll'v------,..--------------------..--,------,~--.Il _ _ ___J
RST~ ;«
I
I
I
I
I
~:;::;.:;::;:.,.,,.J ________ )
L
ITAL 1
Pl.0-P1.1 P3.0-P3.7
270872-1
Figure 1. MCS®-51 Block Diagram
PACKAGES Port 0: Port 0 is an a-bit open drain bidirectional 110
port. As an output port each pin can sink a LS TTL
Part Prefix Package Type inputs.
a051KB P 40-Pin Plastic DIP
D 40-Pin CERDIP Port 0 pins that have 1s written to them float, and in
N 44-Pin PLCC that state can be used as high-impedance inputs.
a052KB P 40-Pin Plastic DIP
D 40-Pin CERDIP Port 0 is also the multiplexed low-order address and
data bus during accesses to external Program and
N 44-Pin PLCC
Data Memory. In this application it uses strong inter-
nal pullups when emitting 1s and can source and
sink a LS TTL inputs.
PIN DESCRIPTIONS
Port 0 also outputs the code bytes during program
Vee: Supply voltage. verification of the ROM code. External pullups are
required during program verification.
Vss: Circuit ground.
7-103
8051KB/8052KB
8052 ONLY
L~,:: P1.0
Pl.l
P1.2
P1.3
38
37
Vee
PO.O
PO.1
PO.2
ADO
AD1
AD2
INDEX
CORNER
P1.4 PO.3 ADJ
P1.S PO.4 AD4 P1.5
P1.6 PO.S ADS Pl.6 ~~~ PO.5
P1.7 PO.6 A06 Pl.7 [E po.,
RST PO.7 AD7 RST [}! PO.7
RXD P3.0 31 EAtVoo P3.D D~ Ell
TXD P3.1 ALE NC D~ NC
INTO P3.2 PSEN P3.l D~ ALE
INn P3.3 P2.7 A1S P3.2 U~ liSEN
TO P3.4 P2.6A14 P3.3 ~E P2.7
n P3.5 P2.S A13
P3.4 2~ ~ ~~~ P2.6
WR PJ.6 16 P2.4 A12
. AD P3.7 17 P2.3 A11
P3.5 )f;~.., .-, ,..-. ,..., ....... -, ,. . ., .......... ,..., r"~~'F P2.5
XTAL2 P2.2 A10
:!: :~: :~: :;;;: :~: :~: :;t: :~: :~: :~: :~:
18
XTAL1 P2.1 A9
Vss P2.D A8
270872-2
Pin Pad
Figure 2. MCS®-51 Connections
Port 1: Port 1 is an 8-bit bidirectional 110 port with ing accesses to external Data Memory that use 8-bit
internal pullups. The Port 1 output buffers can sink/ addresses (MOVX @Ri), Port 2 emits the contents of
source 4 LS TTL inputs. Port 1 pins that have 1s the P2Speciai Function Register.
written to them are pulled high by the internal pull-
ups, and in that state can be used as inputs. As Port 2 also receives the high-order address bits dur-
inputs, Port 1 pins that are externally being pulled ing program verification of the ROM code.
low will source. current (IlL on the data sheet) be-
cause of the internal pullups. Port 3: Port 3 is an 8-bit bidirectional I/O port with
internal pull ups. The Port 3 output buffers can sink/
Port 1 also receives the low-order address bytes source 4 LS TTL inputs. Port 3 pins that have 1s
during program verification of the ROM code. written to them are pulled high by the internal pull-
ups, and in that state can be used as inputs. As
In the 8052KB, Port 1 pins Pl.0 and Pl.l also serve inputs, .Port 3 pins that are externally being pulled
the T2 and T2EX functions, respectively. low will source current (IlL on the data sheet)' be-
cause of the pullups.
Port 2: Port 2 is an 8-bit bidirectional I/O port with
internal pullups. The Port 2 output buffers can sink/ Port 3 also serves the functions of various special
source 4 LS TTL inputs. Port 2 pins that have 1s features of the MeS-51 Family, as listed below:
written to them are pulled high by the internal pull-
ups, and in that state can be used as inputs. As Port
Alternative Function
inputs, Port 2 pins that are externally being pulled Pin
low will source current (IlL on the data sheet) be- P3.0 RXD(serial input port)
cause of the internal pullups. P3.1 TXD (serial output port)
P3.2 INTO (external interrupt 0)
Port 2 emits the high-order address byte during P3.3 INTl (external interrupt 1)
fetches from external Program Memory and during P3.4 TO (Timer 0 external input)
accesses to external Data Memory that use 16-bit P3.5 Tl (Timer 1 external input)
addresses (MOVX @DPTR). In this application it P3.6 WR (external data memory write strobe)
uses strong internal pullups when emitting 1s. Dur- P3.7 RD (external data memory read strobe)
7-104
inter 8051KB/8052KB
RST: Reset input. A high on this pin for two machine XTAL 1: Inputto the inverting oscillator amplifier.
cycles while the oscillator. is running resets the de-
vice. XTAL2: Output from the inverting oscillator amplifi-
er.
ALE: Address Latch Enable output pulse for latching
the low byte of the address during accesses to ex-
ternal memory. OSCILLATOR CHARACTERISTICS
In normal operation ALE is emitted at a constant XTAL1 and XT AL2 are the input and output, respec-
rate of % the oscillator frequency, and may be used tively, of an inverting amplifier which can be config-
for external timing or clocking purposes. Note, how- ured for use as an on-chip oscillator, as shown in
ever, that one ALE pulse is skipped during each ac- Figure 3. Either a quartz crystal or ceramic resonator
cess to external Data Memory. may be used. More detailed information concerning
the use of the on-chip oscillator is available in Appli-
PSEN: Program Store Enable is the read strobe to cation Note AP-155, "Oscillators for Microcontrol-
external Program Memory. lers."
When the device is executing code from external To drive the device from an external clock source,
Program Memory, PSEN is activated twice each ma- XTAL 1 should be grounded, while XT AL2 is driven,
chine cycle, except that two PSEN activations are as shown in Figure 4. There are no requirements on
skipped during each access to external Data Memo- the duty cycle of the external clock signal, since the
ry. input to the internal clocking circuitry is through a
divide-by-two flip-flop, but minimum and maximum
EA: External. Access enable EA must be externally high and low times specified on the Data Sheet must
held low in order to enable the device to fetch code be obsei"Ved.
from external Program memory locations 0 to
OFFFH (0 to 1FFFH, in the 8052KB).
EXTERNAL
C2 OSCILLATOR ------f XTAL2
SIGNAL
, - - - i ' t - -.....----4 XTAL2
o
r--- XTALl
..--n..........,...---4 XTALl
Cl
.....----f vss
.....- - - - - - - - 1 vss
270872-4
270872-3
Cl, C2 = 30 pF ± 10 pF for Crystals Figure 4. External Drive Configuration
= 40 pF ± 10 pF for Ceramic Resonators
Figure 3. Oscillator Connections
7-105
8951 KB/8052KB
ABSOLUTE MAXIMUM RATINGS* NOTICE: This data sheet contains preliminary' infor-
mation on new products in production. It is valid for
Ambient Temperature Under Bias ...... O·C to 70·C the devices indicated in the revision history. The
Storage Temperature .......... - 65·C to + 150·C specifications are subject to change without notice.
Voltage on Any Pin to Vss .......... -0.5V to + 7V * WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
Power Dissipation ....•.............•....... 1.5W These are stress ,ratings only. Operation beyond the
"Operating Conditions" is not recommended and ex-
tended exposure beyond the "Operating Conditions"
may affect device reliability.
D.C. CHARACTERISTICS TA = O·C to 70·C; Vcc = 5V ± 10%; VSS = OV
Symbol Parameter Min Max Units Test Conditions
VIL Input Low Voltage -0.5 O.S V
VIH Input High Voltage (Except XTAL2, RST) 2.0 Vcc + 0.5 V
VIH1 Input High Voltage to XTAL2, RST 2.5 Vcc + 0.5 V XTAL1 = VSS
VOL Output Low Voltage (Ports 1,2,3)* 0.45 V IOL = 1.6 rnA
Vou Output Low Voltage (Port 0, ALE, PSEN)* 0.45 V IOL = 3.2 rnA
VOL2 Output Low Voltage t (Any Combination of 1.0 V IOL = 15 rnA
Four Outputs from Ports 1 and 3)
VOH Output High Voltage (Ports 1, 2, 3) 2.4 V IOH = -so /LA
VOH1 Output High Voltage (Port 0 in 2.4 V IOH = -400/LA
External Bus Mode ALE, PSEN)
IlL Logical 0 Input Current (Ports 1, 2, 3) -800 /LA VIN = 0.45V
11L2 Logical 0 Input Current (XTAL2) -3.2 rnA VIN = 0.45V
III Input Leakage Current (Port 0) ±10 /LA 0.45 :s; VIN :s; Vcc
IIH1 Input Current to RST to Activate Reset 500 /LA VIN < (Vcc - 1.5V)
Icc Power Supply Current: All Outputs
8051KB 125 rnA Disconnected;
S052KB 175 rnA EA = Vcc
CIO Pin Capacitance (Except Xtal1) 10 pF Test freq = 1 MHz
NOTE:
*Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports 1
and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1-to-0
transitions during bus operations. In the worst cases (capacitive loading> 100 pF), the noise pulse on the ALE line may
exceed 0.8V. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt
Trigger STROBE input.
t Any four outputs from Ports 1 and 3 can be loaded to a 15 mA maximum. Excessive heating and dissipation will result if
more than four outputs are loaded to 15 mAo The total IOL for Ports 1 and 3 combined must not exceed 72.8 mA.
7-106
inter 8051 KB/8052KB
A.C. CHARACTERISTICS TA = O°Cto +70°C;Vcc = 5V ±10%;Vss = OV;
Load Capacitance for Port 0, ALE, and PSEN = 100 pF;
Load Capacitance for All Other Outputs = 80 pF
12 MHz Oscillator Variable Oscillator
Symbol Parameter Units
Min Max Min Max
1/TCLCL Oscillator Frequency 3.5 12.0 MHz
TLHLL ALE Pulse Width 127 2TCLCL-40 ns
TAVLL Address Valid to ALE Low 43 TCLCL-40 ns
TLLAX Address Hold after ALE Low 48 TCLCL-35 ns
TLLlV ALE Low to Valid Instr In 233 4TCLCL-100 ns
TLLPL ALE Low to PSEN Low 58 TCLCL-25 ns
TPLPH PSEN Pulse Width 215 3TCLCL-35 ns
TPLIV PSEN Low to Valid Instr In 125 3TCLCL-125 ns
TPXIX Input Instr Hold after PSEN 0 0 ns
TPXIZ Input Instr Float after PSEN 63 TCLCL-20 ns
TPXAV PSEN to Address Valid 75 TCLCL-8 ns
TAVIV Address to Valid Instr In 302 5TCLCL-115 ns
TPLAZ PSEN Low to Address Float 20 20 ns
TRLRH RD Pulse Width 400 6TCLCL-100 ns
TWLWH WR Pulse Width 400 6TCLCL-100 ns
TRLDV RD Low to Valid Data In 252 5TCLCL-165 ris
TRHDX Data Hold after RD 0 0 ns
TRHDZ Data Float after RD 97 2TCLCL-70 ns
TLLDV ALE Low to Valid Data In 517 8TCLCL-150 ns
TAVDV Address to Valid Data In 585 9TCLCL-165 ns
TLLWL ALE Low to RD or WR Low 200 300 3TCLCL-50 3TCLCL+50 ns
TAVWL Address to RD or WR Low 203 4TCLCL-130 ns
TOVWX Data Valid to WR Transition 23 TCLCL-60 ns
TOVWH Data Valid to WR High 433 7TCLCL-150 ns
TWHOX Data Hold after WR 33 TCLCL-50 ns
TRLAZ RD Low to Address Float 20 20 ns
TWHLH RD or WR High to ALE High 43 123 TCLCL-40 TCLCL+40 ns
NOTE:
'This table does not include the 8751-8 A.C. characteristics (see next page).
7-107
infef 8051 KB/8052KB
EXTERNAL PROGRAM MEMORY READ CYCLE
ALE
PORTO
PORT 2
270872-5
7-108
inter 8051 KB/8052KB
EXTERNAL DATA MEMORY READ CYCLE
ALE
i4-----TLLDV - - - . . - I
-.+-------TR~H+--~~
PORTO
PORT 2 P2.0-P2.7 DR AI-A'S FROM DPH AS-A.S FROM PCH
270872-6
EXTERNAL DATA MEMORY WRITE CYCLE
TWHLH
ALE
TLLWL .......~..~I------TWLWH - - - - - -.......~
TQVWX
t-~t-;;;:;.;~ t - - + - - - T Q V W H - - - - - !
PORTO DATA OUT
PORT 2 P2.0-P2.7 OR AS-AI5 FROM DPH AS-A 15 FROM PCH
270872-7
7-109
inter 8051 KB/B052KB
SERIAL PORT TIMING-SHIFT REGISTER MODE
Test Conditions: T A = O°C to 70°C; VCC = 5V ± 10%; VSS = OV; Load Capacitance = 80 pF
12 MHz Oscillator Variable Oscillator
Symbol Parameter Units
Min Max Min Max
TXLXL Serial Port Clock Cycle Time 1.0 12TCLCL fts
TQVXH O~tput Data Setup to Clock Rising 700 1OTCLCL -133 ns
Edge·
TXHQX Output Data Hold after Clock 50 2TCLCL-117 ns
Rising Edge
TXHDX Input Data Hold after Clock Rising 0 0 ns
Edge
TXHDV Clock Rising Edge to Input Data 700 10TCLCL-133 ns
Valid
SHIFT REGISTER TIMING WAVEFORMS
I ,0'
."
I"'TQ"'IIH~! ~ txHQI , I
\ X X X'-_--'X'-_-.JX XI...._--JXI....-_.-J!
"HD,I~ J~"HD'
t
~
SE111
WRITE TO SBUf
INf'UTDATA _ _ _ _ _ _ _ _ _ _ ~~~_', __ ..
~_J ~J~_J'~~, __ ,~_J
t
SET AI
CU.AA .. ,
270872-8
7-110
inter 8051 KB/8052KB
EXTERNAL CLOCK DRIVE
Symbol Parameter Min Max Units
1/TClCl Oscillator Frequency 3.5 12 MHz
TCHCX High Time 20 ns
TClCX low Time 20 ns
TClCH Rise Time 20 ns
TCHCl Fall Time 20 ns
EXTERNAL CLOCK DRIVE WAVEFORM
~---------TCLCL----------~~
270872-9
x=
A.C. TESTING INPUT, OUTPUT WAVEFORM
2.4=X >
G.45
20
08
TEST POINTS < 2.0
0.8
270872-10
A.C. Testing: Inputs are driven at 2.4V for a Logic "1" and 0.45V .
for a Logic "0". Timing measurements are made at 2.0V for a"
Logic "1" and 0.8V for a Logic "0".
7-111
inter 8051 KB/8052KB
NOTE:
"I" = logic high for that pin
"0" = logic low for that pin
"X" = "don't care"
Program Verification +5.
The on-chip Program Memory can be read out for
verification purposes, if desired. The address of the
Program Memory location to be read is applied to
Port 1 and pins P2.0-P2.3. The other pins should be
held at the "Verify" levels indicated in Table 3. The
contents of the addressed location will come out on
Port o. External pullups are required on Port 0 for
this operation. The setup is shown in Figure S.
.55
270872-11
Figure 5. Program Verification
VERIFICATION CHARACTERISTICS
TA = 21°C to 27"C; VCC = sv ±10%; VSS = ov
Symbol Parameter Min Max Units
1/TCLCL Oscillator Frequency 4 6 MHi
TAVQV Address to Data Valid 48TCLCL
TELQV ENABLE Low to Data Valid 48TCLCL
TEHQZ Data Float after ENABLE 0 48TCLCL
7-112
inter 8051 KB/8052KB
VERIFICATION WAVEFORMS DATA SHEET REVISION SUMMARY
1. This is the first version of this data sheet.
}--
j
PloO-P1.7
ADDRESS
P2.0-P2.3
- TAYOY
PORT 0 . DATA OUT
AlE/PROG
~~r---l
TElOY '--
For verification conditions see Figure 5.
J.---- +- TEHOZ
270872-12
7-113
80C51BH/80C31BH
CHMOS SINGLE-CHIP 8-BIT MICROCOMPUTER
80CS1BH-4 KBYTES OF FACTORY MASK-PROGRAMMABLE ROM
80C31BH-CPU WITH RAM AND 110
80C51 BH/80C31 BH-3.S to 12 MHz, Vee = SV ± 20%
80CS1BH-1/80C31BH-1-3.S to 16 MHz, Vee = SV ± 20%
80CS1BH-2/80C31BH-2-D.S to 12 MHz, Vee = SV ± 20%
• Power Control Modes
• Boolean
High Performance CHMOS Process
• 128 x 8-Bit RAM
• Processor
• 32 Programmable 110 Lines
• S Interrupt Sources
• Two 16-Bit Timer/Counters
• Programmable Serial Port
• 64K Program Memory Space • 64K Data Memory Space
• ONCETM (On-Circuit Emulation) Mode
The MCS®·51 CHMOS products are fabricated on Intel's CHMOS III process and are functionally compatible
with the standard MCS-51 HMOS and EPROM products. CHMOS III is a technology which combines the high
speed and density characteristics of HMOS with the low power attributes of CHMOS. This combination ex-
pands the effectiveness of the powerful MCS-51 architecture and instruction set.
Like the MCS-51 HMOS versions, the MCS-51 CHMOS products have the following features: 4 Kbyte of ROM
(80C51BH/80C51BH-1/80C51BH-2 only); 128 bytes of RAM; 321/0 lines; two 16-bit timer/counters; a five-
source two-level interrupt structure; a full duplex serial port; and on-chip oscillator and clock circuitry. In
addition, the MCS-51 CHMOS products have two software selectable modes of reduced activity for further
power reduction-Idle and Power Down.
The Idle mode freezes the CPU while allowing the RAM, timer/counters serial port and interrupt system to
continue functioning. The Power Down mode saves the RAM contents but freezes the oscillator, causing all
other chip functions to be inoperative.
October 1990
7-114 Order Number: 270064-008
80C51BH/80C31BH
P2.0-P2.7
vcc---l
I
,J.VSS-j
----------""
270064-1
Figure 1. Block Diagram
7-115
inter 80C51 BH/80C31 BH
IDLE MODE last instruction executed. The on-chip RAM and
Special Function Registers retain their values until
In the Idle mode, the CPU puts itself to sleep while the Power Down mode is terminated.
all the on chip peripherals stay active. The instruc-
tion that invokes the Idle mode is the last instruction The only exit from Power Down is a hardware reset.
executed in the normal operating mode before Idle Reset redefines the SFRs but does not change the
mode is activated. The content of CPU, the on chip on-chip RAM. The reset should not be activated be-
RAM, and all the Special Function Registers remain fore VCC is restored to its normal operating level and
intact during this mode. The Idle mode can be termi- must be held active long enough to allow the oscilla-
nated either by any enabled interrupt, at which time tor to restart and stabilize.
the process is picked up at the interrupt service rou-
tine and continued, or by a hardware reset which The control bits for the reduced power modes are in
starts the processor the same as a power on reset. the Special Function Register PCON.
NOTE:
POWER DOWN MODE For more detailed information on these reduced
power modes refer to Application Note AP-252,
In the Power Down mode the oscillator is stopped, "Designing with the SOC51BH".
and the instruction that invokes Power Down is the
Table 1. Status of the external pins during Idle and Power Down modes
Program
Mode ALE PSEN PORTO PORT 1 PORT 2 PORT 3
Memory
Idle Internal 1 1 Data Data Data Data
Idle External 1 1 Float Data Address Data
Power Down Internal 0 0 Data Data Data Data
Power Down External 0 0 Float Data Data Data
ONCETM MODE While the device is in ONCE Mode, the Port o pins
go into a float state, and the other port pins and ALE
The ONCE ("On-Circuit Emulation") Mode facilitates and PSEN are weakly pulled high. The oscillator cir-
testing and debugging of systems using the cuit remains active. While the BOC51BH/SOC31BH
BOC51 BH/SOC31 BH without removing the device is in this mode, an emulator or test CPU can be used
from the circuit. The ONCE Mode is invoked by: to drive the circuit. Normal operation is restored
1. Pull ALE low while the device is in reset and when a normal reset is applied.
PSEN is high; .
2. Hold ALE low as RST is de,activated.
PACKAGES
Part Prefix Package Type
SOC51BHI P 40-Pin Plastic DIP
SOC31BH" D 40-Pin CERDIP
N 44-Pin PLCC
S 44-PinQFP
·The 80C51BH-1, 80C51BH-2, 80C31BH-1, and 80C31BH-2
. have the same package types.
7-116
80C51BH/80C31BH
INDEX
Pl.D vee CORNER
Pl.l PO.D
Pl.Z PO.l
Pl.3 PO.2 ~..; ~on; ~"J ~"'J ~"J ~~ ~:Si l:j l~J ~;j L~J
Pl.4 PO.3 Pl.5 !: :~ PO ••
Pl.5 PO.• Pl.6 ~( i~ PO.S
Pl.~ PO.5 Pl.7 =,= ~ ~f PO.6
Pl.7 PO.6 RST !~] rM PO.7
RST PO.7
P3.D/RXD EA P3.0 jf ~ :~ EA
P3.1/TXD ALE Ne 1~j ~M: Ne
P3.2/INTO PSEN P3.1 1~j ~~ ALE
P3.3INT1 PZ.7 P3.2 H~ :~! PSEN
P3.41TO PZ.6 P3.3 1~ ~ ~~! P2.7
P3.51TI PZ.5
P2.4
P3.4 1! ~ :}q P2.6
P3.6/WR
P3.7/RD PZ.3 P3.S 1!~ [1! P2.S
XTAU PZ.Z :=: :~: :~: :c;; ;~: :i :, : ;lQ; :,~i; ;t; ;=:
XTALI PZ.l
VSS P2.0
270064-2 270064-3
Pin Pad (PLCC)
""'t'1.C"'!-::C! uC!-::"!'1
INDEX
CORNER
a:a:o:o:a:~-;}'~~~~
Pl.7 ):::i
RST :~C1
P3.0 ):::1
NC :~:::1
P3.1 ::C1
:iC1
.
P3.2
P3.3 :~:::1
P3.4 ]!f:i
P3.S "1","1 .....................................................
• I' II I' I. II ,. II II It I. I
""
i~~ ~~i ~:q ~~! !~i ~~~ i~! ~~i ~~i ~N~ ~~~
270064-18
Pad (QFP)
Figure 2. Connection Diagrams
7"117
intJ 80C51BH/80C31BH
PIN DESCRIPTIONS Port 3
Port 3 is an 8-bit bidirectional I/O port with internal
VCC pullups. Port 3 pins that have 1s written to them are
pulled high by the internal pullups, and in that state
Supply voltage during normal, Idle, and Power Down can be used as inputs. As inputs, Port 3 pins that are
operations. externally being pulled low will source current (IlL, on
the data sheet) because of the pull ups.
VSS Port 3 also serves the functions of various special
features of the MCS-51 Family, as listed below:
Circuit ground.
Port Pin Alternate Function
P3.0 RXD (serial input port)
PortO P3.1 TXD (serial output port)
Port 0 is an 8-bitopen drain bi-dire6tional I/O port. P3.2 INTO (external interrupt 0)
Port 0 pins that have 1's written to them float, and in P3.3 INT1 (external interrupt 1)
that state can be used as high-impedance inputs. P3.4 TO (Timer 0 external input)
P3.5 T1 (Timer 1 external input)
Port 0 is also the multiplexed low-order address and P3.6 WR (external data memory write
data bus during accesses to external Program and strobe)
Data Memory. In this application it uses strong inter-
P3.7 RD (external data memory read
nal pullups when emitting 1s. '
strobe)
Port l' RST
Port 1 is an 8-bit bidirectional liD port with internal Reset input. A high on this pin for two' machine cy-
pullups. Port 1 pins that have 1s written to them are cles while the oscillator is running resets the device.
pulled high by the internal pullups, and in that state An internal diffused resistor to Vss permits Power-
can be used as inputs. As inputs, Port 1 pins that are On reset using only an external capacitor to Vee.
externally being pulled low will source current (IlL, on
the data sheet) because of the internal pullups.
ALE
Address Latch Enable output pulse for latching the
Port 2 ,low byte of the address during accesses to external
Port 2 is an 8-bit bidirectional I/O port with internal memory.
pullups. Port 2 pins that have 1s written to them are
pulled high by the internal pullups, and in that state In normal operation ALE is emitted at a constant
can be used as inputs. As inputs, Port 2 pins that are rate of 1/6 the oscillator frequency, and may be
externally being pulled low will source current (IlL, on , used for external timing or clocking purposes. Note,
the data sheet) because of the internal pull ups. however, that one ALE pulse is skipped during each
access to external Data Memory.
Port 2 emits the high-order address byte during
fetches from external Program Memory and during If desired, ALE operation can be disabled by setting
accesses to external Data Memory that use 16-bit bit 0 of SFR location 8EH. With the bit set, ALE is
addresses (MOVX @DPTR). In this application it active only during a MOVX instruction. Otherwise,
uses strong internal piJllups when emitting 1s. Dur- the pin is weakly pulled high.
ing accesses to external pata Memory that use 8-bit
addresses (MOVX @Ri), Port 2 emits the contents of
the P2 Special Function Register.
Program Store Enable is the read strobe to external
Program Memory.
7-118
intJ 80C51BH/80C31BH
When the BOC51 BH is executing code from external To drive the device from an external clock source,
Program Memory, PSEN is activated twice each ma- XTAL 1 should be driven, while XTAL2 is left uncon-
chine cycle, except that two PSEN activations are nected, as shown in Figure 4. There are no require-
skipped during each access to external Data Memo- ments on the duty cycle of the external clock signal,
ry. PSEN is not activated during fetches from inter- since the input to the internal clocking circuitry is
nal program memory. through a divide-by-two flip-flop, but minimum and
maximum high and low times specified on the Data
Sheet must be observed.
External Access enable. EA must be strapped to
Vss in order to enable the device to fetch code from Design Considerations
external Program Memory locations starting at • When the Idle mode is terminated by a hardware
OOOOH up to FFFFH. If EA is strapped to Vee the reset, the device normally resumes program exe-
device executes from internal Program Memory un- cution, from where it left off, up to two machine
less the program counter contains an address great- . cycles before the internal reset algorithm takes
er than OFFFH. control. On-chip hardware inhibits access to inter-
nal RAM in this event, but access to the port pins
XTAL1 is not inhibited. To eliminate the possibility of an
unexpected write when Idle is terminated by re-
Input to the inverting oscillator amplifier and input to set, the instruction following the one that invokes
the internal clock generator circuits. Idle should not be one that writes to a port pin or
to external memory.
XTAL2 • An external oscillator may encounter as much as
a 100 pF load at XTAL1 when it starts-up. This is
Output from the inverting oscillator amplifier. due to interaction between the amplifier and its
feedback capacitance. Once the external signal
meets the VIL and VIH specifications the capaci-
tance will not exceed 20 pF.
XTAL2
XTAL 1 NC
- XTAL2
t--------Ivss EXTERNAL
- - - - - - - - - . , . - - i XTAL 1
r-
OSCILLATOR
SIGNAL
270064-4
Figure 3. Crystal Oscillator vss
270064-5
Oscillator Characteristics
Figure 4. External Drive Configuration
XTAL 1 and XTAL2 are the input and output, respec-
tively, of an inverting amplifier which can be config-
ured for use as an on-chip oscillator, as shown in
Figure 3. More detailed information concerning the
use of the on-chip oscillator is available in Applica-
tion Note AP-155, "Oscillator for Microcontrollers".
7-119
intJ 80C51BH/80C31BH
ABSOLUTE MAXIMUM RATINGS· NOTICE: This data sheet contains preliminary infor-
mation on new products in production: The specifica-
Ambient Temperature Under Bias ..•• O°C to + 70°C tions are subject to change without notice.
Storage Temperature ••........ - 65°C to + 150°C • WARNING: Stressing the device beyond the "Absolute
Voltage on any Maximum Ratings" may cause permanent damage.
Pin to VSS ................ -O.5Vto Vee +O.5V These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and ex-
Voltage on VCC to Vss ............. -O.5V to 6.5V tended exp()sure beyond the "Operating Conditions"
Maximum IOL per 1/0 pin ..........••.••.•• 15 mA may affect device reliability.
Power Dissipation ..... , ................... 1.0W·
"This value is based on the maximum allowable die temperature and
the thermal resistance of the package.
Operating Conditions:
TA (under Bias) = O°C to +70°C; VCC = 5V ±20%; Vss = OV
.D.C. CHARACTERISTICS (under Operating Conditions)
Symbol Parameter Min Typ(3) Max Unit Test Conditions
VIL Input Low Voltage -0.5 0.2 Vee -0.1 V
(ExceptEA)
VIU Input Low Voltage (EA) -0.5 0.2 Vee - 0.3 V
VIH Input High Voltage 0.2Vee + 0.9 Vee + 0.5 V
(Except XTAL I, RSn
VIHI Input High Voltage 0.7 Vee Vee + 0.5 V
(XTAL1, FIST)
VOL Output Low Voltage (6) 0.45 V IOL = I.S mA (I)
(Ports 1, 2, 3)
VOU Output Low Voltage (6) 0.45 V IOL = 3.2 mA (I)
(Port 0, ALE, PSEN)
VOH Output High Voltage 2.4 V IOH =·-SOp.AVee = 5V ±10,%
(Ports I, 2, 3, ALE, PSEN)
0.75 Vee V IOH = -25p.A
0.9 Vee V IOH = -10p.A
VOHI Output High Voltage 2.4 V IOH = -800 p.A Vee = 5V ± 10%
(Port 0 in External Bus
0.75 Vee V IOH = -300p.A
Mode)
0.9 Vee V IOH = -80 p.A (2)
IlL Logical 0 Input Current -50 p.A VIN = 0.45V
(Ports 1, 2, 3)
ITL Logical 1 to 0 Transition -650 p.A VIN = 2V
Current (Ports 1, 2, 3)
III Input Leakage Current ±10 p.A 0.45 < VIN < Vee
(PortO, EA)
RRST Reset Pulldown Resistor 50 150 KO
CIO Pin Capacitance 10 ' pF Test Freq = 1 MHz, TA = 25'C
lee Power Supply Current:
Active Mode, 12 MHz (4) 11 20 rnA
Idle Mode, 12 MHz (4) 1.7 5 rnA (5)
Power Down Mode 5 50 p.A
7-120
80C51 BH/80C31 BH
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports
1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1-
to-O transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the ALE line may
exceed O.BV. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt
Trigger STROBE input. .
2. Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9 Vcc
specification when the address bits are stabilizing.
3. "Typicals" are based on a limited number of samples taken from early manufacturing lots and are not guaranteed. The
values listed are at room temperature, 5V.
4. ICCMAX at other frequencies is given by
Active Mode: ICCMAX = 1.47 x FREQ + 2.35
Idle Mode: ICCMAX = 0.33 X FREQ + 1.05
where FREQ is the external oscillator frequency in MHz. ICCMAX is given in mA. See Figure 5.
5. See Figures 6 through 9 for IcC test conditions. Minimum Vee for Power Down is 2V.
6. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per B-bit port-
Port 0: 26 mA
Ports1, 2, and 3: 15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
Vcc
Ice~
vee
vec
PO
RST EA
TYP(3)
r----+---tF--f-----,>'i ACTIVE MODE
XTAL2
XTAL1
vss
MAX
IDLE MODE 270064-14
Figure 6. Icc Test Condition, Active Mode
TYP(3)
All other pins are disconnected.
L:~~::::±::::1::==JIDLEMODE
4MHz 8MHz 12MHz 16MHz
FREO AT XTAL 1
270064-13
Figure 5. Icc VS. Frequency
Valid only within frequency specifications of
the device under test.
XTAL2
XTAL1
vss
270064-15
Figure 7. Icc Test Condition, Idle Mode
All other pins are disconnected.
7-121
inter 80C51BH/80C31BH
Vee-O.s • - - - - - -'''-'~----
0.7 Vee
0.4SV ---1(0.2 Vee-O.l
TCHCL
270064"':16
Figure 8. Clock Signal Waveform for Icc Tests In Active and Idle Modes. TCLCH = TCHCL = 5 "s.
270064-17
Figure 9~ Icc Test Condition, Power Down Mode. All other pins are disconnected. Vcc = 2V to 6V.
EXPLANATION OF THE AC SYMBOLS P: PSEN.
Q: Output data.
Each timing symbol has 5 characters. The first char- A: AD Signal.
acter is always a 'T' (stands for time). The other T: Time.
characters, depending on their positions, stand for V: Valid.
the name of a signal or the logical status of that W:WA signal.
signal. The following is a list of all the characters and X: No longer a valid logic level.
what they stand for. Z: Float. .
A: Address.
C: Clock. EXAMPLE:
D: Input data.
H: Logic level HIGH. TAVLL = Time for Address Valid to ALE Low.
I: Instruction .(program memory contents). TLLPL = Time for ALE Low to PSEN Low.
L: Logic level LOW, or ALE.
7-122
inter SOC51 BH/SOC31 BH
A.C. CHARACTERISTICS
(Under Operating Conditions.) Load Capacitance for Port 0, ALE, and PSEN = 100 pF, Load Capacitance for
All Other Outputs = SO pF)
EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS
12 MHzOsc Variable Oscillator
Symbol Parameter Units
Min Max Min Max
1/TCLCL Oscillator Frequency MHz
SOC51 BH/SOC31 BH 3.5 12
SOC51 BH-1 ISOC31 BH-1 3.5 16
SOC51 BH-2/S0C31 BH-2 0.5 12
TLHLL ALE Pulse Width 127 2TCLCL - 40 ns
TAVLL Address Valid to ALE Low 2S TCLCL - 55 ns
TLLAX Address Hold After ALE Low 4S TCLCL - 35 ns
TLLlV ALE Low to Valiq Instr In 234 4TCLCL - 100 ns
TLLPL ALE Low to PSEN Low 43 TCLCL - 40 ns
TPLPH PSEN Pulse Width 205 3TCLCL - 45 ns
TPLIV PSEN Low to Valid Instr In 145 3TCLCL - 105 ns
TPXIX Input Instr Hold After PSEN 0 0 ns
TPXIZ Input Instr Float After PSEN 59 TCLCL - 25 ns
TAVIV Address to Valid Instr In 312 5TCLCL - 105 ns
TPLAZ PSEN Low to Address Float 10 10 ns
TRLRH RD Pulse Width 400 6TCLCL - 100 ns
TWLWH WR Pulse Width 400 6TCLCL - 100 ns
TRLDV RD Low to Valid Data In 252 5TCLCL - 165 ns
TRHDX Data Hold After RD 0 0 ns
TRHDZ Data Float After RD 97 2TCLCL - 70 ns
TLLDV ALE Low to Valid Data In 517 STCLCL - 150 ns
TAVDV Address to Valid Data In 5S5 9TCLCL - 165 ,ns
TLLWL ALE Low to RD or WR Low 200 300 3TCLCL - 50 3TCLCL + 50 ns
TAVWL Address Valid to RD or WR Low 203 4TCLCL - 130 ns
TOVWX Data Valid to WR Transition 23 TCLCL - 60 ns
TWHOX Data Hold After WR 33 TCLCL - 50 ns
TRLAZ RD Low to Address Float 0 0 ns
TWHLH RD or WR High to ALE High 43 123 TCLCL - 40 TCLCL + 40 ns
7-123
inter 80C51 BH/80C31 BH
EXTERNAL DATA MEMORY READ CYCLE
<C, n,-------+-'Ih,--------" TWHLH
-----TLLOy----
--TLLWl--I----,-TRLRH--+----1
--------~------~ 1,--------------------
- - fRLAl TRHOl' -
I
TRHOZ
--::-
PORTO DATA IN
------TAyOy-------1
PORT2 P2.0-P2.7 OR ""·A15 FROM OPH "'·A15 FROM PCH
270064-6
EXTERNAL PROGRAM MEMORY READ CYCLE
AlE
-TAVLL- - ---TPLPH---
TlLPL
TLLlV
TLLAX TPI,zl--
TPI'X- -
-TPLAZ
'HITR
~RTO IN
~RT2
270064-7
7-124
inter 80C51BH/80C31BH
EXTERNAL DATA MEMORY WRITE CYCLE
TWHLH
ALE
--TLLWL--I-----TWLWH
TQVWX
i- TWHQX
..L
PORTO INSTR
DATA OUT IN
PORT 2 P2.0 - P2.7 OR AB - A15 FROM DPH AB - A15 FROM PCH
270064-8
7-125
80C51 BH/80C31 BH
I!
4-i
I
L
if
I 0
I
Shift Register Mode Timing Waveforms,
7-126
80C51BH/80C31BH
EXTERNAL CLOCK DRIVE
Symbol Parameter Min Max Units
1/TCLCL Oscillator Frequency MHz
80C51 BH/80C31 BH 3.5 12
80C51 BH-1 180C31BH-1 3.5 16
80C51 BH-2/80C31 BH-2 0.5 12
TCHCX High Time 20 ns
TCLCX Low Time 20 ns
TCLCH Rise Time 20 ns
TCHCL Fall Time 20 ns
SERIAL TIMING-SHIFT REGISTER MODE
Test Conditions: TA = O·C to 70·C; Vee = 5V ±20%; Vss = OV; Load Capacitance = 80 pF
12 MHzOsc Variable Oscillator
Symbol Parameter Units
Min Max Min Max
TXLXL Serial Port Clock Cycle Time 1.0 12TCLCL ,...s
TOVXH Output Data Setup to Clock Rising Edge 700 10TCLCL - 133 ns
TXHOX Output Data Hold After Clock Rising Edge 50 2TCLCL - 117 ns
TXHDX Input Data Hold After Clock Rising Edge 0 0 ns
TXHDV Clock Rising Edge to Input Data Valid 700 10TCLCL - 133 ns
EXTERNAL CLOCK DRIVE WAVEFORM
270064-10
AC TESTING INPUT, OUTPUT WAVEFORMS FLOAT WAVEFORMS
VCC-O.5-y 0.2 VCC+O.9 >C VLOAD
0.45 V -.-A_ 2 ....;VC::.:Cc..-_
O_. O._ 1 ---, ' - -_ _ _ _ _-1 VOL +0.1 V
270064-12
270064-11
For timing purposes a port pin is no longer floating when a
AC Inputs during 1esting are driven at Vee - 0.5 for a logic "1" 100 mV change from load voltage occurs, and begins to float
and 0.45 V for a logic "0". Timing measurements are made at VIH when a 100 mV change from the loaded VOHIVOl level occurs.
min, for a logic "1" and Vil max. for a logic "0". IOl/lOH ;,' ± 20 mAo
7-127
intJ 80C51BH/80C31BH
ROM CHARACTERISTICS
Table 2 shows the logic levels for verifying the code data and reading the signature bytes on the 80CS1BHI
80C31BH.
Table 2. ROM Modes
Mode
Verify Code Data
NOTES:
"'1"' = Valid high for that pin
"'0" = Valid low for that pin
Program Verification cations will come out on Port O. External pullups are
required on Port 0 for this operation.
The address of the Program Memory loc~tion to be
read is applied to Port 1 and pins P2.0-P2.3. The Figure 10 shows the setup for verifying the program
other pins should be held at the "Verify" levels indi- memory.
cated in Table 2. The contents of the addressed 10-
+5V
PGM
DATA·
80C51BH
o (ENABLE)
.--...----1XTAL2
'--+----T-tXTAL 1 AS-All
Vss
270064-19
Figure 10. Verifying the ROM
ROM VERIFICATION CHARACTERISTICS
TA= 21°C to 27°C; Vee = SV±O.2SV; Vss = OV
Symbol Parameter Min Max Units
1/TCLCL Oscillator Frequency 4 6 MHz
TAVQV Address to Data Valid 48TCLCL
TELQV ENABLE Low to Data Valid 48TCLCL
TEHQZ Data Float after ENABLE 0 48TCLCL
,
7-128
inter 80C51 BH/80C31 BH
ROM VERIFICATION WAVEFORMS
VERIFICATION
:~:~::~:~ ----_-1f=~=T~:~::~:~ES~S=:J)>----
PORT 0----~(DATA OUT t
P2.7 "''''1 } "'Q'
270064-20
DATA SHEET REVISION SUMMARY
The following are the key differences between the -008 and -007 version of the 80C51 BH data'sheet: .
1. Added ONCE mode feature description.
2. Added ROM characteristics section.
3. Revised Maximum Ratings warning and data sheet status notice.
The following are the key differences between the -007 and the -006 version of cthe 80C51 BH data sheet:
1. Quad flatpack was added.
2. Added external oscillator start-up capacitance.
The following are the key differences between the -006 and the -005 version of the 80C51 BH data sheet:
1. Package table was added.
2. Note 6 on maximum current specifications added to DC Characteristics.
3. Data Sheet Revision Summary was added.
7-129
inter
SOC31 BH/SOC51 BH
EXPRESS
• Extended Temperature Range • 3.5 to 12 MHz Vee = 5V ±20%
• Burn-In
The Intel EXPRESS system offers enhancements to the operational specifications of the MCS®-51 family of
microcontrollers. These EXPRESS products are designed to meet the needs of those applications whose
operating requirements exceed commercial standards.
The EXPRESS program includes the commercial standard temperature range with burn-in and an extended
temperature range with or without burn-in.
With the commercial standard temperature range, operational characteristics are guaranteed over the temper-
ature range of O·C to 70·C. With the extended temperature range option, operational characteristics are
guaranteed over the range of - 40·C to + 85·C. .
The optional burn-in is dynamic for a minimum time of 160 hours at 125·C with Vee = 6.9V ± 0.25V, following
guidelines in MIL-STD-883, Method 1015.
Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part number. The
prefixes are listed in Table 1.
For the extended temperature range option, this data sheet specifies the parameters which deviate from their
commercial temperature range limits. The commercial temperature range data sheets are applicable for all
parameters not listed here. This data sheet is valid in conjunction with the commercial 80C51 BH/80C31 BH
data sheet, 270064-008.
September 1990
7-130 Order Number: 270218-003
80C31BH/80C51BH EXPRESS
Electrical Deviations from Commercial Specifications for Extended Temperature
Range .
D.C. and A.C. parameters not included here are the same as in the commercial temperature range data
sheets.
D.C. CHARACTERISTICS TA = -40°C to +S5°C; Vee = 5V ±20%; Vss = OV
Limits Test
Symbol Parameter Unit
Min Max Conditions
VIL Input Low Voltage (Except EA) -0.5 0.2Vee - 0.15 V
VIL1 EA -0.5V 0.2Vee - 0.35 V
VIH Input High Voltage (Except XTAL 1, RST) 0.2Vee + 1 Vee + 0.5 V
VIH1 Input High Voltage to XTAL 1, RST 0.7Vee + 0.1 Vee + 0.5 V
IlL Logical 0 Input Current (Port 1, 2, 3) -75 poA Yin = 0.45V
ITL Logical 1 to 0 transition -750 poA Yin = 2.0V
Current (Ports 1, 2, 3)
Table 1 Prefix Identification
Prefix Package Type Temperature Range Burn·ln.
P Plastic Commercial No
0 Cerdip Commercial No
N PLCC Commercial No
TP Plastic Extended No
TO Cerdip Extended No
TN PLCC Extended No
ap Plastic Commercial Yes
aD Cerdip Commercial Yes
aN PLCC Commercial Yes
LP Plastic Extended Yes
LD Cerdip Extended Yes
LN PLCC Extended Yes
NOTE:
• Commercial temperature range is o'e to 70'e. Extended temperature range is -40'C to +85°C.
• Burn-in is dynamic for a minimum time of 160 hours at 125'e, Vee = 6.9V ±0.25V, following guidelines in MIL-STD-883
Method 1015 (Test Condition D).
Examples:
PSOC31 BH indicates SOC31 BH in a plastic package and specified for commercial temperature range, without
burn-in.
LDSOC51 BH indicates SOC51 BH in a cerdip package and specified for extended temperature range with burn-
in.
DATA SHEET REVISION HISTORY
The following are the key differences between this and the -002 version of the SOC31 BH/SOC51 BH express
data sheet:
1. Data sheet status changed from "Preliminary" to "Production".
2. Added this revision history.
7-131
80C51 BHP
CHMOS SINGLE-CHIP 8-BIT MICROCOMPUTER
WITH PROTECTED ROM
80C51BHP-3.5-12 MHz, Vee = 5V ± 20%
80C51BHP-1-3.5-16 MHz, Vee = 5V ± 20%
80C51BHP-2-0.5-12 MHz, Vee = 5V ± 20%
• Power Control Modes
• High Performance CHMOS Process
• 128 x 8-Bit RAM
• Boolean Processor
• 32 Programmable I/O Lines
• Programmable
5 Interrupt Sources
• Two 16-Bit Timer/Counters
• 4K Data MemorySerial Port
• 4K Program Memory Space
• Space
(Expandable to 64K)
• Protection Feature Protects ROM Parts
Against Software Piracy
• ONCETM (On-Circuit Emulation) Mode
The MCS®-51 family of CHMOS products is fabricated on Intel's CHMOS III process and is functionally
compatible with the standard 8051 HMOS and EPROM products. CHMOS III is a technology which combines
the high speed and density characteristics of HMOS with the low power attributes of CMOS. This combination
expands the effectiveness of the powerful 8051 architecture and instruction set.
Like the 8051 HMOS versions, the 80C51 BHP has the following features: 4 Kbytes of ROM; 128 bytes of
RAM; 32 110 lines; two 16-bit timer/counters; a five-source two-level interrupt structure; a full duplex serial
port; and on-chip oscillator and clock circuitry. In addition, the 80C51 BHP has two software selectable modes
of reduced activity for further power reduction-Idle and Power Down.
The Idle mode freezes the CPU while allowing the RAM, timer/counters serial port and interrupt system to
continue functioning. The Power Down mode saves the RAM contents but freezes the oscillator, causing all
other chip functions to be inoperative.
The 80C51BHP is identical to the 80C51BH with the exception of the Protection Feature. To incorporate this
Protection Feature, program verification has been disabled and external memory accesses have been limited
to 4K.
October 1990
7-132 Order Number: 270603-003
intJ 80C51 BHP
..LVSS ---1
- I
~-@
- I
~-
270603-1
Figure 1. Block Diagram
7-133
80C51 BHP
IDLE MODE The only exit from Power Down is a hardware reset.
Reset redefines the SFRs but does not change the
In the Idle mode, the CPU puts itself to sleep while on-chip RAM. The reset should not be activated be-
all the on chip peripherals stay active. The instruc- fore Vee is restored to its normal operating level and
tion that invokes the Idle mode is the last instruction must be held active long enough to allow the oscilla-
executed in the normal operating mode before Idle tor to restart and stabilize.
mode is activated. The content of the on-chip RAM
and all the Special Function Registers remain intact The control bits for the reduced power modes are in
during this mode. The Idle mode can be terminated the Special Function Register peON.
either by any enabled interrupt, at which time the
process is picked up at the interrupt service routine NOTE:
and continued, or by a hardware reset which starts For more detailed information on these reduced
the processor the same as a power on reset. power modes refer to Application Note AP-252,
"Designing with the 80C51 BH".
POWER DOWN MODE
ONCETM MODE
In the Power Down mode the oscillator is stopped,
and the instruction that invokes Power Down is the The ONCE ("On-Circuit Emulation") Mode facilitates
last instruction executed. The on-chip RAM and testing and debugging of systems using the
Special Function Registers retain their values until 80C51 BHP without removing the device from the cir-
the Power Down mode is terminated. cuit. The ONCE Mode is invoked by:
1. Pull ALE low while the device is in reset and
PSEN is high;
2. Hold ALE low as RST is deactivated.
Table 1. Status of the external pins during Idle and Power Down modes
Program
Mode ALE PSEN PORTO PORT 1 PORT 2 PORT 3
Memory
Idle . Internal 1 1 Data Data Data Data
Idle External 1 1 Float Data Address Data
Power Down Internal 0 0 Data Data' Data Data
, Power Down External 0 0 Float Data Data Data
INDEX
Pl.0 Vee CORNER
Pl.l PO.O
Pl.2 PO.l
Pl.3 PO.2
Pl.4 PO.3 P1.5 ~~! PO.4
Pl.S PO.4 Pl.6 ~~ PO.S
Pl.6 PO.s Pl.7 ~~?: PO.6
Pl.7 PO.6 RST !~ J :~ PO.7
RST PO.7
P3.0 ]!] ~j~ EA
P3.0/RXD EA
P3.l/TXD ALE NC 1~ ~ ::J! NC
Pl.21INTO PSEN P3.1 ]C ~:?! ALE
P3.3INTl P2.7 P3.2 E~ :~! PSEN
P3.4/TO P2.6 P3.3 !~ ~ ~:?{ P2.7
P3.S/Tl P2.S
P3.4 !~j :~ P2.6
P3.61WR P2.4
P3.7/RD P2.3 P3.S E: :1! P2.S
XTAL2 P2.2 :~1 :~: :~: :;;: ;~; :~~ :£ ~i :~; r~; :~
HALl P2.l
~::;!:j~~~~~~:J~
vss P2.0 a..a..ee> CLa..Q.D..a..
270603-2 270603-3
Pin (PDIP) Pad (PLCC)
Figure 2. Connection Diagrams
7-134
80C51 BHP
While the device is in ONCE Mode, the Port 0 pins Port 2 emits the high-order address byte during
go into a float state, and the other port pins and ALE fetches from external Program Memory and during
and PSEN are weakly pulled high. The oscillator cir- accesses to external Data Memory that use 16-bit
cuit remains active. While the 80C51 BHP is in this addresses (MOVX @DPTR). In this application it
mode, an emulator or test CPU can be used to drive uses strong internal pull ups when emitting 1s. In the
the circuit. Normal operation is restored when a nor- 80C51 BHP, Bits 2.4 through 2.7 are forced to 0,
mal reset is applied. effectively limiting external data and code space to
4K each during external accesses (see Design Con-
siderations). During accesses to external Data Mem-
PACKAGES ory that use 8-bit addresses (MOVX @Ri), Port 2
emits the contents of the P2 Special Function Regis-
Part Prefix Package Type ter.
80C51BHP P 40-Pin Plastic DIP
N 44-Pin PLCC Port 3
Port 3 is an 8-bit bidirectional I/O port with internal
pullups. Port 3 pins that have 1s written to them are
PIN DESCRIPTIONS
pulled high by the internal pullups, and in that state
can be used as inputs. As inputs, Port 3 pins that are
Vee externally being pulled low will source current (IlL on
the data sheet) because of the pullups. '
Supply voltage during normal, Idle, and Power Down
operations. Port 3 also serves the functions of various special
features of the 8051 Family, as listed below:
Vss Port Pin Alternate Function
Circuit ground. P3.0 RXD (serial input port)
P3.1 TXD (serial output port)
Port 0 P3.2 INTO (external interrupt 0)
P3.3 INT1 (external interrupt 1)
Port 0 is an 8-bit open drain bi-directional I/O port. P3.4 TO (Timer 0 external input)
Port 0 pins that have 1's written to them float, and in P3.5 T1 (Timer 1 external input)
that state can be used as high-impedance inputs. WR (external data memory write
P3.6
Port 0 is also the multiplexed low-order address and strobe)
data bus during accesses to external Program and P3.7 RD (external data memory read
Data Memory. In this application it uses strong inter- strobe)
nal pullups when emitting 1s.
RST
Port 1
Reset input. A high on this pin for two machine cy,
Port 1 is an 8-bit bidirectional I/O port with internal cles while the oscillator is running resets the device.
pullups. Port 1 pins that have 1s written to them are An internal diffused resistor to VSS permits Power-
pulled high by the internal pullups, and in that state On reset using only an external capacitor to Vee.
can be used as inputs. As inputs, Port 1 pins that are
externally being pulled low will source current (IlL, on ALE
the data sheet) because of the internal pullups.
Addr.ess Latch Enable output pulse for latching the
low byte of the address during accesses to external
Port 2
memory.
Port 2 is an 8-bit bidirectional I/O port with internal
pull ups. Port 2 pins that have 1s written to them are In normal operation ALE is emitted at a constant
pulled high by the internal pull ups, and in that state rate of 1/6 the oscillator frequency, and may be
can be used as inputs. As inputs, Port 2 pins that are used for external timing or clocking purposes. Note,
externally being pulled low will source current (IlL, on however, that one ALE pulse is skipped during each
the data sheet) be~ause of the internal pullups. access to external Data Memory.
7-135
80C51 BHP
To drive the device from .an external clock source,
XTAL 1 should be driven, while XTAL2 is left uncon-
Program Store Enable is the read strobe to external nected, as shown in Figure 4. There are no require-
Program Memory. ments on the duty cycle of the external clock signal,
since the input to the internal clocking circuitry is
When the device is executing code from external through a divide-by-two flip-flop, but minimum and
Program Memory, PSEN is activated twice each ma- maximum high and low times specified on the Data
chine cycle, except that two PSEN activations are Sheet must be observed.
skipped during each access to external Data Memo-
ry. PSEN is not activated during fetches from inter-
nal program memory. Design Considerations
• The 80C51 BHP cannot access external Program
EA or Data memory above 4K. This means that the
following instructions that use the Data Pointer
External Access enable. EA must be strapped to
only read/write data at address locations below
Vss in order to enable the device to fetch code from OFFFH:
external Program Memory locations· starting at
OOOOH up to FFFFH. If EA is strapped to. Vee the MOVX A, @DPTR
device executes from internal Program Memory un-
MOVX @DPTR, A
less the program counter contains an address great-
er than OFFFH.
When the Data Pointer contains an address
above the 4K limit, those locations will not be ac-
XTAL1 cessed. To access Data Memory above 4K. the
MOVX @Ri, A or MOVX A, @Ri instructions must
Input to the inverting oscillator amplifier and input to be used.
the internal clock generator circuits. • Before entering the Power Down mode the con-
tents of the Carry Bit and B.7 must be equal.
XTAL2 • When the Idle mode is terminated by a hardware
reset, the device normally resumes program exe-
Output from the inverting oscillator amplifier. cution, from where it left off, up to two machine
cycles before the internal reset algorithm takes
control. On-chip hardware inhibits access to inter-
nal RAM in this event, but access to the port pins
,is not inhibited. To eliminate the possibility of an
XTAL2
unexpected write when Idle is terminated by re-
set, the instruction following the one that invokes'
Idle should not be one that writes to a port pin or
XTAL 1
to external memory.
t----------tvss
270603-4
Ne
XTAL2
Figure 3. Crystal Oscillator
EXTERNAL
~1~~~t'TOR - - - - - - - - - - - XTAL 1
OSCillator Characteristics
YSS
XTAL1 and XTAL2 are the input and output, respec-
tively, of an inverting amplifier which can be config-
ured for use as an on-chip oscillator, as shown in
270603-5
Figure 3. More .detailed information concerning the
use of the .on-chip oscillator is available in Applica- Figure 4. External Drive Configuration
tion Note AP-155, "Oscillator for Microcontrollers".
7-136
inter 80C51 BHP
ABSOLUTE MAXIMUM RATI.NGS* NOTICE: This is a production data sheet. The specifi-
cations are subject to change without notice.
Ambient Temperature Under Bias .... O°C to + 70°C
• WARNING: Stressing the device beyond the "Absolute
Storage Temperature .......... - 65°C to + 150°C Maximum Ratings" may cause permanent damage.
Voltage on any These are stress ratings only. Operation beyond the
Pin to Vss ................ -0.5V to VCC +0.5V "Operating Conditions" is not recommended and ex-
tended exposure beyond the "Operating Conditions"
Voltage on Vcc to Vss ............. -0.5V to 6.5V may affect device reliability.
Maximum IOL per I/O Pin .................. 15 mA
Power Dissipation ......................... 1.0W·
'This value is based on the maximum allowable die temperature and
the thermal resistance of the package.
Operating Conditions: T A (Under Bias) = O°C to + 70°C; Vcc = 5V ± 20%; VSS = OV
D.C. CHARACTERISTICS (Under Operating Conditions)
Symbol Parameter Min Typ(3) Max Unit Test Conditions
VIL Input Low Voltage -0.5 0.2 Vee -0.1 V
(Except EA)
VIL1 Input Low Voltage (EA) -0.5 0.2 Vee - 0.3 V
VIH Input High Voltage 0.2 Vee + 0.9 Vee + 0.5 V
(Except XT AU, RST)
VIH1 Input High Voltage 0.7 Vee Vee + 0.5 V
(XTAU, RST)
VOL Output Low Voltage (6) 0.45 V IOL = 1.6 rnA (1)
(Ports 1, 2, 3)
VOL1 Output Low Voltage (6) 0.45 V IOL = 3.2 rnA (1)
(Port 0, ALE, PSEN)
VOH Output High Voltage 2.4 V IOH = -60 /-LA Vee = 5V ± 10%
(Ports 1, 2, 3, ALE, PSEN)
0.75 Vee V IOH = -25/-LA
0.9 Vee V IOH = -10 /-LA
VOH1 Output High Voltage 2.4 V IOH = -800 /-LA Vee = 5V ±10%
(Port 0 in External Bus
0.75 Vee V IOH = -300/-LA
Mode)
0.9 Vee V IOH = -80 /-LA (2)
IlL Logical 0 Input Current -50 /-LA VIN = 0.45V
(Ports 1, 2, 3)
ITL Logical 1 to 0 Transition -650 /-LA VIN = 2V
Current (Ports 1 , 2, 3)
III Input Leakage Current ±10 /-LA 0.45 < VIN< Vee
(Port 0, EA)
RRST Reset Pulldown Resistor 50 150 K!l
cia Pin Capacitance 10 pF Test Freq = 1 MHz, TA = 25"C
lee Power Supply Current:
Active Mode, 12 MHz (4) 11 20 rnA
Idle Mode, 12 MHz (4) 1.7 5 rnA (5)
'Power Down Mode 5 50 /-LA
7-137
80C51 BHP
NOTES:
1. Capacitive loading on Ports a and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports
1 and 3. The noise is due to external bus capacitance discharging into the Port a and Port, 2 pins when these pins make I-
to-a transitions during bus operations. In the worst cases (capacitive loading> 100 pF), the noise pulse on the ALE line may
exceed o.av. In such cases it may be desirabJe to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt
Trigger STROBE input. ,
2. Capacitive loading on Ports a and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9 Vee
specification when the address bits are stabilizing. .
3. "Typicals" are based on a limited number of samples taken from early manufacturing lots and are not guaranteed. The
values listed are at room temperature, 5V.
4. ICCMAX·at other frequencies is given by
Active Mode: ICCMAX = 1.47 x FREQ' + 2.35
Idle Mode: ICCMAX = 0.33 x FREQ + 1.05
where FREQ is the external oscillator frequency in MHz. ICCMAX is given iii mA. See Figure 5.
5. See Figures 6 through 9 for Icc test conditions. Minimum Vcc for Power Down is 2V.
6. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per Port Pin: 10 mA
Maximum IOL per a-Bit Port -
porta: 26mA
Ports 1, 2 and 3: 15 mA
Maximum TotaiiOL for all output pins: 7f mA
If IOL exceeds thetesfcondition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
MAX
25 ,.----.--,.-------r---,,, ACTIVE MODE
20 1---+----+-----,(---1 PO
RST EA
TYP(3)
151--:--+--tF--t--,..j ACTIVE MODE
XTAL2
XTALI
vss
MAX ,270603-7
IDLE MODE
Figure 6. Icc Test Condition, Active Mode
All other pins are disconnected.
TYP(3)
L.:~d:::::::t=j:=J IDLE MODE'
4MHz 8MHz 12MHz 16MHz
fREQ'AT XTALI
270603-6
Figure 5_ Icc vs. Frequency
Valid only within frequency specifications of
the device under test.
, 270603-8
Figure 7. Icc Test Condition, Idle Mode
All other pins are disconnected.
7-138
iritJ 80C51 BHP
Vee.0.5· ••••• -.~~----
0.7 Vee
0.45V ---1(0.2 Vee·O.l
TCHCL
270603-9
Figure 8. Clock Signal Waveform for lee Tests In Active and Idle Modes. TCLCH = TCHCL = 5 ns
Vee
Ice~
i--~ve-c"'~
PO \r--J
RST EA
XTAL2
XTALI
vss
270603-10
Figure 9. lee Test Condition, Power Down Mode. All other pins are disconnected. Vee = 2V to 6V
EXPLANATION OF THE AC SYMBOLS P: PSEN.
Q: Output data.
Each timing symbol has 5 characters. The first char· R: RD signal.
acter is always a 'T' (stands for time). The other T: Time.
characters, depending on their positions, ,stand for V: Valid.
the name of a signal or the logical status of that W: WR signal.
signal. The following is a list of all the characters "and X: No longer a valid logic level.
what they stand for. Z: Float.
A: Address.
C: Clock. EXAMPLE:
D: Input data.
H: Logic level HIGH. TAVLL = Time for Address Valid to ALE Low.
I: Instruction (program memory contents). TLLPL = Time for ALE Low to PSEN Low.
L: Logic level LOW, or ALE.
7-139
80C51 BHP
A.C. CHARACTERISTICS
(Under Operating Conditions: load Capacitance for Port 0, ALE, and PSEN =100 pF, load Capacitance for
All Other Outputs = 80 pF) .
EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS
12 MHzOsc Variable Oscillator
Symbol Parameter Units
Min Max Min Max
1/TClCl Oscillator Frequency MHz
80C51 BH/80C31 BH 3.5 12
80C51 BH-1 180C31 BH-1 3.5 16
80C51 BH-2/80C31 BH-2 0.5 12
TlHll ALE Pulse Width 127 2TClCl - 40 ns
TAVll Address Valid to ALE low 28 TClCl - 55 ns
TllAX Address Hold After ALE low 48 TClCl - 35 ns
TlLlV ALE low to Valid Instr In 234 4TClCl - 100 ns
TllPl ALE low to PSEN low 43 TClCl - 40 ns
TPlPH PSEN Pulse Width 205 3TClCl - 45 ns
TPLIV PSEN low to Valid Instr In 145 3TClCl - 105 ns
TPXIX Input Instr Hold After PSEN 0 0 ns
TPXIZ Input Instr Float After PSEN 59 TClCl - 25 ns
TAVIV Address to Valid Instr In 312 5TClCl - 105 ns
TPlAZ PSEN low to Address Float 10 10 ns
TRlRH RD Pulse Width 400 6TClCl - 100 ns
TWlWH WR Pulse Width 400 6TClCl - 100 ns
TRlDV RD low to Valid Data In 252 5TClCl - 165 ns
TRHDX Data Hold After RD 0 0 ns
TRHDZ Data Float After RD 97 2TClCL - 70 ns
TllDV ALE low to Valid Data In 517 8TClCl - 150 ns
TAVDV Address to Valid Data In 585 9TClCl - 165 ns
TllWl ALE low to RD or WR low 200 300 3TClCl - 50 3TClCl + 50 ns
TAVWl Address Valid to RD or WR low 203 4TClCl - 130 ns
TOVWX Data Valid to WR Transition 23 TClCl - 60 ns
TWHOX Data Hold After WR 33 TClCl - 50 ns
TRLAZ RD low to Address Float 0 0 ns
TWHlH RD or WR High to ALE High 43 123 TClCl - 40 TClCl + 40 ns
7-140
intJ 80C51 BHP
EXTERNAL DATA MEMORY READ CYCLE
TWHLH
ALE
II
I------TLLDV------I
--TLLWL--I-----TRLRH-+----
- -TALAZ
PORTO
--------TAVDV-------
PDRT2 P2.0-P2.7 OR AS-A 15 FAOM DPH AI·A15 FA OM PCH
270603-11
EXTERNAL PROGRAM MEMORY READ CYCLE
AU
-TAYLL- TU'PL - - - T P L P H - - -
TLLlV
TLUI TPIIZI--
TPIIX- -
INITA
PORTO IN
PORT 2 Al-A15
270603-12
7·141
80C51 BHP
EXTERNAL DATA MEMORY WRITE CYCLE
TwHLH
ALE
-TLLWL-I TWLWH
WA
TOVWX
~ TWHOX
_TLLAX_ .L
POATO AO-A7 INSTA
FAOM AIDA DPL OATAOUT IN
POAT2 P2.0 - P2.7 OA AI- A15 FAOM DPH AI- A15 FADM PCH
270603-13
7-142
inter 80C51 BHP
T
~
1
J-i
Shift Register Mode Timing Waveforms
7-143
inter 80C51 BHP
EXTERNAL CLOCK DRIVE
Symbol Parameter Min Max Units
1/TCLCL Oscillator Frequency MHz
80CS1BHP 3.S 12
80CS1BHP-1 3.S 16
80CS1BHP-2 O.S 12
TCHCX High Time 20 ns
TCLCX Low Time 20 ns
TCLCH Rise Time 20 ns
TCHCL Fall Time 20 ns
SERIAL TIMING-SHIFT REGISTER MODE
Test Conditions: TA = ODC to 70DC; Vee = SV ±20%; Vss = OV; Load Capacitance = 80 pF
12 MHzOsc Variable Oscillator
Symbol Parameter Units
Min Max Min Max
TXLXL Serial Port Clock Cycle Time 1.0 12TCLCL ,""S
TQVXH Output Data Setup to Clock Rising Edge 700 10TCLCL - 133 ns
TXHQX Output Data Hold After Clock Rising Edge SO 2TCLCL - 117 ns
TXHDX Input Data Hold After Clock Rising Edge 0 0 ns
TXHDV Clock Rising Edge to Input Data Valid 700 10TCLCL - 133 ns
EXTERNAL CLOCK DRIVE WAVEFORM
270603-15
AC TESTING INPUT, OUTPUT WAVEFORMS FLOAT WAVEFORMS
VCC- 0.5 -y 0.2 Vcc+ 0•9 >C VLOAD TIMING REFERENCE
POINTS
0.45 V ~_0_.2_VC;;.:C:;..-_0_.1_ _ _..... VOL+0.1 V
270603-17
270603-16
For timing purposes a port pin is no longer floating when a
AC Inputs during testing are driven at Vee - 0.5 for a logic "1" 100 mV change from load voltage occurs, and begins to float
and 0.45 V for a logic "0". Timing measurements are made at VIH when a 100 mV change from the loaded VOHIVOL level occurs.
min. for a logic "1" and VIL max. for a logic "0". IOLIIOH;" ±20 mAo
7-144
inter 80C51 BHP
DATA SHEET REVISION HISTORY
The following are the key differences between this and the -002 version of the 80C51 BHP data sheet:
1. Data sheet status changed from "Preliminary" to "Production".
2. Revised Maximum Ratings Warning and Data Sheet Status Notice.
3. ONCETM Mode feature added.
The following are the key differences between this and the -001 version of the 80C51 BHP data sheet:
1. Package Table was added.
2. Note 6 on Maximum Current Specifications was added to D.C. Characteristics.
3. Data Sheet Revision History was added.
7-145
87C51/87C51-1/87C51-2
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
WITH 4K BYTES OF EPROM PROGRAM MEMORY
87CS1-3.S to 12 MHz, Vee =sv ± 10%
87CS1-1-3.S to 16 MHz, Vee = sv ± 10%
87CS1-2-0.S to 12 MHz, Vee = sv ± 10%
• High Performance CHMOS EPROM
• Programmable Serial Channel
• Quick-Pulse Programming™ Algorithm
• TTL- and CMOS-Compatible Logic
• 2-Level Program Memory Lock
•
Levels
• Boolean Processor
•
64K External Program Memory Space
• 128-Byte Data RAM
•
64K External Data Memory Space
• 32 Programmable I/O Lines
•
IDLE and POWER DOWN Modes
ONCETM Mode Facilitates System
• Two 16-Bit Timer/Counters
Testing
• S Interrupt Sources
• LCC, PLCC, and DIP Packaging
Available
The 87C51 is the EPROM version of the 80C51 BH. It is fabricated on Intel's CHMOS II-E process. It contains
4K bytes of on~chip Program memory that can be electrically programmed, and can be erased by exposure to
ultraviolet light.
The 87C51 EPROM array uses a modified Quick-Pulse programming algorithm, by which the entire 4K-byte
array can be programmed in about 12 seconds.
The extremely low operating power, along with the two reduced power modes, Idle and Power Down, make
this part very suitable for low power applications. The Idle mode freezes the CPU while allowing the RAM,
timer/counters, serial port, and interrupt system to continue functioning. The Power Down mode saves the
RAM contents but freezes the oscillator, causing all other chip functions to be inoperative.
October 1988
7-146 Order Number: 270147-005
infef 87C51/87C51-1/87C51-2
-----------,
PSEN .
EA--.-.
ALE TIMING
AND
RST ~ CONTROL
I
L.
XTAL1
-----"'
Pl.O- Pl.7 P3.0- P3.7
270147-1
Figure 1. MCS®-51 Architectural Block Diagram
7-147
intJ 87C51/87C51-1/87C51-2
PACKAGES Vss: Circuit ground.
Part Prefix Package Type Port 0: Port 0 is an 8-bit open drain bidirectional 1/0
40-Pin Plastic DIP port. As an output port each pin can ~ink 8 LS TTL
87C51 I P
inputs. Port 0 pins that have 1s written to them float,
87C51-11 D 40-Pin CERDIP
and in that state can be used as high-impedance
87C51-2 N 44-Pin PLCC inputs.
Port 0 is also the multiplexed low-order address and
P1.0 Vee data bus during accesses to external memory. In this
P1.1 PO.O (ADO) application it uses strong internal pullups when emit-
P1.Z PO. 1 (AD1) ting 1s.
P1.3 PO.2 (ADZ)
P1.4 PO.3 (AD3) Port 0 also receives the code bytes during EPROM
P1.5 PO.4 (AD4) programming, and outputs. the code bytes during
P1.6 PO.5 (ADS) program verification. External pullups are required
P1.7 PO.6 (AD6) during program verification.
PO.7 (AD7)
(RXD) P3.0 EA/Vpp Port 1: Port 1 is an 8-bit bidirectional 1/0 port with
(TXD) P3.1 ALE/PROG internal pullups. Port 1 pins that have 1s written to
(INTO) P3.Z PSEN them are pulled high by the internal pullups, and in
(INTI) P3.3 PZ.7 (A15)
that state can be used as inputs. As inputs, Port 1
(TO) P3.4 PZ.6 (A14)
pins that are externally being pulled low will source
(TI) P3.5 PZ.5 (A13)
current (IlL, on the data sheet) because of the inter-
(WR) P3.6 PZ.4 (A1Z)
nal pullups.
(Ril) P3.7 PZ.3 (All)
XTAL2 P2.2 (Al0)
Port 1 also receives the low-order address bytes
XTAL1 PZ.l (A9)
during EPROM programming and program verifica-
Vss P2.0 (AS)
tion.
270147-2
DIP Port 2: Port 2 is an a-bit bidirectionalliO port with
internal pullups. Port 2 pins that have 1s written to
S-::-N'M
c ceo them are pulled high by the internal pullups, and in
~~~~
~ "'!
__ or: _
l'! _ q q 0
0 0
00 <'i 0
--: 0 '1 that state can be used as inputs. As inputs, Port 2
INDEX
CORNER
~ z > ~ ~ ~ ~ pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the inter-
PO.' (AD4) nal pullups.
PO.S (ADS)
PO.6 (ADS) Port 2 emits the high-order address byte during
PO.7 (AD7)
fetches from external Program memory and during
EA/Vpp accesses to external Data Memory that use 16-bit
NC He
address (MOVX @DPTR). In this application it uses
(TXD) P3.1 ALE/PROO
(INTO) P3.2 PSEN
strong internal pullups when emitting 1s.
(INTI) P3.3
(TO) P3.4 P2 •• (A14) During accesses to external Data Memory that use
(TI) P3.5 P2.S (A13) a-bit addresses (MOVX @Ri), Port 2 emits the con-
tents of the P2 Special Function Register.
Port 2 also receives some control signals and the
high-order address bits during EPROM programming
and program verification.
270147-21
PLCC Port 3: Port 3 is an 8-bit bidirectional 1/0 port with
internal pullups. Port 3 pins that have 1s written to
Figure 2_ Pin Connections them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 3
PIN DESCRIPTION pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the pull-
Vee: Supply voltage during normal, Idle, and Power ups.
Down operations. .
7-148
inter 87C51/87C51-1/87C51-2
Port 3 also serves the functions of various special
features of the MCS-51 Family, as listed below:
Pin Name Alternate Function XTAL2
P3.0 RXD Serial input line
XTAL 1
P3.1 TXD Serial output line
P3.2 INTO External Interrupt 0
P3.3 INT1 External Interrupt 1
...-------1 vss
P3.4 TO Timer 0 external input
270147-3
P3.5 T1 Timer 1 external input
P3.6 WR External Data Memory Write strobe Figure 3. Using the On-Chip Oscillator
P3.7 RD External Data Memory Read strobe
Port 3 also receives some .control signals for
EPROM programming and program verification.
NC - XTAL2
RST: Reset input. A logic high on this pin for two EXTERNAL
machine cycles vyhile the oscillator is running resets OSCILLATOR - - - - t XTAL 1
SIGNAL
the device. An internal pulldown resistor permits a
power-on reset to be generated using only an exter- r vss
nal capacitor to Vee.
-4:-~
ALE/PROG: Address Latch Enable output signal for 270147-4
latching the low byte of the address during accesses
to external memory. This pin is also the program Figure 4. External Clock Drive
pulse input (PROG) during EPROM programming.
In normal operation ALE is emitted at a constant OSCILLATOR CHARACTERISTICS
rate of 1/6 the oscillator frequency, and may be
XTAL 1 and XTAL2 are the input and output, respec-
used for external timing or clocking purposes. Note, tively, of an inverting amplifier which can be config-
however, that one ALE pulse is skipped during each ured for use as an on-chip oscillator, as shown in
access to external Data Memory. Figure 3.
PSEN: Program Store Enable is the Read strobe to To drive the device from an external clock source,
External Program Memory. When the 87C51 is exe- XTAL 1 should be driven, while XTAL2 is left uncon-
cuting from Internal Program Memory, PSEN is inac- nected, as shown in Figure 4. There are no require-
tive (high). When the device is executing code from ments on the duty cycle of the external clock signal,
External Program Memory, PSEN is activated twice since the input to the internal clocking circuitry is
each machine cycle, except that two PSEN activa- through a divide-by-two flip-flop, but minimum and
tions are skipped during each access to External maximum high and low times specified on ·the Data
Data Memory. Sheet must be observed;
EA/Vpp: External Access enable. EA must be
strapped to Vss in order to enable the 87C51 to IDLE MODE
fetch code from External Program Memory locations
starting at OOaOH up to FFFFH. Note, however, that In Idle Mode, the CPU puts itself to sleep while all
if either of the Lock Bits is programmed, the logic the on-chip peripherals remain active. The mode is
level at EA is internally latched during reset. invoked by software. The content .of the on-chip
RAM and all the Special Functions Registers remain
EA must be strapped to Vee for internal program unchanged during this mode. The Idle Mode can be
execution. terminated by any enabled interrupt or by a hard-
ware reset.
This pin also receives the 12.75V programming sup-
ply voltage (Vpp) during EPROM programming. It should be noted that when Idle is terminated by a
hardware reset, the device normally resumes pro-
XTAL 1: Input to the inverting oscillator amplifier and gram execution, from where it left off, up to two ma-
input to the internal clock generating circuits. chine cycles before the internal reset algorithm
takes control. On-chip hardware inhibits access to
XTAL2: Output from the inverting oscillator amplifi- internal RAM in this event, but access to the port
er.
7-149
inter 87C51/87C51-1/87C51-2
Table 1 Status of the external pins during Idle and Power Down
Program
Mode ALE PSEN PORTO PORT1 ~ORT2 PORT3
Memory
Idle Internal 1 1 Data Data Data Data
Idle External 1 1 Float Data Address Data
Power Down Internal 0 0 Data Data Data Data
Power Down . External 0 0 Float Data Data Data
NOTE:
For more detailed information on the reduced power modes refer to current Embedded Controller Handbook, and Applica-
tion Note AP-252, "Designing with the 80C51 BH."
pins is not inhibited. To eliminate the possibility of an Lock Bits: Also on the chip are two Lock Bits which
unexpected write to .a port pin when Idle is terminat- can be left unprogrammed(U) or can be pro-
ed by reset, the. instruction following the one that grammed (P) to obtain the following additional fea-
invokes Idle should not be one that writes to a port tures' ,
pin or to external memory.
Bit 1 Bit 2 Additional Features
POWER DOWN MODE U U none
In the Power Down mode the oscillator is stopped, P U • Externally fetched code can not
and the instruction that invokes Power Down is the access internal Program Memory.
last instruction executed. The on-chip RAM and • Further programming disabled.
Special Function Registers retain their values until U P (Reserved for Future definition.)
the Power Down mode is terminated.
P P • Externally fetched code can not
The only' exit from Power Down is a hardware reset. access internal Program Memory.
Reset redefines the SFRs but does not change the • Further programming disabled.
on~chip RAM. The reset should not be activated be- • Program verification is disabled.
fore VCC is restored to its normal operating level and
must be held active long enough to allow the oscilla-
tor to restart and stabilize. When Lock Bit 1 is programmed, ~he logic level at
the EA pin is sampled and latched during reset. If
the device is powered up without a reset, the ,latch
DESIGNCONS,DERATIONS initializes to a random value, and holds that value
until reset is activated. It is necessary that the
Exposure to light when the device is in operation
'latched value of EA be·in agreement with the current
may cause logic errors. For this reason, it is suggest-
logiC level at that pin in order for the device to func-
ed that an opaque label be placed over the window
tion properly.
when the die is exposed to ambient light. '
If using the 87(;51 to prototype for the 80C51 BH,
consult the Design Considerations section of the ONCETM MODE
80C51 BH data sheet. '
The ONCE ("on-circuit emulation") mode facilitates
testing and debugging of systems using the 87C51
PROGRAM MEMORY LOCK without the 87C51 having to be removed from the
circuit. The ONCE mode is invoked by:
The 87C51 contains two program memory lock
schemes: Encrypted Verify and Lock Bits. 1. Pull. ALE low while the device is in reset and
PSEN is high;
Encrypted Verify: The 87C51 implements a 32- 2. Hold ALE low as RST is deactivated.
byte EPROM array ,that can be programmed by the
customer, and which can then be used to encrypt While the device is in ONCE mode,the .Port 0 pins
the program code bytes during EPROM verification. go into a float state, and the other port pins and ALE'
The EPROM verification procedure is performed as and PSEN are weakly pulled high. The oscillator cir-
usual, except that each code byte comes out logical- cuit remains active. While the 87C51 is in this mode,
ly X-NORed with one of the 32 key,bytes. The key an emulator or test CPU can be used to drive the
bytes are gone through in sequence. Therefore, to circuit. Normal operation is restored when a normal
read the' ROM code, ona has to know the 32 key reset is applied.
bytes in their proper seque~ce.
7-150
intJ 87C51/87C51-1/87C51-2
ABSOLUTE MAXIMUM RATINGS· NOTICE: This data sheet contains preliminary infor-
mation on new products in production. The specifica-
Ambient Temperature Under Bias .... O°C to + 70°C tions are subject to change without notice.
Storage Temperature ..•......• - 65°C to + 150°C • WARNING: Stressing the device beyond the "Absolute
Voltage on EAlVpp Pin to VSS .•...•. OV to + 13.0V Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
Voltage on Any Other Pin to VSS .. -0.5V to + 6.5V "Operating Conditions" is not recommended and ex-
Maximum IOL per I/O Pin .•...•.••....•.... 15 mA tended exposure beyond the "Operating Conditions"
may affect device reliability.
Power Dissipation: .•...•..•................ 1.5W
(Based on package heat transfer limitations, not de-
vice power consumption).
D.C. CHARACTERISTICS: (TA = O°C to + 70°C; Vee = 5V ± 10%; VSS = OV)
Symbol Parameter Min Typ(1) Max Unit Test Conditions
VIL Input Low Voltage (Except EA) -0.5 .2Vcc-· 1 V
VIL1 Input Low Voltage to EA 0 .2Vcc-·3 V
VIH Input High Voltage (Except XT AL 1, RST) .2Vcc+·9 Vcc+·5 V
VIH1 Input High Voltage (XTAL 1, RST) 0.7Vcc Vcc+·5 V
VOL O\ltp\lt Low Voltage (Ports 1, 2, 3) (7) 0.45 . V IOL = 1.6 mA (2)
VOL1 Output Low Voltage (Port 0, ALE, PSEN) (7) 0.45 V IOL = 3.2 mA (2)
VOH O\ltput High Voltage (Ports 1, 2, 3, ALE, PSEN) 2.4 V IOH = -60 ",A
.75Vcc V IOH = -25 ",A
'.
.9Vcc V IOH = -10 ",A
VOH1 Output High Voltage (Port 0 in 2.4 V IOH = -800",A
.75Vcc V IOH = -300 ",A
External Bus Mode) V IOH = -80 ",A (3)
.9Vcc
IlL Logical 0 Input Current (Ports 1, 2, 3) -50 ",A VIN = 0.45 V
ITL LogicaI1-to-0 transition current -650 ",A (4)
(Ports 1, 2, 3)
III Input Leakage Current (Port 0) ±10 ",A VIN = VIL or VIH
Icc. Power Supply Current:
Active Mode@ 12 MHz (5) 11.5 25 mA
Idle Mode @ 12 MHz (5) 1.3 4 mA (6)
Power Down Mode 3 50 ",A
RRST Internal Reset Pulldown Resistor 50 300 kO
CIO Pin Capacitance 1() pF
NOTES:
1. "Typicals" are based on a limited number of samples taken from early manufacturing lots and are not guaranteed. The
values listed are at room temp, 5V.
2. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports
1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1-
to-O transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may
exceed 0.8V. In such cases it may be desirable to qualify ALE with a Schmit! Trigger, or use an address latch with a Schmit!
Trigger STROBE input. .
3. Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily filii below the 0.9Vcc specifi-
cation when the address bits are stabilizing. .
4. Pins of Ports 1, 2, and 3 source a transition current when they are being externally driven from 1 to O. The transition
current reaches its maximum value when VIN is approximately 2V.
5. IccMAX at other frequencies is given by:
Active Mode: IccMAX = 0.94 x FREQ.+ 13.71
Idle Mode: IccMAX = 0.14 x FREQ + 2.31
where FREQ is the external oscillator frequency in MHz. IccMAX is given in mAo See Figure 5.
7-151
inter 87C51/87C51-1/87C51-2
6. See Figures 6 through 9 for Icc test conditions. Minimum Vcc for Power Down is 2V.
7. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL perport pin: 10 mA
Maximum IOL per a-bit port-
PortO: 26 mA
Ports 1, 2, and 3: 15 .mA
Maximum totalloL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification.
Pins are not guaranteed to sink greater than the listed test conditions.
30,---,---,--,---,
WAX
ACTIVE WODE
25f--f--+----,/(----j
RST
XTAL2
15""'--t--t---\-~ r~~~ WODE
XTAL1
VSS
270147-18
101---t--t-r.--\---l
Figure 7. Icc Test Condition, Idle Mode.
All other pins are disconnected.
l---bI'-t---\---::::IMAX
IDLE WODE
TYP(I)
~=l:::==t:::r:=:J IDLE MODE
4_ 8_ 12101Hz 16_
FREQ AT XTAL 1
270147-16
Figure 5_ Icc vs. FREQ_ Valid only
within frequency specifications of the
device under test. XTAL2
XTALI
Vss
270147-20
Figure 9. Icc Test Condition, Power Down
Mode. All other pins are disconnected.
Vcc = 2V to 5.5V.
270147-17
Figure 6. Icc Test Condition, Active Mode.
All other pins are disconnected.
270147-19
Figure 8. Clock Signal Waveform for
Icc tests in Active and Idle Modes.
TCLCH = TCHCL = 5 ns.
7-152
87C51/87C51-1/87C51-2
EXPLANATION OF THE AC SYMBOLS L:Logic level LOW, or ALE.
P:PSEN.
Each timing symbol has 5 characters. The first char- O:Output data.
acter is always a 'T' (stands for time). The other R:RD signal.
characters, depending on their positions, stand for T:Time.
the name of a signal or the logical status of that V:Valid.
signal. The following is a list of all the characters and W:WR signal.
what they stand for. X:No longer a valid logic level.
Z:Float.
A:Address.
C:Clock. For example,
D:lnput data.
H:Logic level HIGH. TAVLL = Time from Address Valid to ALE Low.
1:lnstruction (program memory contents). TLLPL = Time from ALE Low to PSEN Low.
A.C. CHARACTERISTICS: (TA = O°C to + 70°C; Vee = 5V ± 10%; Vss = OV; Load Capacitance for
Port 0, ALE, and PSEN = 100 pF; Load Capacitance for All Other Outputs = 80 pF)
EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS
12 MHz Oscillator Variable Oscillator
Symbol Parameter Units
Min Max Min Max
1/TCLCL Oscillator Frequency
87C51 3.5 12 MHz
87C51-1 3.5 16
87C51-2 0.5 12
TLHLL ALE Pulse Width 127 2TCLCL-40 ns
TAVLL Address Valid to ALE Low 28 TCLCL-55 ns
TLLAX Address Hold After ALE Low 48 TCLCL-35 ns
TLLlV ALE Low to Valid Instr In 234 4TCLCL-100 ns
TLLPL ALE Low to PSEN Low 43 TCLCL-40 ns
TPLPH PSEN Pulse Width 205 3TCLCL-45 ns
TPLIV PSEN Low to Valid Instr In 145 3TCLCL-105 ns
TPXIX Input Instr Hold After PSEN 0 0 ns
TPXIZ Input Instr Float After PSEN 59 TCLCL-25 ns
TAVIV Address to Valid Instr In 312 5TCLCL-105 ns
TPLAZ PSEN Low to Address Float 10 10 ns
TRLRH RD Pulse Width 400 6TCLCL-100 ns
TWLWH WR Pulse Width 400 6TCLCL-100 ns
TRLDV RD Low to Valid Data In 252 5TCLCL-165 ns
TRHDX Data Hold After RD 0 0 ns
TRHDZ Data Float After RD 97 2TCLCL-70 ns
TLLDV ALE Low to Valid Data In 517 8TCLCL-150 ns
TAVDV Address to Valid Data In 585 9TCLCL-165 ns
TLLWL ALE Low to RD or WR Low 200 300 3TCLCL-50 3TCLCL+50 ns
TAVWL Address to RD or WR Low 203 4TCLCL-130 ns
TOVWX Data Valid to WR Transition 23 TCLCL-60 ns
TWHOX Data Hold After WR 33 TCLCL-50 ns
TRLAZ RD Low to Address Float 0 0 ns
TWHLH RD or WR High to ALE High 43 123 TCLCL-40 TCLCL+40 ns
7-153
intJ 87C51/87C51-1/87C51-2
ALE _ _J
PORT 0 _ _..I
PORT 2 _ _ _..I A8-A15
270147-5
External Program Memory Read Cycle
ALE
PSEN
I----TLLDV-----t'!
--..J---- TRLRH ---I
RD.
PORTO INSTR. IN
PORT 2 P2.0-P2.7 OR A8"'A15 FROt.! DPH A8-A 15 FROt.! PCH
270147-6
External Data Memory Read Cycle .
ALE
PSEN
--->l---- TWLWH - - - + I
PORTO DATA OUT INSTR. IN
PORT2 P2.0-P2.7 OR A8-A15 FROt.! DPH A8-A 15 FROt.! PCH
270147-7
External Data Memory Write Cycle
7-154
intJ 87C51/87C51-1/87C51-2
EXTERNAL CLOCK DRIVE EXTERNAL CLOCK DRIVE WAVEFORM
Symbol Parameter Min Max Units
1/TCLCL Oscillator Frequency
B7C51 3.5 12 MHz
B7C51-1 3.5 16
B7C51-2 0.5 12
TCHCX High Time 20 ns 270147-8
TClCX low Time 20 ns
TClCH Rise Time 20 ns
TCHCl Fall Time 20 ns
SERIAL PORT TIMING-SHIFT REGISTER MODE
12MHz
Variable Oscillator
Symbol Parameter Oscillator Units
Min Max Min Max
TXlXL Serial Port Clock Cycle Time 1.0 12TClCl J-Ls
TQVXH Output Data Setup to Clock Rising Edge 700 1OTCLCl -133 ns
TXHQX Output Data Hold After Clock ~ising Edge 50 2TClCL-117 ns
TXHDX Input Data Hold After Clock Rising Edge 0 0 ns
TXHDV Clock Rising Edge to Input Data Valid 700 1OTCLCl -133 ns
SHIFT REGISTER MODE TIMING WAVEFORMS
INSTRUCTION I 4 5
ALE
CLOCK
OUTPUT DATA
\
WRITE TO SBur
INPUT DATA - - - - - - . , . - - . . , - - .
'--_,,'-..J
\ I
CLEAR RI SET RI
270147-9
A.C. TESTING:
=x x==
INPUT, OUTPUT WAVEFORMS FLOAT WAVEFORM
Vee-o.S 0.2 VCc+0.9 .
0.45 V _...0_._2_VC
; ;,;c;.,-_0._1____ .
270147-10 270147-11
For timing purposes a port pin is no longer floating when a 100
AC inputs during testing are driven at Vee - 0.5 for a Logic "1" mV change from load voltage occurs. and begins to float when a
and 0.45V for a Logic "0." Timing measurements are made at VIH 100 mV change from the loaded VOHIVOL level occurs. IOL/IOH
min for a Logic "1" and VIL max for a LogiC "0". ;, ±20 rnA.
7-155
inter 87C51/87C51-1/87C51-2
EPROM CHARACTERISTICS to identify the device. The signature bytes identify
the device as an 87C51 manufactured by Intel.
The 87C51 is programmed by a modified Quick-
Pulse ProgrammingTM algorithm. It differs from older Table 2 shows the logic levels for reading the signa-
methods in the value used for Vpp (Programming ture byte, and for programming the Program Memo-
Supply Voltage) and in the width and number of the ry, the Encryption Table, and the Lock Bits. The cir-
ALE/PROG pulses. cuit configuration and waveforms for Quick-Pulse
Programming™are shown in Figures 10 and 11.
The 87C51 contains two signature bytes that can be Figure 12 shows the circuit configuration for normal
read and used by an EPROM programming system Program Memory verification.
Table 2. EPROM Programming Modes
ALE! EAt
MODE RST PSEN P2.7 P2.6 P3.7 P3.6
PROG Vpp
.Read Signature 1 0 1 1 0 0 0 0
Program Code Data 1 0 ·0' Vpp 1 0 1 1
Verify Code Data 1 0 1 1 0 0 1 1
Pgm Encryption Table 1 0 O· Vpp 1 0 1 0
Pgm Lock Bit 1 1 0 O· Vpp 1 1 1 1
Pgm Lock Bit 2 1 0 O· Vpp 1 1 O. 0
NOTES:
"1" = Valid high for that pin
"0" =. Valid low for that pin
Vpp = 12.7SV ± 0.2SV
Vee = SV ± 10% during programming and verification
• ALE/PROG receives 25 programming pulses while Vpp is held at 12:75V. Each programming pulse is low for 100 ,.S( ± 10
,.S) and high for a minimum of 10 ,.S.
+5V
vce
AO-A7 P1 PO v-_PG_M_DATA
RST EA/Vpp 1+---+12.75V
ALE/PROG ....- - 2 5 100jLs PULSES TO GND
P3.6
PSEN 1+---0
87C51
P3.7
P2.7
P2.6 1+--0
L........._~-I XTAL1 P2.0 /L--A8-_A 11
-P2.3
vss.
270147-12
Figure 10. Programming Configuration
7-156
87C51/87C51-1/87C51-2
1 "'I'~----- 25 PULSES
'I
ALE/PROG:~-----~
'-------'
~ 10).Ls MINi I' 100I::S
:t 10).LS
'I
ALE/PROG:
01 n n 270147-13
Figure 11. PROG Waveforms
Quick-Pulse Programming™ through 1 FH, using the "Pgm Encryption Table" lev-
els. Don't forget that after the Encryption Table is
The setup for Microcontroller Quick·Pulse Program· programmed, verify cycles will produce only encrypt-
mingTM is shown in Figure 10. Note that the 87C51 ed data.
is running with a 4 to 6 MHz oscillator. The reason
the oscillator needs to be running is that the device To program the Lock Bits, repeat the 25-pulse pro-
is executing internal address and program data gramming sequence using the "Pgm Lock Bit" lev-
transfers. els. After one Lock Bit is programmed, further pro-
gramming of the Code Memory and Encryption Ta-
The address of the EPROM location to be pro· ble is disabled. However, the other Lock Bit can still
grammed is applied to Ports 1 and 2, as shown in be programmed.
Figure 10. The code byte to be programmed into
that location is applied to Port O. RST, PSEN, and Note that the EA/vpp pin must not be allowed to go
pins of Ports 2 and 3 specified in Table 2 are held at above the maximum specified Vpplevel. for any
the "Program Code Data" levels indicated in Table amount of time. Even a narrow glitch above that volt-
2. Then ALE/PROG is pulsed low 25 times as age level can cause permanent damage lothe de-
shown in Figure 11. vice. The Vpp. source should.be.weil regulated and
free of glitches and overshoot.
To program the Encryption Table, repeat the 25·
pulse programming sequence for addresses 0
7-157
inter 87C51/87C51-1/87C51-2
+sv
J---I-l\' PGM
AO-A7 PI PO
r-----v DATA
RST EA/Vpp
ALE/PROG
P3.6
PSEN 1+---0
B7eSl
P3.7
P2.7 1+---0 (ENABLE)
XTAL2 P2.6 1+--0
L-.--+_~~ XTAL 1 P2.0 /'--A~8--A 11
-P2.3
VSS
270147-14
Figure 12. Program Verification
Program Verification Program/Verify Algorithms
If Lock Bit 2 has not been programmed, the on-chip Any algorithm in agreement with the conditions list"
Program Memory can be read out for program verifi- ed in Table 2, and which satisfies the timing specifi;
cation.The address of the Program Memory location cations, is suitable.
to be read is applied to Ports 1 and 2 as shown in
Figure 12. The other pins are held at the "Verify
Code Data" levels indicated in Table 2. The con- Erasure Characteristics
tents of the addressed location will be emitted on
Port O. External pull ups are required on Port 0 for Erasure of the EPROM begins to occur when the
this operation. Detailed timing specifications are chip is exposed to light with wavelengths shorter
shown in later sections of this data sheet. than approximately 4,000 Angstroms. Since sunlight
and fluorescent lighting have wavelengths in this
If the Encryption Table has been programmed, the range, exposure to these light sources over an ex-
data presented at Port 0 will be the Exclusive NOR tended time (about 1 week in sunlight, or 3 years in
of the program byte with one of the encryption bytes. room level f!,!orescent lighting) could cause inadver-
The user will have to know the Encryption Table tent erasure. If an application subjects the device to
contents in order to correctly decode the verification this type of exposure, it is suggested that an opaque
data. The Encryption Table itself can not be read label be placed over the window.
out.
The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to an integrat-
Reading the Signature Bytes ed dose of at least 15 W-sec/cm 2 . Exposing the
EPROM to an ultraviolet lamp of 12,000 ,."W/cm2
The signature bytes are read by the same procedure rating for 30 minutes, at a distance of about 1 inch,
as a normal verification of locations 030H and 031 H, should be sufficient.
except that P3.6 and P3.7 need to be pulled to a
logic low. The values returned are: Erasure leaves the array in an all 1s state.
(030H) = 89H indicates manufactured by Intel
(031H) = 57H indicates 87C51
7-158
87C51/87C51-1/87C51-2
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS:
(TA = 21°C to 27°C, Vee = 5V ±10%, VSS = OV)
Symbol Parameter Min Max Units
Vpp Programming Supply Voltage 12.5 13.0 V
Ipp Programming Supply Current 50 mA
1/TCLCL Oscillator Frequency 4 6 MHz
TAVGL Address Setup to PROG Low 48TCLCL
TGHAX Address Hold After PROG 48TCLCL
TDVGL Data Setup to PROG Low 48TCLCL
TGHDX Data Hold After PROG 48TCLCL
TEHSH P2.7 (ENABLE) High to Vpp 48TCLCL
TSHGL Vpp Setup to PROG Low 10 !,-S
TGHSL Vpp Hold After PROG 10 !,-S
TGLGH PROGWidth 90 110 !,-S
TAVOV Address to Data Valid 48TCLCL
TELOV ENABLE Low to Data Valid 48TCLCL
TEHOZ Data Float After ENABLE 0 48TCLCL
TGHGL PROG High to PROG Low 10 !,-S
EPROM Programming and Verification Waveforms
PROGRAMMING· VERIFICATION·
P1.0-Pl.7
ADDRESS ADDRESS
P2.0-P2.3
-TAVQV
0
PORT 0 DATA IN DATA OUT
TDVGL:C~ r- TGHDX
TAVGL ~ TGHAX
-~~
ALE/PROG
TSHGL - ..... TGLGH
- 1_
TGHGL
_ TGHSL
I LOGIC 1 LOGIC 1
- - - - - r - - - - - - - !;2.G!£..D_ - - - ---- ------
P2.7
(ENABLE) - - - "
-
! TEHSH TELOV-
- I--TEHOZ
270147-15
'FOR PROGRAMMING CONDITIONS SEE FIGURE 10.
FOR VERIFICATION CONDITIONS SEE FIGURE 12.
DATA SHEET REVISION SUMMARY
The following are the key differences between this and the -004 version of the 87C51 BH data sheet:
1. Package table was added.
2. Note 7 on maximum current specifications added to DC Characteristics.
3. Data Sheet Revision Summary was added.
7-159
87C51
EXPRESS
• Extended Temperature Range • 3.5 MHz to 12 MHz Vee = 5V ± 10%
• Burn-In
The Intel EXPRESS system offers enhancements to the operational specifications of the MCS®-51 family of
microcontrollers. These EXPRESS products are designed to meet the needs of those applications whose
operating requirements exceed commercial standards.
The EXPRESS program includes the commercial standard temperature range with burn-in and an extended
temperature range with or without burn-in.
With the commercial standard temperature range, operational characteristics are guaranteed over the temper-
ature range of O·C to + 70·C. With the extended temperature range option, operational characteristics are
guaranteed over the range of - 40·C to + 85·C.
The optional burn-in is dynamic for a minimum time of 160 hours at 125·C with Vee = 6.9V ±0.25V, following
guidelines in MIL-STD-883, Method 1015.
Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part number. The
prefixes are listed in Table 1.
For the extended temperature range option, this data sheet specifies the parameters which deviate from their
commercial temperature range limits. The commercial temperature range data sheets are applicable for all
parameters not listed here.
September 1988
7-160 Order Number: 270430-002
87C51 EXPRESS
Electrical Deviations from Commercial Specifications
for Extended Temperature Range
D.C. and A.C. parameters not included here are the same as in the commercial temperature range data
sheets.
D.C. CHARACTERISTICS TA = -40°C to + 85°C; Vee = 5V ±10%;Vss = OV
Limits Test
Symbol Parameter Unit
Min Max Conditions
VIL Input Low Voltage (Except EA) -0.5 0.2Vee - 0.15 V
VIL1 EA 0 0.2Vec - 0.35 V
VIH Input High Voltage (Except XTAL 1, RST) 0.2Vee +1 Vce + 0.5 V
VIH1 Input High Voltage to XTAL 1, RST 0.7Vee + 0.1 Vee +0.5 V
IlL Logical 0 Input Current (Port 1, 2, 3) -75 /LA VIN = 0.45V
ITL Logical 1 to 0 transition -750 /LA VIN = 2.0V
Current (Ports 1, 2, 3)
Icc Power Supply Current (Note 1)
Active Mode 35 rnA
Idle Mode 6 mA
Power Down Mode 50 /LA
NOTE:
1. Vee = 4.5V-5.5V, Frequency Range = 3.5 MHz-12 MHz.
7-161
inter 87C51 EXPRESS
Table 1. Prefix Identification
Prefix Package Type Temperature Range(2) Burn-ln(3)
P Plastic Commercial No
D Cerdip Commercial No
N PLCC Commercial No
TP Plastic Extended No
TO Cerdip Extended No
TN PLCC Extended No
OP Plastic Commercial Yes
OD Cerdip Commercial Yes
ON PLCC Commercial Yes
LP Plastic Extended Yes
LD Cerdip Extended' Yes
LN PLCC Extended Yes
NOTES:
2. Commercial temperature range is O"C to + 70"C. Extended temperature range is - 40"C to + 85"C.
3. Burn-in is dynamic for a minimum time of 160 hours at + 125"C. Vee = 6.9V ± 0.25V. following guidelines in MIL-STO-
883 Method 1015 (Test Condition -0).
Examples:
P87C51 indicates 87C51 in a plastic package and specified for commercial temperature range. without burn-in.
LD87C51 indicates 87C51 in a cerdip package and specified for extended temperature range with burn-in.
7-162
80C52/80C32
CHMOS SINGLE-CHIP 8-BIT MICROCOMPUTER
80C52-8K Bytes of Factory Mask Programmable ROM
80C32-CPU with RAM and I/O
80C521S0C32-3.5 MHz to 12 MHz, Vee = 5V ±20%
80C52-1/S0C32-1-3.5 MHz to 16 MHz, Vee = 5V ± 20%
• Three 16-Bit Timer/Counters • TTL and CMOS Compatible Logic
- Timer 2 is an Up/Down Levels
Timer/Counter and Capture
• 64K External Program Memory Space
• Power Off Flag • 64K External Data Memory Space
• 256 Bytes of On-Chip Data RAM • MCS®-51 Fully Compatible Instruction
• Boolean Processor Set
• 32 Programmable I/O Lines • Power Saving Idle and Power Down
Modes
• 6 Interrupt Sources
• Programmable Serial Channel with: • ONCETM (On-Circuit Emulation) Mode
- Framing Error Detection
- Automatic Address Recognition
MEMORY ORGANIZATION
PROGRAM MEMORY: Up to 8K bytes of the program memory can reside in the on-chip ROM (80C52 only). In
addition the device can address up to 64K of program memory external to the chip.
DATA MEMORY: This microcontrolier has a 256 x 8 on-chip RAM. In addition it can address up to 64K bytes of
external data memory.
The Intel 80C52 is a single-chip control oriented microcontrolier which is fabricated on Intel's reliable
CHMOS III technology. Being a member of the 8051 family, the 80C52 uses the same powerful instruction set,
has the same architecture, and is pin for pin compatible with the existing MCS-51 products. The 80C52 is an
enhanced version of the 80C51 BH. It's added features make it an even more powerful microcontrolier for
applications that require up/down counting capabilities such as motor control or a more versatile serial chan-
nel to facilitate multi-processor communications.
For the remainder of this document, the 80C52 and 80C32 will be referred to as the 80C52.
July 1989
7-163 Order Number: 270757-002
80C52/80C32
-,
z
PSEN
~ f5
.."''''~~===;~=====~~======!=~==~~~=)1
TIMING
ALE/PROG
EIi/VPP
RST
AND
CONTROL g 81'
i!:
..
XTAL1
- _...
P1.0-P1.7 P3.0- P3.7
270757-1
Figure 1. 80C52 Block Diagram
7-164
80C52/80C32
PACKAGES PIN DESCRIPTIONS
Part Prefix Package Type Vee: Supply voltage.
80C52 P 40-Pin Plastic DIP
80C32 D 40-Pin CERDIP Vss: Circuit ground.
N 44-Pin PLCC Port 0: Port 0 is an 8-bit, open drain, bidirectional I/O
port. As an output port each pin can sink several LS
TTL inputs. Port 0 pins that have 1's written to them
float, and in that state can be used as high-imped-
(T2) P1.0 Vee ance inputs.
(T2EX) po.O (AOO)
PO.1 (AD1)
Port 0 is also the multiplexed low-order address and
PO.2 (AD2)
data bus during accesses to external Program and
PO.3 (AD3)
Data Memory. In this application it uses strong inter-
Pl.S PO.4 (AD4)
nal pullups when emitting1 's, and can source and
Pl.S PO.S (ADS)
sink several LS TTL inputs.
PO.S (ADS)
RESET PO.7 (A07)
Port 0 outputs the code bytes during program verifi-
(RXD) P3.0 EA
cation on the 80C52. External pullup resistors are
(TXD) P3.1 ALE
(INTO) P3.2 PSEN
required during program verification.
(INT1) P3.3 P2.7 (A1S)
(TO) P3.4 P2.S (A14)
Port 1: Port 1 is an 8-bit bidirectional I/O port with
(T1) P3.S P2.S (A13)
internal pull ups. The Port 1 output buffers can drive
(WR) P3.S P2.4 (A12) LS TTL inputs. Port 1 pins that have 1's written to
(RO) P3.7 P2.3 (A11) them are pulled high by the internal pullups, and in
XTAL2 P2.2 (A10) that state can be used as inputs. As inputs, Port 1
XTAL1 P2.1 (A9) pins that are externally being pulled low will source
Vss P2.0 (A8) current (IlL, on the da~a sheet) because of the inter-
. nal pullups.
270757-2
DIP In addition, Port 1 serves the functions of the follow-
ing special features of the 80C52:
~ t"! "! ""': q u q ""': "! '"1
INDEX
CORNER
0: c::: a:: a: 0..
u
~ >
0
n.
0 0 0
a.. a.. a..
~~~~~~~~~~ Port Pin Alternate Function
PO.4
P1.0 T2 (External Count Input to
Pl.6 PO.S
Timer/Counter 2)
Pl.7 PO.6
RST PO.7 P1.1 T2EX (Timer/Counter 2
EA Capture/Reload Trigger
NC He and Direction Control)
P3.1 ALE
P3.2 PSEN
Port 1 receives the low-order address bytes during
P3.3 P2.7
ROM verification.
P3.4 P2.6
P3.5 P2.S
Port 2: Port 2 is an 8-bit bidirectional I/O port with
internal pullups. The Port 2 output buffers can drive
LS TTL inputs. Port 2 pins that have 1's written to
them are pulled high by the internal pull ups, and in
270757-3 that state can be used as inputs. As inputs, Port 2
PLCC pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the inter-
Figure 2. Pin Connections nal pullups.
7-165
infef SOC52/S0C32
Port 2 emits the high-order address byte during When the 80C52 is executing code from external
fetches from external Program Memory and during Program Memory, PSEN is activated twice each ma-
accesses to external Data Memory that use 16-bit chine cycle, except that two PSEN activations are
addresses (MOVX @DPTR). In this application it skipped during each access to external Data Memo-
uses strong internal pull ups when emitting 1's. Dur- ry.
ing accesses to external Data Memory that use 8-bit
addresses (MOVX @Ri), Port 2 emits the contents of EAlVpp: .External Access enable. EA must be
the P2 Special Function Register. strapped to VSS in order to enable the device to
fetch code from external Program Memory locations
Some Port 2 pins receive the high-order address bits OOOOH to OFFFFH.
during program verification.
EA should be strapped to Vee for internal program
Port 3: Port 3 is an 8-bit bidirectional 1/0 port with executions.
internal pull ups. The Port 3 output buffers can drive
LS TTL inputs. Port 3 pins that have 1's written to XTAL 1: Input to the inverting oscillator amplifier.
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 3 XTAL2: Output from the inverting oscillator amplifier.
pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the pull-
ups. OSCILLATOR CHARACTERISTICS
Port 3 also serves the functions of various special XTAL 1 and XTAL2 are the input and output, respec-
features of the MCS-51 Family, as listed below: tively, of a inverting amplifier which can be config-
ured for use as an on-chip oscillator, as shown in
Figure 3. Either a quartz crystal or ceramic resonator
Port Pin Alternate Function
may be used. More. detailed information concerning
P3.0 RXD (serial input port) the use of the on-chip oscillator is available in Appli"
P3.1 TXD (serial output port) cation Note AP-155, "Oscillators for Microcontrol"
P3.2 INTO (external interrupt 0) lers."
P3.3 INT1 (external interrupt 1)
To drive the device from an external clock source,
P3.4 TO (Timer 0 external input)
XTAL1 should be driven, while XTAL2 floats, as
P3.5 T1 (Timer 1 external input) shown in Figure 4. There are no requirements on the
P3.6 WR (external data memory write strobe) duty cycle of the external clock signal, since the in-
P3.7 RD (external data memory read strobe) put to the internal clocking circuitry is through a di-
vide-by-two flip-flop, but minimum and maximum
RST: Reset input A high on this pin for two machine high and low times specified on the data sheet must
cycles while the oscillator is running resets the de- be observed.
vice. An internal pulldown resistor permits a power-
on reset with only a capacitor connected to Vee.
C2
ALE: Address Latch Enable output pulse for latching 1--f---4 XTAL 2
the low byte of the address during accesses to ex-
ternal memory. . D
In normal operation ALE is emitted at a constant 1--~--4 XTAL 1
rate of % the oscillator frequency, and may be used t - - - - - - - I Vss
for external timing or clocking purposes. Note, how-
ever, that one ALE pulse is skipped during each ac-
cess to external Data Memory. 270757-4
C1, C2 ~ 30 pF ± 10 pF for Crystals
= 10 pF for Ceramic Resonators
PSEN: Program Store Enable is the read strobe to
external Program Memory. Figure 3. Oscillator Connections
7-166
SOC521S0C32
held active long enough for the oscillator to restart
and stabilize (normally less than 10 ms).
N/C XTAL2
With an external interrupt, INTO and INT1 must be
enabled and configured as level-sensitive. Holding
EXTERNAL
OSCILLATOR XTAL 1
the pin low restarts the oscillator but bringing the pin
SIGNAL back high completes the exit. Once the interrupt is
serviced, the next instruction to be executed after
RETI will be the one following the instruction that put
the device into Power Down.
270757-9
Figure 4. External Clock Drive Configuration DESIGN CONSIDERATION
• When the idle mode is terminated by a hardware
IDLE MODE reset, the device normally resumes program exe-
cution, from where it left off, up to two machine
The user's software can invoke the Idle Mode. When cycles before the internal reset algorithm takes
the microcontroller is in this mode, power consump- control. On-chip hardware inhibits access to inter-
tion is reduced. The Special Function Registers and nal RAM in this event, but access to the port pins
the on board RAM retain their values during Idle, but is not inhibited. To eliminate the possibility of an
the processor stops executing instructions. Idle unexpected write when Idle is terminated by re-
Mode will be exited if the chip is reset or if an en- set, the instruction following the one that invokes
abled interrupt occurs. Idle should not be one that writes to a port pin or
to external memory.
• Writing to unspecified SFR's (see Table 3) may
POWER DOWN MODE cause unpredictable operation.
To save even more power, a Power Down mode can
be invoked by software. In this mode, the oscillator ONCETM MODE
is stopped and the instruction that invoked Power
Down is the last instruction executed. The on-chip The ONCE ("On-Circuit Emulation") Mode facilitates
RAM and Special Function Registers retain their val- testing and debugging of systems using the 80C52
ues until the Power Down mode is terminated. without the 80C52 having to be removed from the
circuit. The ONCE Mode is invoked by:
On the 80C52 either a hardware reset or an external
1) Pull ALE low while the device is in reset and
interrupt can cause an exit from Power Down. Reset
PSEN is high;
redefines all the SFRs but does not change the on-
chip RAM. An external interrupt allows both the 2) Hold ALE low as RST is deactivated.
SFRs and on-chip RAM to retain their values.
While the device is in ONCE Mode, the Port 0 pins
To properly terminate Power Down the reset or ex- go into a float state, and the other port pins and ALE
ternal interrupt should not be executed before VCC is and PSEN are weakly pulled high. The oscillator cir-
restored to its normal operating level and must be cuit remains active. While the 80C52 is in this mode,
an emulator or test CPU can be used to drive the
circuit. Normal operation is restored when a normal
reset is applied.
Table 1. 'Status of the External Pins during Idle and Power Down
Program
Mode ALE PSEN PORTO PORT1 PORT2 PORT3
Memory
Idle Internal 1 1 Data Data Data Data
Idle External 1 1 Float Data Address Data
Power Down Internal 0 0 Data Data Data Data
Power Down External 0 0 Float Data Data Data
NOTE:
For more detailed information on the reduced power modes refer to current Embedded Controller Handbook. and Applica-
tion Note AP-252, "Designing with the 80C51 BH."
7-167
inter 80C52/80C32
ABSOLUTE MAXIMUM RATINGS* NOTICE: This data sheet contains preliminary infor-
mation on new products in production. The specifica-
Ambient Temperature Under Bias .... O°C to + 70°C tions are subject to change without notice.
Storage Temperature .......... - 65°C to + 150°C • WARNING: Stressing the device beyond the "Absolute
Voltage on EAlVpp Pin to Vss ........ OV to + 6.5V Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
Voltage on Any Other Pin to Vss .. - 0.5V to + 6.5V "Operating Conditions" is not recommended and ex-
Maximum IOL per 1/0 Pin .................. 15 mA tended exposure beyond the "Operating Conditions"
may affect device reliability.
Power Dissipation .......................... 1.5W
(based on PACKAGE heat transfer limitations, not
device power consumption)
D.C. CHARACTERISTICS: TA = O°Cto + 70°C; Vee = 5V ±20%;Vss = OV
Typical
Symbol Parameter Min Max Unit Test Conditions
(4)
VIL Input Low Voltage (Except EA) -0.5 0.2Vee- 0.1 V
VIL1 Input Low Voltage EA 0 . 0.2 Vee-0.3 V
VIH Input High Voltage 0.2 Vee + 0.9 Vee+ 0.5 V
(Except XTAL 1, RST)
VIH1 Input High Voltage 0.7 Vee Vee+ 0.5 V
(XTAL 1, RST)
VOL Output Low Voltage (5) 0.3 V IOL = 100 p.A
(Ports 1, 2 and 3, ALE/PROG, PSEN) 0.45 V IOL = 1.6 mA (1 )
1.0 V IOL = 3.5mA
VOL1 Output Low Voltage (5) 0.3 V IOL = 200 p.A
(Port 0) 0.45 V IOL = 3.2mA (1 )
1.0 V IOL = 7.0mA
VOH Output High Voltage Vee- 0.3 V IOH = -10 p.A
(Ports 1, 2 and 3 Vee- 0.7 V IOH = -30 p.A (2)
ALE/PROG and PSEN) Vee- 1.5 V IOH = -60 p.A
VOH1 Output High Voltage Vee- 0.3 V IOH = -200 p.A
(Port 0 in External Bus Mode) Vee- 0.7 V IOH = -3.2 mA (2)
Vee- 1.5 V IOH = -7.0 mA
IlL Logical 0 Input Current -10 -50 p.A VIN = 0.45V
(Ports 1, 2, and 3)
III Input leakage Current 0.02 ±10 p.A 0< VIN < Vee
(Port 0)
ITL Logical 1 to 0 Transition Current -265 -650. p.A VIN = 2V
(Ports 1, 2, and 3)
RRST RST Pulldown Resistor 40 100 225 K!1
CIO Pin Capacitance 10 pF (Note 6)
lee Power Supply Current:
Running al12 MHz (Figure 5) 15 30 mA
(Note 3)
Idle Mode at 12 MHz (Figure 5) 5 7.5 mA
Power Down Mode 5 75 p.A
7-168
inter 80C52180C32
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports
1, 2, and 3. The noise is due to external bus capacitance discharging into the PO.rt 0 and Port 2 pins when these pins make
1 to 0 transitions during bus operations. In applications where capacitance loading exceeds 100 pFs, the noise pulse on the
ALE signal may exceed 0.8V. In these cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an Address
Latch with a Schmitt Trigger Strobe input.
2. Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the 0.9 VCC specification when the
address lines are stabilizing.
3. See Figures 6-9 for test conditions. Minimum VCC for power down is 2V.
4. Typicals are based on limited number of samples, and are not guaranteed. The values listed are at room temperature and
5V.
5. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port -
Port 0: 26 rnA
Ports 1, 2, and 3: 15 rnA
Maximum total IOL for all output pins: 71 rnA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
6. CIO is the adjacent pin capacitance inherent to the package.
~mAr-------'--------'--------r-----~
vee
vce PO
RST fA
80C52
XTAL2
XTAL1
vss
16MHz -= 270757-11
270757-10
All other pins disconnected
ICC Max at other frequencies is given by:
Active Mode
TCLCH ~ TCHCL = 5 ns
Icc MAX ~ 2.2 x FRED + 3.1
Idle Mode Figure 6. Icc Test Condition, Active Mode
Icc MAX ~ 0.49 x FRED + 1.6
Where FRED is in MHz, IccMAX is given in rnA.
Figure 5_ Icc vs Frequency
RST fA
80C52 -=
XTAL2
XTALl
Vss
270757-13
All other pins disconnected
Figure 8. Icc Test Condition, Power Down Mode.
270757-12 Vcc = 2.0V to 6.0V.
All other pins disconnected
TCLCH ~ TCHCL ~ 5 ns
Figure 7_ Icc Test Condition Idle Mode
0.45V
270757-14
Figure 9. Clock Signal Waveform for Icc Tests in Active and Idle Modes. TCLCH = TCHCL = 5 ns.
7-169
inter SOC52/S0C32
EXPLANATION OF THE AC SYMBOLS L: Logic level LOW, or ALE
P:PSEN
Each timing symbol has 5 characters. The first char- Q: Output Data
acter is always a 'T' (stands for time). The other R: RD signal
characters, depending on their positions, stand for T: Time
the name of a signal or the logical status of that V: Valid
signal. The following is a list of all the characters and W: WR signal
what they stand for. X: No longer a valid logic level
Z: Float
A: Address
C: Clock For example,
D: Input Data
H: Logic level HIGH TAVLL = Time from Address Valid to ALE Low
I: Instruction (program memory contents) TLLPL = Time from ALE Low to PSEN Low
A.C. CHARACTERISTICS TA = O°C to + 70°C, Vee = 5V ±20%, Vss = OV, Load Capacitance for
PortO,ALEandPSEN == 100pF,LoadCapacitanceforAliOtherOutputs = 80pF
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
12 MHz Oscillator Variable Oscillator
Symbol Parameter Units
Min Max Min Max
1/TCLCL Oscillator Frequency
80C52 I 3.5 12 MHz
80C52-1 3.5 16
TLHLL ALE Pulse Width 127 2TCLCL-40 ns
TAVLL Address Valid to ALE Low 43 TCLCL-40 ns
TLLAX Address Hold After ALE Low 53 TCLCL-30 ns
TLLlV ALE Low to Valid Instruction In 234 4TCLCL-100 ns
TLLPL ALE Low to PSEN Low 53 TCLCL-30 ns
TPLPH PSEN Pulse Width 205 3TCLCL-45 ns
TPLIV PSEN Low to Valid Instruction In 145 3TCLCL-105 ns
TPXIX Input Instruction Hold After PSEN 0 0 ns
TPXIZ Input Instruction Float After PSEN 59 TCLCL-25 ns
TAVIV Address to Valid Instruction In 312 5TCLCL-105 ns
TPLAZ PSEN Low tq Address Float 10 10 ns
TRLRH RD Pulse Width 400 6TCLCL-100 ns
TWLWH WR Pulse Width 400 6TCLCL-100 ns
TRLDV RD Low to Valid Data In 252 5TCLCL-165 ns
TRHDX Data Hold After RD 0 0 ns
TRHDZ Data Float After RD 107 2TCLCL-60 ns
TLLDV ALE Low to Valid Data In 517 8TCLCL-150 ns
TAVDV Address to Valid Data In 585 9TCLCL-165 ns
TLLWL ALE Low to RD or WR Low 200 300 3TCLCL-50 3TCLCL+50 ns
TAVWL Address Valid to RD or WR Low 203 4TCLCL-130 ns
TQVWX Data Valid to WR Transition 33 TCLCL-50 ns
TWHQX Data Hold after WR 33 TCLCL-50 ns
TQVWH Data Valid to WR High 433 7TCLCL-150 ns
TRLAZ RD Low to Address Float 0 0 ns
TWHLH RD or WR High toALE High 43 123 TCLCL-40 TCLCL+40 ns
7-170
80C52/80C32
EXTERNAL PROGRAM MEMORY READ CYCLE
ALE _ _..J
PSEN _ _oJ
PORT 0
---
PORT2 _ _ _..J~_ _ _ _~~~_~_ _-,~_ _~A~8~-~A~15~______
270757-15
EXTERNAL DATA MEMORY READ CYCLE
ALE
PSEN
i-----TLLDV 'I
Ro
------I==::.:~~=:::1:-- TRLRH ---I
~---------------
PORTO INSTR. IN
P2.0-P2.7 OR A8-A15 FROM DPH
PORT2 __-J''-________________________________ --' A8-A 15 FROM PCH
270757'-16
7-171
80C52/80C32
EXTERNAL DATA MEMORY WRITE CYCLE
ALE I \. ~
-1-TLHLL-': 4TWHLH
\. ~
r----TLLWL TWLWH
.... TAVLL I- '\ I
-TLLAX- ~ Coo t-TWHQX
TQVWH
PORTO
::r FROtl~i~~ OPL
.... TAVWL
DATA OUT K XAO-A7 FROM PCL INSTR. IN
PORT2
:::::> P2.0-P2.7 OR A8-A15 FROM DPH A8-A 15 FROM PCH
270757-17
A.C. TESTING INPUT
Input, Output Waveforms Float Waveforms
VCC-0.5~ 0.2 VCC+ 0•9 V- TIMING REFERENCE
POINTS
0.45 V ~_0_.2_V..;;.c-,-C_-0_._l_ _ _......1\._ VOL +0.1 V
270757-18 270757-19
AC Inputs during testing are driven at Vee-0.5V for a Logic "1" For timing purposes a port pin is no longer floating when a
and OA5V for a Logic "0". Timing measurements are made at VIH 100 mV change from load voltage occurs, and begins to float
min for a Logic "1" and VOL max for a Logic "0". when a 100 mV change from the loaded VOHIVOL level occurs.
IOLIIOH;" ± 20 rnA.
SERIAL PORT TIMING-SHIFT REGISTER MODE
Test Conditions: TA = O°C to + 70°C; Vee = 5V ± 20%; Vss = OV; Load Capacitance = 80 pF
12 MHz Oscillator Variable Oscillator
Symbol Parameter Units
Min Max Min Max
TXLXL Serial Port Clock Cycle Time 1 12TCLCL J-Ls
TOVXH Output Data Setup to Clock 700 1OTCLCL -133 ns
Rising Edge
TXHOX Output Data Hold after 50 2TCLCL-117 ns
Clock Rising Edge
TXHDX Input Data Hold After Clock 0 0 ns
Rising Edge
TXHDV Clock Rising Edge to Input 700 1OTCLCL -133 ns
Data Valid
intJ 80C52/80C32
SHIFT REGISTER MODE TIMING WAVEFORMS
EXTERNAL CLOCK DRIVE
Symbol Parameter Min Max Units
l/TClCl Oscillator Frequency MHz
BOC52/BOC32 3.5 12
BOC52-1/BOC32-1 3.5 16
TCHCX High Time 20 ns
TClCX low Time 20 , ns
TClCH Rise Time 20 ns
TCHCl Fall Time 20 ns
EXTERNAL CLOCK DRIVE WAVEFORM
Vee- O•S • - - - - - --r-....-----"""
0.7 Vee
0.4SV ---'C0.2 Vee -O.l TCHCX
TeHCL
270757-6
7-173
infef 80C52180C32
ROM CHARACTERISTICS
Table 2 shows the logic levels for verifying the code data and reading the signature bytes on the 80CS2.
Table 2 ROM Modes
Mode RST PSEN ALE EA P2.7 P2.6 P3.6 P3.7
Verify Code Data 1 0 1 1 0 0 1 1
Read Signature 1 0 1 1 0 0 0 0
NOTES:
"1" = Valid high for that pin
"0" = Valid low for that pin
Program Verification cations will come out on Port o. External pullups are
required on Port 0 for this operation.
The address of the Program Memory location to be
read is applied to Port 1 and pins P2.0-P2.4. The Figure 10 shows the setup for verifying the program
other pins should be held at the "Verify" levels indi- memo~ .
cated in Table 2. The contents of the addressed 10-
+5V
1---&-", PGM
PO DATA
80C52
.--_-~XTAL2 P2.6
L.-........-+~XTAL 1
vss
270757-7
Figure 10. Verifying the ROM
ROM VERIFICATION CHARACTERISTICS
TA = 21°C to 27°C; Vee = SV±O.2SV; Vss = ov
ADVANCED INFORMATION-CONTACT INTEL FOR DESIGN-IN INFORMATION
Symbol Parameter Min Max Units
1/TCLCL Oscillator Frequency 4 6 MHz
TAVQV Address to Data Valid 48TCLCL
TELQV ENABLE Low to Data Valid 48TCLCL
TEHQZ Data Float after ENABLE 0 48TCLCL
7-174
intJ OOC52100C32
ROM VERIFICATION WAVEFORMS
VERIFiCATION
:~:~::~:~ ----_-f(=E~T:~:§::~E~SS~:J)~---
PORT a -----(DATA OUT
m.,1, -
t
} "',.,
P2.7
270757-8
Reading the Signature Bytes
The signature bytes are read by the same procedure as a normal verification of locations 030H and 031 H,
except that P3.6 and P3.7 need to be pulled to a logic low. The values returned are:
(030H) = 89H indicates manufacture by Intel
(031 H) = 53H indicates 80C52
Table 3. 80C52 Special Function Registers
Address Name Reset Value
80H PO' 111111118
81H SP 000001118
82H DPL 000000008
83H DPH 000000008
87H PCON 00XXOOO08
88H TCON' 000000008
89H TMOD 000000008
8AH TLO 000000008
88H TL1 000000008
8CH THO 000000008
8DH TH1 000000008
90H P1' 111111118
98H SCON' 000000008
99H S8UF XXXXXXXX8
OAOH P2' 111111118
OA8H IE' 000000008
OA9H SADDR 000000008
080H P3* 111111118
088H IP* XOOOOOO08
089H SADEN 000000008
OC8H T2CON* 000000008
OC9H T2MOD XXXXXXX08
OCAH RCAP2L 000000008
OC8H RCAP2H 000000008
OCCH TL2 000000008
OCDH TH2 000000008
ODOH psw* 000000008
OEOH ACC' 000000008
OFOH 8' 000000008
• = Bit Addressable
7-175
80C52/80C32
EXPRESS
BOCS2/80C32-3.S MHz to 12 MHz, Vee = SV ± 10%
BOCS2-1/BOC32-1-3.S MHz to 16 MHz, Vee = sv ± 10%
• Extended Temperature Range • Burn-In
The Intel EXPRESS system offers enhancements to the operational specifications of the MCS®-51 family of
microcontrollers. These EXPRESS products are designed to meet the needs of those applications whose
operating requirements exceed commercial standards.
The EXPRESS program includes the commercial standard temperature range with burn-in and an extended
temperature range with or without burn-in.
With the commercial standard temperature range, operational characteristics are guaranteed over the temper-
ature range of O°C to 70°C. With the extended temperature range option, operational characteristics are
guaranteed over the range of - 40°C to + 85°C.
The optional burn-in is dynamic for a minimum time of 168 hours at 125°C with Vee = 6.9V ±0.25V, following
guidelines in MIL-STD-883, Method 1015. .
Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part numbeL The
prefixes are listed in Table 1.
For the extended temperature range option, this data sheet specifies the parameters which deviate from their
commercial temperature range limits. The commercial temperature range data sheets are applicable for all
parameters not listed here.
March 1990
7-176 Order Number: 270868-001
83C52/80C32 EXPRESS
Electrical Deviations from Commercial Specifications for Extended Temperature
Range
D.C. and A.C. parameters not included here are the same as in the commercial temperature range data
sheets.
D.C. CHARACTERISTICS TA = -40°Cto+85°C;Vcc = 5V ±10%;Vss = ov
Limits Test
Symbol Parameter Unit
Min Max Conditions
IlL Logical 0 Input Current (Port 1, 2, 3) -75 /A-A Vin= O.45V
VOH1 Output High Voltage VCC -1.5 V IOH = -S.OmA
(Port 0 in External Bus Mode)
Table 1. Prefix Identification
Prefix Package Type Temperature Range Burn-In
P Plastic Commercial No
0 Cerdip Commercial No
N PLCC Commercial No
TP Plastic Extended No
TO Cerdip Extended No
S Quad Flat Package Commercial No
TS Quad Flat Package Extended No
TN PLCC Extended No
LP Plastic Extended Yes
LD Cerdip Extended Yes
LN PLCC Extended Yes
NOTE:
.• Commercial temperature range is O°C to 70°C. Extended temperature range is - 40°C to + 85°C. .
• Burn-in is dynamic for a minimum time of 16B hours at 125°C, Vcc = 6.9V ±0.25V, following guidelines in MIL'STD-BB3
Method 1015 (Test Condition D).
Examples:
P80C52 indicates 80C52 in a plastic package and specified for commercial temperature range, without burn-in.
LD80C32 indicates 80C32 in a cerdip package and specified for extended temperature range with burn-in.
87C54/80C54
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
WITH 16 KBYTES USER PROGRAMMABLE EPROM
87CS4/80CS4-3.S MHz to 12 MHz, Vee = SV±20%
87CS4/80CS4-1-3.5 MHz to 16 MHz, Vee = 5V ± 20%
• High Performance CHMOS EPROM
• 6 Interrupt Sources
• Three 16-Bit Timer/Counters
• Programmable Serial Channel with:
• Programmable Clock Out - Framing Error Detection
- Automatic Address Recognition
• Up/Down Timer/Counter
• TTL and CMOS Compatible Logic
• Three Level Program Lock System Levels
• 16K On-Chip EPROM/ROM
• 64K External Program Memory Space
• 256 Bytes of On-Chip Data RAM
• 64K External Data Memory Space
• Improved Quick Pulse Programming™
Algorithm • MCS®-51 Compatible Instruction Set
• Boolean Processor • Power Saving Idle and Power Down
Modes
• 32 Programmable I/O Lines
• ONCETM (On-Circuit Emulation) Mode
• Four-Level Interrupt Priority
MEMORY ORGANIZATION
PROGRAM MEMORY: Up to 16 Kbytes of the program memory can reside in the on-chip EPROM. The device
can also address up to 64K of program memory external to the chip.
DATA MEMORY. This microcontroller has a 256 x 8 on-chip RAM. In addition it can address up to 64 Kbytes of
external data memory.
The Intel 87C54/80C54 is a single-chip control-oriented microcontroller which is fabricated on Intel's reliable
CHMOS III-E technology. Being a member of the MCS-51 family, the 87C54/80C54 uses the same powerful
instruction set, has the same architecture, and is pin for pin compatible with the existing MCS-51 family of
products. The 87C54/80C54 is an enhanced version of the 87C51 180C51 BH. It's added features make it an,
even more powerful microcontroller for applications that require clock output, andup/down counting capabili-
ties such as motor control. It also has a more versatile serial channel that facilitates multi-processor communi-
cations. Throughout this document 8XC54 will refer to both the 87C54 and the 80C54.
November 1990
7-178 Order Number. 270816-002
87C54/80C54
PSEN
TIMING
ALE/PROG
EA/VPP
RST
_ _ _ _ _ .1
PI.O - Pl.7 P3.0- P3.7
270816-1
Figure 1. 8XC54 Block Diagram
7-179
inter 87C54/80C54
PACKAGES Port 0: Port 0 is an 8-bit, open drain, bidirectional I/O
port. As an output port each pin can sink several LS
Part Prefix Package Type TTL inputs. Port 0 pins that have 1 's written to them
8XC54 P 40-Pin Plastic DIP float, and in that state can be used as high-imped-
87C54 0 40-Pin CERDIP ance inputs.
8XC54 N 44-Pin PLCC
Port 0 is also the multiplexed low-order address and
data bus during accesses to external Program and
Data Memory. In this application it uses strong inter-
(T2) PI.0
(T2EX) P1.1
nal pullups when emitting1 's, and can source and
sink several LS TTL inputs.
PO.2 (A02)
Port 0 also receives the code bytes during EPROM
PO.4 (AD4) programming, and outputs the code bytes during
PO.5 (AD5)
program verification. External pullup resistors are re-
PO.6 (AD6)
RESET PO.7 (AD7)
quired during program verification.
(RXO) P3.0 10 J1 Ei./Vpp
(TXD) P3.1 ALE/PROG Port 1: Port 1 is an 8-bit bidirectional I/O port with
internal pullups. The Port 1 output buffers can drive
LS TTL inputs. Port 1 pins that have 1's written to
(TO) P3.4 P2.6 (A14)
them are pulled high by the internal pullups, and in
(n) P3.5 P2.5 (A13)
(Wo) P3.6 P2.4 (AI2)
that state can be used as inputs. As inputs, Port 1
P2.3 (All) pins that are externally being pulled low will source
P2.2 (AI 0) current (IlL, on the data sheet) because of the inter-
XTALI P2.1 (A9) nal pullups.
Vss
270816-2 In addition, Port 1 serves the functions of the follow-
DIP ing special features of the 8XC54:
~ >"C!
"l N C! N
INDEX
~
'"
~ ~ ~ ~
"0
~ ~ ~ '"
~
Port Pin Alternate Function
CORNER
P1.0 T2 (External Count Input to Timer/
PO.4
Counter 2), Clock-Out
PO.S
PO.S P1.1 T2EX (Timer/Counter 2 Capture/
RST PO.7 Reload Trigger and Direction Control)
P3.0 EA/Vpp
NC NC
P3.1 ALE/PROG
Port 1 receives the low-order address bytes during
P3.2 PSEN
P3.3 P2.7
EPROM programming and verifying.
P3.4 P2.6
P3.S P2.5 Port 2: Port 2 is an 8-bit bidirectional I/O port with
internal pull ups. The Port 2 output buffers can drive
"' ~
~
"- ':j
'">'"
~
u
z
~ " "1
~ ~ ~ ~
. LS TTL inputs. Port 2 pins that have 1's written to
~ ~ them are pulled high by the internal pullups, and in
270816-3 that state can be used as inputs. As inputs, Port 2
PLCC pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the inter-
Figure 2. Pin Connections nal pullups.
Port 2 emits the high-order address byte during
PIN DESCRIPTIONS fetches from external Program Memory and during
Vee: Supply voltage. accesses to external Data Memory that use 16-bit
addresses (MOVX @DPTR). In this application it
Vss: Circuit ground. uses strong internal pullups when emitting 1'so Dur-
ing accesses to external Data Memory that use 8-bit
VSS1: Secondary ground (in PLCC only). Provided to addresses (MOVX @Ri), Port 2 emits the contents of
reduce ground bounce and improve power supply the P2 Special Function Register.
by-passing.
NOTE:
This pin is not a substitute for the Vss pin (pin 22).
7,180
inter 87C54/80C54
Some Port 2 pins receive the high-order address bits PSEN: Program Store Enable is the read strobe to
during EPROM programming and program verifica- external Program Memory.
tion.
When the 8XC54 is executing code from external
Port 3:. Port 3 is an 8-bit bidirectional 1/0 port with Program Memory, PSEN is activated twice each
internal pullups. The Port 3 output buffers can drive machine cycle, except. that two PSEN activations
LS TTL inputs. Port 3 pins that have 1's written to are skipped during each access to external Data
them are pulled high by the internal pullups, and in Memory.
that state can be used as inputs. As inputs, Port 3
pins that are externally being pulled low will source EAlVpp: External Access enable. EA must be
current (IlL, on the data sheet) because of the pull- strapped to VSS in order to enable the device to
ups. fetch code from external Program Memory locations
OOOOH to OFFFFH. Note, however, that if any of the
Port 3 also serves the functions of various special Lock bits are programmed, EA will be internally
features of the 8051 Family, as listed below: latched on reset.
EA should be strapped to Vee for internal program
Port Pin Alternate Function
executions.
P3.0 RXD (serial input port)
P3.1 TXD (serial output port) This pin also receives the programming supply volt-
P3.2 INTO (external interrupt 0) age (Vpp) during EPROM programming.
P3.3 INT1 (external interrupt 1)
XTAL1: Input to the inverting oscillator amplifier.
P3.4 TO (Timer 0 external input)
P3.5 T1 (Timer 1 external input) XTAL2: Output from the inverting oscillator amplifier.
P3.6 WR (external data memory write strobe)
P3.7 RD (external data memory read strobe)
OSCILLATOR CHARACTERISTICS
RST: Reset input. A high on this pin for two machine XTAL 1 and XTAL2 are the input and output, respec-
cycles while the oscillator is running resets the de- tively, of a inverting amplifier which can be config-
vice. The port pins will be driven to their reset condi- ured for use as an on-chip oscillator, as shown in
tion when a minimum VIHI voltage is applied whether Figure 3. Either a quartz crystal or ceramic resonator
the oscillator is running or not. An internal pulldown may be used. More detailed information concerning
resistor permits a power-on reset with only a capaci- the use of the on-chip oscillator is available in Appli-
tor connected to Vee. cation Note AP-155, "Oscillators for Microcontrol-
lers."
ALE: Address Latch Enable output pulse for latching
the low byte of the address during accesses to ex-
~
2
ternal memory. This pin (ALE/PROG) is also the
program pulse input during EPROM programming for
o XTAL2
the 87C54. Cl
XTAL 1
In normal operation ALE is emitted at a constant Vss
rate of % the oscillator frequency, and may be used 270816-4
C1.C2 ~ 30pF ±10pFforCrystals
for external timing or clocking purposes. Note, how- ~ 40 pF ± 10 pF for Ceramic Resonators
ever, that one ALE pulse is skipped during each ac-
cess to external Data Memory. Figure 3. Oscillator Connections
If desired, ALE operation can be disabled by setting To drive the device from an external clock source,
bit 0 of SFR location 8EH. With the bit set, ALE is XTAL 1 should be driven, while XTAL2 floats, as
active only during a MOVX instruction. Otherwise, shown in Figure 4. There are no requirements on the
the pin is weakly pulled high. duty cycle of the external clock signal, since the in-
put to the internal clocking circuitry is through a di-
Throughout the remainder of this data sheet, ALE vide-by-two flip-flop, .but minimum and maximum
will refer to the signal coming out of the ALE/PROG high and low times specified on the data sheet must
pin, and the pin will be referred to as the ALE/PROG be observed.
pin.
An external oscillator may encounter as much as a
100 pF load at XTAL1 when it starts up. This is due
to interaction between the amplifier and its feedback
7-181
inter 87C54/80C54
capacitance. Once the external signal meets the VIL With an external interrupt, INTO and INT1 must be
and VIH specifications the capacitance will not ex- enabled and configured as level-sensitive. Holding
ceed 20 pF. the pin low restarts the oscillator but bringing the pin
back high completes the exit. Once the interrupt is
serviced, the next instruction to be executed after
RETI will be the one following the instruction that put
Nlc XTAL 2
the device into Power Down.
EXTERNAL
OSCILLATOR XTAL 1
SIGNAL DESIGN CONSIDERATION
• The window on the 87C54 must be covered by an
270816-5 opaque label. Otherwise, the DC and AC charac-.
teristics may not be met, and the device may
Figure 4. External Clock Drive Configuration functionally be impaired.
• When the idle mode is terminated by a hardware
IDLE MODE reset, the device normally resumes program exe-
cution, from where it left off, up to two machine
The user's software can invoke the Idle Mode. When cycles before the internal reset algorithm takes
the microcontroller is in this mode, power consump- control. On-chip hardware inhibits access to inter-
tion is reduced. The Special Function Registers and nal RAM in this event, but access to the port pins
the onboard RAM retain their values during Idle, but is not inhibited. To eliminate the possibility of an
the processor stops executing instructions. Idle unexpected write when Idle is terminated by re-
Mode will be exited if the chip is reset or if an en- set, the instruction following the one that invokes
abled interrupt occurs. Idle should not be one that writes to a port pin or
to external memory.
POWER DOWN MODE
ONCETM MODE
To save even more power, a Power Down mode can
be invoked by software. In this mode, the oscillator The ONCE ("On-Circuit Emulation") Mode facilitates
is stopped and the instruction that invoked Power testing and debugging of systems using the 8XC54
Down is the last instruction executed. The on-chip without the 8XC54 having to be removed from the
RAM and Special Function Registers retain their val- circuit. .The ONCE Mode is invoked by:
ues until the Power Down mode is terminated.
1) Pull ALE low while the device is in reset and
On the 8XC54 either a hardware reset or an external PSEN is high;
interrupt can cause an !'Ixit from Power Down. Reset 2) Hold ALE low as RST is deactivated.
redefines all the SFRs but does not change the on-
chip RAM. An external interrupt allows both the While the device is in ONCE Mode, the Port 0 pins
SFRs and on-chip RAM to retain their values. go into a float state, and the other port pins and ALE
and PSENare weakly pulled high. The oscillator cir-
To properly terminate Power down the reset or ex- cuit remains active. While the 8XC54 is in this mode,
ternal interrupt should not be executed before Vcc is an emulator or test CPU can be used to drive the
. restored to its normal operating level and must be circuit. Normal operation is restored when a normal
held active long enough for the oscillator to restart reset is applied. .
and stabilize (normally less than 10 ms).
Table 1. Status of the External Pins
, during Idle and Power Down
Program
Mode ALE PSEN PORTO PORT1 PORT2 PORT3
Memory
Idle Internal 1 1 Data Data Data Data
Idle External 1 1 Float Data Address Data
PowerDown Internal 0 0 Data Data Data Data
Power Down External 0 0 Float Data Data Data
NOTE:
For more detailed information on the reduced power modes refer to current Embedded Controller Handbook, and Applica~
tion Note AP-252, "Designing with the 80C51 BH."
7-182
inter 87C54/80C54
ABSOLUTE MAXIMUM RATINGS* NOTICE: This data sheet contains preliminary infor-
mation on new products in production. The specifica-
Ambient Temperature Under Bias .... O°C to + 70°C tions are subject to change without notice.
Storage Temperature .......... - 65°C to + 150°C • WARNING: Stressing the device beyond the "Absolute
Voltage on EAlVpp Pin to Vss ....... OV to + 13.0V Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
Voltage on Any Other Pin to Vss .. - 0.5V to + 6.5V "Operating Conditions" is not recommended and ex-
IOL Per 1/0 Pin ........................... 15 mA tended exposure beyond the "Operating Conditions"
may affect device reliability.
Power Dissipation .......................... 1.5W
(based on PACKAGE heat transfer limitations, not
device power consumption)
Operating Conditions:
= O°C to + 70°C; Vee =
TA (under bias) 5V ± 20%; Vss = OV
D.C. CHARACTERISTICS: (Under Operating Conditions)
Typ
Symbol Parameter Min Max Unit Test Conditions
(Note 4)
VIL Input Low Voltage -0.5 0.2Vee- 0.1 V
VIL1 Input Low Voltage EA 0 0.2Vee- 0.3 V
VIH Input High Voltage 0. 2Vee+ 0.9 Vee+ 0.5 V
(Except XTAL 1, RST)
VIH1 Input High Voltage (XTAL 1, RST) 0.7 Vee Vee+ 0.5 V
VOL Output Low Voltage (Note 5) 0.3 V IOL = 100 /LA (Note 1)
(Ports 1, 2, and 3)
0.45 V IOL = 1.6 mA (Note 1)
1.0 V IOL = 3.5 mA (Note 1)
VOL1 Output Low Voltage (Note 5) 0.3 V IOL = 200 /LA (Note 1)
(Port 0, ALE, PSEN)
0.45 V IOL = 3.2 mA (Note 1)
1.0 V IOL = 7.0 mA (Note 1)
VOH Output High Voltage Vee- 0.3 V IOH = -10 /LA
(Ports 1, 2, and 3, ALE, PSEN)
Vee- 0.7 V IOH = -30/LA
Vec- 1.5 V IOH = -60/LA
VOH1 Output High Voltage Vee- 0.3 V IOH = -200/LA
(Port 0 in External Bus Mode)
Vee- 0.7 V IOH = -3.2 mA
Vee- 1.5 V loti = -7.0 mA
IlL Logical 0 Input Current -50 /LA VIN = 0.45V
(Ports 1, 2, and 3)
III Input leakage Current (Port 0) ±10 /LA 0.45 < VIN < Vee
ITL Logical 1 to 0 Transition Current -650 /LA VIN = 2V
(Ports 1, 2, and 3)
RRST RST Pulidown Resistor 40 225 K!l
CIO Pin Capacitance 10 pF @1 MHz, 25°C
Icc Power Supply Current: (Note 3)
Running at 12 MHz (Figure 5) 20 40 mA
Idle Mode at 12 MHz (Figure 5) 5 10 mA
Power Down Mode 15 100 /LA
7-183
87C54/80C54
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above O.4V to be superimposed on the VOLS of
ALE and Ports 1. 2 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when
these pins change from 1 to O. In applications where capacitive loading exceeds 100 pF. the noise pulses on these signals
may exceed o.av. It may be desirable to qualify ALE or other signals with a Schmitt. Triggers. or CMOS-level input logic.
2. Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the 0.9 Vcc specification when the
address lines are stabilizing. .
3. See Figures 6-9 for test conditions. Minimum Vcc for Power Down is 2V.
4. Typicals are based on limited number of samples and are not guaranteed. The values listed are at room temperature and
5V.
5. Under steady state (non-transient) conditions. IOL must be externally limited as follows:
Maximum IOL per port pin: 10mA
Maximum IOL per B-bit port-
Port 0: 26 mA
Ports 1. 2 and 3: 15 mA
Maximum total IOL for all output pins> 71 mA'
If IOL exceeds the test condition. VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
60mA
SOmA
-(Om"
MAX. ~
~
RST
30mA _.- aXe54
20mA
A/ TYPICAL ________
XTAL2
XTALl
lOrnA /"
V
/' --=:::::: r--
A~
IDLE
----":~.
IDLE
-
TYPICAL
All other pins disconnected
vss
270816-7
OmA
Ot.lHz "MHz 8t.1Hz 12MHz 16Jr,1Hz TCLCH ~ TCHCL ~ 5 ns
270816-6
ICC Max al other frequencies is given by: Figure 6. Icc Test Condition, Active Mode
Active Mode
Icc Max ~ (Osc Freq x 3) + 4
Idle Mode
Icc Max· ~ (Osc Freq x 0.5) + 4
Where Osc Freq is in MHz. Icc is in rnA.
Figure 5. Icc vs Frequency
8XC54
270816-9
270816-8
All other pins disconnected
All other pins disconnected
TCLCH ~ TCHCL ~ 5 ns
Figure 8. Icc Test Condition, Power Down Mode
. Figure 7. Icc Test Condition Idle Mode Vcc = 2.0V to 6.0V
270816-10
Figure 9. Clock Signal Waveform for Icc Tests in Active and Idle Modes. TCLCH = TCHCL = 5 ns
7-184
87C54/80C54
EXPLANATION OF THE AC SYMBOLS L: Logic level LOW, or ALE
P:PSEN
Each timing symbol has 5 characters. The first char- Q: Output Data
acter is always a 'T' (stands for time). The other R: RD signal
characters, depending on their positions, stand for T: Time
the name of a signal or the logical status of that V: Valid
signal. The following is a list of all the characters and W: WR signal
what they stand for. X: No longer a valid logic level
Z: Float
A: Address
C: Clock For example,
D: Input Data
H: Logic level HIGH TAVLL = Time from Address Valid to ALE Low
I: Instruction (program memory contents) TLLPL = Time from ALE Low to PSEN Low
A.C. CHARACTERISTICS (Under Operating Conditions.) Load Capacitance for Port 0, ALE/PROG
and PSEN = 100 pF, Load Capacitance for All Other Outputs = 80 pF)
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
12 MHz Oscillator Variable Oscillator
Symbol Parameter Units
Min Max Min Max
1/TCLCL Oscillator Frequency 3.5 16 MHz
TLHLL ALE Pulse Width . 127 2TCLCL-40 ns
TAVLL Address Valid to ALE Low 43 TCLCL-40 ns
TLLAX Address Hold After ALE Low 53 TCLCL-30 ns
TLLlV ALE Low to Valid Instruction In 234 4TCLCL-100 ns
TLLPL ALE Low to PSEN Low 53 TCLCL-30 ns
TPLPH PSEN Pulse Width 205 3TCLCL-45 ns
TPLIV PSEN Low to Valid Instruction In 145 3TCLCL-105 ns
TPXIX Input Instruction Hold After PSEN 0 0 ns
TPXIZ Input Instruction Float After PSEN 59 TCLCL-25 ns
TAVIV Address to Valid Instruction In 312 5TCLCL-105 ns
TPLAZ PSEN Low to Address Float 10 10 ns
TRLRH RD Pulse Width 400 6TCLCL-100 ns
TWLWH WR Pulse Width 400 6TCLCL-100 ns
TRLDV RD Low to Valid Data In 252 5TCLCL-165 ns
TRHDX Data Hold After RD 0 0 ns
TRHDZ Data Float After RD 107 2TCLCL-60 ns
TLLDV ALE Low to Valid Data In 517 8TCLCL-150 ns
TAVDV Address to Valid Data In 585 9TCLCL-165 ns
TLLWL ALE Low to RD or WR Low 200 300 3TCLCL-50 3TCLCL+50 ns
TAVWL Address Valid to WR Low 203 4TCLCL-130 ns
TQVWX Data Valid before WR 33 TCLCL-50 ns
TWHQX Data Hold after WR 33 TCLCL-50 ns
TQVWH Data Valid to WR High 433 7TCLCL-150 ns
TRLAZ RD Low to Address Float 0 0 ns
TWHLH RD or WR High to ALE High 43 123 TCLCL-40 TCLCL+40 ns
7-185
87C54/80C54
EXTERNAL PROGRAM MEMORY READ CYCLE
ALE _ _. I
TPXIZ
PORT 0
--- AO-A7
PORT2 ______-J~________~____________~,~______A_8_-_A_l_5_______
270816-11
EXTERNAL DATA MEMORY READ CYCLE
ALE
PSEN
I-----TLLDV 'I
-----O-f---- TRLRH - - - - + I
PORTO INSTR. IN
PORT2 P2.0-P2.7 OR A8-A15 FROM DPH A8-A 15 FROM PCH
270816-12
EXTERNAL DATA MEMORY WRITE CYCLE
ALE
-TLHLL-
" I
~TWHLH
~
.~
f.o---- TLLWL
,
TWLWH
..... I-
TAVLL
I - TLLAX __ IIQVWX,
TQVWH
...I --TWHQX
PORTO
:::::r rRott~i S~ DPL
TAVWL
DATA OUT XAO-A7 FROM PCL INSTR. IN
PORT2 ::::) P2.0-P2.7 OR A8-A15 FRPM DPH A8-Al 5 FROM PCH
270816-13
7-186
inter 87C54/80C54
SERIAL PORT TIMING - SHIFT REGISTER MODE
Test Conditions: T A = O'C to + 70'C; Vee = 5V ± 20%; Vss = OV; Load Capacitance = 80 pF
12 MHz Oscillator Variable O.scillator
Symbol Parameter Units
Min Max Min Max
TXLXL Serial Port Clock Cycle Time 1 12TCLCL /-ts
TOVXH Output Data Setup to Clock 700 1OTCLCL - 133 ns
Rising Edge
TXHOX Output Data Hold after 50 2TCLCL-117 ns
Clock Rising Edge
TXHDX Input Data Hold After Clock 0 0 ns
Rising Edge
TXHDV Clock Rising Edge to Input 700 1OTCLCL - 133 ns
Data Valid
SHIFT REGISTER MODE TIMING WAVEFORMS
INSTRUCTION I 0 2 3 4 5 6 7 8
ALE
CLOCK
OUTPUT DATA X 3
X 4
X 5 X 6
X 7
7
t t
WRITE TO SBUf SET TI
INPUT DATA
t I
CLEAR RI SET RI
270816-14
EXTERNAL CLOCK DRIVE
Symbol Parameter Min Max Units
1/TCLCL Oscillator Frequency
8XC54 3.5 12
MHz
8XC54-1 3.5 16
TCHCX High Time 20 ns
TCLCX Low Time 20 ns
TCLCH Rise Time 20 ns
TCHCL Fall Time 20 ns
EXTERNAL CLOCK DRIVE WAVEFORM
270816-15
7-187
inter 87C54/80C54
A.C. TESTING INPUT
Input, Output Waveforms Float Waveforms
VCC- 0•5 -y- 0.2 VCC+ 0.9 V- VLOAD
TIMING REFERENCE
~_0_.2_V.;..CC;;..-_0_.t_ _ _ _~
POINTS
D.45 V
270816-16
For timing purposes a port pin is no longer floating when a
AC Inputs during testing are driven at Vee ··0.5V·for a Logic "1" 100 mV change from load voltage occurs, and begins to float
and 0.45V for a Logic "0". Timing measurements are made at VIH when a 100 mV change from the loaded VOHIVOL level occurs.
min for a Logic "1" and VrL max for a Logic "0",
IOLIlOH ~ ± 20 mAo
Table 2. EPROM Programming Modes
ALE! EAt
Mode RST PSEN P2.6 P2.7 P3.3 P3.6 P3.7 .
PROG Vpp
Program Code Data H L L..f" 12.75V L H H H H
Verify Code Data H L H H L L L H H
Program Encryption H L L..f" 12.75V L H H L H
Array Address 0-3FH
Program Lock Bit 1 H L L..f" 12.75V H H H H H
Bits
Bit2 H L L..f" 12.75V H H H L L
Bit 3 H L L..f" 12.75V H L H H L
Read Signature Byte H L H H L L L L L
DEFINITION OF TERMS PROGRAMMING THE EPROM
ADDRESS LINES: P1.0-P1.7, P2.0-P2.5 respec- . The part must be running with a 4 MHz to 6 MHz
tively for AO-A13. oscillator. The address of an EPROM location to be
programmed is applied to address lines while the
DATA LINES: PO.0-PO.7 for 00-07. code byte to be programmed in that location is ap-
plied to data lines. Control and program signals must
CONTROL SIGNALS: RST, PSEN, P2.6, P2.7, P3.3, be held at the levels indicated in Table 2. Normally
P3.6, .P3.7 EAlVpp is held at logic high until just before ALEI
PROG is to be pulsed. The EAlVpp is raised to Vpp,
PROGRAM SIGNALS: ALE!PROG, EAlVpp ALE/PROG is pulsed low and then EAlVpp is re-
turned to a high (also refer to timing diagrams).
NOTE:
Exceeding the Vpp maximum for any amount of
time could damage the device permanently. The
Vpp source must be well regulated and free of
glitches.
7-188
87C54/80C54
+5V
Vee 40
87e54
EA/Vpp 31
PROGRAM
}
AlE/PROG 30 SIGNALS
_ 29
PSEN
28
P2.7
27
18 P2.6
XTAl2 17
P3.7 CONTROL SIGNALS'
16
P3.6
19 13
XTAll P3.3
20 RST
VSS
- 270816-18
'See Table 2 for proper input on these pins
Figure 10. Programming the EPROM
PROGRAMMING ALGORITHM PROGRAM VERIFY
Refer to Table 2 and Figures 10 and 11 for address, Program verify may be done after each byte that is
data, and control signals set up. To program the programmed, or after a block of bytes that is pro-
87C54 the following sequence must be exercised. grammed. In either case a complete verify of the
1. Input the valid address on the address lines. entire array that has been programmed will ensure a
reliable programming of the 87C54.
2. Input the appropriate data byte on the data
lines. The lock bits cannot be directly verified. Verification
3. Activate the correct combination of control sig- of the lock bits is done by observing that their fea-
nals. tures are enabled. Refer to the EPROM Program
4. Raise EAlVpp from Vee to 12.75V ±O.25V. Lock section in this data sheet.
5. Pulse ALE/PROG 5 times for the EPROM ar-
ray, and 25 times for the encryption table and
the lock bits.
Repeat 1 through 5 changing the address and data
for the entire array or until the end of the object file is
reached.
ADDRESS
X~_ _ _X 14 BITS
DATA
X _______________X
~
B BITS
CONTROL
SIGNALS X _______________X
~
7 BITS
12.75V
EA/Vpp
AlE/PROG
5V..J
TGlGH
TGHGl
--/1-- '-
270816-19
5 Pulses
Figure 11. Programming Signal's Waveforms
7-189
inter 87C54/80C54
ROM and EPROM Lock System Erasing the EPROM also erases the encryption ar-
ray and the program lock bits, returning the part to
The 87C54 and the 80C54 program lock systems, full functionality.
when programmed, protect the on board program
against software piracy.
Reading the Signature Bytes
The 80C54 has a one-level program lock system
and a 64-byte encryption table. See line 2 of Table The 87C54/80C54 each has 3 signature bytes in lo-
3. If program protection is desired, the user submits cations 30H, 31 H, and 60H: To read these bytes fol-
the encryption table with their code, and both the low the procedure for EPROM verify, but activate
lock-bit and encryption array are programmed by the the control lines provided in Table 2 for Read Signa-
factory. The encryption array is not available without ture Byte.
the lock bit. For the lock bit to be programmed, the
Content
user must Submit an encryption table. Location
87C54 80C54
The 87C54 has a 3-level program lock system and a
64-byte encryption array. Since this is an EPROM 30H 89H 89H
device, all locations are user programmable. See 31H 58H 58H
Table 3. 60H 54H 54H/14H
Encryption Array Erasure Characteristics
Within the EPROM array are 64 bytes of Encryption (Windowed Packages Only)
Array that are initially unprogrammed (all 1's). Every Erasure of the EPROM begins to occur when the
time that a byte is addressed during a verify, 6 ad- chip is exposed to light with wavelength shorter than
dress lines are used to select a byte of the Encryp- approximately 4;000 Angstroms. Since sunlight and
tion Array. This byte is then exclusive-NOR'ed fluorescent lighting have wavelengths in this range,
(XNOR) with the code byte, creating an Encryption exposure to these light sources over an extended
Verify byte. The algorithm, with the array in the un- time (about 1 week in sunlight, or 3 years in room-
programmed state (all 1's), will return the code in it's level fluorescent, lighting) could cause inadvertent
original, unmodified form. For programming the En- erasure. If an application subjects the device to this
cryption Array, refer to Table 2 (Programming the type of exposure, it is suggested that an opaque la-
EPROM). bel be placed over the window.
The recommended erasure procedure is exposure
Program Lock Bits to ultraviolet light (at 2537 Angstroms) to an integrat-
ed dose of at least 15 W-secl cm 2; Exposing the
The 87C54 has 3 programmable lock bits that when
EPROM to an ultraviolet lamp of 12,000 ""W/cm 2
programmed according to Table 3 will provide differ-
rating for 30 minutes, aLa distance of about 1 inch,
ent levels of protection for the on-chip code and
should be sufficient'
data.
Erasure leaves all the EPROM Cells in a 1's state.
Table 3 Program Lock Bits and the Features
Program Lock Bits
Protection Type
LB1 LB2 LB3
1 U U U No Program Lock features enabled. (Code verify will still be encrypted by the
Encryption Array if programmed.)
2 P U U MOVC instructions executed from external program memory are disabled
from fetching code bytes from internal memory, EA is sampled and latched on
Reset, and further programming of the EPROM is disabled.
3 P P U Same as 2, also verify is disabled.
4 P P P Same as 3, also external execution is disabled.
Any other combination of the lock bits is not defined.
7-190
87C54/80C54
EPROM 'PROGRAMMING AND VERIFICATION' CHARACTERISTICS
(TA = 21°C to 27"C; Vee = 5V ±20%; Vss = OV)
Symbol Parameter Min Max Units
Vpp Programming Supply Voltage 12.5 13.0 V
Ipp Programming Supply Current 75 mA
1/TCLCL Oscillator Frequency 4 6 MHz
TAVGL Address Setup to PROG Low 48TCLCL
TGHAX Address Hold after PROG 48TCLCL
TDVGL Data Setup to PROG Low 48TCLCL
TGHDX Data Hold after PROG 48TCLCL
TEHSH (Enable) High to Vpp 48TCLCL
TSHGL Vpp Setup to PROG Low 10 fLs
TGHSL Vpp Hold after PROG 10 fLs
TGLGH PROGWidth 90 110 fLs
TAVOV Address to Data Valid 48TCLCL
TELOV ENABLE Low to Data Valid 48TCLCL
TEHOZ Data Float after ENABLE 0 48TCLCL
TGHGL PROG High to PROG Low 10 fLs
EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
PROGRAMMING VERIFICATION
AO-A15---------1::==~AD~D~RE~S~S~~====}_----------1:==~AD~D~RE~S~S==:>---------
-TAVQV
DO-D7---------1~==~~~:~::~------------_1~DA~TA~OU~T~~----------
TDVGL TGHDX
TGHAX
ALE/PROG -----------"'\.I
TSHGL~
TGLGH
EA/Vpp Vce A Vpp
-"';';;---~--""~ITEHSH TEHQZ
CONTROL _ _--._ .
SIGNALS
(ENABLE) ---"""
270816-20
7-191
inter 87C54/80C54
DATA SHEET REVISION SUMMARY
The following differences exist between this data
sheet and the previous version (270816-001):
1. Changed data sheet status from "Advanced" to
"Preliminary" .
2. Added "Four-Level Interrupt Priority" feature bul-
let.
3. Revised RST pin description.
4. Changed Figure 3 to read "= 40 pF ± 10 pF for
Ceramic Resonators".
5. Added VIL 1 specification to D.C. Characteristics
table.
6. Changed test conditions under III from OV to
0.45V for VIN minimum.
7. Revised Absolute Maximum Ratings warning and
data sheet status notice.
8. Reworded D.C. Characteristics Note 1.
9. Changed 1/TCLCL Minimum specification from
0.5 MHz to 3.5 MHz.
10. Deleted -2 reference in "External Clock Drive"
table.
11. Revised "ROM and EPROM Lock System" sec-
tion.
7-192
87C54/80C54
EXPRESS
87C54/80C54-3.5 MHz to 12 MHz, Vee = 5V ±20%
87C54-1/80C54-1-3.5 MHz to 16 MHz, Vee = 5V ± 20%
• Extended Temperature Range • Burn-In
The Intel EXPRESS system offers enhancements to the operational specifications of the MCS®-51 family of
microcontrollers. These EXPRESS products are designed to meet the needs of those applications whose
operating requirements exceed commercial standards.
The EXPRESS program includes the commercial standard temperature range with burn-in and an extended
temperature range with or without burn-in.
With the commercial standard temperature range, operational characteristics are guaranteed over the temper-
ature range of O'C to 70'C. With the extended temperature range option, operational characteristics are
guaranteed over the range of - 40'C to + 85'C.
The optional burn-in is dynamic for a minimum time of 168 hours at 125'C with Vee = 6.9V ±0.25V, following
guidelines in MIL-STD-883, Method 1015.
Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part number. The
prefixes are listed in Table 1.
For the extended temperature range option, this data sheet specifies the parameters which deviate from their
commercial temperature range limits. The commercial temperature range data sheets are applicable for all
parameters not listed here. This data sheet is valid in conjunction with the commercial 87C54/80C54 data
sheet, 270816-002.
October 1990
7-193 Order Number: 270901-001
inter 87C54/80C54 EXPRESS
Electrical Deviations from Commercial Specifications for Extended Temperature
Range
O.C. and A.C. parameters not included here are the same as in the commercial temperature range data
sheets.
D.C. CHARACTERISTICS TA = -40°C to +85°C; VCC = 5V ±20%; Vss = OV
Limits Test
Symbol Parameter Unit
Min Max Conditions
ITl Logical 1 to 0 Transition Current .-750 fl-A VIN = 2V
(Ports 1, 2 and 3)
Table 1. Prefix Identification
Prefix Package Type Temperature Range Burn-In
P Plastic Commercial No
0' Cerdip Commercial No
N PLCC Commercial No
TP Plastic Extended No
TO' Cerdip Extended No
TN PLCC Extended No
LP Plastic Extended Yes
LO* Cerdip Extended Yes
LN PLCC Extended Yes
'Avallable for 87C54 only.
NOTE:
• Commercial temperature range is O'C to 70'C. Extended temperature range is -40'C to + 85'C.
• Burn-in is dynamic for a minimum time of 168 hours at 125'C, Vee = 6.9V ±0.25V, following guidelines in Mll-STD-883
Method 1015 (Test Condition D).
Examples:
P80C54 indicates 80C54 in a plastic package and specified for commercial temperature range, without burn-in.
L080C54 indicates 80C54 in a cerdip package and specified for extended temperature range with burn-in.
DATA SHEET REVISION SUMMARY
This is Rev. 1 of the 80C54/87C54 Express data sheet.
7-194
87C58/80C58
CHMOS SINGLE-CHIP 8~BIT MICROCONTROLLER
WITH 32K BYTES USER PROGRAMMABLE EPROM
87CS8/80CS8-3.S MHz to 12 MHz, Vee = SV ± 20%
87CS8/80CS8-1-3.S MHz to 16 MHz, Vee = SV ± 20%
• Three
High Performance CHMOS EPROM
• 6Four
Interrupt Sources
• Programmable
16-Bit Timer/Counters
• Programmable
Level Interrupt Priority Structure
• Up/Down Timer/Counter
Clock Out
• - Framing ErrorSerial Channel with:
Detection
• Three Level Program Lock System - Automatic Address Recognition
•• 32K On-Chip EPROM/ROM • TTL and CMOS Compatible Logic
Levels
• 2S6 Bytes of On-Chip Data RAM
• 64K External Program Memory Space
• Algorithm
Improved Quick Pulse Programming™
• 64K External Data Memory Space
• Boolean Processor • MCS®-S1 Compatible Instruction Set
• 32 Programmable I/O Lines • Power
Modes
Saving Idle and Power Down
• ONCETM (On-Circuit Emulation) Mode
MEMORY ORGANIZATION
PROGRAM MEMORY: Up to 32K bytes of the program memory can reside in the on-chip EPROM. The device
can also address up to 64K of program memory external to the chip.
DATA MEMORY: This microcontrolier has a 256 x 8 on-chip RAM. In addition it can address up to 64K bytes of
external data memory.
The Intel 87C58/80C58 is a single-chip control-oriented microcontrolier which is fabricated on Intel's reliable
CHMOS III-E technology. Being a member of the MCS-51 family, the 87C58/80C58 uses the same powerful
instruction set, has the same architecture, and is pin-for-pin compatible with the existing MCS-51 family of
products. The 87C58/80C5B is an enhanced version of the B7C51/80C51 BH. It's added features make it an
even more powerful microcontrolier for applications that require clock output,and upl down counting capabili-
ties such as motor control. It also has a more versatile serial channel that facilitates multi-processor communi-
cations. Throughout this document BXC5B will refer to both the B7C5B and the 80C58.
October 1990
7-195 Order Number: 270900-001
infef 87C58/80C58
P2.0 - P2.7
v~
,.- -------,
Vss
E
PSEN
ALE/fSIlOll
TIMING '"~~----~--~~---------LJ---~~--~L-----~ ~
AND
rAjVPP
CONTROL Bl\r-------;;;;:-------------r-r---------r,-------,...,-----.,I ~
RST
'"
PLO - Pl.7 P3.0-P3.7
270900-1
Figure 1. 8XC58 Block Diagram
7-196
inter 87C58/80C58
(T2) P1.0 Vce
(T2EX) P1.l PO.O (ADO)
P1.2 PO.l (AD1)
P1.3 PO.2 (AD2)
P1.4 PO.3 (AD3)
P1.S PO.4 (AD4)
P1.6 PO.S (ADS)
P1.7 PO.6 (AD6)
RESET PO.7 (AD7)
(RXD) P3.0 fA/vpp
(TXD) P3.l ALE/PROG
(INTO) P3.2 PSEN
(iNTl) P3.3 P2.7 (A1S)
(TO) P3.4 P2.6 (AU)
(Tl) P3.S P2.S (A13)
(iYR) P3.6 P2.4 (A12)
(iffi) P3.7 P2.3 (All)
XTAL2 P2.2 (Al0)
XTALl P2.l (A9)
Vss P2.0 (AS)
270900-2
DIP
INDEX
CORNER
": "1 "! q v; q
0: 0: 0: 0: 0: >on ><.J 0.. ci ci '"
<.J
ci .. .. .
N
P1.5 PO.4
P1.6 PO.5
P1.7 PO.6
RST PO.7
P3.0 fA/vpp
NC NC
P3.l ALE/PROG
P3.2 PSEN
P3.3 P2.7
P3.4 P2.6
P3.S P2.5
.'" .....
,..; ,..;
N (fl u
.. . .. .'" ....
0
-' -' (fl z N N N N N
;:! ;:!
x x
>
N
270900-3
PLCC
Figure 2. Pin Connections
PACKAGES PIN DESCRIPTIONS
Part Prefix Package Type Vee: Supply voltage.
8XC58 P 40-Pin Plastic DIP
87C58 D 40-Pin CERDIP Vss: Circuit ground.
8XC58 N 44-Pin PLCC
VSS1: Secondary ground (in PLCC only). Provided to
reduce ground bounce and improve power supply
by-passing.
NOTE:
This pin is not a substitute for the Vss pin (pin 22).
7-197
inter 87C58/80C58
Port 0: Port 0 is an 8-bit, open drain, bidirectional I/O Some Port 2 pins receive the high-order address bits
port. As an output port each pin can sink several LS during EPROM programming and program verifica-
TTL inputs. Port 0 pins that have 1's written to them tion.
float, and in that state can be used as high-imped-
ance inputs. Port 3: Port 3 is an 8-bit bidirectional I/O port with
internal pullups. The Port 3 output buffers can drive
Port 0 is also the multiplexed low-order address and LS TTL inputs. Port 3 pins that have 1's written to
data bus during accesses to external Program and them are pulled high by the internal pullups, and in
Data Memory. In this application it uses strong inter- that state can be used as inputs. As inputs, Port 3
nal pullups when emitting 1's, and can source and pins that are externally being' pulled low will source
sink several LS TTL inputs. current (IlL, on the data sheet) because of the pull-
ups.
Port 0 also receives the code bytes during EPROM
programming, and outputs the code bytes during Port 3 also serves the functions of various special
program verification. External pullup resistors are re- features of the 8051 Family, as listed below:
quired during program verification.
Port Pin Alternate Function
Port 1: Port 1 is an 8-bit bidirectional I/O port with
internal pullups. The Port 1 output buffers can drive P3.0 RXD (serial input port)
LS TTL inputs. Port 1 pins that have 1's written to P3.1 TXD (serial output port)
them are pulled high by the internal pull ups, and in P3.2 INTO (external interrupt 0)
that state can be used as inputs. As inputs, Port 1 P3.3 INT1 (external interrupt 1)
pins that are externally being pulled low will source P3.4 TO (Timer 0 external input)
current (IlL, on the data sheet) because of the inter-
P3.5 T1 (Timer 1 external input)
nal pullups.
P3.6 WR (external data memory write strobe)
In addition, Port 1 serves the functions of the follow- P3.7 RD (external data memory read strobe)
ing special features of the 8XC58:
RST: Reset input. A high on this pin for two .machine
Port Pin Alternate Function cycles while the oscillator is running resets the de-
vice. The port pins will be driven to their reset condi-
P1.0 T2 (External Count Input to Timer/ tion when a minimum VIH1 voltage is applied wheth-
Counter 2), Clock-Out er the oscillator is running or not. An internal pull-
P1.1 T2EX (Timer/Counter 2 Capture/ down resistor permits a power-on reset with only a
Reload Trigger and Direction Control) capacitor connected to Vee.
ALE: Address Latch Enable output pulse for latching
Port 1 receives the low-order address bytes during the low byte of the address during accesses to ex-
EPROM programming and verifying. ternal memory. This pin (ALE/PROG) is also the
program pulse input during EPROM programming for
Port 2: Port 2 is an 8-bit bidirectional I/O port with the 87C58.
internal pull ups. The Port 2 output buffers can drive
LS TTL inputs. Port 2 pins that have 1's written to In normal operation ALE is emitted at a constant
them are pulled high by the internal pullups, and in rate of Ys the oscillator frequency, and may be used
that state can be used as inputs. As inputs, Port 2 for external timing or clocking purposes. Note, how-
. pins that are externally being pulled low will source ever, that one ALE pulse is skipped during each ac-
current (IlL, on the data sheet) because of the inter- cess to external Data Memory.
nal pullups.
If desired, ALE operation can be disabled by setting
Port 2 emits the high-order address byte during bit 0 of SFR location 8EH. With the bit set, ALE is
fetches from external Program Memory and during active only during a MOVX instruction. Otherwise,
accesses to external Data Memory that use 16-bit the pin is weakly pulled high.
addresses (MOVX @DPTR). In this application it
uses strong internal pullups when emitting 1'so Dur- Throughout the remainder of this data sheet, ALE
ing accesses to external Data Memory that use 8-bit will refer to the signal coming out of the ALE/PROG
addresses (MOVX @Ri), Port 2 emits the contents of . pin, and the pin will be referred to as the ALE/PROG
the P2 Special Function Register. pin.
PSEN: Program Store Enable is the read strobe to
external Program Memory.
7-198
inter 87C58/80C58
When the 8XC58 is executing code from external An external oscillator may encounter as much as a·
Program Memory, PSEN is activated twice each 100 pF load at XTAL 1 when it starts up. This is due
machine cycle, except that two PSEN activations to interaction between the amplifier and its feedback
are skipped during each access to external Data capacitance. Once the external signal meets the VIL
Memory. and VIH specifications the capacitance will not ex-
ceed 20 pF.
EAIVpp: External Access enable. EA must be
strapped to VSS in order to enable the device to
fetch code from external Program Memory locations
OOOOH to OFFFFH. Note, however, that if any of the N/C XTAL2
Lock bits are programmed, EA will be internally
latched on reset.
EXTERNAL
OSCILLATOR XTAL 1
EA should be strapped to Vee for internal program SIGNAL
executions.
This pin also receives the programming supply volt-
age (Vpp) during EPROM programming. 270900-5
XTAL 1: Input to the inverting oscillator amplifier. Figure 4. External Clock Drive Configuration
XTAL2: Output from the inverting oscillator amplifier.
IDLE MODE
OSCILLATOR CHARACTERISTICS The user's software can invoke the Idle Mode. When
the microcontroller is in this mode, power consump-
XTAL 1 and XTAL2 are the input and output, respec- tion is reduced. The Special Function Registers and
tively, of a inverting amplifier which can be config- the onboard RAM retain their values during Idle, but
ured for use as an on-chip oscillator, as shown in the processor stops executing instructions. Idle
Figure 3. Either a quartz crystal or ceramic resonator Mode will be exited if the chip is reset or if an en-
may be used. More detailed information concerning· abled interrupt occurs.
the use of the on-chip oscillator is available in Appli-
cation Note AP-155, "Oscillators for Microcontrol-
lers." POWER DOWN MODE
To save even more power, a Power Down mode can
C2 be invoked by software. In this mode, the oscillator
t-----p---t XTAL2 is stopped and the instruction that invoked Power
Down is the last instruction executed. The on-chip
o RAM and Special Function Registers retain their val-
ues until the Power Down mode is terminated.
t-----...-.--I XTAL 1
On the 8XC58 either a hardware reset or an external
t - - - - - - - - 1 vss interrupt can cause an exit from Power Down. Reset
redefines all the SFRs but does not change the on-
270900-4 chip RAM. An external interrupt allows both the
Cl, C2 = 30 pF ± 10 pF for Crystals SFRs and on-chip RAM to retain their values.
= 40 pF ± 10 pF for Ceramic Resonators
Figure 3. Oscillator Connections To properly terminate Power down the reset or ex-
ternal interrupt should not be executed before Vee is
To drive the device from an external clock source, restored to its normal operating level and must be
XTAL 1 should be driven, while XTAL2 floats, as held active long enough for the oscillator to restart
shown in Figure 4. There are no requirements on the and stabilize (normally less than 10 ms).
duty cycle of the external clock signal, since the in-
put to the internal clocking circuitry is through a di-
vide-by-two flip-flop, but minimum and maximum
high and low times specified on the data sheet must
be observed.
7-199
inter 87C58/80C58
With an external interrupt, INTO and INT1 must be Idle should not be one that writes to a port pin or
enabled and configured as level-sensitive. Holding to external memory.
the pin low restarts the oscillator but bringing the pin
back high completes the exit. Once the interrupt is
serviced, the next instruction to be executed after ONCETM MODE
RETI will be the one following the instruction that put
the device into Power Down. The ONCE ("On-Circuit Emulation") Mode facilitates
testing and debugging of systems using the 8XC58
without the 8XC58 having to be removed from the
DESIGN CONSIDERATION circuit. The ONCE Mode is invoked by:
1) Pull ALE low while the device is in reset and
• The window on the 87C58 must be covered by an PSEN is high;
opaque label. Otherwise, the DC and AC charac-
teristics may not be met, and the device may 2) Hold ALE low as RST is deactivated.
functionally be impaired.
While the device is in ONCE Mode, the Port 0 pins
• When the idle mode is terminated by a hardware go into a float state, and the other port pins and ALE
reset, the device normally resumes program exe- and PSEN are weakly pulled high. The oscillator cir-
cution, from where it left off, up to two machine cuit remains active. While the 8XC58 is in this mode,
cycles before the internal reset algorithm takes an emulator or test CPU can be used to drive. the
control. On-chip hardware inhibits access to inter- circuit. Normal operation is restored when a normal
nal RAM in this event, but access to the port pins reset is applied.
is not inhibited. To eliminate the possibility of an
unexpected write when Idle is terminated by re-
set, the instruction following the one that invokes
Table 1. Status of the External Pins during Idle and Power Down
Program
Mode ALE PSEN PORTO PORT1 PORT2 PORT3
Memory
Idle Internal 1 1 Data Data Data Data
Idle External 1 1 Float Data Address Data
Power Down Internal 0 0 Data Data Data Data
Power Down External 0 0 Float Data Data Data
NOTE:
For more detailed information on the reduced power modes refer to current Embedded Controller Handbook, and Applica-
tion Note AP-252, "Designing with the 80C51 BH."
7-200
87C58/80C58
ABSOLUTE MAXIMUM RATINGS* NOTICE: This data sheet contains information on
products in the sampling and initial production phases
Ambient Temperature Under Bias .... O·C to + 70·C of development. The specifications are subject to
Storage Temperature .......... -65·C to + 150·C change without notice.
Voltage on EAlVpp Pin to Vss ....... OV to + 13.0V • WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
Voltage on Any Other Pin to Vss .. - 0.5V to + 6.5V These are stress ratings only. Operation beyond the
IOL Per 1/0 Pin ........................... 15 mA "Operating Conditions" is not recommended and ex-
tended exposure beyond the "Operating Conditions"
Power Dissipation .......................... 1.5W
may affect device reliability.
(based on PACKAGE heat transfer limitations, not
device power consumption)
ADVANCED INFORMATION-CONTACT INTEL FOR DESIGN-IN INFORMATION
Operating Conditions: TA (Under Bias) = O·C to +70·C; Vee = 5V ±20%; Vss = OV
D.C. CHARACTERISTICS: (Under Operating Conditions)
Typ
Symbol Parameter Min Max Unit Test Conditions
(Note 4)
VIL Input Low Voltage -0.5 0. 2Vee- 0.1 V
VIL1 Input Low Voltage EA 0 0.2Vee- 0.3 V
VIH Input High Voltage 0.2 Vee+0.9 Vee+ 0.5 V
(Except XT AL1, RST)
VIH1 Input High Voltage (XTAL 1, RST) 0.7 Vee Vee+ 0.5 V
VOL Output Low Voltage (Note 5) 0.3 V IOL = 100 /LA (Note 1)
(Ports 1, 2, and 3)
0.45 V IOL = 1.6 mA (Note 1)
1.0 V IOL = 3.5 mA (Note 1)
VOL1 Output Low Voltage (Note 5) 0.3 V IOL = 200 /LA (Note 1)
(Port 0, ALE, PSEN)
0.45 V IOL = 3.2 mA (Note 1)
1.0 V IOL = 7.0 mA (Note 1)
VOH Output High Voltage Vee- 0.3 V IOH = -10/LA
(Ports 1, 2, and 3, ALE, PSEN)
Vee- 0.7 V IOH = -30/LA
Vee- 1.5 V IOH = -60/LA
VOH1 Output High Voltage Vee- 0.3 V IOH = -200/LA
(Port 0 in External Bus Mode)
Vee- 0.7 V IOH = -3.2mA
Vee- 1.5 V IOH = -7.0mA
IlL Logical 0 Input Current -50 /LA VIN = 0.45V
(Ports 1, 2, and 3)
III Input leakage Current (Port 0) ±10 /LA 0.45 < VIN < Vee
ITL Logical 1 to 0 Transition Current -650 /LA VIN = 2V
(Ports 1, 2, and 3)
RRST RST Pulldown Resistor 40 225 KO
CIO Pin Capacitance 10 pF @1 MHz, 25·C
Icc Power Supply Current: (Note 3)
Running at 12 MHz (Figure 5) 20 40 mA
Idle Mode at 12 MHz (Figure 5) 5 10 mA
Power Down Mode 15 100 /LA
7-201
87C58/80C58
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4V to be superimposed on the VOlS of
ALE and Ports 1. 2. and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when
these pins change from 1 to O. In applications where capacitive loading exceeds 100 pF. the noise pulses on these signals
may exceed O.SV. It may be desirable to qualify ALE or othor signals with Schmitt triggers or CMOS-level input logic.
2. Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the 0.9 Vee specification when the
address lines are stabilizing.
3. See Figures 6-9 for test conditions. Minimum Vee for Power Down is 2V.
4. Typicals are based on limited number of samples and are not guaranteed. The values listed are at room temperature and
5V.
5. Under steady state (non-transient) conditions. IOl must be externally limited as follows:
Maximum IOl per port pin: lOrnA
Maximum IOl per S-bit port-
Port 0: 26 mA
Ports 1. 2 and 3: 15 rnA
Maximum total IOL for all output pins: 71 mA
If IOl exceeds the test condition. VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
SOmA
50mA
40 rnA
30mA
20mA
lOrnA
TYPICAL
IDLE
OmA
Ot.tHz 4t.tHz Bt.tHz ISt.tHz·
270900-6
ICC Max at other frequencies is given by:
Active Mode
Icc Max ~ (Ose Freq x 3) + 4
Idle Mode
Icc Max ~ (Osc Freq X 0.5) + 4
Where Osc Freq is in MHz, Icc is in rnA.
Figure 5. Icc vs Frequency
7-202
inter 87C58/80C58
Vee
Vee PO PO
RST EA RST EA 1----,
8XC58 8XC58
(NC) XTAL2 eLOCK (NC) XTAL2
CLOCK
XTAL1 XTAL1
SIGNAL SIGNAL
VSS Vss
270900-7 270900-8
All other pins disconnected All other pins disconnected
TCLCH ~ TCHCL ~ 5 ns TCLCH ~ TCHCL ~ 5 ns
Figure 6. Icc Test Condition, Active Mode Figure 7. Icc Test Condition Idle Mode
Vee
Ilee
, vee
Vee
PO
RST EA 1----,
8XC58
XTAL2
XTAL1
Vss
270900-9
All other pins disconnected
Figure 8. Icc Test Condition, Power Down Mode
Vcc = 2.0V to 6.0V
Vee-O.5 • - - - - - -'1'"""-----~
0.7 Vee
O.45V---1(O.2 Vee-0.1
TCHCL
270900-10
Figure 9. Clock Signal Waveform for Icc Tests in Active and Idle Modes. TCLCH = TCHCL = 5 ns
7-203
infef 87C58/80C58
EXPLANATION OF THE AC SYMBOLS P:PSEN
Q: Output Data
Each timing symbol has 5 characters. The first char-
acter is always a 'T' (stands for time). The other R: AD signal
characters, depending on their positions, stand for T: Time
the name of a signal or the logical status of that V: Valid
signal. The following is a list of all the characters and
what they stand for. W: WA signal
X: No longer a valid logic level
A: Address Z: Float
C: Clock
D: Input Data For example,
H: Logic level HIGH TAVLL = Time from Address Valid to ALE Low
I: Instruction (program memory contents) TLLPL = Time from ALE Low to PSEN Low
L: Logic level LOW, or ALE
A.C. CHARACTERISTICS (Under Operating Conditions, Load Capacitance for Port 0, ALE/PAOG and
PSEN = 100 pF, Load Capacitance for All Other Outputs = 80 pF)
ADVANCED INFORMATION-CONTACT INTEL FOR DESIGN-IN INFORMATION
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
12 MHz Oscillator Variable Oscillator'
Symbol Parameter Units
Min Max Min Max
1/TCLCL Oscillator Frequency 3.5 16 MHz
TLHLL ALE Pulse Width 127 2TCLCL-40 ns
TAVLL Address Valid to ALE Low 43 TCLCL-40 ns
TLLAX Address Hold After ALE Low 53 TCLCL-30 ns
TLLlV ALE Low to Valid Instruction In 234 4TCLCL-100 ns
TLLPL ALE Low to PSEN Low 53 TCLCL-30 ns
TPLPH PSEN Pulse Width 205 3TCLCL-45 ns
TPLIV PSEN Low to Valid Instruction In 145 3TCLCL-105 ns
TPXIX Input Instruction Hold After PSEN 0 0 ns
TPXIZ Input Instruction Float After PSEN 59 TCLCL-25 ns
TAVIV Address to Valid Instruction In 312 5TCLCL-105 ns
TPLAZ PSEN Low to Address Float 10 10 ns
TRLRH RD Pulse Width 400 6TCLCL-100 ns
TWLWH WR Pulse Width 400 6TCLCL-100 ns
TRLDV RD Low to Valid Data In 252 5TCLCL-165 ns
TRHDX Data Hold After RD 0 0 ns
TRHDZ Data Float After RD 107 2TCLCL-60 ns
TLLDV ALE Low to Valid Data In 517 8TCLCL-150 ns
TAVDV Address to Valid Data In 585 9TCLCL-165 ns
TLLWL ALE Low to RD or WR Low 200 300 3TCLCL-50 3TCLCL+50 ns
TAVWL Address Valid to WR Low 203 4TCLCL-130 ns
TOVWX Data Valid before WR 33 TCLCL-50 ns
TWHOX Data Hold after WR 33 TCLCL-50 ns
TOVWH Data Valid to WR High 433 lTCLCL-150 ns
TRLAZ RD Low to Address Float 0 0 ns
TWHLH RD or WR High to ALE High 43 123 TCLCL-40 TCLCL+40 ns
7-204
intJ 87C58/80C58
EXTERNAL PROGRAM MEMORY READ CYCLE
ALE _ _J
PSEN _ _J
PORT 0 _ _.J
PORT 2 _ _ _ _ _ _-',~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ J A8-A15
270900-11
EXTERNAL DATA MEMORY READ CYCLE
ALE
PSEN
I--'----TLLDV 'I
RD --------+-------~
--1--- TRLRH ----I
,-------------------
PORTO INSTR. IN
PORT2 P2.0-P2.7 OR AB-AI5 FRO lit DPH AB-A 15 FROIIt PCH
: 270900-12
7-205
inter 87C58/80C58
EXTERNAL DATA MEMORY WRITE CYCLE
ALE '\ I \.
TLHLL- P-TWHLH
I------- TLLWL
,
TWLWH
.... TAVLL
-
-TLLAX- ~
I
.... -TWHQX
TQVWH
PORTO
:::r FROINI~k OPL
TAVWL
DATA OUT AO-A7 FROM PCL INSTR. IN
PORT2 =:) P2.O-P2.7 OR A8-A15 FROM DPH A8-A 15 FROM PCH
270900-13
SERIAL PORT TIMING - SHIFT REGISTER MODE
Test Conditions: TA = O°C to + 70°C; Vee = 5V ±20%; vss = OV; Load Capacitance = 80 pF
12 MHz Oscillator Variable Oscillator
Symbol Parameter Units
Min Max Min Max
TXLXL Serial Port Clock Cycle Time 1 12TCLCL /..I.s
TOVXH Output Data Setup to Clock 700 1OTCLCL -133 ns
Rising Edge
TXHOX Output Data Hold after 50 2TCLCL-117 ns
Clock Rising Edge
. TXHDX Input Data Hold After Clock 0 0 ns
Rising Edge
TXHDV Clock Rising Edge to Input 700 1OTCLCL -133 ns
Data Valid'
SHIFT REGISTER MODE TIMING WAVEFORMS
INSTRUCTION I o 2 3 4 5 6 7 8
ALE
CLOCK
OUTPUT DATA
'--.;;..--:-''-.....;.~ ,--';;""',J
X 3 X 4 X 5 X 6 X 7 tI
I
WRITE TO SBUF SET TI
INPUT DATA -----'V'':'~,...~~iJ-_.,.~~-'V":'~,...~~~_.,.~~-'V":'~,...~~':!.I
I t
CLEAR RI SET RI
270900-14
7-206
inter 87C58/80C58
EXTERNAL CLOCK DRIVE
Symbol Parameter Min r.nax Units
1/TCLCL Oscillator Frequency
8XC58 3.5 12
MHz
8XC5B-1 3.5 16
TCHCX High Time 20 ns
TCLCX Low Time 20 ns
TCLCH Rise Time 20 ns
TCHCL Fall Time 20 ns
EXTERNAL CLOCK DRIVE WAVEFORM
270900-15
A.C. TESTING INPUT
Input, Output Waveforms Float Waveforms
VCC-0.5~ 0.2 VCC+0.9 V- TIMING REFERENCE
0.45 V ---./\_0_.2_V.;:..CC_-_O_.1_ _ _ _ 1'L POINTS
270900-16
For timing purposes a port pin is no longer floating when a·
AC Inputs during testing are driven at Vcc-0.5V for a Logic "1"
100 mV change from load voltage occurs, and begins to float
and 0.45V for a Logic "0". Timing measurements are made at VIH
when a 100 mV change from the loaded VOHIVOl level occurs.
min for a Logic "1" and Vil max for a Logic "0".
IOl/lOH :;, ± 20 mAo
Table 2. EPROM Programming Modes
ALEI EAI
Mode RST PSEN P2.6 P2.7 P3.3 P3.6 P3.7
PROG Vpp
Program Code Data H L Lr 12.75V L H H H H
Verify Code Data H L H H L L L H H
Program Encryption H L Lr 12.75V L H H L H
Array Address 0-3FH
Program Lock Bit 1 H L Lr 12.75V H H H H H
Bits
Bit 2 H L Lr 12.75V H H H L L
Bit 3 H L Lr 12.75V H L H H L
Read Signature Byte H L H H L L L L L
7-207
intJ 87C58/80C58
DEFINITION OF TERMS PROGRAMMING ALGORITHM
ADDRESS LINES: P1.0-P1.7, P2.0-P2.5, P3.4 re- Refer to Table 2 and Figures 10 and 11 for address, '
spectively for AO-A14. data, and control signals set up. To program the
B7C5B the following sequence must be exercised.
DATA LINES: PO.0-PO.7 for 00-07. 1. Input the valid address on the address lines.
CONTROL SIGNALS: RST, PSEN, P2.6, P2.7, P3.3, 2. Input the appropriate data byte on the data
P3.6, P3.7, ' lines.
3. Activate the correct combination of control sig-
PROGRAM SIGNALS: ALE/PROG, EAlVpp nals.'
4. Raise EAlVpp from Vee to 12.75V ±0.25V.
PROGRAMMING THE EPROM 5. Pulse ALE/PROG5 times for the EPROM ar-
ray, and 25 times for the encryption table and
The part must be running with a 4 MHz to 6 MHz the lock bits.
oscillator. The address of an EPROM location to be
programmed is applied to address lines while the Repeat 1 through 5 changing the address and data
code byte to be programmed in that location is ap- for the entire ~rray or until the end of the object file is
plied to data lines. Control and program signals must reached.
be held at the levels indicated in Table 2. Normally
EAlVpp is held at logic high until just before ALEI
PROG is to be pulsed. The EAlVpp is raised to Vpp, PROGRAM VERIFY
ALE/PROG is pulsed low and then EAlVpp is re-
turned to a high (also refer to timing diagrams). Program verify may be done after each byte that is
programmed, or after a block of bytes that is pro-
NOTE: ' grammed. In either case a complete verify of the
Exceeding the Vpp maximum for any amount of entire array that has been programmed will ensure a
time could damage the device permanently. The reliable programming of the 87C58.
Vpp source must be well regulated and free of
glitches. The lock bits cannot be directly verified. Verification
of the lock bits is done' by observing that their fea-
tures are enabled. Refer to the EPROM Program
Lock section in this data sheet.
+5V
Vee 40
1-8 8XC58 32-39
AO-A7 PI PO PGM DATA
21-26 31
P2.0-
A8-A13 fA/vpp PROGRAM
P2:S }
30
~~_ SIGNALS
ALE/PROG
14 29
A14 P3.4 PSEN
28
P2.7
27
P2.6
XTAL2 17
P3.7 CONTROL SIGNALS'
16
P~.6
13
XTAL 1 P3.3
9
Vss' ' RST,
270900-18
'See Table 2 for proper input on these pins
Figure 10. Programming the EPROM
7-208
infef 87C58/80C58
ADDRESS
X 14 BITS
X
DATA
X B BITS
X
CONTROL
SIGNALS X 7 BITS
X
12.7SV
fA/Vpp
ALE/PROG
sv -.! TGLGH '-
270900-19
5 Pulses
Figure 11. Programming Signal's Waveforms
ROM and EPROM Lock System Program Lock Bits
The B7C58 and the BOC5B program lock systems, The B7C5B has 3 programmable lock bits that when
'when programmed, protect the on board program programmed according to Table 3 will provide differ-
against software piracy. ent levels of protection for the on-chip code and
data.
The 80C58 has a one-level program lock system
and a 64-byte encryption table. See line 2 of Table Erasing the EPROM also erases the encryption ar-
3. If program protection is desired, the user submits ray and the program lock bits, returning the part to
the encryption table with their code, and both the full functionality.
lock-bit and encryption array are programmed by the
factory. The encryption array is not available without
the lock bit. For the lock bit to be programmed, the Reading the Signature Bytes
user must submit an encryption table.
The B7C5B/80C5B each has 3 signature bytes in lo-
The B7C58 has a 3-level program lock system and a cations 30H, 31 H, and 60H. To read these bytes fol-
64-byte encryption array. Since this is an EPROM low the procedure for EPROM verify, but activate
device, all locations are user programmable. See the control lines provided in Table 2 for Read Signa-
Table 3. ture Byte.
Content
Encryption Array Location
87CS8 80CS8
Within the EPROM array are 64 bytes of Encryption
30H B9H B9H
Array that are initially unprogrammed (all 1's). Every
time that a byte is addressed during a verify, 6 ad- 31H 58H 5BH
dress lines are used to select a byte of the Encryp- 60H 58H 5BH/1BH
tion Array. This byte is then exclusive-NOR'ed
(XNOR) with the code byte, creating an Encryption
Verify byte. The algorithm, with the array in the un- Erasure Characteristics (Windowed
programmed state (all 1's), will return the code in it's Packages Only)
original, unmodified form. For programming the En-
cryption Array, refer to Table 2 (Programming the Erasure of the EPROM begins to occur when the
EPROM). chip is exposed to light with wavelength shorter than
7-209
intJ 87C58/80C58
approximately 4,000 Angstroms. Since sunlight and The recommended erasure procedure is exposure
fluorescent lighting have wavelengths in this range, to ultraviolet light (at 2537 Angstroms) to an integrat-
exposure to these light sources over an extended ed dose of at least 15 W-sec/cm 2 . Exposing the
time (about 1 week in sunlight, or 3 years in room- EPROM to an ultraviolet lamp of 12,000 IJ-W/cm 2
level fluorescent lighting) could cause inadvertent rating for 30 minutes, at a distance of about 1 inch,
erasure. If an application subjects the device to this should be sufficient.
type of exposure, it is suggested that an opaque la-
bel be placed over the window. Erasure leaves all the EPROM Cells in a 1 's state.
Table 3. Program Lock Bits and the Features
Program Lock Bits
Protection Type
LB1 LB2 LB3
1 U U U No Program Lock features enabled. (Code verify will still be encrypted by the
Encryption Array if programmed.)
2 P U U MOVC instructions executed from external program memory are disabled
from fetching code bytes from internal memory, EA is sampled and latched on
Reset, and further programming of the EPROM is disabled.
3 P P U Same as 2, also verify is disabled.
4 P P P Same as 3, also external execution is disabled.
Any other combination of the lock bits IS not defined.
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
(TA = 21°C to 27"C; Vee = 5V ±20%; vss = OV)
ADVANCED INFORMATION-CONTACT INTEL FOR DESIGN-IN INFORMATION
Symbol Parameter Min Max Units
Vpp Programming Supply Voltage 12.5 13.0 V
Ipp Programming Supply Current 75 mA
1/TCLCL Oscillator Frequency 4 6 MHz
TAVGL Address Setup to PROG Low 48TCLCL
TGHAX Address Hold after PROG 48TCLCL
TDVGL Data Setup to PROG Low 48TCLCL
TGHDX Data Hold after PROG 48TCLCL
TEHSH (Enable) High to Vpp 48TCLCL
TSHGL Vpp Setup to PROG Low 10 IJ-s
TGHSL Vpp Hold after PROG 10 IJ-s
TGLGH PROG Width 90 110 IJ-s
TAVOV Address to Data Valid 48TCLCL
TELOV ENABLE Low to Data Valid 48TCLCL
TEHOZ Data Float after ENABLE 0 48TCLCL
TGHGL PROG High to PROG Low 10 IJ-s
7-210
intJ 87C58/80C58
EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
PROGRAMMING VERIFICATION
AO-A15 -----1::=~~~ ADDRESS
-TAVQV
00-07 -----1{=~~~ DATA OUT
TDVGL
TAVGL
ALE/PROG ------'\1
TSHGL r----
TGLGH
EA/Vpp VCC If VPP
-"';';;'--*-.--+1.
CONTROL _ _ _• •
TEHSH TEHQZ
SIGNALS
(ENABLE) - - -
270900-20
DATA SHEET REVISION SUMMARY
This is Rev.1 of the 87C58/80C58 Data Sheet.
7·211
inter
87C58/80C58
EXPRESS
87CS8/80CS8-3.S MHz to 12 MHz, Vee = SV ± 20%
87CS8-1I80CS8-1-3.S MHz to 16 MHz, Vee = SV ± 20%
• Extended Temperature Range • Burn-In
The Intel EXPRESS system offers enhancements to the operational specifications of the MCS@-S1 family of
microcontrollers. These EXPRESS products are designed to meet the needs of those applications whose
operating requirements exceed commercial standards.
The EXPRESS program includes the commercial standard temperature range with burn-in and an extended
temperature range with or without burn-in.
With the commercial standard temperature range, operational characteristics are guaranteed over the temper-
ature range of O·C to 70·C. With the extended temperature range option, operational characteristics are
guaranteed over the range of - 40·C to + 8S·C.
The optional burn-in is dynamic for a minimum time of 168 hours at 12S·C with Vee = 6.9V ·±0.2SV, following
guidelines in MIL-STD-883, Method 101S.
Package types and EXPRESS versions are identified by a one- or two-letter prefix to the. part number. The
prefixes are listed inTable 1.
For the extended temperature range option, this data sheet specifies the parameters which deviate from their
commercial temperature range limits. The commercial temperature range data sheets are applicable for all
parameters not listed here. .
This data sheet is valid in conjunction with the commercial 87CS8/80CS8 data sheet, 270900-001.
September 1990
7-212 Order Number: 270902-001
inter 87C58/80C58 EXPRESS
Electrical Deviations from Commercial Specifications for Extended Temperature
Range
O.C. and A.C. parameters not included here are the same as in the commercial temperature range data
sheets.
D.C. CHARACTERISTICS TA = -40'C to + BS'C; Vcc = SV ±20%; Vss = OV
Limits Test
Symbol Parameter Unit
Min I Max Conditions
ITL Logical 1 to 0 Transition Current (Ports 1,2 and 3) I -7S0 /J-A VIN = 2V
Table 1. Prefix Identification
Prefix Package Type Temperature Range Burn-In
P Plastic Commercial No
O' Cerdip Commercial No
N PLCC Commercial NQ
TP Plastic Extended No
TO' Cerdip· Extended No
TN PLCC Extended No
LP Plastic Extended Yes
LO* Cerdip Extended Yes
LN PLCC Extended Yes
NOTE:
• Commercial temperature range is O'C to 70'C. Extended temperature range is -40'C to +85'C.
• Burn-in is dynamic for a minimum time of 168 hours at 125'C, Vee = 6.9V ±0.25V, following guidelines in MIL-ST0-883
Method 1015 (Test Condition OJ.
EXAMPLES:
PBOC5B indicates BOC5B in a plastic package and specified for commercial temperature range, without burn-in.
LOBOC5B indicates BOC5B in a cerdip package and specified for extended temperature range with burn-in.
"Available in EPROM version only.
DATA SHEET REVISION SUMMARY
This is the -001 version of the B7CSB/BOCSB Express .data sheet.
7-213
8XC51FX Hardware 8
Description and Data Sheets
October 1990
8XC51FX
Hardware Description
Order Number: 270653-003
8-1
HARDWARE DESCRIPTION OF THE 8XC51FX
CONTENTS PAGE CONTENTS PAGE
7.4 Baud Rates ....................... 8-30
1.0 INTRODUCTION ..................... 8-3
7.5 Using Timer 1 to Generate Baud
2.0 MEMORY ............................ 8-3 Rates .............................. 8-30
2.1 Program Memory .................. 8-3 7.6 USing Timer 2 to Generate Baud
Rates .............................. 8-30
2.2 Data Memory ...................... 8-3
8.0 INTERRUPTS ....................... 8-32
3.0 SPECIAL FUNCTION
REGISTERS ............................ 8-4 8.1 External Interrupts ................ 8-33
8.2 Timer Interrupts .................. 8-33
4.0 PORT STRUCTURES AND
OPERATION ........................... 8-7 8.3 PCA Interrupt ..................... 8-33
4.1 I/O Configurations .-................ 8-7 8.4 Serial Port Interrupt ............... 8-33
4.2 Writing to a Port ................... 8-8 8.5 Interrupt Enable .................. 8-33
4.3 Port Loading and Interfacing ...... 8-10 8.6 Priority Level Structure ............ 8-33
4.4 Read-Modify-Write Feature ....... 8-10 8.7 Response Time ................... 8-37
.4.5 Accessing External Memory ....... 8-10 9.0 RESET .............................. 8-37
5.0 TIMERS/COUNTERS ............... 8-12 9.1 Power-On Reset .................. 8-38
5.1 TIMER 0 AND TIMER 1 ........... 8-12 10.0 POWER·SAVING MODES OF
5.2 TIMER 2 .......................... 8-15 OPERATION ......................... 8-38
10.1 Idle Mode ....................... 8-38
6.0 PROGRAMMABLE COUNTER
ARRAY ... ............................ 8-18 10.2 Power Down Mode .............. 8~40
6.1 PCA 16-BitTimer/Counter ........ 8-20 10.3 ~ower Off Flag .................. 8-40
6.2 Capture/Compare Modules ....... 8-22 11.0 EPROM VERSIONS . ............... 8-40
6.316-Bit Capture Mode .............. 8-24
12.0 PROGRAM MEMORY LOCK ....... 8-40
6.4 16-Bit Software Timer Mode ...... 8-24
6.5 High Speed Output Mode ......... 8-25 13.0 ONCE MODE _...................... 8-41
6.6 Watchdog Timer Mode ............ 8-25
14.0 ON·CHIP OSCiLLATOR ........... 8-41
6.7 Pulse Width Modulator Mode ...... 8-26
15.0 CPU TIMING . ...................... 8-43
7.0 SERIAL INTERFACE ............... 8-27
7.1 Framing Error Detection .......... 8-28
7.2 Multiprocessor Communications .. 8-28
7.3 Automatic Address Recognition ... 8-28
8-2
8XC51FX HARDWARE DESCRIPTION
1.0 INTRODUCTION Table 1. C51FX Family of Microcontrol\ers
The 8XC5lFX is a highly integrated 8·bit microcon- ROMI
ROM EPROM ROMless RAM
troller based on the MCS-5l architecture. As a member EPROM
Device Version Version Bytes
of the MCS-5l family, the 8XC51FX is optimized for Bytes
control applications. Its key feature is the programma- 83C51FA 87C51FA 80C51FA 81S- 256
ble counter array (PCA) which is capable of measuring
and generating pulse information on five I/O pins: Also 83C51FB 87C51FB 80C51FA 16K 256
included are an enhanced serial port for multi-proces- 83C51 FC 87C51 FC 80C51FA 32K 256
sor communications, an up/down timer/counter, and a
program lock scheme for the on-chip program memory.
Since the 8XC51FX products are CHMOS, they have
two software selectable reduced power modes: Idle 2.0 MEMORY ORGANIZATION
Mode and Power Down Mode.
All MCS-51 devices have a separate address space for
The 8XCSIFX uses the standard 8051 instruction set Program and Data Memory. Up to 64 Kbytes each of
and is pin-for-pin compatible with the existing MCS-51 external Program and Data Memory can be addressed.
family of products.
This document presents a comprehensive description of 2.1 Program Memory
the on-chip hardware features of the 8XC5IFX. It be-
gins with a discussion of the on-chip memory and then If the EA pin is connected to Vss, all program fetches
discusses each of the peripherals listed below. Please are directed to external memory. On the 83C51FA (or
note that the 8XC51FC has some additional features 87C51FA), if the EA pin is connected to Vee, then
not found on the 8XC51FA/FB. They are: program- program fetches to addresses OOGOH through IFFFH
mable clock out, four level interrupt priority structure, are directed to internal ROM and fetches to addresses
enhanced program lock scheme and asynchronous port 2GOOH through FFFFH are to external memory.
reset.
On the 83C51FB (or 87C51FB) if EA is connected to
o Four 8-Bit Bidirectional Parallel Ports VCC, program fetches to addresses GOOOH through
.. Three 16-Bit Timer/Counters with 3FFFH are directed to internal ROM, and fetches to
- One Up/Down Timer/Counter addresses 4GOOH through FFFFH are to external mem-
ory.
- Clock Out (8XC51FC)
• Programmable Counter Array with On the 83C51FC (or 87CSIFC) if EA is connected to
Compare/Capture Vee, program fetches to addresses OOOOH through
7FFFH are directed to internal ROM or EPROM and
Software Timer fetches to addresses 8000H through FFFFH are to ex-
High Speed Output ternal memory.
Pulse Width Modulator
- Watchdog Timer 2.2 Data Memory
• Full-Duplex Programmable Serial Port with
The C51FX implements 256 bytes of on-chip data
- Framing Error Detection
RAM. The upper 128 bytes occupy a parallel address
- Automatic Address Recognition space to the Special Function Registers. That means
• Interrupt Structure with they have the same addresses, but are physically sepa-
rate from SFR space.
- Seven Interrupt Sources
- Two Priority Levels (Four on 8XC51FC) When an instruction accesses an internal location above
.. Power-Saving Modes address 7FH, the CPU knows whether the access is to
the upper 128 bytes of data RAM or to SFR space by
Idle Mode
the addressing mode used in the instruction. Instruc-
- Power Down Mode tions that use direct addressing access SFR space. For
example:
Table 1 summarizes the product names and memory
differences of the various 8XC5lFX products currently MOVOAOH, # data
available. Throughout this document, the products will
generally be referred to as the C51 FX.
8-3
inter 8XC51FX HARDWARE DESCRIPTION
PO.O-PO.7
,.----- ----,
v~
vss
E
!'SEN
ALE/i'llOG
EA/vpp
RST
270653-1
Figure 1. 8XC51FX Functional Block Diagram
accesses the SFR at location OAOH (which is P2). In- 3.0 SPECIAL FUNCTION REGISTERS
structions that use indirect addressing access the upper
128 bytes of data RAM. For example: A map of the on-chip memory area called the SFR
(Special Function Register) space is shown in Table 2.
MOV @RO,#data
Note that not all of the addresses are occupied. Unoc-
where RO contains OAOH, accesses the data byte at ad- cupied addresses are not implemented on the chip.
dress OAOH, rather than P2 (whose address is OAOH). Read accesses to these addresses will in general return
Note that stack operations are examples of indirect ad- random data, and write accesses will have no effect.
dressing, so the upper 128 bytes of data RAM are avail-
able as stack space.
8-4
8XC51FX HARDWARE DESCRIPTION
User software should not write Is to these unimple- The functions of the SFRs are outlined below. More
mented locations, since they may be used in future information on the use of specific SFRs for each periph-
MCS-51 products to invoke new features. In that case eral is included in the description of that peripheral.
the reset or inactive values of the new bits will always
be 0, and their active values will be 1. Accumulator: ACC is the Accumulator register. The
mnemonics for Accumulator-Specific instructions,
however, refer to the Accumulator simply as A.
Table 2. SFR Mapping and Reset Values
F8 CH CCAPOH CCAP1H CCAP2H CCAP3H CCAP4H FF
00000000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
FO • B F7
00000000
E8 CL CCAPOL CCAP1L CCAP2L CCAP3L CCAP4L EF
00000000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EO • ACC E7
00000000
08 CCON CMOO CCAPMO CCAPM1 CCAPM2 CCAPM3 CCAPM4 OF
OOXOOOOO OOXXXOOO XOOOOOOO XOOOOOOO XOOOOOOO XOOOOOOO XOOOOOOO
DO 'PSW 07
00000000
C8 T2CON T2MOO RCAP2L RCAP2H TL2 TH2 CF
00000000 XXXXXXXO 00000000 00000000 00000000 00000000
CO C7
B8 • IP SAOEN BF
XOOOOOOO 00000000
BO , P3 "'IPH B7
11111111 XOOOOOOO
A8 'IE SAOOR AF
00000000 00000000
AO • P2 A7
11111111
98 * SCON * SBUF 9F
00000000 XXXXXXXX
90 • P1 97
11111111
88 • TCON *TMOO • TLO • TL1 • THO • TH1 8F
00000000 00000000 00000000 00000000 00000000 00000000
80 • PO • SP • OPL • OPH • PCON" 87
11111111 00000111 00000000 00000000 OOXXOOOO
• = Found in the 8051 core (See 8051 Hardware Description for explanations of these SFRs).
•• = See description of PCON SFR. Bit PCON.4 is not affected by reset.
**.= 8XC51 FC only.
X = Undefined.
8-5
inter 8XC51FX HARDWARE DESCRIPTION
Table 3. PSW: Program Statue Word Register
PSW Address = ODOH Reset Value = 0000 OOOOB
Bit Addressable
CY AC FO RS1 RSO OV P
Bit 7 6 5 4 3 2 o
Symbol Function
CY Carry flag.
AC Auxiliary Carry flag. (For BCD Operations)
FO Flag O. (Available to the user for general purposes).
RS1 Register bank select bit 1.
RSO Register bank select bit o.
RS1 RSO Working Register Bank and Address
o o Bank 0 (OOH-07H)
o 1 Bank 1 (08H-OFH)
1 o Bank 2 (10H-17H)
1 1 Bank 3 (18H-1 FH)
OV Overflow flag.
User definable flag.
P Parity flag. Set!cleared by hardware each instruction cycle to indicate an odd/even
number of "one" bits in the Accumulator, I.e., even parity.
B Register: The B register is used during multiply and RCAP2L) are the capture/reload registers for Timer 2
divide operations. For other instructions it can be treat- in 16-bit capture mode or 16-bit auto-reload mode.
ed as another scratch pad register.
Programmable Counter Array (PCA) Registers: The
Stack Pointer: The Stack Pointer Register is 8 bits 16-bit PCA timer/counter consists of registers CH and
wide. It is incremented before data is stored during CL. Registers CCON and CMOD contain the control
PUSH and CALL executions. The stack may reside and status bits for the PCA. The CCAPMn (n = 0, I,
anywhere in on-chip RAM. On reset, the Stack Pointer 2, 3, or 4) registers control the mode for each of the five
is initialized to 07H causing the stack to begin at loca- PCA modules. The register pairs (CCAPnH, CCAPnL)
tion 08H. are the 16-bit compare/capture registers for each PCA
module.
Data Pointer: The Data Pointer (DPTR) consists of a
high byte (DPH) and a low byte (DPL). Its intended Serial Port Registers: The Serial Data Buffer, SBUF,
function is to hold a 16-bit address, but it may be ma- is actually two separate registers: a transmit buffer and
nipulated as a 16-bit register or as two independent a receive buffer register. When data is moved to SBUF,
8~bit registers. it goes to the transmit buffer where it is held for serial
transmission. (Moving a byte to SBUF initiates the
Program Status Word: The PSW register contains pro- transmission). When data is moved from SBUF, it
gram status information as detailed in Table 3. comes from the receive buffer. Register SCON contains
the control and status bits for the Serial Port. Registers
Ports 0 to 3 Registers: PO, PI, P2, and P3 are the SFR SADDR and SADEN are used to define the Given and
latches of Port 0, Port 1, Port 2, and Port 3 respective- the Broadcast addresses for the Automatic Address
ly. Recognition feature.
Timer Registers: Register pairs (THO, TLO),(THl, Ihterrupt Registers: The individual interrupt enable
TLl), and (TH2, TL2) are the 16-bit count registers for bits are in the IE register. Two priorities can be set for
Timer/Counters 0, 1, and 2 respectively. Control and each of the 7 interrupts in the IP regis~er.
status bits are contained in registers TCON and TMOD
for Timers 0 and 1 and in registers T2CON and Power Control Register: PCON controls the Power
T2MOD for Timer 2. The register pair (RCAP2H, Reduction Modes. Idle and Power Down Modes.
8-6
8XC51FX HARDWARE DESCRIPTION
4.0 PORT STRUCTURES AND Table 4. Alternate Port Functions
OPERATION
Port Pin Alternate Function
All four ports in the C5IFX are bidirectional. Each
consists of a latch (Special Function Registers PO PO.O/ ADO- Multiplexed Byte of Address/Data for
through P3), an output driver, and an input buffer. PO. 7/ ~D7 External Memory
P1.0/T2 Timer 2 External Clock Input/Clock-
The output drivers of Ports 0 and 2, and the input buff- Out'
ers of Port 0, are used in accesses to external memory. PI.l/T2EX Timer 2 Reload/Capture/Direction
In this application, Port 0 outputs the low byte of the Control
external memory address, time-multiplexed with the
byte being written or read. Port 2 outputs the high byte P1.2/ECI PCA External Clock Input
of the external memory address when the address is P1.3/CEXO PCA Module 0 Capture Input,
16 bits wide. Otherwise the Port 2 pins continue to emit Compare/PWM Output
the P2 SFR content. PI.4/CEXI PCA Module I Capture Input,
Compare/PWM Output
All the Port I and Port 3 pins are multifunctional.
They are not only port pins, but also serve the functions PI.5/CEX2 PCA Module 2 Capture Input,
of various special features as listed in Table 4. Compare/PWM Output
PI.6/CEX3 PCAModuie 3 Capture Input,
The alternate functions can only be activated if the cor- Compare/PWM Output
responding bit latch in the port SFR contains a I. Oth- P1.7 /CEX4 PCA Module 4 Capture Input,
erwise the port pin is stuck at O. Compare/PWM Output
P2.0/AS- High Byte of Address for External
4.1 I/O Configurations P2.7/AIS Memory
Figure 2 shows a functional diagram of a typical bit P3.0/RXD Serial Port Input
latch and I/O buffer in each of the four ports. The bit
latch (one bit in the port's SFR) is represented as a P3.l/TXD Serial Port Output
Type D flip-flop, which clocks in a value from the in- P3.2/INTO External InterrUpt 0
ternal bus in response to a "write to latch" signal from P3.3/INT External Interrupt I
the CPU. The Q output of the flip-flop is placed on the
internal bus in response to a "read latch" signal from P3.4/TO Timer 0 External Clock Input
the CPU. The level of the port pin itself is placed on the P3.5/Tl Timer I External Clock Input
internal bus in response to a "read pin" signal from the Write Strobe for External Memory
P3.6/WR
CPU. Some instructions that read a port activate the
"read latch" signal, and others activate the "read pin" P3.7/RD Read Strobe for External Memory
signal. See the Read-Modify-Write Feature section.
'Clock-Out IS present only on the 87C51 FC.
As shown in Figure 2, the output drivers of Ports 0 and
2 are switchable to an internal ADDRESS and AD-
DRESS/DATA bus by an internal CONTROL signal
for use in external memory accesses. During external
memory accesses, the P2 SFR remains unchanged, but
the PO SFR gets Is written to it.
8-7
inter 8XC51FX HARDWARE DESCRIPTION
A. Port 0 Bit B. Port 1 or Port 3 Bit
ADDR/DATA ALTERNATE
VCC OUTPUT
FUNCTION
READ
LATCH
WRITE INT. BUS
TO
LATCH WRITE
TO
LATCH
270653-2
ALTERNATE
INPUT
FUNCTION
270653-4
C. Port 2 Bit
ADDR
VCC
CONTROL
READ
LATCH
INT. BUS
WRITE
TO
LATCH
270653-3
'See Figure 4 for details of the internal pullup
Figure 2. C51FX Port Bit Latches and 1/0 Buffers
Also shown in Figure 2 is that if a PI or P3 latch When configured as inputs they pull high and will
contains a I, then the output level is controlled by the source current (IlL in the data sheets) when externally
signal labeled "alternate output function." The actual pulled low. Port 0, on the other hand, is considered
pin level is always available to the pin's alternate input "true" bidirectional, because it floats when configured
function, if any. as an input.
Ports I, 2, and 3 have internal pullups. Port 0 has open All the port latches have Is written to them by the reset
drain outputs. Each I/O line can be independently used function. If a 0 is subsequently written to a port latch, it
as an input or an output (Ports 0 and 2 may not be used can be reconfigured as an input by writing a 1 to it.
as general purpose I/O when being used as the AD-
DRESS/DATA BUS). To be used as an input, the port
bit latch must contain a I, which turns off the output 4.2 Writing to a Port
driver FET. On Ports 1,2, and 3, the pin is pulled high
by the internal pullup, but can be pulled low by an In the execution of an instruction that changes the
external source. value in a port latch, the new value arrives at the latch
during State 6 Phase 2 of the final cycle of the instruc-
Port 0 differs from the other ports in not having inter- tion. However, port latches are in fact sampled by their
nal pullups. The pullup FET in the PO output driver output buffers only during Phase 1 of any clock period.
(see Figure 2) is used only when the Port is emitting Is (During Phase 2 the output buffer holds the value it
during external memory accesses. Otherwise the pullup saw during the previous Phase 1). Consequently, the
FET is off. Consequently PO lines that are being used as new value in the port latch won't actually appear at the
output port lines are open drain. Writing a 1 to the bit output pin until the next Phase 1, which will be at SIPI
latch leaves both output FETs off, which floats the pin of the next machine cycle. Refer to Figure 3. For more
and allows it to be used as a high-impedance input. information on internal timings refer to,the CPU Tim-
Because Ports 1 through 3 have fixed internal pullups ing section.
they are sometimes call "quasi-bidirectional", ports.
8-8
inter 8XC51FX HARDWARE DESCRIPTION
I
STATE 41 STATE 51 STATE 61 STATE 1 ISTATE 21 STATE 31 STATE 41 STATE 51
~I~ ~I~ ~I~ ~I~ ~I~ ~I~ ~I~ ~I~
XTAL1:
INPUTS SAMPLED: n o'Pl'P2'P3
RST
PO'Pl,P2,P3~
RST=:r-l.-
MOV PORT, SRC: OLD DATA NEW DATA
SERIAL PORT
SHIFT CLOCK
(MODE 0)
--1 I--- RXD PIN SAMPLED RXD SAMPLED --l I--
270653-33
Figure 3. Port Operation
If the change requires a O-to-I transition in Ports I, 2, pFET 1 in is the transistor that is turned on for 2 oscil-
and 3, an additional pullup is turned on during SIPI lator periods after a O-to-l transition in the port latch.
and S1P2 of the cycle in which the transition occurs. A I at the port pin turns on pFET3 (a weak pull-up),
This is done to increase the transition speed. The extra through the invertor. This invertor and pFET form a
pullup can source about 100 times the current that the latch which hold the 1.
normal pullup can. The internal pullups are field-effect
transistors, not linear resistors. The pull-up arrange- If the pin is emitting a 1, a negative glitch on the pin
ments are shown in Figure 4. from some external source can tum off pFET3, causing
the pin to go into a float state. pFET2 is a very weak
The pullup consists of three pFETs. Note that an pullup which is on whenever the nFET is off, in tradi-
n-channel FET (nFET) is turned on when a logical 1 is tional CMOS style. It's only about V,O the strength of
applied to its gate, and is turned off when a logical 0 is pFET3. Its function is to restore a 1 to the pin in the
applied to its gate. A p-channel FET (pFET) is the event the pin had a 1 and lost it to a glitch.
opposite: it is on when its gate sees a 0, and off when its
gate sees a 1.
Vcc Vcc Vcc
6
FROM PORT
LATCH
INPUT Q----<>c;.
DATA
READ
PORT PIN
270653-5
CHMOS Configuration. pFET 1 is turned on for 2 osc. periods after Q makes a O-to-1 transition. During this time, pFET 1
also turns on pFET 3 through the inverter to form a latch which holds the 1. pFET 2 is also on. Port 2 is similar except
that it holds the strong pullup on while emitting 1s that are address bits. (See text, "Accessing External Memory".)
Figure 4. Ports 1 and 3 Internal Pullup Configurations
8-9
inter 8XC51FX HARDWARE DESCRIPTION
4.3 Port Loading and Interfacing DJNZ (decrement and jump if not zero, e.g.,
DJNZ P3, LABEL)
The output buffers of Ports I, 2, and 3 can each sink MOV, PX.Y, C (move carry bit to bit Y of Port X)
1.6 mA at 0.45 V. These port pins can be driven by
CLR px. Y (clear bit Y of Port X)
open-collector and open-drain outputs although O-to-I
transitions will not be fast since there is little current SETB px.y (set bit Y of Port X)
pulling the pin up. An input 0 turns offpullup pFET3,
leaving only the very weak pull up pFET2 to drive the It is not obvious that the last three instructions in this
transition. list are read-modify-write instructions, but they are.
They read the port byte, all 8 bits, modify the addressed
In external bus mode, Port 0 output buffers can each bit, then write the new byte back to the latch.
sink 3.2 mA at 0.45 V. However, as port pins they
require external pullups to be able to drive any inputs. The reason that read-modify-write instructions are di-
rected to the latch rather than the pin is to avoid a
See the latest revision of the data sheet for design-in possible misinterpretation of the voltage level at the
information. pin. For example, a port bit might be used to drive the
base of a transistor. When a I is written to the bit, the
transistor is turned on. If the CPU then reads the same
4.4 Read-Modify-Write Feature port bit at the pin rather than the latch, it will read the
Some instructions that read a port read the latch and base voltage of the transistor" and interpret it as a O.
others read the pin. Which ones do which? The instruc- Reading the latch rather than the pin will return the
tions that read the latch rather than the pin are the ones correct value of I.
that read a value, possibly change it, and then rewrite it
to the latch. These are called "read-modify-write" in-
structions. Listed below are the read-modify-write in-
4.5 Accessing External Memory
structions. When the destination operand is a port, or a Accesses to external memory are of two types: accesses
port bit, these instructions read the latch rather than to external Program Memory "and accesses to external
the pin: Data Memory. Accesses to external Program Memory
ANL (logical AND, e.g., ANL PI, A) use signal PSEN (program store enable) as the read
strobe. Accesses to external Data Memory use RD or
ORL (logical OR, e.g., ORL P2, A) WR (alternate functions of P3. 7 and P3.6) to strobe the
XRL (logical EX-OR, e.g., XRL P3, A) memory. Refer to Figures 5 through 7.
JBC Gump if bit = I and clear bit, e.g.,
Fetches from external Program Memory always use a
JBC Pl.l, LABEL)
16-bit address. Accesses to external Data Memory can
CPL (complement bit, e.g., CPL P3.0) use either a 16-bit address (MOVX @ DPTR) or an
INC (increment, e.g., INC P2) 8-bit address (MOVX @ Ri).
DEC (decrement, e.g., DEC P2)
I STATE
~I~
11 STATE 21 S~ATE 31 STATE 41 STATE 51 STATE 61 STATE 11 STATE 21
~I~ ~I~ ~I~ ~I~ ~I~ ~I~ ~I~
XTAL1:
ALE:
PSEN: ~
---+l
DATA
~SAMPLED
L
PO:
P2: PCH OUT PCH OUT PCH OUT
270653-30
Figure 5. External Program Memory Fetches
8-10
inter 8XC51FX HARDWARE DESCRIPTION
I ~In ~In
I
STATE 41 STATE 51 STATE 61 STATE 1 STATE 21 STATE 31 STATE 41 STATE 51
~In ~In ~In ~In ~In ~In
XTAL1:
ALE:
iiii:
po:
PCH OR PCH OR
P2: DPH OR n SFR OUT
P2SFR P2 SFR
270653-31
Figure 6. External Data Memory Read Cycle
ISTATE 41 STATE 51 STATE 61 STATE 11 STATE 21 STATE 31 STATE 41 STATE 51
~In ~In ~In ~In ~In ~In ~In ~In
XTAL1:
ALE:
WA: PCL OUT IF
t-"~- IS EXTERNAL
PO: -----I DPL OR RI
OUT
DATA OUT
~~f ~
P2 PCH OR PCH OR
DPH OR P2 SFR OUT
P2 SFR P2 SFR
270653-32
Figure 7. External Data Memory Write Cycle
8·11
intJ 8XC51FX HARDWARE DESCRIPTION
Whenever a 16-bit address is used, the high byte of the 5.0 TIMERS/COUNTERS
address comes out on Port 2, where it is held for the
duration of the read or write cycle. The Port 2 drivers The C51 FX has three 16-bit Timer/Counters: Timer 0,
use the strong pullups during the entire time that they Timer I, and Timer 2. Each consists of two S-bit regis-
are emitting address bits that arc Is. This occurs when ters, THx and TLx, (x = 0, I, and 2). All three can be
the MOVX @ DPTR instruction is executed. During configured to operate ,either as timers or event counters.
this time the Port 2 latch (the Special Function Regis-
ter) does not have to contain Is, and the contents of the In the Timer function, the TLx register is incremented
Port 2 SFR are not modified. If the external memory every machine cycle. Thus one can think of it as count-
cycle is not immediately followed by another external ing machine cycles. Since a machine cycle consists of 12
memory cycle, the undisturbed contents of the Port 2 oscillator periods, the count rate is 1/12 of the oscilla-
SFR will reappear in the next cycle. tor frequency.
If an S-bit address is being used (MOVX @ Ri), the In the Counter function, the register is incremented in
contents of the Port 2 SFR remain at the Port 2 pins response to a I-to-O transition at its corresponding ex-
throughout the external memory cycle. In ,this case, ternal input pin-TO, n, or T2. In this function, the
Port 2 pins can be used to page the extern~ data mem- external input is sampled during S5P2 of.every machine
ory. cycle. When the samples show a high in one cycle and a
low in the next cycle, the count is incremented. The
In either case, the low byte of the address is time-multi- new count value appears in the register during S3PI of
plexed with the data byte on Port O. The ADDRESS/ the cycle following the one in which the transition was
DATA signal drives both FETs in the Port 0 output detected. Since it takes 2 machine cycles (24 oscillator
buffers. Thus, in external bus mode the Port 0 pins are periods) to recognize a I-to-O transition, the maximum
not open-drain outputs and do not require external count rate is '124 of the oscillator frequency. There are
pullups. The ALE (Address Latch Enable) signal no restrictions on the duty cycle of the external input
should be used to capture the address byte into an ex- signal, but to ensilre that a given level is sampled at
ternal latch. The address byte is valid at the negative least once before it changes, it should be held for at
transition of ALE. Then, in a write cycle, the data byte least one full machine cycle.
to be written appears on Port 0 just before WR is acti-
vated, and remains there until after WR is deactivated. In addition to the Timer or Counter selection, Timer 0
In a read cycle, the ineomin~te is accepted at Port 0 and Timer 1 have four operating modes from which to •
just before the read strobe (RD) is deactivated. select: Modes 0 - 3. Timer 2 has three modes of opera-
tion:Capture, Auto-Reload, and Baud Rate Generator.
During any access to external memory, the CPU writes
OFFH to the Port 0 latch (the Special Function Regis-
ter), thus obliterating the information in the Port 0 5.1 Timer 0 and Timer 1
SFR. Also, a MOV PO instruction must not take place
during external memory accesses. If the user writes to The Timer or Counter function is selected by control
Port 0 during an external memory fetch, the incoming· bits CIT in the Special Function Register TMOD (Ta-
code byte is corrupted. Therefore, do not write to Port ble 5). These two Timer/Counters have four operating
o if external program memory is used. modes, which are selected by bit-pairs (Ml, MO) in
TMOD. Modes 0, I, and 2 are the same for both Tim-
External Program Memory is accessed under two con- er/Counters. Mode 3 operation is different for the two
ditions: timers.
1. Whenever signal EA is active, or
2. Whenever the program counter (PC) contains an ad- MOOED
dress greater than IFFFH (SK) for the SXC51FA or
3FFFH (16K) for the SXC5IFB, or 7FFFH (32K) Either Timer 0 or Timer 1 in Mode 0 is an 8-bit Coun-
for the S7C5IFC. ter with a divide-by-32 prescaler. Figure S shows the
Mode 0 operation for either timer.
This requires that the ROMless versions have EA wired
to Vss enable the lower SK, 16K, or 32K program In this mode, the Timer register is configured as a
bytes to be fetched from external memory. 13-bit register. As the count rolls over from all Is to all
Os, it sets the Timer interrupt flag TFx. The counted
When the CPU is executing out of external Program input is enabled to the Timer when TRx = 1 and either
Memory, all S bits of Port 2 are dedicated to an output GATE = 0 or INTx = 1. (Setting GAT:E = 1 allows
function and may not be used for general purpose I/O. the Timer to be controlled by external input INTx, to
During external program fetches they output the high facilitate pulse width measurements). TRx and TFx are
byte of the PC with the Port 2 drivers using the strong
pullups to emit bits that are Is.
8-12
8XC51FX HARDWARE DESCRIPTION
control bits in SFR TCON (Table 6). The GATE bit is MODE 2·
in TMOD. There are two different GATE bits, one for
Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3). Mode 2 configures the Timer register as an 8-bit Coun-
ter (TLx) with automatic reload, as shown in Figure 10.
The 13-bit register consists of all 8 bits of THx and the Overflow from TLx not only sets TFx, but also reloads
lower 5 bits of TLx. The upper 3 bits of TLx are inde- TLx with the contents of THx, which is preset by soft-
terminate and should be ignored. Setting the run flag ware. The reload leaves THx unchanged.
(TRx) does not clear these registers.
MODE 1
Mode 1 is the same as Mode 0, except that the Timer
register uses all 16 bits. Refer to Figure 9. In this mode,
THx and TLx are cascaded; there is no prescaler.
Table 5. TMOD:Timer/Counter Mode Control Register
TMOD Address = 89H Reset Value '= OOOOOOOOB
Not Bit Addressable
TIMER 1 TIMER 0
I GATE I CIT I M1 I MO GATE I CIT I M1 I MO I
Bit 7 6 5 4 3 2 o
Symbol Function
GATE Gating control when set. Timer/Counter 0 or 1 is enabled only while INTO or INT1 pin
is high and TRO or TR1 control pin is set. When cleared, Timer 0 or 1 is enabled
whenever TRO or TR1 control bit is set.
c/f Timer or Counter Selector. Clear for Timer operation (input from internal system
clock). Set for Counter operation (input from TO or T1 input pin).
M1 MO Operating Mode
o 0 8-bit Timer/Counter. THx with TLx as 5-bit prescaler.
o 1 16-bitTimer/Counter. THx and TLx are cascaded; there is no prescaler.
o 8-bit auto-reload Timer/Counter. THx holds a value which is to be reloaded into TLx
each time it overflows.
(Timer 0) TLO is an 8-bit Timer/Counter controlled by the standard Timer 0 control
bits. THO is an 8-bit timer only controlled by Timer 1 control bits.
(Timer 1) Timer/Counter stopped.
INTERRUPT
CONTROL OVERFLOW
Tx PIN - - - - - - '
GATE
x ~ 0 or 1
270653-6
Figure 8. Timer/Counter 0 or 1 in Mode 0: 13·Bit Counter
8-13
intJ 8XC51FX HARDWARE DESCRIPTION
Table 6. TCON: Timer/Counter Control Register
TCON Address = aaH Reset Value = 0000 00008
Bit Addressable
TF1 TR1 TFO TRO IE1 IT1 lEO ITO
Bit 7 6 5 4 3 2 o
Symbol Function
TF1 Timer 1 overflow Flag. Set by hardware onTimer/Counter overflow. Cleared by
hardware when processor vectors to interrupt routine.
TR1 Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter 1 on/off.
TFO Timer 0 overflow Flag. Set by hardware on Timer/Counter 0 overflow. Cleared by
hardware when processor vectors to interrupt routine.
TRO Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter 0 on/off.
IE1 Interrupt 1 flag. Set by hardware when external interrupt 1 edge is detected
(transmitted or level-activated). Cleared when interrupt processed only if transition-
activated.
IT1 Interrupt 1 Type control bit. Set/cleared QY software to specify falling edgellow level
triggered external interrupt 1 .
lEO Interrupt 0 flag. Set by hardware when external interrupt 0 edge is detected
(transmitted or level-activated). Cleared when interrupt processed only if transition-
activated.
ITO Interrupt 0 Type control bit. Set/cleared by software to specify falling edgellow level
triggered external interrupt O.
INTERRUPT
CONTROL OVERFLOW
Tx PIN - - - - - - '
TRx ---'---I
x~Oor1
GATE
INTxPIN
270653-34
Figure 9. Timer/Counter 0 or 1 in Mode 1: 16·Bit Counter
MODE 3 a timer function (counting machine cycles) and takes
over the use ofTRI and TFI from Timer 1. Thus THO
Timer I in Mode 3 simply holds its count. The effect is now controls the Timer I interrupt.
the same as setting TRI = O.
Mode 3 is provided for applications requiring an extra
Timer 0 in Mode 3 establishes TLO and THO as two 8-bit timer or counter. When Timer 0 is in Mode 3,
separate counters. The logic for Mode 3 on Timer 0 is Timer I can be turned on and off by switching it out of
shown in Figure II. TLO uses the Timer 0 control bits: and into its own Mode 3, or can still be used by the
elf, GATE, TRO, INTO, and TFO. THO is locked into serial port as a baud rate generator, or in any applica-
tion not requiring an interrupt.
8-14
8XC51FX HARDWARE DESCRIPTION
ciT =0
INTERRUPT
_ _ _ _ _ _...Jl clf = 1
TxPIN -
TRx - - - - - - - i
GATE
INTxPIN
x = Oorl
270653-7
Figure 10. Timer/Counter 1 Mode 2: 8-Blt Auto-Reload
OBC ~G-- 1;1210SC
1112 IOSC - - - - - - ,
~-- INTERRUPT
TO P I N - - - - - - - '
CONTROL OVERFLOW
1112 'osc-----------.. I-o-f I ·1 (::~) H~·~TF-'-..I~ INTERRUPT
________ ~~CONTROL OVERFLOW
TRI -
270653-8
Figure 11. Timer/Counter 0 Mode 3: Two 8-Bit Counters
5.2 Timer2 Table 7. Timer 2 Operating Modes
Timer 2 is a 16-bit Timer/Counter which can operate RCLK + TCLK CP/RL2 n'OE TR2 Mode
either as a timer or as an event counter. This is selected 0 0 0 1 16-Bit
by bit C/T2 in the Special Function Register T2CON Auto-Reload
(Table 8)~ It has three operating modes: capture, auto- 0 1 0 1 16-Bit
reload (up or down counting), and baud rate generator. Capture
The modes are selected by bits in nCON as shown in
1 X X 1 Baud_Rate
Table 7.
Generator
X 0 1 1 Clock-Out
on P1.0·
X X X 0 Timer Off
'Present only on the 87C51FC.
8-15
8XC51FX HARDWARE DESCRIPTION
Table 8. T2CON: Timer/Counter 2 Control Register
T2CON Address = OC8H Reset Value = 0000 00008
Bit Addressable
\. TF2 EXF2 RCLK TCLK I EXEN21 TR2 C/T2IcP/RL2\
Bit 7 6 5 4 3 2 a
Symbol Function
TF2 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will
not be set when either RCLK = 1 or TCLK= 1.
EXF2 Timer 2 external flag set when either a capture or reload is caused by a negative transition .
on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled EXF2 = 1 will cause the CPU
to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 does not
cause an iriterrupt in up/down counter mode (DCEN = 1).
RCLK Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its
receive clock in serial port Modes 1 and 3. RCLK = Qcauses Timer 1 overflow to be used
for the receive clock.
TCLK Transmit clock flag. When set, causes the serial port to us.e Timer 2 overflow pulses for its
transmit clock in serial port Modes 1 and 3. TCLK = a causes Timer 1 overflows to be used
for the transmit clock.
EXEN2 Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a
negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 == a
causes Timer 2 to ignore events at T2EX.
TR2 Startlstop control for Timer 2. A logic 1 starts the timer.
C/T2 Timer or counter select. (Timer 2)
O. = Internal timer (OSC/12 or OSC/2 in baud rate generator mode).
1 = External event counter (falling edge triggered).
CP/RL2 Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if
EXEN2 = 1. When cleared, auto-reloads will occur either with Timer 2 overflows or
negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this
bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
CAPTURE MODE 16-bit timer or counter which upon overflow sets bit
TF2 in TICON. This bit can then be used to generate
In the capture mode there are two options selected by an interrupt. If EXEN2 = I, Timer 2 still does the
bit EXEN2 in TICON. If EXEN2 = 0, Timer 2 is a above, but with the added feature that a I-to-O tran-
TR2
nMER 2
INTERRUPT
TRANSITION
OETECTION
T2EX PIN
EXEN2
270653-9
Figure 12. Timer 21n Capture Mode
8-16
8XC51FX HARDWARE DESCRIPTION
sition at external input T2EX causes the current value default to count up. When DCEN is set, Timer 2 can
in the Timer 2 registers, TH2 and· TL2, to be captured count up or down depending on the value of the T2EX
into registers RCAP2H and RCAP2L, respectively. In pin.
addition, the transition at T2EX causes bit EXF2 in
T2CON to be set. The EXF2 bit, like TF2, can generate Figure 13 shows Timer 2 automatically counting up
an interrupt. The capture mode is illustrated in Figure when DCEN = o. In this mode there are two options
12. selected by bit EXEN2 in T2CON. If EXEN2 = 0,
Timer 2 counts up to OFFFFH and then sets the TF2
bit upon overflow. The overflow also causes the timer
AUTO-RELOAD MODE registers to be reloaded with the 16-bit value in
(UP OR DOWN COUNTER) RCAP2H and RCAP2L. The values in RCAP2H and
RCAP2L are preset by software. If EXEN2 = I, a 16-
Timer 2 can be programmed to count up or down when
bit reload can be triggered either by an overflow or by a
configured in its 16-bit auto-reload mode. This feature
\-to-O transition at external input T2EX. This tran-
is invoked by a bit named DCEN (Down Counter En-
sition also sets the EXF2 bit. Either the TF2 or EXF2
able) located in the SFR T2MOD (see Table 9). Upon
bit can generate the Timer 2 interrupt if it is enabled.
reset the DCEN bit is set to 0 so that Timer 2 will
Table 9. T2MOD: Timer 2 Mode Control Register
T2MOD Address = OC9H Reset Value = XXXX XXXOB
Not Bit Addressable
T20E DCEN
Bit .7 6 5 4 3 2 o
Symbol Function
Not implemented, reserved for future use.'
T20E Timer 2 Output Enable bit. Only in the 8.7C51 FC.
DCEN Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down
counter .
• User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke
new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value
read from a reserved bit is indeterminate.
_ . .,. cln = 1
T2 PIN D-----'
TRANSITION
DETECTION
TIMER 2
INTERRUPT
T2EX PIN
EXEN2
270653-10
Figure 13. Timer 2 Auto Reload Mode (DCEN = 0)
8-1.7
inter 8XC51FX HARDWARE DESCRIPTION
Setting the DCEN bit enables Timer 2 to count up or The Clock-out frequency depends on the oscillator fre-
down as shown in Figure 14. In this mode the T2EX quency and the reload value of Timer 2 capture regis-
pin controls the direction of cOllnt. A logic I at T2EX ters (RCAP2H, RCAP2L) as shown in this equation:
makes Timer 2 count up. The timer will overflow at
OFFFFH and set the TF2 bit which can then generate Clock-out Frequency =
an interrupt if it is enabled. This overflow also causes a
the 16-bit value in RCAP2H and RCAP2L to be re- Oscillator Frequency
loaded into the timer registers, TH2 and TL2, respec- 4 x (65536 - RCAP2H, RCAP2L)
tively.
In the Clock-Out mode Timer 2 roll-overs will not gen-
A logic 0 at T2EX makes Timer 2 count down. Now erate an interrupt. This is similar to when it is used as a
the timer underflows when TH2 and TL2 equal the baud-rate generator: It is possible to use Timer 2 as a
values stored in RCAP2H and RCAP2L. The under- baud-rate generator and a clock generator simulta-
flow sets the TF2 bit and causes OFFFFH to be reload- neously. Note, however, that the baud-rate and the
ed into the timer registers. Clock-out frequency will be the same.
The EXF2 bit toggles whenever Timer 2 overflows or
underflows. This bit can be used as a 17th bit of resolu- 6.0 Pi=lOGRAMMABLE COUNTER
tion if desired. In this operating mode, EXF2 does not ARRAY
generate an interrupt.
, The Programmable Counter Array (PCA) consists of a
16-bit timer/counter and five 16-bit compare/capture
BAUD RATE GENERATOR MODE modules as shown in Figure 15a. The PCA timerlcoun-
ter serves as a common time base for the five modules
The baud rate generator mode is selected by setting the
and is the only timer which can service the PCA. Its
RCLK and/or TCLK bits in T2CON. Timer 2 in this
clock input can be programmed to count anyone of the
mode will be described in conjunction with the serial
following signals:
port.
• oscillat~r frequency -i- 12
• oscillator frequency -i- 4
PROGRAMMABLE CLOCK OUT
• Timer 0 overflow
The 87C51FC has a new feature. A 50% duty cycle • external input on ECI (P1.2).
clock can be programmed to come out on Pl.O. This
pin, besides. being a regular I/O pin, has two alternate Each compare/capture module can be programmed in
functions. It can be programmed (1) to input the exter- anyone of the following modes:
nal clock for Timer/Counter 2 or (2) to output a 50%
duty cycle clock ranging from 61 Hz to 4 MHz at a 16 • rising and/or falling edge capture
MHz operating frequency. • software timer
• high speed output
To configure the Timer/Counter 2 as a clock generator,
bit C/T2 (in T2CON) must be cleared and bit T20E in • pulse width modulator.
T2MOD must be set. Bit TR2 (T2CON.2) also must be
set to start the timer (see Table 6 for operating modes). Module 4 can also be programmed as a watchdog tim-
er.
When the compare/capture modules are programmed
in the capture mode, software timer, or high speed out-
put mode, an interrupt can be generated when the mod-
ule executes its function. All five modules plus the PCA
timer overflow share one interrupt vector (more about
this in the PCA Interrupt section).
8-18
8XC51FX HARDWARE DESCRIPTION
(DOWN COUNTING RELOAD VALUE)
TOGGLE
_ t cln = 1
T2 PIND--'
COUNT
DIRECTION
1 =
UP
0= DOWN
(UP COUNTING RELOAD VALUE)
T2EX PIN
270653-11
Figure 14. Timer 2 Auto Reload Mode (DCEN = 1)
--, Transition T20E (T2CON.1)
LDetector
P1.1~1-_ _ _"""i?~
(T2EX) ~
Timer2
~ Interrupt
EXEN2
270653-35
Figure 15. Timer 2 in Clock-Out Mode
8-19
infef 8XC51FX HARDWARE DESCRIPTION
- 16 BITS EACH -
.1 MODULE 0 ~:: P1.3/CEXO
·1
.1 MODULE 1 t ~:: P l.4/CEX 1
1 1
- - 16 BITS -----
I PCA TIMER/COUNTER MODULE 2 t
1
. : : Pl.S/CEX2
I.
MODULE 3 ::;:: Pl.6/CEX3
I
L-_MODULE
_ _ 4_-I...... --t.a:;::
' I - Pl.7/CEX4
270653-12
Figure 15a. Programmable Counter Array
The PCA timer/counter and compare/capture modules gram of this timer. The clock input can be selected
share Port 1 pins for external I/O. These pins are listed from the following four modes:
below. If the port pin is not used for the PCA, it can • Oscillator frequency 7 12
still be used for standard I/O. The PCA timer increments once per machine cycle.
With a 16 MHz crystal, the timer increments every
PCA Component External I/O Pin 750 nanoseconds.
16-bit Counter P1.2/ ECI
• Oscillator frequency 7 4
16-bit Module 0 P1.3 / CEXO
The PCA timer increments three times per machine
16-bit Module 1 P1.4 / CEX1 cycle. With a 16 MHz crystal, the timer increments
16-bit Module 2 P1.5 / CEX2 every 250 nanoseconds.
16-bit Module 3 P1.6 / CEX3
• Timer 0 overflows
16-bit Module 4 P1.7 / CEX4 The PCA timer increments whenever Timer 0 over-
flows. This mode allows a programmable input fre-
quency to the PCA.
6.1 PCA 16-Bit Timer/Counter
• External input
The PCA has a free-running 16-bit timer/counter con- The peA timer increments when a I-to-O transi-
sisting of registers CH and CL (the high and low bytes tion is detected on the ECI pin (P1.2). The max-
of the count value). These two registers can be read or imum input· frequency in this mode is oscillator
written to at any time. Figure 16 shows a block dia- frequency 7 8.
FOSC/12
FOSC/4
TIMER 0 1---1-<"'-;- o-If-- INTERRUPT
OVERFLOW
EXTERNAL
INPUT
(ECI)
CIDL
PROCESSOR IN
IDLE MODE
270653-13
Figure 16. PCA Timer/Counter
8-20
8XC51FX HARDWARE DESCRIPTION
The mode register CMOD contains the Count Pulse The CCON register, shown in Table II, contains two
Select bits (CPS I and CPSO) to specify the clock input. more bits which are associated with the PCA timer/
CMOD is shown in Table 10. This register also con- counter. The CF bit gets set by hardware when the
tains the ECF bit which enables the PCA counter over- counter overflows, and the CR bit is set or cleared to
flow to generate the PCA interrupt. In addition, the turn the counter on or off. The other five bits in this
user has the option of turning off the PCA timer during register are the event flags for the compare/capture
Idle Mode by setting the Counter Idle bit (CIDL). The modules and will be discussed in the next section.
Watchdog Timer Enable bit (WDTE) will be discussed
in a later section.
Table 10. CMOD: PCA Counter Mode Register.
CMOD Address = OD9H Reset Value = OOXX XOOOB
Not Bit Addressable
CIDL I WDTE I CPS1 CPSO ECF
Bit 7 6 5 4 3 2 o
Symbol Function
CIDL Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during
idle Mode. CIDL = 1 programs it to be gated off during idle.
WDTE Watchdog Timer Enable: WDTE =·0 disables Watchdog Timer function on PCA Module 4.
WDTE = 1 enables it.
Not implemented, reserved for future use.'
CPS1 PCA Count Pulse Select bit 1.
CPSO PCA Count Pulse Select bit O.
CPS1 CPSO Selected PCA Input"
o 0 Internal clock, Fosc 7 12
o 1 Internal clock, Fosc 74
o Timer 0 overflow
External clock at ECIIP1.2 pin (max. rate = Fosc 78)
ECF PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an
interrupt. ECF = 0 disables that function of CF.
NOTE:
'User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke
new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value
read from a reserved bit is indeterminate.
"Fosc = oscillator frequency
inter 8XC51FX HARDWARE DESCRIPTION
Table 11. CCON: PCA Counter Control Register
CCON Address = 008H Reset Value = OOXO OOOOB
Bit Addressable
CF CR CCF4 CCF3 CCF2 CCF1 CCFO
Bit 7 6 5 4 3 2 o
Symbol Function
CF PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an
interrupt if bit ECF in CMOO is set. CF may be set by either hardware or software but can
only be cleared by software. .
CR PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared
by software to turn the PCA counter off.
Not implemented, reserved for future use'.
CCF4 PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software.
CCF3 PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software.
CCF2 PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software.
CCF1 PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software. .
CCFO PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software.
'NOTE:
User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke
new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value
read from a reserved bit is indeterminate.
6.2 Capture/Compare Modules when a module's event flag is set. The event flags
(CCFn) are located in· the CCON register and get set
Each of the five compare/capture modules has six pos- when a capture event, software timer, or high speed
sible functions it can perform: output event occurs for a given module.
16-bit Capture, positive-edge triggered
Table 13 shows the combinations· of bits in the
. - 16-bit Capture, negative-edge triggered CCAPMn register that are valid and have a defined
- 16-bit Capture, both positive and negative-edge function. Invalid combinations will produce undefined
triggered results.
16-bit Software Timer
Each module also has a pair of 8-bit compare/capture
16-bit High Speed Output registers (CCAPnH and CCAPnL) associated with it.
8-bit Pulse Width Modulator. These registers store the time when a capture event oc-
curred or when a compare event should occur. For the
In addition, module 4 can be used as a Watchdog Tim- PWM mode, the high byte regiser CCAPnH controls
er. The modules can be programmed in any combina- the duty cycle of the waveform.
tion of the different modes.
The next five sections describe each of the compare/
Each module has a mode register called CCAPMn capture modes in detail.
(n = 0, I, 2, 3, or 4) to select which function it will
perform. The CCAPMn register is shown in Table 12.
Note the ECCFn bit which enables the PCA interrupt
8-22
8XC51FX HARDWARE DESCRIPTION
Table 12. CCAPMn: PCA Modules Compare/Capture Registers
CCAPMn Address CCAPMO ODAH Reset Value = XOOO OOOOB
(n = 0-4) CCAPM1 ODBH
CCAPM2 ODCH
CCAPM3 ODDH
CCAPM4 ODEH
Not Bit Addressable
IECOMn I CAPPn ICAPNn I MATn TOGn PWMn I ECCFn I
Bit 7 6 5 4 3 2 o
Symbol Function
Not implemented, reserved for future use·.
ECOMn Enable Comparator. ECOMn = 1 enables the comparator function.
CAPPn Capture Positive, CAPPn = 1 enables positive edge capture.
CAPNn Capture Negative, CAPNn = 1 enables negative edge capture.
MATn Matph. When MATn = 1, a match of the PCA counter with this module's compare/capture·
register causes the CCFn bit in CCON to be set, flagging an interrupt.
TOGn Toggle. When TOGn = 1, a match of the PCA counter with this module's compare/capture
register causes the CEXn pin to toggle.
PWMn Pulse Width Modulation "",ode. PWMn = 1 enables the CEXn pin to be used as a pulse width
modulated output.
ECCFn Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register to generate
an interrupt.
NOTE:
• User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke
new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value
read from a reserved bit is indeterminate.
Table 13. PCA Module Modes (CCAPMn Register)
- ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn Module Function
X 0 0 0 0 0 0 0 No operation
X X 1 0 0 0 0 X 16-bit capture by a postive-edge trigger on CEXn
X X 0 1 0 0 O. X 16-bit capture by a negative-edge trigger on CEXn
X X 1 1 0 0 0 X 16-bit capture by a transition on CEXn
X 1 0 0 1 0 0 X 16-bit Software Timer
X 1 0 0 1 1 0 X 16-bit High Speed Output
X 1 0 0 0 0 1 0 8-bitPWM
X 1 0 0 1 x 0 x Watchdog Timer
x= Don't Care
8-23
intJ 8XC51FX HARDWARE DESCRIPTION
6.3 16·Bit Capture Mode In the interrupt service routine, the 16-bit capture value
must be saved in RAM before the next capture event
Both positive and negative transitions can trigger a cap- occurs. A subsequent capture on the same CEXn pin
ture with the PCA. This gives the PCA the flexibility to will write over the first capture value in CCAPnH and
measure periods, pulse widths, duty cycles, and phase CCAPnL.
differences on up to five separate inputs. Setting the
CAPPnand/or CAPNn in the CCAPMn mode register
select the input trigger-positive and/or negative tran- 6.4 16·Bit Software Timer.Mode
sition~for module n. Refer to Figure 17.
In the compare mode, the 16-bit value of the PCA tim-
The external input pins CEXO through CEX4 are sam- er is compared with a 16-bit value pre-loaded in the
pled for a transition. When a valid transition is detected module's compare registers (CCAPnH, CCAPrtL). The
(positive and/or negative edge), hardware loads the comparison occurs three times per machine cycle in
16-bit value of the PCA timer (CH, CL) into the mod- order to recognize the fastest possible clock input (i.e.
ule's capture registers (CCAPnH, CCAPnL). The re- 'I. x oscillator frequency). Setting the ECOMn bit in
sulting value in the capture registers reflects the PCA the .mode register CCAPMn enables the comparator
timer. value at the time a transition was deteCted on the function as shown in Figure 18.
CEXn pin.
. For the Software Timer mode, the MATn bit also needs
Upon a capture, the module's event flag (CCFn) in to be set. When a match occurs between the PCA timer
CCON is set, and an interrupt is flagged if the ECCFn and the compare registers, a match signal is generated
bit in the mOde register CCAPMn is set. The PCA in- and the module's event flag (CCFrt) is set. An interrupt
terrupt will then be generated if it is enabled. Since the is then flagged if the ECCFn bit is set. The PCA inter-
hardware does not clear an event flag when the inter- rupt is generated only if it has been properly enabled.
rupt is vectored to, the flag must be cleared in software.• Software must clear the event flag before the next inter-
rupt will be flagged.
-11---'-' INTERRUPT
PCA
TIMER/COUNTER
"--.,...--.,-....1
CEXn
PIN
n = 0,1,2,3 or 4
x = Don't Care
CCAPMn MODE REGISTER
270653-14
. Figure 17. PCA 16-Bit Capture Mode
8-24
intJ 8XC51FX HARDWARE DESCRIPTION
During the interrupt routine, a new 16-bit compare val- regular hold-off signals to the Watchdog. These circuits
ue can be written to the compare registers (CCAPnH are used in applications that are subject to electrical
and CCAPnL). Notice, however, that a write to noise, power glitches, electrostatic discharges, etc., or
CCAPnL clears the ECOMn bit which temporarily dis- where high reliability is required.
ables the comparator function while these registers are
being updated so an invalid match does not occur. A The Watchdog Timer function is only .available on
write to CCAPnH sets the ECOMn bit and re-enables PCA module 4. In this mode, every time the count in
the comparator. For this reason, user software should the PCA timer matches the value stored in module 4's
write toCCAPnL first, then CCAPnH. compare registers, an internal reset is generated. (See
Figure 19.) The bit that selects this mode is WDTE in
the CMOD register. Module 4 must be set up in either
6.5 High Speed Output Mode compare mode as a Software Timer or High Speed Out-
put.
The High Speed Output (HSO) mode toggles a CEXn
pin when a match occurs between the PCA timer and a When the PCA Watchdog Timer times out, it resets the
pre-loaded value in a module's compare registers. For chip just like a hardware reset, except that it does not
this mode, the TOGn bit needs to be set in addition to drive the reset pin high.
the ECOMn and MATn bits as seen in Figure 18. By
setting or clearing the pin in software, the user can To hold off the reset, the user has three options:
select whether the CEXn pin will change from a logical (1) periodically change the compare value so it will
o to a logical 1 or vice versa. The user also has the never match the PCA timer,
option of flagging an interrupt when a match event oc-
curs by setting the ECCFn bit. (2) periodically change the PCA timer value so it will
never match the compare value,
The HSO mode is more accurate than toggling port (3) disable the Watchdog by clearing the WDTE bit
pins in software because the toggle occurs before before a match occurs and then later re-enable it.
branching to an interrupt. That is, interrupt latency
will not effect the accuracy of the output. If the user The first two options are more reliable because the
does not change the compare registers in an interrupt Watchdog Timer is never disabled as in option # 3. The
routine, the next toggle will occur when the PCA timer second option is not recommended if other PCA mod-
rolls over and matches the last compare value. ules are being used since this timer is the time base for
all five modules. Thus, in most applications the first
solution is the best option.
6.6 Watchdog Timer Mode
If a Watchdog Timer is not needed, module 4 can still
A Watchdog Timer is a circuit that automatically in- be used in other modes.
vokes a reset unless the system being watched sends
PCA CEXn PIN
TIMER/COUNTER
ENABLE
CCAPlroIn MODE REGISTER
RESET
WRITE TO
CCAPnL
/
WRITE TO
n = 0, 1.2,3 or 4
CCAPnH x = Don't Care
"1"
270653-15
Figure 18. PCA 16-Bit Comparator Mode: Software Timer and High Speed Output
8-25
8XC51FX HARDWARE DESCRIPTION
6.7 Pulse Width Modulator Mode The PCA generates 8-bit PWMs by comparing the low
byte of the PCA timer (CL) with the low byte of the
Any or all of the five PCA modules can be pro- module's compare registers (CCAPnL). Refer to Figure
grammed to be a Pulse Width Modulator. The PWM 20. When CL < CCAPnL the output is low. When CL
output can be used to convert digital data to an analog :2 CCAPnL the output is high. The value in CCAPnL
signal by simple external circuitry. The frequency of the controls the duty cycle of the waveform. To change the
PWM depends on the clock sources for the PCA timer. value in CCAPnL without output glitches, the user
With a 16 MHz crystal the maximum frequency of the must write to the high byte register (CCAPnH). This
PWM waveform is 15.6 KHz. value is then shifted by hardware into CCAPnL when
CL rolls over from OFFH to DOH which corresponds to
the next period of the output.
PCA
TIMER/COUNTER '-_~.....J
4--. RESET
ENABLE
CCAPM4 ",ODE REGISTER
RESET
WRITE TO
CCAP4L
x = Don't Care
270653-16
Figure 19. ~alchdog Timer Mode
CL MADE
FF TO 00 ---..!i~
TRANSITION
"0"
CL < CCAPnL
CL 2: CCAPnL CEXn PIN
"1"
n='0,1,2,30r4
x = Don't Care
CCAPMn "'ODE REGISTER
270653-17
Figure 20. peA 8-BII PWM Mode
8-26
inter 8XC51FX HARDWARE DESCRIPTION
DUTY CYCLE CCAPnH OUTPUT WAVEFORM
100% 00
90% 25
50% 128
10% 230
0.4% 255
270653-18
Figure 21. CCAPnH Varies Duty Cycle
CCAPnH can contain any integer from 0 to 255 to vary The serial port can operate in 4 modes:
the duty cycle from a 100% to 0;4% (see Figure 21).
Mode 0: Serial data enters and exits through RXD.
TXD outputs the shift clock. 8 bits are transmitted/re-
7.0 SERIAL INTERFACE ceived: S. data bits (LSB first). The baud rate is fixed at
1112 the oscillator frequency.
The serial port is full duplex, meaning it can transmit
and receive simultaneously. It is also receive-buffered, Mode 1: 10 bits are transmitted (through TXD) or re-
meaning it can commence reception of a second byte ceived (through RXD): a start bit (0), S data bits (LSB
before a previously received byte has been read from first), and a stop bit (1). On receive, the stop bit goes
the receive register. (However, if the first byte still into RBS in Special Function Register SCON. The
hasn't been read by the time reception of the second baud rate is variable.
byte is complete, one of the bytes will be lost). The
serial port receive and transmit registers are both ac- Mode 2: II bits are transmitted (through TXD) or re-
cessed through Special Function Register SBUF. Actu- ceived (through RXD): a start bit (0), S data bits (LSB
ally, SBUF is two separate registers, a transmit buffer first), a programmable 9th data bit, and a stop bit (1).
and a receive buffer. Writing to SBUF loads the trans- Refer to Fiugre 22. On Transmit, the 9th data bit (TBS
mit register, and reading SBUF accesses a physically in SCON) can be assigned the value of 0 or 1. Or, for
separate receive register. example, the parity bit (P in the PSW) could be moved
into TBS. On receive, the 9th data bit goes into RBS in
The serial port control and status register is the Special SCON, while the stop bit is ignored. (The validity of
Function Register SCON, shown in Table 14. This reg- the stop bit can be checked with Framing Error Detec-
ister contains the mode selection bits (SMO and SM1); tion.) The baud rate is programmable to either '132 or
the SM2 bit for the multiprocessor modes (see Multi- 1/64 the oscillator frequency.
processor Communications section); the Receive En-
able bit (REN); the 9th data bit for transmit and receive
(TBS and RBS); and the serial port interrupt bits (TI
and RI).
STOP BIT
NINTH OATA BIT (Mod,. 2 and 3 only)
270653-19
Figure 22. Data Frame: Modes 1,2 and 3
8-27
infef 8XC51FX HARDWARE DESCRIPTION
Mode 3: 11 bits are transmitted (through TXD) or re· byte has its 9th bit set to O. All the slave processors
ceived (through RXD): a start hit (0), 8 data bits (LSB should have their SM2 bits set to 1 so they will only be
first), a programmable 9th data hit and a stop bit (1). In interrupted by an address byte. In fact, the C5lFX has
fact, Modc 3 is the same as Mode 2 in all respects an Automatic Address Recognition feature which al·
except the haud rate. The baud rate in Mode 3 is vari· lows only the addressed slave to be interrupted. That is,
able. the address comparison occurs in hardware, not soft·
ware. (On the 8051 serial port, an address byte inter·
In all four modes, transmission is initiated by any in· rupts all slaves for an address comparison.)
struction that uses SBUF as a destination register. Re·
ception is initiated in Mode 0 by the condition RI = 0 The addressed slave's software then clears its SM2 bit
and REN = 1. Reception is initiated in the other and prepares to receive the data bytes that will be com·
modes by the incoming start bit if REN = 1. For more ing. The other slaves are unaffected by these data bytes.
detailed information on each serial port mode, refer to They are still waiting to be addressed since their SM2
the "Hardware Description of the 8051, 8052, and bits are all set. .
SOC51."
7.3 . Automatic Address Recognition
7.1 Framing Error Detection
Automatic Address Recognition reduces the CPU time
Framing Error Detection allows the serial port to check required to service the serial port. Since the CPU is
for valid stop bits in modes 1, 2, or 3. A missing stop bit only interrupted. when it receives its own address, the
can be caused, for example, by noise on the serial lines, software overhead to compare addresses is eliminated.
or transmission by two CPUs simultaneously. With this feature enabled in one of the 9·bit modes, the
Receive Interrupt (RI) flag will only get set when the
If a stop bit is missing, a Framing Error bit 'FE is set. . received byte corresponds to either a Given or Broad·
The FE bit can be checked in software after each recep· cast address.
tion to detect communication errors. Once set, the FE
bit must be'cleared in software. A valid stop bit will not The feature works the same way in the 8·bit mode
clear FE. (Mode 1) as in the 9·bit modes, except that the stop bit
takes the place of the. 9th data bit. If SM2 is set, the RI
The FE bit is located in SCON and shares the same bit flag is set only ifthe received byte matches the Given or
address as SMO. Control bit SMODO in the PCON reg· Broadcast Address· and is terminated by a valid stop
ister (location PCON.6) determines whether the SMO bit. Setting the SM2 bit has .no effect in Mode O.
or FE bit is accessed. If SMODO = 0, then accesses to
SCON.7 are to SMO. IfSMODO = 1, then accesses to The master can selectively communicate with groups of
SCON.7 are to FE. slaves by using the Given Address. Addressing· all
slaves at once is possible with the Broadcast Address.
These addresses are defined for each slave by two Spe·
7.2 Multiprocessor Communications cial Function Registers: SADDR and SADEN.
Modes 2 and 3 provide a 9·bit mode to facilitate multi· A slave's individual address is specified in SADDR.
processor comunication. The 9th bit allows the control· SADEN is a mask byte that defines don't·cares to fonn
ler to distinguish between address and data bytes. The the Given Address. These don't·cares allow' flexibility
. 9th bit is set to 1 for address bytes and set to 0 for data in the user·dermed protocol to address one or more
bytes. When receiving, the 9th bit goes into RB8 in slaves at a time. The following is an example of how the
SCON. When transmitting, TB8 is set or cleared in user could define Given Addresses to selectively ad·
software... dress different slaves.
The serial port can be programmed such that when the Slave 1:
stop bit is received the serial port interrupt will be acti· SADDR 1111 0001
vated only if the received byte is an address byte (RB8 SADEN 1111 1010
= 1). This feature is enabled by setting the SM2 bit in
SCON, A way to use this feature in multiprocessor sys· GIVEN 1111 OXOX
terns is as follows.
Slave 2:
When the master processor wants to transmit a block of SADDR 1111 0011
data to one of several slaves, it first sends out an ad· SADEN 1111 1001
dress byte which identifies the target slave. Remember,
an address byte has its 9th bit set to 1, whereas a data GIVEN 1111 OXX1
8·28
iritJ 8XC51FX HARDWARE DESCRIPTION
Table 14. SCON: Serial Port Control Register
. SCON Address = 98H Reset Value = 0000 OOOOB
Bit Addressable
ISMO/FEI SM1 SM2 REN TB8 RB8 TI RI
Bit: 7 6 5 4 3 2 o
(SMODO =O/1)'
Symbol Function
FE Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE
bit is not cleared by valid frames but should be cleared by software. The SMODO' bit must be
set to enable access to the FE bit. .
SMO Serial Port Mode Bit 0, (SMODO must = 0 to access bit SMO)
SM1 Serial Port Mode Bit 1
SMO SM1 Mode Description Baud Rate"
o 0 0 shift register Fose/12
o 1 1 S-bit UART variable
o 2 9-bit UART Fose/64 or Fose/32
1 3 9-bit UART variable
SM2 Enlibles the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then RI will
not be set unless the received 9th data bit (RBS) is 1, indicating an address, and the received
byte is a Given or Broadcast Address. In Mode 1, if SM2 = 1 then RI will not be activated
unless a valid stop bit was received, and the received byte is a Given or Broadcast Address.
In Mode 0, SM2 should be o.
REN Enables serial reception. Set by software to enable reception, Clear by software to disable
reception.
TBS The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as
desired.
R.BS In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RBS is the stop
bit that was received. In Mode 0, RBS is not used. .
TI Transmit interrupt flag. Set by hardware at the end of the Sth bit time in Mode 0, or at the
beginning of the stop bit in the other modes, in any serial transmission: Must be cleared by
software.
RI Receive interrupt flag. Set by hardware at the end of the Sth bit time in Mode 0, .or halfway
through the stop bit time in the other modes, in any serial reception (except see SM2). Must
be cleared by software.
NOTE:
'SMODO is located at peON6.
"Fosc = oscillator frequency
The SADEN byte are selected such that each slave can Notice, however, that bit 3 is a don't-care for both
be addreSsed separately. Notice that bit I (LSB) is a slaves. This allows two different addresses to select
don't-care for Slave 1's Given Address, but bit 1 = 1 both slaves (1111 0001 or 1111 0101). If a third slave
for Slave 2. Thus, to selectively communicate with just was added that required its bit 3 = 0, then the latter
Slave 1 the master must send an address with bit 1 = 0 address could be used to communicate with Slave 1 and
(e.g. 1111 0000). 2 but not Slave 3.
Similarly, bit 2 = 0 for Slave 1, but is a don't-care for The master can also communicate with all slaves at
Slave 2. Now to communicate with just Slave 2 an ad- once with the Broadcast Address. It is formed from the
dress with bit 2 = 1 must be used (e.g. 1111 0111). logical OR of the SADDR and SADEN registers with
zeros defined as don't-cares. The don't-cares also allow
Finally, for a master to communicate with both slaves
at once the address must have bit 1 = 1 and bit 2 = O.
S-29
inter 8XC51FX HARDWARE DESCRIPTION
flexibility in defining the Broadcast Address, but in Modes 1 and 3 = SMODl Timer 1 Overflow Rate
most applications a Broadcast Address will be OFFH. Baud Rate 2 x 32
SADDR and SADEN are located at address A9H and The Timer 1 interrupt should be disabled in thisappli-
B9H, respectively. On reset, the SADDR and SADEN cation. The Timer itself can be configured for either
registers arc initialized to DOH which defines the Given "timer" or "counter" operation, and in any of its 3
and Broadcast Addresses as XXXX XXXX (all don't- running modes. In most applications, it is configured
cares). This assures the C5lFX serial port to be back- for "timer" operation in the auto-reload mode (high
wards compatibility with other MCS®-51 products nibble ofTMOD = 00 lOB). In this case, the baud rate
which do not implement Automatic Addressing. is given by the formula:
Modes 1 and 3 2SMODl x Oscillator Frequency
7.4 Baud Rates Baud Rate 32 x 12 x [256 - (TH1)1
The baud rate in Mode 0 is fixed: One can achieve very low baud rates with Timer I by
leaving the Timer I interrupt enabled, and configuring
Oscillator Frequency the Timer to run as a 16-bit timer (high nibble of
Mode 0 Baud Rate = 12
TMOD = DOOIB), and using the Timer I interrupt to
do a 16-bit software reload.
The baud rate in Mode 2 depends on the value of bit
SMODI in Special Function Register PCON. If Table 15 lists various commonly used baud rates and
SMODI = 0 (which is the value on reset), the baud how they can be obtained from Timer 1.
rate is 1/64 the oscillator frequency. IfSMODI = I, the
baud rate is '/32 the oscillator frequency.
7.6 Using Timer 2 to Generate Baud
Mode 2 Baud Rate = 2SMODl x Oscillator Frequency Rates
64 .
Timer 2 is selected as the baud rate generator by setting
The baud rates in Modes I and 3 are determined by the TCLK and/or RCLK in T2CON (Table 7). Note that
Timer I overflow rate, or by Timer 2 overflow rate, or the baud rates for transmit and receive can be simulta-
by both (one for transmit and the other for receive). neously different. Setting RCLK and/or TCLK puts
Timer 2 into its baud rate generator mode, as shown in
Figure 23.
7.5 Using Timer 1 to Generate Baud
Rates The baud rate generator mode is similar to the auto-re-
load mode, in that a rollover in TH2 causes the Timer 2
When Timer I is used as the baud rate generator, the registers to be reloaded with the 16-bit value in registers
baud rates in Modes I· and 3 are determined by the RCAP2H and RCAP2L, which are preset by software.
Timer I overflow rate and the value of SMODI as fol-
lows:
Table 15. Timer 1 Generated Commonly Used Baud Rates
Timer 1
Baud Rate fose SMOD Reload
cif Mode
Value
Mode 0 Max: 1 MHz 12 MHz X X X X
Mode 2 Max: 375K 12 MHz 1 X X X
Modes 1, 3: 62.5K 12 MHz 1 0 2 FFH
19.2K 11.059 MHz 1 0 2 FDH
9.6K 11.059 MHz 0 0 2 FDH
4.8K 11.059 MHz 0 0 2 FAH
2.4K 11.059 MHz 0 0 2 F4H
1.2K 11.059 MHz 0 0 2 E8H
137.5 11.986 MHz 0 0 2 1DH
110 6MHz 0 0 2 72H
110 12MHz 0 0 1 FEEBH
8-30
inter 8XC51FX HARDWARE DESCRIPTION
The baud rates in Modes I and 3 are determined by as a baud rate generator, T2EX can be used as an extra
Timer 2's overflow rate as follows: external interrupt, if desired.
M d d B Timer 2 Overflow Rate It should be noted that when Timer 2 is running (TR2
o es1 an 3 audRates = 16
= 1) in "timer" function in the baud rate generator
mode, one should not try to read or write TH2 or TL2.
The Timer can be configured for either "timer" or Under these conditions the Timer is being incremented
"counter" operation. In most a~ications, it is config- every state time, and the results of a read or write may
ured for "timer" operation (C/T2 = 0). The "Timer" not be accurate. The RCAP2 registers may be read, but
operation is different for Timer 2 when it's being used shouldn't be written to, because a write might overlap a
as a baud rate generator. Normally, as a timer, it incre- reload and cause write and/or reload errors. The timer
ments every machine cycle (1/12 the oscillator frequen- should be turned off (clear TR2) before accessing the
cy). As a baud rate generator, however, it increments Timer 2 or RCAP2 registers.
every state time ('/2 the oscillator frequency). The baud
rate formula is given below: Table 16 lists commonly used baud rates and how they
can be obtained from Timer 2.
Modes 1 and 3 Oscillator Frequency
Baud Rate 32 x [65536 - (RCAP2H, RCAP2L)] Table 16. Timer 2 Generated
Commonly Used Baud Rates
where (RCAP2H, RCAP2L) is the content of
RCAP2H and RCAP2L taken as a 16-bit unsigned Baud Osc Timer 2
integer. Rate Freq RCAP2H RCAP2L
Timer 2 as a baud rate generator is shown in Figure 23. 375K 12MHz FF FF
This figure is valid only if RCLK and/or TCLK = I in 9.6K 12MHz FF D9
T2CON. Note that a rollover in TH2 does not set TF2, 4.8K 12MHz FF B2
and will not generate an interrupt. Therefore, the Tinier 2.4K 12MHz FF 64
2 interrupt does not have to be disabled when Timer 2 1.2K 12MHz FE C8
is in the baud rate generator mode. Note too, that if 300 12 MHz FB 1E
EXEN2 is set, a I-to-O transition in T2EX will set 110 12 MHz F2 AF
EXF2 but will not cause a reload from (RCAP2H,
300 6MHz FD 8F
RCAP2L) to (TH2, TL2). Thus when Timer 2 is in use
·110 6MHz F9 57
TIMER 1
OVERFLOW
RX CLOCK
TX CLOCK
"TIMER 2"
nEX PIN
INTERRUPT
EXEN2
L HOTE AYAILABlLITY Of ADOITIONAL EXTERNAL INTERRUPT
270653-20
Figure 23. Timer 2 in Baud Rate Generator Mode
8-31
8XC51FX HARDWARE DESCRIPTION
8.0 INTERRUPTS All of the bits that generate interrupts can be set or
cleared by software, with the same result as though it
The C51FX has a total of 7 interrupt vectors: two ex- had been set or cleared by hardware. That is, interrupts
temaiinterrupts (INTO and INTI). three timer inter- can be generated or pending, interrupts can be cancelled
rupts (Timers O. 1. and 2), the PCA interrupt, and the in software.
serial port interrupt. These interrupts are all shown in
Figure 24. Each of these interrupts will be briefly described fol-
lowed by a discussion of the interrupt enable bits and
the interrupt priorit>: levels.
INTO---C1" ITO
rro-----------------------------------~------__.~
iim---C1" ITt
TF"1-------------..;....--..,...-------------------------+~
INTERRUPT
SOURCES
ccFn~ECCFn
5
~\-----------------r=:>~'------------------------.
TF2:----------------
r
EXF2 ,
D>-______________________
'
-+
~,
270653-21
(See exceptions when Timer 2 is used as baud rate generator or an up/down counter.)
Figure 2~. Interrupt Sources
8-32
inter 8XC51FX HARDWARE DESCRIPTION
8.1 Externallnterrupts 8.3 peA Interrupt
External Interrupts INTO and INTi can each be either· The PCA interrupt is generated by. the logical OR of
level-activated or. transition-activated, depending on CF, CCFO, CCFI, CCF2, CCF3, and CCF4 in register
bits ITO and ITi in register TCON. If ITx = 0, exter- CCON. None of these flags is cleared by hardware
nal interrupt x is triggered by a detected low at the when the service routine is vectored to. Normally the
INTx pin. If ITx = I, external interrupt x is negative service routine will have to determine which bit flagged
edge-triggered. The flags that actually generate these the interrupt and clear that bit in software. The PCA
interrupts are bits lEO and lEI in TCON. These flags interrupt is enabled by bit EC in the Interrupt Enable
are cleared by hardware when the service routine is register (see Table 16). In addition, the CF flag and
vectored to only if the interrupt was transition-activat- each of the CCFn flags must also be enabled by bits
ed. If the interrupt was level-activated, then the exter- ECF and ECCFn in registers CMOD and CCAPMn
nal requesting source is what controls the request flag, respectively, in order for that flag to be able to cause an
rather than the on-chip hardware. interrupt.
Since the external interrupt pins are sampled once each
machine cycle, an input high or low should hold for at 8.4 Serial Port Interrupt
least 12 oscillator periods to ensure sampling. If the
external interrupt is transition-activated, the external The serial port interrupt is generated by the logical OR
source has to hold the request pin high for at least one of bits RI and TI in register SCON. Neither of these
cycle, and then hold it low for at least one cycle to flags is cleared by· hardware when the service routine is
ensure that the transition is seen so that interrupt re- vectored to. The service routine will normally have to
quest flag lEx will be set. lEx will be automatically determine whether it was RI or TI that generated the
cleared by the CPU when the service routine is called. interrupt, and the bit will have to be cleared in soft-
ware.
If external interrupt INTO or INTi is level-activated,
the external source has to hold the request active until
the. requested interrupt is actually generated. Then it 8.5 Interrupt Enable
has to deactivate the request before the interrupt serv-
ice routine is completed, or else another interrupt will Each of these interrupt sources can be individually en-
be generated. abled or disabled by setting or clearing a bit in the
Interrupt Enable (IE) register. (See Table 17.) Note
that IE also contains a global disable bit, EA. If EA is
8.2 Timer Interrupts set (I), the interrupts are individually enabled or dis-
abled by their corresponding bits in IE. If EA is clear
Timer 0 and Timer I Interrupts are generated by TFO (0), all interrupts are disabled.
and TFI in register TCON, which are set by a rollover
in their respective Timer/Counter registers (except see
Timer 0 in Mode 3). When a timer interrupt is generat- 8.6 Priority Level Structure
ed, the flag that generated it is cleared by the on-chip
hardware when the service routine is vectored to. Each interrupt source can also be individually pro-
grammed to one of two priority levels, by setting or
Timer 2 Interrupt is generated by the logical OR of bits clearing a bit in the Interrupt Priority (IP) register
TF2 and EXF2 in register T2CON. Neither of these shown in Table 18. A low-priority interrupt can itself
flags is cleared by hardware when the service routine is be interrupted by a higher priority interrupt, but not by
vectored to. In fact, the service routine may have to another low-priority interrupt. A high priority inter-
determine whether it was TF2 or EXF2 that generated rupt cannot be interrupted by any other interrupt
the interrupt, and the bit will have to be cleared in source.
software.
8-33
intJ 8XC51FX HARDWARE DESCRIPTION
Table 17. IE: Interrupt Enable Register
IE Address = OA8H Reset Value = 0000 OOOOB
Bit Addressable
EA EC ET2 ES ET1 EX1 ETO EXO
Bit 7 6 5 4 3 2 o
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables it.
Symbol Function
EA Global disable bit. If EA = 0, all Interrupts are disabled. If EA = 1, each Interrupt can be
individually enabled or disabled by setting or clearing its enable bit. .
EC PCA interrupt enable bit.
ET2 Timer 2 interrupt enable bit.
ES Serial Port interrupt enable bit.
ET1 Timer 1 interrupt enable bit.
EX1 External interrupt 1 enable bit.
ETO Timer 0 interrupt enable bit.
EXO External interrupt 0 enable bit.
Table 18.IP: Interrupt Priority Registers
IP Address = OB8H Reset Value = XOOO OOOOB
Bit Addressable
PPC PT2 PS PT1 PX1 PTO PXO
Bit 7 6 5 4 3 2 o
Priority Bit = 1 assigns high priority
Priority Bit = 0 assigns low priority
Symbol Function
. Not implemented, reserved for future use. •
PPC PCA interrupt priority bit.
PT2 Timer 2 interrupt priority bit.
PS Seriai Port interrupt priority bit.
PT1 Timer 1 interrupt priority bit.
PX1 External interrupt 1 priority bit.
PTO Timer 0 interrupt priority bit.
PXO External interrupt 0 priority bit.
NOTE:
'User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke
new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value
read from a reserved bit is indeterminate.
8-34
infef 8XC51FX HARDWARE DESCRIPTION
If two requests of different priority levels are received Table 21. Priority Level Bit Values
simultaneously, the request of higher priority level is (8XC51FC Only)
serviced. If requests of the same priority level are re-
ceived simultaneously, an internal polling sequence de- Priority
Bits Interrupt Priority
termines which request is serviced. Thus within each
priority level there is a second priority structure deter- Level
IPH.x IP.x
mined by the polling sequence shown in Table 19.
0 0 Level 0 (Lowest)
Note that the "priority within level" structure is only
0 1 Level 1
used to resolve simultaneous requests of the same priori-
ty level. 1 0 Level 2
Table 19. Interrupt Priority 1 1 Level 3 (Highest)
within Level Polling Sequence
1 (Highest) INTO How Interrupts are Handled
2 Timer 0
3 INT1 The interrupt flags are sampled at SSP2 of every ma-
chine cycle. The samples are polled during the follow-
4 Timer 1
ing machine cycle. The Timer 2 interrupt cycle is
5 PCA slightly different, as described in the Response Time
6 Serial Port section. If one of the flags was in a set condition at
7 (Lowest) Timer 2 SSP2 of the preceding cycle, the polling cycle will find
it and the interrupt system will generate an LCALL to
the appropriate service routine, provided this hard-
8XC51FC Interrupt Priority Structure ware-generated LCALL is not blocked by any of the
following conditions:
In the 8XCSIFC, a second Interrupt Priority register
(lPH) has been added, increasing the number of priori- 1. An interrupt of equal or higher priority level is al-
ty levels to four. Table 20 shows this second register. ready in progress.
The added register becomes the MSB of the priority 2. The current (polling) cycle is not the final cycle in
select bits and the existing IP register acts as the LSB. the execution of the instruction in progress.
This scheme maintains. compatibility with the rest of 3. The instruction in progress is RETI or any write to
the MCS-Sl family. Table 21 shows the bit values and the IE or IP registers.
priority levels associated with each combination.
Table 20. IPH: Interrupt Priority High Register
IPH (8XC51FC Only) Address = OB7H Reset Value = XOOO 0000
Bit Addressable
PPCH PT2H PSH PT1 H PX1 H PTOH PXOH
Bit 7 6 5 4 3 2 o
Symbol Function
Not implemented, reserved for future use.
PPCH PCA interrupt priority high bit.
PT2H Timer 2 interrupt priority high bit.
PSH Serial Port interrupt priority high bit.
PT1H Timer 1 interrupt priority high bit.
PX1H External interrupt 1 priority high bit.
PTOH Timer 0 interrupt priority high bit.
PXOH External interrupt priority high bit.
8-35
inter 8XC51FX HARDWARE DESCRIPTION
Any of these three conditions will block the generation Table 22. Interrupt Vector Address
of the LCALL to the int~rrupt service routine. Condi-
'tion 2 ensures that the instruct ion in progress will be Interrupt Interrupt Cleared by Vector
completed before vectoring to any service routine. Con- Source Request Bits Hardware Address
dition 3 ensures that if the instruction in progress is INTO lEO No (level) 0OO3H
RETI or any write to IE or II', then at least one more
Yes (trans.)
instruction will be executed before any interrupt is vec-
tored to.
TIMER 0 TFO Yes OOOBH
The polling cycle is repeated with each machine cycle,
and the values polled are the values that were present at INT1 IE1 No (level) 0013H
S5P2 of the previous machine cycle. If the interrupt Yes (trans.)
flag for a level-sensitive external interrupt is active but
-
not being responded to for one of the above conditions TIMER 1 TF1 Yes 001BH
and is not still active when the blocking condition is
removed, the denied interrupt will not be serviced. In RI, TI 0023H
SERIAL PORT No
other words, the fact that the interrupt flag was once
active but not serviced is not remembered. Every poll-
ing cycle is new. TIMER2 TF2, EXF2 No 002BH
The polling cycle/LCALL sequence is illustrated in PCA CF, CCFn No 0033H
Figure 25. (n = 0-4)
Note that if an interrupt of a higher priority level goes
Execution procyeds from that location until the RETI
active prior to S5P2 of the machine cycle labeled C3 in
instruction is encountered. The RETI instruction in-
Figure 25, then in accordance with the above rules it
forms the processor that this interrupt routine is no
will be vectored to during C5 and C6, without any in- longer in progress, then pops the top two bytes from the
struction of the lower priority routine having been exe- stack and reloads the Program Counter. Execution of
cuted. the interrupted program continues from where it left
off.
Thus the processor acknowledges an interrupt request
by executing a hardware-generated LCALL to the ap- Note that a simple RET instruction would also have
propriate servicing routine. The hardware-generated returned execution to the interrupted program, but it
LCALL pushes the contents of the Program Counter
would have left the interrupt control system thinking
onto the stack (but it does not save the PSW) and re- interrupt was still in progress.
loads the PC with an address that depends on the
source of the interrupt being vectored to, as shown in
Note that the starting addresses of consecutive inter-
Table 22.
rupt service routines are only 8 bytes apart. That means
if consecutive interrupts are being used (lEO and TFO,
for example, or TFO and lEI), and if the first interrupt
routine is more than 7 bytes long, then that routine will
have to execute a jump to some other memory location
where the service routine can be completed without
overlapping the starting address of the next interrupt
routine .
........ ---C1-...,.-t-I...- - C 2 - -...~It---C3
ISSP21 S6
_I. C4 -I- C5--, .....
········~'\----'----t1'1i--,....-'----t"l.'l:t,....----I.----
f'T't
INTERRUPT INTERRUPT
INTERRUPTS
ARE POLLED
LONG CALL TO
INTERRUPT
VECTOR ADDRESS
INTERRUPT ROUTINE
GOES LATCHED
ACTIVE
270653-22
This is the fastest possible response when C2 is the final cycle of an instruction other than RETI or y.trite IE or IP.
Figure 25. Interrupt Response Timing Diagram
8-36
infef 8XC51FX HARDWARE DESCRIPTION
8.7 Response Time or write to lE or IP, the additional wait time cannot be
more than 5 cycles (a maximum of one or more cycle to
The INTO and INTI levels are inverted and latched complete the instruction in progress, plus 4 cycles to
into the Interrupt Flags lEO and lEI at S5P2 of every complete the next instruction if the instruction is MUL
machine cycle. Similarly, the Timer 2 flag EXF2 and or DIV).
the Serial Port flags RI and TI are set at S5P2. The
values are not actually polled by the circuitry until the Thus, in a single-interrupt system, the response time is
next machine cycle. always more than 3 cycles and less than 9 cycles.
The Timer 0 and Timer I flags, TFO and TFI, are set at
S5P2 of the cycle in which the timers overflow. The 9.0 RESET
values are then polled by the circuitry in the next cycle.
However, the Timer 2 flag TF2 is set at S2P2 and is The reset input is the RST pin, which has a Schmitt
polled in the same cycle in which the timer overflows. Trigger input. A reset is accomplished by holding the
RST pin high for at least two machine cycles (24 oscil-
If a request is active and conditions are right for it to be lator periods) while the oscillator is running. The CPU
acknowledged, a hardware subroutine call to the re- responds by generating an internal reset, with the tim-
quested service routine will be the next instruction to be ing shown in Figure 26.
executed. The call itself takes two cycles. Thus, a mini-
mum of three complete machine cycles elapses between The external reset signal is asynchronous to the internal
activation of an external interrupt request and the be- clock. The RST pin is sampled during State 5 Phase 2
ginning of execution of the service routine's first in- of every .machine cycle. On· the 8XC51FA and
struction. Figure 25 shows interrupt response timing. 8XC51FB the port pins, ALE and PSEN wil1 maintain
their current activities for 19 oscillator periods after a
A longer response time would result if the request is logic I has been sampled at the RST pin; that is, for 19
blocked by one of the 3 previously listed conditions. If to 31 oscil1ator periods after the external reset signal
an interrupt of equal or higher priority level is already has been applied to the RST pin.
in progress, the additional wait time obviously depends
on the nature of the other interrupt's service routine. If On the 8XC51FC, the port pins are driven to their reset
the instruction in progress is not in its final cycle, the state as soon as a valid high is detected on the RST pin,
additional wait time cannot be more than 3 cycles, since regardless of- whether the clock is running. ALE and
the longest instructions (MUL and DIV) are only 4 PSEN are synchronized to the RST input identical to
cycles long, and if the instruction in progress is RETI the 8XC5IFA/FB as described above.
1---12 OSC. PERIODS ----J
I S5 I S6 I S1 I S2 I S3 I S4 I S5 I S6 I S1 I S2 I S3 I S4 I S5 I S6 I S1 I S2 I S3 I S4 I
RST:
11111111111~
'-.J
SAMPLE, RST SAMPLE
, RST
c
-
INTERNAL RESET SIGNAL
ALE: IL.-!----In'--_-'
PSEN:
po:
,
1+--11 OSC. PERIODS - , 1 4 · - - - - - - 1 9 OSC. PERIODS --------<...
270653-23
Figure 26. Reset Timing
8-37
8XC51FX HARDWARE DESCRIPTION
While the RST pin is high, the port pins, ALE and Note that the port pins will be in a random state until the
PSEN are weakly pulled high. After RST is pulled low, oscillator has started and the internal reset algorithm
it will take I to 2 machine cycles for ALE and PSEN to has wrillen 1s to them.
start clocking. For this reason, ot her devices can not be
synchronized to the internal timings of the 8XC51FAI Powering up the device without a -valid reset could
FB. cause the CPU to start executing instructions from an
indeterminate location. This is because the SFRs, spe-
Driving the ALE and PSEN pins to 0 while reset is cifically the Prograni Counter, may not get properly
active could cause the device to go into an indetermi- initialized.
nate state.
The internal reset algorithm redefines all the SFRs. Ta- 10.0 POWER-SAVING MODES OF
ble 1 lists the SFRs and their reset values. The internal OPERATION
RAM is not affected by reset. On power up the RAM
content is indeterminate. For applications where power consumption is critical,
the C51FX provides two power reducing modes of op-
eration: Idle and Power Down. The input through
9.1 Power-On Reset which backup power is supplied during these opera-
tions is Vee. Figure 28 shows the internal circuitry
For CHMOS devices, when VCC is turned on, an auto- which implements these features. In the Idle mode
matic reset can be .obtained by connecting the RST pin (lDL = I), the oscillator continues to run and the In-
to VCC through a I tJ-F capacitor (Figure 27). The terrupt, Serial Port, PCA, and Timer blocks continue
CHMOS devices do not require an external resistor like to be clocked, but the clock signal is gated off to the
the HMOS devices because they have an internal pull- CPU. In Power Down (PD = I), the oscillator is fro- .
down on the RST pin. zen. The Idle and Power Down modes are activated by
setting bits in Special Function Register PCON (Table
When power is turned on, the circuit holds the RST pin 23).
high for an amount of time that depends on the capaci-
tor value and the rate at which it charges. To ensure a
valid reset the RST pin must be held high long enough 10.1 Idle Mode
to allow the oscillator to start up plus two machine
cycles. An instruction that sets PCON.Ocauses that to be the
last instruction executed before going into the Idle
mode. In the Idle mode, the internal clock signal is
Vee--~~----------------'
gated off to the CPU, but not to the Interrupt, Timer,
and Serial Port functions. The PCA can be pro-
grammed either to pause or continue operating during
+ Vee Idle (refer to the PCA section for more details). The
CPU status is preserved in its entirety: the Stack Point-
8XCStFA/FB/FC er, Program Counter, Program Status Word, Accumu-
lator, ,and all other registers maintain their data during
RST Idle. The port pins hold the logical states they had at
the time Idle was activated. ALE and PSEN hold at
logic high levels.
There are two ways to terminate the Idle Mode. Activa-
tion of any enabled interrupt will cause PCON.O to be
270653-24
cleared by hardware, terminating the Idle mode. The
interrupt will be serviced, and following RET! the next
Figure 27. Power on Reset Circuitry
instruction to be executed will be the one following the
On power up, Vee should rise within approximately instruction that put the device into Idle.
ten milliseconds. The oscillator start-up time will de-
pend on the oscillator frequency. For a 10 MHz crystal, The flag bits (GFO and GFI) can be used to give an
the start-up time is typically 1 msec. For a 1 MHz indication if an interrupt occurred during normal oper-
crystal, the start-up time is typically 10 msec. ation or during Idle. For example, an instruction that
activates Idle can also set one or both flag bits. When
With the given circuit, reducing Vee quickly to 0 caus- Idle is terminated by an interrupt, the interrupt service
es the RST pin voltage to momentarily fall below OV. routine can examine the flag bits.
However, this voltage is internally limited and will not
harm the device.
8-38
inter 8XC51FX HARDWARE DESCRIPTION
The other way of terminating the Idle mode is with a The signal at the RST pin clears the IDL bit directly
hardware reset. Since the clock oscillator is still run- and asynchronously. At this time the CPU resumes
ning, the hardware reset needs to be held active for only program execution from where it left off; that is, at the
two machine cycles (24 oscillator periods) to complete instruction following the one that invoked the Idle
the reset. Mode. As shown in Figure 26, two or three machine
cycles of program execution may take place before the
~~
XTAL 2 =- XTAL 1
INTERRUPT,
J-:-+--DSERIAL PORT,
TIMER BLOCKS
CPU
270653-25
Figure 28. Idle and Power Down Hardware
Table 23. PCON: Power Control Register
PCON Address = 8?H Reset Value = OOXX OOOOB
Not Bit Addressable
ISMOD1 ISMODO I POF GF1 GFO PD IDL
Bit ? 6 5 4 3 2 o
Symbol Function
SMOD1 Double Baud rate bit. When set to a 1 and Timer 1 is used to generate baud rates, and the
Serial Port is used in modes 1, 2, or 3.
SMODO When set, Read/Write accesses to SCON.? are to the FE bit. When clear, Read/Write
accesses to SCON.? are to the SMO bit.
Not implemented, reserved for future use.'
POF Power Off Flag. Set by hardware on the rising edge of Vee. Set or cleared by software. This
flag allows detection of a power failure caused reset. Vee must remain above 3V to retain
this bit.
GF1 General-purpose flag bit.
GFO General-purpose flag bit.
PD Power Down bit. Setting this bit activates Power Down operation.
IDL Idle mode bit. Setting this bit activates idle modes operation.
If 1s are written to PD and IDL at the same time, PD takes precedence.
NOTE:
'User software should not write 1s to unimplemented bits. These bits may be used in future 8051 family products to
invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1.
The value read from a reserved bit is indeterminate
8-39
8XC51FX HARDWARE DESCRIPTION
internal reset algorithm takes control. On-chip hard- Immediately after reset, the user's software can check
ware inhibits access to the internal RAM during this the status of the POF bit. POF = 1 would indicate a
time, but access to the port pins is not inhibited. To cold start. The software then clears POF and com-
eliminate the possibility of unexpected outputs at the mences its tasks. POF = 0 immediately after reset
port pins, the instruction following the one that invokes would indicate a warm start.
Idle should not be one that writes to a port pin or to
external Data RAM. Vee must remain above 3 volts for POF to retain a O.
10.2 Power Down Mode 11.0 EPROM VERSIONS
An instruction that sets PCON.l causes that to be the The 87C5IFA/FB/FC uses the fast "Quick-Pulse"
last instruction executed before going into the Power programming™ algorithm. The devices program at
Down mode. In this mode the on-chip oscillator is Vpp = 12.75V (and Vee = 5.0V) using a series of
stopped. With the clock frozen, all functions are twenty-five 100 /Jos PROG pulses per byte programmed.
stopped, but the on-chip RAM and Special Function This results in a total programming time of approxi-
Registers are held. The port pins output the values held mately 26 seconds for the 87C51FA's 8K bytes and
by their respective SFRs, and ALE and PSEN output approximately 50 seconds for the 87C51FB's 16K
lows. In Power Down Vee can be reduced to as low as bytes.
2V. Care must be taken, however, to ensure that Vee is
not reduced before Power Down is invoked. The 87C51FC can be programmed with fewer PROG
pulses. Under same programming conditions as the
The C51FX can exit Power Down with either a hard- s'XC5IFA/FB the 87C51FC can be programmed with
ware reset or external interrupt. Reset redefines all the only 5 pulses. The programming time for the
SFRs but does not change the on-chip RAM. An exter- 87C51FC's 32K bytes can be as low as 20 seconds.
nal interrupt allows both the SFRs and the on-chip
RAM to retain their values. Exposure to Light: The EPROM window must be cov-
ered with an opaque label when the device is in opera-
To properly terminate Power Down the reset or exter- tion. This is not so much to protect the EPROM array
nal interrupt should not be executed before Vee is from inadvertent erasure, but to protect the RAM and
restored to its normal operating level and must be held other on-chip logic. Allowing light to impinge on the
active long enough for the oscillator to restart and sta- silicon die while the device is operating can cause logi-
bilize (normally less than 10 msec). cal malfunction.
With an external interrupt, INTO or INTI must be en-
abled and configured as level-sensitive. Holding the pin 12.0 PROGRAM MEMORY LOCK
low restarts the oscillator and bringing the pin back
high completes the exit. After the RET! instructiori is In some microcontroller applications, it is desirable
executed in the interrupt service routine, the next in- that the Program Memory be secure from software pi-
struction will be the one following the instruction that racy. The C51FX has varying degrees of program pro-
put the device in Power Down. - tection depending on the device. Table 24 outlines the
lock schemes available for each device.
10.3 Power Off Flag Encryption Array: Within the EPROM/ROM is an ar-
ray of encryption bytes that are initially unprogrammed
The Power Off Flag (POF) is set by hardware when (all I's). For EPROM devices, the user can program
Vee rises from 0 to 5 Volts. POF can also be set or the encryption array to encrypt the program code bytes
cleared by software. This allows the user to distinguish during EPROM verification. For ROM devices, the
between a "cold start" reset and a "warm start" reset. user submits the encryption array to be programmed by
the factory. If an encryption array is submitted, LBI
A cold start reset is one that is coincident with Vee will also be programmed by the factory. The encryption
being turned on to the device after it was turned off. A array is not available without the Lock Bit. Program
warm start reset occurs while Vee is still applied to the code verification is performed as usual, except that each
device and could be generated, for example, by a code byte comes out exciusive-NOR'ed (XNOR) with
Watchdog Timer or an exit from Power Down.
8-40
inter 8XC51FX HARDWARE DESCRIPTION
one of the key bytes. Therefore, to read the 13.0 ONCE MODE
ROM/EPROM code, the user has to know the encryp-
tion key bytes in their proper sequence. The ONCE (ON-Circuit Emulation) mode facilitates
testing and debugging of systems using the C51FX
Unprogrammed bytes have the value OFFH. If the En- without having to remove the device from the circuit.
cryption Array is left unprogrammed, all the key bytes The ONCE mode is invoked by:
have the value OFFH. Since any code byte XNOR'ed
1. Pulling ALE low while the device is in reset and
with OFFH leaves the byte unchanged, leaving the En- PSEN is high;
cryption Array unprogrammed in effect bypasses the
encryption feature. 2. Holding ALE low as RST is deactivated.
Program Lock Bits: Also included in the Program While the device is in ONCE mode, the Port 0 pins go
Lock scheme are Lock Bits which can be enabled to into a float state, and the other port pins, ALE, and
provide varying degrees of protection. Table 25 lists the PSEN are weakly pulled high. The oscillator circuit
Lock Bits and their corresponding influence on the mi- remains active. While the device is in this mode, an
crocontroller. Refer to Table 24 for the Lock Bits avail- emulator or test CPU can be used to drive the circuit.
able on the various products. The user is responsible for
programming the Lock Bits on EPROM devices. On Normal operation is restored' after a valid reset is ap-
ROM devices, LBI is automatically set by the factory plied.
when the encryption array is submitted. The Lock Bit
is not available without the encryption array on ROM
devices. 14.0 ON-CHIP OSCILLATOR
Erasing the EPROM also erases the Encryption Array The on-chip oscillator for the CHMOS devices, shown
and the Lock Bits, returning the part to full functionali- in Figure 29, consists of a single stage linear inverter
ty. intended for use as a crystal-controlled, positive reac-
tance oscillator. In this application the crystal is operat-
Table 24. C51FX Program Protection ing in its fundamental response mode as an inductive
reactance in parallel resonance with capacitance exter-
Device Lock Bits Encrypt Array nal to the crystal (Figure 30).
83C51FA None None
The oscillator on the CHMOS devices can be turned off
83C51FB None None under software control by setting the PD bit in the
PCON register. The feedback resistor Rr in Figure 29
83C51 FC LB1 64 Bytes consists of paralleled n- and p-channel FETs controlled
87C51FA LB1,LB2 32 Bytes by the PD bit, such that Rr is opened when PD = 1.
The diodes D 1 and D2, which act as clamps to Vee
87C51FB LB1,LB2 32 Bytes and VSS, are parasitic to the Rr FETs.
87C51FC LB1,LB2,LB3 64 Bytes
Table 25. Lock Bits
Program Lock Bits
Protection Type
LB1 LB2 LB3
1 U U U No program lock features enabled. (Code verify will still be encrypted by the
encryption array if programmed.)
2 P U U MOVC instructions executed from external program memory are disabled from
fetching code bytes from internal memory, EA is sampled and latched on
reset, and further programming of the EPROM is disabled.
3 P P U Same as 2, also verify is disabled.
4 P P P Same as 3, also external execution is disabled.
P = Programmed
U = Unprogrammed
Any other combination of the Lock Bits is not defined.
8-41
intJ 8XC51FX HARDWARE DESCRIPTION
The crystal specifications and capacitance values (Cl A more in-depth discussion of crystal specifications, ce-
and C2 in Figure 30) are not critical. 30 pF can be used ramic resonators, and the selection of values for C 1 and
in these positions at any frequency with good quality C2 can be found in Application Note AP-155, "Oscilla_
crystals. In general, crystals used with these devices tors for Microcontrollers" in the Embedded Control
typically have the following specifications: Applications handbook.
ESR (Equivalent Series Resistance) see Figure 32
To drive the CHMOS parts with an external clock
Co (shunt capacitance) 7.0 pF maximum source, apply the external clock signal to XTALI and
CL (load capacitance) 30 pF ± 3 pF leave XTAL2 floating as shown in Figure 31. This is an
Drive Level I MW important difference from the HMOS parts. With
HMOS, the external clock source is applied to XTAL2,
Frequency, tolerance, and temperature range are deter- and XTAL 1 is grounded.
mined by the system requirements. .
An external oscillator may encounter as much as a
A. ceramic resonator can be used in place of the crystal 100 pF load at XTALI when it starts up. This is due to
in cost-sensitive applications. When a ceramic resona- interaction between the' amplifier and its feedback ca-
tor is used, Cl and C2 are normally selected as higher pacitance. Once the external signal meets the VIL and
values, typically 47 pF. The manufacturer of the ceram- VIH specifications the capacitance will not exceed
ic resonator should be consulted for recommendations 20pF.
on the values of these capacitors.
VCC
TO INTERNAL
TIMING CKTS
01
4000
XTAL1 XTAL2
02
r PO
270653-26
Figure 29. On-Chip Oscillator Circuitry
8-42
8XC51FX HARDWARE DESCRIPTION
VCC
TO INTERNAL
TIMING CKTS
VSS
XTAL2------
SOC51
~-r--- QUARTZ CRYSTAL
OR CERAMIC
RESONATOR
270653-27
Figure 30_ Using the CHMOS On-Chip Oscillator
~--------------------~
8XC51FA/FB
NC XTAL2 500
EXTERNAL
OSCILLATOR
SIGNAL
tx-----t XTALl Ul
::E
:I:
0
.E
400
300
Vss
CMOS GATE '"
Ul
200
'"
270653-28 100
Figure 31. Driving the CHMOS Partswith an
4 B 12 16
External Clock Source
CRYSTAL FREQUENCY in 104Hz
270653-29
15.0 CPU TIMING Figure 32. ESR vs Frequency
The internal clock generator defines the sequence of
states that make up a machine cycle. A machine cycle each other. The timings published in the data sheets
consists of 6· states, numbered S 1 through S6. Each include the effects of propagation delays under the
state time lasts for two oscillator periods. Thus a ma- specified test condition.
chine cycle takes 12 oscillator periods or 1 microsecond
if the oscillator frequency is 12 MHz. Each state is then
divided into a Phase 1 and Phase 2 half. ADDITIONAL REFERENCES
The following application notes provide supplemental
Rise and fall times are dependent on the external load-
information to this document and can be found in the
ing that each pin must drive. They are approximately
Embedded Control Applications handbook.
10 nsec, measured between O.8V and 2.0V.
1. AP-125 "Designing Microcontroller Systems for
Propagation delays are different for different pins. For Electrically Noisy Environments"
a given pin they vary with pin loading, temperature, 2. AP-155 "Oscillators for Microcontrollers"
Vco and manufacturing lot. If the XTALI. waveform 3. AP-252 "Designing with the 80C51BH"
is taken as the timing reference, propagatIOn delays
may vary from 25 to 125 nsec. 4. AP-41O "Enhanced Serial Port on the 83C51FA"
5. AP-415 "83C51FA/FB PCA Cookbook"
The AC Timings section of the data sheets do not refer-
6. AB-41 "Software Serial Port Implemented with the
ence any timing to the XTALI waveform. Rather, they
PCA"
relate the critical edges of control and input signals to
7. AP-425 "Small DC Motor Control"
8. The appropriate data sheet.
8-43
April 1990
8XC51GB
Hardware Description
Automotive
Order Number: 270691-002
8-44
8XC51GB HARDWARE CONTENTS PAGE
DESCRIPTION 1.0 FUNCTIONAL DESCRiPTION ....... 8-47
1.1 8XC51GB Features .............. 8-47
1.2 Summary of 8XC51 GB B-Step
Enhancements ................ 8-47
1.3 Compatibility with MCS®-51
Family ......................... 8-49
2.0 EPROM VERSIONS ................. 8-49
2.1 EPROM Program Memory
Locks ......................... 8-49
2.2 EPROM Programming and
Verification Characteristics ..... 8-51
3.0 MEMORY ........................... 8-54
3.1 Upper 128 Bytes of RAM ......... 8-54
3.2 8XC51GB External Memory
Addressing .................... 8-54
4.0 SPECIAL FUNCTION
REGISTERS ...................... 8-54
5.0 PORT STRUCTURES AND
OPERATION ...................... 8-58
5.1 I/O Configurations ............... 8-59
5.2 Writing to a Port .................. 8-60
5.3 Port Loading and Interfacing ..... 8-60
5.4 Read-Modify-Write Feature ...... 8-60
5.5 Accessing External Memory ...... 8-61
6.0 TIMERS/COUNTERS ............... 8-62
6.1 Timer 0 and Timer 1 .............. 8-62
6.2 Timer 2 .......................... 8-64
7.0 PROGRAMMABLE COUNTER/
TIMER ARRAYS (PCAs) .......... 8-68
7.1 Overview of the PCA and PCA 1
Hardware ...................... 8-69
7.2 PCA 16-BitTimer/Counters ...... 8-69
7.3 PCA116-BitTimer/Counter ...... 8-71
7.4 Capture/Compare Modules ...... 8-73
7.5 16-Bit Capture Mode ............. 8-75
7.6 16-Bit Software Timer Mode ...... 8-75
7.7 High Speed Output Mode ........ 8-76
7.8 Pulse Width Modulator Mode ..... 8-76
7.9 PCA Watchdog Timer Mode ...... 8-77
8-45
CONTENTS PAGE CONTENTS PAGE
8.0 SERIAL INTERFACE ................ 8-77 11.0 INTERRUPTS ...................... 8-91
8.1 Automatic Address Recognition .. 8-78 11.1 Interrupt Enable ............... 8-93
8.2 Framing Error Detection .......... 8-78 11 .2 Priority Level Structure ........ 8-94
8.3 Serial Port Control Register ...... 8-79 11.3 External Interrupts ............. 8-97
8.4 Baud Rates ...................... 8-79 11.4 Response Time ............... 8-98
8.5 Using Timer 1 to Generate Baud 11.5 Single Step Operation ......... 8-98
Rates ......................... 8-80
8.6 Using Timer 2 to Generate Baud 12.0 RESET ............................. 8-98
Rates ......................... 8-80 12.1 Power-On Reset .............. 8-99
8.7 Mode 0 Serial ......... ; .......... 8-82
13.0 WATCHDOG TIMER (WDT) ....... 8-99
8.8 Mode 1 Serial .................... 8-82
13.1 WDT in Idle Mode ............. 8-99
8.9 Modes 2 and 3 Serial ............ 8-85
13.2 WDT in Power Down Mode ... 8-100
9.0 SERIAL EXPANSION PORT
(SEP) ............................. 8-88 14.0 POWER·SAVING MODES OF
OPERATION ................... 8-100
9.1 Transmitting ..................... 8-88
14.1 Idle Mode .................... 8-101
9.2 Receiving ........................ 8-88
14.2 Power Down Mode ........... 8-101
9.3 SEP Interrupt .................... 8-89
14.3 Power Off Flag ............... 8-101
10.0 AID CONVERTER ... '.............. 8-89
15.0 OSCILLATOR FAIL DETECT
10.1 Conversion Cycle .............. 8-89 (OFD) .......................... 8-102
10.2 AID Modes ................... 8-90
16.0 RFI REDUCTION MODE .......... 8-102
10.3 COMPREF Feature ............ 8-91
17.0 PIN ASSiGNMENT ................ 8-103
8-46
inter
8XC51GB HARDWARE DESCRIPTION
1.0 FUNCTIONAL DESCRIPTION • Serial Expansion Channel
• 48 Programmable I/O Lines with:
The 8XCSIGB is a highly integrated 8-bit microcon- - 40 Schmitt Trigger Inputs
troller based on the MCS®-Sl architecture. Its key fea-
tures include a Serial Expansion Port, an 8-bit 8-chan- • 15 Interrupt Sources with:
nel A/D converter, a flexible timer/counter subsystem, - 7 External, 8 Internal Sources
hardware support for operation in electrically noisy en- - 4 Programmable Priority Levels
vironments, and security for the on-chip EPROM • Pre-Determined Port States
memory. As a member of the MCS-SI family of devic-
es, the 8XCSIGB is optimized for control applications. • High Performance CHMOS Process
Its architecture and instruction set facilitate efficient • TTL and CHMOS Compatible Logic Levels
utilization of the on-chip memory and peripheral re- • Power Saving Modes
sources.
• 64K External Data Memory Space
The 8XCSIGB is a superset of the 80CSI microcontrol- • 64K External Program Memory Space
ler. It is software compatible with the 80CSI allowing • Two Level Program Lock System
use of existing software development tools.
• Once™ (ON-Circuit Emulation) Mode
• Quick Pulse Programming™ Algorithm
1.1 8XC51GB Features • MCS®-Sl Fully Compatible Instruction Set
The features of the 8XCSI GB are: • Boolean Processor
• Extended Automotive Temperature Range • Oscillator Fail Detect
- (-40°C to + 125°C Ambient) • RFI Reduction Mode
• 8K Bytes On-Chip EPROM • Available in 68-Pin LCC, 68-Pin PLCC
• 256 Bytes of On-Chip Data RAM
• Two Programmable Counter Arrays with: 1.2 Summary of 8XC51GB B-Step
- 2 X 5 High Speed Input/Output Channels Enhancements
- Compare/Capture • Reset pin; changed from Active High to Active Low
- Pulse Width Modulators
• Port I; changed from High, to Low by Reset
- Watchdog Timer Capabilities
• Signature Bytes; changed from 2-byte to FX 3-byte
• Three 16-Bit Timer/Counters with: Scheme
- Four Programmable Modes (Timers 0, 1)
- Capture, Baud Rate Generation (Timer 2) • P1.0/T2 is a Timer 2 overflow output
• Third security bit added for RAM contents protec-
•Dedicated Watchdog Timer
tion
•8-Bit, 8-Channel AID with:
- Eight 8-Bit Result Registers
- Four Programmable Modes
•Programmable Serial Channel with:
Framing Error Detection
- Automatic Address Recognition
8-47
intJ 8XC51GB HARDWARE DESCRIPTION
PO.O - PO.7
-
Vee" - - - - - - - - - -
Vss I
-±:
SF"Rs
TIMERs
P.C.A
P.C.A.1
SERIAL PORTS
!'SEN
ALE/~
£A/Vpp
RESET
r.....;:.:;.-......-'-TRIGIN
COMPREF
AV REf
L-,....'T'rI,...-I-·AVss
A
..,..... C
P1.0- Pl.7 PS.O-PS.7 ~4.0- P4.7 P3.0-P3.7 H
7
270691-1
Figure 1. 8XC51GB Block Diagram
8-48
infef 8XC51GB HARDWARE DESCRIPTION
1.3 Compatibility with MCS®-51 Family
The 8XC51GB is compatible with the 87C51 and 87C51FA as shown in Table 1.
Table 1. GB's Compatibility with 80C51 Family of Products
GB Features 80C51 FA
Ports 0-3 No' No'
Ports 4,5 No No
Hysteresis Inputs No No
Timers 0 and 1 Same Same
Timer 2 No Same
PCA No Same
PCA1 No No
Serial Port Comp Same
SEP No No
AID No No
INTO,INT1 Same Same
INT2-6 No No
Internal Interrupts Comp Comp
Dedicated Watchdog Timer No No
Idle Mode Same Same
Power Down Mode Comp Same
Oscillator Fail Detect No No
RFI Reduction No No
Reset (Active Low) No (Active High) No (Active High)
Key
No This part does not have the feature.
Comp The GB feature is backwards compatible with the feature on this part.
Same The GB' feature is the same as the feature on this part.
N.C. This part has this feature but it is not compatible with the GB's feature.
'Ports I and 4 reset to Low.
2.0 EPROM VERSIONS the RAM and other on-chip logic. Allowing light to
impinge on the silicon die while the device is operating
The GB uses the fast Quick-Pulse™ Programming al- can cause logical malfunction.
gorithm. The GB programs at Vpp = 12.75V (and
Vee = 5.0V) using a series of twenty-five 100 Il-s
PROG pulses per byte programmed. This results in a 2.1 EPROM Program Memory Locks
total programming time of approximately 26 sec,onds
for the 87C51GB's 8K bytes of EPROM. In some microcontroller applications it is desirable that
the Program Memory be secure from software piracy.
Exposure to Light: It is good practice to cover the The GB has two security features which protect the
EPROM window with an opaque label when the device code of the on-chip EPROM: a 64-byte encryption ar-
is in operation. This is not so much to protect the ray and two Program Lock bits.
EPROM array from inadvertent erasure, but to protect
8-49
8XC51GB HARDWARE DESCRIPTION
Table 2. Program Lock Bit Features Erasure Characteristics
EPROM
Erasure of the EPROM begins to occur when the chip
Allowed States Result is exposed to light with wavelength shorter than ap-
LB3 LB2 LB1 proximately 4,oooA. Since sunlight and fluorescent
lighting have wavelengths in this range, exposure to
U U U No protection these light sources over an extended time (about 1 week
U U P No external MOVe in sunlight, or 3 years in room-level fluorescent light-
ing) could cause inadvertent erasure. If an application
u p P No external MOVe, subjects the device to this type of exposure, it is sug-
No Verify gested that an opaque label be placed over the window.
p p P No external MOVe, The recommended erasure procedure is exposure to ul-
No Verify, no external traviolet light (at 2537A) to an integrated dose of at
Opcodes least 15 W-sec/cm. Exposing the EPROM to an ultra-
violet lamp of 12,000 p. W/cm rating for 30 minutes, at
a distance of about 1 inch, should be sufficient.
Reading the Signature Bytes
Erasure leaves EPROM Cells in all Is state.
The signature bytes are read by the same procedure as a
normal verification of locations IEH and IFH, except
that P3.6 and P3.7 need to be pulled to a logic low. The
values returned are:
(IEH) = 89H indicates manufactured by Intel
(IFH) = 5AH indicates 87C51GB
(060H) = EBH indicates 87C51GB
8-50
8XC51GB HARDWARE DESCRIPTION
2.2 EPROM Programming and Verification Characteristics
(TA = 21°C to 27°C; Vee = sv ± 10%; vss = OV)
ADVANCED INFORMATION. CONTACT INTEL FOR DESIGN-IN INFORMATION
Symbol Parameter Min Max Units
Vpp Programming Supply Voltage 12.5 13.0 V
Ipp Programming Supply Current 50 mA
1/TCLCL Oscillator Frequency 4 6 MHz
TAVGL Address Setup to PROG Low 48TCLCL
TGHAX Address Hold after PROG 48TCLCL
TDVGL Data Setup to PROG Low 48TCLCL
TGHDX Data Hold after PROG 48TCLCL
TEHSH P2.7 (ENABLE) High to Vpp 48TCLCL
TSHGL Vpp Setup to PROG Low 10 ).Ls
TGHSL Vpp Hold after PROG 10 ).Ls
TGLGH PROGWidth 95 105 ).Ls
TAVQV Address to Data Valid 48TCLCL
TELQV ENABLE Low to Data Valid 48TCLCL
TEHQZ Data Float after ENABLE 0 48TCLCL
TGHGL PROG High to PROG Low 10 ).Ls
EPROM CHARACTERISTICS to be running is that the internal bus is being used to
transfer address and program data to appropriate inter-
Table 3 shows the logic levels for programming the nal EPROM locations.) The address of an EPROM lo-
Program memory, the Encryption Table, and the Lock cation to be programmed is applied to Port 1 and pins
Bits and for reading the signature bytes. P2.0-P2.4 of Port 2, while the code byte to be pro-
grammed into that location is applied to Port O.
ALE/PROG is pulsed low to program the code byte
PROGRAMMING THE EPROM into the addressed EPROM location.
To be programmed, the part must be running with a
4 to 6 MHz oscillator. (The reason the oscillator needs
Table 3. EPROM Programming Modes
ALE! EA!
Mode RST PSEN P2.7 P2.6 P3.6 P3.7
PROG Vpp
Program Code Data 1 0 O· Vpp 1 0 1 1
Verify Code Data 1 0 1 1 0 0 1 1
Program Encryption Table
Use Addresses 0-3F
1 0 O' Vpp 1 0 0 1
Program Lock x = 1 1 0 o· Vpp 1 1 1 1
Bits (LBx) x = 2 1 0 O· Vpp 1 1 0 0
Read Signature 1 0 1 1 0 0 0 0
NOTES:
"1" = Valid hi9h for that pin
"0" = Valid low for that pin
"Vpp" = +12.75V ±0.25V
* ALE/PROG is pulsed low for 100 fLs for programming (Quick-Pulse Programming)
8-51
inter 8XC51GB HARDWARE DESCRIPTION
+5V
vee
AO-A7 Pl PO PGM DATA
RST EA/Vpp 1+---+12.75V
ALE/PROG 1+---25 100}.l.s PULSES TO GND
P3.6
PSEN ....- - 0
BXC51GB
P3.7
P2.7
P2.6 ....- - 0
P2.0
AB-A12
-P2.4
270691-2
Figure 2. Programming the EPROM
Normally EA/vpp is held at logic high until just before ming, the entire array should be verified. The only dif-
ALE/PROG is to be pulsed. Then EA/Vpp is raised to ference in programming Program Lock features is that
Vpp, ALE/PROG is pulsed low, and then EA/Vpp is the Program Lock features cannot be directly verified.
returned to a valid high voltage. The voltage on the Instead, verification of programming is by observing
EA/Vpp pin must be at the valid EA/Vpp high level that their features are enabled.
before a verify is attempted. Waveforms and detailed
timing specifications are shown in later sections of this
data sheet. Program Verification (EPROM only)
Note that the EA/Vpp pin must not be allowed to go If the Program Lock Bits have not been programmed,
above the maximum specified Vpp level for any amount the on-chip Program Memory can be read out for veri-
of time. Even a narrow glitch above that voltage level fication purposes, if desired, either during or after the
can cause permanent da.mage to the device. The Vpp programming operation. The address of the Program
source should be well regulated and free of glitches. Memory location to be read is applied to Port I and
pins P2.0-P2.4. The contents of the addressed loc;a-
tions will come out on Port O. External pull ups are
Quick-Pulse Programming Algorithm required on Port O. External pullups are required. on
Port 0 for this operation.
The 87C51GB (EPROM only) can be programmed us-
ing the Quick-Pulse Programming Algorithm for mi- If the Encryption Array in the EPROM has been pro-
crocontrollers. The features of the new programming grammed, the data present at Port 0 will be Code Data
method are a lower Vpp (12.75V as compared to 21V) XNOR Encryption Data. The user must know the En-
and a shorter programming pulse. It is possible to pro- cryption Array contents to manually "unencrypt" the
grani the entire 8K Bytes of EPROM memory in less data during verify.
than 25 seconds with this algorithm!
The setup, which is shown in Figure 4 is the same as for
To program the part using the new algorithm, Vpp programming the EPROM except that pin P2.7 is held
must be 12.75V ±O.25V. ALE/PROG is pulsed low at a logic low, or may be used as an active-low read
for 100 p.s, 25 times as shown in Figure 3. Then, the strobe.
byte just programmed may be verified. After program-
8-52
8XC51GB HARDWARE DESCRIPTION
1 ~I· - - - - - - 2 5 PULSES --------1'1
ALE/PROG:~-----~
'------..---J
"'-. 1 I' 100).'s
'I
n n
10}Ls MIN :I: 10}Ls
ALE/PROG :---"':''''1
O~ ____________ ~ ~ __________ ~. ~. _____
270691-3
Figure 3. PROG Waveforms
+5V
Vee
1----11-1, PGM
AO-A7 Pl PO r - - - , / DATA
RST EA/Vpp
ALE/PROG
P3.6
PSEN 1+----0
aXC51GB
P3.7
P2.7 1+----0 (ENABLE)
XTAL2 P2.6 1+----0
'--_-~__iXTAL 1
Vss
270691-4
Figure 4. Verifying the EPROM
EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
PROGRAMMING VERIFICATION
P1.0-P1.7
P2.0-P2.4 ------1:::~~~~ ADDRESS
-TAVOV
PORTO------~(::~~~ DATA OUT
TDVGL TGHDX
TGHAX
ALE/PROG -------'"\1
TSHGLt--
TGLGH
EA/Vpp If Vpp EA/HIGH
----~-;-
.......~ITEHSH
TELOV1J1-_ _ _--Ji .....-_TE_H_O_Z____
P2.7
-_.....
270691-5
8-53
inter 8XC51GB HARDWARE DESCRIPTION
3.0 MEMORY The MOVX A,@Ri instructions allow 256 bytes of ex-
ternal data memory to be addressed with just Port 0,
ALE (Address Latch enable), RD and WR. Port 2 is
3.1 Upper 128 Bytes of RAM not affected. Port 0 is multiplexed with address and
data.
The 8XCSIGB implements a full 256 bytes of on-chip
data RAM. The upper !28 bytes occupy a parallel ad- The DPTR 16-bit register can be used to access any
dress space to the Special Function Registers. That byte in the 64K external data address space. Use of port
means they have the same addresses, but they are phys- pins and paging is not necessary to address > 2S6 bytes.
ically separate from SFR space. The MOVX A,@DPTR instructions use both Port 0
and Port 2 for address. The instructions follow the
When an instruction accesses an internal location above same pattern as previously shown.
address 7FH, the CPU knows whether the access is to
the upper 128 bytes of data RAM or to SFR space by In addition to opcode fetches, the program code memo-
the addressing mode used in the instruction. Instruc- ry can be accessed with the MOVC instruction. The
tions that use direct addressing access SFR space. For MOVC instruction uses A as an index to either DPTR
example: or PC. Only read cycles are allowed and PSEN (Pro-
gram Store enable) is used to strobe a program memory
MOV OAOH, # data read. For a common program and data memory, PSEN
and RD can be NORed for a single read strobe. The
accesses the SFR at location OAOH (which is P2). In- instruction formats for program memory accessed are
structions that use indirect addressing access the upper shown below:
128 bytes of data RAM. For example:
MOVC A,@+PC ;A ~ «A + PC»
MOV@RO,#data MOVC A,@A + DPTR ; A ~ «A + DPTR»
where RO contains OAOH, accesses the data byte at ad- There are reasons for using MOVX A, @DPTR and
dress OAOH, rather than P2 (whose address is OAOH). MOVC A,@A + DPTR for external tables. MOVC
Note that stack operations are examples of indirect ad- is the quickest since the exact table location is calcu-
dressing, so the upper 128 bytes of data RAM are avail- lated in hardware. For the fastest table access, the
able as stack space. MOVC A,@A + DPTR,PC instructions are preferred.
The access time required by the data memory instruc-
tions is much relaxed as compared with EPROM ac-
3.2 8XC51GB External Memory cess time. Therefore in low cost lookup applications,
Addressing slow EPROMs addressed by MOVX instructions are
probably more cost effective.
In addition to internal memory accesses, the 8XC51GB
allows for external program and data memory access-'
ing. The implementation follows that of the 80CS!. The 4.0 SPECIAL FUNCTION REGISTERS
program and data memory sections are each 64K bytes'
long. The first 8K of the program address space is used A map of the on-chip memory area called SFR (Special
by on-chip EPROM. When EA (External Address en- Function Register) space is shown in Table 4.
able) is tied low and the security bits are not pro-
grammed, the first 8K of the program address space Note that not all of the addresses are occupied. Unoc-
will be mapped external (no internal EPROM access- cupied addresses are not implemented on the chip.
es). The MOVX instruction is used for external data Read accesses to these addresses will in general return
reads and writes, and the MOVC can be used to read random data, and write accesses will have no effect.
program code.
User software should not write Is to these unimple-
For data transfers, RO or RI can be used as a pointer to mented locations, since they may be used in future
the first page of external data memory. Read and write MCS-SI products to invoke 'new features. In that case
instructions are coded as follows: the reset or inactive values of the new bits will always
be 0, and their active values will be 1.
MOVX A,@Ri (i = 0, I) ; A ~ «Ri»
MOVX @Ri,A ; «Ri» ~ A
8-54
inter 8XC51GB HARDWARE DESCRIPTION
The functions of the SFRs are outlined below. More and status bits are contained in registers TCON and
information on the use of specific SFRs with each pe- TMOD for Timers 0 and I and in registers T2CON and
ripheral is found in the description of that peripheral. T2MOD for Timer 2. The register pair (RCAP2H,
RCAP2L) are the Capture/Reload registers for Timer
Accumulator: ACC is the Accumulator register. The 2 in 16-bit capture mode or 16-bit auto-reload mode.
mnemonics for Accumulator-Specific instructions,
however, refer to the Accumulator simply as A. Programmable Counter Array (PCA) Registers: For
the PCA, registers CCON and CMOD contain the con-
B Register: The B register is used during multiply and trol and status bits. The PCA 16-bit timer is registers
divide operations. For other instructions it can be treat- CH and CL. CCAPMO-CCAPM4 control the mode
ed as another scratch pad register. for each of the five PCA modules, and register pairs
(CCAPOH, CCAPOL)-(CCAP4H, CCAP4L) are the
Stack Pointer: The Stack Pointer Register is 8 bits 16-bit Compare/Capture registers for each PCA mod-
wide. It is incremented before data is stored during ule. The corresponding PCAI registers are CICON,
PUSH and CALL executions. While the stack may re- CIMOD, CHI, CLl, CICAI'MO-CICAPM4, and
side anywhere in on-chip RAM, the Stack Pointer is pairs (C I CAPOH , CICAPOL)-(CICAP4H,
initialized to 07H after a reset. This causes the stack to CICAP4L).
begin at location OSH.
Serial Port Registers: The Serial Data Buffer, SBUF, is
Data Pointer: The Data Pointer (DPTR) consists of a actually two separate registers, a transmit buffer and a
high byte (DPH) and a low byte (DPL). Its intended receive buffer register. When data is moved to SBUF, it
function is to hold a 16-bit address. It may be manipu- goes to the transmit buffer where it is held for serial
lated as a 16-bit register or as two independent S-bit transmission. (Moving a byte to SBUF is what initiates
registers. the transmission). When data is moved from SBUF, it
comes from the receive buffer. Register SCON contains
Ports 0 to 5 Registers: PO, PI, P2, P3, P4, and P5 are the control and status bits for the Serial Port. Registers
the SFR latches of Port 0, Port I, Port 2, Port 3, Port 4, SADDR and SADEN are used to define the Given and
and Port 5 respectively. the Broadcast addresses for the Automatic Address
Recognition feature.
Timer Registers: Register pairs (THO, TLO), (THI,
TLl), and (TH2, TL2) are the l6-bit Counting registers Program Status Word: The PSW register contains pro-
for Timer/Counters 0, I, and 2, respectively. Control gram status information as detailed in Table 5.
8-55
inter 8XC51GB HARDWARE DESCRIPTION
Table 4. SFR Mapping and Reset Values
F8
*P5 CH CCAPOH CCAP1H CCAP2H CCAP3H CCAP4H FF
00000000 00000000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
*S ADRES7 SEPSTA
FO 00000000 00000000 XXXXXOOO F7
'C1CON CL CCAPOL CCAP1L CCAP2L CCAP3L CCAP4L EF
E8 00000000 00000000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
'ACC ADRES6 SEPDAT
EO 00000000 00000000 XXXXXXXX E7
D8 'CCON CMOD CCAPMO CCAPM1 CCAPM2 CCAPM3 CCAPM4 DF
OOXOOOOO OOXXXOOO XOOOOOOO XOOOOOOO XOOOOOOO XOOOOOOO XOOOOOOO
'PSW ADRES5 SEPCON D7
DO 00000000 00000000 XXOOOOOO
C8 *T2CON T2MOD RCAP2L RCAP2H TL2 TH2 CF
00000000 XXXXXXXO 00000000 00000000 00000000 00000000
*P4 ADRES4 EXICON ACMP
co 00000000 00000000 XOOOOOOO 00000000 C7
S8 'IP SADEN C1CAPOH C1CAP1H C1CAP2H C1CAP3H C1CAP4H CH1 SF
XOOOOOOO 00000000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00000000
so 'P3 ADRES3 IPA1 IPA IPL S7
11111111 00000000 00000000 00000000 XOOOOOOO
A8 'IE SADDR C1CAPOL C1CAP1L C1CAP2L C1CAP3L C1CAP4L CL1 AF
00000000 00000000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00000000
*P2 ADRES2 OFDCON WDTCON lEA
AD 00000000 00000000 XXXXXXXO XXXXXXXX 00000000 A7
'SCON SSUF C1CAPMO C1CAPM1 C1CAPM2 C1CAPM3 C1CAPM4 C1MOD 9F
98
00000000 XXXXXXXX XOOOOOOO XOOOOOOO XOOOOOOO XOOOOOOO XOOOOOOO XXXXOOOO
90
'P1 ADRES1 ACON 97
11111111 00000000 XXOOOOOO
'TCON TMOD TLO TL1 THO TH1 AUXR 8F
88
00000000 00000000 00000000 00000000 00000000 00000000 XXXXXXXO
'PO SP DPL DPH ADRESO PCON"
80 11111111 00000111 00000000 00000000 00000000 OOXXOOOO 87
• Bit addressable registers. All registers at addresses that end In OH or 8H are bit-addressable .
.. Bit PCON.4 is not affected by reset. See description of PCON in Table 35.
8·56
8XC51GB HARDWARE DESCRIPTION
Table 5. PSW: Program Status Word Register
PSW Address = ODOH Reset Value = 0000 OOOOB
Bit 765 4 3 2 o
PSW CY AC FO RS1 RSO OV P
Symbol Name and Significance
CY Carry flag.
AC Auxiliary Carry flag. (For BCD operations)
FO Flag o. (Available to the user for general purposes).
RS1 Register bank select bit 1.
RSO Register bank select bit o.
RS1 RSO Working Register Bank and Address
o 0 Bank 0 (00H-07H)
o 1 Bank 1 (08H-OFH)
1 0 Bank 2 (10H-17H)
Bank 3 (18H-1FH)
OV Overflow flag.
User definable flag.
P Parity flag. Set/cleared by hardware each instruction cycle to indicate an odd/even
number of "one" bits in the Accumulator, i.e., even parity.
Serial Expansion Port (SEP) Registers: The SEPDAT quest bits are in the various peripheral control registers
register is the serial expansion port data register. The (see Interrnpts section). The individual interrupt enable
SEPCON register controls the operation of the SEP, bits are in registers IE and lEA. One of four priorities
and the SEPSTA register returns the status of the SEP can be set for each of the 15 interrupts in registers IP,
operation. IPL, IPA, and IPAI.
AID Converter Registers: Register ACON controls the Control Registers: WDTCON is the Watchdog Timer
AID operation. Register ACMP holds the compare re- Reset Register. PCON controls the Power Reduction
sults and registers ADRESO through ADRES7 hold Modes. The Oscillator Fail Detect Register OFDCON
the conversion results of eight channels. controls the oscillator fail detect feature. The Auxiliary
Register AUXR controls the RFI reduction mode.
Interrupt Registers: The interrupt request bits for ex-
ternal interrupts are in register EXICON. Other re-
8-57
inter 8XC51GB HARDWARE DESCRIPTION
5.0 PORT STRUCTURES AND external memory address, time-multiplexed with byte
being written or read. Port 2 outputs the high byte of
OPERATION the external memory address when the address is 16
All six ports in the GB are bidirectional. Each consists bits wide. Otherwise the Port 2 pins continue to emit
of a latch (Special Function Registers PO through PS), the P2 SFR content.
an output driver, and an input buffer.
All the Port I, Port 3, and Port 4 pins, and five Port S
The output drivers of Ports 0 and 2, and the input buff- pins are multifunctional. They are not only port pins,
ers of Port 0, are used in accesses to external memory. but also serve the functions of various special features
In this application, Port 0 outputs the low byte of the as listed in Table 6.
Table 6. Alternate Port Functions
PORT /PIN ALTERNATE FUNCTION
PO.O/ ADO- MUltiplexed Byte of Address/Data for External Memory
PO.7 / AD7
Pl.O/T2 Timer 2 External Clock Input
Pl.l /T2EX Timer 2 Reload/Capture/Direction Control
P1.2 / C PCA External Clock Input
P1.3 / CEX3 PCA Module 0 Capture Input, Compare/PWM Output
P1.4/ CEX4 PCA Module 1 Capture Input, Compare/PWM Output
Pl.S / CEXS PCA Module 2 Capture Input, Compare/PWM Output
P1.6 / CEX6 PCA Module 3 Capture Input, Compare/PWM Output
P1.7 / CEX7 PCA Module 4 Capture Input, Compare/PWM Output
P2.0/ A8- High Byte of Address for External Memory
P2.7 / AIS
P3.0/RxD Serial Port Input
P3.1/TxD Serial Port Output
P3.2/INTO External Interrupt
P3.3 / INTl External Interrupt
P3,4/TO Timer 0 External Clock Input
P3.S /Tl Timer I External Clock Input
P3.6/WR Write Strobe for External Memory
P3.7/RD Read Strobe for External Memory
P4.0 / SEPCLK Clock Source for Serial Expansion Port
P4.1 / SEPDAT Data I/O for the Serial Expansion Port
P4.2 / Cl PCAI External Clock Input
P4.3/CIEX3 PCA I Module 0 Capture Input, Compare/PWM Output
P4,4/ CIEX4 PCA 1 Module 1 Capture Input, Compare/PWM Output
P4.S / CIEXS PCAI Module 2 Capture Input, ComparelPWM Output
P4.6/CIEX6 PCAI Module 3 Capture Input, Compare/PWM Output
P4.7/CIEX7 PCAI Module 4 Capture Input, Compare/PWM Output
PS.O/- No Alternate Port Function
PS.l/- No Alternate Port Function
PS.2 / INT2 External Interrupt INT2
PS.3 / INn External Interrupt INT3
PS.4/INT4 External Interrupt INT4
PS.S /INTS External Interrupt INTS
PS.6/INT6 External Interrupt INT6
PS.7/- No Alternate Port Function
8-58
inter 8XC51GB HARDWARE DESCRIPTION
ADDR/DATA READ
VCC LATCH
INT. B:..:U:..:S~~-i
INT. B:"U:"S'---+-I WRITE
TO
WRITE LATCH
TO _---'T'----'
LATCH
READ
READ PIN
PIN 270691-7
270691-6 B. Port 5.0, 5.1, 5.7 Bit
A. PortO Bit
ADDR ALTERNATE
OUTPUT
CONTROL
READ FUNCTION
LATCH
INT. BUS
WRITE
TO
LATCH WRITE
TO
LATCH
270691-8
ALTERNATE
C. Port 2 Bit INPUT
FUNCTION
270691-9
D. Ports 1, 3, 4, 5 Bit
Figure 5. 8XC51GB Port Bit Latches and I/O Buffers
The alternate functions can only be activated if the cor- external memory accesses. During external memory ac-
responding bit latch in the port SFR contains a I. Oth- cesses, the P2 SFR remains unchanged, but the PO SFR
erwise the port pin is stuck at O. . gets Is written to it.'
Also shown in Figure 5 is that if a P3 (or PI, P4, or P5)
5.1 1/0 Configurations latch contains a I, then the output level is controlled by
the signal labeled "alternate output function." The ac-
Figure 5 shows a functional diagram of a typical bit tual pin level is always avaihible to the pin's alternate
latch and I/O buffer in each of the four ports. The bit input function, if any.
latch (one bit in the port's SFR) is represented as a
Type D flip-flop, which will clock in a value from the Ports I, 2, 3, 4, and 5 have internal pullups. Port 0 has
internal bus in response to a "write to latch" signal open drain outputs. Each I/O line can be independently
from the CPU. The Q output of the flip-flop is placed used as an input or an output (Ports 0 and 2 may not be
on the internal bus in response to a "read latch" signal used as general purpose I/O when being used as the
from the CPU. The level of the port pin itself is placed ADDR/DATA BUS). To be used as an input, the port
on the internal bus in response to a "read pin" signal bit latch must contain a I, which turns off the output
from the CPU. Some instructions that read a port acti- driver FET. Then for Ports 1 through 5, the pin is
vate the "read latch" signal, and others activate the pulled high by the internal pullup, but can be pulled
"read pin" signal. See the Read-Modify-Write Feature low by an external source.
section.
Port 0 differs in not having internal pullups. The pullup
As shown in Figure 5, the output drivers of Ports 0 and FET in the PO output driver (see Figure 2) is used only
2 are switchable to an internal' ADDR and ADDR/ when the Port is emitting Is during external memory
DATA bus by an internal CONTROL signal for use in
8-59
8XC51GB HARDWARE DESCRIPTION
accesses. Otherwise the pullup FET is off. Consequent- Notice that only ports 1 through 5 have Schmitt trigger
ly PO lines that are being used as output port lines are inputs. Port 0 does not.
open drain. Writing a I to the bit latch leaves both
output FETs off, so the pin floats. In that condition it
can be used as a high-impedance input. 5.3 Port Loading and Interfacing
Because Ports I through 5 have fixed internal pullups The output of Ports 1-5 can each drive 4 LS TTL
they are sometimes called "quasi-bidirectional" ports. inputs. These port pins can be driven by open-collector
When configured as inputs they pull high and will and open-drain outputs, but note that O-to-I transitions
source current (IlL, in the data sheets) when externally will not be fast. An input 0 turns off pullup pFET3,
pulled low. Port 0, on the other hand, is considered leaving only the very weak pullup pFET2 to drive the
"true" bidirectional, because when configured as an in- transition.
put it floats.
Port 0 output buffers can each drive 8 LS TTL inputs
For system flexibility, Ports 0 and 3 reset asynchro- in external bus mode. However, as port pins they re-
nously to a I, and Ports I, 2, 4, and 5 reset asynchro- quire external pullups to be able to drive any inputs.
nously to a O. If a 0 is subsequently written to a port
latch, it can be reconfigured as an input by writing a I
to it. 5.4 Read-Modiiy-Wriie feaiure
Some instructions that read a port read the latch and
5.2 Writing to a Port others read the pin. Which ones do which? Theinstruc-
tions that read the latch rather than the pin are the ones
In the execution of an instruction that changes the val- that read a value, possibly change it, and then rewrite it
ue in a port latch, the new value arrives at the latch to the latch. These are called "read-modify-write" in-
during S6P2 of the final cycle of the instruction. How- structions. The instructions listed below are read-modi-
ever, port latches are in fact sampled by their output fy-write instructions. When the destination operand isa
buffers only during phase I of any clock period. (Dur- port, or a port bit, these instructions read the latch
ing Phase 2 the output buffer holds the value it saw rather than the pin:
during the previous Phase I.) Consequently, the new
value in the port latch won't actually appear at the ANL (logical AND, e.g., ANL PI, A)
output pin until the next Phase I, which will be at SIPI ORL (logical OR, e.g., ORL P2, A)
of the next machine cycle. XRL (logical EX-OR, e.g., XRL P3, A)
JBC Gump if bit = 1 and clear bit, e.g.,
If the change requires a O-to-I transition in Ports 1-5, JBC Pl.l, LABEL)
an additional pullup is turned on during SIPI and SIP2 CPL (complement bit, e.g., CPL P3.0)
of the cycle in which the transition occurs. This is done INC (increment, e.g., INC P2)
to increase the transition speed. The extra pullup can DEC (decrement, e.g., DEC P2)
source about 100 times the normal pullup current. The DJNZ (decrement and jump if not zero,
internal pullups are field-effect transistors, not linear e.g., DJNZ P3, LABEL)
resistors. The pull-up arrangements are shown in Fig- MOY,PX.Y,C (move carry bit to bit Y of Port X)
ure 6.. CLRPX.Y (clear bit Y of Port X)
SETB PX.Y (set bit Y of Port X)
The pullup consists of three pFETs. Note that an
n-channel FET (nFET) is turned on when a logical I is It is not obvious that the last three instructions in this
applied to its gate, and is turned off when a logical 0 is list are read-modify-write instructions, but they are.
applied to its gate. A p-channel FET (pFET) is the They read the port byte, all 8 bits, modify the addressed
opposite: it is on when its gate sees a 0, and off when its bit, then write the new byte back to the latch.
gate sees a 1.
The reason that read-modify-writeinstructions are di-
pFET I in Figure 6 is the transistor that is turned on rected to the latch rather than the pin is to avoid a
for 2 oscillator periods after a O-to-I transition in the possible misinterpretation of the voltage level at the
port latch. A I at the port pin turns on pFET3 (a weak pin. For example, a port bit might be used to drive the
pull-up), through the inverter. This inverter and pFET base of a transistor. When a I is written to the bit, the
form a latch which hold thel. transistor is turned on. If the CPU then reads the same
port bit at the pin rather than the latch, it will read the
Note that if the pin is emitting a I, a negative glitch on base voltage of the transistor and interpret it as a O.
the pin from some external source can turn off pFET3, Reading the latch rather than the pin will return the
causing the pin to go into a float state. pFET2 is a very correct value of 1.
weak pullup which is on whenever the nFET is off, in
traditional CMOS style. It's only about 1/10 the
strength of pFET3. Its function is to restore a I to the
pin in the event the pin had a I and lost it to a glitch.
8-60
intJ 8XC51GB HARDWARE DESCRIPTION
VCC VCC VCC
6
FROM PORT
LATCH
INPUT 0 - - 0 <
DATA
READ
PORT PIN
270691-10
NOTE:
pFETl is turned on for 2 osc. periods after Q makes a 1-\0-0 transition. During this time, pFET1 also turns on pFET3
through the inverter to form a latch which holds the 1. pFET2 is also on.
Figure 6. Internal Pull up Configurations
5.5 Accessing External Memory buffers. Thus, in this application the Port 0 pins are not
open-drain outputs, and do not require external pull-
Accesses to extenial memory are of two types: accesses ups. Signal ALE (Address Latch Enable) should be
to external Program Memory and accesses to external used to capture the address byte into an external latch.
Data Memory. Accesses to external Program Memory The address byte is valid at the negative transition of
use signal PSEN (program store enable) as the read ALE. Then, in a write cycle, the data byte to be written
strobe. Accesses to external Data Memory use RD or appears on Port 0 just before WR is activated, and re-
WR (alternate functions ofP3.7 and P3.6) to strobe the mains there until after WR is deactivated. In a read
memory. cycle, the incoming byte is accepted at Port 0 just be-
fore the read strobe is deactivated.
Fetches from external Program Memory always use a
l6-bit address. Accesses to external Data Memory can During any access to external memory, the CPU writes
use either a 16-bit address (MOYX @DPTR) or an OFFH to the Port 0 latch (the Special Function Regis-
S-bit address (MOYX @Ri). ter), thus obliterating whatever information the Port 0
SFR may have been holding. Also, a MOY PO instruc-
Whenever a 16-bit address is used, the high byte of the tion must not take place during external memory ac-
address comes out on Port 2, where it is held for the cesses.
duration of the read or write cycle. Note that the Port 2
drivers use the strong pullups during the entire time External Program memory is accessed under two con-
that they are emitting address bits that are Is. This is ditions:
during the execution of a MOYX @DPTR instruction. 1. Whenever signal EA is active, or
During this time the Port 2 latch (the Special Function
2. Whenever the program counter (PC) contains a
Register) does not have to contain Is, and the contents
of the Port 2 SFR are not modified. If the external
memory cycle is not immediately followed by another
.
number that is larger than IFFFH (SK).
This requires that the ROMless versions have EA wired
external memory cycle, the undisturbed contents of the
to Yss to enable the lower SK program bytes to be
Port 2 SFR will reappear in the next cycle.
fetched from external memory.
If an S-bit address is being used (MOYX @Ri), the
When the CPU is, executing out of external Program
contents of the Port 2 SFR remain at the Port 2 pins
Memory, all S bitsi of Port 2 are dedicated to an output
throughout the external memory cycle. This will facili-
function and may IJ,ot be used for general purpose I/O.
tate paging.
During external prbgram fetched they output the high
byte of the Pc. During this time the Port 2 driver~ use
In any case, the low byte of the address is time-multi-
the strong pullups to'ernit:PC bi.ts that are Is.
plexed with the data byte on Port O. The ADDR/
DATA signal drives both FETs in the Port 0 output
8-61
inter 8XC51GB HARDWARE DESCRIPTION
6.0 TIMERS/COUNTERS select. Timer 2 has three modes of operation: Capture,
Auto-Reload, and baud rate generator.
The 8XC51GB has three 16-bit Timer/Counters: Tim-
er 0, Timer I, and Timer 2. Each consists of two 8-bit
registers, THx and TLx, for x 0, I, and 2. All three 6.1 Timer 0 and Timer 1
can be configured to operate either as timers or event
counters. The Timer or Counter function is selected by control
bits CIT in the Special Function Register TMOD (Ta-
In the Timer function, the TLx register is incremented ble 6). These two Timer/Counters have four operating
every machine cycle. Thus one can think of it as count- modes, which are selected by bit-pairs (MI, MO) in
ing machine cycles. Since a machine cycle consists of 12 TMOD. .
oscillator periods, the count rate is 1/12 of the oscilla-
tor frequency. Modes 0, I, and 2 are the same for both Timer/Coun-
ters. Mode 3 is different. The four operating modes are
In the Counter function, the register is incremented in described in the following text.
response to a I-to-O transition at its corresponding ex-
ternal input pin, TO, TI. or T2. In this function, the 6.1.1 MODE 0
external input is sampled during S5P2 of every machine
cycle. When the samples show a high in one cycle and a Either Timer 0 or Timer I in Mode 0 is an 8-bit Coun-
low in the next cycle, the count is incremented. The ter with a divide-by-32 prescaier. Figure 7 shows the
new count value appears in the register during S3PI of Mode 0 operation as it applies to Timer 1.
the cycle following the one in which the transition was
detected. Since it takes 2 machine cycles (24 oscillator In this mode, the Timer register is configured as a
periods) to recognize a I-to-O transition, the maximum 13-bit register. As the count rolls over from all Is to all
count rate is 1/24 of the oscillator frequency. There are Os, it sets the Timer interrupt flag TFI. The counted
no restrictions on the duty cycle of the external input input is enabled to the Timer when TRI = I and either
signal, but to ensure that a given level is sampled at GATE = 0 or INTI = 1. (Setting GATE = I allows
least once before it changes, it should be held for at the Timer to be controlled by external input INTi; to
least one full machine cycle. facilitate pulse width measurements). TRI and TFI are
control bits in SFR TCON (Table 8). GATE is in
In addition to the Timer or Counter selection, Timer 0 TMOD.
and Timer I have four operating modes from which to
Table 7. TMOD: Timer/Counter Mode Control Register
TMOD Reset Value = 0000 OOOOB
Address = 89H Not Bit Addressable
Bit 7 6 5 4 3 2 2 0
TMOD GATE CIT M1 MO GATE CIT M1 MO
TIMER 1 TIMER 0
GATE Gating control when set. Timer/Counter 0 or I is enabled only while INTO or INTi pin is high
and TRO or TRI control pin is set. When cleared Timer 0 or I is enabled whenever TRO or TRI
control bit is set.
CIT Timer or Counter Selector cleared for Timer operation (input from internal system clock). Set for
Counter operation (input from TO or Ti input pin).
M1 MO Operating Mode
o 0 8-bit Timer/Counter THx with TLx as 5-bit prescaler.
o 16-bit Timer/Counter THx and TLx are cascaded;
there is no prescaler.
o 8-bit auto-reload Timer/Counter THx holds a value
which is to be reloaded into TLx each time it
overflows.
(Timer 0) TLO is an 8-bit Timer/Counter controlled
by the standard Timer 0 control bits. THO is an 8-bit
timer only controlled by Timer 1 control bits.
(Timer 1) Timer/Counter stopped.
8-62
inter 8XC51GB HARDWARE DESCRIPTION
INTERRUPT
_____.-Jl cif" 1
T1 PIN -
GATE
270691-11
Figure 7. Timer/Counter 1 Mode 0: 13-Bit Counter
Table 8. TCON: Timer/Counter Control Register
TCON Reset Value = 0000 OOOOB
Address = 88H Bit Addressable
Bit Bit 7 6 5 4 3 2 1 o
Address TCON TF1 TR1 TFO TRO IE1 IT1 lEO ITO
Symbol Name and Significance
8F TF1 Timer 1 overflow Flag. Set by hardware on Timer/Counter overflow. Cleared
by hardware when processor vectors to interrupt routine.
8E TR1 Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter 1
on/off.
80 TFO Timer 0 overflow Flag. Set by hardware on Timer/Counter 0 overflow. Cleared
by hardware when processor vectors to interrupt routine.
8C TRO Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter 0
on/off.
8B IE1 Interrupt 1 Edge flag. Set by hardware when external interrupt 1 edge is
detected. Cleared when interrupt processed.
8A IT1 Interrupt 1 Type control bit. Set/cleared by software to specify falling
edge/low level triggered external interrupt 1.
89 lEO Interrupt 0 Edge flag. Set by hardware when external interrupt 0 edge is
detected. Cleared when interrupt processed.
88 ITO Interrupt 0 Type control bit. Set/cleared by software to specify falling
edge/low level triggered external interrupt O.
The 13-bit register consists of all bits of TH 1 and the 6.1.3 MODE 2
lower 5 bits of TL1. The upper 3 bits of TLl are inde-
terminate and should be ignored. Setting the run flag Mode 2 configures the Timer register as an 8-bit Coun-
(TR 1) does not clear the registers. ter (TLl) with automatic reload, as shown in Figure 8.
Overflow from TL1 not only sets TF1, but also reloads
Mode 0 operation is the same for Timer 0 as for Timer TLl with the contentsofTH1, which is preset by soft-,
1. Substitute TRO, TFO, and INTO for the correspond- ware. The reload leaves TH1 unchanged. Mode 2 oper-
ing Timer 1 signals in Figure 7. There are two different ation is the same for Timer/Counter O.
GATE bits, one for Timer 1 (TMOD.7) and one for
Timer 0 (TMOD.3).
6.1.4 MODE 3
6.1.2 MODE 1 Timer 1 in Mode 3 simply holds its count. The effect is
the same as setting TR1 = o.
Mode 1 is the same as Mode 0, except that the Timer
register uses all 16 bits.
8-63
inter 8XC51GB HARDWARE DESCRIPTION
Timer 0 in Mode 3 establishes TLO and THO has two 6.2 ~Timer 2
separate counters. The logic for Mode 3 on Timer 0 is
shown in Figure 9. TLO uses the Timer 0 control bits: Timer 2 is a 16-bit Timer/Counter which like Timers 0
CIT, GATE, TRO, INTO, and TFO. THO is locked into and I, can operate either as a timer or as an event
a timer function (counting machine cycles) and takes counter. This is selected by bit CIT2 in the Special
over the use ofTRI and TFI from Timer I. Thus THO Function Register nCON (Table 10). It has three op-
now controls the Timer 1 interru pI. erating modes: capture, auto-reload, and baud rategen-
erator, which are selected by bits in T2CON (Table 9)
Mode 3 is provided for applications requiring an extra as shown in Table 10.
8-bit timer or counter. With Timer 0 in Mode 3, and
8XC51GB can look like it has fnur Timer/Counters.
When Timer 0 is in Mode 3, Timer I can be turned on
6.2.1 CAPTURE MODE
and off by switching it out of and into its own Mode 3, In the Capture Mode there are two options which are
or can still be used by the serial port as a baud rate selected by bit EXEN2 in T2CON. If EXEN2 = 0,
generator, or in fact, in any application not requiring an then Timer 2 is a 16-bit timer or counter which upon
interrupt. overflowing set~ bit TF2, the Timer 2 overflow bit,
ciT = 0
INTERRUPT
______--'1 clf =1
T1 PIN -
TR1-----i
GATE
iNrQPIN
270691-12
Figure 8. Timer/Counter 1 Mode 2: a-Bit Auto-Reload
osc ~B- 1/1210SC
1I1210SC - - - - - - - ,
1------ INTERRUPT
TO P I N - - - - - -....
CONTROL
GATE
1/1210s c ------------tI-<f.! I
_ _ _ _ _ _ _.... CONTROL
·1 (::~) H . _T_F_l....l---INTERRUPT
TRl -
270691-13
Figure 9. Timer/Counter 0 Mode 3: Two 8-Blt Counters
8-64
inter 8XC51GB HARDWARE DESCRIPTION
which can be used to generate an interrupt. If Table 9. Timer 2 Operating Modes
EXEN2 = I, then Timer 2 still does the above, but
with the added feature that a I-to-O transition at exter- RCLK + TCLK CP/RL2 TR2 Mode
nal input T2EX causes the current value in the Timer 2 0 0 1 16-Bit Auto Reload
registers, TL2 and TH2, to be captured into registers 0 1 1 16-Bit Capture
RCAP2L an RCAP2H, respectively. In addition, the
1 X 1 Baud Rate Generator
transition at T2EX causes bit EXF2 in T2CON to be
set, and EXF2, like TF2, can generate an interrupt. The X X 0 (Off)
Capture Mode is illustrated in Figure 10.
TIMER 2
INTERRUPT
EXEN2
270691-14
Figure 10. Timer 2 in Capture Mode
8-65
intJ 8XC51GB HARDWARE DESCRIPTION
Table 10. T2CON: Timer/Counter 2 Control Register
T2CON Reset Value = 0000 OOOOB
Address = OCBH Bit Addressable
Bit Bit 7 6 5 4 3 2 1 o
Address T2CON TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2
Symbol Name and SIgnificance
CF TF2 Timer 2 overflow flag set by a Timer 2 overflow and must be cle~red by software. TF2
will not be set when either RCLK = 1 or TCLK = 1.
CE EXF2 Timer 2 external flag set when either a capture or reload is caused by a negative
transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, E)(F2 = 1 will
cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by
software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).
CD RCLK Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for
its receive clock in Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for
the receive clock.
CC TCLK Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for
its transmit clock in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for
the transmit clock.
CB EXEN2 Timer 2 external enable flag. When set, allows a capture oneload to occur as a result
of a negative transition on T2EX if Timer 2 is not being used to clock the serial port.
EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
CA TR2 Start/stop control for Timer 2. A logic 1 starts the timer.
C9 C/T2 Timer or counter select. (Timer 2).
CIT = 0 Internal timer (OSC/12 or OSC/2 baud rate generator mode).
C/T2 = 1: External event counter (falling edge triggered).
C8 CP/RL2 Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if
EXEN2 = 1. When cleared, auto-reloads will occur all either with Timer 2 overflows or
negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1,
this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
6.2.2 BAUD RATE GENERATOR MODE with the added feature that a I-to-O transition at exter-
nal input T2EX will also trigger the 16-bit reload and
The baud rate generator mode is selected by RCLK = set EXF2. The auto-reload mode is illustrated in Figure
I and/or TCLK = 1. It will be described in conjunc- 11.
tion with the serial port.
6.2.4 UP/DOWN COUNTER MODE
6.2.3 AUTO-RELOAD MODE
Timer 2 can be programmed to count up or down when
In the auto-reload mode there are again two options, configured in its 16-bit auto-reload mode.
which are selected by bit EXEN2 in T2CON. If
EXEN2 = 0, then when Timer 2 rolls over it not only The Special Function Register T2MOD contains a bit
sets TF2 but also causes the Timer 2 registers to be named DCEN (Down Counter Enable). T2MOD is
reloaded with the 16-bit value in registers RCAP2L shown in Table II. When this bit is clear (D), the Timer
and RCAP2H, which are preset by software. If 2 Auto-Reload Mode is in the Auto-Reload Mode. Fig-
EXEN2 = I, then Timer 2 still does the above, but ure. II shows Timer 2 in Auto-Reload Mode with
DCEN = O.
8-66
inter 8XC51GB HARDWARE DESCRIPTION
T2 PIN - - - - - - - - '
TIMER 2
INTERRUPT
T2EX PIN ------I~I
EXEN2
270691-15
Figure 11. Timer 2 Auto Reload Mode (DCEN = 0)
Table 11. T2MOD: Timer 2 Mode Control Register
T2MOD Address = OC9H Reset Value = XXXX XXXOB
Bft 7 6 5 4 3 2 o
DCEN
Symbol Function
Not implemented, reserved for future use.'
DCEN When set, this bit allows Timer 2 to be configured as an up/down counter.
'User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke
new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value
read from a reserved bit is indeterminate.
8-67
inter 8XC51GB HARDWARE DESCRIPTION
When DCEN is set (1), the Timer 2 Auto-Reload Mode ters can be programmed to count in response to one of
takes the form shown in Figure 12. The T2EX pin now several clock sources. Each compare/capture module
controls the direction of count. A logic 1 at T2EX can be programmed to one of several modes: 16-bit cap-
makes Timer 2 count up. A logie a at T2EX makes ture, 16-bit software timer, high speed output, and 8-bit
Timer 2 count down. Also, the EXF2 bit toggles every pulse width modulator.
time Timer 2 overflows or underflows. In this operating
mode, the EXF2 bit does not flag an interrupt. The two PCAs are functionally the same except for
some differences in the PCA timers and control regis-
ters. The PCA timer has four input sources while the
7.0 PROGRAMMABLE COUNTER! PCAI has seven. The PCA and PCAI modules have
TIMER ARRAYS (PCAs) the same modes except PCA Module 4 has a Watchdog
Timer mode.
The 8XC5lGB implements two complete Programma-
ble .Counter/Timer Arrays, PCA and PCAI. The After an overview of the PCA hardware, the PCA Tim-
a
PCAs (PCA and PCAl) each consist of 16-bit coun- er/Counter and the PCAI Timer/Counter are dis-
ter and five 16-bit compare/capture modules as shown cussed and then the Compare/Capture registers will be
in Figure 13. The 16-bit timers provide a common ref- discussed with a section on each of the possible module
erence to each of their five modules. Each of the coun- modes.
(UP COUNTING OVERFLOW VALUE)
T20----.....
1 =UP
T2EX D----....."O.:.=~D:-;O:,:,W",N,.---4
270691-16
Figure 12. Timer 2 Auto Reload Mode when DCEN = 1
-16 BITS EACH- +-16 BITS EACH-
MODULE 0 Pl.3 P4.3
MODULE 1 Pl.4 P4.4
- 1 6 BITS EACH--
PCA TIMER/COUNTER MODULE 2 Pl.5 PCA TIMER/COUNTER P4.5
MODULE 3 Pl.6 P4.6
PCA PCAI
MODULE 4 Pl.7 P4.7
270691-17
Figure 13. Programmable Counter Arrays
8-68
intJ 8XC51GB HARDWARE DESCRIPTION
7.1 Overview of the PCA and PCA 1 CR in the SFR CCON (Table 13). The PCA timer can
Hardware be programmed to count one of four inputs as deter-
mined by the value of bits CPS I and CPSO in SFR
The PCAs are accessed and controlled through several C!'40D (Table 12). The following four signals can be
Special Function Registers. Each PCA has a counter selected as inputs to the PCA timer (where Fosc is the
with mode and control registers, and 5 modules with 8XC51GB oscillator frequency):
mode registers implemented in the SFRs. In addition, • Fosc/12: The Counter increments once per machine
the compare/capture modules and the PCA counters cycle.
each have a pin available for external I/O. The SFRs
• Fosc/4: With a 12 MHz crystal, the counter incre-
and I/O pins for the PCAs are shown below.
ments once every 333 ns.
• Timer 0 overflow: The counter is incremented
7.2 PCA 16-Bit Timer/Counters whenever Timer 0 overflows. This mode allows a
. programmable input frequency to the PCA.
The programmable 16-bit timer/counter of the PCA is • External input on Pl.21C pin: The counter is incre-
the only timer which can serve the PCA. The PCA mented on every I-to-O transition detected on the C
timer is started or stopped by setting or clearing bit pin. Input frequencies are limited to Fosc/8.
PCA Components SFRs Mode Reg.s External 1/0 Pin
16-Bit Counter CH/CL CMOD/CCON P1.2/C
16-Bit Module 0 CCAPOH/CCAPOL CCAPMO P1.3/CEXO
16-Bit Module 1 CCAP1H/CCAP1L CCAPM1 P1.4/CEX1
16-Bit Module 2 CCAP2H/CCAP2L CCAPM2 P1.5/CEX2
16-Bit Module 3 CCAP3H/CCAP3L CCAPM3 P1.6/CEX3
16-Bit Module 4 CCAP4H/CCAP4L CCAPM4 P1.7/CEX4
PCA 1 Components SFRs Mode Reg.s External 1/0 Pin
16-Bit Counter CH1/CL1 C1MOD/C1CON P4.2/C1
16-Bit Module 0 C1CAPOH/C1CAPOL C1CAPMO P4.3/C1EXO
16-Bit Module 1 C1CAP1H/C1CAP1L C1CAPM1 P4.4/C1EX1
16-Bit Module 2 C1CAP2H/C1CAP2L C1CAPM2 P4.5/C1EX2
16-Bit Module 3 C1CAP3H/C1CAP3L C1CAPM3 P4.6/C1EX3
16-Bit Module 4 C1CAP4H/C1CAP4L C1CAPM4 P4.7/C1CEX4
Table 12. CMOD: PCA Counter Mode Register
CMOD Address = OD9H . Reset Value = OOXX XOOOB
Not Bit Addressable
Bit 7 6 5 4 3 2 1 o
CMOD CIDL WDTE CPS1 CPSO ECF
Symbol Function
CIDL Counter Idle Control: CIDL = 0 programs PCA and PCA1 Counters to continue function
during Idle mode. CIDL = 1 programs them to be gated off during Idle.
WDTE Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4.
WDTE = 1 enables it.
Not implemented, reserved for future use. *
CPS1 PCA Count Pulse Select bit 1.
CPSO PCA Count Pulse Select bit O.
CPS1 CPSO Selected PCA Input
o 0 Internal clock, Fosc/12
o 1 Internal clock, Fosc/4
1 0 Timer 0 overflow
1 1 External clock at C/P1.2 pin (max. rate = Fosc/8)
ECF PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an
interrupt. ECF = 0 disables that function of CF.
'User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke
new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value
read from a reserved bit is indeterminate.
8-69
8XC51GB HARDWARE DESCRIPTION
When the PCA timer/counter rolls over, the counter The 16-bit PCA and PCAI timer/counters can both be
flag CP in register CCON (Table 12) is set. This flag programmed to either run or pause when the CPU is in
can cause an interrupt if bit ECF in register CMOD Idle mode by clearing or setting bit CrDL in register
(Table 12) is set to enable an interrupt. Also, the PCA CMOD. CMODalso contains bit WDTE which en-
interrupt enable bit ¥-C in register IE must be set to ables the PCA Watchdog mode on Module 4.
enable the PCA interrupt. CCON also contains inter-
rupt flags CCPn from each of the live PCA modules.
Table 13. CCON: PCA Counter Control Register
CCON Address = OD8H Reset Value = OOXO OOOOB
Bit Addressable
Bit Bit 7 6 5 4 3 2 1 o
Address CCON CF CR CCF4 CCF3 CCF2 CCF1 CCFO
Symbol Function
DF CF PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF
flags an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or
software but can only be cleared by software.
DE CR PCA Counter Run control bit. Set by software to turn the PCA counter on. Clear
by software to turn the PCA counter off.
Not implemented, reserved for future use.'
DC CCF4 PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs.
Must be cleared by software.
DB CCF3 PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs.
Must be cleared by software.
DA CCF2 PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs.
Must be cleared by software.
D9 CCF1 PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs.
Must be cleared by software.
D8 CCFO PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs.
Must be cleared by software.
'User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke
new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value
read from a reserved bit is indeterminate.
8-70
intJ 8XC51GBHARDWARE DESCRIPTION
7.3 PCA116-Bit Timer/Counter • External input on Pl.2IC pin: The counter is incre-
mented on every I-to-O transition detected on the C
The programmable 16-bit timer/counter of PC Al is the pin. Input frequencies are limited to Fosc/S.
only timer which can serve the PCAls. The PCAI tim- • Timer 1 overflow: The counter is incremented
er is started or stopped by setting or clearing bit CR 1 in whenever Timer 1 overflows. This mode allows a
the SFR CICON (Table 15). The PCAI timer can be programmable input frequency to the PCAL
programmed to count one of seven inputs as deter-
• External input on P4.2/Cl pin: The counter is in-
mined by the value of bits CIPS2, CIPSI and CIPSO in
SFR CIMOD (Table 14). The following seven signals cremented on every I-to-O transition detected on the
can be selected as inputs to the PCAI timer (where Cl pin. Input frequencies are limited to Fosc/S.
Fosc is the oscillator frequency): • External input on PLO/T2pin: The counter is incre-
• Fosc/12: The Counter increments once per machine mented on every I-to-O transition detected on the T2
cycle. pin. Input frequencies are limited to Fosc/S.
• Fosc/4: With a 12 MHz crystal, the counter incre-
ments once every 333 ns.
e Timer 0 overflow: The counter is incremented
whenever Timer 0 overflows. This mode allows a
programmable input frequency to the PCA.
Table 14. C1MOD: PCA1 Mode Register
C1MOD Reset Value = XXXX OOOOB
Address = 9FH Not Bit Addressable
Bit 7 6 5 4 3 2 1 o
C1MOD C1PS2 C1PS1 C1PSO
ECF1
Symbol Function
Not implemented, reserved for future use. •
C1PS2 PCA 1 Count Pulse Select bit 2.
C1PS1 PCA 1 Count Pulse Select bit 1.
C1PSO PCA 1 Count Pulse Select bit O.
C1PS2 C1PS1 C1PSO Selected PCA1input
o 0 0 Internal clock, Fosc/12
o 0 1 Internal clock, Fosc/4
o 1 0 Timer 0 overflow
o 1 1 External clock on C/P1.2 pin (max. rate = Fosc/B)
1 0 0 Same as 000, not to be used.
o External clock on T2/P1.0 pin (max. rate = Fosc/B)
1 0 Timer 1 overflow
1 External clock on C1 IP4.2 pin (max. rate = Fosc/B)
ECF1 PCA 1 Enable Counter Overflow interrupt. ECF1 = 1 enables CF1 bit in C1 CON to generate
an interrupt. ECF1 = 0 disables that function.
'User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke
new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value
read from a reserved bit is indeterminate.
B-71
8XC51GB HARDWARE DESCRIPTION
If one of the four inputs sources of the PCA is also When the PCAI timer/counter rolls over, the counter
chosen for the PCAI, then they can be programmed to flag CFI in register CICON (Table 15) is set. This flag
run off the same timing source. They can run indepen- can cause an interrupt if bit ECFI in register CIMOD
dently or they can be enabled simultaneously by setting (Table 14) is set to enable an interrupt. Also, the PCA
bit CRE of the CICON register. When CRE is set, the interrupt enable bit ECI in register lEA must be set to
PCAI counter is enabled whenever both the CR and enable the PCAI interrupt. CICON also contains inter-
CRI bits are set, and is disabled when anyone of them rupt flags CICFn from each of the five PCAI modules.
is cleared. To start or stop the two PCA and PCAI
counters simultaneously with the CRE bit high, set the The 16-bit PCA and PCAI timer/counters can both be
CR 1 bit first, and then 'start or stop both counters by programmed to either run or pause when the CPU is in
setting or clearing the CR bit. Idle mode by clearing or setting bit CIDL in register
CMOD.
Table 15. C1CON: PCA1 Counter Control Register
C1CON Reset Value = 0000 OOOOB
Address = OE8H Bit Addressable
Bit Bit 7 6 5 4 3 2 1 a
Address C1CON CF1 CR1 CRE C1CF4 C1CF3 C1CF2 C1CF1 C1CFO
Symbol ,Function
EF CF1 PCA 1 Counter Overflow flag. Set by hardware when the counter rolls over. CF1
flags an interrupt if bit ECF1 in C1 MOD is set. CF1 may be set by either hardware
or software but can only be cleared by software.
EE CR1 PCA 1 Counter Run control bit. Set by software to turn the PCA 1 counter on. Clear
by software to turn the PCA 1 counter off.
ED CRE CR Enable bit. When high, PCA 1 counter incrementing is enabled when both CR.
and CR1 are high and is disabled when anyone of them is low. When CRE is low,
CR has no control over PCA 1 counter and the counter is controlled only by CR 1.
EC C1CF4 PCA 1 Module 4 interrupt flag. Set by hardware when a match or capture occurs.
Must be cleared by software.
EB C1CF3 PCA 1 Module 3 interrupt flag. Set by hardware when a match or capture occurs.
Must be cleared by software.
EA C1CF2 PCA 1 Module 2 interrupt flag. Set by hardware when a match or capture occurs.
Must be cleared by software.
E9 C1CF1 PCA 1 Module 1 interrupt flag. Set by hardware when a match or capture occurs.
Must be cleared by software.
E8 C1CFO a
PCA 1 Module interrupt flag. Set by hardware when a match or capture occurs.
Must be cleared by software.
8-72
8XC51GB HARDWARE DESCRIPTION
7.4 Capture/Compare Modules flag CCFn bit in register CCON is set when the module
executes its function. If the ECCFn in register
Each of ten 16-bit compare/capture modules, five for CCAPMn is set then the CCFn flag is enabled to cause
PCA and five for PCAI, can be programmed to one of an interrupt.
the following six modes:
The mode of each of the five PCAI modules is deter-
16-bit capture, positive edge activated. mined by the settings of each Compare/Capture Mode
16-bit capture, negative edge activated. register, CICAPMn, n = 0 - 4. The bits EICOMn,
16-bit capture, both positive and negative edge CAPIPn, CAPINn, MATln, TOGln, and PWMln in
activated. each CICAPMn (Table 18) register define that mod-
16-bit software timer. ule's functions.
16-bit high speed output.
S-bit Pulse Width Modulator (PWM). When any of the compare/capture modules are pro-
grammed to the capture mode or the 16-bit Timer/
In addition, Compare/Capture module 4 of PCA can High speed output mode, the corresponding interrupt
be used as a Watchdog Timer. flag CICFn bit in register CICON is set when the mod-
ule executes its function. If the EICCFn in register
The mode of each of the five PCA modules is deter- CICAPMn is set then theCICFn flag is enabled to
mined by the settings of each Compare/Capture Mode cause an interrupt.
register, CCAPMn, n = 0 - 4. The bits ECOMn,
CAPPn, CAPNn, MATn, TOGn, and PWMn in each There are 6 modes of operation for each of the 5 PCA
CCAPMn (Table 17) register define that module's modules. Shown in Table 16 are the combinations of
functions. bits in the CCAPMn register that are valid and have a
defined function. The results are the same for PCAI
When any of the compare/capture modules are pro- modules using the corresponding bits in CICAPMn.
grammed to the capture mode or the 16-bit Timer/ Invalid combinations will produce undefined results.
High speed output mode, the corresponding interrupt
Table 16. PCA Module Modes (same for PCA1)
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn Module Function
0 0 0 0 0 0 0 0 No Operation
16-Bit Capture by a Positive-Edge
0 X 1 0 0 0 0 X
Trigger on CEXn
16-Bit Capture by a Negative-Edge
0 X 0 1 0 0 0 X
Trigger on CEXn
16-Bit Capture by a Transition
0 X 1 1 0 0 0 X
on CEXn
0 1 0 0 1 0 0 X 16-Bit Software Timer
0 1 0 0 1 1 0 X High Speed Output
0 1 0 0 0 0 1 0 8-Bit PWM
x= Don't Care
8-73
intJ 8XC51GB HARDWARE DESCRIPTION
The following are descriptions of the PCA module PCA modes using the corresponding PCAI registers
modes: Capture Mode, Software Timer Mode, High and pins. The Watchdog Timer mode is only available
Speed Output Mode, and Pulse Width Modulator on PCA Module 4.
Mode. The PCAI module modes are identical to the
Table 17. CCAPMn: PCA Modules Compare/Capture Registers
CCAPMn Address CCAPMOO OAH Reset Value = XOOO OOOOB
CCAPM1 OOBH Not Bit Addressable
CCAPM2 OOCH
CCAPM3 OOOH
CCAPM4 OOEH
Bit 7 6 5 4 3 2 o
CCAPMn ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
Symbol Function
Not implemented, reserved for future use.'
ECOMn Enable Comparator. ECOMn = 1 enables the comparator function. This bit is automatically
cleared by any write to the CCAPnL register, and automatically set by any write to the
CCAPnH register. This prevents unintended matches from occurring during writes to the 16-
bit Compare/Capture register.
CAPPn Capture Positive. Positive edge capture enable. When CAPPn = 1, a positive transition at
the CEXn pin triggers a 16-bit capture from the PCA counter to this module's Compare/
Capture register.
CAPNn Capture Negative. Negative edge capture enable. When CAPNn = 1, a negative transition
at the CEXn pin triggers a 16-bit capture from the PCA counter to this modules Compare/
Capture register.
MATn Match. When MATn = 1, a match of the PCA Counter with this module's Compare/Capture
register causes the CCFn bit in CCON to be set, flagging an interrupt.
TOGn Toggle. When TOGn = 1, a match of the PCA Counter with this module's Compare/
Capture register causes the CEXn pin to toggle.
PWMn Pulse Width Modulation Mode. When PWMn = 1, CEXn is driven high when the low byte of
the PCA Counter (CL) matches the low byte of this module's Compare/Capture register
(CCAPnL). When CL rolls over to OOH, the CEXn pin is driven low and CCAPnL is updated
with the value in CCAPnH. This enables the CEXn pin to be used as a pulse width
modulated output. Software varies the pulse width by writing to CCAPnH.
ECCFn Enable CCF interrupt. Enables Compare/Capture Flag CCFn in the CCON register to
generate an interrupt.
·User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke
new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value
read from a reserved bit is indeterminate.
8-74
inter 8XC51GB HARDWARE DESCRIPTION
7.5 16-Bit Capture Mode the values in CL and CH at the time a transition was
detected on the CEXn pin. The event flag CCFn is set
Setting CAPPn and/or CAPNn puts PCA Compare/ and causes an interrupt if bit ECCFn is set.
Capture module n into Input Capture mode, as shown
for a PCA module in Figure 14. The external input pins
CEXO through CEX4 are sampled for a transition. 7.6 16-Bit Software Timer Mode
When a valid transition is detected for the current
mode of operation (rising edge, falling edge, or either Setting bit ECOMn in the Compare/Capture Mode
edge), CL is transferred into the CCAPnL register, and Register (CCAPMn) enables the Comparator function
CH is transferred into CCAPnH. The resulting value in as shown in Figure 15 for a PCA module. The Compar-
the Capture Registers, CCAPnL and CCAPnH,reflect ator compares a 16-bit value stored in the compare/
capture register with the count value of the counter
Table 18. C1CAPMn: PCA 1 Modules Compare/Capture Registers
C1CAPMn Address C1CAPMO 9AH Reset Value = XOOO OOOOB
C1CAPM1 9BH Not Bit Addressable
C1CAPM2 9CH
C1CAPM3 90H
C1CAPM4 9EH
Bit 7 6 5 4 3 2 o
C1CAPMn E1COMn CAP1Pn CAP1Nn MAT1n TOG1n PWM1n E1CCFn
Symbol Function
Not implemented, reserved for future use. *
E1 COMn Enable Comparator.
CAP1 Pn Capture Positive.
CAP1 Nn Capture Negative.
MAT1 n Match.
TOG1 N Toggle.
PWM1 n Pulse Width Modulation Mode.
E1 CCFn Enable CCF interrupt.
Refer to the CCAPMn register for details on each of the corresponding bits.
• User software should not write 1s to reserved "bits. These bits may be used in future 8051 family products to invoke
new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value
read from a reserved bit is indeterminate.
PCA TIMER / COUNTER VALUE
CEXn
CCAPMn REGISTER
270691-18
Figure 14. PCA 16·Bit Capture Mode
8-75
inter 8XC51GB HARDWARE DESCRIPTION
module. When they are equal, a match signal is gener- value of its Compare registers three times per machine
ated which can set the status hit CCFn in the PCA cycle. When a match occurs, if bit TOGn is set, the
Control register CCON and/or toggle the correspond- module reverses the logic level of its I/O pin, and/or
ing CEXn pin. can generate an interrupt as shown in Figure 15. When
the PCA module is configured in this manner as a High
Bit ECOMn is set by software and is initially cleared Speed Output, the user, by setting or clearing the pin in
during reset. It also gets cleared when a write to software, can select whether the module's output pin
CCAPnL register happens and is sct if CCAPnH is will change from a logical 0 to a logical I or vice versa.
written to. This feature prevents actions until the com-
plete 16-bit value is loaded into the CCAPn register if
the low value is written to the 16-hit 'register first. 7.8 Pulse Width Modulator Mode
When the MATn (Match) bit is set in the Compare/ Any or all of the five modules of the PCA can be pro-
Capture Mode Register, the corresponding module in grammed to be a pulse Width Modulator as shown in
the PCA is configured as a 16-bit timer. When the val- Figure 16 for a PCA module. In this mode, the PWM
ue in the 16-bit Compare/Capture register is equal to output can be used to convert digital data to an analog
the 16-bit value on the Count Bus, the hardware sets signal by simple external circuitry. The frequency of the
the CCFn flag. This bit flags an interrupt if ECCFn is PWM depends on which of the clock sources is selected
also set. for the PCA Timer. With a 12 MHz crystal the maxi-
mum frequency of the output waveform of the PWM is
11.7 KHz. The duty cycle of the waveform is controlled
7.7 High Speed Output Mode by the contents of an 8-bit register (CCAPnH) that can
be programmed to be any integer from 0 to 255.
When programmed as a timer, the PCA module com-
pares the contents of the 16-bit timer with the preset
WOlE
16
WRITE TO
CCAPnl
RESET---L.,
WRITE TO
CCAPnH
270691-19
n ~ 0, 1,2,3 or 4
x ~ Don't Care
Figure 15. PCA 16·Bit Comparator Mode
8-76
inter 8XC51GB HARDWARE DESCRIPTION
CL MADE
FF TO 00 - - - o J
TRANSITION
....._....r....L.-_--.
CCAPnH
WRITE TO _ _---.
CCAPnH
"1"
270691-20
n = 0, 1, 2, 3 or 4
x = Don't C,are
Figure 16. peA a-bit PWM Mode
7.9 PCA Watchdog Timer Mode The GB also has a dedicated Watchdog Timer. The
PCA Watchdog timer need only be used if a program-
A Watchdog Timer is a circuit that automatically in- mable time is needed for the watchdog function.
vokes a reset unless the system being watched sends
regular hold-off signals to the Watchdog. These circuits
are used in applications that are subject to electrical 8.0 SERIAL INTERFACE
noise, power glitches, electrostatic discharges, etc., or
where high reliability is required with hands-off opera- The serial port is full duplex, meaning it can transmit
tion. and receive simultaneously. It is also receive-buffered,
meaning it can commence reception ofa second byte
In this mode, every time the count in the PCA counter before a previously received byte has been read from
module matches the value stored in compare/capture the receive register. (However, if the first byte still
module 4, lm internal reset is generated. The bit that hasn't been read by the time reception of the second
selects this mode is WDTE in the CMOD register. byte is complete, one of the bytes will be lost). The
PCA Compare/Capture module 4 should be set up to serial port receive and transmit registers are both ac-
be a 16-bit timer or a High Speed Output in the Watch- cessed at Special Function Register SBUF. Writing to
dog Timer mode. SBUF loads the transmit register, and reading SBUF
accesses a physically separate receive register.
To hold off the reset, the user's software can:
The serial port can operate in 4 modes:
• Continually reset the PCA 16-bit timer value to a
lower value than the reset value in module 4.
Mode 0: Serial data enters and exits through RXD.
• Clear the WDTE bit when a match is about to occur TXD outputs the shift clock. 8 bits are transmitted/re-
and then set the WDTE bit just after the match ceived: 8 data bits (LSB first). The baud rate is fixed at
condition (temporarily disabing the feature). 1/12 of oscillator frequency.
or
• Continually change the CCAP4H and CCAP4L val- Mode 1: 10 bits are transmitted (through TXD) or re-
ue to one that is "far" from a match value. ceived (through RXD): a start bit (0), 8 data bits (LSB
Finally, the Watchdog Timer can be used to program a
reset by allowing a match to occur.
8-77
8XC51GB HARDWARE DESCRIPTION
first), and a stop bit (I). On receive, the stop bit goes The Given Address is specified by the contents of two
into RB8 in /Special Function Register SCaN. The new SFRs: SADDR and SADEN. The 8XC51GBs in-
baud rate is variable. dividual address is defined in SADDR. SADEN is a
mask byte that defines don't cares in SADDR to form
Mode 2: II bits are transmitted through (TXD) or re- the Given Address. For example,
ceived (through RXD): a start bit (0), 8 data bits (LSB
first), a programmable 9th data bit, and a stop bit (I). SADDR = 01010110
On Transmit, the 9th data bit (TB8 in SCaN) can be SADEN = 11111100
assigned the value of 0 or I. Or, for example, the parity
bit (P, in the PSW) could be moved into TB8. On re- specify the Given Address to be OlOIOIXX.
ceive, the 9th data bit goes into RB8 in Special Func-
tion Register SCaN, while the stop bit is ignored. The The Broadcast Addressis formed from the logical OR
baud rate is programmable to either 1/32 or 1/64 the of SADDR and SADEN. Zeros in the logical OR are
oscillator frequency. don't cares. For example, the values above for SADDR
and SADEN define the broadcast address to be
Mode 3: 11 bits are transmitted (through TXD) or re- III t IIIX.
ceived (through RXD): a start bit (0), 8 data bits (LSB
first), a programmable 9th data bit and a stop bit (1). In Automatic Address Recognition allows a host proces-
fact, Mode 3 is the same as Mode 2 in all respects sor to establish communication with an addressed
except the baud rate. The baud rate in Mode 3 is vari- slave, without all the other slave controllers having to
able. respond to the transmission. The addressed slave then
clears its SM2 bit to enable reception of data bytes (9th
In all four modes, transmission is initiated by any in- data bit = 0) from the host.
struction that uses SBUF as a destination register. Re-
ception is initiated in Mode 0 by the condition RI = 0 The Given and Broadcast addresses allow each micro-
and REN = I. Reception is initiated in the other controller to have its own (Given) address and a com-
modes by the incoming start bit if REN = 1. mon (Broadcast) address. A "host" on the serial chan-
nel can selectively address single 8XC51GBs using the
Given Address or all 8XC51GBs using the .Broadcast
8.1 Automatic Address Recognition Address. .
Automatic Address Recognition is useful in multi-proc- On reset, the SADDR and SADEN registers are initial-
essor applications in which the CPUs communicate ized to OOR. This defines the Given and Broadcast ad-
through the serial channel. Using this feature,the dresses to be XXXXXXXX (all don't-cares) for back-
8XC5JGBs Serial Port refrains from interrupting the wards compatibility with the 8051 family.
CPU unless it receives its own address. Automatic Ad-
dress Recognition is enabled by setting the SM2 bit in
SCON. 8.2 Framing Error Detection
Normally the Serial Port would be configured into ei- Another new feature of the Serial Port is Framing Er-
ther of the 9-bit modes (modes 2 and 3). In these ror Detection. This allows the receiving controller to
modes, if SM2 is set, the Receive Interrupt flag RI is check the stop bit in modes I, 2, or 3. A missing stop
not activated unless the received byte is an address byte bit causes a Framing Error bit, FE, to be set. The FE
(9th data bit = I), and the address corresponds toei- bit can then be checked in software immediately after
ther a Given Address or a Broadcast Address. each reception to detect the lack of a valid stop bit. A
missing stop bit can be caused, for example, by noise on
The feature works the same way in the 8-bit mode the serial lines, or by two CPUs trying to transmit at
(mode I) as in the 9-bit modes, except that the stop bit the same time. The FE bit, once set, must be cleared in
takes the place of the 9th data bit. That is, if SM2 is set, software. A valid stop bit does not cause the FE bit to
Ri is not activated unless the received byte agrees with be cleared.
either the Given or Broadcast address and is terminated
by a valid stop bit. The FE bit resides in SCaN, and has the same bit ad-
dress as the SMO bit. A new control bit in the PCON
register determines if access to the SMO/FE bit address
are to SMO or to FE. The new control bit in PCON is
8-78
8XC51GB HARDWARE DESCRIPTION
Table 19. SCON: Serial Port Control Register
SCON Reset Value = 0000 OOOOB
Address = 98H Bit Addressable
Bit Bit 7 6 5 4 3 2 1 o (SMODO = 0)'
Address SCON SMO SM1 SM2 REN TB8 RB8 TI RI(SMOOO= 1)*
FE
Symbol Function.
9F FE Framing Error bit. This bit is set by the receiver when an invalid stop bit is
detected. The FE bit is not cleared by valid frames but should be cleared by
software. The SMOOO bit must be set to enable access to the FE bit.
9F SMO Serial Port Mode Bit 0, (SMOOO must = 0 to access bit SMO)
9E SM1 Serial Port Mode Bit 1
SMO SM1 Mode Description Baud Rate
o 0 0 shift register Fosc/12
o 1 1 8-bit UART variable
o 2 9-bit UART Fosc/64 or Fosc/32
3 9-bit UART variable
90 SM2 Enables the Automatic Address Recognition featur1:l in Modes 2 or 3. If SM2 = 1
then RI will not be set unless the received 9th data bit (RB8) is 1, indicating an
address, and the received byte is the Given or Broadcast Address. In Mode 1, if
SM2 = 1 then RI will not be activated unless a valid stop bit was received. In
Mode 0, SM2 should be O.
9C REN Enables serial reception. Set by software to enable reception. Clear by software
to disable reception.
9B TB8 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by
software as desired.
9A RB8 In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8
is the stop bit that was received. In Mode 0, RB8 is not used.
99 TI Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0,
or at the beginning of the stop bit in the other modes, in any serial transmission.
Must be cleared by software.
98 RI Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or
halfway through the stop bit time in the other modes, in any serial reception
(except see SM2). Must be cleared by software.
'SMODO is located in peON.6.
called SMODO, and resides at PCON.6 (Table 35). If The baud rate in Mode 2 depends on the value of bit
SMODO = 0, then accesses to SCON.7 are to SMO. If SMODI in Special Function Register PCON. If
SMODO = I, then accesses to SCON.7 are to FE. SMODI = 0 (which is the value on reset), the baud
rate is '/64 the oscillator frequency. If SMODI = 1, the
baud rate is '/32 the oscillator frequency.
8.3 Serial Port Control Register
Mode 2. = 2SMODI X (Oscillator Frequency)
The serial port control and status register is the Special Baud Rate 64
Function Register SCON, shown in Table 19. This reg-
ister contains not only the mode selection bits, but also The baud rates in Modes 1 and 3 are determined by the
the 9th data bit for transmit and receive (TB8 and Timer 1 overflow rate, or by Timer 2 overflow rate, or
RB8), and the serial port interrupt bits (TI and RI).
by both (one for transmit and the other for receive).
8.4 Baud Rates
The baud rate in Mode 0 is fixed:
Oscillator Frequency
Mode 0 Baud Rate = -------''-----'-
12
8-79
8XC51GB HARDWARE DESCRIPTION
8.5 Using Timer 1 to Generate Baud er" operation is a little different for Timer 2 when it's
being used as a baud rate generator: Normally, as a
Rates timer, it would increment every mach cycle (thus at
When Timer 1 is used as the baud rate generator, the 1112 the oscillator frequency). As a baud rate genera-
baud rates in Modes 1 and 3 arc determined by the tor, however, it increments every state time (thus at '/2
Timer 1 overflow rate and the value of SMODI as fol- the oscillator frequency). In that case the baud rate is
lows: given by the formula:
Modes 1 and 3 = 2SMODI X (Timer I Overflow Rate) Modes 1 and 3 Oscillator Frequency
Baud Rate 32 Baud Rate 32 X [65536 - (RCAP2H, RCAP2L)1
The Timer 1 interrupt should be disabled in this appli- where (RCAP2H, RCAP2L) is the content of
cation. The Timer itself can be configured for either RCAP2H and RCAP2L taken as a 16-bit unsigned in-
"timer" or "counter" operation, and in any of its 3 teger.
running modes. In the most typical applications, it is
configured for "timer" operation, in the auto-reload Timer 2 as a baud rate generator is shown in Figure 17.
mode. (high nibble of TMOD = 00 lOB). In that case, This figure is valid only if RCLK + TCLK = 1 in
the baud rate is given by the formula: T2CON. Note that a rollover in TH2 does not set TF2,
and will not generate an interrupt. Therefore, the Timer
Modes 1 and 3 2SMODI Oscillator Frequency 2 interrupt does not have to be disabled when Timer 2
= - - - X ------''----':- is in the baud rate generator mode. Note too, that if
Baud Rate 32 12X [256 - (THI)l EXEN2 is set, a I-to-O transition in T2EX will set
EXF2 but will not cause a reload from (RCAP2H,
One can achieve very low baud rates with Timer 1 by RCAP2L) to (TH2, TL2). Thus when Timer 2 is in use
leaving the Timer 1 interrupt enabled, and configuring as a baud rate generator, T2EX can be used as an extra
the Timer to run as a 16-bit timer (high nibble of external interrupt; if desired.
TMOD = DOOlB), and using the Timer 1 interrupt to
do a 16-bit software reload. It should be noted that when Timer 2 is running (TR2
= 1) in "timer" function in the baud rate generator
Table 20 lists various commonly used baud rates and mode, one should not try to read or write TH2 or TL2.
how they can be obtained from Timer 1. Under these conditions the Timer is being incremented
every state time, and the results of a read or write may
not be accurate. The RCAP2 registers may be read, but
8.6 Using Timer 2 to Generate Baud shouldn't be written to, because a write might overlap a
Rates reload and cause write and/or reload errors. Tum the
Timer off (clear TR2) before accessing the Timer 2 or
Timer 2 is selected as the baud rate generator by setting RCAP2 register, in this case.
TCLK and/or RCLK in T2CON (Table 9). Note then
the baud rates for transmit and receive can be simulta- Table 21 lists various commonly used baud rates and
neously different. Setting RCLK and/or TCLK puts how they can be obtained from Timer 2.
Timer 2 into its baud rate generator mode, as shown in
Figure 14. Table 21. Timer 2 Generated
Commonly Used Baud Rates
The baud rate generator mode is similar to the auto"re-
load mode, in that a rollover in TH2 causes the Timer 2 Timer 2
registers to be reloaded with the 16-bit value in registers Baud Rate Os Freq
RCAP2H and RCAP2L, which are preset by software. RCAP2H RCAP2L
375K 12MHz FF FF
Now, the baud rates in Modes I and 3 are determined 9.6K 12 MHz FF 09
by Timer 2's overflow rate as follows: 4.8K 12 MHz FF B2
2.4K 12 MHz FF 64
Modes I and 3. _ Timer 2 Overflow Rate
1.2K 12 MHz FE C8
Baud Rates - 16
300 12MHz FB 1E
110 12 MHz F2 AF
The Timer can be configured for either "timer" or
"counter" operation. In the most typical applications, it 300 6MHz FO 8F
is configured for "timer" operation (C/T2 = 0). "Tim- 110 6MHz F9 57
8-80
8XC51GB HARDWARE DESCRIPTION
Table 20. Timer 1 Generated Commonly Used Baud Rates
Timer 1
Baud Rate fose SMOD
Reload
CIT Mode
Value
Mode 0 Max: 1 MHz 12MHz X X X X
Mode 2 Max: 375K 12 MHz 1 X X X
Modes 1. 3: 62.5K 12 MHz 1 0 2 FFH
19.2K 11.059 MHz 1 0 2 FDH
9.6K 11.059 MHz 0 0 2 FDH
4.8K 11.059 MHz 0 0 2 FAH
2.4K 11.059 MHz 0 0 2 F4H
1.2K 11.059 MHz 0 0 2 E8H
137.5K 11.986 MHz 0 0 2 1DH
110K 6MHz 0 0 2 72H
110K 12MHz 0 0 1 FEEBH
TIMER 1
OVERFLOW
NOTE: OSC. FREO.IS DIVIOEO BY 2. NOT 12.
12 P I N - - - - - - '
RX CLOCK
TX CLOCK
12EX PIN "TIMER 2"
INTERRUPT
EXEN2
L NOTE AVAILABILITY OF ADDmONAL EXTERNAL INTERRUPT
270691-21
Figure 17. Timer 2 in Baud Rate Generator Mode
8-81
8XC51GB HARDWARE DESCRIPTION
8.7 Mode 0 Serial 8.8 Mode 1 Serial
Serial data enters and exits through RXD. TXD out- Ten bits are transmitted (through TXD), or received
puts the shift clock. 8 bits arc transmitted/received: 8 (through RXD): a start bit (0), 8 data bits (LSB first),
data bits (LSB first). The baud rate is fixed at '/,2 the and a stop bit (I). On receive, the stop bit goes into
oscillator frequency. RB8 in SCON. The baud rate is determined either by
the Timer 1 overflow rate, or the Timer 2 overflow rate,
Figure 18 shows a simplified functional diagram of the or both (one for transmit and the other for receive).
serial port in Mode 0, and associated timing.
Figure 19 shows a simplified functional diagram of the
Transmission is initiated by any instruction that uses serial port Mode 1, and associated timings for transmit
SBUF as a destination register. The "write to SBUF" receive.
signal at S6P2 also loads a I into the 9th position of the
transmit shift register and tells the TX Control block to Transmission is initiated by any instruction that uses
commence a transmission. The internal timing is such SBUF as a designation register. The "write to SBUF"
that one full machine cycle will elapse between "write signal also loads a I into the 9th bit position of the
to SBUF" and activation of SEND. transmit shift register and flags the TX Control unit
that a transmission is requested. Transmission actually
SEND enables the output of the shift register to the commences at SIPI of the machine cycle following the
alternate output function line of P3.0, and also enables next rollover in the divide-by-16 counter. (Thus, the bit
SHIFT CLOCK to the alternate output function line of timers are synchronized to the divide-by-16 counter,
P3.1. SHIFT CLOCK.is low during S3, S4, and S5 of not to the "write to SBUF" signal.)
every machine cycle, and high during S6, S I, and S2.
At S6P2 of every machine cycle in which SEND is The transmission begins with activation of SEND,
active, the contents of the transmit shift register are which puts the start bit at TXD. One bit time later,
shifted to the right one position. DATA is activated, which enables the output bit of the
transmit shift register to TXD. The first shift pulse oc-
As data bits shift out to the right, zeroes come in from curs one bit time after that.
the left. When the MSB of the data byte is at the output
position of the shift register, then the I that was initial- As data bits shift out the right, zeroes are clocked in
ly loaded into the 9th position, is just to the left of the . from the left. When the MSB of the data byte is at the
MSB, and all positions to the left ofthat·contain zeroes. output position of the shift register, then the I that was
This condition flags the TX Control block to do one initially loaded into the 9th position is just to the left of
last shift and then deactivate SEND and set TI. Both of the MSB, and all positions to the left of that contain
these actions occur at SIP I of the 10th machine cycle zeroes. This condition flags the TX Control unit to do
after "write to SBUF." one last shift and then deactivate SEND and set TI.
This occurs at the 10th divide-by-16 rollover after
Reception is initiated by the condition REN = I and "write to SBUF".
Rl = O. At S6P2 of the next machine cycle, theRX
Control unit writes the bits 11111110 to the receive Reception is initiated by a detected I-to-O transition at
shift register, an in the next close phase activates RE- RXD. For this purpose, RD is sampled at a rate of 16
CEIVE. times whatever baud rate has been established. When a
transition is detected, the divide-by-16 counter is imme-
RECEIVE enables SHIFT CLOCK to the alternate diately reset, and IFFH is written into the input shift
output function line of P3.1. SHIFT CLOCK makes register. Resetting the divide-by-16 counter aligns its
transitions at S3P I and S6P I of every machine cycle. . rollovers with the boundaries of the incoming bit times.
At S6P2 of every machine cycle in which RECEIVE is
active, the contents of the receive shift register are shift- The 16 states of the counter divide each bit time into
ed to the left one position. The value that comes in 16ths. At the 7th, 8th, and 9th counter states of each bit
from the right is the value that was sampled at the P3.0 time, the bit detector samples the value of RD. The
pin at S5P2 of the same machine cycle. value accepted is the value that was seen in at least 2 of
the 3 samples. This is done for noise rejection. If the
As data bits comcin from the right, Is shift to the left. valued accepted during the first bit time is not 0, the
When the 0 that was initially loaded into the rightmost receive circuits are reset and the unit goes back to look-
position arrives at the leftmost position in the shift reg- ing for another I-to-O transition. This is to provide re-
ister, it flags the RX Control block to do one last shift jection of false start bits. If the start bit proves valid, it
and load SBUF. At SIPI of the 10th machine cycle is shifted into the input shift register, and reception of
after the write to SCON that cleared RI, RECEIVE is the rest of the frame will proceed.
cleared and RI is set.
8-82
inter 8XC51GB HARDWARE DESCRIPTION
WRITE
TO - - r - - + J I ' - - - - '
RXD
SBUF r-----~----1_--------r_, P3.0ALT
OUTPUT
FUNCTION
S6-,----I
TXD
P3.1 ALT
OUTPUT
FUNCTION
'-----~ RX CLOCK
REN RX CONTROL SHIFT
Ri--...-}-----I START 1 1 1 1 1 1 1 0
RXD
P3.0ALT
INPUT
FUNCTION
READ
SBUF
ALE
--II WRITE TO SBUF
SENDLS6P2 I
SHIFT
RXD (DATA OUT) , TRANSMIT
---11 WRITE TO SCON (CLEAR RI)
RII~I~~=====r========================================================~r----
~CEIVE
SHIFT
~
RECEIVE
RXD (DATAIN)---i1""'---ac!!..!.--~~--{}""--""""LF"----{},"-'<...--1:F'----O='-'--
TXD (SHIFT CLOCK)
270691-22
Figure 18. Serial Port Mode 0
8-83
intJ 8XC51GB HARDWARE DESCRIPTION
TIMER 1 TIMER 2
OVERFLOW OVERFLOW
WRITE
TO
SElUF
--~r-----~=-t;i~~--~~-----, ____~~ TXD
TCLK -
TI
TRANSMIT
~16RESET
1
-:r;~LOCK' n ~T"R1 BIT~ 00
D' D3 06 oj
STOP BIT
RECEIVE BIT DETECTOR SAMPLE TIMES
SHIFT
__________________________________________________________
~R~I ~r----
270691-23
Figure 19. Serial Port Mode 1
8-84
inter 8XC51GB HARDWARE DESCRIPTION
As data bits come in from the right, Is shift to the left. curs on bit time after that. The first shift clocks a I (the
When the start bit arrives at the leftmost position in the stop bit) into the 9th bit position of the shift register.
shift register (which in mode I is a 9-bit register), it Thereafter, only zeroes are clocked in. Thus, as data
flags the RX Control block to do one last shift, load bits shift out to the right, zeroes are clocked in from the
SBUP and RBS, and set RI. The signal to load SBUP left. When TBS is at the output position of the shift
and RBS, and to set RI will be generated if, and only if, register, then the stop bit is just to the left of TBS, and
the following conditions are met at the time the final all positions to the left of that contain zeroes. This con-
shift pulse is generated. dition flags the TX Control unit to do one last shift and
1. RI = 0 then deactivate SEND and set TI. This occurs at the
II th divide-by-16 rollover after "write to SBUP".
2. Either SM2 = 0, or the received stop bit =
Reception is initiated by a detected I-to-O transition at
If either of these two conditions is not met, the received RXD. Por this purpose RXD is sampled at a rate of 16
frame is irretrievably lost. If both conditions arc met, times whatever baud rate has been established. When a
the stop bit goes into RBS, the S data bits go into transition is detected, the divide-by-16 counter is imme-
SBUP, and RI is activated. At this time, whether the diately reset, and IPPH is written to the input shift
above conditions are met or not, the unit goes back to register.
looking for a I-to-O transition in RXD.
At the 7th, Sth and 9th counter states of each bit time,
to the bit detector samples the value of RXD. The value
8.9 Modes 2 and 3 Serial accepted is the value that was seen in at least 2 of the 3
samples. If the value accepted during the first bit time
Eleven bits are transmitted (through TXD), or received
is not 0, the receive circuits are reset and the unit goes
(through RXD): a start bit (0), S data bits (LSB first), a
back to looking for another 1-to-O transition. If the
programmable 9th data bit, and a stop bit (1). On trans-
start bit proves valid, it is shifted into the input shift
mit, the 9th data bit (TBS) can be assigned the value of
register, and reception of the rest of the frame,will pro-
o or 1. On receive, the 9th data bit goes into RBS in ceed.
SCaN. The baud rate is programmable to either Timer
1 or 2 depending on the state of TCLK and RCLK.
As data bits come in from the right, Is shift to the left.
When the start bit arrives at the leftmost position in the
Pigure 20 and Pigure 21 show a functional diagram of
shift register (which in Modes 2 and 3 is a 9-bit regis-
the 'serial port in Modes 2 and 3. The receive portion is
ter), it flags the RX Control block to do one last shift,
exactly the same as in Mode 1. The transmit portion
load SBUP and RBS, and set RI. The signal to load
differs from Mode 1 only in the 9th bit of the transmit
SBUP and RBS, and to set RI, will be generated if, and
shift register.
only if, the following conditions are met at the time the
final shift pulse is generated:
Transmission is initiated by any instruction that uses
SBUP as a destination register. The "write to SBUP" 1. RI = 0, and
signal also loads TBS into the 9th bit position of the
2. Either SM2 = 0 or the received 9th data bit =
transmit shift register and flags the TX Control unit
that a transmission is requested. Transmission comm-
If either of these conditions is not met, the received
mences at SIPI of the machine cycle following the next
frame is irretrievably lost, and RI is not set. If both
rollover in the divide-by-16 counter. (Thus, the bit
conditions are met, the received 9th data bit goes into
times are synchronized to the divide-by-16 counter, not
RBS, and the first S data bits go into SBUP. One bit
to the "write to SBUP" signal.)
time later, whether the above conditions were met or
not, the unit goes back to looking for a I-to-O transition
The transmission begins with activation of SEND,
at the RXD input.
which puts the start bit at TXD. One bit time later,
DATA is activated, which enables the output bit of the
Note that the value of the received stop bit is irrelevant
transmit shift register to TXD. The first shift pulse oc-
to SBUP, RBS, or RI.
8-85
inter 8XC51GB HARDWARE DESCRIPTION
TXD
PHASE 2 CLOCK
('I, lose)
MODE2
SMOD = I SERIAL
PORT
INTERRUPT
SMOD=Q
(SMOD IS PCON.?) '--..-----,---1
LOAD
SBUF
RXD
READ
SBUF
TX
~LOC~~~~~~~L_-"L_~I'--_JL_~L__~I____JL-__~L__~L__~L-___
---"WRITE TO SBUF
- - - - , SEND
DATA L SIPI ,
SHIFT TRANSMIT
~STARTBITI DO
TI
I
: 16 RESET
RECEIVE
! RXD BIT DETECTOR' START BIT I
SHIFT
~RI~
SAMPLE TIMES
______
DO 01 02
~--~'--__- " L -__~L____JL____IL-_~l_ _-L____~____L-____
____________________________________________________
~ ~r----
270691-24
Figure 20. Serial Port Mode 2
8-86
inter 8XC51GB HARDWARE DESCRIPTION
TIMER 1 TIMER 2
OVERFLOW OVERFLOW
WRITE
TO __ ~ ______ ~~ __- J
SBUF r-----~----~ __~~,
TXD
TCLK - TXCONTROL
SEND
TI
TX
_~LOC~~~!~=-~~__~L_ _~~_ _"~_ _~L_ _~'_ _ _ _'L-__~~__~L_ _~'L-_ _
nWRITE TO SBUF
~ SEND
DATA L SlP1 I
TRANSMIT
STOP BIT
RECEIVE
! RXD BIT DETECTORJ START 8" I
SHIFT
SAMPLE TIMES
____,'--____J'--____~'______~L____~L____~L____~L____~L____~'_____ _
________________________________________________________________
~R~I ~r_____
270691-25
Figure 21. Serial Port Mode 3
8-87
inter 8XC51GB HARDWARE DESCRIPTION
9.0 SERIAL EXPANSION PORT (SEP) combinations of the CLKP and CLKPH bits allow four
different serial interface timings as shown in the Figure
In addition to the serial port, a half-duplex synchro- 22. No matter which timing is chosen, the data will
nous serial interface is provided on the 8XC51GB. Two always be transmitted a half cycle ahead of the sam-
pins, SEPIO/P4.1 and SEPCLK/P4.0, are used for the pling edge.
interface. The SEPIO pin is used for transmission or
reception of 8-bit packets of serial data, and the
SEPCLK outputs the synchronizing clock signal. Four 9.1 Transmitting
clock frequencies and four serial interface timing modes
are provided through the SEP Control Register. The SEPIO pin will float until transmit is initiated by
writing to the SEPDAT register. Note that the Receive
Three SFRs are used for the Serial Expansion Port. The Enable Bit SEPREN must be cleared before transmit-
SEPCON register (Table 22) controls the operation of ting. The data byte that is written to SEPDAT will be
the SEP while the SEPSTA (Table 23) register returns shifted out through the SEPIO pin, MSB first. At the
the status of the SEP operation. The data is exchanged same time, the synchronous clock SEPCLK will be out-
through the SEPDAT register. . put (8 cycles). If an attempt to read or write is made to
the SEPDAT register during a transmit operation the
Reset disables the SEP by resetting the enable bit, Fault Write Bit SEPFWR will be set. The transmit op-
SEPE. When SEPE is set by software, the SEPCLK eration will still be completed, and the SEPIF bit will
will assume the idle state controlled by the CLKP bit. be set. SEPFWR can be cleared by software or by a
If CLKP = 0 the idle state of the SEPCLK clock out- reset.
put is low, and if CLKP = 1 the idle state of the
SEPCLK output is high.
9.2 Receiving
The CLKPH bit controls the point in time at which the
input data is sampled. If CLKPH = 0 the data is sam- Data reception is initiated by setting the SEPREN bit
pled for 8 cycles starting from the first SEPCLK tran- in the SEPCON SFR. The SEPCLK outputs the syn-
sition edge. If CLKPH = 1 the data is sampled for 8 chronizingclock, and the data received on the SEPIO
cycles starting from the transition edge one-half phase pin is shifted into SEPDAT. The SEPREN bit is auto-
later from the first SEPCLK transition edge. The four matically cleared after 8 bits have been received. The
Read Fault bit SEPFRD is set when a read or write to
Table 22. SEPCON: Serial Expansion Port
SEPCON Reset Value = XXOO OOOOB
Address = OD7H Not Bit Addressable
Bit 7 6 5 4 3 2 1 o
SEPCON SEPE SEPREN CLKP CLKPH SEPS1 SEPSO
Symbol Function
Not implemented, reserved for future use. •
SEPE SEP Enable: 1 = Enable, 0 =: Disable with SEPIO and SEPCLK tri-stated.
SEPREN SEP Receive Enable: 1 = Enable, 0 = Disable
CLKP Clock Polarity: 0 = Idle Polarity is Low,
1 = Idle Polarity is High
CLKPH Clock Phase: 0 = Start Data Sample on First SEPCLK Edge, 1 = Start Data Sample' on
SEPCLK Edge Half Phase Later
SEPS1 SEP Speed Select Bit 1
SEPSO SEP Speed Select Bit 0
XTAL Freq.
SEPS1 SEPSO Divided by (@12MHz)
0 0 12 1.000 MHz
0 1 24 500 KHz
1 0 48 250 KHz
1 96 125 KHz
·User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke
new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value
read from a reserved bit is indeterminate.
8-88
inter 8XC51GB HARDWARE DESCRIPTION
the SEPDAT register is attempted during a receive op- 10.0 AID CONVERTER
eration. The' data reception will be completed and the
false operation will be ignored. The SFRFRD bit can The 8XC51 GB AID Converter is an 8-bit device with 8
be cleared by software or a reset. Note that the input inputs. It features Internal Sample and Hold and uses
data must be stable during the SEPCLK pulse train. the successive approximation method of conversions.
The source of the transmitted data during a receive op- The AID consists of eight dedicated analog inputs pins,
eration has no control over the clock. ACHO-ACH7, and eight AID conversion result regis-
ters, ADRESO-ADRES7. In addition, the AID has a
comparison voltage input pin, COMPREF, and one
9.3 SEP Interrupt comparison result register, ACMP. It also has a control
input pin, TRIGIN, a separate voltage reference pin,
At the end of either a transmission or reception, the VREF, and an analog ground pin, AGND. One'AID
SEP interrupt flag SEPIF is set, and if the ESEP bit control register, ACON, is located in the SFRs.
(register lEA, see Interrupts section) equals a I then an
interrupt is generated. The SEPIF bit can be set regard-
less of the state of the ESEP bit, but SEPIF must be 10.1 Conversion Cycle
cleared by software.
The GB AID conversion cycle consists of eight conver-
sions. When a conversion cycle begins, the first channel
is converted and the result placed in register ADRESO,
CLKP CLKPH
" " SEPCLK ..... S L
I
" SEPCLK ..... n. . .____I
" SEPCLK ..... ILI
I
SEPCLK ....• -.J
SEPIO
DATA
= MSB
I I
I
I
I
I
I
...... @
I
LSB
SAMPLED t t t ••• •• _ . . 1 -_ __
270691-26
Figure 22. SEP Clock Waveforms
Table 23.SEPSTA: Serial Expansion Port Status Register
SEPSTA Reset Value = XXXX XOOOB
Address = OF7H Not Bit Addressable
Bit 7 6 5 4 3 2 1 0
SEPFWR SEPFRD SEPIF
Symbol Function
Not implemented, reserved for future use.'
SEPFWR SEPFWR = 1: SEPDAT Read/Write Attempted During Data Reception
SEPFRD SEPFRD = 1: SEPDAT Read/Write Attempted During Data Reception
SEPIF SEPIF = 1: Interrupt Flag Set upon Completion of Data Transmission or
Reception, SEPIF = 0: Interrupt Flag Cleared
'User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke
new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value
read from a reserved bit is indeterminate.
8-89
8XC51GB HARDWARE DESCRIPTION
. then the second channel is converted .and its result plete, sets the AIF bit, and then begins the conversion
placed in ADRESl, and so on until the eighth result is cycle again with the first channel. Conversions continue
placed in ADRES7. When ADRES7 is written to, the in this fashion as long as ACE = 1 and ATM = O.
AID Interrupt Flag, AIF in register ACON is set. If
the AID interrupt is enabled, an interrupt is generated. . Trigger Mode: In trigger mode, the conversion cycle is
The conversion time for a single channel is 26 machine triggered on the trailing edge of pin TRIG IN, and exe-
cycles, or 26 /-I.s at 12 MHz clock frequency. The con- cuted only once from channel 0 to 7. Setting ATM =
version time for the complete cycle of eight conversions I, puts the AID into trigger mode. Bit ACE must be set
is 208 machine cycles, or 208 /-I.s at 12 MHz. The AID during trigger mode as well. After bit ACE is set, the
will operate in both normal or idle modes. first faIling edge of TRIGIN will begin a single conver-
sion cycle. Any further trailing edge ofTRIGIN will be
There is no mode for selecting one channel and doing a ignored until the current conversion cycle is completed.
single conversion. The AID does eight conversions
each time. Scan Mode: In scan mode, the AID converts each of
the eight channels, ACHO-ACH7 in order and places
the results in register ADRESO-ADRES7, respective-
10.2 AID Modes ly. Scan mode is selected by setting AIM (AID Input
Mode) = O.
There are two modes for starting AID conversions:
continuous mode and trigger mode. There are also two Select Mode: In select mode, one of the first four chan-
modes for determining the sequence of channel conver- nels, ACHO-ACH3, is converted four times and the
sions: scan mode and select mode. These modes are set results placed in registers ADRESO-ADRES3. Then
by bits in ACON (Table 23) as described below. channels ACH4-ACH7 are converted once each and
the results placed in registers ADRES4-ADRES7. Set~
Continuous Mode: In continuous mode, conversions ting AIM = 1 places the AID in select mode. The
from channels 0 to 7 are repeated while the AID Con- channel to be converted four times is selected by the
version Enable bit, ACE is set. Continuous mode is AID Channel Select bits ACSI and ACSO as shown in
entered by setting bit ATM (AID Trigger Mode) = O. Table 24. This mode allows the AID to do repeated
Wheu ACE is set, the AID always begins with the first conversions on the same channel quickly.
channel. It continues until the eighth channel is com-
Table 24. ACON: AID Control Register
ACON Reset Value =. OXOO OOOOB
Address = 97H Not Bit Addressable
Bit 7 6 5 4 3 2 1 0
ACON AIF ACE ACS1
ACSO AIM ATM
Symbol Function
Not implemented, reserved for future use.'
AIF AID Interrupt Flag. This bit is set when an AID conversion cycle is completed.
ACE AID Conversion Enable. This bit, when set by software enables the AID.
ACS1 AID Channel Select bin.
ACSO AID Channel Select bit o.
ACS1 ACSO Selected Channel
o 0 ACHO
o 1 ACH1
1 0 ACH2
'1 ACH3
AIM AID Input Mode. This bit selects between the Scan and Select modes for the AID. When
AIM is low, the Scan mode is enabled.
ATM AID Trigger Mode. This bit selects between continuous and triggered conversion modes.
When ATM is set high by software, the Triggered conversion mode is enabled. When
ATM is low, the Continuous. mode is enabled .
• User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke
new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value
read from a reserved bit is indeterminate.
8-90
inter 8XC51GB HARDWARE DESCRIPTION
Table 25 shows the conversion results in the scan and 11.0 INTERRUPTS
select mode and the comparison results in the two
modes. The 8XC51GB has a total of 15 interrupt vectors. It
has seven external interrupt pins, INTO-INT6, as al-
ternate functions on port 3 pins and port 5 pins. The
10.3 COMPREF Feature eight internal interrupts are generated by the peripher-
als: three timer interrupts (Timer 0, Timer I and Timer
All channels are automatically compared against a sin- 2), two programmable counter array interrupts (PCA
gle voltage reference provided by pin COMPREF. If and PCA I), a serial port interrupt, a SEP interrupt,
the particular channel voltage is greater than the refer- and an A/D interrupt. These interrupts are shown in
ence, the corresponding bit in register ACMP is set. If Figure 23.
the voltage is less than or the same.as the COMPREF
voltage, then the corresponding bit is cleared. All eight Each of these interrupts will be briefly described fol-
channels are compared in channel, sequence regardless lowed by a discussion of the interrupt enable bits and
of the scan/select mode. If the AID is in select mode, the interrupt priority levels.
ACMP will still store the comparison results of
ACHO-ACH7 and COMPREF. Table 26 shows the
ACMP register; notice that the channel comparison re-
sults are stored in reverse bit order.
Table 25. The Mode of Execution and Channel Selection
[Mode of Channel Selection)
Comparison All
Conversion Scan Select Result Mode
Result I Mode I Mode
ADRESO ~ ACHO ~ ACHx CMPO ~ ACHO
ADRES1 ~ ACH1 ~ ACHx CMP1 ~ ACH1
ADRES2 ~ ACH2 ~ ACHx CMP2 ~ ACH2
ADRES3 ~ ACH3 ~ ACHx CMP3 ~ ACH3
ADRES4 ~ ACH4 ~ ACH4 CMP4 ~ ACH4
ADRES5 ~ ACH5 ~ ACH5 CMP5 ~,ACH5
ADRES6 ~ ACH6 ~ ACH6 CMP6 ~ ACH6
ADRES7 ~ ACH7 ~ ACH7 CMP7 ~ ACH7
(if ACS1 ,0 = 00 then x = 0, ACS1 ,0 = 01 then x = 1,
ACS1,0 = 10 then x = 2,ACS1,0 = 11 then x = 3)
Table 26. ACMP: AID Compare Register
ACMP Reset Value = 0000 OOOOB
Address = OC7H Not Bit Addressable
Bit 7 6 5 4 3 2 1 0
ACMP CMPO CMP1 CMP2 CMP3 CMP4 CMP5 CMP6 CMP7
Symbol Function
CMPO-7 Comparison results with pin COMPREF. Pins ACHO-ACH7 are automatically
compared to the single voltage reference on pin COMPREF. If pin ACHO-7 is greater
than the reference, CMPO-7 is set high. If not, CMPO-7 is set low.
8-91
inter 8XC51GB HARDWARE DESCRIPTION
External Interrupts INTO and INTI can each be either
level-activated or transition-activatcd, depending on
bits ITO and IT! in Register TCON. The flags that
actually generate these interrupts arc bits lEO and lEI
in TCON. When an external interrupt is generated, the
flag that generated it is cleared by the hardware when
the service routine is vectored, but only if the interrupt
was negative transition-activated .. If the interrupt was
level activated, then the external requesting source con-
trols the request flag, rather than the on-chip hardware.
External Interrupts INT2 and INT3 can each be either
positive or negative traI]sition activated as determined
by bits IT2 and IT3 in register EXICON (Table 27).
The interrupt request is generated by the IE2 and IE3
status bits in EXICON. The IE2 and IE3 bits will be
cleared by the on-chip hardware when the service rou-
tine is vectored to.
External Interrupts INT4, INTS and INT6 are all posi-
tive transition activated. The interrupt request is gener-
ated by the IE4, IES and IE6 bits in register EX ICON
(Table 27). The IE4, IES and IE6 bits will be cleared by
the on-chip hardware when the service routine is vcc-
tored to. INT4~
Timer 0 and Timer I Interrupts are generated by TFO INT5~
and TFI in register TCON, which are set by a rollover
in their respective Timer/Counter registers (except
Timer 0 in Mode 3). When a timer interrupt is generat- INT6~.
ed, the flag that generated it is cleared by the on-chip
hardware when the service routine is vectored to.
T,O---'----------+
T,1
Timer 2 Interrupt is generated by the logical OR of
TF2 and EXF2 in register T2CON. Neither of these
flags is cleared by hardware when the service routine is
T,2
EX,2 D •
vectored to. In fact, the service routine may have to CF--O~;tc,
ro
determine whether it was TF2 or EXF2 that generated
""~""
the interrupt, and the bit will have to be cleared in
software. •
PCA and PCAI Interrupts: The PCA interrupt is gen- ,
erated by the logical OR of CF, CCFO, CCFI, CCF2, '5
CCF3, and CCF4 in register CCON. The PCAI inter-
CF1~C'1
""'~'''''. ro
rupt is generated by the logical OR of CFI, CICFO,
CICFl, ClCF2, CICF3, and ClCF4 in register
CICON. None of these flags is cleared by hardware
when the service routine is vectored to. In fact, normal-
ly the service routine will have to determine which bit
flagged the interrupt and cl~ar that bit in software. The '5
PCA/PCAI interrupt is enabled by bit EC/ECI in the
enable register as shown in Tables 28 and 29. In addi-
tion, each of the CF/CFI and CCFn/ClCFn flags
TI
Rt
SEPIF
D •
must also be enabled by bits ECF/ECFI and
ECCFn/EICCFn in registers CMOD/CIMOD and AIF
CCAPMn/ClCAPMn respectively, in order for that 270691-27
flag to be able to cause an interrupt.
Figure 23. Interrupt Sources
8-92
inter 8XC51GB HARDWARE DESCRIPTION
Table 27. EXICON: External Interrupt Control Register
EXICON Reset Value = XOOO OOOOB
Address = OC6H Not Bit Addressable
Bit 765 4 3 210
EXICON IE6 IE5 IE4 IE3 IE2 IT3 IT2
Symbol Function
Not implemented, reserved for future use.'
IE6 Interrupt 6 Edge flag. This bit is set by hardware when an external interrupt
edge is detected.
IE5 Interrupt 5 Edge flag. This bit is set by hardware when an external interrupt
edge is detected.
IE4 Interrupt 4 Edge flag. This bitis set by hardware when an external interrupt
edge is detected.
IE3 Interrupt 3 Edge flag. This bit is set by hardware when an external interrupt
edge is detected.
IE2 Interrupt 2 Edge flag. This bit is set by hardware when an external interrupt
edge is detected.
IT3 Interrupt 3 Type control bit. This bit is set or cleared by software to control
whether INT3 is positive or negative transition activated. When IT3 is high, IE3
is set by a positive transition on pin INT3. When IT3 is low, IE3 is set by a
negative transition on pin INT3.
IT2 Interrupt 2 Type control bit. This bit is set or cleared by software to control
whether INT2 is positive or negative transition activated. When IT2 is high, IE2
is set by a positive transition on pin INT2. When IT2 is low, IE2 is set by a
negative transition on pin INT2 .
• User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke
new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value
read from a reserved bit is indeterminate.
Serial Port Interrupt is generated by the logical OR of All of the bits that generate interrupts can be set or
RI and TI in register SCON. Neither of these flags is cleared by software, with the same result as though it
cleared by hardware when the service routine is vec- had been set or cleared by hardware. That is, interrupts
tored to. In fact, the service routine will normally have can be generated or pending interrupts can be cancelled
to determine whether it was RI or TI that generated the in software.
interrupt, and the bit will have to be cleared in soft-
ware.
11.1 Interrupt Enable
SEP Interrupt is generated by SEPIF in register
SEPSTA, which is set at the end of either a transmis- Each of these interrupt. sources can be individually en-
sion or reception on the Serial Expansion Port. The abled or disabled by setting or clearing a bit in Special
SEPIF is not cleared by hardware, but will have to be Function Register IE (Table 28) or IEA (Table 29).
cleared in software. Note that IE also contains a global disable bit, EA. If
EA is set (1), the interrupts are individually enabled or
AID Interrupt is generated by AIF in register ACON, disabled by their corresponding bits in IE. If EA is
which is set when an AID conversion cycle of eight clear (0), all interrupts are disabled.
channels has been completed, i.e., when register
ADRES7 is written. The AIF is not cleared by hard-
ware, but will have to be cleared in software.
8-93
8XC51GB HARDWARE DESCRIPTION
Table 28. IE: Interrupt Enable Register
IE Address = OA8H Reset Value
= 0000 OOOOB
Bit Addressable
Bit 7 6 5 4 3 210
IE EA EC ET2 ES ET1 EX1 ETO EXO
Enable bit = 1 enables the interrupt.
Bit Enable bit = 0 disables it.
Address Symbol Function
AF EA Disables all interrupts. If EA = 0, all interrupts are disabled. If EA = 1, each
interrupt can be individually enabled or disabled by setting or clearing its
enable bit.
AE EC PCA interrupt enable bit.
AD ET2 Timer 2 interrupt enable bit.
AC ES Serial Port interrupt enable bit.
AB ET1 Timer 1 interrupt enable bit.
AA EX 1 External interrupt 1 enable bit.
A9 ETO Timer 0 interrupt enable bit.
A8 EXO External interrupt 0 enable bit.
Table 29. lEA: Interrupt Enable A Register
lEA Address = OA7H Reset Value = 0000 OOOOB
Not Bit Addressable
Bit 7 6 5 4 3 210
lEA EAD EX6 EX5 EX4 EX3 EX2 EC1 ESEP
Enable bit = 1 enables the interrupt.
Enable bit = 0 disables it.
Symbol Function
EAD AID Converter Interrupt enable bit.
EX6 External interrupt 6 enable bit.
EX5 External interrupt 5 enable bit.
EX4 External interrupt 4 enable bit.
EX3 External interrupt 3 enable bit.
EX2 External interrupt 2 enable bit.
EC1 PCA 1 interrupt enable bit.
ESEP Serial Expansion port interrupt enable bit.
~ 11.2 Priority LevelStructure Table 30. Priority within
Level Polling Sequence
Each interrupt source can also be individually pro-
grammed to one of four priority levels, depending on 1 (Highest) INTO
the value of the two corresponding bits in registers IP 2 SEP
and IPI or IPA and IPAI as shown in Table 31 or 3 INT2
Table 32. A low-priority interrupt can itself be inter- 4 Timer 0
rupted by an interrupt of a higher priority interrupt, 5 PCA1
but not by an interrupt of the same or lower priority 6 INT3
level. An interrupt of the highest priority cannot be 7 INT1
interrupted by any other interrupt source. 8 AID
9 INT4
If two or more requests of different priority levels are 10 Timer 1
received simultaneously, the request of highest priority 11 PCA
level.is serviced. Thus within each priority level there is 12 INT5
a second priority structure determined by the polling 13 Serial Port
sequence shown in Table 30. 14 Timer 2
15 (Lowest) INT6
8-94
8XC51GB HARDWARE DESCRIPTION
Note that the "Priority within level" structure is only 2. The current (polling) cycle is not the final cycle in
used to resolve simultaneous requests of the same prior- the execution of the instruction in progress.
ity level. 3. The instruction in progress is RETI or any write to
the IE or IP registers.
11_2_1 HOW INTERRUPTS ARE HANDLED
Any of these three conditions will block the generation
The interrupt flags are sampled at S5P2 of every ma- of the LCALL to the interrupt service routine. Condi-
chine cycle. The samples are polled during the follow- tion 2 ensures that the instruction in progress will be
ing machine cycle. If one of the flags was in a set condi- completed before vectoring to any service routine. Con-
tion at S5P2 of the preceding cycle, the polling cycle dition 3 ensures that if the instruction in progress is
will find it and the interrupt system will generate an RETI or any access to IE or IP, then at least one more
LCALL to the appropriate service routine, provided instruction will be executed before any interrupt is vec-
this hardware-generated LCALL is not blocked by any . tored to.
of the following conditions:
1. An interrupt of equal or higher priority level is al-
ready in progress.
Table 31. IP and IP1: Interrupt Priority Registers
IPL Address = OB7H Reset Value = XOOO OOOOB
Not Bit Addressable
IP Address = OB8H Reset Value = XOOO OOOOB
Bit Addressable
Bit 7 6 5 4 1 o
IPL PC_1 PT2_1 PS_1 PTO_1 PXO_1
IP PC PT2 PS PTO PXO
IPLbit IP bit Interrupt
0 0 o (Lowest)
0 1 1
1 0 2
1 3 (Highest)
IP1 bit IP bit Bit Address Function
Not implemented, reserved for future use.'
PC_1 PC BE PCA interrupt Priority bits.
PTL1 PT2 BO Timer 2 interrupt Priority bits.
PS_1 PS BC Serial Port interrupt Priority bits.
PT1_1 PT1 BB Timer 1 interrupt Priority bits.
PX1_1 PX1 BA External Interrupt 1 Priority bits.
PTO_1 PTO B9 Timer 0 interrupt Priority bits.
PXO_ PXO B8 External Interrupt 0 Priority bits.
'User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke
new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value
read from a reserved bit is indeterminate.
8-95
infef 8XC51GB HARDWARE DESCRIPTION
The polling cycle is repeated with each machine cycle, Thus the processor acknowledges an interrupt request
and the values polled are the values that were present at by executing a hardware-generated LCALL to the ap-
S5P2 of the previous machine cycle. Note then that if propriate servicing routine. The hardware-generated
one of the above conditions, if the flag is not still active LCALL pushes the contents of the Program Counter
when the blocking condition is removed, the denied in- onto the stack (but it does not save the PSW) and re-
terrupt will not be serviced. In other words, the fact loads the PC with an address that depends on the
that the interrupt flag was once active but not serviced source of the interrupt being vectored to, as shown in
is not remembered. Every polling cycle is new. Table 33.
The polling cycle/LCALL sequence is illustrated in Execution proceeds from that location until the RET!
Figure 24. instruction is encountered. The RETI instruction in-
forms the processor that this interrupt routine is no
Note that if an interrupt of a higher priority level goes longer in progress, then pops the top two bytes from the'
active prior to S5P2 of the machine cycle labeled C3 in
Figure 24, then in accordance with the above rules it
will be vectored to during C5 and C6, without any in-
struction of the lower priority routine having been exe-
cuted.
Table 32. IPA and IPA 1: Interrupt Priority A Registers
IPA1 Address = OB5H Reset Value = 0000 OOOOB
IPA Address = OB6H Reset Value = 0000 OOOOB
Not Bit Addressable
Bit 6 5 4 3 2 1 0
IPA1 PX6_1 PX5_1 PX4_1 PX3_1 ' PXL1 PC1_1 PSEP_1
IPA PX6 PX5 PX4 PX3 PX2 PC1 PSEP
IPA1 bit IPAblt Priority Level
o o o (Lowest)
o 1 1
1 o 2
3 (Highest)
IPA1 bit IPAblt Function
PAD_1 PAD AID Converter interrupt priority bits.
PX6_1 PX6 External Interrupt 6 Priority bits.
PX5_1 PX5 External Interrupt 5 Priority bits.
PX4_1 PX4 External Interrupt 4 Priority bits.
PX3_1 PX3 External Interrupt 3 Priority bits.
PXL1 PX2 External Interrupt 2 Priority bits.
PC1_1 PC1 PCA 1 interrupt priority bits.
PSEP_1 PSEP Serial Expansion Port priority bits.
· .. ·····_--C1--.......I ...o - - - C 2 - -...+I...- - C 3 I • --CS-_·····
C 4 - -••-tI...
tS5P21 56 I
........ ~,~,--'---'--l~~t---L-~'\1:~---'----,
f71
INTERRUPT INTERRUPT
INTERRUPTS
ARE POLLED
LONG CALL TO
INTERRUPT
VECTOR ADDRESS
INTERRUPT ROUTINE
GOES LATCHED
ACTIVE
270691-28
This is the fastest possible response when C2 is the final cycle of an instruction other than RETI or an access to IE or
IP.
Figure 24. Interrupt Response Tlmh"lg Diagram
8-96
inter 8XC51GB HARDWARE DESCRIPTION
Table 33. Interrupt Vector Address Handling
Interrupt Interrupt Cleared by Interrupt Vector
Source Request Bits Hardware Enable Bits' Address
INTO lEO NO (level) EXO 0003H
YES (trans.)
INT1 IE1 NO (level) EX1 0013H
YES (trans.)
INT2 IE2 YES EX2 0053H
INT3 IE3 YES EX3 005BH
INT4 IE4 YES EX4 0063H
INT5 IE5 YES EX5 006BH
INT6 IE6 YES EX6 0073H
TIMER 0 TFO YES ETO OOOBH
TIMER 1 TF1 YES ET1 001BH
TIMER 2 TF2, EXF2 NO ET2 002BH
PCA CF, CCFn NO EC 0033H
n = 0-4
PCA1 CF1, C1CFn NO EC1 0043H
n = 0-4
Serial Port RI, TI NO ES 0023H
SEP SEPIF NO ESEP 004BH
AID AIF NO EAD 003BH
• All Interrupt Enable bits are located in registers IE and lEA.
stack and reloads the Program Counter. Execution of 11.3 External Interrupts
the interrupted program continues from where it left
off. Of the seven external interrupt sources, lNTO-lNT3
can be programmed to different activation modes as
Note that a simple RET instruction would also have shown in Table 34. INTO and INTI can be pro-
returned execution to the interrupted program, but it grammed to be level-activated or transition-activated
would have left the interrupt control system thinking as by setting or clearing bit ITI/ITO in Register TCON. If
interrupt was still in progress. ITI/ITO = 0, external interrupt 1 or 0 is triggered by a
detected low at the INTI/INTO pin. If ITI/ITO = 1,
Note that the starting. addresses of consecutive inter- external interrupt 1 or 0 is negative edge-triggered.
rupt service routine are only 8 bytes apart. That means INT2 and INT3 can be programmed to be positive or
if consecutive interrupts are being used (lEO and TFO, negative transition activated. Setting IT2/IT3 = I
for example, or TFO and IEI), and ifthe first interrupt makes INT2/INT3 positive edge triggered, while clear-
routine is more than 7 bytes long, then that routine will ing IT2/IT3 makes INT2/INT3 negative edge trig-
have to execute a jump out to some other memory loca- gered. INT4, INT5, and INT6 are all positive tran-
tion where the service routine can be completed with- sition activated.
out overlapping the starting address of the next inter-
rupt routine.
Table 34. Interrupt Activation Polarities
INTERRUPT
SOURCE ITn = 0 ITn = 1 (n = 0 to 3)
INTO Level Low Negative Edge
INT1 Level Low Negative Edge
INT2 Negative Edge Positive Edge
INT3 Negative Edge Positive Edge
INT4 Positive Edge Only
INT5 Positive Edge Only
INT6 Positive Edge Only
8-97
8XC51GB HARDWARE DESCRIPTION
For negative edge triggered interrupts, if successive 11.5 Single Step Operation
samples of the INTx pin show a high in one cycle and a
low in the next cycle, interrupt request flag lEx is set. The 8051 interrupt structure allows single-step execu-
Flag bit lEx then requests the interrupt. For positive tion with very little software overhead. As previously
edge triggered interrupts, successive samples of'the noted, an interrupt request will not be responded to
INTx pin must show a low in one cycle and a high in while an interrupt of equal priority level is still in prog-
the next cycle to set interrupt flag lEx. ress, nor will it be responded to after RETI until at
least one other instruction has been executed. Thus,
Since the external interrupt pins arc sampled once each once an interrupt routine has been entered, it cannot be
machine cycle, an input high or low should hold for at re-entered until at least one instruction of the interrupt-
least 12 oscillator periods to ensure sampling. If the ed program is executed. One way to use this feature for
external interrupt is transition-activated, the external single-stop operation is to program one of the external
source has to hold the request pin high for at least one interrupts, INTO or INTI, to be level-activated. The
cycle, and then hold it low for at least one cycle to service routine for the interrupt will terminate with the
ensure that the transition is seen so that interrupt re- following code:
quest flag lEx will be set. lEx will be automatically
JNB P3.2,$ ;Wait Here Till INTO Goes High
cleared by the CPU when the service routine is called.
JB P3.2,$ ;Now Wait Here Till It Goes Low
RET! ;Go Back and Execute One Instruction
If external interrupt INTO or INTI is level-activated,
the external source has to hold the request active until
Now if the INTO pin, which is also the P3.2 pin, is held
the requested interrupt is actmilly generated. Then it
normally low, the CPU will go right into the External
has to deactivate the request before the interrupt serv-
Interrupt 0 routine and stay there until INTO is pulsed
ice routine is completed, or else another interrupt will (from low to high to low). Then it will execute RET!,
be generated.
go back to the task program, execute one instruction,
and immediately re-enter the External Interrupt 0 rou-
tine to await the next pulsing of P3.2. One step of the
11.4 Response Time task program is executed each time P3.2 is pulsed.
The External Interrupt levels are inverted and latched
into the Interrupt Flags lEx at S5P2 of every machine
cycle. The values are not actually polled by the circuit- 12.0 RESET
ry until the next machine cycle. If a request is active
The reset input is the RST pin, which is the input to a
and conditions are 'right for it to be acknowledged, a
Schmitt Trigger. A reset is accomplished by holding the
hardware subroutine call to the requested service rou-
RST pin low for at least two machine cycles (24 oscilla-
tine will be the next instruction to be executed. The call
tor periods), while the oscillator is running. The CPU
itself takes two cycles. Thus, a minimum of three com-
responds by generating an internal reset, with the tim-
plete machine cycles elapse between activation of an
ing shown in Figure 25.
external interrupt request and the beginning of execu-
tion of the first instruction of the service routine. Fig-
The external reset signal is asynchronous to the internal
ure 24 shows interrupt response timing.
clock. The RST pin is sampled during State 5 Phase 2
of every machine cycle. The port, pins will 'maintain
A longer response time would result if the request is
their current activities for the 19 oscillatorperiods after
blocked by one of the 3 previously listed conditions. 'If
a logic 0 has been sampled at the RST pin; that is, for
an interrupt of equal or higher priority level is already
19 to 31 oscillator periods after the external reset signal
in progress, the additional wait time obviously depends
has been applied to the RST pin.
on the nature of the other interrupt's service routine. If
the instruction in progress is not in its final cycle, the
While the RST pin is low, ALE and PSEN are weakly
additional wait time cannot be more than 3 cycles, since
pulled high. After RST is pulled high, it will take I ~o 2
the longest instructions (MUL and DIY) are only 4
machine cycles for ALE and PSEN to start clockmg.
cycles long, and if the instruction in progress is RETI
For this reason, other devices can not be synchronized
or an access to IE, lEA, IP, IPI, IPA, or IPAI, the
to the internal timings of the GB.
additional wait time cannot be more than 5 cycles (a
maximum of one or more cycle to complete the instruc-
The internal reset algorithm resets all the SFRs. Table
tion in progress, plus 4 cycles to 'complete the next in-
4 lists the SFRs and their reset values. The internal
struction if the instruction is MUL or DIV).
RAM is not affected by reset. On power up the RAM
content is indeterminate.
Thus, in a single-interrupt system, the response time is
always more than 3 cycles and less than 9 cycles.
8-98
inl:ef 8XC51GB HARDWARE DESCRIPTION
r-- 12 OSC. PERIODS - 1
I 55 I 56 I 51 I 52 I 53 I 54 I 55 I 56 I 51 I 52 I 53 I 54 I 55 I 56 I 51 I 52 I 53 I 54 I
RST: \ \ \ \ \ \ \ \ \ \ ,
'-' '-'
SAMPLE RST SAMPLE RST r--r----------
, ' ~INTERNAL RESET SIGNAL
PSEN:
po:
....---11 OSC. PERIODS ----~----19 OSC. PERIODS - - - -......
270691-29
Figure 25. Reset Timing
12.1 Power-On Reset The GB has an asynchronous reset on the ports. When
reset is applied to the chip, all ports go to their respec-
The internal reset pull-up resistor can be used to gener- tive reset states.
ate an automatic reset.
An automatic reset can be obtained when Vee is 13.0 WATCHDOG TIMER (WDT)
turned on by connecting the RST pin to Vss through a
10 /LF capacitor (Figure 26), providing the Vee rise- The Watchdog Timer (WOT) provides the ability to
time does not exceed a millisecond and the oscillator recover from hardware or software malfunctions 'by
start-up time does not exceed 10 ms. forcing the part into reset. The WOT is a 14-bit counter
which must be cleared by software before the counter
When power is turned on the circuit holds the RST pin reaches the maximum value of 3FFFH. Otherwise, the
low for an amount of time that depends on the value of WOT generates an internal reset signal. The external
the capacitor and the rate at which it charges. To en- RESET pin is not driven upon a WOT generated reset.
sure a good reset the RST pin must be low long enough The counter is cleared by reset or a software clear and,
to allow the oscillator time to start up (normally a few subsequently incremented every machine cycle. A soft-
msec) plus two machine cycles. ware clear consists of writing the sequence 01EH and
OEIH to the Watchdog Timer Reset Register
WOTCON (Table 35).
80C51GB The WOT operates in both normal and idle modes; it
cannot be disabled during either mode and is active
anytime the oscillator is running.
13.1 WDT in Idle Mode
R5T
+ Since the WOT continues to count while the part is in
10~F _
Idle mode, the user must dedicate some internal or ex-
Vss ternal hardware to service the WOT during Idle. One
way to service the Watchdog Timer is to use one of the
hardware timer!counters on the GB. Prior to entering
270691-30
Idle mode, the software should reset the timer and en-
Figure 26. Power On Reset Circuitry able the timer interrupt for timer overflow. The inter-
rupt will bring the part out of idle. The interrupt ser-
8-99
inter 8XC51GB HARDWARE DESCRIPTION
Table 35. WDTCON: Watchdog Timer Reset Register
WDTCON Address = OA6H Reset Value = XXXX XXXXB
Function: Writing sequence 1EH and E1 H clears the watchdog timer registers to Os.
vice routine can then clear the WDT, reload the timer which implements these features. In the Idle mode
for the next service period of the WDT, and then put (IDL = 1), the oscillator continues to run and the pe-
the part back into Idle. These activities are cumber- ripheral blocks continue to be clocked, but the clock
some for the Idle mode user, but it is necessary to retain signal is gated off to the CPU. In Power Down (PD =
a Watchdog Timer that has the least probability of fail- 1), the oscillator is frozen. The Idle and Power Down
ing by inadvertently getting disabled. modes are activated by setting bits in Special Function
Register PCON (Table 36).
13.2 WDT in Power Down Mode
The power down mode stops all phase clocks. This
means that the WDT will stop counting and hold its
count during .power down. WDT will resume counting
where it left off at the onset of power down if the power
~~.
XTAL 2 = XTAL 1
down mode is terminated by INTO or INTI. WDT will
be cleared and resume count from zero if the power
down is terminated by a reset. INTERRUPT.
1-.---t:>SERIAL PORT,
TIMER BLOCKS
14.0 POWER-SAVING MODES OF CPU
OPERATION
For applications where power consumption is critical
270691-31
the SXC51GB provides two power reducing modes of
operation, Idle and Power Down. The input through Figure 27. Idle and Power Down Hardware
which backup power is supplied during these opera-
tions is Vee. Figure 27 shows the internal circuitry
Table 36. PCON: Power Control Register
-
Address = 87H Reset Value = OOXX.OOOOB
PCON
Not Bit Addressable
Bit 7 6 5 4 3 2 1 0
PCON SMOD1 SMODO POF GF1 GFO PD IDL
Symbol Function
SMOD1 Double Baud rate bit. When set to a 1 and Timer 1 is used to generate baud rate, and the
Serial Port is used in modes 1, 2, or 3.
SMODO When set, Read/Write accesses to SCON.7 are to the FE bit. When clear, Read/Write
accesses to SCON.7 are to the SMO bit. .
Not implemented, reserved for future use. •
POF Power Off Flag. Set by hardware on the rising edge of Vee. Set or cleared by software.
This flag allows detection of a power failure caused reset. Vee must remain above 3V to
retain this bit.
GF1 General-purpose flag bit.
GFO General-purpose flag bit.
PD Power Down bit. Setting this bit activates power down operation.
IDL Idle mode bit. Setting this bit activates Idle modes operation.
If 1s are written to PD and IDL at the same time. PD takes precedence.
·User software should not write 1s to unimplemented bits. These bits may be used in future 8051 family products to
invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The
value read from a reserved bit is indeterminate.
8~100
intJ 8XC51GB HARDWARE DESCRIPTION
14.1 Idle Mode clock frozen, all functions are stopped, but the on~chip
RAM and Special Function Registers are held. The
An instruction that sets PCON.O causes that to be the port pins output the values held by their respective
last instruction executed before going into the Idle SRFs ALE and PSEN output lows.
mode. In the Idle mode, the internal clock signal is
gated off to the CPU, but not to the peripheral func- The 8XC51GB can exit Power Down with either a
tions. The CPU status is preserved in its entirety: the hardware Reset or External Interrupts, INTO or INTI.
Stack Pointer, Program Counter, Program Status An exit with an External Interrupt allows not only the
Word, Accumulator, and all other registers maintain on-chip RAM, but also the SFRs to. be saved.
their data during Idle. The port pins hold the logical
states they had at the time Idle was activated. ALE and The External Interrupt, INTO or INTI, must be en-
PSEN hold at logic high levels. abled and configured as level-sensitive to properly ter-
minate Power Down. Also the interrupt should not be
There are two ways to terminate the Idle. Activation of executed before Vee is.restored to its normal operating
any enabled interrupt will cause PCON.O to be cleared level. The pin must be held down long enough for the
by hardware, terminating the Idle mode. The interrupt oscillator to restart and stabilize and then. be brought
will be serviced, and following RETI the next instruc- ,high to complete the exit. Once the interrupt is serv-
tion to be executed will be the one following the in- iced, the next instruction executed after RETI will be
struction that put the device into Idle. the one following the instruction that put the device in
Power Down.
The flag bits (GFO) and GFI can be used to give an
indication if an interrupt occured during normal opera- In the Power Down mode of operation, Vee can be
tion or during an Idle. For example, an instruction that reduced to as low as 2V. Care must be taken, however,
activates Idle can also set one or both flag bits. When to ensure that Vee is not reduced before the Power
Idle is terminated by an interrupt, the interrupt service Down mode is invoked, and that Vee is restored to its
routine can examine the flag bits. normal operating level, before the Power Down mode is
terminated. The reset that terminates Power Down also
The other way of terminating the Idle mode is with a frees the oscillator. The reset should not be activated
hardware reset. Since the clock oscillator is still run- before Vee is restored to its normal operating level,
ning, the hardware reset needs to be held active for only and must be held active long enough to allow the oscil-
two machine cycles (24 oscillator periods) to complete lator to restart and stabilize (normally less than 10 ms).
the rest.
The signal at the RST pin clears the ID L bit directly 14.3 Power Off Flag
and asynchronously. At this time the CPU resumes
program execution from where it left off; that is, at the The Power Off Flag, POF, is set by hardware when
instruction following the one that invoked the Idle Vee comes up, and can be set or cleared by software.
Mode. As shown in Figure 25, two or three machine This allows one to distinguish between a "cold start"
cycles of program execution may take place before the reset and a "warm start" reset.
internal reset algorithm takes control. On-chip hard-
ware inhibits access to the internal RAM during this A cold start reset is one that is coincident with Vee
time, but access to the port pins is not inhibited. To being turned on to the device after it was turned off. A
eliminate the possibility of unexpected outputs at the warm start reset could be generated, for example, by a
port pins, the instruction following the one that invokes Watchdog Timer, or as an exit from Power Down
Idle should not be one that writes to a port pin or to Mode.
external Data RAM. The PCA can be programmed to
either pause or continue operations during Idle. To use the feature, one checks the POF bit in software
immediately after reset. POF = I would indicate a
cold start. The software 'then clears POF, and com-
14.2 Power Down Mode mences its tasks. POF = 0 immediately after reset
would indicate a warm start.
An instruction that sets PCON.I causes that to be the
last instruction executed before going into the Power Vee must remain a!:lOve 3V for POF to retain a O.
Down mode, the on-chip oscillator is stopped. With the
8-101
inter 8XC51GB HARDWARE DESCRIPTION
15.0 OSCILLATOR FAIL DETECT The status of the OFD can be read in OFDS, bit 0 of
OFDCON (Table 37). This register. will read OFEH
(OFD) when OFD is enabled and OFFH when it is disabled.
The Oscillator Fail Detect Circuit t riggers a reset (for 4
machine cycles) if the oscillator frequency is below the
trigger frequency (range of 20 KHz to 400 KHz). The 16.0 RFI REDUCTION MODE
reset is removed when the oscillator frequency is higher
than the trigger frequency. The oro can be disabled The 8XC51GB contains an RFI reduction mode that is
by software by writing the sequence ElH and IEH to useful in applications that are using no external memo-
the OFDCON register. Writing anything to OFDCON ry. The RFI reduction mode is entered by setting the
except the disable sequence, EIH and IEH, will have RFI bit in the AUXR (Table 38). This will prohibit the
no effect. toggling of pin ALE, a significant cause of RFI. ALE
pin will float high by a weak pullup after being charged
Before going to the Power Down Mode, the OFD must to a high level by a strong device off of reset. The
be disabled or the OrD will force the GB out of Power MOVX instruction will still toggle ALE as a normal
Down. Once the OrD has been disabled, it can only be MOVX. ALE will retain its normal high value during
enabled again by a chip reset via the RESET pin, WDT idle mode and a low value during power down while in
reset, OFD reset, or by exiting Power Down Mode with the RFI reduction mode.
an INTO, INTI, or reset. The OFD cannot be enabled
under software control.
Table 37. OFDCON
OFDCON Address = OA5H Reset Value = XXXX XXXOH
Not Bit Addressable
Bit 7 6 5 432 1 0
OFDCON OFDS
Function: Writing E1 H followed by 1 EH to this register disables the OFD function.
OFDS Reading the value of this bit displays the status of the OFD function.
OFDS = 0: OFD Active
OFDS = 1: OFD Disabled
Table 38. AUXR: Auxiliary Register
AUXR Address = 8EH Reset Value = XXXX XXXOB
Not Bit Addressable
Bit 7 6 5 4 3 2 1 0
AUXR RFI
RFI This bit is set by software to enable the RFI reduction m0ge.
8-102
inter 8XC51GB HARDWARE DESCRIPTION
17.0 PIN ASSIGNMENT
The 8XC51GB will be packaged in the 68 lead PLCC and LCC/CERQUAD package. Its pin assignment is shown in
Figure 28.
C1EX2/P4.S P2.3/All
C1EX3/P4.6 P2.2/Al0
C1EX4/P4.7 P2.1/A9
vee P2.0/A8
PS.O EA/Vpp
PS.l ALE/PROG
INT2/PS.3 PSEN
INT3/P5.4 XTAL2
8XCS1GB XTAL1
INT4/PS.S
INTS/PS.6 (TOP VIEW)
Vss
INT6/PS.7 TRIGIN
INT7/PS.2 ACHO
T2/P1.0 ACHI
T2EX/Pl.l ACH2
C/P1.2 ACH3
CEXO/Pl.3 ACH4
CEX1/P1.4 ACHS
III II! ": It;;
- -D.. a..
- .....
VI
Q..
.....................
N '" ..
'"
~ ~.~
u u u
270691-32
Figure 28. Pin Assignment
8-103
83C51FA/80C51FA
CHMOS SINGLE-CHIP 8~BIT MICROCONTROLLER
83C51 FA-8K Bytes of Factory Mask Programmable ROM
80C51FA....;.cPU with RAM and I/O
83C51FA/80C51FA-3.5 MHzto~12 MHz, Vee = 5V ±20%
83C51FA-1/80C51FA-1-3.5 MHz to 16 MHz, Vee = 5V ±20%
83C51FA-2/80C51FA-2-o.5 MHz to 12 MHz, Vee = 5V ± 20%
• High Performance CHMOS EPROM
• Programmable
7 Interrupt Sources
• Three 16-Bit Timer/Counters
- Timer 2 is an Up/Down • - Framing ErrorSerial Channel with:
Detection
Timer/Counter - Automatic Address Recognition
• Programmable Counter Array with:
- High Speed Output,
• TTL and CMOS Compatible Logic
Levels
- Compare/Capture,
- Pulse Width Modulator, • 64K External Program Memory Space
- Watchdog Timer capabilities • 64K External Data Memory Space
• Boolean Processor
256 Bytes of On-Chip Data RAM • Power Saving Idle and Power Down
MCS®-51 Compatible Instruction Set
• 32 Programmable I/O Lines • Modes
• • ONCETM (On-Circuit Emulation) Mode
MEMORY ORGANIZATION
PROGRAM MEMORY: Up to 8K bytes of the program memory can reside in the on-chip ROM (83C51FA only).
In addition the device can address up to 64K of program memory external to the chip.
DATA MEMORY: This microcontroller has a 256 x 8 on-chip RAM. In addition it can address up to 64K bytes of
external data memory.
The Intel 83C51FA is a single-chip control oriented microcontroller which is fabricated on Intel's reliable
a
CHMOS III technology. Being member of the 8051 family, the 83C51 FA uses the same powerful instruction
set, has the same architecture, and is pin for pin compatible with the existing MCS-51 products. The 83C51 FA
is an enhanced version of the 80C51 BH. It's added features make it an even more powerful microcontroller for
applications that require Pulse Width Modulation, High Speed I/O, and up/down counting capabilities such as
motor control. It also has a more versatile serial channel that facilitates multi-processor communications.
For the remainder of this document, the 83C51FA and 80C51FA will be referred to as the 83C51 FA.
October 1989
8-104 Order Number: 270538-003
inter 83C51FA/80C51FA
Vee .. -----------,
v~
E
=1
I
PSEN
TIMING
ALE/fSiWG
a/vpp
RST
-----.1
PloD - PL7 P3.0- P3.7
270538-1
Figure 1. 83C51FA Block Diagram
8-105
inter 83C51FA/80C51FA
PACKAGES
Part Prefix Package Type
83C51FA P 40-Pin Plastic DIP
80C51FA D 40-Pin CERDIP
N 44-Pin PLCC
S 44-Pin QFP
"II; "'! C'i 0 (.) q . C"! I""!
INDEX
(T2) PLO Vee a::D..D..n.n.~>u~~~:r
CORNER
(T2EX) PI. 1 PO.O (ADO) ~~~~~~~~~~
(ECI) Pl.2 PO.l (AD1)
Pl.S PO.4
(CEXO) P1.3 PO.2 (AD2)
Pl.S PO.S
(CEX1)Pl.4 PO.3 (AD3)
Pl.7 PO.S
(CEX2) Pl.S PO .. (AD4)
RST PO.7
(CEX3) Pl.S PO.S (ADS) fA
P3.0
(CEX4) Pl.7 PO.S (ADS)
NC He
RESET PO.7 (AD7) P3.1 ALE'
(RXD) P3.0 EA P3.2 PSEN
(TXD) P3.1 ALE P3.3 P2.7
(iNTO) P3.2 PSEN P3.4 P2.6
(INn) P3.3 P2.7 (A1S) P3.S P2.S
(TO) P3.4 P2.S (A 14)
(n) P3.S P2.S (A 13)
(VIR) P3.S P2.4 (A 12)
(Ril) P3.7 P2.3 (All)
XTAL2 P2.2 (A 10) 270538-19
XTAL1 P2.1 (A9) PLCC
Vss P2.0 (AB)
270538-2
DIP
INDEX
CORNER \
.1:::11~11~11::;:11~11~11~11t::;11~11~11~1
Pl.S 1:!....., ....,...., . ~ . -I .. -...., ....' .. -,'-I .. -·L3) PO.'4
Pl.S 2:; I~ PO.S
Pl.7 3:! i.t1 PO.6
RST .(! L3~ PO.7
P3.0 5:; l~ EA
NC (! L2ls NC
P3.1 (! If? ALE
Pl.2 s:: ~is PSEN
P3.3 (! ;)} P2.7
PH 19; l~ P2.S
P3.5 (i; 12) P2.5
• :~~ :~~ ;--:!~ :~~ :~~ ~~ ~~ :~~ ~~ :~~ :~~.
270538-20
(QFP)
Figure 2. Pin Connections
8-106
intJ 83C51 FAl80C51 FA
PIN DESCRIPTIONS Port 2: Port 2 is an 8-bit bidirectional 1/0 port with
internal pullups. The Port 2 output buffers can drive
Vee: Supply voltage. LS TTL inputs. Port 2 pins that have 1's written to
them are pulled high by the internal pullups, and in
Vss: Circuit ground. that state can be used as inputs. As inputs, Port 2
pins that are externally being pulled low will source
Port 0: Port 0 is an 8-bit, open drain, bidirectional 1/0 current (II L, on the data sheet) because of the inter-
port. As an output port each pin can sink several LS na pullups.
TTL inputs. Port 0 pins that have 1's written to them
float, and in that state can be used as high-imped- Port 2 emits the high~order address byte during
ance inputs. fetches from external Program Memory and during
accesses to external Data Memory that use 16-bit
Port 0 is also the multiplexed low-order address and addresses (MOVX @DPTR). In this application it
data bus during accesses to external Program and uses strong internal pullups when emitting 1'so Dur-
Data Memory. In this application it uses strong inter- ing accesses to external Data Memory that use 8-bit
nal pullups when emitting1 's, and can source and addresses (MOVX @Ri), Port 2 emits the contents of
sink several LS TTL inputs. the P2 Special Function Register.
Port 0 outputs the code bytes during program verifi- Some Port 2 pins receive the high-order address bits
cation on the 83C51 FA. External pullup resistors are during program verification.
required during program verification.
Port 3: Port 3 is an 8-bit bidirectional 1/0 port with
Port 1: Port 1 is an 8-bit bidirectional 1/0 port with internal pull ups. The Port 3 output buffers can drive
internal pullups. The Port 1 output buffers can drive LS TTL inputs. Port 3 pins that have 1's written to
LS TTL inputs. Port 1 pins that have 1's written to them are pulled high by the internal pullups, and in
them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 3
that state can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source
pins that are externally being pulled low will source current (IlL, on the data sheet) because of the pull-
current (IlL, on the data sheet) because of the inter- ups.
nal pullups.
Port 3 also serves the functions of various special
In addition, Port 1 serves the functions of the follow- features of the MCS-51 Family, as listed below:
ing special features of the 83C51 FA:
Port Pin Alternate Function
Port Pin Alternate Function
P3.0 RXD (serial input port)
P1.0 T2 (External Count Input to Timerl P3.1 TXD (serial output port)
Counter 2) P3.2 INTO (external interrupt 0)
P1.1 T2EX (Timer/Counter 2 Capturel P3.3 INT1 (external interrupt 1)
Reload Trigger and Direction Control) P3.4 TO (Timer 0 external input)
P1.2 ECI (External Count Input to the PCA) P3.5 T1 (Timer 1 external input)
P1.3 CEXO (External 1/0 for Comparel P3.6 WR (external data memory write strobe)
Capture Module 0) P3.7 RD (external data memory read strobe)
P1.4 CEX1 (External 1/0 for Comparel
Capture Module 1) RST: Reset input. A high on this pin for two machine
P1.5 CEX2 (External 1/0 for Compare I cycles while the oscillator is running resets the de-
Capture Module 2) vice. An internal pulldown resistor permits a power-
on reset with only a capacitor connected to Vee.
P1.6 CEX3 (External 1/0 for Comparel
Capture Module 3) ALE: Address Latch Enable output pulse for latching
P1.7 CEX4 (External 1/0 for Compare I the low byte of the address during accesses to ex-
Capture Module 4) ternal memory.
In normal operation ALE is emitted at a constant
Port 1 receives the low-order address bytes during
rate of % the oscillator frequency, and may be used
ROM verification.
for external timing or clocking purposes. Note, how-
ever, that one ALE pulse is skipped during each ac-
cess to external Data Memory.
8-107
inter 83C51FA/80C51FA
PSEN: Program Store Enable is the read strobe to
external Program Memory. C2
I--t---I XTAL2
When the 80C51 FA is executing code from external
Program Memory, PSEN is activated twice each ma-
chine cycle, except that two PSEN activations are
I-~~--I XTAL 1
skipped during each access to external Data Memo-
ry. t - - - - - - - - - 1 Vss
EAlVpp: External Access enable. EA must be
270538-3
strapped to VSS in order to enable the device to Cl, C2 = 30 pF ± 10 pF for Crystals
fetch code from external Program Memory locations = 10 pF for Ceramic Resonators
OOOOH to OFFFFH. Note, however, that if either of
the Program Lock bits are programmed, EA will be Figure 3. Oscillator Connections
internally latched on reset.
EA should be strapped to Vee for internal program
executions. NIC XTAL2
XTAL 1: Input to the inverting oscillator amplifier. EXTERNAL
OSCILLATOR XTAL 1
XTAL2: Output from the inverting oscillator amplifier. SIGNAL
vss
OSCILLATOR CHARACTERISTICS
270538-4
XTAL 1 and XT AL2 are the input and output, respec-
tively, of a inverting amplifier which can be config- Figure 4. External Clock Drive Configuration
ured for use as an on-chip oscillator, as shown in
Figure 3. Either a quartz crystal or ceramic resonator
may be used. More detailed information concerning IDLE MODE
the use of the on-chip oscillator is available in Appli-
cation Note AP-155, "Oscillators for Microcontrol- The user's software can invoke the Idle Mode. When
lers." the microcontroller is in this mode, power consump-
tion is reduced. The Special Function Registers and
To drive the device from an external clock source, the onboard RAM retain their values during Idle, but
XTAL 1 should be driven, while XTAL2 floats, as the processor stops executing instructions. Idle
shown in Figure 4. There are no requirements on the Mode will be exited if the chip is reset or. if an en-
duty cycle of the external clock signal, since the in- abled interrupt occurs. The PCA timer/counter can
put to the internal clocking circuitry is through a di- optionally be left running or paused during Idle
vide-by-two flip-flop, but minimum and maximum Mode.
high and low times specified on the data sheet must
be observed.
POWER DOWN MODE
An external oscillator may encounter as much as a
100 pF load at XTAL 1 when it starts up. This is due To save even more power, a Power Down mode can
to interaction between the amplifier and its feedback be invoked by software. In this mode, the oscillator
capacitance. Once the external signal meets the VIL is stopped and the instruction that invoked Power
and VIH specifications the capacitance will not ex- Down is the last instruction executed. The on-chip
ceed 20 pF. RAM and Special Function Registers retain their val-
ues until the Power Down mode is terminated.
8-108
inter 83C51 FA/80C51 FA
On the 83C51 FA either a hardware reset or an ex- nal RAM in this event, but access to the port pins
ternal interrupt can cause an exit from Power Down. is not inhibited. To eliminate the possibility of an
Reset redefines all the SFRs but does not change unexpected write when Idle is terminated by re-
the on-chip RAM. An external interrupt allows both set, the instruction following the one that invokes
the SFRs and on-chip RAM to retain their values. Idle should not be one that writes to a port pin or
to external memory.
To properly terminate Power Down the reset or ex-
ternal interrupt should not be executed before Vce is
restored to its normal operating level and must be ONCETM MODE
held active long enough for the oscillator to restart
and stabilize (normally less than 10 ms). The ONCE ("On-Circuit Emulation") Mode facilitates
testing and debugging of systems using the
With an external interrupt, INTO and INT1 must be 83C51FA without the 83C51FA having to be re-
enabled and configured as level-sensitive. Holding moved from the circuit. The ONCE Mode is invoked
the pin low restarts the oscillator but bringing the pin by:
back high completes the exit. Once the interrupt is 1) Pull ALE low while the device is in reset and
serviced, the next instruction to be executed after PSEN is high;
RETI will be the one following the instruction that put
the device into Power Down. 2) Hold ALE low as RST is deactivated.
While the device is in ONCE Mode, the Port 0 pins
go into a float state, and the other port pins and ALE
DESIGN CONSIDERATION and PSEN are weakly pulled high. The oscillator cir-
• When the idle mode is terminated by a hardware cuit remains active. While the 83C51 FA is in this
reset, the device normally resumes program exe- mode, an emulator or test CPU can be used to drive
cution, from where it left off, up to two machine the circuit. Normal operation is restored when a nor-
cycles before the internal reset algorithm takes mal reset is applied.
control, On-chip hardWare inhibits access to inter-
Table 1. Status of the External Pins during Idle and Power Down
Program
Mode ALE PSEN PORTO PORT1 PORT2 PORT3
Memory
Idle Internal 1 1 Data Data Data Data
Idle External 1 1 Float Data Address Data
Power Down Internal 0 0 Data Data Data Data
Power Down External 0 0 Float Data Data Data
NOTE:
For more detailed information on the reduced power modes refer to current Embedded Controller Handbook, and Applica-
tion Note AP-252, "Designing with the 80C51 BH."
8-109
inter 83C51FA/80C51FA
ABSOLUTE MAXIMUM RATINGS* NOTICE: This data sheet contains preliminary infor-
mation on new products in production. The specifica-
Ambient Temperature Under Bias. ; .. O°C to + 70°C tions are subject to change without notice.
Storage Temperature .. , ....... - 65°C to + 150°C • WARNING: Stressing the device beyond the "Absolute
Voltage on EA/vpp Pin to Vss ........ OV to + 6.5V Maximum Ratings" may cause permanent damage.
These. are stress ratings only. Operation beyond the
Voltage on Any Other Pin to Vss .. - 0.5V to + 6.5V "Operating Conditions" is not recommended and ex-
IOL per 1/0 Pin .... : ...................... 15 mA tended exposure beyond the "Operating Conditions"
may affect device reliability.
Power Dissipation .......................... 1.5W
(based on PACKAGE heat transfer limitations, not
device power consumption)
D.C. CHARACTERISTICS: TA = O°Cto + 70°C; Vee = 5V ±10%;Vss = OV
Typical
Symbol Parameter Min Max Unit Test Conditions
(Note 4)
IvIL Input Low Voltage (Except EA) -0.5 0.2Vee- 0.1 V
1v1L1 Input Low Voltage EA 0 0.2Vee- 0.3 V
IvIH Input High Voltage 0.2 Vee+0.9 Vee+ 0.5 V
(Except XTAL 1, RST)
VIH1 Input High Voltage 0.7 Vee Vee + 0.5 V
(XTAL 1, RST)
VOL Output Low Voltage (Note 5) . 0.3 V IOL = 100 /LA
(Ports 1, 2 and 3) 0.45 V IOL = 1.6 mA (Note 1)
1.0 V IOL = 3.5 mA
VOL1 Output Low Voltage (Note 5) 0.3 V IOL = 200/LA
(Port 0, ALE/PROG, PSEN) 0.45 V IOL = 3.2 mA (Note 1)
1.0 V IOL = 7.0 mA
VOH Output High Voltage Vee- 0.3 V IOH = -10/LA
(Ports 1, 2 and 3 Vee- 0.7 V IOH = -30/LA (Note 2)
ALE and PSEN) Vee- 1.5 V IOH = -60/LA
VOH1 Output High Voltage Vee- 0.3 V IOH = - 200 /LA
(Port 0 in External Bus Mode) Vee- 0.7 V IOH = -3.2mA (Note 2)
Vee-1.5 V IOH = -7.0 mA
IlL Logical 0 Input Current -10 -50 /LA VIN = 0.45V
(Ports 1, 2, and 3)
III Input leakage Current 0.02 ±10 /LA 0.45 < VIN < Vee
(Port 0 and EA)
ITL Logical 1 to 0 Transition Current -265 -650 /LA VIN = 2V
(Ports 1, 2, and 3)
RRST RST Pulldown Resistor 40 100 225 K!l
CIO Pin Capacitance 10 pF @1MHz,25°C
Icc Power Supply Current:
Running at 12 MHz (Figure 5) 15 30 mA
(Note 3)
Idle Mode at 12 MHz (Figure 5) 5 7.5 mA
Power Down Mode 5 75 /LA
8-110
83C51FA/80C51FA
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports
1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to
o transitions during bus operations. In applications where capacitance loading exceeds 100 pFs, the noise pulse on the ALE
signal may exceed 0.8V. In these cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an Address Latch
with a Schmitt Trigger Strobe input. .
2. Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the 0.9 VCC specification when the
address lines are stabilizing.
3. See Figures 6-9 for test conditions. Minimum VCC for power down is 2V.
4. Typicals are based on limited number of samples, and are not guaranteed. The values listed are at room temperature and
5V.
5. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port -
Port 0: 26' rnA
Ports 1, 2, and 3: 15 mA
Maximum total IOL for all output pins: 71 rnA
If IOL exceeds the test condition, VOL may exceed the related specification. 'Pins are not guaranteed to sink current greater
than the listed test conditions.
~~r-------,-------~--------r-----~
Vee
30~ 1-------+-----+----::7/"""----1
vce
RST
20~ 1----+--~4-__:==1--=.....-l
83C51FA
XTAL2
XTALt
vss
4MHz 8MHz 12MHz 16MHz
270538-5 270538-6
All other pins disconnected
ICC Max at other frequencies is given by:
Active Mode
TCLCH = TCHCL = 5 ns
IcC MAX = 2.2 x FREQ + 3.1
Idle Mode Figure 6. Icc Test Condition, Active Mode
Icc MAX = 0.49 x FREQ + 1.6
Where FREQ is in MHz. IccMAX is given in rnA.
Figure 5. Icc vs Frequency
Vec
PO
Vce RST EA
.....--v-
ee... llec Vee 83C51FA
PO ¢:::I XTAl2
XTAL1
Rsr EA Vss
83C51FA
270538-8
XTAL2 . All other pins disconnected
XTAL1
Vss
Figure 8. Icc Test Condition, Power Down Mode.
270538-7 Vcc = 2.0V to 6.0V.
All other pins disconnected
TCLCH = TCHCL = 5 ns
Figure 7. Icc Test Condition Idle Mode
270538-9
Figure 9. Clock Signal Waveform for Icc Tests in Active and Idle Modes. TCLCH = TCHCL = 5 ns.
8-111
intJ 83C51FA/80C51FA
EXPLANATION OF THE AC SYMBOLS L: Logic level LOW, or ALE
P:PSEN
Each timing symbol has 5 characters. The first char- Q: Output Data
acter is always a 'r (stands for time). The other R: RD signal
characters, depending on their positions, stand for T: Time
the name of a signal or the logical status of that V: Valid
signal. The following is a list of all the characters and W: WR signal
what they stand for. X: No longer a valid logic level
Z: Float
A: Address
C: Clock For example,
D: Input Data
H: Logic level HIGH TAVLL = Time from Address Valid to ALE Low
I: Instruction (program memory contents) TLLPL = Time from ALE Low to PSEN Low
• I ' •
A.C. CHARACTERISTICS TA = O°C to + 70"C, Vee = 5V ± 20%, Vss = OV, Load Capacitance for
Port 0, ALE and PSEN = 100 pF, Load Capacitance for All Other Outputs = 80 pF
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
12 MHz Oscillator Variable Oscillator
Symbol Parameter Units
Min Max Min Max
1/TCLCL Oscillator Frequency
83C51FA 3.5 12 MHz
83C51FA-1 3.5 16
83C51FA-2 0.5 12
TLHLL ALE Pulse Width 127 2TCLCL-40 ns
TAVLL Address Valid to ALE Low 43 TCLCL-40 ns
TLLAX Address Hold After ALE Low 53 TCLCL-30 ns
TLLlV ALE Low to Valid Instruction In 234 4TCLCL-100 ns
TLLPL ALE Low to PSEN Low 53 TCLCL-30 ns
TPLPH PSEN Pulse Width 205 3TCLCL-45 ns
TPLIV PSEN Low to Valid Instruction In 145 3TCLCL-105 ns
TPXIX Input Instruction Hold After PSEN 0 0 ns
TPXIZ Input Instruction Float After PSEN 59 TCLCL-25 ns
TAVIV Address to Valid Instruction In 312 5TCLCL-105 ns
TPLAZ PSEN Low to Address Float 10 10 ns
TRLRH RD Pulse Width 400 6TCLCL-100 ns
TWLWH WR Pulse Width 400 6TCLCL-100 ns
TRLDV RD Low to Valid Data In 252 5TCLCL-165 ns
TRHDX Data Hold After RD 0 0 ns
TRHDZ Data Float After RD 107 2TCLCL-60 ns
TLLDV ALE Low to Valid Data In 517 8TCLCL-150 ns
TAVDV Address to Valid Data In 585 9TCLCL-165 ns
TLLWL ALE Low to RD or WR Low 200 300 3TCLCL-50 3TCLCL+50 ns
TAVWL Address Valid to RD or WR Low 203 4TCLCL-130 ns
TQVWX Data Valid to WR Transition 33 TCLCL-50 ns
TWHQX Data Hold after WR 33 TCLCL-50 ns
TQVWH Data Valid to WR High 433 7TCLCL-150 ns
TRLAZ RD Low to Address Float 0
, 0 ns
TWHLH RD or WR High to ALE High 43 123 TCLCL-40 TCLCL+40 ns
8-112
infef 83C51 FAl80C51 FA
EXTERNAL PROGRAM MEMORY READ CYCLE
. ALE
---'
PSEN
---'
TPXIZ
PORT a--..I AO-A7
PORT 2 _ _ _J A8- A15
270538-10
EXTERNAL DATA MEMORY READ CYCLE
ALE
PSEN
I------TLLDV '\
---+-1---- TRLRH - - - - 1
RD
PORTO INSTR. IN
PORT 2 P2.0-P2.7 OR A8-A15 FROM DPH A8-A15 FROM PCH
270538-11
8-113
83C51FAl80C51FA
EXTERNAL DATA MEMORY WRITE CYCLE
~TLHLL~
ALE 1 /
4TWHLH
/
,
,
-TLLWL TWLWH
- TAVLL
-
-TLLAX- ~
J
.... t-TWHQX
TQVWH
PORTO
~ FRO.lWj"~k OPl DATA OUT K AO-A7 FROM PCL INSTR. IN
TAVWL
PORT2 ::) P2.0-P2.7 OR A8-AIS FROM DPH A8-A 15 FROM PCH
270538-12
A.C. TESTING INPUT
Input, Output Waveforms Float Waveforms
VCC-O.SVO.2VCC+O.9 V- TIMING REFERENCE
0.45 V~_0_.2_VC::.:C=--_0_.'_ _ _.... A- POINTS
VOL +0.1 V
270538-16
270538-15
For timing purposes a port pin is no longer floating when a
AC Inputs during testing are driven at Vee-0.5V for a Logic "1"
100 mV change from load voltage occurs, and begins to float
and 0.45V for a Logic "0". Timing measurements are made at VIH
min for a Logic "1" and VOL max for a Logic "0". when a 100 mV change from the loaded VOHIVOl level occurs.
IOl/lOH ;" ± 20 rnA.
SERIAL PORT TIMING-SHIFT REGISTER MODE
Test Conditions: TA = ODC to + 70DC; Vee = 5V ± 20%; Vss = OV; Load Capacitance = 80 pF
12 MHz Oscillator Variable OSCillator
Symbol Parameter Units
Min Max Min Max
TXLXL Serial Port Clock Cycle Time 1 12TCLCL /Ls
TOVXH Output Data Setup to Clock 700 1OTCLCL -133 ns
Rising Edge
TXHOX Output Data Hold after 50 2TCLCL-117 ns
Clock Rising Edge
TXHDX Input Data Hold After Clock 0 0 ns
Rising Edge
TXHDV Clock Rising Edge to Input 700 1OTCLCL - 133 ns
Data Valid
8-114
intJ 83C51FA/80C51FA
SHIFT REGISTER MODE TIMING WAVEFORMS
INSTRUCTION I o 2 3 4 5 6 7 8
ALE
CLOCK
OUTPUT DATA 2 X 3 X 4 X 5 X 6 X 7 /
f t
WRITE TO SBUF SET TI
INPUT DATA ----~~~-~ ':":"7:V'-v.-;:~r--V:=",""""",~7:V'-v.-;:~r--v:=",""""",~:::v
f t
CLEAR RI SET RI
270538-13
EXTERNAL CLOCK DRIVE
Symbol Parameter Min Max Units
Oscillator Frequency
83C51 FAl80C51 FA 3.5 12
1/TClCl MHz
83C51 FA-1 180C51 FA-1 3.5 16
83C51 FA-2/80C51 FA-2 0.5 12
TCHCX High Time 20 ns
TClCX low Time 20 ns
TClCH Rise Time 20 ns
TCHCl Fall Time 20 ns
EXTERNAL CLOCK DRIVE WAVEFORM
270538-14
ROM CHARACTERISTICS
Table 2 shows the logic levels for verifying the code data and reading the signature bytes on the 83C51 FA.
Table 2. ROM Modes
Mode RST PSEN ALE EA P2.7 P2.6 P3.6 P3.7
Verify Code Data 1 0 1 1 0 0 1 1
Read Signature 1 0 1 1 0 0 0 0
NOTES:
"1" = Valid high for that pin
"a" = Valid low for that pin
8-115
inter 83C51FA/80C51FA
Program Verification If the Encryption Array in the ROM has been pro-
grammed, the data present at Port 0 will be Code
If the Program Lock Bit has not been programmed, Data XNOR Encryption Data. The user must know
the on-chip Program Memory can be read out for the Encryption Array contents to manually "unen-
verification purposes, if desired. The address of the crypt" the data during verify.
Program Memory location to be read is applied to
Port 1 and pins P2.0-P2.4. The other pins should be Figure 10 shows the setup for verifying the program
held at the "Verify" levels indicated in Table 2. The memory.
contents of the addressed locations will come out
on Port o. External pullups are required on Port 0 for
this operation.
+5V
vee
I----I-~\. PGM
AO-A7 PI PO
t----vDATA
RST EA
ALE
P3.S
PSEN 1+---0
83C51FA
P3.7
P2.7 1+---0 {ENABLE}
XTAL2 P2.S 1+---0
1...--+--;1---1 XTAL 1 _~~:~ I~''''_-_-_-A8::-A 12
vss
270538-17
Figure 10. Verifying the ROM
ROM VERIFICATION CHARACTERISTICS
= SV±O.2SV; Vss = OV
TA = 21°C to 27"C; Vee
ADVANCED INFORMATION-CONTACT INTEL FOR DESIGN-IN INFORMATION
Symbol Parameter Min Max Units
1/TCLCL Oscillator Frequency 4 6 MHz
TAVQV Address to Data Valid 48TCLCL
TELQV ENABLE Low to Data Valid 48TCLCL
TEHQZ Data Float after ENABLE 0 48TCLCL
8-116
83C51FA/80C51FA
ROM VERIFICATION WAVEFORMS Reading the Signature Bytes
The signature bytes are read by the same procedure
VERIFICATION as a normal verification of locations 030H and 031 H,
Pl.0-Pl.7
P2.0-P2.4 ----j1::::=~AD~D~RE~SS~:J)~---
,. ,
except that P3.6 and P3.7 need to be pulled to a
logic low. The values returned are:
-TAVQV
(030H) = 89H indicates manufacture by Intel
PORT 0 -----1JD~A~TA~O~U~T=>_---- (031 H) = 53H indicates 83C51 FA
P2.7
rru"l- ) Lrr,,,
270530-18
DATA SHEET REVISION SUMMARY
The following are the key differences between this and the -002 version of the 83C51 FA/80C51 FA data sheet:
1. Raised Vee max tolerance to 20%.
2. Dropped Program Lock System spec and description.
3. Dropped word "maximum" from IOL in the Absolute Maximum Rating table.
4. Dropped EA from III spec of the D. C. table.
5. Corrected TQVWH spec (from TTCLCL-70 to TCLCL-150).
6. QFP Package was added.
7. Note on external clock capacitance loading was added.
The following are the key differences between the -002 and the -001 version of the 83C51 FA/80C51 FA data
sheet:
1. Data sheet was upgraded from ADVANCE INFORMATION to PRELIMINARY.
2. The old device name (83C252/80C252) was removed from the title.
3. PLCC pin connection diagram was added.
4. Package table was added.
5. Exit from Power Down Mode was clarified.
6. Maximum IOL per 1/0 pin was added to the ABSOLUTE MAXIMUM RATINGS.
7. Note 4 was added to explain the maximum safe current spec.
8. Ipd was improved from 100 p.A to 75 p.A.
9. Typical DC characteristics were added for: IlL, Ill, ITL, RRST, ICC.
10. Note 5 was added to explain the test conditions for typical values.
11. Maximum clock frequency was added to the AC table.
12. Timing spec's improved for:
T AVLL changed from TCLCL - 55 to TCLCL - 40
TLLAX changed from TCLCL - 35 to TCLCL - 30
TLLPL changed from TCLCL - 40 to TCLCL - 30
TRHDZ changed from TCLCL -70 to TCLCL - 60
TQVWX changed from "Address Valid Before WR" to "Data Valid to WR Transition", and changed from
TCLCL - 60 to TCLCL - 50
TQVWH was added.
13. Data sheet revision summary was added.
8-117
83C51 FA/80C51 FA
EXPRESS
83C51FA/80C51FA-3.5 MHz to 12 MHz, Vee = 5V ± 10%
83~51FA-1/80C51FA-1-3.5 MHz to 16 MHz, Vee = 5V ± 10%
83C51FA-2/80C51FA-2-0.5 MHz to 12 MHz, Vee = 5V ± 10%
• Extended Temperature Range • Burn-In
The Intel EXPRESS system offers enhancements to the operational specifications of the MCS®-51 family of
microcontrollers. These EXPRESS products are designed to meet the needs of those applications whose
operating requirements exceed commercial standards.
The EXPRESS program includes the commercial standard temperature range with burn-in and an extended
temperature range with or without burn-in.
With the commercial standard temperature range, operational characteristics are guaranteed over the temper-
ature range of O·C to 70·C. With the extended temperature range option, operational characteristics are
guaranteed over the range of. - 40·C to + 85·C.
The optional burn-in is dynamic for a minimum time of 168 hours at 125·C with Vee = 6.9V ±0.25V, following
guidelines in MIL-STD-883, Method 1015.
Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part number. The
prefixes are listed in Table 1.
For the extended temperature range option, this data sheet specifies the parameters which deviate from their
commercial temperature range limits. The commercial temperature range data sheets. are applicable for all
parameters not listed here. .
August 1988
8-118 Order Number: 270620-001
inter 83C51FAl80C51FA EXPRESS
Electrical Deviations from Commercial Specifications for Extended Temperature
Range
D.C. and A.C. parameters not included here are the same as in the commercial temperature range data
sheets.
D.C. CHARACTERISTICS TA = -40°C to + 85°C; VCC = 5V ± 10%; Vss = OV
Limits Test
Symbol Parameter Unit
Min Max Conditions
IlL Logical 0 Input Current (Port 1, 2, 3) -75 !J-A Vin = 0.45V
VOH1 Output High Voltage VCC -1.5 V IOH = -6.0 mA
(Port 0 in External Bus Mode)
Table 1. Prefix Identification
Prefix Package Type Temperature Range Burn-In
P Plastic Commercial No
0 Cerdip Commercial No
N PLCC Commercial No
TP Plastic Extended No
TO Cerdip Extended No
TN PLCC Extended No
LP Plastic Extended Yes
LD Cerdip Extended Yes
LN PLCC Extended Yes
NOTE:
• Commercial temperature range is O°C to 70°C. Extended temperature range is - 40°C to + 85°C.
• Burn-in is dynamic for a minimum time of 168 hours at 125°C. Vee = 6.9V ±0.25V, following guidelines in MIL-STD-883
Method 1015 (Test Condition D).
Examples:
P83C51 FA indicates 83C51 FA in a plastic package and specified for commercial temperature range, without
burn-in.
LD80C51 FA indicates 80C51 FA in a cerdip package and specified for extended temperature range with burn-
in.
8-119
87C51FA
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
8K BYTES USER PROGRAMMABLE EPROM
87CS1FA-3.S MHz to 12 MHz, Vee SV ± 10%
87CS1FA-1-3.S MHz to 16 MHz, Vee 5V ± 10%
• High Performance CHMOS EPROM • 32 Programmable I/O Lines
• Power Control Modes • 7 Interrupt Sources
• Three 16-Bit Timer/Counters • Programmable Serial Channel with:
• Programmable Counter Array with: - Framing Error Detection
- High Speed Output, - Automatic Address Recognition
- Compare/Capture, • TTL Compatible Logic Levels
- Pulse Width Modulator, • 64K External Program Memory Space
- Watchdog Timer capabilities
• 64K External Data Memory Space
• Up/Down Timer/Counter
• MCS®-51 Compatible Instruction Set
• Two Level Program Lock System
• Power Saving Idle and Power Down
• 8K On-Chip EPROM Modes
• 256 Bytes of On-Chip Data RAM • ONCETM (On-Circuit Emulation) Mode
• Quick Pulse Programming™ Algorithm
• Boolean Processor
MEMORY ORGANIZATION
PROGRAM MEMORY: Up to 8K bytes of the program memory can reside in the on·chip EPROM. In addition
the device can address up to 64K of program memory external to the chip.
DATA MEMORY: This microcontrolier has a 256 x 8 on-chip RAM. In addition it can address up to 64K bytes of
external data memory.
The Intel 87C51 FA is a single·chip control oriented microcontrolier which is fabricated on Intel's reliable
CHMOS II-E technology. Being a member of the MCS®·51 family, the 87C51 FA uses the same powerful
instruction set, has the same architecture, and is pin for pin compatible with the existing MCS-51 products. The
87C51 FA is an enhanced version of the 87C51. It's added features make it an even more powerful microcon-
troller for applications that require Pulse Width Modulation, High Speed I/O, and up/down counting capabili-
ties such as motor control. It also has a more versatile serial channel that facilitates multi-processor communi-
cations.
October 1989
8-120 Order Number: 270258-004
intJ 87C51FA
PO.O-PO.7
V r - - - - - - - - - - --,
Vss
~
..r
z
n~~~G ~ mlJL---""'---=--'----.1...J'---~--J....I----...J
PSEN
ALE/1'RlR:
rJ./VPP CONTROL i!: !31'\r------.,.,.-------..,-,r-----..,-,-----",.----,/
RST "'0<
;;;
Pl.O- Pl.7 P3.0-P3.7
270258-1
Figure 1. 87C51FA Block Diagram
8-121
inter 87C51FA
PACKAGES Port 0: Port 0 is an 8-bit, open drain, bidirectional 1/0
port. As an output port each pin can sink several LS
Part Prefix Package Type TTL inputs. Port 0 pins that have 1's written to them
float, and in that state can be used as high-imped-
8?CS1FA P 40-Pin Plastic DIP
ance inputs.
0 40-Pin CERDIP
N 44-PIN PLCC Port 0 is also the multiplexed low-order address and
data bus during accesses to external Program and
Data Memory. In this application it uses strong inter-
nal pullups when emitting 1's, and can source and
(T2) PLO Vcc sink several LS TTL inputs.
(T2EX) Pl.l po.o (AOO)
(ECI) Pl.2 3 PO.l (AD1) Port 0 also receives the code bytes during EPROM
(CEXO) Pl.3 PO.2 (AD2) programming, and outputs the code bytes during
(CEX1) Pl.4 PO.3 (AD3) program verification. External pullup resistors are re-.
(CEX2) PI.S S PO.4 (AD4) qui red during program verification.
(CEX3) Pl.S 7 PO.S (ADS)
(CEX4) Pl.7 B PO.S (ADS)
Port 1: Port 1 is an 8-bit bidirectional 1/0 port with
RESET PO.7 (AD7)
internal pullups. The Port 1 output buffers can drive
(RXD) P3.0 EA/Vpp
LS TTL inputs. Port 1 pins that have 1's written to
(TXD) P3.l ALE/PROG
them are pulled high by the internal pullups, and in
(ii'ffii) P3.2 PSEN
(lNT1) P3.3 P2.7 (A1S)
that state can be used as inputs. As inputs, Port 1
(TO) P3.4 P2.S (A14)
pins that are externally being pulled low will source
(T1) P3.S P2.S (A13)
current (IlL, on the data sheet) because of the inter-
(Viii) P3.S P2.4 (A12)
nal pullups.
(Rli) P3.7 P2.3 (All)
XTAL2 P2.2 (Al0) In addition, Port 1 serves the functions of the follow-
XTALl P2.l (A9) ing special features of the 8?CSI FA:
Vss P2.0 (AB)
270258-2 Port Pin Alternate Function
DIP P1.0 T2 (External Count Input to Timerl
. Counter 2)
INDEX
CORNER
~i~~i~~~~~~ P1.1 T2EX (Timer/Counter 2 Capturel
Reload Trigger and Direction Control)
PO.4 Pl.2 ECI (External Count Input to the PCA)
PO.S
Pl.3 CEXO (External 1/0 for Comparel
PO.S
Capture Module 0)
RST PO.7
EA/Vpp P1.4 CEX1 (External 1/0 for Comparel
NC NC Capture Module 1)
P3.l ALE/PROG P1.S CEX2 (External 1/0 for Comparel
P3.2 PSEN Capture Module 2)
P3.3 P2.7
P3.4 P2.S P1.6 CEX3 (External 1/0 for Comparel
P2.S Capture Module 3)
P1.? CEX4 (External 1/0 for Comparel
..... e e
..; "•
~
N
-' ....
..J en
en
> ~ ~ ~ ~ ~ ~
Capture Module 4)
270258-23 Port 1 receives the low-order address bytes during
PAD EPROM programming and verifying.
Figure 2•.Pin Connections Port 2: Port 2 is an 8-bit bidirectional 1/0 port with
internal pullups. The Port 2 output buffers can drive
LS TTL inputs. Port 2 pins that have 1's written to
PIN DESCRIPTIONS them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 2
Vee: Supply voltage. pins that are externally being pulled low will source
current (Ill> on the data sheet) because of the inter-
Vss: Circuit ground. nal pullups.
8-122
inter 87C51FA
Port 2 emits the high-order address byte during When the 87C51 FA is executing code from external
fetches from external Program Memory and during Program Memory, PSEN is activated twice each ma-
accesses to external Data Memory that use 16-bit chine cycle, except that two PSEN activations are
addresses (MOVX @DPTR). In this application it skipped during each access to external Data Memo-
uses strong internal pull ups when emitting 1'so Dur- ry.
ing accesses to external Data Memory that use 8-bit
addresses (MOVX @Ri), Port 2 emits the contents of EA/vpp: External Access enable. EA must be
the P2 Special Function Register. strapped to VSS in order to enable the device to
fetch code from external Program Memory locations
Some Port 2 pins receive the high-order address bits OOOOH to OFFFH. Note, however, that if either of the
during EPROM programming and program verifica- Program Lock bits are programmed, EA will be inter-
tion. nally latched on reset.
Port 3: Port 3 is an 8-bit bidirectional 1/0 port with EA should be strapped to Vee for internal program
internal pullups. The Port 3 output buffers can drive executions.
LS TTL inputs. Port 3 pins that have 1's written to
them are pulled high by the internal pullups, and in This pin also receives the programming supply volt-
that state can be used as inputs. As inputs, Port 3 age (Vpp) during EPROM programming.
pins that are externally being pulled low will source
XTAL 1: Input to the inverting oscillator amplifier.
current (IlL, on the data sheet) because of the pull-
ups. XTAL2: Output from the inverting oscillator amplifier.
Port 3 also serves the functions of various special
features of the MCS-51 Family, as listed below: OSCILLATOR CHARACTERISTICS
XT AL 1 and XT AL2 are the input and output, respec-
Port Pin Alternate Function tively, of a inverting amplifier which can be config-
P3.0 RXD (serial input port) ured for use as an on-chip oscillator, as shown in
P3.1 TXD (serial output port) Figure 3. Either a quartz crystal or ceramic resonator
P3.2 INTO (external interrupt 0) may be used. More detailed information concerning
the use of the on-chip oscillator is available in Appli-
P3.3 INT1 (external interrupt 1) cation Note AP-155, "Oscillators for Microcontrol-
P3.4 TO (Timer 0 external input) lers."
P3.5 T1 (Timer 1 external input)
P3.6 WR (external data memory write strobe) To drive the device from an external clock source,
P3.7 RD (external data memory read strobe) XT AL 1 should be driven, while XTAL2 floats, as
shown in Figure 4. There are no requirements on the
duty cycle of the external clock signal, since the in-
RST: Reset input. A high on this pin for two machine·
put to the internal clocking circuitry is through a di-
cycles while the oscillator is running resets the de-
vide-by-two flip-flop, but minimum and maximum
vice. An internal pulldown resistor permits a power-
high and low times specified on the data sheet must
on reset with only a capacitor connected to Vee.
be observed.
ALE: Address Latch Enable output pulse for latching An external oscillator may encounter as much as a
the low byte of the address during accesses to ex- 100 pF loa9 at XT AL1 when it starts up. This is due
ternal memory. This pin (ALE/PROG) is also the to interaction between the amplifier and its feedback
program pulse input during EPROM programming for capacitance. Once the external signal meets the VIL
the 87C51 FA. and VIH specifications the capacitance will not ex-
ceed 20 pF.
In normal operation ALE is emitted at a constant
rate of Ys the oscillator frequency, and may be used
2
~
for external timing or clocking purposes. Note, how-
ever, that one ALE pulse is skipped during each ac- . 0 XTAL2
cess to external Data Memory.
Cl
XTAL 1
Throughout the remainder of this data sheet, ALE
Vss
will refer to the signal coming out of the ALE/PROG
phi, and the pin will be referred to as the ALE/PROG 270258-3
pin. C1, C2 = 30 pF ± 10 pF for Crystals
= 10 pF for Ceramic Resonators
PSEN: Program Store Enable is the read strobe to
Figure 3. Oscillator Connections
external Prograr:n Memory.
8-123
inter 87C51FA
With an external interrupt, INTO and INT1 must be
enabled and configured as level-sensitive. Holding
N/C XTAL2 the pin low restarts the oscillator but bringing the pin
back high completes the exit. Once the interrupt is
serviced, the next instruction to be executed after
EXTERNAL
XTAL 1
RETI will be the one following the instruction that put
OSCILLATOR
SIGNAL the device into Power Down.
vss
DESIGN CONSIDERATION
270258-4 • Ambient light is known to affect the internal RAM
contents during operation. If the 87C51 FA appli-
Figure 4. External Clock Drive Configuration cation requires the part to be run under ambient
lighting, an opaque label should be placed over
IDLE MODE the window to exclude light.
• When the idle mode is terminated by a hardware
The user's software can invoke the Idlei Mode. When reset, the device normally resumes program exe-
the microcontroller is in this mode, power consump- cution, from where it left off, up to two machine
tion is reduced. The Special Function Registers and cycles before the internal reset algorithm takes
the onboard RAM retain their values during Idle, but control. On-chip hardware inhibits access to inter-
the processor stops executing instructions. Idle nal RAM in this event, but access to the port pins
Mode will be exited if the chip is reset or if an en- is not inhibited. To eliminate the possibility of an
abled interrupt occurs. The PCA timer/counter can unexpected write when Idle is terminated by re-
optionally be left running or paused during Idle set, the instruction following the one that invokes
Mode. Idle should not be one that writes to a port pin or
to external memory.
POWER DOWN MODE
ONCETM MODE
To save even more power, a Power Down mode can
be invoked by software. In this mode, the oscillator The ONCE ("On-Circuit Emulation") Mode facilitates
is stopped and the instruction that invoked Power testing and debugging of systems using the
Down is the last instruction executed. The .on-chip 87C51 FA without the 87C51 FA having to be re-
RAM and Special Function Registers retain their val- moved from the circuit. The ONCE Mode is invoked
ues until the Power Down mode is terminated. by:
1) Pull ALE low While the device is in reset and
On the 87C51 FA either hardware reset or external
PSEN is high;
interrupt can cause an exit from Power Down. Reset
redefines all the SFRs but does not change the on- 2) Hold ALE low as RST is deactivated.
chip RAM. An external interrupt allows both the
SFRs and the on-chip RAM to retain their values. While the device is in ONCE Mode, the Port 0 pins
go into a float state, and the other port pins and ALE
To properly terminate Power Down the reset or ex- and PSEN are weakly pulled high. The oscillator cir-
ternal interrupt should not be executed before VCC is cuit remains active. While the 87C51 FA is in this
restored to its normal operating level and must be mode, an emulator or test CPU can be used to drive
held active long enough for the oscillator to restart the circuit. Normal operation is restored when a nor-
and stabilize (normally less than 10 ms). mal 'reset is applied.
Table 1. Status of the External Pins during Idle and Power Down
Program
Mode ALE PSEN PORTO PORT1 PORT2 PORT3
Memory
Idle Internal 1 1 Data Data Data Data
Idle External 1 1 Float Data Address Data
Power Down Internal 0 0 Data Data Data Data
Power Down External 0 0 Float Data Data Data
NOTE: .
For more detailed information on the reduced power modes refer to current Embedded Controller Handbook, and Applica-
tion Note AP-252,"Designing with the 80C51 BH."
8-124
inter 87C51FA
ABSOLUTE MAXIMUM RATINGS* NOTICE: This data sheet contains preliminary infor-
mation on new products in production. The specifica-
Ambient Temperature Under Bias .... O°C to + 70°C tions are subject to change without notice.
Storage Temperature .......... - 65°C to + 150°C * WARNING: Stressing the device beyond the "Absolute
Voltage on EA/vpp Pin to Vss ....... OV to + 13.0V Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
Voltage on Any Other Pin to V ss .. - O.5V to + 6.5V "Operating Conditions" is not recommended and ex-
IOL per I/O Pin ........................... 15 mA tended exposure beyond the "Operating Conditions"
Power Dissipation .......................... 1.5W may affect device reliability.
(based on PACKAGE heat transfer limitations, not
device power consumption)
D.C. CHARACTERISTICS: (TA = O°Cto + 70°C; Vee = 5V ±10%;Vss = OV)
Typical
Symbol Parameter Min Max Unit Test Conditions
(Note 4)
Vil Input Low Voltage -0.5 0.2Vee- 0.1 V
VIL1 Input Low VoltageEA 0 0.2 Vee-0.3 V
VIH Input High Voltage 0.2Vee+ 0.9 Vee+ 0.5 V
(Except XT AL 1, RST)
VIH1 Input High Voltage 0.7 Vee Vee+ 0.5 V
(XTAL1, RST)
VOL Output Low Voltage (Note 5) 0.3 V IOl = 100,.,.A
(Ports 1, 2 and 3) 0.45 IOl = 1.6 mA (Note 1)
1.0 IOl = 3.5mA
VOL1 Output Low Voltage (Note 5) 0.3 V IOL = 200,.,.A
(Port 0, ALE/PROG, PSEN) 0.45 IOl = 3.2 mA (Note 1)
1.0 IOl = 7.0 mA
VOH Output High Voltage Vee - 0.3 V IOH = -10,.,.A
(Ports 1, 2 and 3 Vee -0.7 V IOH = - 30 ,.,.A (Note 2)
ALE/PROG and PSEN) Vee -1.5 V IOH = -60,.,.A
VOH1 Output High Voltage Vee -0.3 V IOH = -200,.,.A
(Port 0 in External Bus Mode) Vee -0.7 V IOH = -3.2 mA (Note 2)
Vee -1.5 V IOH = -7.0 mA
III Logical 0 Input Current -10 -50 ,.,.A VIN = 0.45V
(Ports 1, 2, and 3)
III Input leakage Current 0.02 ±10 ,.,.A VIN = Vil or VIH
(Port 0)
III Logical 1 to 0 Transition Current -265 -650 ,.,.A VIN = 2V
(Ports 1, 2, and 3)
RRST RST Pulldown Resistor 40 100 225 Kn
CIO Pin Capacitance 10 pF @1MHz,25°C
lee Power Supply Current: (Note 3)
Running at 12 MHz (Figure 5) 15 30 mA
Idle Mode at 12 MHz (Figure 5) 5 7.5 mA
Power Down Mode 5 75 ,.,.A
8-125
inter 87C51FA
NOTES:
1. Capacitive loading on Ports 0 and 2 may causespurious noise pulses to be superimposed on the VOLS of ALE and Ports
1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to
o transitions during bus operations. In applications where capacitance loading exceeds 100 pFs, the noise pulse on the ALE
signal may exceed O.BV. In these cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an Address Latch
with a Schmitt Trigger Strobe input.
2. Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the 0.9 VCC specification when the
address lines are stabilizing.
3. See Figures 6-9 for test conditions. Minimum VCC for power down is 2V.
4. Typicals are based on limited number of samples, and are not guaranteed. The values listed are at room temperature and 5V.
5. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: lOrnA
Maximum IOL per B-bit port -
Port 0: 26 rnA
Ports I, 2, and 3: 15 rnA
Maximum total IOL for all output pins: 71 rnA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
-lOrnA
MAX. Vee
30rnA
2DrnA
AcnVE V Vee
...V_ ~
TYPICAL
87e51rA
lOrnA
DrnA
-- "'-,OLE MAX.
TYPICAL
XTAL2
XTAL1
Vss
OMHz 4MHz 8MHz 12lro4Hz 16MHz
270258-5
270258-6
IcC Max at other frequencies is given by: All other pins disconnected
Active Mode TCLCH ~ TCHCL ~ 5 ns
Icc MAX ~ '2.2 X FREQ + 3.1
Idle Mode
ICC MAX ~ 0.49.x FREQ + 1.6 Figure 6. Icc Test Condition, Active Mode
Where FREQ is in MHz, 'cCMAX is given in rnA.
Figure 5. Icc vs Frequency
vce
PO
EA RST
87C51rA 87C252
XTAL2 XTAL2
XTAL1 XTAL1
SIGNAL
Vss vss
270258-7 270258-8
All other pins disconnected All other pins disconnected
TCLCH ~ TCHCL ~ 5 ns
Figure 8. ICC' Test Condition, Power Down Mode.
Figure 7. Icc Test Condition Idle Mode Vcc = 2.0V to 5.SV.
Vcc-O.s· - - - - - - " . . - - - - - -
0.7 VCC
D.45V---"(D.2 VCC-D.t
TCHCL
270258-19
Figure 9. Clock Signal Waveform for Icc Tests in Active and Idle Modes. TCLCH = TCHCL = 5 ns.
8-126
inter 87C51FA
EXPLANATION OF THE AC SYMBOLS L: Logic level LOW, or ALE
P: PSEN
Each timing symbol has 5 characters. The first char- Q: Output Data
acter is always a 'T' (stands for time). The other R: RD signal
characters, depending on their positions, stand for T: Time
the name of a signal or the logical status of that V: Valid
signal: The following is a list of all the characters and W: WR signal
what they stand for. X: No longer a valid logic level
Z: Float
A: Address
C: Clock For example,
0: Input Data
H: Logic level HIGH TAVLL = Time from Address Valid to ALE Low
I: Instruction (program memory contents) TLLPL = Time from ALE Low to PSEN Low
A.C. CHARACTERISTICS (TA = O°C to + 70°C, Vee = 5V ± 10%, Vss = OV, Load Capacitance for
Port 0, ALE/PROG and PSEN = 100 pF, Load Capacitance for All Other Outputs = 80 pF)
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
12 MHz Oscillator Variable Oscillator
Symbol Parameter Units
Min Max Min Max
1 Oscillator Frequency
- - 87C51FA 3.5 12 MHz
TCLCL
87C51FA-1 3.5 16 MHz
TLHLL ALE Pulse Width 127 2TCLCL-40 ns
TAVLL Address Valid to ALE Low 43 TCLCL-40 ns
TLLAX Address Hold After ALE Low 53 TCLCL-30 ns
TLLlV ALE Low to Valid Instruction In 234 4TCLCL-100 ns
TLLPL ALE Low to PSEN Low 53 TCLCL-30 ns
TPLPH PSEN Pulse Width 205 3TCLCL-45 ns
TPLIV PSEN Low to Valid Instruction In 145 3TCLCL-105 ns
TPXIX Input Instruction Hold After PSEN 0 0 ns
TPXIZ Input Instruction Float After PSEN 59 TCLCL-25 ns
TAVIV Address to Valid Instruction In 312 5TCLCL-105 ns
TPLAZ PSEN Low to Address Float 10 10 ns
TRLRH RD Pulse Width 400 6TCLCL-100 ns
TWLWH WR Pulse Width 400 6TCLCL-100 ns
TRLDV RD Low to Valid Data In 252 5TCLCL-165 ns
TRHDX Data Hold After RD 0 0 ns
TRHDZ Data Float After RD 107 2TCLCL-60 ns
TLLDV ALE Low to Valid Data In 517 8TCLCL-150 ns
TAVDV Address to Valid Data In 585 9TCLCL-165 ns
TLLWL ALE Low to RD or WR Low 200 300 3TCLCL-50 3TCLCL+50 ns
TAVWL Address Valid to WR Low 203 4TCLCL-130 ns
TQVWX Data Valid to WR Transition 33 TCLCL-50 ns
TWHQX Data Hold after WR 33 TCLCL-50 ns
TQVWH Data Valid to WR High 433 . 7TCLCL -150 ns
TRLAZ RD Low to Address Float 0 0 ns
TWHLH RD or WR High to ALE High 43 123 TCLCL-40 TCLCL+40 ns
8-127
inter 87C51FA
EXTERNAL PROGRAM MEMORY READ CYCLE
ALE _ _J
PSEN _ _J
TPXIZ
PORT 0 AO-A7
----'
PORT 2 A8-A15
--,---'
270258-9
EXTERNAL DATA MEMORY READ CYCLE
ALE
PSEN
I------TLLDV 'I
----0-1---- TRLRH - - - I
RD
PORTO INSTR. IN
PORT2 P2.0-P2.7 OR A8-A15 FROM DPH AB-A15 FROM PCH
270258-10
EXTERNAL DATA MEMORY WRITE CYCLE
ALE
, I \. ~
-TLHLL- 4TWHLH
- TAVLL
I----- TLLWL
- , TWLWH
I
-TLLAX- ~ .- -TWHOX
TOVWH
PORTO
::>-- FROt.t~i~~ DPL
TAVWL
DATA OUT XAO-A7 FROM PCL INSTR. IN
PORT2
::J P2.0-P2.7 OR A8-A15 FROM DPH A8-A15 FROM PCH
270258-11
8-128
inter 87C51FA
SERIAL PORT TIMING - SHIFT REGISTER MODE
Test Conditions: T A = O'C to + 70'C; Vee = 5V ± 10%; Vss = OV; Load Capacitance = 80 pF
12 MHz Oscillator Variable Oscillator
Symbol Parameter Units
Min Max Min Max
TXLXL Serial Port Clock Cycle Time 1 12TCLCL !-,-S
TQVXH Output Data Setup to Clock 700 1OTCLCL -133 ns
Rising Edge
TXHQX Output Data Hold after 50 2TCLCL-117 ns
Clock Rising Edge
TXHDX Input Data Hold After Clock 0 0 ns
Rising Edge
TXHDV Clock Rising Edge to Input 700 1OTCLCL -133 ns
Data Valid
SHIFT REGISTER MODE TIMING WAVEFORMS
INSTRUCTION I 0 2 3 4 5 6 7 8
ALE
CLOCK
OUTPUT DATA
'--...;..~ '--..;..~ \.-"';"--IX 3 X 4 X 5 X 6 X 7 "
I
WRITE TO SBUF SET TI
INPUT OATA -----...=-.~-~':':':~-~~r_~=.r_~':'!":"::!.r_"""\..~~~~~-U7:~
I t
CLEAR RI SET RI
270258-12
EXTERNAL CLOCK DRIVE
Symbol Parameter Min Max Units
1/TCLCL Oscillator Frequency
87C51FA 3.5 12 MHz
87C51FA-1 3.5 16 MHz
TCHCX High Time 20 ns
TCLCX Low Time 20 ns
TCLCH Rise Time 20 ns
TCHCL Fall Time 20 ns
EXTERNAL CLOCK DRIVE WAVEFORM
270258-13
8-129
intJ 87C51FA
A.C. TESTING INPUT
Input, Output Waveforms Float Waveforms
VCC-0.5~0.2VCC+0.9 V- TIMING REFERENCE
POINTS
0.45 V --.I\_0_.2_V=:CC::..-_0_.1_ _ _ ~"'- VOL +0.1 V
270258-15
270258-14
For liming purposes a port pin is no longer floating when a
AC Inputs during testing are driven at Vee - 0.5V for a Logic "1" 100 mV change from load voltage occurs. and begins to float
and 0.45V for a Logic "0". Timing measuroments are made at VIH whon a 100 mV change from the loaded VOHIVOL level occurs.
min for a Logic "1" and VOL max for a Logic "0", IOLlioH <: ± 20 mAo
EPROM CHARACTERISTICS
Table 2 shows the logic levels for programming the
Program Memory, the Encryption Table, and the
Lock Bits and for reading the signature bytes.
Table 2. EPROM Programming Modes
ALE! EAt
Mode RST PSEN P2.7 P2.S P3.S P3.7
PROG Vpp
Program Code Data 1 0 O' Vpp 1 0 1 1
Verify Code Data 1 0 1 1 0 0 1 1
Program Encryption Table 1 0 O' Vpp 1 0 0 1
Use Addresses 0-1 FH
Program Lock x=1 1 0 O' Vpp 1 1 1 1
Bits (LBx) x=2 1 0 O' Vpp 1 1 0 0
Read Signature 1 0 1 1 0 0 0 0
NOTES:
"1" = Valid high for that pin
'0" = Valid low for that pin
"VPP" = + 12.75V ±0.25V
• ALE/PROG is pulsed low for 100 JLs for programming. (Quick-Pulse Pragramming™)
PROGRAMMING THE EPROM Normally EAlVpp is held at logic high uf!!!!...iust be-
fore ALE/PROG is to be pulsed. Then EAlVpp is
To be programmed, the part must be running with a raised to Vpp, ALE/PROG is pulsed low, and then
4 to 6 MHz oscillator. (The reason the oscillator EAlVpp is returned to a valid high voltage. The volt-
needs to be running is that the internal bus is being age on the EAlVpp pin must be at the valid EAlVpp
used to transfer address and program data to appro- high level before a verify is attempted. Waveforms
priate internal EPROM locations.) The address of an and detailed timing specifications are shown in later
EPROM location to be programmed is applied to sections of this data sheet.
Port 1 and pins P2.0 - P2.4 of Port 2, while the code
byte to be programmed into that location is applied Note that the EAlVpp pin must not be allowed to go
to Port O. The other Port 2 and 3 pins, RST PSEN, above the maximum specified Vpp level for any
and EAlVpp should be held at the "Program" levels amount of time. Even a narrow glitch above that volt-
indicated in Table 2. ALE/PROG is pulsed low to age level can cause permanent damage to the de-
program the code byte into the addressed EPROM vice. The Vpp source should be well regulated and
location. The setup is shown in Figure 10. free of glitches.
8-130
inter 87C51FA
+5V
Vee
AO-A7 Pl PO PGM DATA
RST Th/vpp 1+---+12.75V
ALE/PROG 1+---25 100).ls PULSES TO GND
P3.6
PSEN 1+---0
87C51FA
P3.7
P2.7
XTAL2 P2.6 1+---0
'--......-r--IXTAL 1 P2.0 A8-A12
-P2.4 v - - -
vss
270258-20
Figure 10. Programming the EPROM
Quick-Pulse Programming™ Algorithm Program Verification
The 87C51 FA can be programmed using the Quick- If the Program Lock Bits have not been pro-
Pulse Programming™ Algorithm for microcontrol- grammed, the on-chip Program Memory can be read
lers. The features of the new programming method out for verification purposes, if desired, either during
are a lower Vpp (12.75V as compared to 21V) and a or after the programming operation. The address of
shorter programming pulse. It is possible to program the Program Memory location to be read is applied
the entire 8K Bytes of EPROM memory in less than to Port 1 and pins P2.0 - P2.4. The other pins should
25 seconds with this algorithm! be held at the "Verify" levels indicated in Table 3;
The contents of the addressed locations will come
To program the part using the new algorithm, Vpp out on Port O. External pullups are required on Port 0
must be 12.75V ±0.25V. ALE/PROG is pulsed low for this operation.
for 100 JLs, 25 times as shown in Figure 11. Then,
the byte just programmed may be verified. After pro- If the Encryption Array in the EPROM has been pro-
gramming, the entire array should be verified. The grammed, the data present at Port 0 will be Code
Program Lock features are programmed using the Data XNOR Encryption Data. The user must know
same method, but with the setup as shown in Table . the Encryption Array contents to manually "unen-
2. The only difference in progra,mming Program Lock crypt" the data during verify.
features is thatthe Program Lock features cannot be
directly verified. Instead, verification of programming The setup, which is shown in Figure 12, is the same
is by observing that their features are enabled. as for programming the EPROM except that pin P2.7
is held at a logic low, or may be used as an active-
low read strobe.
8-131
87C51FA
1 I' 25 PULSES 'I
ALE/PROG:~-----~
'-----'
1 "-. 10},. Iot'N111·'--~!°7.1~;tt~:'---'1
ALE/PROG:
---:....
o _---In'---_......Jn'---
1.0-'
Figure 11. PROG Waveforms
270258-21
Vee
I--~ PGIot
PI PO r---.....,/ DATA
RST "EA/Vpp
ALE/PROG
P3.6
PSEN ....- - 0
S7C51FA
P3.7
P2.7 ....- - 0 (ENABLE)
XTAL2 P2.S ....- - 0
L--6-~--1 XTAL 1 P2.0 'L..-'-A-S-_A 12
-P2.4
Vss
270258-22
Figure 12. Verifying the EPROM
8-132
infef 87C51FA
EPROM Program Lock Reading the Signature Bytes
The two-level Program Lock system consists of two The signature bytes are read by the same procedure
Program Lock bits and a 32 byte Encryption Array as a normal verification of locations 030H and 031 H,
which are used to protect the program memory except that P3.6 and P3.7 need to be pulled to a
against software piracy. logic low. The values returned are:
(030H) = 89H indicates manufacture by Intel
(031 H) = 50H indicates 87C51 FA
Encryption Array
Within the EPROM array are 32 bytes of Encryption
Array that are initially unprogrammed (all 1's). Every Erasure. Characteristics
time that a byte is addressed during a verify, 5 ad- Erasure of the EPROM begins to occur when the
dress lines are used to select a byte of the Encryp- chip is exposed to light with wavelength shorter than
tion Array. This byte is then exclusive-NOR'ed approximately 4,000 Angstroms. Since sunlight and
(XNOR) with the code byte, creating an Encrypted fluorescent lighting have wavelengths in this range,
Verify byte. The algorithm, with the array in the un- exposure to these light sources over an extended
programmed state (all 1's), will return the code in its time (about 1 week in sunlight, or 3 years in room-
original, unmodified form. level fluorescent lighting) could cause inadvertent
erasure. If an application subjects the device to this
type of exposure, it is suggested that an opaque la-
Program Lock Bits bel be placed over the window.
Also included in the EPROM Program Lock scheme The recommended erasure procedure is exposure
are two Program Lock Bits which are programmed to ultraviolet light (at 2537 Angstroms) to an integrat-
as shown in Table 2.
ed dose of at least 15 W-sec/cm. Exposing the
EPROM to an ultraviolet lamp of 12,000 /J-W/cm rat-
Table 3 outlines the features of programming the ing for 30 minutes, at a distance of about 1 inch,
Lock Bits.
should be sufficient.
Erasing the EPROM also erases the Encryption Ar- Erasure leaves the all EPROM Cells in a 1's state.
ray and the Program Lock Bits, returning the part to
full functionality.
Table 3 Program Lock Bits and their Features
Program Lock Bits
Logic .Enabled
LB1 LB2
U U No Program Lock features enabled. (Code Verify will still be
encrypted by the Encryption Array.)
P U MOVC instructions executed from external program memory
are disabled from fetching code bytes from internal memory,
EA is sampled and latched on reset, and further programming
of the EPROM is disabled.
P P Same as above, but Verify is also disabled
U P Reserved for Future Definition
8-133
inter 87C51FA
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
(TA = 21°C to 27"C; Vee = 5V±0.25V; vss = OV)
Symbol Parameter Min Max Units
Vpp Programming Supply Voltage 12.5 13.0 V
Ipp Programming Supply Current 50 mA
1/TCLCL Oscillator Frequency 4 ,6 MHz
TAVGL Address Setup to PROG Low 48TCLCL
TGHAX Address Hold after PROG . 48TCLCL
TDVGL Data Setup to PROG Low 48TCLCL
TGHDX Data Hold after PROG 48TCLCL
TEHSH P2.7 (ENABLE) High to Vpp 48TCLCL
TSHGL Vpp Setup to PROG Low 10 fts
TGHSL Vpp Hold after PROG 10 fts
TGLGH PROG Width 90 110 fts
TAVQV Address to Data Valid 48TCLCL
TELQV ENABLE Low to Data Valid 48TCLCL
TEHQZ Data Float after ENABLE 0 48TCLCL
TGHGL PROG High to PROG Low 10 fts
EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
PROGRAMMING VERIFICATION
PLO-Pl.?
P2.0-P2.4 -----{=2AD~D~R§ES~S~~==t_----~{=2AD~D~R§ES~S==>----
-TAVQV
PORTO------1~=~~~:~~~-------_1~D~A~TA~OU~T=~~~----
TDVGl- TGHDX
TAVGl
AlE/PROG -------~I
TSHGLr--
EA/Vpp TAGH vp~ EA/HIGH
-----~-.-...
....~ITEHSH
TElQV1~_ _ _.Jj _ _T_EH_Q_Z_ __
P2.?
-_....
270258-18
8-134
inter 87C51FA
DATA SHEET REVISION SUMMARY
The following are the key differences between this and the -003 version of the 87C51 FA data sheet:
1. Included the 16 MHz device.
2. Deleted the word Maximum from the IOL line of ABSOLUTE MAXIMUMRATINGS.
3. Deleted the EA from VIH line of D. C. Table.
4. Pin capacitance now specified as Typical only.
The following are the key differences between the -003 and the -002 version of the 87C51 FA data sheet:
1. Data sheet was upgraded from ADVANCE INFORMATION to PRELIMINARY.
2. The old device name (87C252) was removed from the title.
3. PLCC pin connection diagram was added.
4. Package table was added. '
5. Exit from Power Down Mode was clarified.
6. Maximum IOL per 1/0 was added to ABSOLUTE MAXIMUM RATINGS.
7. Note 4 was added to explain the maximum safe current spec.
8. Ipo was improved from 100 /LA to 75 /LA.
9. Typical DC characteristics were added for IlL, Ill, ITL, RRST and Icc.
10. Note 5 was added to explain the test conditions for typical values.
11. Timing spec's improved for:
TAVLL changed from TCLCL-55 to TCLCL-40
TLLAX changed from TCLCL-35 to TCLCL-30
TLLPL changed from TCLCL-40 to TCLCL-30
TRHDZ changed from TCLCL-70 to TCLCL-60
TQVWX changed from "Address Valid Before WR" to "Data Valid to WR Transition" and changed from
TCLCL-60 to TCLCL-50
TQVWH was added.
12. Data sheet revision summary was added.
13. EA Leakage current not spec'ed.
8-135
87C51FA
EXPRESS
• Extended Temperature Range • 3.5 MHz to 12 MHz Vee = 5V ± 10%
• Burn-In
The Intel EXPRESS system offers enhancements to the operational specifications of the 8051 family of
microcontrollers. These EXPRESS products are designed to meet the needs of those applications whose
operating requirements exceed commercial standards.
The EXPRESS program includes the commercial standard temperature range with burn-in and an extended
temperature range with or without burn-in.
With the commercial standard temperature range, operational characteristics are guaranteed over the temper-
ature range of ooe to + 70 o e. With the extended temperature range option, operational characteristics are
guaranteed over the range of - 400 e to + 85°e.
The optional burn-in is dynamic for a minimum time of 168 hours at 125°e with Vee = 6.9V ± 0.25V, following
guidelines in MIL-STD-883, Method 1015.
Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part number. The
prefixes are listed in Table 1.
For the extended temperature range option, this data sheet specifies the parameters which deviate from their
commercial temperature range limits. The commercial temperature range data sheets are applicable for all
parameters not listed here.
June 1988
8-136 Order Number: 270619-001
intJ 87C51FA EXPRESS ~[Q)W~OO©[§ OOO!P@OOfMlb\'U'O@OO
Electrical Deviations from Commercial Specifications
for Extended Temperature Range
D.C. and A.C. parameters not included here are the same as in the commercial temperature range data
sheets.
D.C. CHARACTERISTICS TA = -40·Cto + 85·C; Vee = 5V ±10%;Vss = ov
Limits Test
Symbol Parameter Unit
Min Max Conditions
IlL Logical 0 Input Current (Port 1, 2, 3) -75 /k A VIN = 0.45V
III Input Leakage Current ±15 /k A VIN = VIL or VIH
(Port 0 and EA)
ITL Logical 1 to 0 transition -750 /k A VIN = 2.0V
Current (Ports 1, 2, 3)
Icc Power Supply Current (Note 1)
Active Mode 35 rnA
Idle Mode 7.5 rnA
Power Down Mode 150 /k A
NOTE:
1. Vee = 4.5V-5.5V,Frequency Range = 3.5 MHz-12 MHz.
8-137
87C51FA EXPRESS ~[Q)W~OO©~ OOOI?@OOfMl~iiO@OO
Table 1 Prefix Identification
Prefix Package Type· Temperature Range(2) Burn-In(~)
P Plastic Commercial No
0 Cerdip Commercial No
N PLCC Commercial No
TP Plastic Extended No
TO Cerdip Extended No
TN PLCC Extended No
LP Plastic Extended Yes
LD Cerdip Extended Yes
LN PLCC Extended Yes
NOTES:
2. Commercial temperature range is O·C to + 70·C. Extended temperature range is ~ 40·C to + 85·C.
3. Burn-in is dynamic for a minimum time of 168 hours at + 125·C, Vee = 6.9V ±0.25V, .following guidelines in MIL-STD-
883 Method 1015 (Test Condition D). .
Examples:
P87C51 FA indicates 87C51 FA in a plastic package and specified for commercial temperature range, without
burn-in.
LD87C51 FA indicates 87C51 FA in a cerdip package and specified for extended temperature range with burn-
~ .
8-138
83C51FB
CHMOS SINGLE-CHIP8-BIT MICROCONTROLLER
83C51FB-16K bytes of Factory Mask Programmable ROM
83C51FB-3.5 MHz to 12 MHz, Vee = 5V ± 10%
83C51FB-1-3.5 MHz to 16MHz, Vee = 5V ± 10%
83C51FB-2-0.5 MHz to 12 MHz, Vee = 5V ± 10%
• High Performance CHMOS EPROM
• 7 Interrupt Sources
• Three 16-BitTimer/Counters
• Programmable Serial Channel with:
• Programmable Counter Array with:
- High Speed Output,
- Framing Error Detection
- Automatic Address Recognition
- Compare/Capture,
- Pulse Width Modulator,
• TTL and CMOS Compatible Logic
Levels
- Watchdog Timer Capabilities
• Up/Down Timer/Counter • 64K bytes External Program Memory
Space
• Program Lock System
• 64K bytes External Data Memory Space
• 16K bytes of On-Chip Program ROM
• MCS®-51 Compatible Instruction Set
• 256 Bytes of On-Chip Data RAM
• Power Saving Idle and Power Down
• Boolean Processor
•
Modes
ONCETM (On-Circuit Emulation) Mode
• 32 Programmable I/O Lines
MEMORY ORGANIZATION
PROGRAM MEMORY: Up to 16K bytes of the program memory can reside in the on-chip ROM. In addition the
device can address up to 64K bytes of program memory external to the chip.
DATA MEMORY: This microcontrolier has a 256 x 8 on-chip RAM. In addition it can address up to 64K bytes of
external data memory.
The Intel 83C51 FB is a single-chip control-oriented microcontrolier which is fabricated on Intel's reliable
CHMOS IV technology. Being a member of the MCS-51 family, the 83C51 FB uses the same powerful instruc-
tion set, has the same architecture, and is pin-for-pin upward compatible with the existing MCS-51 products.
The 83C51 FB is an enhanced version of the 80C51 BH. Its added features make it an even more powerful
microcontrolier for applications that require Pulse Width Modulation, High Speed 1/0, and upldown counting
capabilities such as motor control. It also has a more versatile serial channel that facilitates multi-processor
communications.
October 1989
8-139 Order Number: 270598-003
83C51FB
PO .0- PO.7
----------,
PSEN
ALE/i'lmG
£A/vpp
RST
P3.0- P3.7
270598-1
Figure 1. 83C51FB Block Diagram
8-140
inter 83C51FB
PACKAGES
Part Prefix Package Type PIN DESCRIPTIONS
B3C51FB P 40-Pin Plastic DIP Vee: Supply voltage.
D 40-Pin CERDIP
N 44-Pin PLCC Vss: Circuit ground.
Port 0: Port 0 is an B-bit, open drain, bidirectional 1/0
port. As an output port each pin can sink severalLS
TTL inputs. Port 0 pins that have 1's written to them
(T2) PLO vee float, and in that state can be used as high-imped-
(T2EX) PI. 1 PO.O (ADO)
ance inputs.
(ECI) Pl.2 PO.l (ADI)
(CEXO) Pl.3 PO.2 (AD2)
Port 0 is also the multiplexed low-order address and
(CEX1) Pl.4 PO.3 (A03)
data bus during accesses to external Program and
(CEX2) Pl.S PO.4 (AD4)
Data Memory. In this application it uses strong inter-
(CEX3) Pl.6 PO.S (ADS) nal pullups when emitting 1's, and can source and
(CEX4) Pl.7 PO.6 (AD6) sink several LS TTL inputs.
RESET PO.7 (AD7)
(RXD) P3.0 EA/Vpp Port 0 outputs the code bytes during program verifi-
(TXD) P3.1 AlE/PROG cation on the B3C51 FB. External pullup resistors are
(INTO) P3.2 PSEN required during program verification.
(INT1 ) P3.3 P2.7 (A1S)
(TO) P3.4 P2.6 (AU) Port 1: Port 1 is an B-bit bidirectional 1/0 port with
(T1) P3.S P2.S (AI3) internal pull ups. The Port 1 output buffers can drive
(ViR) P3.6 P2.4 (AI2) LS TTL inputs. Port 1 pins that have 1's written to
(Rii) P3.7 P2.3 (Al1) them are pulled high by the internal pullups, and in
XTAl2 P2.2 (Al0) that state can be used as inputs. As inputs, Port 1
XTALI P2.1 (A9) pins that are externally being pulled low will source
P2.0 (AB) current (IlL, on the data sheet) because of the inter-
nal pullups.
270598-2
DIP In addition, Port 1 serves the functions of the follow-
ing special features of the B3C51 FB:
INDEX
CORNER
Port Pin. Alternate Function
Pl.S !~; ~?! PO.4 P1.0 T2 (External Count Input to Timerl
Pl.6 .':; :~ PO.S
Counter 2)
Pl.7 )~ ~ :~~ PO.&
RST 1~ ~ :~ PO.7 P1.1 T2EX (Timer I Counter 2 Capturel
Pl.O )!i Reload Trigger and Direction Control)
Ne ~~~
P1.2 ECI (External Count Input to the PCA)
Pl.l 1~~ :~ ALE
P3.2 H~ :~! PSEN P1.3 CEXO (External 1/0 for Comparel
P3.3 ~~; :~! P2.7 Capture Module 0)
P3.4 ~~; ::;.; P2.&
P1.4 CEX1" (External 110 for Compare I
P3.S ~C [)! P2.S
;~: :~: :g: :~ ;~: :~~ :~: ;lQi :;:; :ti ;~: Capture Module 1)
P1.5 CEX2 (External 1/0 for Comparel
Capture Module 2)
270598-3 P1.6 CEX3 (External 1/0 for Comparel
PLCC Capture Module 3)
P1.7 CEX4 (External 1/0 for Comparel
Figure 2_ Connection Diagrams
Capture Module 4)
B-141
83C51FB
Port 1 receives the low-order address bytes during for external timing or clocking purposes. Note, how-
ROM verification. "ever, that one ALE pulse is skipped during each ac-
cess to external Data Memory.
Port 2: Port 2 is an 8-bit bidirectional 1/0 port with
internal pullups. The Port 2 output buffers can drive PSEN: Program Store Enable is the read strobe to
LS TTL inputs. Port 2 pins that have 1's written to external Program Memory.
them are pulled high by the internal pulh-ips, and in When the 83C51 FB is executing code from external
that state can be used as inputs. As inputs, Port 2 Program Memory, PSEN is activated twice each ma-
pins that are externally being pulled low will source chine cycle, except that two PSEN activations are
current (IlL, on the data sheet) because of the inter- skipped during each access to external Data Memo-
nal pullups. ry.
Port 2 emits the high-order address byte during EA: External Access enable. EA must be strapped to
fetches from external Program Memory and during VSS in order to enable the device to fetch code from
accesses to external Data Memory that use 16-bit external Program Memory locations OOOOH to
addresses (MOVX @DPTR). In this application it OFFFFH. Note, however, that if the Program Lock bit
uses strong internal pullups when emitting 1'so Dur- is programmed, EA will be internally latched on re-
ing accesses to external Data Memory that use 8-bit set.
addresses (MOVX @Ri), Port 2 emits the contents of
the P2 Special Function Register. EA should be strapped to Vee for internal program
executions.
Some Port 2 pins receive the high-order address bits XTAL 1: Input to the inverting oscillator amplifier.
during program verification.
XTAL2: Output from the inverting oscillator amplifier.
Port 3: Port 3 is an 8-bit bidirectional 1/0 port with
internal pullups. The Port 3 output buffers can drive OSCILLATOR CHARACTERISTICS
LS TTL inputs. Port 3 pins that have 1's written to
them are pulled high by the internal pullups, and in XTAL 1 and XTAL2 are the input and output, respec-
that state can be used as inputs. As inputs, Port 3 tively, of a inverting amplifier which can be config"
pins that are externally being pulled low will source ured for use as an on-chip oscillator, as shown in
current (IlL, on the data sheet) because of the pull- Figure 3. Either a quartz crystal or ceramic resonator
ups. may be used. More detailed information concerning
the use of the on-chip oscillator is available in Appli-
Port 3 also serves the functions of various special cation Note AP-155, "Oscillators for Microcontrol-
features of the 8051 Family, as listed below: lers."
To drive the device from an external clock source,
Port Pin Alternate Function XTAL 1 should be driven, while XTAL2 floats, as
shown in Figure 4. There are no requirements on the
P3.0 RXD (serial input port) duty cycle of the external clock signal, since the in-
P3.1 TXD (serial output port) put to the internal clocking circuitry is through a di-
P3.2 INTO (external interrupt 0) vide-by-two flip-flop, but minimum and maximum
P3.3 INT1 (external interrupt 1) high and low times specified on the data sheet must
P3.4 TO (Timer 0 external input) be observed.
P3.5 T1 (Timer 1 external input) An external oscillator may encounter as much as a
P3.6 WR (external data memory write strobe) 100 pF load at XTAL 1 when it starts up. This is due
P3.7 RD (external data memory read strobe) to interaction between the amplifier and its feedback
capacitance. Once the external signal meets the VIL
RST: Reset input. A high on this pin for two machine and VIH specifications the capacitance will not ex-
cycles while the oscillator is running resets the de- ceed 20 pF.
vice. An internal pulldown resistor permits a power-
~
2
on reset with only a capacitor connected to Vee.
. 0 XTAL2
ALE: Address Latch Enable output pulse for latching
Cl
the low byte of the address during accesses to ex- XTAL 1
ternal memory.
Vss
270598-4
In normal operation ALE is emitted at a constant C1, C2 ~ 30 pF ± 10 pF for CrYstals
rate of % the oscillator frequency, and may be used ~ 10 pF for Ceramic Resonators
Figure 3. Oscillator Connections
8-142
inter 83C51FB
held active long enough for the oscillator to restart
and stabilize (normally less than 10 ms).
N/C XTAL2
With an external interrupt, INTO and INT1 must be
EXTERNAL
enabled and configured as level-sensitive. Holding
OSCILLATOR XTAL 1 the pin low restarts the oscillator but bringing the pin
SIGNAL back high completes the exit. Once the interrupt is
vss serviced, the next instruction to be executed after
RETI will be the one following the instruction that put
the device into Power Down.
270598-5
Figure 4. External Clock Drive Configuration DESIGN CONSIDERATION
• When the idle mode is terminated by a hardware
IDLE MODE reset, the device normally resumes program exe-
cution, from where it left off, up to two machine
The user's software can invoke the Idle Mode. When cycles before the internal reset algorithm takes
the microcontroller is in this mode, power consump- control. On-chip hardware inhibits access to inter-
tion is reduced. The Special Function Registers and nal RAM in this event, but access to the port pins
the onboard RAM retain their values during Idle, but is not inhibited. To eliminate the possibility of an
the processor stops executing instructions. Idle unexpected write when Idle is terminated by·re-
Mode will be exited if the chip is reset or if an en- set, the instruction following the one that invokes
abled interrupt occurs. The PCA timer/counter can Idle should not be one that writes to a port pin or
optionally be left running or paused during Idle to external memory.
Mode.
ONCETM MODE
POWER DOWN MODE
The ONCE ("On-Circuit Emulation") Mode facilitates
To save even more power, a Power Down mode can testing and debugging of systems using the
be invoked by software. In this mode, the oscillator 83C51FB without the 83C51FB having to be re-
is stopped and the instruction that invoked Power moved from the circuit. The ONCE Mode is invoked
Down is the last instruction executed. The on-chip by:
RAM and Special Function Registers retain their val-
1) Pull ALE low while the device is in reset and
ues until the Power Down mode is terminated.
PSEN is high;
On the 83C51 FB either a hardware reset or external 2) Hold ALE low as RST is deactivated.
interrupt can cause an exit from Power Down. Reset
redefines all the SFRs but does not change the on- While the device is in ONCE Mode, the Port 0 pins
chip RAM. An external interrupt allows both the go into a float state, and the other port pins and ALE
SFRs and the on~chip RAM to retain their values. and PSEN are weakly pulled high. The oscillator cir-
cuit remains active. While the 83C51 FB is in this
To properly terminate Power Down the reset or ex- mode, an emulator or test CPU can be used to drive
ternal interrupt should not be executed before Vcc is the circuit. Normal operation is restored when a nor-
restored to its normal operating level and must be mal reset is applied.
Table 1. Status of the External Pins during Idle and Power Down
Program
Mode ALE PSEN PORTO PORT1 PORT2 PORT3
Memory
Idle Internal 1 1 Data Data Data Data
Idle External 1 1 Float Data Address Data
Power Down Internal 0 0 Data Data Data Data
Power Down External 0 0 Float Data Data Data
NOTE:
For more detailed information on the reduced power modes refer to current Embedded Controlier Handbook, and Applica·
tion Note AP·252, "Designing with the BOC51 BH."
8-143
inter 83C51FB
ABSOLUTE MAXIMUM RATINGS* NOTICE: This data sheet contains information on
products in the sampling and initial production phases
Ambient Temperature Under Bias .... ODC to + 70DC of development. The specifications are subject to
Storage Temperature .......... - 65 DC to + 150DC change without notice. .
Voltage on EA Pin to VSS ........... OV to + 13.0V • WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause. permanent damage.
Voltage on Any Other Pin to V ss .. - 0.5V to + 6.5V These are stress ratings only. Operation beyond the
IOL Per 110 Pin. ; ......................... 15 mA "Operating Conditions" is not recommended and ex-
tended exposure beyond the "Operating Conditions"
Power Dissipation ........ ; ................. 1.5W
may affect device reliability.
(based on PACKAGE heat transfer limitations, not
device power consumption)
ADVANCED INFORMATION......,.CONTACT INTEL FOR DESIGN-IN INFORMATION
D.C. CHARACTERISTICS: (TA = ODC to + 70DC; VCC = 5V ± 10%; Vss = OV)
Typical
Symbol Parameter Min Max Unit Test Conditions
(Note 4)
VIL Input Low Voltage -0.5 0.2Vee- 0.1 V
VIL1 Input Low Voltage EA 0 0.2Vee- 0.3 .V
VIH Input High Voltage 0.2Vee+ 0.9 Vee+ 0.5 V
(Except XTAL1, RST)
VIH1 Input High Voltage 0.7 Vee Vee+ 0.5 V
(XTAL1, RST)
VOL Output Low Voltage (Note 5) 0.3 V IOL = 100 /LA (Note 1)
(Ports 1, 2, and 3) 0.45 V IOL = 1.6 mA (Note 1)
1.0 V IOL = 3.5 mA (Note 1)
VOL1 Output Low Voltage (Note 5) 0.3 V IOL = 200 /LA (Note 1)
(Port 0, ALE, PSEN) 0.45 V IOL = 3.2 rnA (Note 1)
1.0 V IOL = 7.0 rnA (Note 1)
VOH Output High Voltage Vee- 0.3 V IOH = -10 /LA
(Ports 1, 2, and 3) V
Vee- 0.7 IOH = -30/LA
Vec- 1.5 V IOH = -60/LA
VOH1 Output High Voltage Vec- 0.3 V IOH = - 200 /LA
(Port 0 in External Bus Mode, Vce- O.7 V IOH = -3.2 rnA
ALE, PSEN)
Vee- 1.5 V IOH = -7.0rnA
IlL Logical 0 Input Current -50 /LA VIN = 0.45V
(Ports 1, 2, and 3)
III Input Leakage Current ±10 /LA 0.45 < VIN < Vee - 0.3V
(Port 0)
ITL Logical 1 to 0 Transition -650 /LA VIN =2V
Current (Ports 1, 2, and 3)
RRST RST Pulldown Resistor 40 225 KO
CIO Pin Capacitance 10 pF @1 MHz, 25DC
Icc Power Supply Current: (Note 3)
Running at 12 MHz (Figure 5) 20 40 rnA
Idle Mode at 12 MHz (Figure 5) 5 10 rnA
Power Down Mode 15 100 /LA
8-144
83C51FB
D.C. CHARACTERISTICS: (T A = OOG to + 70o G; Vcc 5V ± 10%; VSS OV)(Gontinued) = =
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOlS of ALE and Ports
I, 2 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1
to 0 transitions during bus operations. In applications where capacitance loading exceeds 100 pFs, the noise pulse on the
ALE signal may exceed 0.8V. In these cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an Address
Latch with a Schmitt Trigger Strobe input.
2. Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the 0.9 VCC specification when the
address lines are stabilizing. .
3. See Figures 6-9 for test conditions. Minimum VCC for power down is 2V.
4. Typicals are based on limited number of samples and are not guaranteed. The values listed are at room temperature and
5V.
5. Under steady state (non-transient) conditions, IOl must be externally limited as follows:
Maximum IOl per port pin: 10 mA
Maximum IOl per 8-bit port-
Port 0: 26 mA
Ports I, 2, and 3: 15 mA
Maximum total IOl for all output pins: 71 mA
If IOl exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
GOmA
SOmA
MAX.
AOmA
30mA
20mA
lOrnA
OmA
oMHz
.....-:
-
............
4MHz
j.--"
.---- ----- -------
ACTIVE
~~
BMHz
TYPICAL
OLE TYP
12MHz
---
MAX.
270598-20
16MHz
RST
a3eSl FB
XTAL2
XTAl1
vss
Icc Max at other frequencies is given by: 270598-7
Active Mode All other pins disconnected
Icc Max = (OSC Freq x 3) + 4 TClCH = TCHCl = 5 ns
Idle Mode
Icc Max = (OSC Freq x 0.5) + 4 . Figure 6. Icc Test Condition, Active Mode
Where Osc Freq is in MHz and Icc is in rnA.
Figure 5. Icc vs Frequency
RST RST
83C51FB 83eSl FB
XTAL2 XTAL2
XTAL1 XTAL1
Vss vss
270598-9
270598-8
All other pins disconnected All ~ther pins disconnected
TClCH = TCHCl = 5 ns
Figure 8. Icc Test Condition, Power Down Mode.
Figure 7. Icc Test Condition Idle Mode Vcc = 2.0V to 5.5V.
270598-10
Figure 9. Clock Signal Waveform for Icc Tests in Active and Idle Modes. TCLCH = TCHCL = 5 ns.
8-145
inter 83C51FB
EXPLANATION OF THE AC SYMBOLS L: Logic level LOW, or ALE
P: PSEN
Each timing symbol has 5 characters. The first char- Q: Output Data
acter is always a 'T' (stands for time). The other R: RD signal
characters, depending on their positions, stand for T: Time
the name of a signal or the logical status of that V: Valid
Signal. The following is a list of all the characters and W: WR Signal
what they stand for. X: No longer a valid logic level
Z: Float
A: Address
C: Clock For example,
D: Input Data
H: Logic level HIGH TAVLL = Time from Address Valid to ALE Low
I: Instruction (program memory contents) TLLPL = Time from ALE Low to PSEN Low
A.C. CHARACTERISTICS T A = o°c to + 70°C, VCC = 5V ± 10%, VSS = OV, Load Capacitance for
Port 0, ALE and PSEN = 100 pF, Load Capacitance for All Other Outputs = 80 pF
ADVANCED INFORMATION-CONTACT INTEL FOR DESIGN-IN INFORMATION
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
12 MHz Oscillator Variable Oscillator
Symbol Parameter Units
Min Max Min Max
1/TCLCL Oscillator Frequency MHz
83C51FB 3.5 12
83C51FB-1 3.5 16
83C51FB-2 0.5 12
TLHLL ALE Pulse Width 127 2TCLCL-40 ns
TAVLL Address Valid to ALE La\(\' 43 TCLCL-40 ns
TLLAX Address Hold After ALE Low 53 TCLCL-30 ns
TLLlV ALE Low to Valid Instruction In 234 4TCLCL-100 ns
TLLPL ALE Low to PSEN Low 53 TCLCL-30 ns
TPLPH PSEN Pulse Width 205 3TCLCL-45 ns
TPLIV PSEN Low to Valid Instruction In 145 3TCLCL-105 ns
TPXIX Input Instruction Hold After PSEN 0 0 ns
TPXIZ Input Instruction Float After PSEN 59 TCLCL-25 ns
TAVIV Address to Valid Instruction In 312 5TCLCL-105 ns
TPLAZ PSEN Low to Address Float 10 10 ns
TRLRH RD Pulse Width 400 6TCLCL-100 ns
TWLWH WR Pulse Width 400 6TCLCL-100 ns
TRLDV RD Low to Valid Data In 252 5TCLCL-165 ns
TRHDX Data Hold After RD 0 0 ns
TRHDZ Data.Float After RD 107 2TCLCL-60 ns
TLLDV ALE Low to Valid Data In 517 8TCLCL-150 ns
TAVDV Address to Valid Data In 585 9TCLCL-165 ns
TLLWL ALE Low to RD or WR Low 200 300 3TCLCL-50 3TCLCL+50 ns
TAVWL Address Valid to RD or WR Low 203 4TCLCL-130 ns
TOVWX Data Valid before WR 33 TCLCL-50 ns
TWHOX Data Hold after WR 33 TCLCL-50 ns
TOVWH Data Valid to WR High 433 lTCLCL-150 ns
TRLAZ RD Low to Address Float 0 0 ns
TWHLH RD or WR High to ALE High 43 123 TCLCL-40 TCLCL+40 ns
8-146
intJ 83C51FB
EXTERNAL PROGRAM MEMORY READ CYCLE
ALE _ _J
PSEN _ _J
TPXIZ
PORT 0
---- AD-A7
PORT 2 _ _ _J A8-A15
270598-11
EXTERNAL DATA MEMORY READ CYCLE
ALE
---TLHLL---+-
PSEN
1 - - - - - - TLLDV 'I
-~-t---- TRLRH - - - - - I
RD
PORTO INSTR. IN
PORT2 P2.0-P2.7 OR A8-A15 FROM OPH A8-A15 FROM PCH
270598-12
EXTERNAL DATA MEMORY WRITE CYCLE
ALE '\ X /
-TLHLL- P-TWHLH
,
~TLLWL TWLWH
- TAVLL
-
-TLLAX- ~
TQVWH
- --TWHQX
PORTO
:::r AO-A7
FROM RI OR DPL
TAVWL
DATA OUT K AO-A7 FROM peL INSTR. IN
PORT2
::::> P2.0-P2.7 OR A8-A 15 FROM DPH A8-A 15 FROM PCH
270598-13
8-147
inter 83C51FB
A.C. TESTING INPUT
Input, Output Waveforms Flo~t Waveforms
Vee-O.5-y- 0.2 Vee +0.9 V-- TIMING REFERENCE
POINTS
0.45 V---./\._0_.2_VC.:.:C:..-_0_.l_ _ _ _ ~ VOL +0.1 V
270598-21 270598-15
For timing purposes a port pin is no longer floating when a
AC inputs during testing are driven at Vee-0.5V for a Logic "1"
100 mV change from load voltage occurs, and begins to float
and 0.45V for a Logic "0". Timing measurements are made at VIH
min for a Logic "1" and V'L max for a Logic "0". when a 100 mV change from the loaded VOHIVOL level occurs.
IOLlloH;:' ±20 mAo
SERIAL PORT TIMING-SHIFT REGISTER MODE
Test Conditions: TA = O·Cto +70·C;Vcc = 5V ±10%;Vss = OV;LoadCapacitance = 80pF
12 MHz Oscillator Variable Oscillator
Symbol Parameter Units
Min Max Min Max
TXLXL Serial Port Clock Cycle Time 1 12TCLCL f-Ls
TQVXH Output Data Setup to Clock 700 1OTCLCL -133 ns
Rising Edge
TXHQX Output Data Hold after 50 2TCLCL-117 ns
Clock Rising Edge
TXHDX Input Data Hold After Clock 0 0 ns
, Rising Edge
TXHDV Clock Rising Edge to Input 700 1OTCLCL - 133 ns
Data Valid
SHIFT REGISTER MODE TIMING WAVEFORMS
IHSTRUCTION I. 0 2 3 4 5 6 7 8
ALE
CLOCK
OUTPUT DATA
~~~~~~~~J
X 3 X 4 X 5 X 6 X 7
t
I
f
WRITE TO saur SET TI
IHPUT DATA -----~~!IJ"""""Jr.:.~,._~~!IJ""""".r.':~,._~~!IJ""""".r.':~,._~~!IJ"""""~~
f t
CLEAR RI SET RI
270598-16
8-148
83C51FB
EXTERNAL CLOCK DRIVE
Symbol Parameter Min Max Units
1/TClCl Oscillator Frequency MHz
83C51FB 3.5 12
83C51 FB-1 3.5 16
83C51FB-2 0.5 12
TCHCX High Time 20 ns
TClCX low Time 20 ns
TClCH Rise Time 20 ns
TCHCl Fall Time 20 ns
EXTERNAL CLOCK DRIVE WAVEFORM
270598-17
ROM CHARACTERISTICS
Table 2 shows the logic levels for verifying the code data and reading the signature bytes on the 83C51 FB.
Table 2. ROM Modes
Mode RST PSEN ALE EA P2.7 P2.6 P3.6 P3.7
Verify Code Data 1 0 1 1 0 0 1 1
Read Signature 1 0 1 1 0 0 0 0
NOTES:
"1" = Valid high for that pin
"0" = Valid low for that pin
8-149
83C51FB
Program Verification If the Encryption Array in the ROM has been pro-
grammed, the data present at Port 0 will be Code
If the Program Lock Bits have not been pro- Data XNOR Encryption Data. The user must know
grammed, the on-chip Program Memory can be read the Encryption Array contents to manually "un en-
out for verification purposes, if desired. The address crypt" the data during verify.
of the Program Memory location to be read is ap-
plied to Port 1 and pins P2.0-P2.5. The other pins Figure 10 shows the setup for verifying the program
should be held at the "Verify" levels indicated in Ta- memory.
ble 2. The contents of the addressed locations will
come out on Port O. External pull ups are required on
Port 0 for this operation.
vee
AO-A7 PGM
Pl PO ,----'11' DATA
RST EA
ALE
P3.6
PSEN 1+--"";""0
S3C51FB
P3.7
P2.7 1+--- 0 (ENABLE)
P2.6 1 + - - 0
P2.0 /L.-A-S--A13
-P2.5
270598-18
Figure 10. Verifying the ROM
ROM VERIFICATION CHARACTERISTICS
TA = 21°C to 27°C; Vee = SV±0.2SV; Vss = ov
ADVANCED INFORMATION-CONTACT INTEL FOR DESIGN-IN INFORMATION
Symbol Parameter Min Max Units
1/TCLCL Oscillator Frequency 4 6 MHz
TAVQV Address to Data Valid 48TCLCL
TELQV ENABLE Low to Data Valid 48TCLCL
TEHQZ Data Float after ENABLE 0 48TCLCL
8-1S0
inter 83C51FB ~[Q)W~~©~ O~[f@rrulMl~'TI'O@~
I
ROM VERIFICATION WAVEFORMS Reading the Signature Bytes
VERIFICATION The signature bytes are read by the same procedure
as a normal verification of locations 030H and 031 H,
~~:~:~~:~ -..;....~-_. .f~:~=~T:~:§::~E~SS=:J)f-----
except that P3.6 and P3.7 need to be pulled to a
logic low. The values returned are:
(030H) = 89H indicates manufacture by Intel
PoRTo-----...t~D~AT~A~O~UT~:t~I------ (031 H) = 5EH indicates 83C51 FB
P2.7
'>CO'l( ) "." OAT A SHEET REVISION SUMMARY
270598-19 The following are the key differences between this
and the -002 version of the 83C51 FB data sheet:
1. Word "maximum" was de,leted from the IOL line in
the ABSOLUTE MAXIMUM RATINGS.
ROM Program Lock
2. Parameter VIL1 was deleted from the DC CHAR-
The Program Lock system consists of one Program ACTERISTICS.
Lock bit and a 32 byte Encryption Array which are 3. Note 4 was deleted from DC CHARACTERISTICS
used to protect the program memory against soft- and from the list of notes and notes were rese-
ware piracy. quenced.
Table 3 outlines the features of programming the 4. Parameter IU1 was deleted from the DC CHAR-
Lock Bit. ACTERISTICS.
5. Figure 5 was replaced to show correct Icc curves.
Table 3. Program Lock Bit and their Features 6. External clock capacitive loading note was added.
Program
Lock The following are the key differences between the
Logic Enabled -002 and the -001 version of the 83C51 FB data
Bit
sheet:
LB1
1. Package table was added.
U No Program Lock features enabled.
2. Note 4 was added to explain the maximum safe
(Code Verify will still be encrypted by
current spec.
the Encryption Array.)
3. Maximum IOL per 1/0 pin was added to the AB-
P MOVC instructions executed from SOLUTE MAXIMUM RATING.
external program memory are disabled
from fetching code bytes from internal 4. Typical values for ICC table were added.
memory, EA is sampled and latched on 5. Note 5 was added to explain the test conditions
reset. for typical values,
6. Icc vs Frequency (Figure 5) was changed to re-
semble the 87C51FB data sheet.
Encryption Array 7. Timing specs improved for:
TLLAX changed from TCLCL-35 to TCLCL-30
Within the ROM array are 32 bytes of Encryption TLLPL changed from TCLCL - 40 to TCLCL - 30
Array that are initially unprogrammed (all 1's). Every TRHDZ changed from TCLCL-70 to TCLCL-60
time that a bytE;) is addressed during a verify, 5 ad- TOVWH was added.
dress lines are used to select a byte of the Encryp- TOVWX changed from TCLCL - 60 to TCLCL - 50
tion Array. This byte is then exclusiv!3-NOR'ed
(XNOR) with the code byte, creating an Encrypted 8. A.C. TESTING INPUT figure and specs were
Verify byte. The algorithm, with the array in the un- changed to match the 87C51 FB.
programmed state (all 1's), will return the code in it's 9. Data sheet revision summary was added.
original, unmodified form.
8-151
87C51FB
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
16K Bytes User Programmable EPROM
87C51FB-3.5 MHz to 12 MHz, Vee = 5V± 10%
87C51 FB-1-3.5 MHz to 16 MHz, Vee = 5V ± 10%
87C51 FB-2-0.5 MHz to 12 MHz, Vee = 5V ± 10%
• Three
High Performance CHMOS EPROM
• 732Interrupt
Programmable I/O Lines
• Programmable
16-Bit Timer/Counters
• Programmable Sources
• - High Speed Output,
Counter Array with:
• - Framing ErrorSerial Channel with:
Detection
- Compare/Capture, - Automatic Address Recognition
- Pulse Width Modulator,
- Watchdog Timer capabilities • TTL and CMOS Compatible Logic
Levels
• Two
Up/Down Timer/Counter
• 64K External Program Memory Space
• 16K On-Chip
Level Program Lock System
• MCS®-51 Compatible Instruction Set
64K External Data Memory Space
• 256 Bytes of EPROM • Power Saving Idle and Power Down
• Quick Pulse Programming™
On-Chip Data RAM
• Modes
• Boolean Processor Algorithm
• • ONCETM (On-Circuit Emulation) Mode
MEMORY ORGANIZATION
PROGRAM MEMORY: Up to 16K bytes of the program memory can reside in the on-chip EPROM. In addition
the device can address up to 64K of program memory external to the chip.
DATA MEMORY: This microcontroller has a 256 x 8 on-chip RAM. In addition it can address up to 64K bytes of
external data memory.
The Intel 87C51 FB is a single-chip control-oriented microcontroller which is fabricated on Intel's reliable
CHMOS III-E technology. Being a member of the MCS-51 family, the 87C51FB uses the same powerful
instruction set, has the same architecture, and is pin for pin compatible with the existing MCS-51 family of
products. The 87C51 FB is an enhanced version of the 87C51. It's added features make it an even more
powerful microcontroller for applications that require Pulse Width Modulation, High Speed I/O, and up/down
counting capabilities such as motor control. It also has a more versatile serial channel that facilitates multi-
processor communications.
October 1989
8-152 Order Number: 270563-003
inter 87C51FB
PO.0-PO.7
~~
,,----------~~~~;u, --------~-,
VSS
..r
PSEN
ALE/1'ROl: TIMING
AND
'"
~~----~--~~---------L~--~~--~------~
rA/VPP CONTROL 8~------~------------_r,_--------,,------~~----v'1
RST
'"
P1.0 - P1.7 P3.0-P3.7
270563-1
Figure 1. 87C51FB Block Diagram
8-153
87C51FB
PACKAGES Port 0: Port 0 is an 8-bit, open drain, bidirectional i/o
port. As an output port each pin can sink several LS
Part Prefix Package Type TTL inputs. Port 0 pins that have 1's written to them
float, and in that state can be used as high-imped-
P 40-Pin Plastic DIP ance inputs.
87C51FB D 40-Pin CERDIP
N 44-Pin PLCC Port 0 is also the multiplexed low-order address and
data bus during accesses to external Program and
Data Memory. In this application it uses strong inter-
nal pullups when emitting1's, and can source and
(T2) Pt.O Vee sink several LS TTL inputs.
(T2EX) PI.I po.o (AOO)
PO.I (AOI) Port o also receives the qode bytes during EPROM
PO.2 (A02)
programming, and outputs the code bytes during
PO.3 (A03)
program verification. External pullup resistors are re-
(eEX2) PI.S PO.4 (A04)
quired during program verification.
(eEX3) Pt.& PO.S (ADS)
PO.& (AO&)
RESET PO.7 (A07)
, Port 1: Port 1 is an 8-bit bidirectional I/O port with
(RXO) P3.D fA/vpp
internal pullups. The Port 1 output buffers can drive
(TXD) P3.1 ALE/PROG
LS TTL inputs. Port 1 pins that have 1's' written to
(INTO) P3.2 PSEN them are pulled high by the internal pLiliups, and in
(INTI) P3.3 P2.i (AI5) that state can be used as inputs. As' inputs, Port 1
(TO) P3.4 P2.& (A14) pins that are externally being pulled low will source
(TI) P3.5 P2.5 (AI3) current (IlL, on the data sheet) because of the inter-
(Wil) P3.& P2.4 (AI2) nal pullups.
(iiii) P3.7 P2.3 (All)
XTAL2 P2.2 (AIO) In addition, Port 1 serves the functions of the follow-
XTALI P2.1 (A9) ing special features of the 87C51 FB:
Vss
270563-2 Port Pin Alternate Function
DIP
P1.0 T2 (E,xternal Count Input to Timer/
Counter 2)'
INDEX
CORNER P1.1 T2EX (Timer/Counter 2 Capture/
~~~~~~~~~~ Reload Trigger and Direction Control)
PO.4
P1.2 ECI (External Count Input to the PCA)
po.s
PO.S P1.3 CEXO (External 1/0 for Compare!
RST pO.? Capture Module 0)
P3.0 EA/V" PM CEX1(Externall!0 for Compare!
Ne Ne
Capture Module 1)
P3.1 ALE/PROO
P3.2 PSEN P1.5 CEX2 (Externall!O for Compare!
P3.3 Capture Module 2)
P3.4 P2.6
P1.6 CEX3 (Externall!O for Compare!
P3.5 P2.S
Capture Module 3)
P1.7 CEX4 (External 110 for Comparel
Capture Module 4)
270563-23 ,
PLCC Port 1 receives the low-order address bytes during
EPROM programming and verifying. ,
Figure 2. Pin Connections
Port 2: Port 2 is an 8-bit bidirectional 1/0 port with
internal pullups. The Port 2 output buffers can drive
PIN DESCRIPTIONS LS TTL inputs. Port 2 pins that have 1's written to
them are pulled high by the internal pullups, and in
Vee: Supply voltage. that state can be used as inputs. As inputs, Port 2
pins that are externally being pulled low will source
Vss: Circuit ground. current (IlL, on the data sheet) because of the inter-
nal pullups.
8-154
87C51FB
Port 2 emits the high-order address byte during When the 87C51 FB is executing code from external
fetches from external Program Memory and during Program Memory, PSEN is aCtivated twice each ma-
accesses to external Data Memory that use 16-bit chine cycle, except that two PSEN activations are
addresses (MOVX@DPTR). In this application it skipped during each access to external Data Memo-
uses strong internal pullups when emitting 1'so Dur- ry.
ing accesses to external Data Memory that use 8-bit
addresses (MOVX @Ri), Port 2 emits the contents of EAlVpp: External Access enable. EA must be
the P2 Special Function Register. strapped to VSS in order to enable the device to
fetch code from external Program Memory locations
Some Port 2 pins receive the high-order address bits OOOOH to OFFFFH. Note, however, that if either of
during EPROM programming and program verifica- the Program Lock bits are programmed, EA will be
tion. internally latched on reset.
EA should be strapped to Vee for internal program
Port 3: Port 3 is an 8-bit bidirectional 1/0 port with executions. '
internal pull ups. The Port 3 output buffers can drive
LS TIL inputs. Port 3 pins that have 1's written to This pin also receives the programming supply volt-
them are pulled. high by the internal pullups, and in age (Vpp) during EPROM programming.
that state can be used as inputs. As inputs, Port 3
pins that are externally being pulled low will source XTAL1: Input to the inverting oscillator amplifier.
current (IlL, on the data sheet) because of the pull- XTAL2: Output from the inverting oscillator amplifier.
ups.
Port 3 also serves the functions of various speciai OSCILLATOR CHARACTERISTICS
features of the 8051 Family, as listed below: XTAL1 and XTAL2 are the input and output, respec-
tively, of a inverting amplifier which can be config-
Port Pin Alternate Function ured for use as an on-chip oscillator, as shown in
Figure 3. Either a quartz crystal or ceramic resonator
P3.0 RXD (serial input port) may be used. More detailed information concerning
P3.1 TXD (serial output port) the use of the on-chip oscillator is available in Appli-
P3.2 INTO (external interrupt 0) cation Note AP-155, "Oscillators for Microcontrol-
P3.3 INT1 (external interrupt 1) lers."
P3.4 TO (Timer 0 external input) To drive the device from an external clock source,
P3.5 T1 (Timer 1 external input) XTAL 1 should be driven, while XTAL2 floats, as
P3.6 WR (external data memory write strobe) shown in Figure 4. There are no requirements on the
P3.7 RD (external data memory read strobe) duty cycle of the external clock signal, since the in-
put to the internal clocking circuitry is through a di-
RST: Reset input. A high on this pin for two machine vide-by-two flip-flop, but minimum and maximum
cycles while the oscillator is running resets the de- high and low times specified on the data sheet must
vice. An internal pulldown resistor permits a power- be observed.
on reset with only a capacitor connected to Vee. An external oscillator may encounter as' much as a
100 pF load at XTAL 1 when it starts up. This is due
ALE: Address Latch Enable output pulse for latching
to interaction between the amplifier and its feedback
the low byte of the address during accesses to ex- capacitance. Once the external signal meets the VIL
ternal memory. This pin (ALE/PROG) is also the
and VIH specifications the capacitance will not ex-
program pulse input during EPROM programming for
ceed 20 pF.
the 87C51FB.
In normal operation ALE is emitted at a constant C2
rate of Ys the oscillator frequency, and may be used r------ll t - -....---I XTAL 2
for external timing or clocking purposes. Note, how-
ever, that one ALE pulse is skipped during each ac-
cess to external Data Memory.
I-~"""--I XTAL 1
Throughout the remainder of this data sheet, ALE
will refer to the signal coming out of the ALE/PROG ...------1 vss
pin, and the pin will be referred to as the ALE/PROG 270563-3
pin. Cl. C2 = 30 pF ±10 pF for Qystals
= 10 pF for Ceramic Resonators
PSEN: Program Store Enable is the read strobe to Figure 3. Oscillator Connections
external Program Memory.
8-155
inter 87C51FB
With an external interrupt, INTO and INT1 must be
enabled and configured as level-sensitive. Holding
N/C XTAL2 the pin low restarts the oscillator but bringing the pin
back high completes the exit. Once the interrupt is
EXTERNAL
serviced, the next instruction to be executed after
OSCILLATOR XTAL 1 RETI will be the .one following the instruction that put
SIGNAL the device into Power Down.
vss
DESIGN CONSIDERATION
270563-4 • Ambient light is known to affect the internal RAM
contents during operation. If the 87C51 FB appli-
Figure 4. External Clock Drive Configuration cation requires the part to be run under ambient
lighting, an opaque label should be placed over
IDLE MODE the window to exclude light.
• When the idle mode is terminated by Ii hardware
The user's software can invoke the Idle Mode: When
reset, the device normally resumes program exe-
the microcontroller is in this mode, power consump-
cution, from where it left off, up to two machine
tion is reduced. The Special Function Registers and
cycles before the internal reset algorithm takes
the onboard RAM retain their values during Idle, but
control. On-chip hardware inhibits access to inter~
the processor stops executing instructions. Idle
nal RAM in this event, but access to the port pins
Mode will be exited if the chip is reset or if an en-
is not inhibited. To eliminate the possibility of an
abled interrupt occurs. The PCA timer/counter can
unexpected write when Idle is terminated by Je-
optionally be left running or paused during Idle set, the instruction following the one that invokes
Mode.
Idle should not be one that writes to a port pin or
to external memory.
POWER DOWN MODE
To save even more power, a Power Down mode can ONCETM MODE
be invoked by software. In this mode, the oscillator
The ONCE ("On-Circuit Emulation") Mode facilitates
is stopped and the instruction that invoked Power
testing and debugging of systems using the
Down is the last instruction executed. The on-chip
87C51FB without the 87C51FB having to be re-
RAM and Special Function Registers retain their val-
moved from ttie circuit. The ONCE Mode is invoked
ues until the Power Down mode is terminated.
by:
On the 87C51 FBeither a hardware reset or. an ex- 1) Pull ALE low whfle the device· is in reset and
ternal interrupt can cause' an exit from Power Down. PSEN is high;
Reset redefines all the SFRs but does not change 2) Hold ALE low as RST is deactivated.
the on-chip RAM. An external interrupt allows both
the SFRs and on-chip RAM to retain their values. While the device is in ONCE Mode, the Port 0 pins
go into a float state, arid the other port pins and ALE
To properly terminate Power down the reset or ex- and PSEN are weakly pulled high. The oscillator cir-
ternal interrupt should not be executed before Vee is cuit remains active. While the 87C51 FB is in this
restored to its normal operating level and must be mode, an emulator or test CPU can be used to drive
held active 10l']g enough for the oscillator to restart the circuit. Normal operation is restored when a nor-
and stabilize (normally less than 10 ms). mal reset is applied.
Table 1 Status of ·the External Pins during Idle and Power Down
Program PORT1 '
Mode ALE PSEN PORTO PORT2 PORT3
Memory
Idle Internal 1 1 Data Data Data Data
Idle External 1 1 Float Data Addre~s Data
Power Down Internal 0 0 Data Data Data Data'
Power Down External 0 0 Float Data Data Data
NOTE:
For more detailed information on the reduced power modes refer to current Embedded Controller Handbook, and Applica-
tion Note AP-252, "DeSigning with the BOC51 BH."
8-156
infef 87C51FB
ABSOLUTE MAXIMUM RATINGS* NOTICE: This data sheet contains information on
products in the sampling and initial production phases
Ambient Temperature Under Bias .. , .ODC to + 70DC of development. The specifications are subject to
Storage Temperature .......... - 65DC to + 150DC change without notice.
Voltage on EAlVpp Pin to Vss ....... OV to + 13.0V • WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
Voltage on Any Other Pin to Vss .. -0.5V to + 6.5V These are stress ratings only. Operation beyond the
IOL Per 1/0 Pin ........................... 15 rnA "Operating Conditions" is not recommended and ex-
tended exposure beyond the "Operating Conditions"
Power Dissipation .......... '................ 1.5W
may affect device reliability.
(based on PACKAGE heat transfer limitations, not
device power consumption)
ADVANCED INFORMATION-CONTACT INTEL FOR DESIGN-IN INFORMATION
D.C. CHARACTERISTICS: (TA = ODCto +70DC;Vee = 5V ±10%;Vss = OV)
Typ
Symbol Parameter Min Max Unit Test Conditions
(Note 4)
VIL Input Low Voltage -0.5 0.2Vee- 0.1 V
VIL1 Input Low Voltage EA 0 0.2Vee- 0.3 V
VIH Input High Voltage 0. 2Vec+ 0.9 Vee+ 0.5 V
(Except XTAL 1, RST) '.
VIH1 Input High Voltage (XTAL 1, RST) 0.7 Vee Vee + 0.5 V
VOL Output Low Voltage (Note 5) 0.3 V lei = 100 /l-A (Note 1)
(Ports 1, 2, and 3)
0.45 V IOL = 1.6 rnA (Note 1)
1.0 V IOL = 3.5 rnA (Note 1)
VOL1 Output Low Voltage (Note 5) 0.3 V IOL = 200 /l-A (Note 1)
(Port 0, ALE, PSEN)
0.45 V IOL = 3.2 rnA (Note 1)
1.0 V IOL = 7.0 rnA (Note 1)
VOH Output High Voltage Vee- 0.3 V IOH = -10/l-A
(Ports 1, 2, and 3)
Vee- 0.7 V IOH = -30/l-A
Vee- 1.5 V IOH = -60/l-A
VOH1 Output High Voltage Vet-0.3 V IOH = -200/l-A
(Port 0 in External Bus Mode,
Vee- 0.7 V IOH = -3.2 rnA
ALE, PSEN)
Vee- 1.5 V IOH = -7.0 rnA
IlL Logical 0 Input Current -50 /l-A VIN = 0.45V
(Ports 1, 2, and 3)
III Input leakage Current (Port 0) ±10 /l-A 0.45 < VIN < Vee-0.3V
ITL Logical 1 to 0 Transition Current -650 /l-A VIN = 2V
(Ports 1, 2, and 3)
RRST RST Pulldown Resistor 40 225 K!1
CIO Pin CapaCitance 10 pF @1 MHz, 25DC
,
lee Power Supply Current: (Note 3)
Running at 12 MHz (Figure 5) 20 40 rnA
Idle Mode at 12 MHz (Figure 5) 5 10 rnA
Power Down Mode 15 100 /l-A
8-157
87C51FB
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports
1, 2, and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make
1 to 0 transitions during bus operations: In applications where capacitance loading exceeds 100 pFs, the noise pulse on the
ALE signal may exceed O.BV. In these case!?, it may be desirable to qualify ALE with a Schmitt Trigger, or use an Address
Latch with a Schmitt Trigger Sjrol:!e input.
2. Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the 0.9 Vee specification when the
address lines are stabilizing. . .
3. See Figures 6-9 for test conditions. Minimum Vcc for Power Down is 2V.
4. Typicals are based on limited number of samples and are not guaranteed. The values listed are at room temperature and
5V.
5. Under steady state (non·transient) conditions, 10L must be extemally limited as follows:
, Maximum 10L per port pin: . 10mA '
Maximum 10L per B·bit port-
Port 0: 26 mA
Ports 1, 2 and 3: 15 mA
Maximum total 10L for all output pins: 71 mA
If 10L exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
60mA
50mA
.........- Vee
--
MAX.
40mA
30mA
ACTIVE ..........- PO
EA
~
RST
TYPICAL
-
20mA
~ LE
I-"" A~ 87C51FB
......: - ' ,....
MAX.
10mA ..
XTAL2
OmA XTALI
oMHz "MHz 8t.tHz 12WHz 1SWHz Vss
270563-24
Icc Max at other frequencies is given by: 270563-6
Active Mode All other pins disconnected
Icc max = (Osc Iraq x 3) + 4
TCLCH = TCHCL = 5, ns
Idle Mode
Icc max = (Osc Iraq x 0.5) + 4
Where Osc Freq is in MHz and Icc is in mAo Figure 6. Icc Test Condition, Active Mode
Figure 5. Icc vs Frequency
Vee
PO
RSTEA
87C51FB 87C51FB
XTAL2 XTAL2
XTALI XTALI
vss vss
270563-7 270563-8
All other pins disconnected All other pins disconnected
TCLCH = TCHCL = 5 ns
Figure 8. Icc Test Condition, Power Down Mode.
Figure 7. Icc Test Condition Idle Mode Vcc = 2.0V to 5.5V.
270563-19
Figure 9. Clock Signal Waveform for Icc Tests In Active and Idle Modes. TCLCH = TCHCL = 5 ns.
8·158
87C51FB
EXPLANATION OF THE AC SYMBOLS L: Logic level LOW, or ALE
P: PSEN
Each timing symbol has 5 characters. The first char- Q: Output Data
acter is always a 'T' (stands for time). The other R: RD signal
characters, depending on their positions, stand for T: Time
the name of a signal or the logical status of that V: Valid
signal. The following is a list of all the characters and W: WR signal
what they stand for. X: No longer a valid logic level
Z: Float
A: Address
C: Clock For example,
0: Input Data
H: Logic level HIGH TAVLL = Time from Address Valid to ALE Low
I: Instruction (program memory contents) TLLPL = Time from ALE Low to PSEN Low
A.C. CHARACTERISTICS (TA = O°C to + 70°C, Vee = 5V ± 10%, Vss = OV, Load Capacitance for
Port 0, ALE/PROG and PSEN = 100 pF, Load Capacitance for All Other Outputs = 80 pF)
ADVANCED INFORMATION-CONTACT INTEL FOR DESIGN-IN INFORMATION
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
12 MHz Oscillator Variable Oscillator
Symbol Parameter Units
Min Max Min Max
1/TCLCL Oscillator Frequency 0.5 16 MHz
TLHLL ALE Pulse Width 127 2TCLCL-40 ns
TAVLL Address Valid to ALE Low 43 TCLCL-40 ns
TLLAX Address Hold After ALE Low 53 TCLCL-30 ns
TLLlV ALE Low to Valid Instruction In 234 4TCLCL-100 ns
TLLPL ALE Low to PSEN Low 53 TCLCL:"'30 ns
TPLPH PSEN Pulse Width 205 3TCLCL-45 ns
TPLIV PSEN Low to Valid Instruction In 145 3TCLCL-105 ns
TPXIX Input Instruction Hold After PSEN 0 0 ns
TPXIZ Input Instruction Float After PSEN 59 TCLCL-25 ns
TAVIV Address to Valid Instruction In 312 5TCLCL-105 ns
TPLAZ PSEN Low to Address Float 10 10 ns
TRLRH RD Pulse Width 400 6TCLCL-100 ns
TWLWH WR Pulse Width 400 6TCLCL-100 ns
TRLDV RD Low to Valid Data In 252 5TCLCL-165 ns
TRHDX Data Hold After RD 0 0 ns
TRHDZ Data Float After RD 107 2TCLCL-60 ns
TLLDV ALE Low to Valid Data In 517 8TCLCL-150 ns
TAVDV Address to Valid Data In 585 9TCLCL-165 ns
TLLWL ALE Low to RD or WR Low 200 300 3TCLCL-50 3TCLCL+50 ns
TAVWL Address Valid to WR Low 203 4TCLCL-130 ns
TQVWX Data Valid before WR 33 TCLCL-50 ns
. TWHQX Data Hold after WR 33 TCLCL-50 ns
TQVWH Data Valid to WR High 433 7TCLCL-150 ns
TRLAZ RD Low to Address Float 0 0 ns
TWHLH RD or WR High to ALE High 43 123 TCLCL-40 TCLCL+40 ns
8-159
87C51FB
EXTERNAL PROGRAM MEMORY READ CYCLE
ALE _ _..f
PSEN _ _..f
TPXIZ
PORT 0 _ _...f AO-A7
PORT 2 A8-A15
----'
270563-9
EXTERNAL DATA MEMORY READ CYCLE
ALE
PSEN
1 - - - - - - TLLDV 'I
---0-1+--- TRLRH - - - + I
RD
PORTO INSTR. IN
PORT2 P2.0-P2.7 OR A8-A15 FROM DPH A8-A15 FROM PCH
270563-10
EXTERNAL DATA MEMORY WRITE CYCLE
-i..-TLHLL~
ALE I /
=t-TWHLH
,
!---TLLWL TWLWH
--- TAVLL
-
-TLLAX- ~ ... r--TWHQX
TQVWH
PORTO
~ rRotl~iSk DPL DATA OUT K AO-A7 FROM PCL INSTR. IN
TAVWL
PORT2
~ P2.0-P2.7 OR A8-A 15 FROM DPH X A8-A15 FROM PCH
270563-11
8-160
inter 87C51FB
SERIAL PORT TIMING - SHIFT REGISTER MODE
Test Conditions: TA = O·C to + 70·C·, Vee = SV - 10%', Vss = OV', Load Capacitance = 80 pF
+
12 MHz Oscillator Variable Oscillator
Symbol Parameter Units
Min Max Min Max
TXLXL Serial Port Clock Cycle Time 1 12TCLCL Il s
TOVXH Output Data Setup to Clock. 700 1OTCLCL -133 ns
Rising Edge
TXHOX Output Data Hold after SO 2TCLCL-117 ns
Clock Rising Edge
TXHDX. Input Data Hold After Clock 0 0 ns
Rising Edge
TXHDV Clock Rising Edge to Input 700 1OTCLCL -133 ns
Data Valid
SHIFT REGISTER MODE TIMING WAVEFORMS
EXTERNAL CLOCK DRIVE
Symbol Parameter Min Max Units
1/TCLCL Oscillator Frequency
87CS1FB 3.S 12
MHz
87C51FB-1 3.5 16
87C51FB-2 0.5 12
TCHCX High Time 20 ns
TCLCX Low Time 20 ns
TCLCH Rise Time 20 ns
TCHCL Fall Time 20 ns
EXTERNAL CLOCK DRIVE WAVEFORM
270563-13
8-161
87C51FB
A.C. TESTING INPUT
Input, Output Waveforms Float Waveforms
VLOAO+O.l V , . . - - - - - - -......
•
,vcc-os=x 0.2 VCC+O.9 ~ VLOAO >TtMING REFERENCE
POINTS
0.45 V 1 _ _ __
._0_.2_V..:C:.::C_-_O._ VLOAO-O.l V '---_ _ _ _ _....:...J VOL +0.1 V
270563-15
270563-14
For timing purposes' a port pin is no longer floating when a
AC Inputs during testing are driven at Vee - O.5V for a Logic "1" 100 mV change from load voltage occurs. and begins to float
and 0.45V for a Logic "0". Timing measuremonts are made at VIH when a 100 mV change from the loaded VOHIVOL level occurs.
min for a Logic "1" and VIL max for a Logic "0", IOL/loH <: ± 20 rnA.
EPROM CHARACTERISTICS
Table 2 shows the logic levels for programming the
Program Memory, the Encryption Table, and the
Lock Bits and for reading the signature bytes.
Table 2. EPROM Programming Modes
ALE! EAt
Mode RST PSEN P2.7 P2.6 P3.6 P3.7
PROG Vpp
Program Code Data 1 0 O' Vpp 1 0 1 1
Verify Code Data 1 0 1 1 0 0 1 1
Program Encryption Table 1 0 O' Vpp 1 0 0 1
Use Addresses 0-1 FH
Program Lock x=1 1 0 O' Vpp 1 1 1 1
Bits (LBx) x=2 1 0 O' Vpp 1 1 0 0
Read Signature 1 0 1 1 0 0 0 0
NOTES:
"1" = Valid high for that pin
"0" = Valid low for that pin
"VPP" = + 12.75V ±0.25V
• ALE/PROG is pulsed low for 100 ".s for programming. (Quick-Pulse Programming™)
PROGRAMMING THE EPROM Normally EAlVpp is held at logic high until just be-
fore ALE/PROG is to be pulsed. Then EAlVpp is
To be programmed, the part must be running with a raised to Vpp, ALE/PROG is pulsed low, and then
4 to 6 MHz oscillator. (The reason the oscillator EAlVpp is returned to a valid high Voltage. The volt-
needs to be running is that the internal bus is being age on the EAlVpp pin must be at the valid EAlVpp
used to transfer address and program data to appro- high level before a verify is attempted. Waveforms
priate internal EPROM locations.) The address of an and detailed timing specifications are shown in later
EPROM location to be programmed is applied to sections of this data sheet.
Port 1 and pins P2.0 - P2.5 of Port 2, while the code
byte to be programmed into that location is applied Note that the EAlVpp pin must not be allowed to go
to Port O. The other Port 2 and 3 pins, RST, PSEN, above the maximum specified Vpp level for any
and EAlVpp should be held at the "Program" levels amount of time. Even a narrow glitch above that volt-
indicated in Table 2. ALE/PROG is pulsed low to age level can cause permanent damage to the de-
program the code byte into the addressed EPROM vice. The Vpp source should be well regulated and
location. The setup is shown in Figure 10. free of glitches.
8-162
inter 87C51FB
+5V
Vee
Pl PO PGM DATA
RST D/vppJ+---+12.75V
ALE/PROG ~--25 100 JLS PULSES TO GND
P3.6
87C51FB
PSEN J+---O
P3.7
P2.7
XTAL2 P2.6 ~--O
---~-+--iXTAL 1
vss
270563-20
Figure 10. Programming the EPROM
Quick-Pulse Programming™ Algorithm Program Verification
The 87C51 FB can be programmed using the Quick- If the Program Lock Bits have not been pro-
Pulse Programming™ Algorithm for microcontrol- grammed, the on-chip Program Memory can be read
lers. The features of the new programming method out for verification purposes, if desired, either during
are a lower Vpp (12.75V as compared to 21V) and a or after the programming operation. The address of
shorter programming pulse. It is possible to program the Program Memory location to be read is applied
the entire 16K Bytes of EPROM memory in less than to Port 1 and pins P2.0 - P2.5. The other pins should
50 seconds with this algorithm! be held at the "Verify" levels indicated in Table 2.
The contents of the addressed locations will come
To program the part using the new algorithm, Vpp out on Port O. External pullups are required on Port 0
must be 12.75V ±0.25V. ALE/PROG is pulsed low for this operation.
for 100 j.Ls, 25 times as shown in Figure 11. Then,
the byte just programmed may be verified. After pro- If the Encryption Array in the EPROM has been pro-
gramming, the entire array should be verified. The grammed, the data present at Port 0 will be Code
Program Lock features are programmed using the Data XNOR Encryption Data. The user must know
same method, but with the setup as shown in Table the Encryption Array contents to manually "unen-
2. The only difference in programming Program Lock crypt" the data during verify.
features is that the Program Lock features cannot be
directly verified. Instead, verification of programming The setup, which is shown in Figure 12, is the same
is by observing that their features are enabled. as for programming the EPROM except that pin P2.7
is held at a logic low, or may be used as an active-
low read strobe.
8-163
intJ 87C51FB
1 1-','--------25 PULSES "
ALE/PROG:~-----rnm-
'-----'
1 "--. 10)'s M1N1" "~~~t:
ALE/PROG:---":o~I ______ ---InL._____--,n..___
270563-21
Figure 11. PROG Waveforms
+5V
AO-A7 PGM
PI PO
DATA
RST EA/Vpp
ALE/PROG
P3.6
PSEN 0
87C51FB
P3.7
P2.7 0 (ENABLE)
XTAL2 P2.S D
XTAL 1 P2.D
-P2.S
vss
270563-22
Figure 12. Verifying the EPROM
8-164
87C51FB
EPROM Program Lock Reading the Signature Bytes
, The two-level Program Lock system consists of two The signature bytes are read by the same procedure
Program Lock bits and a 32 byte Encryption Array as a normal verification of locations 030H and 031 H,
which are used to protect the program memory except that P3.6 and P3.7 need to be pulled to a
against software piracy. logic low. The values returned are:
(030H) = 89H indicates manufacture by Intel
,(031H) = 5FH indicates 87C51FB
Encryption Array
Within the EPROM array are 32 bytes of Encryption
Array that are initially unprogrammed (all 1's). Every
Erasure Characteristics
time that a byte is addressed during a verify, 5 ad- Erasure of the EPROM' begins to occur when the
dress lines are used to select a byte of the Encryp- chip is exposed to light with wavelength shorter than
tion Array. This byte is 'then exclusive-NOR'ed approximately 4,000 Angstroms. Since sunlight and
(XNOR) with the code byte, creating an Encrypted fluorescent lighting have wavelengths in this range,
Verify byte. The algorithm, with the array in the un- exposure to these light sources over an extended
programmed state (all 1's), will return the code in it's time (about 1 week in sunlight, or 3 years in room-
original, unmodified form. level fluorescent lighting) could cause inadvertent
erasure. If an application subjects the device to this
type of exposure, it is suggested that an opaque la-
Program Lock Bits bel be placed over the window.
Also included in the EPROM Program Lock scheme The recommended erasure procedure is exposure
are two Program Lock Bits which are programmed to ultraviolet light (at 2537 Angstroms) to an integrat-
as shown in Table 2. ed dose of at least 15 W-sec/cm 2. Exposing the
EPROM to an ultraviolet lamp of 12,000 )J-W/cm2
Table 3 outlines the features of programming the rating for 30 minutes, at a distance of about 1 inch,
Lock Bits. should be sufficient.
Erasing the EPROM also erases the Encryption Ar- Erasure leaves all the EPROM Cells in a 1's state.
ray and the Program Lock Bits, returning the part to
full functionality.
Table 3 Program Lock Bits and their Features
Program Lock Bits
Logic Enabled
LB1 LB2
U U No Program Lock features enabled. (Code Verify will still be
encrypted by the Encryption Array.)
P U MOVC instructions executed from external program memory
are disabled from fetching code bytes from internal memory,
EA is sampled and latched on reset, and further programming
of the EPROM is disabled. /
P P Same as above, but Verify is also disabled
U P Reserved for Future Definition
8-165
inter 87C51FB
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
(TA = 21°C to 27"C; Vee = SV±0.2SV; vss = OV)
ADVANCED INFORMATION-CONTACT INTEL FOR DESIGN-IN INFORMATION
Symbol Parameter Min Max Units
Vpp Programming Supply Voltage 12.S 13.0 V
Ipp Programming Supply Current SO mA
1/TCLCL Oscillator Frequency 4 6 MHz
TAVGL Address Setup to PROG Low 48TCLCL
TGHAX Address Hold after PROG 48TCLCL
TDVGL Data Setup to PROG Low 48TCLCL
TGHDX Data Hold after PROG 48TCLCL
TEHSH P2.7 (ENABLE) High to Vpp 48TCLCL
TSHGL Vpp Setup to PROG Low 10 JLs
TGHSL Vpp Hold after PROG 10 JLs
TGLGH PROG Width 90 110 JLs
TAVQV Address to Data Valid 48TCLCL
TELQV ENABLE Low to Data Valid 48TCLCL
TEHQZ Data Float after ENABLE 0 48TCLCL
TGHGL PROG High to PROG Low 10 JLs
EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
PROGRAMMING VERIFICATION
P1.0-P1.7
P2.0-P2.S -----C=~~~
ADDRESS ADDRESS
-TAVOV
PORT 0 -----+{:=~~~ TGHDX
DATA OUT
TAVGL
ALE/PROG - - - - - -... 1
1
TSHGLr----
TGLGH
EA/Vpp Vee Vpp
---A-"'--
EA/HIGH
TEHSH
TELOVll'-_ _ _.Ji __T_EH_O_Z_ __
P2.7
--- 270563-18
8-166
87C51FB
DATA SHEET REVISION SUMMARY
The following are the key differences between this and the -002 version of the 87C51 FB data sheet:
1. Word "maximum" was deleted from the IOL line in the ABSOLUTE MAXIMUM RATINGS.
2. Parameter VIL 1 was deleted from the DC CHARACTERISTICS.
3. Note 4 was deleted from DC CHARACTERISTICS and from the list of notes and notes were resequenced
4. Parameter IUl was deleted from the DC CHARACTERISTICS.
5. Figure 5 was replaced to show correct Icc curves.
6. External clock capacitive loading note was .added.
The following are the differences between the -002 and the -001 version of the 87C51 FB datasheet:
1. Title changed to include -1 and -2 version of the device.
2. PLCC pin connection diagram was added.
3. Package table was added.
4. Exit from power down mode was clarified.
5. Maximum IOL per I/O pin was added to the ABSOLUTE MAXIMUM RATINGS.
6. Note 6 was added to explain the maximum safe current spec.
7. Typical values for ICC table were added.
8. Note 5 was added to explain the test conditions for typical values.
9. Timing specs improved for:
TLLAX changed from TCLCL - 35 to TCLCL - 30
TLLPL changed from TCLCL - 40 to TCLCL - 30
TRHDZ changed from TCLCL - 70 to TCLCL -60
TOVWX changed from TCLCL - 60 to TCLCL - 50
TOVWH was added
10. Data sheet revision summary was added.
8-167
87C51FB
EXPRESS
• Extended Temperature Range • 3.5 MHz to 12 MHz Vee = 5V ± 10%
• Burn-In
The Intel EXPRESS system offers enhancements to the operational specifications of the 8051 family of
microcontrollers. These EXPRESS products are designed to meet the needs of those applications whose
operating requirements exceed commercial standards.
The EXPRESS program includes the commercial standard temperature range with burn·in and an extended
temperature range with or without burn·in.
With the commercial standard temperature range, operational characteristics are guaranteed over the temper·
ature range of ooe to + 70 oe. With the extended temperature range option, operational characteristics are
guaranteed over the range of - 40 e to + 85°e.
0
The optional burn·in is dynamic for a minimum time of 168 hours at 125°e with Vee = 6.9V ±0.25V, following
guidelines in MIL·STD·883, Method 1015.
Package types and EXPRESS versions are identified by a one· or two-letter prefix to the part number. The
prefixes are listed in Table 1.
For the extended temperature range option, this data sheet specifies the parameters which deviate from their
commercial temperature range limits. The commercial temperature range data sheets are applicable for all
parameters not listed here.
May 1989
8-168 Order Number: 270767-1101
87C51FB EXPRESS £@W£OO©!.§ OOOIP@rnHMl£lfO@OO
Electrical Deviations from Commercial Specifications
for Extended Temperature Range
D.C. and A.C. parameters not included here are the same as in the commercial temperature range data
sheets.
D.C. CHARACTERISTICS TA = -40°C to + 85°C; Vee = 5V ±10%;Vss = OV
Limits Test
Symbol. Parameter Unit
Min Max Conditions
IOH1 Output High Vee - 0.3 IOH = -200 p.A
PO, ALE, PSEN Vee - 0.7 V IOH = -2.5mA
Vee - 1.5 IOH = -6.0mA
VIH1 Input High V (Xtal1, RST) 0.7 Vee + 0.1 Vee + 0.5 V
VIL Input Low Voltage -0.5 0.2 Vee - 0.2 V
III Input Leakage -10 +10 0.45 < VIN < Vee
p.A
(PO)
ITL 1 to 0 transition -825 VIN = 2.0V
p.A
(Ports 1, 2, 3)
8-169
inter 87C51FB EXPRESS £@W£OO©~ O~[P©OO~£iiD©~
Table 1 Prefix Identification
Prefix Package Type Temperature Range(2) Burn-ln(3)
0 Cerdip Commercial No
TO Cerdip Extended No
LO Cerdip Extended Yes
NOTES:
2. Commercial temperature range is O'C to + 70'C. Extended temperature range is -40'C to + 85'C.
3. Burn-in is dynamic for a minimum time of 168 hours at + 125'C, Vee = 6.9V ±0.25V, following guidelines in MIL-STD-
883 Method 1015 (Test Condition OJ.
Examples:
087C51 FB indicates 87C51 FB in a cerdip package and specifiedJor commercial temperature range, without
burn-in.
L087C51 FB indicates 87C51 FB in a cerdip package and specified for extended temperature range with burn-
in.
8-170
87C51FC/83C51FC
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
32K BYTES USER PROGRAMMABLE EPROM
87CS1 FC/83CS1 FC-3.5 MHz to 12 MHz, Vee = SV±20%
87CS1FC/83CS1FC-1-3.S MHz to 16 MHz, Vee = SV ± 20%
• Three
High Performance CHMOS EPROM
• 732Interrupt
Programmable I/O Lines
• Programmable Clock Out
16-Bit Timer/Counters
• Four Level Interrupt Priority
Sources
• Programmable Counter Array with: • Programmable Serial Channel with:
• - High Speed Output, •- Framing Error Detection
- Compare/Capture, - Automatic Address Recognition
- Pulse Width Modulator,
- Watchdog Timer capabilities • TTL and CMOS Compatible Logic
Levels
• Three
Up/Down Timer/Counter
• 64K External Program Memory Space
• 32K On-Chip
Level Program Lock System
• MCS®-S1 Fully Compatible Instruction
64K External Data Memory Space
• 2S6 Bytes of EPROM • Set
• Improved QuickOn-Chip Data RAM
• Algorithm Pulse Programming™ • Power
Modes
Saving Idle and Power Down
• Boolean Processor • ONCETM (On-Circuit Emulation) Mode
MEMORY ORGANIZATION
PROGRAM MEMORY: Up to 32 Kbytes of the program memory can reside in the on·chip EPROM. In addition
the device can address up to 64K of program memory external to the chip.
OATA MEMORY: This microcontroller has a 256 x 8 on-chip RAM. In addition it can address up to 64 Kbytes of
external data memory.
The Intel 87C51 FC/83C51 FC is a single-chip control-oriented microcontroller which is fabricated on Intel's
reliable CHMOS III-E technology: Being a member of the MCS-51 family, the 87C51 FC/83C51 FC uses the
same powerful instruction set, has the same architecture, and is pin for pin compatible with the existing
MCS-51 family of products. The 87C51 FC/83C51 FC is an enhanced version of the 87C51 /80C51 BH. It's
added features make it an even more powerful microcontroller for applications that require Pulse Width
Modulation, High Speed I/O, and up/down counting capabilities such as motor control. It also has a more
versatile serial channel that facilitates mUlti-processor communications. Throughout this document 8XC51 FC
will refer to both the 83C51 FC and the 87C51 FC. .
October 1990
8-171 Order Number: 270789-002
infef 87C51 FC/83C51 FC
P2.0-P2.7
v~
.. - ----------,
Vss
..r
z
PSEN
ALE/~
TIMING
AND ~ =_-==.:....____
g!2!ffi IJL_ _ ...L-L_~=___.LJ _ _ ____l
EAjVpp
RST
CONTROL := 1;ll'\r----,,-------~~----~----><~--.1
"""
;:;
P3.0- P3.7
270789-1
Figure 1. 8XC51FC Block Diagram
PACKAGES
Part Prefix Package Type
8XC51FC P 40·Pin Plastic DIP
87C51FC D 40-Pin CERDIP
8XC51FC N 44-Pin PLCC
8-172
inter 87C51FC/83C51FC
Port 0 is also the multiplexed low-order address and
(T2) PI.O 1 Vee
(f2EX) P1.1 2 pO.a (ADO)
data bus during accesses to external Program and
(Eel) Pl.2 .} PO.t (AD1) Data Memory. In this application it uses strong inter-
(CEXO) P1.3 " 37 PO.l (ADZ) nal pullups when emitting 1's, and can source and
(CEXt) P1.4 5 PO.3 (ADS) sink several LS TTL inputs.
(CEX2) PI.S 6 PD •• (AD4)
(CEX3) PI.6 7 PO.S (ADS) Port 0 also receives the code bytes during EPROM
(CEX4) PI.7 8 PO.6 (ADS) programming, and outputs the code bytes during
PO.7 (AD7)
program verification. External pullup resistors are re-
ALE/ PROG
quired during program verification.
P2.7 (A1S)
Port 1: Port 1 is an 8-bit bidirectional 1/0 port with
P2.6 (At"')
internal pullups. The Port 1 output buffers can drive
P2.S (AIS) LS TTL inputs. Port 1 pins that have 1's written to
P2.4 (AI2) them are pulled high by the internal pullups, and in
PZ.3 (All) that state can be used as inputs. As inputs, Port 1
P~.2 (AID)
pins that are externally being pulled low will source
pz.t (A9)
current (IlL, on the data sheet) because of the inter-
nal pull ups.
270789-2
DIP In addition, Polrt 1 serves the functions of the follow-
ing special features of the 8XC51 FC:
~~~-;qilioq-:~",!
INDEX 0:: a: ii:'0:: 0::. >1/1":: f ~ f f
CORNER
~~~~~~~~~
Port Pin Alternate Function
PD •• P1.0 T2 (External Count Input to Timerl
PO.S Counter 2), Clock-Out
PO.S
PO.7 P1.1 T2EX (Timer/Counter 2 Capture I
fA/Vpp Reload Trigger and Direction Control)
He
ALE/PROG
P1.2 ECI (External Count Input to the PCA)
PSEN P1.3 CEXO (External 1/0 for Comparel
Capture Module 0)
P2.6
P.3.S P2.S P1.4 CEX1 (External 1/0 for Compare I
Capture Module 1)
P1.5 CEX2 (External 110 for Comparel
Capture Module 2)
270789-3
P1.6 CEX3 (External 1/0 for Comparel
PLCC Capture Module 3)
Figure 2. Pin Connections P1.7 CEX4 (External 1/0 for Compare I
Capture Module4)
PIN DESCRIPTIONS Port 1 receives· the low-order address bytes during
Vee: Supply voltage. EPROM programming and verifying.
Port 2: Port 2 is an 8-bit bidirectional 1/0 port with
Vss: Circuit ground. internal pullups. The Port 2 output buffers can drive
LS TTL inputs. Port 2 pins that have 1 's written to
VSS1: Secondary ground (in PLCC only). Provided to
them are pulled high by the internal pullups, and in
reduce ground bounce and improve power supply
that state can be used as inputs. As inputs, Port 2
by-passing.
pins that are externally being pulled low will source
NOTE: current (IlL, on the data sheet) because of the inter-
This pin is not a substitute for the Vss pin (pin 22). nal pullups.
Port 2 emits the high-order address byte during
Port 0: Port 0 is an 8-bit, open drain, bidirectional 1/0
fetches from external Program Memory and during
port. As an output port each pin can sink several LS
accesses to external Data Memory that use 16-bit
TTL inputs. Port 0 pins that have 1's written to them
addresses (MOVX @DPTR). In this application it
float, and in that state can be used as high-imped-
uses strong internal pullups when emitting 1'so Dur-
ance inputs.
ing accesses to external Data Memory that use 8-bit
addresses (MOVX @Ri), Port 2 emits the contents of
the P2 Special Function Register.
8-173
@
inter 87C51 FC/83C51 FC
Some Port 2 pins receive the high-order address bits When the 8XC51 FC is executing code from external
during EPROM programming and program verifica- Program Memory, PSEN is activated twice each ma-
tion. chine cycle, except that two PSEN activations are
skipped during each access to external Data Memo-
Port 3: Port 3 is an 8-bit bidirectional 1/0 port with ry.
internal pullups. The Port 3 output buffers can drive
LS TIL inputs. Port 3 pins that have 1's written to EAlVpp: External Access enable. EA must be
them are pulled high by the internal pullups, and in strapped to VSS in order to enable the device to
that state can be used as inputs. As inputs, Port 3 fetch code from external Program Memory locations
pins that are externally being pulled low will source OOOOH to OFFFFH. Note, however, that if either of
current (ilL, on the data sheet) because of the pull- the Program Lock bits are programmed, EA will be
ups. internally latched on reset.
Port 3 also serves the functions of various special EA should be strapped to Vee for internal program
features of the 8051 Family, as listed below: executions.
This pin also receives the programming supply volt-
Port Pin Alternate Function age (Vpp) during EPROM programming.
P3.0 RXD (serial input port)
P3.1 TXD (serial output port) XTAL1: Input to the inverting oscillator amplifier.
P3.2 INTO (external interrupt 0) , XTAL2: Output from the inverting oscil'ator amplifier.
P3.3 INT1 (external interrupt 1)
P3.4 TO (Timer 0 external input)
P3.5 T1 (Timer 1 external input) OSCILLATOR CHARACTERISTICS
P3.6 WR (external data memory write strobe)
P3.7 RD (external data memory read strobe) XTAL 1 and XTAL2 are the input and output, respec-
tively, of a inverting amplifier which can be config-
RST: Reset input. A high on this pin for two machine ured for use as an on-chip oscillator; as shown in
cycles while the oscillator is running resets the de- Figure 3. Either a quartz crystal or ceramic resonator
vice. The Port Pins will be driven to their reset condi- may be used. More detailed information concerning
tionwhen a minimum VIH1 is applied whether the the use of the on-chip oscillator is available in Appli-
oscillator is running or not. An internal pulldown re- cation Note AP-155, "Oscillators for Microcontrol-
sistor permits a power-dn reset with only a capacitor lers."
connected to Vee.
To drive the device from an external clock source,
ALE: Address Latch Enable output pulse for latching XTAL1 should be driven, while XTAL2 floats, as
the low byte of the address during accesses to ex- shown in Figure 4. There are no requirements on the
ternal memory. This pin (ALE/PROG) is also the duty cycle of the external clock signal, since the in-
program pulse input during EPROM programming for put to the internal clocking circuitry is through a di-
the 87C51 FC. vide-by-two flip-flop, but minimum and maximum
high and low times specified on the data sheet must
In normal operation ALE is emitted at a constant be observed.
rate of % the oscillator frequency, and may be used
for external timing or clocking purposes. Note, how- An external oscillator may encounter as much as a
ever, that one ALE pulse is skipped during each ac- 100 pF load at XTAL1 when it starts up. This is due
cess to external Data Memory. to interaction between the amplifier and its feedback
capacitance. Once the external Signal meets the VIL
If desired, ALE operation can be disabled by setting and VIH speCifications the capacitance will not ex-
bit 0 of SFR location 8EH. With the bit set, ALE is ceed 20 pF.
active only during a MOVX instruction. Otherwise the
pin is weakly pulled high.
~
2
Throughout the remainder of this data sheet, ALE D. XTAl2
will refer to the signal coming out of the ALE/PROG Cl
pin, and the pin will be referred to as the ALE/PROG XTAl1
pin. Vss
270789-4
PSEN: Program Store Enable is the read strobe to CI, C2 = 30 pF ± 10 pF for Crystals
external Program Memory. = 40 pF ± 10 pF for Ceramic Resonators
Figure 3. Oscillator Connections
8-174
intJ 87C51 FC/83C51 FC
With an external interrupt, INTO and INT1 must be
enabled and configured as level-sensitive. Holding
Nlc XTAL2
the pin low restarts the oscillator but bringing the pin
back high completes the exit. Once the interrupt is
EXTERNAL
OSCILLATOR XTAL 1 serviced, the next instruction to be executed after
SIGNAL RETI will be the one following the instruction that put
Vss the device into Power Down.
270789-5
DESIGN CONSIDERATION
Figure 4. External Clock Drive Configuration
• The window on the 87C51 FC must be covered by
an opaque label. Otherwise, the DC and AC char-
IDLE MODE acteristics may not be met, and the device may
functionally be impaired.
The user's software can invoke the Idle Mode. When
the microcontroller is in this mode, power consump- • When the idle mode is terminated by a hardware
tion is reduced. The Special Function Registers and reset, the device normally resumes program exe-
the onboard RAM retain their values during Idle, but cution, from where it left off, up to two machine
the processor stops executing instructions. Idle cycles before the internal reset algorithm takes
Mode will be exited if the chip is reset or if an en- control. On-chip hardWare inhibits access to inter-
abled interrupt occurs. The PCA timer/counter can nal RAM in this event, but access to the port pins
optionally be left running or paused during Idle is not inhibited. To eliminate the possibility of an
Mode. unexpected write when Idle is terminated by re-
set, the instruction following the one that invokes
Idle should not be one that writes to a port pin or
to external memory.
POWER DOWN MODE
To save even more power, a Power Down mode can
be invoked oy software. In this mode, the oscillator ONCETM MODE
is stopped and the instruction that invoked Power
Down is the last instruction executed. The on-chip The ONCE ("On-Circuit Emulation") Mode facilitates
RAM and Special Function Registers retain their val- testing and debugging of systems using the
ues until the Power Down mode is terminated. 8XC51 FC without the 8XC51 FC having to be re-
moved from the circuit. The ONCE Mode is invoked
On the 8XC51 FC either a hardware reset or an ex- by:
ternal interrupt can cause an exit from Power Down. 1) Pull ALE low while the device is in reset and
Reset redefines all the SFRs but does not change PSEN is high;
the on-chip RAM. An external interrupt allows both 2) Hold ALE low as RST is deactivated.
the SFRs and on-chip RAM to retain their values.
While the device is in ONCE Mode, the Port 0 pins
To properly terminate Power down the reset or ex- go into a float state, and the other port pins and ALE
ternal interrupt should not be executed before Vcc is and PSEN are weakly pulled high. The oscillator cir-
restored to its normal operating .level and must be cuit remains active. While the 8XC51 FC is in this
held active long enough for the oscillator to restart mode, an emulator or test CPU can be used to drive
and stabilize (normally less than 10 ms). the circuit. Normal operation is restored when a nor-
mal reset is applied.
Table 1. Status of the External Pins during Idle and Power Down
Program
Mode ALE PSEN PORTO PORn PORT2 PORT3
Memory
Idle Internal 1 1 Data Data Data Data
Idle External 1 1 Float Data Address Data
Power Down Internal 0 0 Data Data Data Data
Power Down External 0 0 Float Data Data Data
NOTE:
For more detailed information on the reduced power modes refer to current Embedded Controller Handbook, and Applica-
tion Note AP-252, "Designing with the 80C51BH."
8-175
87C51 FC/83C51 FC
ABSOLUTE MAXIMUM RATINGS* NOTICE: This data sheet contains preliminary infor-
mation on new products in production. The specifica-
Ambient Temperature Under Bias .... O°C to + 70°C tions are subject to change without notice.
Storage Temperature .......... -65°C to + 150°C • WARNING: Stressing the device beyond the "Absolute
Voltage on EAlVpp Pin to VSS ....... OV to + 13.0V Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
Voltage on Any Other Pin to Vss .. -0.5V to +6.5V "Operating Conditions" is not recommended and ex-
IOL Per I/O Pin .................. ~ ........ 15 mA tended exposure beyond the "Operating Conditions"
may affect device reliability.
Power Dissipation .......................... 1.5W
(based on PACKAGE heat transfer limitations, not
device power consumption)
Operating Conditions: TA (under Bias) = O°C to + 70°C, Vee = 5V ±20%, Vss = OV
. D.C. CHARACTERISTICS: (Under Operating Conditions)
Typ
Symbol Parameter Min Max Unit Test Conditions
(Note 4)
V,L Input Low Voltage -0.5 0.2Vee- 0.1 V
V,L1 Input Low Voltage EA 0 0.2Vee- 0.3 V
V,H Input High Voltage 0.2 Vee + 0.9 Vee+ 0.5 V
(Except XTAL 1, RST)
V,H1 Input High Voltage (XT AL 1, RST) 0.7 Vee Vee+ 0.5 V
VOL Output Low Voltage (Note 5) 0.3 V IOL = 100 /J-A (Note 1)
(Ports 1, 2, and 3)
0.45 V IOL = 1.6 mA (Note 1)
1.0 V IOL = 3.5 mA (Note 1)
Vou Output Low Voltage (Note 5) 0.3 V IOL = 200 /J-A (Note 1)
(Port 0, ALE, PSEN)
0.45 V IOL = 3.2 mA (Note 1)
1.0 V IOL = 7.0 mA (Note 1)
VOH Output High Voltage Vee- 0.3 V IOH = ~10 /J-A
(Ports 1, 2, and 3, ALE, PSEN)
Vee- 0.7 V IOH = -30/J-A
Vee- 1.5 V IOH = -60/J-A
VOH1 Output High Voltage Vee- 0.3 V IOH = -200/J-A
(Port 0 in External Bus Mode)
Vee- 0.7 V IOH = -3.2 mA
Vee- 1.5 V IOH = -7.0 mA
I,L Logical 0 Input Current -50 /J- A Y,N = 0.45V
(Ports 1, 2, and 3)
III Input leakage Current (Port 0) ±10 /J- A 0.45V < Y,N < Vee
ITL Logical1 to 0 Transition Current -650 /J- A Y,N = 2V
(Ports 1, 2, and 3)
RRST RST Pulldown Resistor 40 225 K!l
CIO Pin Capacitance 10 pF @1 MHz, 25°C
Icc Power Supply Current: (Note 3)
Running at 12 MHz (Figure 5) 20 40 mA
Idle Mode at 12 MHz (Figure 5) 5 10 mA
Power Down Mode 15 100 /J- A
8-176
inter 87C51FC/83C51FC
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above O.4V to be superimposed on the VOLs of
ALE and Ports 1, 2, and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when
these pins change from 1 to O. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals
may exceed 0.8V. It may be desirable to qualify ALE or other signals with Schmitt triggers or CMOS-level input logic.
2. Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the 0.9 Vee specification when the
address lines are stabilizing.
3. See Figures 6-9 for test conditions. Minimum VCC for Power Down is 2V.
4. Typicals are based on limited number of samples and are not guaranteed. The values listed are at room temperature and
5V.
5. Under steady state (non-transient) conditions, 10L must be externally limited as follows:
Maximum 10L per port pin: 10mA
Maximum 10L per 8-bit port-
Port 0: 26 mA
I;'orts 1, 2 and 3: 15 rnA
Maximum total 10L for all output pins: 71 mA
If 10L exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
60mA
SOmA
40mA
MAX. ~ vee
30mA
~
A~ TYPICA;"--
--
20mA 87C51FC
10mA
.....
~f-'" A~ ~M~X.
IDLE
IDl.E
-
TYPICAL - XTAL2
XTALt
OmA vss
OMHz 4MHz BMHz 12MHz 16MHz
270789-6
270789-7
ICC Max at other frequencies is given by: All other pins disconnected
Active Mode
TCLCH = TCHCL = 5 ns
Icc Max = (Osc Freq x 3) + 4
Idle Mode
Icc Max = (Osc Freq x 0.5) + 4 Figure 6. Icc Test Condition, Active Mode
Where Osc Freq is in MHz, Icc is in rnA.
Figure 5. Icc vs Frequency
RST RST
87C51FC 87C51FC
XTAL2 XTAL2
XTALI XTALI
Vss vss
270789-8 270789-9
All other pins disconnected All other pins disconnected
TCLCH = TCHCL = 5 ns
Figure 8. Icc Test Condition, Power Down Mode
Figure 7. Icc Test Condition Idle Mode Vcc = 2.0V to 6.0V
270789-10
Figure 9. Clock Signal Waveform for Icc Tests in Active and Idle Modes. TCLCH = TCHCL = 5 ns
8-177
inter 87C51 FC/83C51 FC
EXPLANATION OF THE AC SYMBOLS L: Logic level LOW, or ALE
P: PSEN
Each timing symbol has 5 characters. The first char- Q: Output Data
acter is always a 'T' (stands for time). The other R: RD signal
characters, depending on their positions, stand for T: Time
the name of a signal or the logical status of that V: Valid
signal. The following is a list of all the characters and W: WR signal
what they stand for. X: No longer a valid logic level
Z: Float
A: Address
C: Clock For example,
0: Input Data
H: Logic level HIGH TAVLL = Time from Address Valid to ALE Low
I: Instruction (program memory contents) TLLPL = Time from ALE Low to PSEN Low
A.C. CHARACTERISTICS (Under Operating Conditions, Load Capacitance for Port 0, ALE/PROG and
PSEN = 100 pF, Load Capacitance for All Other Outputs = 80 pF)
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
12 MHz Oscillator Variable Oscillator
Symbol Parameter Units
Min Max Min Max
1/TCLCL Oscillator Frequency 3.5 16 MHz
TLHLL ALE Pulse Width 127 2TCLCL-40 ns
TAVLL Address Valid to ALE Low 43 TCLCL-40 ns
TLLAX Address Hold After ALE Low 53 TCLCL-30 ns
TLLlV ALE Low to Valid Instruction In 234 4TCLCL-100 ns
TLLPL ALE LOw to PSEN Low 53 TCLCL-30 ns
TPLPH PSEN Pulse Width 205 3TCLCL-45 ns
TPLIV PSEN Low to Valid Instruction In 145 3TCLCL-105 ns
TPXIX Input Instruction Hold After PSEN 0 0 ns
TPXIZ Input Instruction Float After PSEN 59 TCLCL-25 ns
TAVIV Address to Valid Instruction In 312 5TCLCL-105 ns
TPLAZ PSEN Low to Address Float 10 10 ns
TRLRH RD Pulse Width 400 6TCLCL-100 ns
TWLWH WR Pulse Width 400 6TCLCL-100 ns
TRLDV RD Low to Valid Data In 252 , 5TCLCL-165 ns
TRHDX Data Hold After RD 0 0 ns
TRHDZ Data Float After RD 107 2TCLCL-60 ns
TLLDV ALE Low to Valid Data In 517 8TCLCL-150 ns
TAVDV Address to Valid Data In 585 9TCLCL-165 ns
TLLWL ALE Low to RD or WR Low 200 300 3TCLCL-50 3TCLCL+50 ns
TAVWL Address Valid to WR Low 203 4TCLCL-130 ns
TgVWX Data Valid before WR 33 TCLCL-50 ns
TWHQX Data Hold after WR 33 TCLCL-50 ns
TQVWH Data Valid to WR High 433 7TCLCL-150 ns
TRLAZ RD Low to Address Float 0 0 ns
TWHLH RD or WR High to ALE High 43 123 TCLCL-40 TCLCL+40 ' ns
8-178
87C51FC/83C51FC
EXTERNAL PROGRAM MEMORY READ CYCLE
ALE
---'
PSEN
---'
PORT 0
----'
PORT 2 AB-AI5
---..I
270789-11
EXTERNAL DATA MEMORY READ CYCLE
ALE
PSEN
i-----TLLDV 'I
- - - < - t - - - - TRLRH - - - - - I
RD
PORTO INSTR. IN
PORT2 P2.0-P2.7 OR AB-AI5 FROM DPH AB-AI5 FROM PCH
270789-12
EXTERNAL DATA MEMORY WRITE CYCLE
I
ALE
-TLHLL--
" H-TWHLH
\.
- TAVLL
------ TLLWL
- , TWLWH
I
-TLLAX- ~ .... ~TWHQX
TQVWH
PORTO
:::r AO-A7
FROM RI OR DPL
TAVWL
DATA OUT K AO-A7 FROM PCl INSTR. IN
PORT2
::::> P2.0-P2.7 OR AB-A 15 FROM DPH X AB-A 15 FROM PCH
270789-13
8-179
inter 87C51 FC/83C51FC
SERIAL PORT TIMING - SHIFT REGISTER MODE
Test Conditions: TA = O·C to + 70·C; Vee = 5V ± 20%; Vss = OV; Load Capacitance = 80 pF
12 MHz Oscillator Variable Oscillator
Symbol Parameter Units
Min Max Min Max
TXLXL Serial Port Clock Cycle Time 1 12TCLCL f-ts
TOVXH Output Data Setup to Clock 700 1OTCLCL - 133 ns
Rising Edge
TXHOX Output Data Hold after 50 2TCLCL-117 ns
Clock Rising Edge
TXHDX Input Data Hold After Clock 0 0 ns
Rising Edge
TXHDV Clock Rising Edge to Input 700 1OTCLCL -133 ns
Data Valid
SHIFT'REGISTER MODE TIMING WAVEFORMS
INSTRUCTION I 0 2 3 4 5 6 7 8
ALE
CLOCK
OUTPUT DATA IX X 3
X 4 X 5
X 6
X 7 I
I t
WRITE TO SBU, SET TI
INPUT DATA
I t
CLEAR RI SET RI
270789-14
EXTERNAL CLOCK DRIVE
Symbol Parameter Min Max Units
1/TCLCL Oscillator Frequency
8XC51FC 3,5 12
3,5 MHz
8XC51 FC-1 16
TCHCX High Time 20 ns
TCLCX Low Time 20 ns
TCLCH Rise Time 20 ns
TCHCL Fall Time 20 ns
EXTERNAL CLOCK DRIVE WAVEFORM
270789-15
8-180
intJ 87C51FC/83C51FC
A.C. TESTING INPUT
Input, Output Waveforms Float Waveforms
VCC- 0.5 -V 0.2 VCC+0.9 V- VlOAO+O.l V ~------,
VlOAO ... TIMING REFERENCE<
V~_0_.2_V.;..CC_-_0_.1_ _ _~A-
POINTS
0.45 VlOAO-O.l v .
270789-16 270789-17
AC Inputs during testing are driven at VCC-0.5V for a Logic "1" For timing purposes a port pin is no longer floating when a
and 0.45V for a Logic "0". Timing measurements are made at VIH 100 mV change from load voltage occurs, and begins to float
min for a Logic "1" and VIL max for a Logic "0". when a 100 mV change from the loaded VOHIVOL level occurs.
IOL/loH "' ± 20 mA.
Table 2. EPROM Programming Modes
ALE! EA!
Mode RST PSEN P2.6 P2.7 P3.3 P3.6 P3.7
PROG Vpp
Program Code Data H L L.J' 12.75V L H H H H
Verify Code Data H L H H L L L H H
Program Encryption H L L.J' 12.75V L H H L H
Array Address 0-3FH
Program Lock Bit 1 H L L.J' 12.75V H H H H H
Bits
Bit 2 H L L.J' 12.75V H H H L L
Bit 3 H L L.J' 12.75V H L H H L
Read Signature Byte H L H H L L L L L
DEFINITION OF TERMS PROGRAMMING THE EPROM
ADDRESS LINES: P1.0-P1.7, P2.0-P2.5, P3.4 re- The part must be running with a 4 MHz to 6 MHz
spectively for AO-A 14. oscillator. The address of an EPROM location to be
programmed is applied to address lines while the
DATA LINES: PO.0-PO.7 for 00-07. code byte to be programmed in that location is ap-
plied to data lines. Control and program signals must
CONTROL SIGNALS: RST, PSEN, P2.6, P2.7, P3.3, be held at the levels indicated in Table 2. Normally
P3.6, P3.7 EAlVpp is held at logic high until just before ALEI
PROG is to be pulsed. The EAlVpp is raised to Vpp,
PROGRAM SIGNALS: ALE/PROG, EAlVpp ALE/PROG is pulsed low and then EAlVpp is re-
turned to a high (also refer to timing diagrams).
NOTE:
Exceeding the Vpp maximum for any amount of
time could damage the device permanently. The
Vpp source must be well regulated and free of
glitches.
8-181
87C51 FC/83C51 FC
+5V
40
Vee
87e51re
31
fA/vpp PROGRAM
30 } 'SIGNALS
ALE/PROG
14
AU P3.4. --
PSEN
29
28
P2.7
27
18 P2.6
XTAL2 17
P3.7 CONTROL SIGNALS·
16
P3.6
19 13
XTAL 1 P3.3
20 Vss RST
270789-18
·See Table 2 for proper input on these pins
Figure 10. Programming the EPROM
PROGRAMMING ALGORITHM PROGRAM VERIFY
Refer to Table 2 and Figures 10 and 1i for address, Program verify may be done after each byte that is
.data, and control signals set up. To program the programmed, or after a block of bytes that is pro-
87C51 FC the following· sequence must be exer- grammed. In either case a complete verify of the
cised. entire array that has been programmed will ensure a
1. Input the valid address on the address lines. reliable programming of the 87C51 FC:
2. Input the appropriate data byte on the data The lock bits cannot be directly verified. Verification
lines. of the lock bits is done by observing that their fea-
3. Activate the correct combination of control sig- tures are enabled. Refer to the EPROM Program
nals. Lock section in this data sheet.
4. Raise EAlVpp from Vee to 12.75V ±O.25V.
5. Pulse ALE/PROG 5 times for the EPROM ar-
ray, and 25 times for the encryption table and
the lock bits.
Repeat 1 through 5 changing the address and data,
for the entire. array or until theerid of the object file is
reached.
ADDRESS X_l_6_B_mi______________ X
DATA
><__ 8_BI~
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) (
CONTROL
SIGNALS >< 7BI~ )(
_ 12.75V J
EA/Vpp
ALE/PROG
5V
TGLGH '-
270789-19
5Putses
FIgure 11. Programming Signal~s Waveforms
8-182
87C51FC/83C51FC
ROM and EPROM Lock System Reading the Signature Bytes
The 87C51 FC and the 83C51 FC program lock sys- The 8XC51 FC has 3 signature bytes in locations
tems, when programmed, protect the onboard pro- 30H, 31 H, and 60H. To read these bytes follow the
gram against software piracy. procedure for EPROM verify, but activate the control
lines provided in Table 2 for Read Signature Byte.
The 83C51 FC has a one-level program lock system
and a 64-byte encryption table. See line 2 of Table
Contents
3. If program protection is desired, the user submits Location
the encryption table with their code, and both the 87C51FC 83C51FC
lock-bit and encryption array are programmed by the
factory. The encryption array is not available without 30H 1;l9H 89H
the lock bit. For the lock bit to be programmed, the 31H 58H 58H
user must submit an encryption table.
60H FCH FCH/5CH
The 87C51 FC has a 3-level program lock system
and a 64-byte encryption array. Since this is an
EPROM device, all locations are user-programma- Erasure Characteristics (Windowed
ble. See Table 3. Packages Only)
Erasure of the EPROM begins to occur when the
Encryption Array chip is exposed to light with wavelength shorter than
approximately 4,000 Angstroms. Since sunlight and
Within the EPROM array are 64 bytes of Encryption fluorescent lighting have wavelengths in this range,
Array that are initially unprogrammed (all 1's). Every exposure to these light sources over an extended
time that a byte is addressed during a verify, 6 ad- time (about 1 week in sunlight, or 3 years in room-
dress lines are used to select a byte of the Encryp- level fluorescent lighting) could cause inadvertent
tion Array. This byte is then exclusive-NOR'ed erasure. If an application subjects the device to this
(XNOR) with the code byte, creating an Encryption type of exposure, it is suggested that an opaque la-
Verify byte. The algorithm, with the array in the un- bel be placed over the window.
programmed state (all 1's), will return the code in it's
original, unmodified form. For programming the En- The recommended erasure procedure is exposure
cryption Array, refer to Table 2 (Programming the to ultraviolet light (at 2537 Angstroms) to an integrat-
EPROM). ed dose of at least 15 W-sec/cm 2 . Exposing the
EPROM to an ultraviolet lamp of 12,000 p.W/cm 2
rating for 30 minutes, at a distance of about 1 inch,
Program Lock Bits should be sufficient.
The 87C51 FC has 3 programmable lock bits that Erasure leaves all the EPROM Cells in a 1's state.
when programmed according to Table 3 will provide
different levels of protection for the on-chip code
and data.
Erasing the EPROM also erases the encryption ar-
ray and the program lock bits, returning the part to
full functionality.
Table 3. Program Lock Bits and the Features
Program Lock Bits
Protection Type
LB1 LB2 LB3
1 U U U No Program Lock features enabled. (Code verify will still be encrypted by the
Encryption Array if programmed.)
2 P U U MOVC instructions executed from external program memory are disabled
from fetching code bytes from internal memory, EA is sampled and latched on
Reset, and further programming of the EPROM is disabled.
3 P P U Same as 2, also verify is disabled.
4 P P P Same as 3, also external execution is disabled.
Any other combination of the lock bits is not defined.
8-183
inter 87C51 FC/83C51 FC
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
(TA = 21°C to 27"C; Vee = 5V ±20%; vss = OV)
Symbol Parameter Min Max Units
Vpp Programming Supply Voltage 12.5 13.0 V
Ipp Programming Supply Current 75 mA
1/TCLCL Oscillator Frequency 4 6 MHz
TAVGL Address Setup to PROG Low 48TCLCL
TGHAX Address Hold after PROG 48TCLCL
TDVGL Data Setup to PROG Low 48TCLCL
TGHDX Data Hold after PROG 48TCLCL
TEHSH (Enable) High to Vpp 48TCLCL
TSHGL Vpp Setup to PROG Low 10 f-ts
TGHSL Vpp Hold after PROG 10 f-ts
TGLGH PROG Width 90 110 f-ts
TAVOV Address to Data Valid 48TCLCL
TELOV ENABLE Low to Data Valid 48TCLCL
TEHOZ Data Float after ENABLE 0 48TCLCL
TGHGL PROG High to PROG Low 10 f-ts
EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
PROGRAMMING VERIFICATION
AO-A15---------1::::~A§DD~REES~S~:::::)_----------1::::!A§DD~REES~S:::>---------
-TAVQV
DO-D7---------1~::~~~:::::~----~------_1~DA~~~OU~T~~----------
TDVGL~ TGHDX
TAVGL TGHAX
ALE/PROG ------------""\1
TSHGLr--
TGLGH
EA/Vpp
Vce A Vpp
-------*-..-.. ~ITEHSH
CONTROL _ _..........
SIGNALS
TEHQZ'
(ENABLE) - - - - '
270789-20
8-184
87C51 FC/83C51 FC
DATA SHEET REVISION SUMMARY
The following differences exist between this data sheet and the previous version (270789-001):
1. Changed title from "87C51FC" to "87C51 FC/83C51 FC".
2. Changed data sheet status from "Advanced" to "Preliminary".
3. Deleted all references to -2 version.
4. Added "Four Level Interrupt Priority" feature bullet.
5. Changed feature bullet, "Two Level Program Lock System" to read, "Three Level Program Lock System".
6. Revised RST pin description to include asynchronous port reset feature.
7. Changed Figure 3 to read, "= 40 pF ± 10 pF for Ceramic Resonators".
8. Added VIL1 specification to D.C. Characteristics Table.
9. Changed test conditions under III from OV to 0.45V for VIN minimum.
10. Changed Vee maximum from 5.5V to 6.0V for lee Test Condition under Figure 8.
11. Revised Absolute Maximum Ratings warning and data sheet status notice.
12. Reworded D.C. Characteristics Note 1.
13. Changed 1/TCLCL Minimum specification from 0.5 MHz to 3.5 MHz.
14. Revised "EPROM Program Lock" section to include ROM lock description.,
15. Deleted all references to A 15 in "Definition of Terms" and Figure 10.
16. Changed number of encryption array address lines from 5 to 6 under "Encryption Array" section.
17. Added signature byte table to "Reading the Signature Bytes" section.
18. Added this revision summary.
8-185
87C51 FC/83C51 FC
EXPRESS
87C51FC/83C51 FC-3.5 MHz to 12 MHz, Vee = 5V ±20%
87C51FC-1/83C51FC-1-3.5 MHz to 16 MHz, Vee = 5V ± 20%
• Extended Temperature Range • Burn-In
The Intel EXPRESS system offers enhancements to the operational specifications of the MCS®-51 family of
microcontrollers. These EXPRESS products are designed to meet the needs of those applications whose
operating requirements exceed commercial standards.
The EXPRESS program includes the commercial standard temperature range with burn-in and an extended
temperature range with or without burn-in.
With the commercial standard temperatl,Jre range, operational characteristics are guaranteed over the temper-
ature range of O°C to 70°C. With the extended temperature range option, operational characteristics are
guaranteed over the range of - 40°C to + 85°C.
The optional burn-in is dynamic for a minimum time of 168 hours at 125°C with Vee = 6.9V ± 0.25V, following
guidelines in MIL-STD-883, Method 1015.
Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part number. The
prefixes are listed in Table 1. .
For the extended temperature range option, this data sheet specifies the parameters which deviate from their
commercial temperature range limits. The commercial temperature range data sheets are applicable for all
parameters not listed here. This data sheet is valid in conjunction with the commercial 87C51 FC/83C51 FC
data sheet, 270789-002.
October 1990
8-186 Order Number: 270903-001
87C51FC/83C51FC EXPRESS
Electrical Deviations from Commercial Specifications for Extended Temperature
Range
D.C. and A.C. parameters not included here are the same as in the commercial temperature range data
sheets.
D.C. CHARACTERISTICS TA = -40°C to + 85°C; VCC = 5V ±20%; Vss = OV
Limits Test
Symbol Parameter Unit
Min Max Conditions
ITL Logical 1 to 0 Transition Current -750 p.A VIN = 2V
(Ports 1, 2 and 3)
Table 1. Prefix Identification
Prefix Package Type Temperature Range Burn-In
P Plastic Commercial No
0* Cerdip Commercial No
N PLCC· Commercial No
TP Plastic Extended No
TO* Cerdip Extended No
TN PLCC Extended No
LP Plastic Extended Yes
LO* Cerdip Extended Yes
LN PLCC Extended Yes
NOTE:
• Commercial temperature range is O'C to 70°C. Extended temperature range is -40°C to + 85°C.
• Burn·in is dynamic for a minimum time of 168 hours at 125°C, Vee = 6.9V ±0.25V, following guidelines in MIL·STO·883
Method 1015 (Test Condition 0).
'Available for 87C51FC only.
Examples:
P87C51 FC indicates 87C51 FC in a plastic package and specified for commercial temperature range, without
burn·in.
L087C51 FC indicates 87C51 FC in a cerdip package and specified for extended temperature range with burn·
in.
DATA SHEET REVISION SUMMARY
This is Rev. 1 of the 87C51 FC/83C51 FC Express data sheet.
8-187
87C51GB/80C51GB
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
87C51GB-8K Bytes OTP/Factory Programmable ROM
80C51GB-CPU with RAM and I/O
3.5 MHz-16 MHz ±20% Vee
• 8K Bytes On-Chip ROM/OTP ROM
• -48 40Programmable I/O Lines with:
• 256 Bytes of On-Chip Data RAM Schmitt Trigger Inputs
• -15 7Interrupt
• Two Programmable Counter Arrays
with:
Sources with:
External, 8 Internal Sources
- 4 Programmable Priority Levels
- 2 x 5 High Speed Input/Output
Channels Compare/Capture
- Pulse Width Modulators
• Pre-Determined Port States
- Watchdog Timer Capabilities • High Performance CHMOS Process
• Three 16-Bit Timer/Counters with
- Four Programmable Modes:
• TTL and CHMOS Compatible Logic
Levels
- Capture, Baud Rate Generation • 64K
Power Saving Modes
(Timer 2)
• 64K External
External Data Memory Space
• Dedicated Watchdog Timer
• Three Level Program
Program Memory Space
• -8-Bit, 8-Channel A/D with:
Eight 8-Bit Result Registers • ONCETM (ON-Circuit Emulation)
Lock System
- Four Programmable Modes • Quick Pulse Programming™ Algorithm
Mode
• -Programmable Channel with:
Serial. • MCS®-51 Fully Compatible Instruction
Framing Error Detection
- Automatic Address Recognition
• Set
• Serial Expansion Port
• Boolean Processor
• Programmable Clock Out
• OSCillator Fall Detect
• Available in 68-Pin PLCC
MEMORY ORGANIZATION
PROGRAM MEMORY: Up to 8K bytes of the program memory can reside in the on-chip ROM. Also, the device
can address up to 64K of program memory external to the Chip.
DATA MEMORY: This microcontroller has a 256 x 8 on-chip RAM. In addition it can address up to 64K bytes of
external data memory.
The Intel 87C51 GB is a single-chip control oriented microcontroller which is fabricated on Intel's CHMOS III-E
technology. The 87C51 GB is an enhanced version of the 87C51 FA and uses the same powerful instruction set
and architecture as existing MCS®-51 products. Added features make it an even more powerful microcontrol-
ler for applications that require On-Chip AID, Pulse Width Modulation, High Speed I/O, up/down counting
. capabilities and memory protection features. It also has a more versatile serial channel that facilitates multi-
processor communications.
June 1990
8-188 Order Number: 270869-001
inter 87C51GB/80C51GB
P2 .0- P2.7
~
-
Vee r - - - - - - - - - - - - -
Vss •
SfRs
TIMERs
P.C.A
P.CA.1
SERIAL PORTS
P5EN
ALE/PROG
EAjVPP
RESET
,.--.::.:;.-.....- " - TRIGIN
COMPREF
AV REf
....,.-.."T'"........I-. AVss
Pl.D - P1.7 P5.0- P5.7 P4.0- P4.7 P3.0- P3.7
_c A
270869-1
Figure 1. 87C51GB Block Diagram
8·189
87C51GB/80C51GB
PARALLEL 1/0 PORTS Port Pins as Inputs
The 87C51GB contains six 8-bit parallel 1/0 ports. The pins of all six ports are configured as inputs by
All six ports are bidirectional and consist of a latch, writing a logic 1 to them. Since Port 0 is an open
an output driver, and an input buffer. Many of the drain port, it provides a very high input impedance.
port pins have multiplexed 1/0 and control functions. Since pins of Port 1, 2, 3, 4 and 5 have weak pullups
(which are always on), they source a small current
when driven low externally. All ports except Port 0
Port Pins as Outputs have Schmitt trigger inputs.
Port 0 has open drain outputs when it is not serving
as the external data bus. The internal pullup is active Port States during Reset
only when the pin is outputting a logic 1 during exter-
nal memory access. An external pullup resistor is Ports 0 and 3 reset asynchronously to a one and
required on Port 0 when it is serving as an output Ports 1, 2, 4, and 5 reset to a zero asynchronously.
port.
Ports 1, 2, 3, 4, and 5 have quasi-bidirectional out- PIN DESCRIPTIONS
puts. A strong pullup provides a fast rise time when
the pin is set to a logic 1. This pullup turns on for two The 87C51 GB will be packaged in the 68-lead PLCC
oscillator periods to drive the pin high and then turns package. Its pin assignment is shown in Figure 2.
off. The pin is held high by a weak pull up.
Writing the PO, P1, P2, P3, P4 or P5 Special Function
Register sets the corresponding port pins. All six
port registers are bit addressable.
C1EX2/P4.S P2.3/All
C1EX3/P4.6 P2.2/Al0
C1EX4/P4.7 P2.1/A9
Vee P2.0/A8
,
ps.o EA/Vpp
PS.l ALE/PROG'
lNT2/PS.2 PSEN
lNT3/PS.3 XTAL2
INT4/PS.4 87CS1GB XTAL1
INTS/PS.5 (TOP VIEW)
Vss
INT6/PS.6 TRIGIN
PS.7 ACHO
T2/P1.0 ACHI
T2EX/P1.1 ACH2
ECI/P1.2 ACH3
CEXO/Pl.3 ACH4
CEX1/P1.4 ACHS
270869-3
'OTP only
Figure 2. Pin Connections
8-190
infef 87C51GB/80C51GB
ALTERNATE PORT FUNCTIONS
Ports 0, 1, 2, 3, 4 and 5 have alternate functions as well as their I/O function as described below.
Port Pin Alternate Function
PO.O/ ADO-PO.7 / AD7 Multiplexed Address/Data for External Memory
P1.0/T2 Timer 2 External Clock Input/Clock-Out
P1.1/T2EX Timer 2 Reload/Capture/Direction Control
P1.2/ECI PCA External Clock Input
P1.3/CEXO-P1.7/CEX4 PCA Capture Input, Compare/PWM Output
P2.0/ A8-P2.7 / A15 High Byte of Address for External Memory
P3.0/RXD Serial Port Input
P3.1/TXD Serial Port Output
P3.2/INTO External Interrupt 0
P3.3/INT1 External Interrupt 1
P3.4/TO Timer 0 External Clock Input
P3.5/T1 Timer 1 External Clock Input
P3.6/WR Write Strobe for External Memory
P3.7/RD Read Strobe for External Memory
P4.0/SEPCLK Clock Source for Serial Expansion Port
P4.1/SEPDAT Data I/O for the Serial Expansion Port
P4.2/ECI1 PCA 1 External Clock Input
P4.3/C1 EXO-P4.7 /C1 EX4 PCA1 Capture Input, Compare/PWM Output
P5.2/INT2-P5.6/INT6 External Interrupt INT2-INT6
Vee: Supply Voltage. PSEN: Program Store Enable is the read strobe to
external Program Memory.
Vss: Circuit Ground.
When the 87C51GB is executing code from external
RESET: Reset input. A low on this pin for two ma- Program Memory, PSEN is activated twice each ma-
chine cycles while the oscillator is running resets the chine cycle, except that two PSEN activations are
device. An internal pullup resistor permits a power- skipped during each access to external Data Memo-
on with only a capacitor connected to Vss. ry.
ALE/PROG: Address Latch Enable output pulse for EA/Vpp: External Access enable. EA must be
latching the low byte of the address during accesses strapped to Vss in order to enable the device to
to external memory. This pin (ALE/PROG) is also fetch code from external Program Memory locations
the program pulse input during programming of the OOOOH to 1FFFH. Note, however, that if either of the
87C51GB. Program Lock bits are programmed, EA will be inter-
nally latched on reset. .
In normal operation ALE is emitted at a constant
rate of % the oscillator frequency, and may be used EA should be strapped to Vee for internal program
for external timing or clocking purposes. Note, how- executions.
ever, that one ALE pulse is. skipped during each ac-
cess to external Data Memory. This pin also receives the 12.75V programming sup-
ply voltage (Vpp) during programming.
Throughout the remainder of this data sheet, ALE
will refer to the signal coming out of the ALE/PROG XTAL 1: Input to the inverting oscillator amplifier.
pin, and the pin will be referred to as the ALE/PROG
pin. XTAL2: Output from the inverting oscillator amplifi-
er.
8-191
inter 87C51GB/80C51GB
AID CONVERTER which of the six PCAIPCA 1 interrupts has occurred.
The EC Bit in the IE (Interrupt Enable) Special Func-
The 87C51GB A/D converter has a resolution of 8 tion Register is a global interrupt enable for the PCA.
bits and an accuracy of ± 1 LSB. The conversion
time for a single channel is 20 /Ls at a clock frequen-
cy of 16 MHz with the sample and hold function in-
cluded. Independent supply voltages are provided P1.7/P4.7 ~ REG/COM MODULE 4
(CEX4)/(C1EX4) t--------I
for the AID. Also, the AID operates both in Normal Pl.6/P4.6 ~ REG/COM MODULE 3
Mode or in Idle Mode. (CEX3)/(Cl EX3) t--------I
Pl.5/P4.5 ~ REG/COM MODULE 2
The AID has 8 analog input pins; ACHO (AID CHan- (CEX2)/(Cl EX2) t--------I
P1.4/P4.4 ~ REG/COM MODULE 1
nel 0) ... ACH7, 1 reference input pin; COMPREF (CEX1)/(C1EX1) t--------I
(COMParison REFerence), 1 control input pin; TRI- Pl.3/P4.3 ~ REG/COM MODULE 0
(CEXO)/(C1EXO) ' -_ _ _ _ _ _....1
GIN (TRIGger IN), and 2 power pins; AVREF (Volt-
age REFerence) and analog ground (ANalog
GrouND). In addition, the AID has 8 conversion re-
tt ... t t
sult registers; ADRESO (AID result for channel 0) ... COUNTER MODULE
ADRES7, 1 comparison result register; ACMP (Ana-
270869-4
log Comparison), and 1 control register; ACON (A/D
Control). Figure 3. Programmable Counter Arrays
The control bit ACE (AID Conversion Enable) in
ACON controls whether the A/D is in operation or OSCILLATOR CHARACTERISTICS
not. ACE = 0 idles the A/D. ACE = 1 enables AID
conversion. The control bit AIM (AID Input mode) in XTAL 1 and XTAL2 are the input and output, respec-
ACON controls the mode of channel selection. AIM tively, of an inverting amplifier which can be config-
= 0 is the Scan Mode, and AIM = 1 is the Select ured for use as an on-chip oscillator, as shown in
Mode. The result registers ADRES4 ... ADRES7 al- Figure 4. Either a quartz crystal or ceramic resonator
ways contain the result of a conversion from the cor-\ may be used. More detailed information concerning
responding channels ACH4 ... CH7. However, the the use of the on-chip oscillator is available in Appli-
result registers ADRESO ... ADRES3 depend on the cation Note AP-155, "Oscillators for Microcontrol-
mode selected. In the scan mode, ADRESO ... lers."
ADRES3 contain the values from ACHO ... ACH3. In
the Select Mode, one of the four channels ACHO ... To drive the device from an external clock source,
ACH3 is converted four times, and the four values XTAL should be driven, while XTAL2 floats, as
are stored sequentially in locations ADRESO ... shown in Figure 5. There are no requirements on the
ADRES3. Its channel is selected by bits ACS1 and duty cycle of the external clock Signal, since the in-
ACSO (AID Channel Select 1 and 0) in ACON. put to the internal clocking circuitry is through a di-
vide-by-two flip-flop, but minimum and maximum
high and low times specified on the data sheet must
PROGRAMMABLE COUNTER ARRAYS be observed.
The Programmable Counter Arrays (PCA-PCA1) are
each made up of a Counter Module and five Regis-
C2
ter/Comparator Modules as shown below. The
1--.....--1 XTAL2
16-bit output of the counter module is available to all
five Register/Comparator Modules, providing one
common timing reference. Each Register/Compara- o
tor Module is associated with a pin of Port 1/Port 4 .
t--~--t XTAL 1
and is capable of performing input capture, output
compare and pulse width modulation functions. The ..--------1 vss
PCAs are exactly the same in function except for the
addition of clock input sources on PCA 1. 270869-5
Cl, C2 = 30 pF ± 10 pF for Crystals
The PCA Counter and five Register/Comparator = 10 pF for Ceramic Resonators
Modules each have a status bit in the CCON/
C1 CON Special Function Registers. These six Figure 4. Oscillator Connections
status bits are set according to the selected modes
of operation described below. The CCON/C1 CON
Register provides a convenient means to determine
8-192
inter 87C51GB/80C51GB
ured as level sensitive. To properly terminate Power
Down the reset or external interrupt should not be
N/C XTAL2 executed before Vee is restored to its normal oper-
ating level, and must be held active long enough for
the oscillator to restart and stabilize. The Oscillator
EXTERNAL
OSCILLATOR XTAL 1 Fail Detect must be disabled prior to entering Power
SIGNAL Down.
DESIGN CONSIDERATIONS
270869-6
• When the idle mode is terminated by a hardware
Figure 5. External Clock Drive Configuration reset, the device normally resumes program exe-
cution, from where it left off, up to two machine
cycles before the internal reset algorithm takes
IDLE MODE contro\. On-chip hardware inhibits access to inter-
nal RAM in this event, but access to the port pins
The user's software can invoke the Idle Mode. When is not inhibited. To eliminate the possibility of an
the micro controller is in this mode, power consump- unexpected write when Idle is terminated by re-
tion is reduced. The Special Function Registers and set, the instruction following the one that invokes
the onboard RAM retain their values during idle, pe- Idle should not be one that writes to a port pin or
ripherals continue to operate, but the processor to external memory.
stops executing instructions. Idle Mode will be exited • Once RESET is no longer at logic 0, the
if the chip is reset or if an enabled interrupt occurs. 8XC51GB will remain in its reset condition for up
The PCA timer/counter can optionally be left run- to 5 machine cycles (60 oscillator periods) after
ning or paused during Idle Mode. The Watchdog RESET reaches VIH1. .
Timer continues to count in Idle Mode and must be
serviced to prevent a device RESET while in Idle.
ONCETM MODE
POWER DOWN MODE The ONCE ("On-Circuit Emulation") Mode facilitates
testing and debugging of systems using the
To save even more power, a Power Down mode can 87C51GB without the 87C51GB having to be re-
be invoked by software. In this mode, the oscillator moved from the circuit. The ONCE Mode is invoked
is stopped and the instruction that invoked Power by:
Down is the last instruction executed. The on-chip
1) Pulling ALE low while ·the device is in reset and
RAM and Special Function Registers retain their val-
PSEN is high;
ues until the Power Down mode is terminated.
2) Holding ALE low as RESET is deactivated.
On the 87C51GB either a hardware reset or an ex-
ternal interrupt can cause an exit from Power Down. While the device is in ONCE Mode, the Port 0 pins
Reset redefines all the SFRs but does not change go into a float state, and the other port pins and ALE
the on-chip RAM. An external interrupt does not re- and PSEN are weakly pulled high. The oscillator cir-
define the SFR's or change the on-chip RAM. An cuit remains active. While the 87C51 GB is in this
external interrupt will modify the interrupt associated mode, an emulator or test CPU can be used to drive
SFR's in the same wayan interrupt will in all other the circuit. Normal operation is restored when a nor-
modes. The interrupt must be enabled and config- mal reset is applied.
Table 1. Status of the External Pins during Idle and Power Down
Program
Mode ALE PSEN PORTO PORT1 PORT2 PORT3
Memory
Idle Internal 1 1 Data Data Data Data
Idle External 1 1 Float Data Address Data
Power Down Internal 0 0 Data Data Data Data
Power Down External 0 0 Float Data Data Data
NOTE:
For more detailed information on the reduced power modes refer to current Embedded Controller
Handbook, and Application Note AP·252, "Designing with the BOC51 BH."
8-193
inter 87C51GB/80C51GB
Watchdog Timer (WOn Four Interface Modes- High/Low/Falling/Rising
Edges.
The 87C51GB contains a dedicated Watchdog Tim- Interrupt Driven ..
er (WDn to allow recovery from a software or hard-
ware upset. The WDT consists of a 14-bit counter
which is cleared on Reset, and subsequently incre- Oscillator Fail Detect (OFO)
mented every machine cycle. While the oscillator is
running, the WDT will be incrementing and cannot The Oscillator Fail Detect circuitry triggers a reset if
be disabled. The counter may be reset by writing the oscillator frequency is lower than the OFD trig-
1EH and E1 H in sequence to .the WDTRST Special ger frequency. It can be disabled by software during
Function Register. If the counter is not reset before Power Down Mode and has the following features.
it reaches 3FFFH (16383D), the chip will be forced
into a reset sequence by the WDT. This works out to OFD Trigger Frequency: Below 20 KHz, the
1.024 ms @ 16 MHz. WDTRST is a write only regis- 87C51GB will be held in reset. Above 400KHz,
ter. TheWDT does not force the external reset pin the 87C51GB will not be held is reset.
low.
Functions in Normal and Idle Modes.
While in Idle mode the. WDT continues to count. If Reactivated by Reset (or External Interrupt Ze-
the user does not wish to exit Idle with a reset, then ro/One Pins) after Software Disable.
some internal or external hardware must be dedicat-
ed to service the WDT during Idle. In Power Down
mode, the WDT stops counting and holds its current
value.
Serial Expansion Port (SEP)
The Serial ,Expansion Port is a half-duplex synchro"
no us serial interface with the following features:
Four Clock Frequencies- XTALl12, 24, 48,96.
8-194
inter 87C51GB/80C51GB
ABSOLUTE MAXIMUM RATINGS· NOTICE: This document contains information on
products in the design phase of development. Do not
Ambient Temperature under Bias .... o·e to + 70·e finalize a design with this information. Revised infor.-
Storage Temperature .......... - 65·e to + 150·e mation will be published when the product is avail-
able.
Voltage on EAlVpp
Pin to Vss ......... ',' .......... OV to + 13.0V· 'WARNlNG: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
Voltage on Any Other These are stress ratings only. Operation beyond the
Pin to Vss .................... -0.5V to +6.5V "Operating Conditions" is not recommended and ex-
Power Dissipation .......................... 1.5W tended exposure beyond the "Operating Conditions"
(Based on Package heat transfer limitations, not de- may affect device reliability.
vice power consumption)
NOTICE: This document contains Information on
'OTP only. products in the design phase of development. Con-
tact the Intel Sales Office for availability and current
specifications before finalizing a design.
o.C. CHARACTERISTICS T A = o·e to + 70·e·, Vee = 50V +- 20%', Vss = OV
Targeted Targeted Targeted
Symbol Parameter Typ(1) Unit Test Conditions
Min Max
VT+ High-Going Threshold TBD TBD V
(Ports 1', 2, 3, 4 and 5)
VL Low-Going Threshold TBD TBD V
(Ports 1, 2, 3, 4 and 5)
VHYS Hysteresis (VT + - VT_) TBD V
(Ports 1, 2, 3,4 and 5)
VIL Input Low Voltage -0.5 0.2 v'ee - 0.1 V
(XTAL1, RST, PortO)
VIH Input High Voltage 0.2 Vee + 0.9 Vee + 0.5 V
(Port 0)
VIHl Input High Voltage 0.7 Vee Vee + 0.5 V
(XTAL1, RST) .
VOL Output Low Voltage 0.3 V IOL = 100 p.A (2,3)
(Ports 1, 2, 3, 4 and 5) IOL = 1.6 rnA (2,3)
0.45 V
1.0 V IOL = 3.5 rnA (2,3)
VOL1 Output Low Voltage 0.3 V IOL == 200 p.A (2,3)
(Port 0, PSEN) IOL = 3.2 rnA (2,3)
0.45 V
1.0 V IOL = 7.0 rnA (2,3)
VOL2 Output Low Voltage 0.3 V IOL = 200 p.A (2,3)
(ALE) IOL = 3.2 rnA (2,3)
0.45 V
1.8 V IOL = 7.0 rnA (2,3)
VOH Output High Voltage Vee - 0.3 V IOH = -10 p.A (4)
(Ports 1, 2, 3, 4 and 5, V IOH = -30 p.A (4)
Vee - 0.7
ALE, PSEN)
Vee - 1.5 V IOH = -60 p.A (4)
VOHl Output High Voltage Vee - 0.3 V IOH = -200p.A
(Port 0 in External
Vee - 0.7 V IOH = -3.2 rnA
Bus Mode)
Vee - 1.5 V IOH = -7.0mA
8-195
intJ 87C51GB/80C51GB
D.C. CHARACTERISTICS TA = O°C to + 70°C; VCC = 5.0V :t 20%; VSS = OV (Continued)
Targeted Targeted Targeted
Symbol Parameter Typ(l) Unit Test Conditions
Min Max
I,l Logical 0 Input Current -50 /-LA Y,N = 0.45V
(Ports 1, 2, 3, 4, 5)
III Logical l-to-O Transition -650 /-LA Y,N = 2.0V
Current (Ports 1, 2, 3, 4, 5)
VTL Logical l-to-O Transition TBD V
Voltage (Ports 1, 2, 3, 4, 5)
III Input Leakage Current ±10 /-LA 0.45 < Y,N < Vcc
(Port 0)
RRST RST Pullup Resistor 40 225 k.fl
C'O Pin Capacitance 10 pF Freq = 1 MHz
TA = 25°C
Ipo Power Down Current 150 200 /-LA (5)
IOl Idle Mode Current 8 15 mA (5)
Icc Operating Current 26 50 mA (5)
IREF AID Converter Reference 2 5 mA
Current
NOTES:
1. Typical values are obtained using Vee = 5.0V, TA = 25°C, early manufacturing lots and are not guaranteed.
2. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per Port Pin: 10 mA
Maximum IOL per 8-Bit Port-
Port 0: 26 mA
Ports 1 -5: 15 mA
Maximum Total IOL for All Outputs Pins: 101 mA
If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current
greater than the listed test conditions. .
3. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL s of ALE and Ports
1 and 3. The "ground bounce" is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these
pins make 1 to 0 transitions during bus operations. In applications where capacitive loading exceeds 100 pF, the noise pulse
on the ALE signal. may exceed O.BV. In these cases, it may be desirable to qualify ALE with f Schmitt Trigger or use an
Address Latch with a Schmitt Trigger Strobe input.
4. Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the 0.9 Vee specification when the
address lines are stabilizing. .
5. See Figures 6-10 for test conditions. Minimum Vee for Power Down is 2V.
8-196
inter 87C51 GB/80C51 GB
60mA ,------,----r----,-----,
16t.lHz
270869-8
270869-7
ICC Max at other frequencios is given by: All other pins disconnected.
Active Mode TCLCH = TCHCL = 5 ns
Icc Max = (Osc Freq :- 3) 1- 4
Idle Mode Figure 7. Ice Test Condition,
Icc Max = (Osc Freq )( 0.5) + 4 Active Mode
Where Osc Freq is in MHz, Icc is in rnA.
Figure 6. Icc vs Frequency
87C51GB -=
SIGNAL
270869-10
270869-9
All other pins disconnected.
All other pins disconnected.
TCLCH = TCHCL = 5 ns
Figure 9. Icc Test Condition, Power Down Mode
Figure 8. Icc Test Condition Idle Mode Vec = 2.0V to 5.5V
270869-11
Figure 10. Clock Signal Waveform for Icc Tests in Active and Idle Modes. TCLCH = TCHCL = 5 ns.
A.C. SPECIFICATIONS
TA = O°C to + 70°C, VCC = 5.0V ±20%, Load Capacitance on Port 0, ALE, and PSEN 100 pF, Load
Capacitance on ail other outputs = 80 pF
EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS
12 MHz Osc. Variable Osc.
Symbol Parameter Targeted Targeted Units
Min Max
Min Max
1/TCLCL Osc. Freq. 3.5 16 MHz
TLHLL ALE "Pulse Width 127 2TCLCL - 40 ns
TAVLL ADDR Valid to ALE Low 43 TCLCL- 40 ns
TLLAX ADDR Hold after ALE Low 53 TCLCL - 30 ns
8-197
inter 87C51GB/80C51GB
EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS (Continued)·
12 MHzOsc. Variable Osc.
Symbol Parameter Targeted Targeted Units
Min Max
Min Max
TLLlV ALE Low to Valid Inst. IN 234 4TCLCL - 100 ns
TLLPL ALE LOWto PSEN LOW 53 TCLCL - 30 ns
TPLPH PSEN Pulse Width 205 3TCLCL - 45 ns
TPLIV PSEN Low to Valid Instr In 145 3TCLCL - 105 ns
TPXIX Input Instr. Hold after PSEN 0 0 ns
TPXIZ Input Instr. Float after PSEN 59 TCLCL - 25 ns
TAVIV ADDR to Valid Instr. In 312 5TCLCL - 105 ns
TPLAZ PSEN Low to ADDR Float 10 10 ns
TRLRH RD Pulse Width 400 6TCLCL - 100 ns
TWLWH WR Pulse Width 400 6TCLCL - 100 ns
TRLDV RD Low to Valid Data In 252 5TCLCL - 165 ns
TRHDX Data Hold after RD 0 0 ns
TRHDZ Data Float after RD 107 2TCLCL - 60 ns
TLLDV ALE Low to Valid Data In 517 8TCLCL - 150 ns
TAVDV ADDR to Valid Data In 585 9TCLCL - 165 ns
TLLWL ALE Low to RD or WR Low 200 300 3TCLCL ~ 50 3TCLCL + 50 ns
TAVWL AD DR Valid to RD or WR Low 203 4TCLCL - 130 ns
TQVWX Data Valid to WR Transition 33 TCLCL - 50 ns
TWHQX Data Hold after WR 33 TCLCL - 50 ns
TQVWH Data Valid to WR High 433 7 TCLCL - 150 ns
TRLAZ RD Low to Addr Float 0 0 ns
TWHLH RD or WR High to ALE High 43 123 TCLCL - 40 TCLCL + 40 ns
EXPLANATION OF THE A.C. L: Logic Level LOW, or ALE
SYMBOLS P:PSEN
Q: Output Data
Each timing symbol has 5 characters. The first char-
R: RD Signal
acter is always a T (stands for time). The other char-
acters, depending on their positions, stand for the T:Time
name of a signal or the logical status of that signal. V: Valid
The following is a list of all the characters and what W: WRSignal
they stand for: X: No Longer a Valid Logic Level
A: Address Z: Float
C: Clock
0: Input Data For Example:
H: Logic Level HIGH TAVLL = Time from Address Valid to ALE Low
I: Instruction (Program Memory Contents) TLLPL = Time from ALE Low to PSEN Low
8-198
inter 87C51GB/80C51GB
EXTERNAL PROGRAM MEMORY READ CYCLE
ALE
PSEN _ _oF
TPXIZ
PORT 0 AO-A7
PORT 2 A8-A15
270869-12
EXTERNAL DATA MEMORY READ CYCLE
ALE
PSEN
~----TLLDV 'I
---0-+--- TRLRH
RD
PORTO INSTR. IN
PORT2 P2.0-P2.7 OR A8-A15 FROM DPH A8-A 15 FROM PCH
270869-13
EXTERNAL DATA MEMORY WRITE CYCLE
ALE
-TLHLL-
" TWHLH
/
!+--TLLWL TWLWH
- TAVLL ~
~TLLAX- ~ " J
- -TWHOX
TOVWH
PORTO
=r AD-A7
FROM RI OR DPL
TAVWL
DATA OUT XAO-A7 FROM peL INSTR. IN
PORT2 ::::) P2.0-P2.7 OR A8-A 15 FROM DPH X AB-AI5 FROM PCH
270869-14
8-199
inter 87C51GB/80C51GB
SERIAL PORT TIMING-SHIFT REGISTER MODE
= O°C to + 70°C; Vee = 5V ± 20%; Vss = OV;
Test Conditions: TA Load Capacitance = 80 pF
12MHz Variable
Oscillator Oscillator
Symbol Parameter Targeted Targeted Targeted Targeted Units
Min Max Min Max
TXLXL Serial Port Clock 1 12TCLCL /A-s
Cycle Time
TQVXH Output Data Setup to 700 10TCLCL - 133 ns
Clock Rising Edge
TXHQX Output Data Hold after 50 2TCLCL - 117 ns
Clock Rising Edge
TXHDX Input Data Hold after 0 0 ns
Clock Rising Edge
TXHDV Clock Rising Edge to 700 10TCLCL - 133 ns
Input Data Valid
SHIFT REGISTER MODE TIMING WAVEFORMS
INSTRUCTION I 2 7 8
ALE
CLOCK
I TQVXH1iTXHQX
OUTPUT DATA 0 I 1 I 2 3 4 5 6 7
f I -l rTXHDX I
WRITE TO SBur -l TXHDV I: SET TI
INPUT DATA ---~-V~AL~IO-"'\!i::AUO~'--~ALJ~O';V'""'"\i~ALJ:-::DV-~=V--v.:V~-~AUO~'--~ALJ~D'(V
f I
CLEAR RI SET RI
270869-15
EXTERNAL CLOCK DRIVE
Symbol Parameter Min Max Units
1/TCLCL Oscillator Frequency 3.5 16 MHz
TCHCX High Time 20 ns
TCLCX Low Time 20 ns
TCLCH Rise Time 20 ns
TCHCL Fall Time 20 ns
EXTERNAL CLOCK DRIVE WAVEFORM
270869-16
8-200
infef 87C51GB/80C51GB
A.C. TESTING INPUT
Input, Output Waveforms Float Waveforms
v -o.s=><
ee .
0.45V
0.2 Vee+0.9
0.2 Vee-0.1
0..-....;;.;;.-._ _ _ _ __
>C
270869-17
270869-18
Ae inputs during testing are driven at Vee - 0.5V for a
Logie "1" and 0.5V for a Logic "0". Timing measurements For timing purposes a port pin is no longer floating
are made at VIH for a Logie "1" and VOL max for a Logie when a 100 mV change from load voltage occurs.
"0". and begins to float when a 100 mV change from
the loaded VOHIVOL level occurs. IOL/IOH ;:, ±20
mA.
A TO D CHARACTERISTICS OPERATING CONDITIONS
The absolute conversion accuracy is dependent on Vee ............................... 4.0V to 6.0V
the accuracy of AVREF. The specifications given be- AVREF ............................. 4.5V to 5.5V
low assume adherence to the Operating Conditions
section of this data sheet. Testing is done at Vss. AVss .................................. OV
AVREF = 5.12V. ACHO-7 ..................... ; .... AVsstoVREF
T A ....................... O·C to + 70·C Ambient
FOSC ........................ 3.5 MHz to 16 MHz
Test Conditions:
AVREF ................................. 5.12V
Vee .................................... 5.0V
AID CONVERTER SPECIFICATIONS T A = O·C to + 70·C
Targeted Targeted Targeted
Parameter Units" Notes
Min Typ' Max
Resolution 256 256 Levels
8 8 Bits
Absolute Error 0 ±1 LSB
Full Scale Error ±1 LSB (8)
Zero Offset Error ±1 LSB (8)
Non-Linearity 0 ±1 LSB (8)
Differential Non-Linearity 0 ±1 LSB (8)
Channel-to-Channel Matching 0 ±1 LSB (8)
Repeatability ±0.25 LSB (8)
8-201
inter 87C51GB/80C51GB
AID CONVERTER SPECIFICATIONS TA = O°Cto +70°C (Continued)
Targeted Targeted Targeted
Parameter Units" Notes
Min Typ* Max
Temperature Coefficients:
Offset 0.003 LSB/oC
Full Scale 0.003 LSBI"C (8)
Differential Non-Linearity 0.003 LSBI"C
Input Capacitance 3 pF (8)
Off Isolation -60 dB (8,9,10)
Feedthrough -60 dB (8,9)
Vcc Power Supply Rejection -60 dB (8,9)
Input Resistance to 750 1.2K fl. (8)
Sample-and-Hold Capacitor
D.C. Input Leakage 0 3.0 /LA
NOTES:
'These values are expected for most parts at 25"C
-'AN "LSB" as used here, has a value of approximately 20 mV.
8. These values are not tested in production and are based on thooretical estimates and laboratory tests.
9. DC to 100 KHz
10. Multiplexer Break-Before-Make Guaranteed.
11. There is no indication when a single AID conversion is complotc. Ploase refer to the 8XC51GB Hardware description on
how to read a single AID conversion.
AID Conversion Time Notes
Per Channel I 26TCY (8,11)
8 Conversions I 208TCY (8)
Table 2. OTP Programming Modes
ALEI EAI
Mode RST PSEN P2.6 P2.7 P3.3 P3.6 P3.7
PROG Vpp
Program Code Data L L -U 12.75V L H H H H
Verify Code Data L L H H L L L H H
Program Encryption L L -U 12.75V L H H L H
Array Address 0-3FH
Program Lock Bit 1 L L -U 12.75V H H H H H
Bits H H
Bit 2 L L -U 12.75V H L L
Bit 3 L L -U 12.75V H L H H L
Read Signature Byte L H H H L L L L L
8-202
inter 87C51GB/80C51GB
DEFINITION OF TERMS PROGRAMMING THE OTP
ADDRESS LINES: P1.0-P1.7, P2.0-P.5, P3.4-P3.5 The part must be running with a 4 MHz to 6 MHz
respectively for AO-A 15. oscillator. The address of a location to be pro-
grammed is applied to address lines while the code
DATA LINES: PO.0-PO.7 for 00-07. byte to be programmed in that location is applied to
data lines. Control and program signals must be held
CONTROL SIGNALS: RST, PSEN, P2.6, P2.7, P3.3, at the levels indicated in Table 2. Normally EAlVpp
P3.6, P3.7 is held at logic high until just before ALE/PROG is to
be pulsed. The EAlVpp is raised to Vpp, ALE/PROG
PROGRAM SIGNALS: ALE/PROG, EAlVpp is pulsed low and then EAlVpp is returned to a high
(also refer to timing diagrams).
NOTE:
Exceeding the Vpp maximum for any amount of time
could damage the device permanently. The Vpp
source must be well regulated and free of glitches.
+5V
Vee 40
87C51GB 32-39
PGM DATA
"'--
P2.0- 31
EAjV pp PROGRAM
P2.5 }
30
ALEjPROG 1 - - - - SIGNALS
14
A14 P3.4 29
PSEN
15 28
A15- P3.5 P2.7
27
18 P2.6
XTAL2 17
P3.7 CONTROL SIGNALS·
16
P3.6
19 13
XTAL 1 P3.3
20 9
vss RST
270869-19
'See Table 2 for proper input on these pins.
Figure 11. Programming the OTP
8-203
inter 87C51GB/80C51GB
PROGRAMMING ALGORITHM Repeat 1 through 5 changing the address and data
for the entire array or until the end of the object file is
Refer to Table 2 and Figures 11 and 12 for address, reached.
data, and control signals set up. To program the
87C51GB the following sequence must be exer-
cised. PROGRAM VERIFY
1. Input the valid address on the address lines. Program verify may be done after each byte that is
2. Input the appropriate data byte on the data lines. programmed, or after a block of bytes that is pro-
3. Activate the correct combination of control sig- grammed. In either case a complete verify of the
nals. entire array that has been programmed will ensure a
reliable programming of the 87C51GB.
4. Raise EAlVpp from Vee to 12.75V ±0.25V.
5. Pulse ALE/PROG 5 times for the OTP array, and The lock bits cannot be directly verified. Verification
25 times for the encryption table and the lock bits. of the lock bits is done by observing that their fea-
tures are enabled. Refer to the Program Lock sec-
tion in this data sheet.
ADDRESS X 1381TS
x
DATA X----------X
881TS
CONTROL
SIGNALS X 781TS X
J
'--
_ 12.7SV
EA/Vpp SV
TGLGH
ALE/PROG
270869-20
Figure 12. Programming Signal's Waveforms
8-204
infef 87C51GB/80C51GB
OTP Program Lock Program Lock Bits
The 87C51 GB has a 3·bit program lock system and The 87C51GB has 3 programmable lock bits that
a 64·byte encryption array which are designed to when programmed according to Table 3 will provide
protect the onboard program and data against soft· different levels of protection for the on·chip code
ware piracy. and data.
Encryption Array Reading the Signature Bytes
Within the programmable array are 64 bytes of En· The 87C51GB has 3 signature bytes in locations
cryption Array that are initially unprogrammed (all 30H, 31 H, and 60H. To read these bytes follow the
1's). Every time that a byte is addressed during a procedure for verify, but activate the control lines
verify, 5 address lines are used to select a byte of provided in Table 2 for Read Signature Byte.
the Encryption Array. This byte is then exclusive· Location: 30H = 89H
NOR'ed (XNOR) with the code byte, creating an En·
cryption Verify byte. The algorithm, with the array in 31H = 58H
the unprogrammed state (all 1's), will return the 60H = EBH
code in its original, unmodified form. For program·
ming the Encryption Array, refer to Table 2.
Table 3. Program Lock Bits and the Features
'Program Lock Bits
Protection Type
LB1 LB2 LB3
1 U U U No Program Lock features enabled. (Code verify will
still be encrypted by the Encryption Array if
programmed).
2 P U U MOVC instructions executed from external program
memory are disabled from fetching code bytes from
internal memory, EA is sampled and latched on
Reset, and further programming of the EPROM is
disabled.
3 P P U Same as 2, also verify is disabled.
4 P P P Same as 3, also external execution is disabled.
• Any other combination of lock bits IS not defined.
8·205
inter 87C51GB/80C51GB
OTP PROGRAMMING AND VERIFICATION CHARACTERISTICS
= 5V ± 20%; Vss = OV)
(TA = 21°C to 27"C; Vee
Symbol Parameter Min Max Units
Vpp Programming Supply Voltage 12.5 13.0 V
Ipp Programming Supply Current 75 mA
1/TCLCL Oscillator Frequency 4 6 MHz
TAVGL Address Setup to PROG Low 48TCLCL
TGHAX Address Hold after PROG 48TCLCL
TDVGL Data Setup to PROG Low 48TCLCL
TGHDX Data Hold after PROG 48TCLCL
TEHSH (Enable) High to Vpp 48TCLCL
TSHGL Vpp Setup to PROG Low 10 JLs
TGHSL Vpp Hold after PROG 10 JLs
TGLGH PROGWidth 90 110 JLs
TAVQV Address to Data Valid 48TCLCL
TELQV ENABLE Low to Data Valid 48TCLCL
TEHQZ Data Float after ENABLE 0 48TCLCL
TGHGL PROG High to PROG Low 10 JLs
PROGRAMMING AND VERIFICATION WAVEFORMS
PROGRAMMING VERIFICATION
AO-A 15 ----~==~AD~D~R~ES~S~ ADDRESS
-TAVOV
00-07 ------1-(=!!~~ DATA OUT
TDVGL TGHDX
ALE/PROG - - - - - -.....1
TSHGL~
TGLGH
EA/Vpp vee If' Vpp
----~-~-'~ITEHSH TEHOZ
CONTROL - - _ . _
SIGNALS _ __
270869-21
*25 Pulses for Encryption Table and Lock Bits.
8-206
87C51GB/80C51GB
AID Glossary of Terms Ideal Characteristic-A characteristic with its first
code transition at VIN = 0.5 LSB, its last code tran-
Absolute Error-The maximum difference between sition at VIN = (VREF - 1.5 LSB) and all code
corresponding actual and ideal code transitions. Ab- widths equal to one LSB.
solute Error accounts for all deviations of an actual
converter from an ideal converter. Input Resistance-The effective series resistance
from the analog input pin to the sample capacitor.
Actual Characteristic-The characteristic of an ac-
tual converter. The characteristic of a given convert- LSB-Least Significant Bit-The voltage corre-
er may vary over temperature, supply voltage, and sponding to the full scale voltage divided by 2n,
frequency conditions. An actual characteristic rarely where n is the number of bits of resolution of the
has ideal first and last transition locations or ideal converter. For an 8-bit converter with a reference
code widths. It may even vary over multiple conver- voltage of 5.12V, one LSB is 20 mV. Note that this is
sions under the same conditions. different than digital LSBs since an uncertainty of
two LSBs, when referring to an AID converter,
Break-Before-Make-The property of a multiplexer equals 40 mV. (This has been confused with an un-
which guarantees that a previously selected channel certainty of two digital bits, which would mean four
will be deselected before a new channel is selected counts, or 80 mV).
(e.g., the converter will not short inputs together).
Monotonic-The property of successive approxi-
Channel-to-Channel Matching-The difference be- mation converters which guarantees that increasing
tween corresponding code transitions of actual char- input voltages produce adjacent codes of increasing
acteristics taken from different channels under the value, and that decreasing input voltages produce
same temperature, voltage and frequency condi- adjacent codes of decreasing value.
tions.
No Missed Codes-For each and every output
Characteristic-A graph of input voltage versus the code, there exists a unique input voltage range
resultant output code for an AID converter. It de- which produces that code only.
scribes the transfer function of the AID converter.
Non-Linearity-The maximum deviation of code
Code-The digital value output by the converter. transitions of the terminal based characteristic from
the corresponding code transitions of the ideal char-
Code Center-The voltage corresponding to the acteristic.
midpoint between two adjacent code transitions.
Off-Isolation-Attenuation of a voltage applied on a
Code Transition-The point at which the converter deselected channel of the AID converter. (Also re-
changes from an output code of Q, to a code of Q + ferred to as Crosstalk.)
1. The input voltage corresponding to a code tran-
sition is defined to be that voltage which is equally Repeatability-The difference between corre-
likely to produce either of two adjacent codes. sponding code transitions from different actual char-
acteristics taken from the same converter on the
Code Width-The voltage corresponding to the dif- same channel at the same temperature, voltage and
ference between two adjacent code transitions. frequency conditions.
Crosstalk-See "Off-Isolation". Resolution-The number of input voltage levels
that the converter can unambiguously distinguish
D.C. Input Leakage-Leakage current to ground between. Also defines the number of useful bits of
from an analog input pin. information which the converter can return.
Differential Non-Linearity-The difference be- Sample Delay-The delay from receiving the start
tween the ideal and actual code widths of the termi- conversion signal to when the sample window
nal based characteristic. opens.
Feedthrough-Attenuation of a voltage applied on Sample Delay Uncertainty-The variation in the
the selected channel of the AID Converter after the sample delay.
sample window closes.
Sample Time-The time that the sample window is
Full Scale Error-The difference between the ex- open.
pected and actual input voltage corresponding to
the full scale code transition. Sample Time Uncertainty-The variation in the
sample time.
8-207
inter 87C51GB/80C51GB
Sample Window-'-Begins when the sample capaci- Terminal Based Characteristic-An actual charac-
tor is attached to a selected channel and ends when teristic which has been rotated and translated to re-
the sample capacitor is disconnected from the se- move zero offset and full scale error.
lected channel.
Vee Refection-Attenuation of noise on the Vee
Successive Approximation-An AID conversion line to the AID converter.
method which uses a binary search to arrive at the
best digital representation of an analog input. Zero Offset-The difference between the expected
and actual input voltage corresponding to the first
Temperature Coefficients-Ghange in the stated code transition.
variable per degree centrigrade temperature
change. Temperature coefficients are added to the
typical values of a specification to see the effect of DATA SHEET REVISION SUMMARY
temperature drift. 1. This is the first revision (-001).
8-208
87C51GB/80C51GB
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
Express
87C51GB-8K Bytes OTP/Factory Pro-
grammable ROM
80C51GB-CPU with RAM and I/O
3.5 MHz-16 MHz ± 20% Vee
• Extended Temperature Range
( - 40°C to +85°C) • -48 40Programmable I/O Lines with:
Schmitt Trigger Inputs
• 8K Bytes On-Chip ROM/OTP ROM
• 256 Bytes of On-Chip Data RAM
• -15 7Interrupt Sources with:
External, 8 Internal Sources
- 4 Programmable Priority Levels
• Two Programmable Counter Arrays
with: • High
Pre-Determined Port States
- 2 x 5 High Speed Input/Output
Channels Compare/Capture
• TTL and Performance CHMOS Process
- Pulse Width Modulators
- Watchdog Timer Capabilities
• Levels CHMOS Compatible Logic
• Three 16-Bit Timer/Counters with • 64K
Power Saving Modes
- Four Programmable Modes: • 64K External Data Memory Space
- Capture, Baud Rate Generation
(Timer 2) • Three Level Program Lock System
External Program Memory Space
• Dedicated Watchdog Timer •
• 8-Bit, 8-Channel AID with: • ONCETM (ON-Circuit Emulation) Mode
- Eight 8-Bit Result Registers • MCS®-51 Fully Compatible Instruction
Quick Pulse Programming™ Algorithm
•
- Four Programmable Modes
Programmable Serial Channel with:
• Set
- Framing Error Detection
- Automatic Address Recognition
• Oscillator
Boolean Processor
• Fall Detect
•
•
Serial Expansion Port
Programmable Clock Out
• Available in 68-Pin PLCC
The Intel EXPRESS system offers enhancements to the operation specifications of the MCS-51 family of
microcontrollers. These EXPRESS products are designed to meet the needs of those applications whose
operating requirements exceed commercial standards.
With the commercial standard temperature range, operational characteristics are guaranteed over the temper-
ature range of O°C to + 70°C. With the extended temperature range option, operational characteristics are
guaranteed over the range of - 40°C to + 85°C.
The 87C51 GB EXPRESS is packaged in the 68-lead PLCC package. In order to designate a part as an
EXPRESS part, a 'T' is added as a prefix to the part number. TN87C51 GB denotes an EXPRESS part in a
PLCC package.
All A.C. and D.C. parameters in the commercial data sheets apply to the EXPRESS devices.
July 1990
8-209 Order Number: 270889-001
UCS51
ASIC FAMILY OF ENHANCED a-BIT
MICROCONTROLLERS WITH USER-SELECTABLE
PERIPHERAL SET AND ROM/RAM CONFIGURATIONS
UCS5116 MHz, Vee = 5V ± 10%, 0°C-70°C Case
12 MHz, Vee = 5V ± 10%, -55°C- + 125°C Case
• SFR Bus-Compatible Peripherals
- A/D Converter
• -CoreROM,Configurations
OK-32K, 4K Increments
- Bus Interface/Port - RAM 128 Bytes and 256 Bytes
- Baud-Rate Generator - 5 and 10 Interrupts
-UART·
- Timer Counter • -De-Multiplexed Ports
Ports and Databus can be used
• -Customer-Designed SFR Peripherals
Extensive Cell Library Available
concurrently
• 1.5 Micron CHMOS III
The UCS51 microcontroller core cell allows customers to gain access to the internal peripheral bus (Special
Function Register) SFR bus. This provides .peripheral selection which exactly fits the customer's needs. When
the supplied peripheral set is insufficient, an optimum peripheral can be designed by the customer.
The SFR bus supports direct addressing of peripherals, which allows for enhanced performance, more effi-
cient code utilization, and increased bit-manipulation capability.
See the "ASIC Embedded Controller Handbook" for detailed information about the UCS51 product family.
CUSTOMER DEFINED SFR PERIPHERALS
UCS51
ASIC
CORE
NON-SFR
PERIPHERAL
IS-BIT ADDRESS BUS
270801-1
Figure 1. UeS51 Block Diagram
VAX is a trademark of Digital Equipment Corporation.
Zycad is a trademark of Zyvision.
November 1990
8-210 Order Number: 270801-002
UCS51
Table 1
Operation Case Temperature Range Voltage Range
Commercial O°C-70°C 5V ±10%
Industrial -40°C-85°C 5V ±10%
Military - 55°C-125°C 5V ±10%
PIN DESCRIPTION
RXD
SCLK IP30-37
TXD
MODEO OP30-37
INTOL
INTlL IP20-27
TO
OP20-27
Tl
WRL
IPOO-07
RDL
EAL OPOO-07
PSENL
ALE P2EXT
P2
RESET UCS51 AO-A15
(128 BYTE RAM)
ERST (5 INTERRUPTS)
CLK EADBO-7
PWRDN
SFR BUS
TOllNH
ROM EXPANSION
POINH
INTERFACE
P21NH (0 TO 32K)
P31NH
RAM EXPANSION
SCINH
~
ENHANCED INTERFACE
INTERRUPT TOIINTL (ADDITIONAL 128 BYTES)
INTERFACE TOINTSEL
INTERRUPT EXPANSION
TlIlNTL
~ UNIT (EU) INTERFACE
TllNTSEL (ADDITIONAL 5 INTERRUPTS)
SCIINTL
SCOINTL TEST INTERFACE
270BOl-2
Figure 2. UCS51 Functional Diagram
8-211
infef UCS51
CLK: The Input Clock is the clock signal input to the T1I1NTL: Timer 1 Interrupt In is the active-low Timer
UCS51 core during normal user operation. Connect 1 interrupt input. This interrupt may be reassigned to
to the output of either the POSC or PWOSC com- an external interrupt source.
panion cell when using a crystal oscillator clock
source. EADBO-7: The External Address/Data Bus must be
brought off-chip for testing and for off-chip program
TICLK: Tester Input Clock supplies the clock to the and data memory accesses. MANDATORY PACK-
UCS51 core during test. MANDATORY PACKAGE AGE PINS.
PIN.
AO-A15: AO-A15 is the 16-bit address bus for ex-
EAL: EAL is an input pin that specifies the location ternal program and data memory.
of program memory: 0 = external, 1 = internal. It is
latched on the falling edge of ERST and RESET. For IPOO-7: Input Port 0 is the demultiplexed, 8-bit Port
test purposes, EAL must be controllable from a o input bus (address = 80H)',
package pin. EAL is not present on ROMless UCS51
cores. OPOO-7: Output Port 0 is the demultiplexed, 8-bit
Port 0 output bus (address = 80H).
ALE: Address Latch Enable is used for external pro-
gram memory expansion in conjunction with PSENL. IP20-7: Input Port 2 is the demultiplexed, 8-bit Port
In conjunction with WRL and RDL, ALE is used for 2 input bus (address = AOH).
external data memory expansion. When ALE is a
logic 1, the memory address is available on EADBO- OP20-7: Output Port 2 is the demultiplexed, 8-bit
7. The entire latched address is available on AO- Port 2 output bus (address = AOH). Unlike Port 2 of
A15. the 80C51, OP20-7 is not used to output the high
order address during fetches to internal program
PSENL: Program Strobe Enable is an active-low out- memory (see P2EXT).
put that can be used to enable the output drivers of
external program memory. IP30-7: Input Port 3 is the demultiplexed, 8-bit Port
3 input bus (address = BOH).
ERST: External Reset is an active-high input that
provides an Qxternal (off-chip) reset for the entire OP30-7: Output Port 3 is the demultiplexed, 8-bit
chip during both normal user operation and testing. Port 3 output bus (address = BOH).
Do not use internal user logic to drive this input.
MANDATORY PACKAGE PIN. P2: Phase 2 Clock is a UCS51 core output clock
signal with a frequency equal to % of CLK/TICLK.
RESET: Internal Reset is an active-high input that
enables on-chip user logic to reset the UCS51 core. P2EXT: The Port 2/ A8-15 Select is an active-high
Apply a logic 1 for at least 12 oscillator periods to output signal that can be used to reconstruct the
reset the core. 80C51 Port 2 output function. While internal program
memory is selected (Le., EAL is high), P2EXT is ac-
INTOL: External Interrupt 0 is an active-low external tive during the execution of a MOVX @DPTR instruc-
interrupt input. tion. While external program memory is selected
(Le., EAL is low or the addressing limit of the internal
INT1L: External Interrupt 1 is an active-low external ROM is exceeded), P2EXT is always active except
interrupt input. during a MOVX @Ri.
SCIINTL: Serial Port Interrupt In is the active-low se- TO: Timer/Counter 0 is the Timer 0 external input
rial port interrupt input. This interrupt input may be pin.
reassigned to an external interrupt source.
T1: Timer/Counter 1 is the Timer 1 external input
SCOINTL: Serial Port Interrupt Out is an active-low pin.
output that indicates a serial port interrupt. A logical
OR of the receive interrupt flag and the transmit in- WRL: The Write Strobe is an active-low strobe out-
terrupt flag in the SCON register generates put for external data memory.
SCOINTL.
TOIINTL: Timer 0 Interrupt In is the active-low Timer
o interrupt input. This interrupt may be reassigned to
an external interrupt source.
8-212
infef UCS51
RDL: The Read Strobe is an active-low strobe out- TOPP2TO: Test Programmable Pin 2 Output .Enable
put for external data memory. controls the direction of the TPP2 PRGUCS com-
o panion cell during test mode. TOPP2TO is low dur-
RXD: RXD is the serial input port during all four seri- ing normal user operation, which configures
al port modes. TPRG210 as an output.
TXD: TXD is the serial output port during all four TPPC: The Test Programmable Connector Control
serial port modes. signal control both PRGUCS companion cells. When
the PRGUCS companion cell is configured an out-
SCLK: The Serial Port Shift Clock is equivalent to put, TPPC is the multiplexer ·select signal that en-
the Mode 0 TXD output on the the 80C51. SClK is ables either the TPRGxlO signal or the user output
fixed at one-sixth of the input clock (ClK or TIClK). signal (UOS). TPPC is a logic 1 during the test mode,
Output only during Serial Mode O. which selects the test programmable pin outputs
(TPRGx10). TPPC remains low during normal user
MOD ED: Mode 0 Control is an active-high output operation, which selects the user-output signals
that is active during Serial Port Mode 0 operation. (UOS).
MODEO enables the designer to recombine Port 3
with RXD, TXD, and SClK to create an 80C51-type TADBC: The Test Address/Data Bus Control signal
Serial Mode O. controls the PRGPIN companion cell. When the
PRGPIN companion cell is configured as an output,
PWRDN: Power Down is an active-high output signal TADBC is the multiplexer select signal that enables
that indicates that the core is in power-down mode. either the ALE signal or the user-output signal
PWRDN goes active when bit 1 of the PCON regis- (UOS). TADBC is a logic 1 during test mode, which
ter is set. Internal RAM is preserved during the pow- selectS ALE.
er-down mode.
During normal user operation TADBC is low, which
CORETEST: Core Test is an active-high output that selects the user-output signal (UOS).
signifies that the core is in test mode and is driving
data onto the EADB bus. When active, all user logic TPRG110: Test Programmable Pin 1 Input/Output
must three-state the EADB bus. signal functions as the 10 path during test mode. It is
used in conjunction with the PRGUCS companion
TADBOE: The Test Address/Data Bus Output En- cell. MANDATORY PACKAGE PIN.
able Control controls the direction of the PADB com-
panion cells that bring the EADB bus off-chip. A low TPRG210: Test Programmable Pin 2 Input/Output
level on TADBOE three-states the PADB cells. signal functions as the 10 path during test mode. It is
When user-logic connects to the EADB bus, com- used in conjunction with the PRGUCS companion
bine TADBOE with the user-logic direction-control cell. MANDATORY PACKAGE PIN.
signal to control the PADB companion cells.
SPH2:. SFR Phase 2 Clock is a UCS51 Phase 2
TITEST: The Test Mode Enable input enables the clock output. It is not active during Idle mode.
UCS51 core test mode during a reset (ERST or Re-
set high). TITEST is multiplexed with ALE during test SPH2S: SFR Phase 2 Sleep Clock is a UCS51
mode. MANDATORY PACKAGE PIN. Phase 2 clock output. It remains active during Idle
mode ..
TOPP1TO: Test Programmable Pin 1 Output Enable
controls the direction of the TPP1 PRGUCS com-
panion cell during test mode. TOPPHO is low dur-
ing normal user operation, which configures the
TPRGIO pin as an output.
8-213
inter UCS51
UCS51 DESCRIPTION ing 105 user-available signals. Intel has ensured
compatibility with the .cell library while maintaining
code and functional compatibility .with the standard
Many UCS Core Celis to Choose From product, but also allowing code optimization. Design-
ers can take advantage of the UCS51's de multi-
The UCS51 is a modified Cell version of Intel's indus- plexed 110 ports to optimize their application code.
try standard 80C51 Microcontroller. When used in
conjunction with the Intel 1.5 Micron CHMOS III Cell
Library, the UCS51 core enables a designer to im- Special Function Register Bus
plement a semi-custom integrated circuit that in- Provides Direct Access to Peripherals
cludes an 80C51 core, various peripherals that inter-
face to the core, and design-specific support logic. The most powerful feature of the UCS51· cell family
This allows the designer to explore application areas is the ability to directly interface to the internal bus of
previously reserved for custom design solutions. the cores. This bus is called the Special Function
Register (SFR) bus. The SFR bus is a synchronous
The UCS51 core cell is available with 0 to 32 Kbytes B-bit, multiplexed address/data bus which allows
of Read Only Memory (ROM) in 4K increments. The specially designed eXternal peripheral blocks to be
use of additional ROM expands the codespace ca- directly connected to the UCS51 core. In this man-
pability of the UCS51 core beyond the 4 Kbytes ner, the registers in these peripherals become
available with the 80C51 standard product, in most mapped to addresses in the core's special function
cases alleviating the need' for external program register address space. These SFR peripheral regis-
memory. The ROM less version of the UCS51 core ters are accessed by the UCS51 cores in the same
cell provides an 80C31-compatible core. manner as any internal special function register
(e.g., the liD ports, serial port, timers, etc.). The
In addition to configurable ROM selections, the SFR bus, however can only be used for on-chip pe-
UCS51 core is available with' either 128 or 256 Bytes ripheral blocks and not for peripherals which lie off-
of Random Access.Memory (RAM). chip.
TheUCS51 core contains three internal and two ex- A number of benefits. result from direct peripheral
ternal interrupt sources. The addition of the interrupt connection to the SFR bus. First, peripheral regis-
expansion unit increases the number of external in- ters residing in the SFR address space can take full
terrupts from two to seven. This allows for core con- advantage 01 the UCS51's rich set of direct address-
figurations of either 5 or 10 interrupt sources. ing and bit operations. Second, the user interface
logic required to connect a peripheral with a core is
greatly simplified if not completely eliminated. Final-
80C51 1/0 Demultiplexed ly, code effectiveness and the consequential per-
formance increase, ~s a result of being able to di-
In transforming the BOC51 into an ASIC core cell, the rectly address the SFR bus, make the UCS suitable
standard product's 110 drivers and pin multiplexers for applications that were not possible with the
were eliminated. As a result, all of the functional pins BOC51.
of the 80C51 are available to the UCS51 user, total-
B-214
UCS51
UCS51 PERIPHERAL CELLS UCS51SIO-SeriaII/O Interface Cell
Intel offers a family of. peripheral cells in the 1.5 mi- The UCS51SIO is a programmable, full-duplex serial
cron CHMOS III Cell Library. These cells are de- port with five operating modes. It is similar in func-
signed for the efficient interfacing to the UCS51 tion to the serial port on the UC551 core, with the
cores through the SFR bus. added capability of a fifth operating mode (Mode 4).
Cell Name Cell Description Because the UCS51510 is a full-duplex serial port it
can transmit and receive simultaneously. It is also
UCS51 BIU SFR Bus Interface Unit
re~~ive-buffered, which means that it can begin re-
UCS51 AD 8-Bit Analog-to-Digital Converter
ceiving a second byte before it reads the first byte.
UCS51T2 16-Bit Timer
UCS51SIOUART Serial Interface
UCS51 BRG Baud Rate Generator
UCS51 BRG-Baud-Rate Generator
The UCS51 Baud Rate Generator contains a 14-bit
~CS51BIU-Bus Interface Unit counter register and a 14-bit reload register. By pro-
gramming specific values· into the registers, design-
The UCS51 BIU is an 8-bit Bus Interface Unit with
ers can use the UCS51 BRG to generate the baud-
e!ght in~uts and eight outputs. It is designed to pro-
rate clock for the UCS51SIO peripheral cell. When
~Ide an Inte~ace between on-chip, user-defined pe-
used in conjunction with the UCS51SIO, the
ripheral logic and the UCS51 core. Built-in hand-
UCS51 BRG supports baud rates of 50 Hz to
shaking circuitry aids in the transfer of data between
the UCS51 core and a user-defined peripheral. 19.2 KHz.
A secondary application for the UCS51 BRG is as a
general-purpose programmable clock divider that is
UCS51AD-Analog-to-Digital capable of generating clocks ranging from 244 Hz to
Converter Cell 4 MHz when using a 16 MHz system clock.
The UCS51AD is an 8-bit, successive approximation
(Note that designers may also create their own pe-
type Analog-to-Digital Converter. It features eight
ripheral macro-cells using the 551 and MSI Cells in
user-selectable analog input channels, internal sam-
the 1.5 micron library.) .
ple and hold, and user-selectable conversion speed
control.
Extended Temperature Operation
UCS51T2-Timer 2 Cell· The Intel cell library supports three temperature
ranges: commercial, industrial, and military. Intel
The UCS51T2 is a 16-bit timer or up/down counter
guarantees the specified cell performance as long
that is a functional super-set of the Timer 2 peripher-
as the supply voltage and case temperature of the
al found in the 8052 standard product. The
ASIC device remain within the ranges in Table 1.
UCS51T2 peripheral can function as either a timer or
an event counter, and it supports three operating
modes: capture, auto-reload and baud-rate genera-
tor.
8-215
UCS51
UCS51 ASIC SUPPORT TOOLS Workstation Platform Support
The Intel ASIC design environment provides cus- Intel offers functional and timing simulation capabili-
tomers with a full range of ASIC design tools and ties on Mentor workstations. This allows the design-
utilities for efficient capture, simulation, code devel- er to complete an entire design or any of the
opment, emulation, and testing of a UCS51-based various design phases on an in-house engineering
design. workstation.
Design Entry Tool (DEn Test Vector Generation
The UCS51 DET simplifies the process of designing Intel tests vector for' core-based ASIC's using the
an ASIC device, and automates the complex con- same test programs used for its standard products.
nections often involved in capturing a core-based ASIC designers need only to develop test vectors for
design. DET allows the designer to specify the de- their unique logic. Intel provides the ExtASM51 as
sign from a menu interface, selecting port, timer in- an extension of Intel's ASM51 , providing the system
terrupt options and peripheral addresses, etc. The designer with the additional capability of generating
tool then establishes the appropriate connections vectors for a simulator and production tester. .
between the core, peripherals, and power and
ground buses. The designer finally connects the re-
maining system logic and I/O pads with a schematic Emulation Capability
editor.
The ICE-UCS51 emulator kit allows software devel-
opment and system prototyping to occur in parallel
Mainframe Design Verification System with ASIC design. It is a complete development and
(MDVS) . debug system which allows the system designer to
develop and test code for a UCS51-based ASIC
MDVS provides users with an integrated gate-level product and to emUlate ASIC product in the target
simulation environment using Intel's reference simu- system.
lator. MDVS is based on a VAXTM mainframe com-
puter utilizing a Zycad™ hardware accelerator, and (For more details of the ASIC design tools see the
offers full timing simulation checks including toggle "ASIC Embedded Controller Handbook".) .
and spike detection and reporting. MDVS is an ex-
tension of the workstation platforms and can be ac-
cessed from user sites and Intel Technology Cen-
ters.
liv:nI4ila:I",.It_jj(·)~I:I·I'tJ·.,-- ________
LOW COST CODE EVALUATION TOOL
Intel's EV80C51FB evaluation board provides a hardware environment for code
execution and software debugging at a relatively low cost. The board features the
80C51FB or 80C51FA, single chip, CHMOS*, 8-bit microcontrollers, the newest members
of the industry standard 8051 family. The board allows the user to take full advantage of
the power of the 8051. The EV80C51FB provides up to 16 MHz execution of a user's
code. Plus, its memory (ROMsim) can be reconfigured to match the user's planned
memory system, allowing for exact analysiS of code execution speeds in a particular
application.
Popular features such as a single line assembler / disassembler, single-step program
execution, and sixteen software breakpoints are standard on the EV80C51FB. Intel
provides a complete code development environment using assembly language (ASM-51)
as well as Intel's high-level language PL/M-51 to accelerate development schedules.
The evaluation board is hosted on an IBM PC** or BIOS-compatible clone, already a
standard development solution in most of today's engineering environments. The source
code for the on-board monitor (written in ASM-51) is public domain. The program is
about 3K bytes and can be easily modified to be included in the user's target hardware.
In this way, the provided PC host software can be used throughout the development
phase.
EV80C51FB FEATURES
• Up to 16 MHz .Execution Speed • Sixteen Software Breakpoints
• 16K Bytes of ROMsim • Program Step Mode
• Flexible Chip-Select Controller • High-Level Language Support
• Totally CMOS, low power board • Single Line Assembler/Disassembler
• Concurrent Interrogation of Memory • RS-232-C Communication Link
and Registers
FULL SPEED EXECUTION
The EV80C51FB executes the user's code from on-board ROMsim at up to 16 MHz. By
changing crystals on the 80C51FB any slower execution speed can be evaluated. The
board's host interface timing is not affected by this crystal change.
16K BYTES OF ROMSIM
The board comes with 16K bytes of SRAM to be used as ROMsim for the user's code and
as data memory if needed. .
inter---------~
~CHMOS is a patented Intel process.
·"IBM pc, XT, AT and OOS arc registered trademarks of International Business Machines Corporation.
Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent
licenses aTe implied. Infannalion contained herein supersedes previously published specifications on these devices from Intel.
AUGUST 1988
© Intel Corporation 1988 Order number: 270618-0~n
8-217
la":nI&111;latA'l_j.(.)~I;I')'\JI. ____:--____
FLEXIBLEMEMORYDECODllVG
By changing the Programable Logic Device (PLD) on the board, the memory on the board
can be made to look like the memory system planned for the user's hardware application.
The PLD controls the chip-select inputs on the board with 64 byte boundaries of resolution
TOTALLY CMOS BOARD
The EV8OC51FB board is built totally with CMOS components. Its power consumption is
therefore very low, requiring 5 volts at only 225 rnA. If the on board LED's are disabled,
the current drops to only 80 rnA. The board also requires +/-12 volts at 10 rnA.
CONCURRENT INTERROGATION OF MEMORY AND REGISTERS
The monitor for the EV80C51FB allows the user to read and modify internal registers and
external memory while the user's code is running in the board.
SIXTEEN SOF1WARE BREAKPOINTS
There are sixteen breakpoints available which nutomatically substitute an LCALL
instruction for a user's instruction at the breakpoint location. The substitution occurs when
execution is started. If the code is halted or a brenkpoint is reached,the user's code is
restored into the ROMsim. -
PROGRAM STEP MODE
The stepping mode redirects the external interrupt () vector for use by the monitor. All other
interrupts are available to the user, and will function as normal. External interrupt 0 is
returned to the user after stepping.
HIGH LEVEL LANGUAGE SUPPORT
The host software for the EV80C51FB board is able to lond absolute object code generated
by ASM-51, PL/M-51 or RL-51 all of which are available from Intel.
SllVGLE LllVE ASSEMBLER/DISASSEMBLER
The host has a Single Line Assembler, and a Disassmbler, to simplify modification and·
, eX3minntion of code loaded on the board.
RS-232-C COMMUNICATION LllVK
Thl' EV80C51FB communicates with the host using an Intel 82510 UART provided on
board. This frees the on-chip UART of the 8OC51FB or 8OC51 FA for the user's application.
PERSONAL COMPUTER REQUIREMENTS
The EV8DC51FB Evaluation Board is hosted on an IBM PC", XT", AT"or BIOS
compatible clone. The PC must meet the following minimum requirements:
• 512K Bytes of Memory • A Serial Port (COM1 or COM2) at
• One 360K Byte floppy Disk Drive 9600 Baud
• PC DOS" 3.1 or Later • ASM-51 or PLlM-51 '
• A text editbrsuch as AEDrr
~
RS·232
BUFFERS BOC51fB CHIP
SELECT
LOGIC
CPU
P2
Txd· l
ADDRESS'I
Rxd
8Kx8 8Kx8
82510
DATA
RAM or
EPROM
RAM or
EPROM
UART
....
DIGITALVO I DIGITAL
1/0
CONTROL MEMORY MEMORY
I
"* Block Diagram of the EV80C51 FB Board
8-218
li'.I:UI"iIOlh".'j(.)~I:t·'+'tJl.,--________
LOW COST CODE EVALUATION TOOL
Intel's EV80C51FC evaluation board provides a hardware environment for code
execution and software debugging at a relatively low cost. The board features the
80C51FC, single chip, CHMOS*, 8-bit microcontrollers, the newest member of the
industry standard 8051 family. The board allows the user to take full advantage of the
power of the 8051. The EV80C51FC provides up to 16 MHz execution of a user's code.
Plus, its memory (ROMsim) can be reconfigured to match the user's planned memory
system, allowing for exact analysis of code execution speeds in a particular application.
Popular features such as a single line assembler / disassembler, single-step program
execution, and sixteen softWare breakpoints are standard on the EV80C51FC. Intel
provides a complete code development environment using assembly language (ASM-51)
as well as Intel's high-level languages PL/M-51 to accelerate development schedules.
The evaluation board is hosted on an IBM PC** or BIOS-compatible clone, already a
standard development solution in most of today's engineering environments. The source
code for the on-board monitor (written in ASM-51) is public domain. The program is
about 3K bytes and can be easily modified to be included in the user's target hardware.
In this way, the provided PC host software can be used throughout the development
phase.
EVSOC51FC FEATURES
• Up to 16 MHz Execution Speed • Sixteen Software Breakpoints
• 32K Bytes of ROMsim • Program Step Mode
• Flexible Chip-Select Controller • High-Level Language Support
• Totally CMOS, Low Power Board • Single Line Assembler/Disassembler
• Concurrent Interrogation of Memory • RS-232-C Communication Link
and Registers • Evaluation Support for 8XC51FA, FB,
and FC Microcontrollers .
FULL SPEED EXECUTION
The EV80C51FC executes the user's code from on-board ROMsim at up to 16 MHz. By
changing crystals on the 80C51FC any slower execution speed can be evaluated. The
board's host interface timing is not affected by this crystal change.
32K BYrES OF ROMSIM
The board comes with 32K bytes of SRAM to be used as ROMsim for the user's code and
as data memory if needed.
intero-- - - - - - - -
*CHMOS is a patented Intel process.
uIBM PC, XT, AT and DOS aTe registered trademarks of International Business Machines Corporation.
Intel Corporation assumes no responsibility for the usc of any circuitl)' other than circuitry embodied in an Intel product. No other circuit patent
licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.
JANUARY 1990
@OIn!elCorporation1988 Order number: 270802~OOl
8-219
liv:nI4iIOl"A'.mjj(.'~I:t·'dtJ ••_________
FLEXIBLE MEMORY DECODING
By changing the Programable Logic Device (PLD) on the board, the memory on the board
can be made to look like the memory system planned for the user's hardware application.
The PLD controls the chip-select inputs on the board with 64 byte boundaries of resolution.
TOTALLY CMOS BOARD
The EV80C51FC board is built totally with CMOS components. Its power consumption is
therefore very low, requiring 5 volts at only 225 rnA. If the on board LED's are disabled,
the current drops to only 80 rnA. The board also requires +/- 12 volts at 10 rnA.
CONCURRENT INTERROGATION OF MEMORY AND REGISTERS
The monitor for the EV80C51FC allows the user to read and modify internal registers and
external memory while the user's code is running in the board.
SIXTEEN SOFTWARE BREAKPOINTS
There are sixteen breakpoints available which automatically substitute an LCALL
instruction for a user's instruction at the brmkpoint location. The substitution occurs
when execution is started. If the code is hailed Dr a breakpoint is reached, the user's code
is restored in the ROMsim.
PROGRAM STEP MODE
The stepping mode redirects the external intl'rrupt 0 vector for use by the monitor. All
other interrupts are available to the user, and will function ,lS normal. External interrupt
ois returned to the user after stepping.
HIGH LEVEL LANGUAGE SUPPORT
The host software for the EV80C51FC board is able to load absolute object code generated
by ASM-51, PL/M-51 or RL-51 all of which are available from Intel.
SINGLE LINE ASSEMBLER/DISASSEMBLER
The host has a Single Line Assembler, and a Disassmbler, to simplify modification and
examination of code loaded on the board,
RS-232-C COMMUNICATION LINK
The EV80C51FC communicates with the host using an Intel 82510 UART provided on
board. This frees the on-chip UART of the 80C51FC; or for the user's application.
PERSONAL COMPUTER REQUIREMENTS
The EYSOC51FC Evaluation Board is hosted on an IBM PC**, XT**, AT** or BIOS
compatible clone. The PC must meet the following minimum requirements:
_ 512K Bytes of Memory _ A Serial Port (COM1 or COM2) at
_ One 360K Byte floppy Disk Drive 9600 Baud
_ PC DOS** 3.1 or Later _ ASM-51 or PL/M-51
_ A text editor such as AEDIT
~
RS-232
BUFFERS CHIP
SELECT
LOGIC
CPU
P2
Txd l
Rxd ADDRESS]
8KxB BKx8 82510
RAM or RAM or UART
OATA EPROM
EPROM
t-
DIGITAL ItO J DIGITAL
1/0
CONTROL MEMORY MEMORY
I -"If-
Block Diagram of the EV80C51 FC Board
8~220
8XF51FC Hardware 9
Description and Data Sheets
October 1990
8XF51FC
User's Manual
Order Number: 270904-001
9-1
8XF51FC User's Manual
CONTENTS PAGE CONTENTS PAGE
6.3 16-Bit Capture Mode .............. 9-33
1.0 INTRODUCTION ..................... 9-3
6.4 16-Bit Software Timer Mode ...... 9-33
2.0 MEMORY ORGANIZATION .......... 9-5 6.5 High Speed Output Mode ......... 9-34
2.1 Flash Memory Overview ........... 9-5 6.6 Watchdog Timer Mode ............ 9-34
2.2 Flash Memory Special Function 6.7 Pulse Width Modulator Mode ..... ,,9-35
Registers ........................... 9-6
,2.3 In-Circuit Flash Programming ....... 9-8 7.0 SERIAL INTERFACE ., ............. 9-36
2.4 In-Circuit Flash Erase .............. 9-8 7.1 Framing Error Detection .......... 9-37
2.5 Array Swapping ................... 9-12 7.2 Multiprocessor Communications .. 9-37
Out-of-Circuit Array Swapping ..... 9-12 7.3 Automatic Address Recognition ... 9-37
In-Circuit Array Swapping .......... 9-13 7.4 Baud Rates ....................... 9-39
2.6 On-Chip Voltatile RAM ............ 9-13 7.5 Using Timer 1 to Generate Baud
Rates .............................. 9-39
3.0 SPECIAL FUNCTION 7.6 Using Timer 2 to Generate Baud
REGiSTERS .......................... 9-13 Rates .............................. 9-39
4.0 PORT STRUCTURES AND 8.0 INTERRUPTS ....................... 9-41
OPERATION ........ ; ................ 9-16
8.1 External Interrupts ................ 9-42
4.1 I/O Configurations ................ 9-16
8.2 Timer Interrupts .................. 9-42
4.2 Writing to a Port .................. 9-17
8.3 PCA Interrupts .................... 942
4.3 Port Loading and Interfacing ...... 9-19
8.4 Serial Port Interrupts .............. 9-42
4.4 Read-Modify-Write Feature ....... 9-19
8.5 Write Complete Interrupt .......... 9-42
4.5 Accessing External Memory ...... 9-19
8.6 Interrupt Enable .................. 9-42
5.0 TIMERS/COUNTERS ............... 9-21 8.7 Priority Level Structure ............ 9-42
5.1 Timer 0 and Timer 1 .............. 9-21 How Interrupts are Handled ........ 9-45
Mode 0 .....................,...... 9-21 8.8 Response Time ................... 9-46
Mode 1 ........................... 9-22
9.0 RESET .............................. 9-46
Mode 2 ................ , .......... 9-22
9.1 Power-On Reset .................. 9-47
Mode 3 ................... '........ 9-23
5.2 Timer 2 ........................... 9-24 10.0 POWER-SAVING MODES OF
OPERATION ......................... 9-48
Capture Mode ..................... 9-25
10.1 Idle Mode ....................... 9-48
Auto-Reload Mode
(Up or Down Counter) ........... 9-26 10.2 Power Down Mode .............. 9-49
Baud Rate Generator Mode ....... 9-27 10.3 Power Off Flag .................. 9-49
Programmable Clock Out .......... 9-27 11.0 FLASH MEMORY PROTECTION
SCHEME ............................. 9-50
6.0 PROGRAMMABLE COUNTER
ARRAy ..... '" ....................... 9-27 12.0 ONCE MODE ...................... 9-51
6.1 PCA 16-Bit Timer/Counter ........ 9-29
13.0 ON-CHIP OSCILLATOR ........... 9-51
6.2 Capture/Compare Modules ....... 9-31
14.0 TIMING ............................ 9-53
9-2
inter 8XF51FC
1.0 INTRODUCTION • Four 8-Bit Bidirectional Ports
• Three l6-Bit Timer/Counters with One Up/Down
The 88FSIFC is a highly integrated 8-bit microcontrol- Counter
ler based on the MCS-Sl architecture. Its key feature is
32 Kbytes of nonvolatile, read/write Flash memory. • Programmable Counter Array with
The Flash memory is broken into two independently - Compare/Capture
erasable arrays of 4 Kbytes and 28 Kbytes. Also includ- Software Timer
ed are a programmable counter array (PCA), an en-
- High Speed Output
hanced serial port, an up/down counter/timer, and a
4-bit protection scheme for the on-chip memory. Since - Pulse Width Modulator
this product is CHMOS, it has two software selectable - Watchdog Timer
reduced power modes: Idle Mode and Power Down
Mode. As a member of the MCS-Sl family, the • Clock Out
88FSIFC is optimized for control applications. • Full-Duplex Programmable Serial Interface with
- Framing Error Detection
The 83FSIFC is an 88FSIFC on which one array of
- Automatic Address Recognition
memory is Flash and one array is factory-programmed
ROM. (See Section 2 for a description of the two arrays • Interrupt Structure with
of memory.) The user can request that the factory pro- - Eight Interrupt Sources
gram either array A (4 Kbytes) and its associated pro-
- Four Priority Levels
tection bits or array B (28 Kbytes) and its associated
protection bits. The memory will be configured by the • Reduced Power Modes
factory such that whichever array has been factory-pro- - Idle Mode
grammed will reside at address O.
- Power Down Mode
This document presents a comprehensive description of
The 8XF51 FC uses the standard 80S 1 instruction set
the on-chip hardware features of the 8XF51FC. It be-
and is pin-for-pin compatible with the existing MCS-Sl
gins with an extensive discussion of the Flash memory
"family of products.
and then discusses each of the peripherals as follows:
• 2S6 Bytes On-Chip Data RAM Figure 1 shows a functional block diagram of the
• Special Function Registers 8XFSIFC.
9-3
8XF51FC
PO.O-PO.7
-----------,
PSEN
AlE/PROG
IA/VPP
RST
P1.0 - P1.7 P3.0 - P3.7
270904-5
Figure 1. 8XF51FC Functional Block Diagram
9-4
8XF51FC
2.0 MEMORY ORGANIZATION Programming and erasing of the Flash memory can
take place either "in-circuit" (during code execution) or
All MCS-Sl devices have a separate address space for "out-of-circuit" (by applying signals to the pins, as with
Program and Data Memory. Up to 64 Kbytes each of a traditional EPROM programmer). Timings, control
external Program and Data Memory can be addressed. line levels and algorithms for out-of-circuit program-
In the case of the 88FSIFC the on-chip "Program" ming are given in the data sheet.
memory is 32 Kbytes of Flash memory which is read/
writable and thus can also act as "Data Memory". The memory is user-configurable. Either array A or
With the 83FSIFC, only onc of the two memory arrays array BO may reside at address O. Array Bl always
can be used as both program and data memory. Note occupies addresses 2000H to 7FFFH. Figure 2 shows
that the term "wrik" refers to both program and erase the possible configurations. With the 83FSIFC, the fac-
operations on the Flash memory. tory sets the memory configuration so that the factory-
programmed array occupies address O.
2.1 Flash Memory Overview The "swapable" array structure of the 88FSlFC allows
the user to erase either array while still maintaining
The 32 Kbytes of Flash memory on the 88FSI FC arc program control. Since either array can reside at ad-
broken into two arrays. Array A contains 4 Kbytes and dress 0, the user can design a system so that the array
array B contains 28 Kbytes. Array B is further broken which is being erased is always at address 1000h. This
into a 4 Kbyte array (BO) and a 24 Kbyte array (Bl). way, the initialization code and interrupt vectors will
The Flash memory is programmed and read by bytes always be available upon request.
and erased by blocks.
In addition to the 32 Kbytes of regular Flash memory,
On the 83FSIFC, one array is Flash memory and one there is another address space which contains Special
array is factory-programmed ROM. The user may se- Flash Bits. The Special Flash Bits include the four pro-
lect which array will be Flash. tection bits (RP A, RPB, WP A and WPB), the swap
bits (SWOA, SWIA) and the memory structure bit
(MS). These bits are discussed in detail in the protec-
tion and array swapping sections later in this docu-
ment.
-Addr. 7FFFh-
Array 81 Array 81
-Addr. 2000h -
Array 80 Array A
-Addr. 1000h-
Array A Array 80
-Addr. OOOOh-
NOTE:
When the 88F51 Fe is entirely erased, array 80 occupies address 0 as shown in the right-hand configuration above.
Figure 2. Possible Flash Memory Configurations
9-5
infef 8XF51FC
2.2 Flash Memory Special Function The FT register controls the length of the program and
erase pulses. This register allows the user to meet the
Registers pulse length (TWLWHp and the TWLWHE) specifica-
In-circuit accesses to the Flash memory are controlled tions given in the data sheet and still operate the part in
by two new Special Function Registers: FCON (Flash a wide range of frequencies. Use the following formula
CONtrol) and FT (Flash Timing). These registers are to determine the pulse lengths from the values in FT:
shown in Tables 1 and 2. Program Pulse Duration = (2 x Crystal period) x
. (4S)x(ft+l)
The FCON register controls the selection of memory Erase Pulse Duration = 1024 x program pulse
array (either array A or array B) and address space duration
(regular Flash memory or Special Flash Bit space). It is
also used to enable and flag the new Write Complete where: s = binary value of FT.5-FT.4
interrupt. FCON.5 is used to determine the current ft = binary value of Fr.3-FT.O.
memory configuration. The lowest three bits of FCON
are used to select one of the five different Flash opera-
tions shown in Table 3.
Table 1. FCON: Flash Control Register
FCON Address = OCEH Reset Value = OOXO 00008
Not Bit Addressable
WIE WC ICNFG I AS AR HV WRIVER IPGM/ERS I
Bit ? 6 5 4 3 2 a
Symbol Function
WIE Write Complete Interrupt Enable bit. The WIE bit, the EWC bit (IEA.6-see Interrupts
section), and the EA bit (IE.?) must all be set to enable the Write Complete interrupt.
WC Write Complete bit. Set by hardware when write operation is complete. Flags an
interrupt if one has been enabled. Cleared by hardware when the part vectors to the
interrupt.
CNFG Flash configuration bit. When read it returns a "1" if array A resides at address 0 and
a "a" if array B is at zero. Writing to this bit has no effect.
AS Address Space bit. If zero, subsequent flash accesses are to regular flash memory. If
one, flash accesses are to Special Flash bit space.
AR Address Range bit. Selects the memory array that MOVX instructions operate on. If
zero, subsequent flash operations access array A. If one, flash accesses are to array
8.
HV High Voltage bit. Must be set before flash operations which require the VPPH voltage
level (program/erase/verify). Should be cleared otherwise.
WRIVER WritelVerify bit. Must be set before program and erase operations. Is automatically
cleared after a program or erase operation to p~epare for a verify operation.
PGM/ERS Program/Erase bit. One during program and program verify operations. Zero during
erase and erase verify operations.
9-6
infef 8XF51FC
Table 2. FT: Flash Timing Register
FT Address = OCFH Reset Value = XOOO OOOOB
Not Bit Addressable
I SWPP I S1 so FT3 FT2 FT1 FTO
Bit 7 6 5 4 3 2 o
Symbol Function
Not implemented, resorved for future use.'
SWPP SWaP Preparation bit. This bit is set as part of the array swapping algorithm. Once
this bit is set, a NOP instruction causes the arrays to be swapped to the configuration
determined by the SWOA and SW1 A bits (in Special Flash Bit space).
S1, SO The binary value of these bits is used to calculate the program and erase pulse
durations using the equation given below. S1 is the MSB; SO is the LSB.
FT3, FT2, The binary value of these bits is used to calculate the program and erase pulse
FT1, FTO durations using the equation given below. FT3 is the MSB; FTO is the LSB.
Program Pulse Duration = (2 x Crystal period) x (4 5 ) x (ft + 1)
Erase Pulse Duration = 1024 x program pulse duration
where: s = binary value of FT.5-FT.4
ft = binary value of FT3.-FT.0.
NOTE:
'User software should not write 1s to reserved bits. These bits may be used in future 8051 family
products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and
its active value will be 1. The value read from a reserved bit is indeterminate.
Table 3. Flash Operations
Operation HV, WRIVER, PGMlERS
code fetch 0,0,0
program 1, 1, 1
erase 1, 1,0
prog. verify 1,0, 1
erase verify 1,0,0
9-7
inter 8XF51FC
2.3 In-Circuit Flash Programming should be applied before considering a byte "un-pro-
grammablc". The expected number 'of program/erase
Programming a byte of flash memory involves three cycles is also given in the data sheet.
main steps: setup, program, and verification. The mech-
anism for doing the actual programming is a "MOVX The 8XF51FC cannot program into the same memory
@DPTR, A" instruction where the data pointer con- array from which it is executing. A hardware reset will
tains the destination address and the accumulator holds result if this is attempted. Also, the 8XF51FC will reset
the data to be programmed. itself if a program operation is st arted while a previous
write operation is still in progress.
The setup stage of a program operation starts with ini-
tialization of the FT register to correctly define the
length of the write pulses. If the Write Complete inter- 2.4 In-Circuit Flash Erase
rupt is to be used it must be enabled by setting the WIE
(FCON.7), IEA.6 and EA bits. This stage might also The In-Circuit Erase algorithm is similar to the In-Cir-
include code til determine the memory configuration cuit Program process described ahovc with a few im-
and set the Address Range (FCON.3) bit appropriately. portant differences. First, while the 8FX51FC is pro-
An example of initialization code is given in Listing 1. grammed a byte at a time, it is erased a block at a time.
The EA/Vpp pin can either be tied to the VpPH voltage Either array A or array B (and the Protection/Swap
level throughout device operation or can be raised to hits associated with them) is erased with one operation.
the VpPH voltage level just before programming begins.
Secondly, every byte in an array must be programmed
The program stage begins by settin~e HV (FCON.2), to 00 hefore that array is erascd. This includes the pro-
WR/vER (FCON.l) and PGM/ERS (FCON.O) bits. tection bits and swap bits (array A only). Ifa byte is not
Once these bits are set, a MOVX instruction accesses programmcd hefore crasure it may be "over-erased"
FlasI.!....!!Iemory and begins the programming process. which could prevent future programming of that mem-
The EA/Vpp pin should be raised to the VPPH voltage ory location.
level before thc MOVX instruction is executed. Pro-
gramming act ually starts one instruction after the The code in Listing 1 initializes the 8XF51FC so that it
MOVX instruction. The example in Listing 2 shows the is set up for a write operation on the array that occupies
8XF51FC entering idle mode while waiting for the address lOOOh. It is recommended that the user only
Write Complcte interrupt. perform erase operations while executing from the ar-
ray which occupies address O. This way, program con-
Following a program operation, the WR/VER bit is trol can be maintained in case of an inadvertant reset.
automatically cleared by hardware so that the part is
setup for a verification operation. EACH BYTE MUST Listing 3 contains code to erase and verify the array at
BE VERIFIED AFTER IT IS PROGRAMMED TO address lOOOh. The, EA/Vpp pin must be at the VpPH
DETERMINE IF ANOTHER PROGRAM PULSE voltage level during both erase and verify. As with a
IS NEEDED. Use MOVC instructions to perform the program operation, the HV, WR/vER and PGM/ERS
verification. bits are set to appropriate values and followed by a
MOVX instruction. The destination operand of the
Note that the EA/Vpp pin must still be at the VpPH MOVX instruction may be any memory location within
voltage level during verification. If EA/VPP is at Vee the array which is being erased.
during this operation, the byte is not truly verified, it is
just read. What is the difference? A positive verification Once the erase operation is complete, hardware sets the
assures the user that a byte will remain programmed WC bit (FCON.6) bit and clears the WR/VER
despite the stresses caused by subseHuent programming (FCON.l) bit in preparation for a verification opera-
of other memory locations. A read operation and a ver- tion. Every byte in the array must verify as OFFh if an
ify operation could return different values for the same erase operation is to be considered successful. If an
"half-programmed" memory location. Do not consider erase was not successful, apply another write pulse by
a byte successfully programmed until a verify operation resetting the WR/VER bit and performing another
returns the value to which it was programmed. After a MOVX. The data sheet gives the maximum number of
memory location has been successfully programmed, erase pulses which should be applied before an erase
read operations (with the EA/vpp at Vee) should be operation is considered a failure.
used to determine the location's contents.
The 8XF51FC cannot erase the same memory array
If programming was not successful, apply another pro- from which it is executing. A hardware reset will result
gram pulse by resetting the WR/VER bit and perform- if this is attempted. Also, the 8XF51 FC will reset itself
ing another MOVX instruction. The data sheet if an erase operation is started while a previous write
operation is still in progress.
9-8
inter 8XF51FC
;**** Interrupt Service Routine for the Write Complete Interrupt ***
; This routine is used to "wake up" the part from idle mode.
;*******************************************************************
ORG 073h
ANL FCON, #OBFh ; clear WC bit
RETI
i***** INIT ROUTINE*************************************************
This routine is used to setup the 88F51FC for a write operation.
This routine:
-Puts correct value into timing register
-Enables flash interrupt
-Sets AR bit. in FCON depending on memory configuration
, Registers used: ACC
i***************************************************** **************
init:
MOV FT, #OlEH correct value for 16MHz is 24h
For 12MHz, use FT=lEH
SETB EA enable interrupt in general
ORL lEA, #040H enable Write Complete interrupt
ORL FCON, #WIE set Write Interrupt Enable bit in FCON
MOV A, FCON
ANL A, #020H zero everything but the CNFG bit
JZ B At Zero
ORL FCON, #00001000B set AR bit since we are operating
RET from array A and want to access array B
B At Zero:
-ANL FCON, #11110111B clear AR bit since we are operating
RET from array B and will access array A
270904-1
NOTE:
This code is designed to reside in the lowest 4 Kbytes of Flash memory.
Listing 1. Initialization Code for Flash Operations
9-9
inter 8XF51FC
;***** Prog Routine**********************************************
-Programs the data in the acc~mulator into the address in
the data pointer.
-This code assumes we are accessing regular (not Special Flash
Bit) memory
Registers used: ACC, RO, Rl
Return value: The bit "Write error" is set if the location
; is not successfully programmed
i***************************************************** ***********
Prog:
MOV RO, #MaxProg MaxProg is equal to the maximum number
of programming pulses given in the
daLi! sheet. RO is used to count the
number of programming pulses.
ANL FCON, #111011llB clf'or liS bit for regular memory space
prog loop:
-ORL FCON, #07H sc't !lV, I'IR/RDII & PGM/ERS# in FCON
MOVX @DPTR, II pcrfo~m write -- the dota pointer
cOIlLul.llC' Lhe destination address
while the accumlotor contains the
data to be programmed.
MOV PCON, #1 enter idle mode and wait for WC into
MOV Rl, A store the data we just programmed •
MOV A, #0
Move A, @A+DPTR verify write
XRL A, Rl destination=source?
JZ prog_good
DJN~ RO, prog_loop try no more than the maximum number
of program pulses given in the data sheet
SETB Write error program was unsucessful after maximum pulses
IINL FCON, #OF8H ; clear BV, WR/VER# & PGM/ERS# in FCON
RET
prog good:
-CLR Write error program operation successful
ANL FCON,-#OF8h clear BV, WR/VER# & PGM/ERS#
RET
270904-2
Listing 2. Flash Programming Code
9-10
8XF51FC
;**** Erase Routine
-Erases whichever array begins at address 1000h
-verifies that the erase was successful
Registers Used: RO,R1, B, Acc
Return Value: Sets the bit "write error" if erasure
; was unsuccessful
;*****
MOV RO, to RO and R1 will be used to count the number
MOV R1, to of erase pulses applied
MOV DPTR, j/lOOOh We'll be erasing the array which starts
at address 1000h
MOV A, FCON determine current memory config
so we know how many bytes to
"pre-program" and verify
ANL A, #020h clear all but the CNFG bit
JZ Erasing A
MOV B,' #080h put upper byte of ending addr into B
JMP Erase
Erasing A:
MOV B, j/lOh put upper byte of ending addr into B
Erase:
ORL FCON, #00000110B set HV and WR/RD# bits
ANL FCON, #11111110B clearPGM/ERS# bits
MOV A, tOFFh
MOVX @DPTR, A DPTR contains either 1000h (if this is
the first erase pulse) or the address
of the first non-erased memory location.
This way, we can begin our verification
at the first non-erased location and
don't have to re-verify the whole array
with every pulse.
MOV PCON,f01 enter idle -- WC interrupt wakes the part up
verify loop:
CLR A A=OO
MOVC A, @A+DPTR do all bytes OFF?
CPL A
JNZ erase error
INC. DPTR
MOV A, DPH
CJNE A, B, verify_loop have we reached the last address?
CLR indicate success
RET
270904-3
NOTE:
This code is designed to reside in the lowest 4 Kbytes of Flash memory.
listing 3. Flash Erase Code
9-11
intJ 8XF51FC
erase error:
INC RO increment the pulse count stored
CJNE RD, iO, no_inc_Rl in RO (low byte) and Rl (high byte)
INC Rl
no inc Rl:
- CJNE Rl, iMaxEraseHi, Erase ;MaxEraselli is equal to the
high byte of the maximum number
of erase pulses given in the
data sheet. If· we haven't reached
the limiting value, we apply another
erase pulse.
SETB Write_error Since we reached the pulse limit without
a successful verify, we quit and signal
a write error. The main program should
handle such errors.
RET
270904-4
Listing 3. flash Erase Code (Continued)
2.5 Array Swapping A special Memory Structure bit is provided to facilitate
out·or-circuit swapping. This bit is located in Special
The memory of the 88F51 Fe can he arranged in either Flash Bit space at address IOh. Read operations on this
of the two configurations shown in Figure 2. Two bits bit ret urn a "a" if array A occupies address a and a "I"
located in Special Flash hit space determine the struc· if array B occupies address o. Since the swap bit ad-
ture of the memory. These hits are the SWOA and dresses change as soon as the arrays are swapped, the
SWIA bits. They arc associated with array A which user must read this bit to determine what memory loca-
implies that they arc erased whenever array A is erased tion to verify. An out-of-circuit swap algorithm in-
and that they must be programmed either out·of·circuit volves these steps:
or when operating from array B or external memory. 1. Determine present memory configuration by r!!ading
the Memory Structure Bit.
Table 4 shows how the values of SWOA and SWIA
correspond to the different memory configurations. 2. Decide which swap bit needs to be programmed
Note that when the 88F51FC is entirely erased, array based on the memory configuration. If array BO is
BO occupies address O. currently at address 0, the SWOA bit needs to be
programmed. Otherwise the SWIA bit needs to be
programmed. (Note that if both bits are already pro-
OUT-Of-CIRCUIT ARRAY SWAPPING grammed, array A must be erased before further
swapping).
As with programming and erasing, array swapping can
3. Apply a programming pulse with the control lines at
be accomplished either from the pins (out-of-circuit) or
the levels given in the data' sheet.
during execution (in-circuit). The data sheet gives the
control line levels and timings for out-of-cireuit pro- 4. Read the Memory Structure Bit to determine if the
gramming of the swap bits. With the out-of-circuit arrays have been swapped.
method, the arrays are swapped as soon as the swap bit 5. If the. aFays have been swapped, verify the swap bit
is successfully programmed. programming at its new address. Otherwise go back
to step 3.
9-12
inter 8XF51FC
IN-CIRCUIT ARRAY SWAPPING When an instruction accesses an internal location above
address 7FH, the CPU knows whether the access is to
In-circuit array swapping does not occur immediately the upper 128 bytes of data RAM or to SFR space by
after successful programming of the swap bits. Instead, the addressing mode used in the instruction. Instruc-
two additional steps are added to allow the user to tions that use the direct addressing access SFR space.
know precisely when swapping will occur. This way, For example,
the user can maintain code control during a swap. This
is the process for in-circuit array swapping: MOV OAOH, # data
1. Determine the current memory configuration by
reading the CNFG bit (FCON.5). Read operations access the SFR at location OAOH (which is P2). In-
on this bit return a "0" if array B resides at address 0 structions that use indirect addressing access the upper
and a "1" if array A occupies address O. 128 bytes of data RAM. For example,
2. Decide which swap bit will be programmed based Oil MOVB @RO, # data
the memory configuration. If array BO is currently at
address 0, the SWOA bit needs to be programmed. where RO contains OAOH, accesses the data byte at ad-
Otherwise, the SWIA bit needs to be programmed. dress OAOH, rather than P2 (whose address is OAOH).
(Note that if both bits are already programmed, ar- Note that stack operations are examples of indirect ad-
ray A must be erased before further swapping.) dressing, so the upper 128 bytes of data RAM are avail-
3. Program the appropriate swap bit using the in-circuit able as stack space.
programming algorithm. For swap bit programming,
the AS bit (FCON.4) must be set so that Special
Flash Bit space is accessed instead of regular Flash 3.0 SPECIAL FUNCTION REGISTERS
memory.
4. Set the SWPP (SWaP Preparation) bit at FT.6. A map of the on-chip memory area called the SFR
(Special Function Register) space is shown in Table 5.
5. Execute a NOP instruction.
Note that not all of the addresses are occupied. Unoc-
Following the NOP instruction, the program counter cupied addresses are not implemented on the chip.
will be incremented normally. However, it now points Read accesses to these addresses will in general return
into a diferent array of memory. To illustrate, suppose random data, and write accesses will have no effect.
the NOP instruction that will accomplish the swap is
located at address 100h in array B. After execution of User software should not write Is to these unimple-
the NOP, the next instruction executed will be from mented locations, since they may be used in future
address 1Olh-which is now in array A. MCS-51 products to invoke new features. In that case
the reset or inactive values of the new bits will always
It is recommended that vital start-up code and inter- be 0, and their active values will be 1.
rupt vectors be copied into both memory arrays so that
control can be maintained in case a reset occurs after a The functions of the SFRs are outlined below. More
swap. information on the usc of specific SFRs for each periph-
eral is included ill the description of that peripheral.
2.6 On-Chip Volatile RAM Accumulator ACC is the Accumulator register. The
mnemonics for Accumulator-Specific instructions,
In addition to .the 32 Kbytes of Flash memory, the however, refer to the Accumulator simply as A.
8XF51FC implements 256 bytes of on-chip data RAM.
The upper 128 bytes occupy a parallel address space to
the Special Function Registers. That means they have
the same addresses, but they are physically separate
from SFR space.
Table 4. Swap Bit Values and Addresses
Array A Array BO SW1A SWOA
SW1A , SWOA
Location Location Address Address
0 , 0 10QOh OOh 1031h 1030h
0 , 1 1000h OOh 1031h 1030h
1 , 0 OOh 1000h 31h 30h
1 1 1000h OOh 1031h 1030h
9-13
8XF51FC
Table 5. SFR Mapping and Reset Values
F8 CH CCAPOH CCAP1H CCAP2H CCAP3H CCAP4H FF
00000000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
FO *S F7
00000000
E8 CL CCAPOL CCAP1L CCAP2L CCAP3L CCAP4L EF
00000000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EO 'ACC E7
00000000
D8 CCON CMOD CCAPMO CCAPM1 CCAPM2 CCAPM3 CCAPM4 OF
OOXOOOOO OOXXXOOO XOOOOOOO XOOOOOOO XOOOOOOO XOOOOOOo XOOOOOOO
00 • P$W 07
00000000
C8 T2CON T2MOD RCAP2L RCAP2H TL2 TH2 FCON FT CF
00000000 XXXXXXXO 00000000 00000000 00000000 00000000 OOXOOOOO XOOOOOOO
co C7
S8 • IP SADEN SF
XOOOOOOO 00000000
so , P3 IPAH IPA IPH S7
11111111 00000000 00000000 XOOOOOOO
A8 , IE SADDR - AF
00000000 00000000
AO • P2 lEA A7
11111111 00000000
98 • SCON • SSUF 9F
00000000 XXXXXXXX
90 , P1 97
11111111
88 • TCON 'TMOD • TLO • TL 1 * THO • TH1 8F
00000000 00000000 00000000 00000000 00000000 00000000
80 , PO • SP * DPL • DPH 'PCON ** 87
11111111 00000111 00000000 00000000 OOXXOOOO
.. . .
• = Found In the 8051 core (See 8051 Hardware Description for explanations of these SFRs).
•• = See description of PCON SFR. Bit PCON.4 is not affected by reset.
X = Undefined.
9·14
8XF51FC
Table 6. PSW: Program Statue Word Register
PSW Address = ODOH Reset Value = 0000 OOOOB
Bit Addressable
CY AC FO RS1 RSO OV P
Bit 7 6 5 4 3 2 o
Symbol Function
CY Carry flag.
AC Auxiliary Carry flag. (For BCD Operations)
FO Flag O. (Available to the user for general purposes).
RS1 Register bank select bit 1.
RSO Register bank select bit o.
RS1 RSO Working Register Bank and Address
o o Bank 0 (00H-07H)
o 1 Bank 1 (OBH-OFH)
1 o Bank 2 (1 OH -17H)
1 1 Bank 3 (1BH-1 FH)
OV Overflow flag.
User definable flag.
P Parity flag. Set/cleared by hardware each instruction cycle to indicate an odd/even
number of "one" bits in the Accumulator, i.e., even parity:
B Register: The B register is used during multiply and Programmable Counter Array (PCA) Registers: The
divide operations. For other instructions it can be treat- 16-bit PCA timer/counter consists of registers CH and
ed as another scratch pad register. CL. Registers CCON and CMOD contain the control
and status bits for the PCA. The CCAPMn (n = 0, I,
Stack Pointer: The Stack Pointer Register is 8 bits 2, 3, or 4) registers control the mode for each of the five
wide. It is incremented before data is stored during PCA modules. The register pairs (CCAPnH, CCAPnL)
PUSH and CALL executions. The stack may reside are the 16-bit compare/capture registers for each PCA
anywhere in on-chip RAM. On reset, the Stack Pointer module.
is initialized to 07H causing the stack to begin at loca-
tion 08H. Serial Port Registers: The Serial Data Buffer, SBUF, is
actually two separate registers: a transmit buffer and a
Data Pointer: The Data Pointer (DPTR) consists of a receive buffer register. When data is moved to SBUF, it
high byte (DPH) and a low byte (DPL). Its intended goes to the transmit butTer where it is held for serial
function is to hold a 16-bit address, but it may be ma- transmission. (Moving a byte to SBUF initiates the
nipulated as a 16-bit register or as two independent transmission). When data is moved from SBUF, it
8-bit registers. comes from the receive buffer. Register SCON contains
the control and status bits for the Serial Port. Registers
Program Status Word: The PSW register contains pro-
SADDR and SADEN are used to define the Given and
gram status information as detailed in Table 6.
the Broadcast addresses for the Automatic Address
Ports 0 to 3 Registers: PO, PI, P2, and P3 are the SFR Recognition feature.
latches of Port 0, Port I, Port 2, and Port 3 respective-
ly. Interrupt Registers: The individual interrupt enable
bits are in the IE and lEA registers. One of four priori-
Timer Registers: Register pairs (THO, TLO), (THI, ty levels can be selected for each of the 8 interrupts
TLl), and (TH2, TL2) are the 16-bit count registers for using the IP, IP A, IPH and IP AH registers.
Timer/Counters 0, I, and 2 respectively. Control and
status bits are contained in registers TCON and TMOD Power Control Register: PCON controls the Power Re-
for Timers 0 and 1 and in registers T2CON and duction Modes: Idle and Power Down.
T2MOD for Timer 2. The register pair (RCAP2H,
RCAP2L) are the capture/reload registers f9r Timer 2 Flash Memory Registers: The registers FCON and FT
in 16-bit capture mode or 16-bit auto-reload mode. control accesses to the Flash memory.
9-15
inter 8XF51FC
4.0 PORT STRUCTURES AND Table 7. Alternate Port Functions
OPERATION
All four ports in the 8XF51FC are bidirectional. Each Port Pin Alternate Function
consists of a latch (Special Function Registers PO PO.O/ADO- Multiplexed Byte of Address/Data for
through P3), an output driver, and an input buffer. PO. 7/AD7 External Memory
The output drivers of Ports 0 and 2, and the input buff· P1.0/T2 Timer 2 External Clock Input/Clock·
ers of Port 0, are used in accesses to external memory. Out
In this application, Port 0 outputs the low byte of the Pl.1/T2EX Timer 2 Reload/Capture/Direction
external memory address, time·multiplexed with the Control
byte being written or read. Port 2 out puts the high byte PI.2/ECI PCA External Clock Input
of the external memory address whcn the address is
16 bits wide. Otherwise the Port 2 pins continue to emit P1.3/CEX3 PCA Module 0 Capture Input, Com·
the P2 SFR content. pare/PWM Output
P 1.4/CEX4 PCA Module 1 Capture Input, Com·
All the Port I and Port 3 pins arc multifunctional. pare/PWM Output
They are not only port pins, but also serve the functions P 1.5/CEX5 PCA Module 2 Capture Input, Com·
of various special features as listed in Table 7. pare/PWM Output
The alternate functions can only bc act ivated if the cor· P 1.6/CEX6 PCA Module 3 Capture Input, Com·
responding bit latch in the port SFR contains a 1. Oth· pare/PWM Output
erwise the port pin is stuck at O. 1'1.7/CEX7 PCA Modulc 4 Capture Input,Com·
pare/I'WM Output .
4= 1 110 Configurations P2.0/A8- High Byte of Address for External
P2.7/A15 Memory
Figure 3 shows a functional diagram of a typical hit
latch and I/O buffer in each of the four ports. The bit P3.0/RXD Serial Port Input
latch (one bit in the port's SFR) is represented as a
P3.I/TXD Serial Port Output
Type D flip· flop. which clocks in a value from the in·
ternal bus in response to a "write to latch" signal from P3.2/INTO External Interrupt 0
the CPU. Thc Q output of the flip·flop is placed on the P3.3/INT External Interrupt I
internal bus in response to a "read latch" signal from
P3.4/TO Timer 0 External Clock Input
the CPU. The level of the port pin itself is placed on the
internal bus in response to a "read pin" signal from the P3.5/TI Timer I External Clock Input
CPU. Some instructions that read a port activate the P3.6/WR Write Strobe for External Memory
"read latch" signal, and others activate the "read pin"
P3.7/RD Read Strobe for External Memory
signal. See the Rcad·Modify·Write Feature section.
As shown in Figure 3, the output drivers of Ports 0 and
2 are switchable to an internal ADDRESS and AD·
DRESS/DATA bus by an internal CONTROL signal
for use in external memory accesses. During external
memory accesses, the P2 SFR remains unchanged, but
the PO SFR gets Is written to it.
9·16
infef 8XF51FC
A. Port 0 Bit B. Port 1 or Port 3 Bit
ADDR/DATA ALTERNATE
VCC OUTPUT
FUNCTION
WRITE
TO
LATCH WRITE
TO
LATCH
270004-6
ALTERNATE
INPUT
FUNCTION
270904-7
C. Port 2 Bit
ADDR
VCC
CONTROL
READ
LATCH
INT. BUS
WRITE
TO
LATCH
READ
PIN
270904-8
·See Figure 5 for details of the internal pullup
Figure 3. 8XF51FC Port Bit Latches and I/O Buffers
Also shown in Figure 3 is that if a PI or P3 latch When configured as inputs they pull high and will
contains a 1, then the output level is controlled by the source current (IlL in the data sheets) when externally
signal labeled "alternate output function." The actual pulled low. Port 0, on the other hand, is considered
pin level is always available to the pin's alternate input "true" bidirectional, because it floats when configured
function, if any. as an input.
Ports 1, 2, and 3 have internal pullups. Port 0 has open All the port latches have Is written to them by the reset
drain outputs. Each I/O line can be independently used function. If a 0 is subsequently written to a port latch, it
as an input or an output (Ports 0 and 2 may not be used can be reconfigured as an input by writing a I to it.
as general purpose I/O when being used as the AD-
DRESS/DATA BUS). To be used as an input, the port
bit latch must contain a I, which turns off the output 4.2 Writing to a Port
driver FET. On Ports I, 2, and 3, the pin is pulled high
by the internal pullup, but can be pulled low by an In the execution of an instruction that changes the
external source. value in a port latch, the new value arrives at the latch
during State 6 Phase 2 of the final cycle of the instruc-
Port 0 differs from the other ports in not having inter- tion. However, port latches are in fact sampled by their
nal pullups. The pullup FET in the PO output driver output buffers only during Phase 1 of any clock period.
(see Figure 3) is used only when the Port is emitting Is (During Phase 2 the output buffer holds the value it
during external memory accesses. Otherwise the pullup saw during the previous Phase I). Consequently, the
FET is off. Consequently PO lines that are being used as new value in the port latch won't actually appear at the
output port lines are open drain. Writing a I to the bit output pin until the next Phase I, which will be at SIPI
latch leaves both output FETs off, which floats the pin of the next machine cycle. Refer to Figure 4. For more
and allows it to be used as a high-impedance input. information on internal timings refer to the CPU Tim-
Because Ports 1 through 3 have fixed internal pull ups ing section.
they are sometimes call "quasi-bidirectional" ports.
. 9-17
intJ 8XF51FC
I~1P341 ~1P351 ~1P3'I ~1P3 I~1P321 ~1P331 ~1P341 ~1P351
STATE STATE STATE STATE 1 STATE STATE STATE STATE
XTAL1:,
INPUTS SAMPLED: -n 'Pl'P3'P3
RST
PO'Pl'P2,P3~
RST=:rl.-
MaV PORT, SRC: OLD DATA NEW DATA
SERIAL PORT
SHIFT CLOCK
(MaDE 0)
--l I-- RXD PIN SAMPLED RXD SAMPLED --l I--
270904-9
Figure 4. Port Operation
If the change requires a O-to-I transition in Ports I, 2, pFET I in is the transistor that is turned on for 2 oscil-
and 3, an additional pullup is turned on during SIPI lator periods after a O-to-\ transition in the port latch.
and S 11'2 of the cycle in which the transition occurs. A \ at the port pin turns on pFET3 (a weak pull-up),
This is done to increase the transition speed. The extra through the invertor. This invertor and pFET form a
pullup cali source about 100 times the current that the latch whieh hold the 1.
normal pullup can. The internal pullups are field-effect
transistors, not linear resistors. The pull-up arrange- If the pin is emitting a 1, a negative glitch on the pin
ments are shown in Figure 5. from some external source can tum off pFET3, causing
the pin to go into a float state. pFET2 is a very weak
The pullup consists of three pFETs. Note that an pullup which is on whenever the nFET is off, iri tradi-
n-channel FET (nFET) is turned on when a logical I is tional CMOS style. It's only about %0 the strength of
applied to its gate, and is turned off when a logical 0 is PFET3. Its function is to restore a I to the pin in the
applied to its gate. A p-channel FET (pFET) is the event the pin had a 1 and lost it to a glitch.
opposite: it is on when its gate sees a 0, and off when its
gate sees a 1.
Vcc Vcc Vcc
o
FROM PORT
LATCH
INPUTO_ _OC:;;:
DATA
READ
PORT PIN
270904:"10
CHMOS Configuration. pFET 1 is turned on for 2 osc. periods after-a makes a O-to-1 trarisition. During this time, pFET 1
also turns on pFET 3 through the inverter to form a latch which holds the 1. pFET 2 is also on.' Port 2 is similar except
that it holds the strong pullup on while emitting 1s that are address bits. (See text, "AcceSSing External Memory".)
Figure 5_ Ports 1 and 3 Internal Pullup Configurations
9-18
intJ 8XF51FC
4.3 Port Loading and Interfacing DJNZ (decrement and jump if not zero, e.g.,
DJNZ P3, LABEL)
The output buffers of Ports 1, 2, and 3 can each sink MOV,PX.Y,C (move carry bit to bit Y of Port X)
1.6 rnA at 0.45 V. These port pins can be driven by CLRPX.Y (clear bit Y of Port X)
open-collector and open-drain outputs although O-to-l SETBPX.Y (set bit Y of Port X)
transitions will not be fast since there is little current
pulling the pin up. An input 0 turns off pullup pFET3, It is not obvious that the last three instructions in this
leaving only the very weak pullup pFET2 to drive the· list are read-modify-write instructions, but they are.
transition. They read the port byte, all 8 bits, modify the addressed
bit, then write the new byte back to the latch.
In external bus mode, Port 0 output bufT~rs can each
sink 3.2 rnA at 0.45 V. However, as port pins they The reason that read-modify-write instructions are di-
require external pullups to be able to driv~ any inputs. rected to the latch rather than the pin is to avoid a
possible misinterpretation of the voltage level at the
See the latest revision of the data shed for d~sign-in pin. For example, a port bit might be used to drive the
information. base of a transistor. When a I is written to the bit, the
transistor is turned on. If the CPU then reads the same
port bit at the pin rather than the latch, it will read the
4.4 Read-Modify-Write Feature base voltage of the transistor and interpret it as a O.
Reading the latch rather than the pin will return the
Some instructions that read a port read the latch and correct value of 1.
others read the pin. Which ones do which? The instruc-
tions that read the latch rather than the pin are the ones
that read a value, possibly change it, and then rewrite it 4.5 Accessing External Memory
to the latch. These are called "read-modify-write" in-
structions. Listed below are the read-modify-write in- Accesses to external memory are of two types: accesses
structions. When the destination operand is a port, or a to external Program Memory and accesses to external
port bit, these instructions read the latch rather than Data Memory. Accesses to external Program Memory
the pin: use signal PSEN (program store enable) as the read
strobe. Accesses to external Data Memory use RD or
ANL (logical AND, e.g., ANL PI, A)
ORL (logical OR, e.g., ORL P2, A) WR (alternate functions of P3.7 and P3.6) to strobe the
(logical EX-OR, e.g., XRL P3, A) memory. Refer to Figures 6 through 8.
XRL
JBC Gump if bit = I and clear. bit, e.g.,
JBC Pl.l, LABEL) Fetches from external Program Memory always use a
CPL (complement bit, e.g., CPL P3.0) 16-bitaddress. Accesses to external Data Memory can
INC (increment, e.g., INC P2) use either a 16-bit addr~ss (MOVX @ DPTR) or an
(decrement, e.g., DEC P2) 8-bit address (MOYX @ Ri).
DEC
1STATE 11 STATE 21 STATE 31 STATE 41 STATE 51 STATE 61 STATE 11 STATE 21
~I~ ~I~ ~I~ ~I~ ~I~ ~I~ ~I~ ~I~
XTAL1:
ALE:
PSEN: ~
-.t
DATA
}.-SAMPLED
L
PO:
P2: PCH OUT PCH OUT PCH OUT
270904-11
Figure 6. External Program Memory Fetches
9-19
intJ 8XF51FC
I ~I~ ~I~
I
STATE 41 STATE 51 STATE 61 STATE 1 STATE 21 STATE 31 STATE 41 STATE 51
~I~ ~I~ ~I~ ~I~ ~I~ ~I~
XTAL1:
ALE:
RD:
PO:
PCH OR PCH OR
P2: DPH OR P2 SFR OUT
P2 SFR P2SFR
270904-12
Figure 7. External Data Memory Read Cycle
41 STATE 51 STATE 81 STATE 1 ISTATE. 21 STATE 31 STATE 41 STATE 51
ISTATE
~I~ ~I~ ~I~ ~I~ ~I~ ~I~ ~I~ ~I~
XTAL1:
ALE:
WR: PCl OUT IF
PO: DPL OR RI
OUT
DATA OUT
~---
~f ~
IS EXTERNAL
~
PCH OR PCH OR
DPH OR P2 SFA OUT
P2 SFR P2SFA
270904-13
Figure 8. External Data Memory Write Cycle
9-20
infef 8XF51FC
Whenever a 16-bit address is used, the high byte of the 5.0 TIMERS/COUNTERS
address comes out on Port 2, where it is held for the
duration of the read or write cycle. The Port 2 drivers The 8XF51FC has three 16-bit Timer/Counters: Timer
use the strong pullups during the entire time that they 0, Timer I, and Timer 2. Each consists of two 8-bit
are emitting address bits that are Is. This occurs when registers, THx and TLx, (x = 0, I, and 2). All three
the MOYX @ DPTR instruction is executed. During can be configured to operate either as timers or event
this time the Port 2 latch (the Special Function Regis- counters.
ter) does not have to contain is, and the contents of the
Port 2 SFR are not modified. If the external memory In the Timer function, the TLx register is incremented
cycle is not immediately followed by another external every machine cycle. Thus one can think of it as count-
memory cycle, the undisturbed contents of the Port 2 ing machine cycles. Since a machine cycle consists of 12
SFR will reappear in the next cycle. oscillator periods, the count rate is 1/12 of the oscilla-
tor frequency.
If an 8-bit address is being used (MOYX @ Ri), the
contents of the Port 2 SFR remain at the Port 2 pins In the Counter function, the register is incremented in
throughout the external memory cycle. In this case, response to a I-to-O transition at its corresponding ex-
Port 2 pins can be used to page the external data mem- ternal input pin-TO, TI, or T2. In this function, the
ory. external input is sampled during S5P2 of every machine
cycle. When the samples show a high in one cycle and a
In either case, the low byte of the address is time-multi- low in the next cycle, the count is incremented. The
plexed with the data byte on Port o. The ADDRESS/ new count value appears in the register during S3P I of
DATA signal drives both FETs in the Port 0 output the cycle following the one in which the transition was
buffers. Thus, in external bus mode the Port 0 pins are detected. Since it takes 2 machine cycles (24 oscillator
not open-drain outputs and do not require external periods) to recognize a L-to-O transition, the maximum
pullups. The ALE (Address Latch Enable) signal count rate is '/24 of the oscillator frequency. There are
should be used to capture the address byte into an ex- no restrictions on the duty cycle of the external input
ternal latch. The address byte is valid at the negative signal, but to ensure that a given level is sampled at
transition of ALE. Then, in a write cycle, the data byte least once before it changes, it should be held for at
to be written appears on Port 0 just before WR is acti- least one full machine cycle.
vated, and remains there until after WR is deactivated.
In a read cycle, the incoming byte is accepted at Port 0 In addition to the Timer or Counter selection, Timer 0
just before the read strobe (RD) is deactivated. and Timer I have four operating modes from which to
select: Modes 0 - 3. Timer 2 has three modes of opera-
During any access to external memory, the CPU writes tion: Capture, Auto-Reload, and Baud Rate Generator.
OFFH to the Port 0 latch (the Special Function Regis-
ter), thus obliterating the information in the Port 0
SFR. Also, a MOY PO instruction must not take place 5.1 Timer 0 and Timer 1
during external memory accesses. If the user writes to
Port 0 during an external memory fetch, the incoming The Timer or Counter function is selected by control
code byte is corrupted. Therefore, do not write to Port bits c/f in the Special Function Register TMOD (Ta-
o if external program memory is used. ble 8). These two Timer/Counters have four operating
modes, which arc selected by bit-pairs (MI, MO) in
External Program Memory is accessed under two con- TMOD. Modes 0, I, and 2 arc the same for both Tim-
ditions: er/Counters. Mode 3 operation is different for the two
1. Whenever signal EA is active, or timers.
2. Whenever the program counter (PC) contains an ad-
dress greater than 7FFFH (32k). MODE 0
When the CPU is executing out of external Program Either Timer 0 or Timer 1 in Mode 0 is an 8-bit Coun-
Memory, all 8 bits of Port 2 are dedicated to an output ter with a divide-by-32 prescaler. Figure 9 shows the
function and may not be used for general purpose I/O. Mode 0 operation for either timer.
During external program fetches they output the high
byte of the PC with the Port 2 drivers using the strong In this mode, the Timer register is configured as a
pullups to emit bits that are 1s. 13-bit register. As the count rolls over from all Is to all
Os, it sets the Timer interrupt flag TFx. The· counted
input is enabled to the Timer when TRx = I and either
GATE = 0 or INTx = 1. (Setting GATE = I allows
the Timer to be controlled by external input INTx, to
facilitate pulse width measurements). TRx and TFx are
9-21
intJ 8XF51FC
control bits in SFR TCON (Table 9). The GATE bit is MODE 2
in TMOD. There are two different GATE bits, one for
Timer I (TMOD.7) and one for Timer 0 (TMOD.3). Mode 2 configures the Timer register as an 8-bit Coun-
ter (TLx) with automatic reload, as shown in Figure II.
The 13-bit register consists of all 8 bits of THx and the Overflow from TLx not only sets TFx, but also reloads
lower 5 bits of TLx. The upper 3 bits of TLx are inde- TLx with the contents of THx, which is preset by soft-
terminate and should be ignored. Setting the run flag ware. The reload leaves THx unchanged.
(TRx) does not clear these registers.
MODE 1
Mode I is the same as Mode 0, except that the Timer
register uses all 16 bits. Refer to Figure 10. In this
mode, THx and TLx are cascaded; there is no prescal-
er.
Table 8. TMOD: Timer/Counter Mode Control Register
------------~----------------------,
TMOD Address = 89H Reset Value = 0000 00008
Not Bit Addressable
TIMER 1 TIMER 0
I GATE I CIT I M1 I MO GATE I CIT I M1 I MO I
Bit 7 6 5 4 3 2 o
Symbol Function
GATE Gating control when set. Timer/Counter Oar 1 is enabled only while INTO or INT1 pin
is high and TRO or TR1 control pin is set. When cleared, Timer 0 or 1 is enabled
whenever TRO or TR1 control bit is set.
CIT Timer or Counter Selector. Clear for Timer operation (input from internal system
clock). Set for Counter operation (input from TO or T1 input pin).
M1 MO Operating Mode
0 0 8-bit Timer/Counter. THx with TLx as 5-bit prescaler.
0 1 16-bit Timer/Counter. THx and TLx are cascaded; there is no prescaler.
1 0 8-bit auto-reload Timer/Counter. THx holds a value which is to be reloaded into TLx
each time it overflows.
(Timer 0) TLO is an 8-bit Timer/Counter controlled by the standard Timer 0 control
bits. THO is an 8-bit timer only controlled by Timer 1 control bits.
(Timer 1) Timer/Counter stopped.
INTERRUPT
CONTROL OVERFLOW
Tx PIN - - - - - - - - - '
TR'----~
x = Oor 1
270904-14
Figure 9. Timer/Counter 0 or 1 in Mode 0: 13-Bit Counter
9-22
8XF51FC
Table 9. TCON: Timer/Counter Control Register
TCON Address = BBH Reset Value = 0000 OOOOB
Bit Addressable
TF1 TR1 TFO TRO IE1 IT1 lEO ITO
Bit 7 6 5 4 3 2 o
Symbol Function
TF1 Timer 1 overflow Flag. Set by hardware on Timer/Counter overflow. Cleared by
hardware when processor vectors to interrupt routine.
TR1 Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter 1 on/off.
TFO Timer 0 overflow Flag. Set by hardware on Timer/Counter 0 overflow. Cleared by
hardware when processor vectors to interrupt routine.
TRO Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter 0 on/off.
IE1 Interrupt 1 flag. Set by hardware when external interrupt 1 edge is detected
(transmitted or level-activated). Cleared when interrupt processed only if transition-
activated.
IT1 Interrupt 1 Type control bit. Set/cleared by software to specify falling edge/low level
triggered external interrupt 1.
lEO Interrupt 0 flag. Set by hardware when external interrupt 0 edge is detected
(transmitted or level-activated). Cleared when interrupt processed only if transition-
activated.
ITO Interrupt 0 Type control bit. Set/cleared by software to specify falling edge/low level
triggered external interrupt O.
cif ~ 0
THx TLx INTERRUPT
TxP1N
_____--'1- Cif ~ 1
TRx----f
x ~ 00r1
GATE
INTX PIN
270904-15
Figure 10. Timer/Counter 0 or 1 in Mode 1: 16-Bit Counter
MODE 3 a timer function (counting machine cycles) and takes
over the use of TR 1 and TFI from Timer 1. Thus THO
Timer I in Mode 3 simply holds its count. The effect is now controls the Timer 1 interrupt.
the same as setting TRI = O.
Mode 3 is provided' for applications requiring an extra
Timer 0 in Mode 3 establishes TLO and THO as two 8-bit timer or counter. When Timer 0 is in Mode 3,
separate counters. The logic for Mode 3 on Timer 0 is Timer I can be turned on and off by switching it out of
shown in Figure 12. TLO uses the Timer 0 control bits: and into its own Mode 3, or can still be used by the
elf, GATE, TRO, INTO, and TFO. THO is locked into serial port as a baud rate generator, or in any applica-
tion not requiring an interrupt.
9-23
inter 8XF51FC
ciT = 0
INTERRUPT
______-'1 ciT" = 1
TxPIN -
TRx------I
GATE
iiiiTx PIN
270904-16
Figure 11. Timer/Counter 1 Mode 2: a-Bit Auto-Reload
osc ~B- 1/1210SC
1/12 IOSC - - - - - - - ,
. - - - INTERRUPT
TO PIN - - - - - - - '
CONTROL OVERFLOW
TRO-----t
1/12 lose -----------,\----1 I ·\. ._(_::_~_)_HL_T_Fl_. ~
_ _ _ _ _ _ _}.... CONTROL OVERFLOW
. INTERRUPT
TRI -
270904-17
Figure 12. Timer/Counter 0 Mode 3: Two a-Bit Counters
5.2 Timer 2 Table 10. Timer 2 Operating Modes
Timer 2 is a 16-bit Timer/Counter which can operate RCLK + TCLK CP/RL2 T2*OE TR2 Mode
either as a timer or as an event counter. This is selected 0 0 0 1 16-Bit
by bit CIT2 in the Special Function Register T2CON Auto-Reload
(Table II). It has three operating modes: capture, auto- 0 1 0 1 16-Bit
reload (up or down counting), and baud rate generator.
Capture
The modes are selected by bits in T2CON as shown in
Table 10. 1 X X 1 Baud_Rate
Generator
X 0 1 1 Clock-Out
on P1.0
X X X 0 Timer Off
9-24
inter 8XF51FC
Table 11. T2CON: Timer/Counter 2 Control Register
T2CON Address = OC8H Reset Value = OOOOOOOOB
Bit Addressable
TF2 EXF2 RCLK TCLK I EXEN21 TR2
Bit 7 6 5 4 3 2 o
Symbol Function
TF2 Timor 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will
not bo set when either RCLK = 1 or TCLK = 1. '
EXF2 Timer 2 external flag set when either a capture or reload is caused by a negative transition
on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled EXF2 = 1 will cause the CPU
to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 does not
cause an interrupt in up/down counter mode (DCEN = 1).
RCLK Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its
receive clock in serial port Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used
for the receive clock.
TCLK Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its
transmit clock in serial port Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used
for the transmit clock.
EXEN2 Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a
negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0
causes Timer 2 to ignore events at T2EX.
TR2 Start/stop control for Timer 2. A logic 1 starts the timer.
C/T2 Timer or counter select. (Timer 2)
o = Internal timer (OSC/12 or OSC/2 in baud rate generator mode).
1 = External event counter (falling edge triggered).
CP/RL2 Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if
EXEN2 = 1. When cleared, auto-reloads will occur either with Timer 2 overflows or
negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK. = 1, this
bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
CAPTURE MODE 16-bit timer or counter which upon overflow sets bit
TF2 in T2CON. This bit can then be used to generate
In the capture mode there are two options selected by an interrupt. If EXEN2 = 1, Timer 2 still does the
bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a above, but with the added feature that a I-to-O tran-
T2 PIN o-----t TR2
CAPTURE TIMER 2
INTERRUPT
TRANSITION
DETECTION
T2EX PIN
EXEN2
270904-18
Figure 13. Timer 2 in Capture Mode
9-25
8XF51FC
sition at external input T2EX causes the current value will default to count up. When DCEN is set, Timer 2
.in the Timer 2 registers, TH2 and TL2, to be captured can count up or down depending on the value of the
into registers RCAP2H and RCAP2L, respectively. In T2EX pin. .
addition, .the transition at T2EX causes bit EXF2 in
T2CON to be set. The EXF2 bit, like TF2, can generate Figure 14 shows Timer 2 automatically counting up
an interrupt. The capture mode is illustrated in Figure when DCEN =. O. In this mode there are two options
13. selected by bit EXEN2 in T2CON. If EXEN2 = 0;
Timer 2 counts up to OFFFFH and then sets the TF2
bit upon overflow. The overflow also causes the timer
AUTO-RELOAD MODE registers to be reloaded with the 16-bit value in
(UP OR DOWN COUNTER) RCAP2H and RCAP2L. The values in RCAP2H and
Timer 2 can be programmed to count up or down when RCAP2L are preset by software. If EXEN2 = I, a 16-
configured in its 16-bit auto-reload mode. This feature bit reload can be triggered either by an overflow or by a
is invoked by a bit named DCEN (Down Counter En- I-to-O transition at external input T2EX. This tran-
sition also sets the EXF2 bit.Eithcr the TF2 or EXF2
able) located in the SFR T2MOD (sec Table 12). Upon
reset the DCEN bit is set to 0 so that Timer 2 bit can generate the Timer 2 interrupt if it is enabled.
Table 12. T2MOD: Timer 2 Mode Control Register
T2MOD Address = OC9H Reset Value = XXXX XXXOB
Not Bit Addressable
T20E DCEN
Bit 7 6 5 4 3 2 o
Symbol Function
Not implemented, reserved for future use. *
T20E Timer 2 Output Enable bit. Only in the 87C51 FC.
DECN Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down
counter.
'User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke
new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value
read from a reserved bit is indeterminate.
OVERFLOW
T2 PIN 0----1'
TRANSITION
DETECTION
TIMER 2
INTERRUPT
T2EX PIN
EXEN2
270904-19
Figure 14. Timer 2 Auto Reload Mode (DCEN = 0)
9-26
infef 8XF51FC
Setting the DCEN bit enables Timer 2 to count up or The Clock-out frequency depends on the oscillator fre-
down as shown in Figure IS. In this mode the T2EX quency and the reload value of Timer 2 capture regis-
pin controls the direction of count. A logic I at T2EX ters (RCAP2H, RCAP2L) as shown in this equation:
makes Timer 2 count up. The timer will overflow at
OFFFFH and set the TF2 bit which can then generate Clock-out Frequency =
an interrupt if it is enabled. This overflow also causes a
the l6-bit value in RCAP2H and RCAP2L to be re- Oscillator Frequency
loaded into the timer registers, TH2 and TL2, respec- 4 X (65536 - RCAP2H, RCAP2L)
tively.
A logic 0 at T2EX makes Timer 2 count down. Now In the Clock-Out mode Timer 2 roll-overs will not gen-
the timer underflows when TH2 and TL2 equal the erate an interrupt. This is similar to when it is used as a
values stored in RCAP2H and RCAP2L. The under- baud-rate generator. It is possible to use Timer 2 as a
flow sets the TF2 bit and causes OFFFFH to be reload- baud-rate generator and a clock generator simulta-
ed into the timer registers. neously. Note, however, that the baud-rate and the
Clock-out frequency will be the same.
The EXF2 bit toggles whenever Timer 2 overflows or
underflows. This bit can be used as a 17th bit of resolu-
tion if desired, In this operating mode, EXF2 does not 6.0 PROGRAMMABLE COUNTER
generate an interrupt. ARRAY
The Programmable Counter Array (PCA) consists of a
BAUD RATE GENERATOR MODE 16-bit timer/counter and five 16-bit compare/capture
modules as shown in l'i[',ure 17. The PCA timer/coun-
The baud rate generator mode is selected by setting the ter serves as a common lime base for the five modules
RCLK and/or TCLK bits in T2CON. Timer 2 in this and is the only timer which can service the PCA. Its
mode will be described in conjunction with the serial clock input can be programmed to count anyone of the
port. following signals:
• osciJIator frequency 12
PROGRAMMABLE CLOCK OUT • oscillator frequency 4
A 50% duty cycle clock can be programmed to come • Timer 0 overt1ow
out on Pl.O. This pin, besides being a regular I/O pin, • external input on ECI (1'1.2).
has two alternate functions. It can be programmed (1)
to input the external clock for Timer/Counter 2 or (2) Each compare/capture module can be programmed in
to output a 50% duty cycle clock ranging from 61 Hz anyone of the following modes:
to 4 MHz at a 16 MHz operating frequency. See Figure
• rising and/or falling edge capture
16.
• software timer
To configure the Timer/Counter 2 as a clock generator, • high speed ou I pu t
bit C!T2 (in T2CON) must be cleared and bit T20E in
• pulse width lIlodulalor.
T2MOD must be set. Bit TR2 (T2CON.2) also must be
set to start the timer (see Table 10 for operating
Module 4 can also be programmed as a watchdog tim-
modes).
er.
When the compare/capture modules are programmed
in the capture mode, software timer, or high speed out-
put mode, an interrupt can be generated when the mod-
ule executes its function. All five modules plus the PCA
timer overflow share one interrupt vector (more about
this in the PCA Interrupt section).
9-27
inter 8XF51FC
(DOWN COUNTING RELOAD VALUE)
TOGGLE
_ + c/fz =
T2 PIND--'
1
COUNT
DIRECTION
1 = UP
o = DOWN
(UP COUNTING IllLUI,O VALUE)
T2EX PIN
270904-20
Figure 15. Timer 2 Auto Reload Mode (DCEN 1)
-, Transition T20E (T2CON.l)
"'!.- Detector
P1.1'O-_+-<CY(~
~
(T2EX)
Timer2
~ Interrupt
EXEN2
270904-21
Figure 16. Timer 2 in Clock-Out Mode
9·28
8XF51FC
- 16 BITS EACH -
MODULE 0 P1.3/CEXO
MODULE 1 Pl.4/CEXI
--168ITS-
PCA TIMER/COUNTER I---+----l~ MODULE 2 P1.5/CEX2
L..._ _ _- - '
MODULE 3 Pl.6/CEX3
MODULE 4 Pl.7/CEX4
270904-22
Figure 17. Programmable Counter Array
The PCA timer/counter and compare/capture module~ gram of this timer. The clock input can be selected
share Port I pins for external I/O. These pins are listed from the following four modes:
below. If the port pin is not used for the PCA, it can • Oscillator frequency ..;- 12
still be used for standard I/O. The peA timer increments once per machine cycle.
With a 16 MHz crystal, the timer increments every
PCA Component External 110 Pin 750 ns.
16-bit Counter P1.2/ ECI
• Oscillator frequency ..;- 4
16-bit Module 0 P1.3/ CEXO The peA timer increments three times per machine
16-bit Module 1 P1.4 / CEX1 cycle. With a 16 MHz crystal, the timer increments
16-bit Module 2 P1.5/ CEX2 every 250 ns.
16-bit Module 3 P1.6 / CEX3
• Timer 0 overflow~
16-bit Module 4 P1.7 / CEX4 The peA timer increments whenever Timer 0 over-
flows. This mode allows a programmable input fre-
quency to the peA.
6.1 PCA 16-Bit Timer/Counter
• External input
The PCA has a free-running 16-bit timer/counter con- The peA timer increments when a I-to-O transi-,
sisting of registers CH and CL (the high and low bytes tion is detected on the Eel pin (PI.2). The max-
of the count value). These two registers can be read or imum input frequency in this mode is oscillator
written to at any time. Figure 18 shows a block dia- frequency 7 8.
FOSC/12
FOSC/4
TIMER 0 1---HYo 0-11--. INTERRUPT
OVERFLOW
EXT[~NAl
INPUT
(ECI)
CIDL
PROCESSOR IN
IDLE MODE
270904-23
Figure 18. PCA Timer/Counter
9-29
inter 8XF51FC
The mode register CMOD contains the Count Pulse The CCON register, shown in Table 14, contains two
Select bits (CPS 1 and CPSO) to specify the clock input. more bits which are associated with the PCA timer/
CMOD is shown in Table 13. This register also con- counter. The CF bit gets sct by hardware when the
tains the ECF bit which enables the PCA counter over- counter overflows, and the CR bit is set or cleared to
flow to generate the PCA interrupt. In addition, the turn the counter on or off. The other five bits in this
user has the option of turning off the PCA timer during register are the event flags for the compare/cflpture
Idle Mode by setting the Counter Idle bit (CIDL). The modules and will be discussed in the next section.
Watchdog Timer Enable bit (WDTE) will be discussed
in a later section.
Table 13. CMOD: PCA Counter Mode Register
CMOD Address = OD9H Reset Value = OOXX XOOOB
Not Bit Addressable
~C_ID_L~lw__DT_E~I~__~__~ ____~_C_PS_1-L_C_PS_O~_E_C_F~
BH 7 6 5 .4 3 2 0
Symbol Function
CIDL Counter Idle control: CIDL = 0 programs tho PCA Counter to continue functioning during
idle Mode. CIDL = 1 programs it to be gatod off during idle.
WDTE Watchdog Timer Enable: WDTE = 0 disables Watchdog Timor function on PCA Module 4.
WDTE = 1 enables it.
Not implemented, reserved for future use. '
CPS1 PCA Count Pulse Select bit 1.
CPSO PCA Count Pulse Select bit o.
CPS1 CPSO Selected PCA Input"
o 0 Internal clock, Fosc -7- 12
o 1 Internal clock, Fosc -7- 4
o Timer 0 overflow
1 External clock at ECI/P1.2 pin (max. rate = Fosc-7- 8)
ECF PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an
interrupt. ECF = 0 disables that function of CF.
NOTE:
'User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke
new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value
read from a reserved bit is indeterminate.
"Fosc = oscillator frequency
9-30
inter 8XF51FC
Table 14. CCON: PCA Counter Control Register
CCON Address = OD8H Reset Value = OOXO OOOOB
Bit Addressable
CF CR CCF4 CCF3 CCF2 CCF1 CCFO
Bit 7 6 5 4 3 2 o
Symbol Function
CF PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an
interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software but can
only be cleared by software.
CR PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared
by software to turn the PCA counter off.
Not implemented, reserved for future use'.
CCF4 PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software. .
CCF3 PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software.
CCF2 PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software.
CCF1 PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Mustbe
cleared by software.
CCFO PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software.
'NOTE:
User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke
new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value
read from a reserved bit is indeterminate.
6.2 Capture/Compare Modules Note the ECCFn bit which enables the PCA interrupt
when a module's event flag is set. The event flags
Each of the five compare/capture modules has six pos- (CCFn) are located in the CCON register and get set
sible functions it can perform: when a capture event, software timer, or high speed
output event occurs for a given module.
16-bit Capture, positive-edge triggered
16-bit Capture, negative-edge triggered Table 16 shows the combinations of bits in the
16-bit Capture, both positive and negative-edge CCAPMn register that arc valid and have a defined
triggered function. Invalid combinations will produce undefined
results.
16-bit Software Timer
16-bit High Speed Output Each module also has a pair of 8-bit compare/capture
8-bit Pulse Width Modulator. registers (CCAPnH and CCAPnL) associated with it.
These registers store the time when a capture event oc-
In addition, module 4 can be used as a Watchdog Tim- curred or when a compare event should occur. For the
er. The modules can be programmed in any combina- PWM mode, the high byte regiser CCAPnH controls
tion of the different modes. the duty cycle of the waveform.
Each module has a mode register called CCAPMn The next five sections describe each of the compare/
(n = 0, I, 2, 3, or 4) to select which function it will capture modes in detail.
perform. The CCAPMn register is shown in Table 15.
9-31
inter 8XF51FC
Table 15. CCAPMn: PCA Modules Compare/Capture Registers
CCAPMn Address CCAPMO ODAH Reset Value = XOOO OOOOB
(n = 0-4) CCAPM1 ODBH
CCAPM2 ODCH
CCAPM3 ODDH
CCAPM4 ODEH
Not Bit Addressable
IECOMn ICAPPn ICAPNn I MATn TOGn I PWMn IECCFn I
Bit 7 6 5 4 3 2 o
Symbol Function
Not implemented, reserved for future use'.
ECOMn Enable Comparator. ECOMn = 1 enables tho comparator function.
CAPPn Capture Positive, CAPPn = 1 enables positive edge capture.
CAPNn Capture Negative, CAPNn = 1 enables negative edge capture.
MATn Match. When MATn = 1, a match of the PCA counter with this module's compare/capture
register causes the CCFn bit in CCON to be set, flagging an interrupt.
TOGn Toggle. When TOGn = 1, a match of the PCA counter with this module's compare/capture
register causes the CEXn pin to toggle.
PWMn Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pin to be used as a pulse width
modulated output.
ECCFn Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register to generate
an interrupt.
NOTE:
'User software should not writo Is \0 reserved bits. These bits may be used in future 8051 family products to invoke
new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value
read from a reserved bit is indetorminate.
Table lS. PCA Module Modes (CCAPMn Register)
- ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn Module Function
X 0 0 0 0 0 0 0 No Operation
X X 1 0 0 0 0 X lS-Bit Capture by a Postive-Edge
Trigger on CEXn
X X 0 1 0 0 0 X lS-Bit Capture by a NegativecEdge
Trigger on CEXn
X X 1 1 0 0 0 X IS-Bit Capture by a Transition on CEXn
X 1 0 0 1 0 0 X IS-Bit Software Timer
X 1 0 0 1 1 0 X IS-Bit High Speed Output
X 1 0 0 0 0 1 0 8-Bit PWM
X 1 0 0 1 x 0 x Watchdog Timer
x= Don't Care
9-32
8XF51FC
6.3 16-Bit Capture Mode In the interrupt service routine, the l6-bit capture value
must be saved in RAM before the next capture event
Both positive and negative transitions can trigger a cap- occurs. A subsequent capture on the same CEXn pin
ture with the PCA. This gives the PCA the flexibility to will write over the first capture value in CCAPnH and
measure periods, pulse widths, duty cycles, and phase CCAPnL.
differences on up to live separate inputs. Setting the
CAPPn and/or CAPNn in the CCAPMn mode register
selects the input trigger-positive and/or negative tran- 6.4 16-Bit Software Timer Mode
sition-for module n. Refer to Figure 19.
In the compare mode, the l6-bit value of the PCA tim-
The external input pins CEXO through CEX4 are sam- er is compared with a l6-bit value pre-loaded in the
pled for a transition. When a valid transition is detected module's compare registers (CCAPnH, CCAPnL). The
(positive and/or negative edge), hardware loads the comparison occurs three times per machine cycle in
l6-bit value of the PCA timer (CH, CL) into the mod- order to recognize the fastest possible clock input (i.e.
ule's capture registers (CCAPnH, CCAPnL). The re- 1/. x oscillator frequency). Setting the ECOMn bit in
sulting value in the capture registers reflects the PCA the mode register CCAPMn enables the comparator
timer value at the time a transition was detected on the function as shown in Figure 20.
CEXn pin.
For the Software Timer mode, the MATn bit also needs
Upon a capture, the module's event flag (CCFn) in to be set. When a match occurs between the PCA timer
CCON is set, and an interrupt is flagged if the ECCFn and the compare registers, a match signal is generated
bit in the mode register CCAPMn is set. The PCA in- and the module's event flag (CCFn) is set. An interrupt
terrupt will then be generated if it is enabled. Since the is then flagged if the ECCFn bit is set. The PCA inter-
hardware does not clear an event flag when the inter- rupt is generated only if it has been properly enabled.
rupt is vectored to, the flag must be cleared in software. Software must clear the event flag before the next inter-
rupt will be flagged.
-1---_ INTERRUPT
PCA
TIMER/COUNTER
_--..--I
L..........
CEXn
PIN
n ~ 0, 1, 2, 3 or 4
x ~ Don't Care
CCAPMn MODE REGISTER
270904-24
Figure 19. PCA 16-Bit Capture Mode
9-33
8XF51FC
During the interrupt routine, a new 16-bit compare val- regular hold-ofT signals to the Watchdog. These circuits
ue can be written to the compare registers (CCAPnH are used in applications that are subject to electrical
and CCAPnL). Notice. however. that a write to noise, power glitches, electrostatic discharges, etc., or
CCAPnL clears the ECOMn bit which temporarily dis- where high reliability is required.
ables the comparator function while these registers are
being updated so an invalid match does not occur. A The Watchdog Timer function is only available on
write to CCAPnH sets the ECOMn bit and re-enables PCA module 4. In this mode, every time the count in
the comparator. For this reason, user software should the PCA timer matches the value stored in module 4's
write to CCAPnL first, then CCAPnH. compare registers, an internal reset is generated. (See
Figure 21.) The bit that selects this mode is WDTE in
the CMOD register. Module 4 must be set up in either
6.5 High Speed Output Mode compare mode as a Software Timer or High Speed Out-
put.
The High Speed Output (HSO) mode toggles a CEXn
pin when a match occurs between the PCA timer and a When the PCA Watchdog Timer times out, it resets the
pre-loaded value in a module's compare registers. For chip just like a hardware reset, except that it does not
this mode. the TOGri bit needs to be set in addition to d ri vc the reset pin high.
the ECOMn and MATn bits as seen in Figure 20. By
setting or clearing the pin in soft ware, the user can To hold ofT the reset, the user has three options:
select whether the CEXn pin will change from a logical (I) periodically change the compare value so it will
o to a logical I or vice versa. The user also has the never match the PCA timer,
option of flagging an interrupt when a match event oc-
(2) periodically change the PCA timer value so it will
curs by setting the ECCFn bit.
never match the compare value,
The HSO mode is more accurate than toggling port (3) disable the Watchdog by clearing the WDTE bit
pins in software because the toggle occurs before before a match occurs and then later re-enable it.
branching to an interrupt. That is. interrupt latency
will not effect the accuracy of the output. If the user The first two options are more reliable because the
does not change the compare registers in an interrupt Watchdog Timer is never disabled as in option # 3. The
routine, the next toggle will occur when the PCA timer second option is not recommended if other PCA mod-
rolls over and matches the last compare value. ules are being used since this timer is the time base for
all five modules. Thus, in most applications the first
solution is the best option.
6.6 Watchdog Timer Mode
If a Watchdog Timer is not needed, module 4 can·still
A Watchdog Timer is a circuit that automatically in- be used in other modes.
vokes a reset unless the system being watched sends
PCA CEXn PIN
TI"ER/CQUNTER
ENABLE
CCAP~n MODE REGISTER
RESET
WRITE TO
CCAPnl
WRITE TO n = 0, 1, 2, 3 or 4
CCAPnH x = Don'1 Care
"'" 270904-25
Figure 20. PCA 16·Bit Comparator Mode: Software Timer and High Speed Output
9-34
8XF51FC
6.7 Pulse Width Modulator Mode The PCA generates 8-bit PWMs by comparing the low
byte of the PCA timer (CL) with the low byte of the
Any or all of the five PCA modules can be pro- module's compare registers (CCAPnL). Refer to Figure
grammed to be a Pulse Width Modulator. The PWM 22. When CL < CCAPnL the output is low. When CL
output can be used to convert digital data to an analog 2 CCAPnL the output is high. The value in CCAPnL
signal by simple external circuitry. The frequency of the controls the duty cycle of the waveform. To change the
PWM depends on the clock sources for the PCA timer. value in CCAPnL without output glitches, the user
With a 16 MHz crystal the maximum frequency of the must write to the high byte register (CCAPnH). This
PWM waveform is 15.6 kHz. value is then shifted by hardware into CCAPnL when
CL rolls over from OFFH to OOH which corresponds to
the next period of the output.
PCA
Tltr.4ER/COUNTER
F=~--+.../ -+--+ RESET
ENABLE
GCAPM4 MODE REGISTER
RESET
WRITE TO
CCAP4l
Oon'l Cam
270004-26
Figure 21. Watchdog Timer Mode
CL MADE
FF TO 00 ---~7
TRANSITION
CL < CCAPnL
CL 2! CCAPnL CEXn PIN
n = 0,1,2,3 or 4
x = Don't Care
CCAPMn MODE REGISTER
270904-27
Figure 22. peA a-Bit PWM Mode
9-35
8XF51FC
DUTY CYCLE CCAPnH OUTPUT WAVEFORM
100% 00
90% 25
50% 128
10% 230
0.4% 255
270904-28
Figure 23. CCAPnH Varies Duty Cycle
CCAPnH can contain any integer from 0 to 255 to vary The serial port can operate in 4 modes:
the duty cycle from a 100% to 0.4% (see Figure 23).
Mode 0: Serial data enters and exits through RXD.
TXD outputs the shift clock. S bits are transmitted/re-
7.0 SERIAL INTERFACE ceived: S data bits (LSB first). The baud rate is fixed at
'/I:! the oscillator frcquency.
The serial port is full duplex, meaning it can transmit
and receive simultaneously. It is also receive-buffered, Mode 1: 10 bits arc transmitted (through TXD) or re-
meaning it can commence reception of a second bytc ceived (through RXD): a start bit (0), S data bits (LSB
before a previously received byte has been read from first), and a stop bit (1). On receive. the stop bit goes
. the, receive register. (However, if the first byte still into RBS in Special Function Register SCaN. The
hasn't been read by the time recept ion of the second baud rate is variable.
byte is complete, one of the bytes will be lost). The
serial port receive and transmit registers are both ac- Mode 2: II bits are transmitted (through TXD) or re-
cessed through Special Function Register SBUP. Actu- ceived (through RXD): a start bit (0), S data bits (LSB
ally, SBUF is two separate registers, a transmit buffer first). a programmable 9th data bit, and a stop bit (1).
and a receive buffer. Writing to SBUI' loads the trans- Refer to Figure 24. On Transmit, the 9th data bit (TBS
mit register, and reading SBUF accesses a physically in SCaN) can be assigned the value of 0 or I. Or, for
separate receive register. example, the parity bit (P in the PSW) could be moved
intoTB8. On receive, the 9th data bit goes into RB8 in
The serial port control and status register is the Special SCaN, while the stop bit is ignored. (The validity of
Function Register SCaN, shown in Table 17. This reg- the stop bit can be checked with Framing Error Detec-
ister contains the mode selection bits (SMO and SMI); tion.) The baud rate is programmable to either 1/32 or
the SM2 bit for the multiprocessor modes (see Multi- 1/64 the oscillator frequency.
processor Communications section); the Receive En-
able bit (REN); the 9th data bit for transmit and receive
(TBS and RBS); and the serial port interrupt bits (TI
andRI).
1 ,\1 ~STOP BIT
NINTH DATA BIT (Modes 2 and 3 only)
270904-29
Figure 24. Data Frame: Modes 1, 2 and 3
9-36
8XF51FC
Mode 3: 11 bits are transmitted (through TXD) or re- byte has its 9th bit set to O. All the slave processors
ceived (through RXD): a start bit (0), 8 data bits (LSB should have their SM2 bits set to 1 so they will only be
first), a programmable 9th data bit and a stop bit (1). In interrupted by an address byte. In fact, the 8XC51FA/
fact, Mode 3 is the same as Mode 2 in all respects FB has an Automatic Address Recognition feature
except the baud rate. The baud rate in Mode 3 is vari- which allows only the addressed slave to be interrupted.
able. That is, the address comparison occurs in hardware,
not software. (On the 8051 serial port, an address byte
In all four modes, transmission is initiated by any in- interrupts all slaves for an address comparison.)
struction that uses SBUF as a destination register. Re-
ception is initiated in Mode 0 by the condition RI = 0 The addressed slave then clears its SM2 bit and pre-
and REN = 1. Reception is initiated in the other pares to receive the data bytes that will be coming. The
modes by the incoming start bit if REN = 1. For more other slaves are unaffected by these data bytes. They
detailed information on each serial port mode, refer to are still waiting to be addressed since their SM2 bits are
the "Hardware Description of the 8051, 8052, and all set.
80C51."
7.3 Automatic Address Recognition
7.1 Framing Error Detection
Automatic Address Recognition reduces the CPU time
Framing Error Detection allows the serial port to check required to service the serial port. Since the CPU is
for valid stop bits in modes 1, 2, or 3. A missing stop bit only interrupted when it receives its own address, the
can be caused, for example, by noise on the serial lines, software overhead to compare addresses is eliminated.
or transmission by two CPUs simultaneously. With this feature enabled in one of the 9-bit modes, the
Receive Interrupt (RI) flag will only get set when the
If a stop bit is missing, a Framing Error bit FE is set. received byte corresponds to either a Given or Broad-
The FE bit can be checked in software after each recep- cast address.
tion to detect communication errors. Once set, the FE
bit must be cleared in software. A valid stop bit will not The feature works the same way in the 8-bit mode
clear FE. (Mode 1) as in the 9-bit modes, except that the stop bit
takes the place of the 9th data bit. If SM2 is set, the RI
The FE bit is located in SCON and shares the same bit flag is set only if the received byte matches the Given or
address as SMO. Control bit SMODO in the PCON reg- Broadcast Address and is terminated by a valid stop
ister (location PCON.6) determines whether the SMO bit. Setting the SM2 bit has no effect in Mode O.
or FE bit is accessed. If SMODO = 0, then accesses to
SCON.7 are to SMO. If SMODO = l, then accesses to The master can selectively communicate with groups of
SCON.7 are to FE. slaves by using the Given Address. Addressing all
slaves at once is possible with the Broadcast Address.
These addresses are defined for each slave by two Spe-
7.2 Multiprocessor Communications cial Function Registers: SADDR and SADEN.
Modes 2 and 3 provide a 9-bit mode to facilitate multi- A slave's individual address is specified in SADDR.
processor comunication. The 9th bit allows the control- SADEN is a mask byte that defines don't-cares to form
ler to distinguish between address and data bytes. The the Given Address. These don't-cares allow flexibility
9th bit is set to 1 for address bytes and set to 0 for data in the user-defined protocol to address one or more
bytes. When receiving, the 9th bit goes into RB8 in slaves at a time. The following is an example of how the
SCON. When transmitting, TB8 is set or cleared in user could define Given Addresses to selectively ad-
software. dress different slaves. .
The serial port can be programmed such that when the Slave 1:
stop bit is received the serial port interrupt will be acti- SADDR 1111 0001
vated only if the received byte is an address byte (RB8 SADEN 1111 1010
= 1). This feature is enabled by setting the SM2 bit in
SCON. A way to use this feature in multiprocessor sys- GIVEN 1111 OXOX
tems is as follows.
Slave 2:
When the master processor wants to transmit a block of SADDR 1111 0011
data to one of several slaves, it first sends out an ad- SADEN 1111 1001
dress byte which identifies the target slave. Remember,
an address byte has its 9th bit set to 1, whereas a data GIVEN 1111 OXX1
9-37
ifltti 8XF51FC
Table 17. SCON: Serial Port Control Register
.SCON Address = 98H Reset Value = 0000 OOOOB
Bit Addressable
ISMO/FEI SM1 SM2 REN TB8 RB8 TI RI
Bit: 7 6 5 4 3 2 o
(SMODO = 0/1)*
Symbol . Function
FE Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE
bit is not cleared by valid frames but should be cleared by software. The SMODO' bit mllst be
set to enable access to the FE bit.
SMO Serial. Port Mode Bit 0, (SMODO must = 0 to access bit SMO)
SM1 Serial Port Mode Bit 1
SMO SM1 Mode Description Baud Rate"
o 0 0 shift rogister Fosc/12
o 1 1 8-bit UART variable
o 2 9-bit UART Fosc/64 or Fosc/32
3 9-bit UART variable
SM2 Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then RI will
not be set unless the received 9th data bit (RBB) is 1, indicating an address, and the received
byte is a Given or Broadcast Address. In Mode 1, if SM2 = 1 then RI will not be activated
unless a valid stop bit was received, and the received byte is a Given or Broadcast Address.
In Mode 0, SM2 should be o.
REN Enables serial reception. Set by software to enable reception. Clear by software to disable
reception. .
TB8 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as
. desired. .
RB8 In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop
bit that was received. In Mode 0, RB8 is not used.
TI Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the
beginning of the stop bit in the other modes, in any serial transmission. Must be cleared by
software. '
RI Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway
through the stop bit time in the other modes, in any serial reception (except see SM2). Must
be clear.ed by software. . . ,
NOTE:
'SMODO is located at PCON.6
•• Fosc = oscillator frequency
The SADEN byte are selected such that each slave can Notice, however, that, bit 3 is a don't-care for both
be addressed separately. Notice that bit I (LSB) is a slaves. This allows two different addresses to select
don't-care for Slave l's Given Address, but bit 1 = 1 both slaves (1111 0001 or 1111 0101). If a third slave
for Slave 2. Thus, to selectively communicate with jus~ was added that required its bit 3 = 0, then the latter
Slave I the master must send an address with bit 1 =, 0 address could be used to communicate with Slave 1 and
(e.g. 1111 0000). 2 but not Slave 3.
Similarly, bit 2 = 0 for Slave 1, but is a don't-care for The master can also communicate. with all slaves at
Slave 2. Now to communicate with just Slave 2 an ad- once with the Broadcast Address. It is formed from the
dress with bit 2 = 1 must be used (e.g. 1111 0111). logical OR of the SADDR and SADEN registers with
zeros defined as don't-cares. The don't-cares also allow
Finally, for a master to communicate with both slaves
at once the address must have bit 1 = 1 and bit 2 = o.
9-38
8XF51FC
flexibility in defining the Broadcast Address, but in The Timer 1 interrupt should be disabled in this appli-
most applications a Broadcast Address will be OFFH. cation. The Timer itself can be configured for either
"timer" or "counter" operation, and in any of its 3
SADDR and SADEN are located at address A9H and running modes. In most applications, it is configured
B9H, respectively. On reset, the SADDR and SADEN for "timer" operation in the auto-reload mode (high
registers are initialized to DOH which defines the Given nibble ofTMOD = DOIDB). In this case, the baud rate
and Broadcast Addresses as XXXX XXXX (all don't- is given by the formula:
cares). This assures the 8XC5IFA/FB serial port to be
backwards compatibility with other MCS®-51 products Modes 1 and 3 2SMOD1 X Oscillator Frequency
which do not implement Automatic Addressing. Baud Rate 32 X 12 X [256 - (TH1)]
One can achieve very low baud rates with Timer 1 by
7.4 Baud Rates leaving the Timer 1 interrupt enabled, and configuring
the Timer to run as a 16-bit timer (high nibble of
The baud rate in Mode 0 is fixed: TMOD = DOOIB), and using the Timer 1 interrupt to
do a 16-bit software reload.
d Oscillator Frequency
Mode 0 Bau Rate = 12
Table 18 lists various commonly used baud rates and
how they can be obtained from Timer 1.
The baud rate in Mode 2 depends on the value of bit
SMODI in Special Function Register PCON. If
SMOOI = 0 (which is the value on reset), the baud 7.6 Using Timer 2 to Generate Baud
rate is '164 the oscillator frequency. If SMODI = 1, the Rates
baud rate is '132 the oscillator frequency.
Timer 2 is selected as the baud rate generator by setting
Mo de 2 BaudRate =
2SMOD1
x Oscillator64
Frequency TCLK and/or RCLK in T2CON (Table 11). Note that
the baud rates for transmit and receive can be simulta-
neously different. Setting RCLK and/or TCLK puts
The baud rates in Modes 1 and 3 are determined by the Timer 2 into its baud rate generator mode, as shown in
Timer 1 overflow rate, or by Timer 2 overflow rate, or Figure 25.
by both (one for transmit and the other for receive).
The baud rate generator mode is simijar to the auto-re-
load mode, in that a rollover in TH2 causes the Timer 2
7.5 Using Timer 1 to Generate Baud registers to be reloaded with the 16-bitvalue in registers
Rates RCAP2H and RCAI'2L, which are preset by software.
When Timer 1 is used as the baud rate generator, the
baud rates in Modes I and 3 are determined by the
Timer 1 overflow rate and the value of SMODI as fol-
lows:
Modes 1 and 3 = 2SM OD1 X Timer 1 Overflow Rate
Baud Rate 32
Table 18. Timer 1 Generated Commonly Used Baud Rates
-
Timer 1
Baud Rate Fosc ·SMOD Reload
CIT Mode
Value
Mode 0 Max: 1 MHz 12MHz X X X X
M.ode 2 Max: 375k 12MHz 1 X X X
Modes 1, 3: 62.5k 12MHz 1 0 2 FFH
19.2k 11.059 MHz 1 0 2 FDH
9.6k 11.059 MHz 0 0 2 FDH
4.8k 11.059 MHz 0 0 2 FAH
2.4k 11.059 MHz 0 0 2 F4H
1.2k 11.059 MHz 0 0 2 E8H
137.5 11.986 MHz 0 0 2 1DH
110 6MHz 0 0 2 72H
110 12MHz 0 0 1 FEEE;3H
9-39
intJ 8XF51FC
The baud rates in Modes 1 and 3 are determined by EXF2 but will not cause a reload from (RCAP2H,
Timer 2's overflow rate as follows: RCAP2L) to (TH2, TL2). Thus when Timer 2 is in use
as a baud rate generator, T2EX can be used as an extra
Timer 2 Overflow Rate external interrupt, if desired.
Modes 1 and 3 Baud Rates = 16
It should be noted that when Timer 2 is running (TR2
The Timer can be configured for either "timer" or = I) in "timer" function in the baud rate generator
"counter" operation. In most aEE,lications, iUs config- mode, one should not try to read or write TH2 or TL2.
ured for "timer" operation (C/T2 = 0). The "Timer" Under these conditions the Timer is being incremented
operation is different for Timer 2 when it's being used every state time, and the results of a read or write may
as a baud rate generator. Normally, as a timer, it incre- not be accurate. The RCAP2 registers may be read, but
ments every machine cycle (1/12 the oscillator frequen- shouldn't be written to, because a write might overlap a
cy). As a baud rate generator, however, it increments reload and cause write and/or reload errors. The timer
every state time ('12 the oscillator frequency). The baud should be turned off (clear TR2) before accessing the
rate formula is given below: Timer 2 or RCAP2 registers.
Modes 1 and 3 Oscillator Frequency Table 19 lists commonly used baud rates and how they
Baud Rate 32 x [65536 - (RCAP2H, RCAP2L)j can be obtained from Timer 2.
Table 19. Timer 2 Generated
where (RCAP2H, RCAP2L) is the content of Commonly Used Baud Rates
RCAP2H and RCAP2L taken as a 16-bit unsigned
Baud Fosc Timer 2
integer.
Rate Freq RCAP2H RCAP2L
Timer 2 as a baud rate generator is shown in Figure 25. 375k 12 MHz FF FF
This figure is.valid only if RCLK and/or TCLK = 1 in 9.6k 12 MHz FF D9
T2CON. Note that a rollover in 1'112 does not set TF2, 4.Bk 12 MHz FF B2
and will not generate an interrupt. Therefore, the Timer 2.4k 12MHz FF 64
2 interrupt does not have to be disabled when Timer 2 1.2k 12 MHz FE CB
is in the baud rate generator mode. Note too, thai if 300 12 MHz FB 1E
EXEN2 is set, a I-to-O transition in T2EX will set 110 12 MHz F2 AF
300 6MHz FD SF
110 6MHz F9 57
nMER 1
OVERFLOW
NOTE: OSC. FREQ. IS DIVIDED BY Z. NOT lZ.
TZ P I N - - - - - - '
RX CLOCK
TX CLOCK
"TIMER Z"
TZU PIN
INTERRUPT
EXENZ
L NOTE AVAILABILITY OF ADD~NAL EXTERNAL INTERRUPT
270904-30
Figure 25. Timer 2 in Baud Rate Generator Mode
9-40
8XF51FC
8.0 INTERRUPTS All of the bits that generat~ interrupts can be set or
cleared by software, with the same result as though it
The 8XF5IFC has a total of 8 interrupt vectors: two had been set or cleared by hardware. That is, interrupts
external interrupts (INTO and INTI), three timer inter- can be generated or pending interrupts can be cancelled
rupts (Timers 0, I, and 2), the PCA interrupt, the serial in software.
port interrupt and the write complete interrupt. These
interrupts are all shown in Figure 26. Each of these interrupts will be briefly described fol-
lowed by a discussion of the interrupt enable bits and
the interrupt priority levels.
INTO----o'" ITO
TFO-----------------------------------...
iNfi'---<l' 1T1
TF1-------------------------------------..
INTERRUPT
SOURCES
CF-:JECF
CCFn - : J E C C F n
~:-----------------D~-------------------------~~
TF2
EXF2------------------
D ~------------------------~.
WC----------------------------------------------~.
270904-31
(See exceptions when Timer 2 is used as baud rate generator or an up/down counter.)
Figure 26. Interrupt Sources
9-41
inter 8XF51FC
8.1 Externallnterrupts CCON. None of these flags is cleared by hardware
when the service routine is vectored to. Normally the
External Interrupts INTO and INTI can each be either service routine will have to determine which bit flagged
level-activated or transition-activated, depending on the interrupt and clear that bit in software. The PCA
bits ITO and ITt in register TCON. If ITx = 0, exter- interrupt is enabled by bit EC in the Interrupt Enable
nal interrupt x is triggered by a detected low at the register (sec Table 20). In addition, the CF flag and
INTx pin. If ITx == 1, external interrupt x is negative eaeh of the CCFn flags must also be enabled by bits
edge-triggered. The flags that actually· generate these ECF and ECCFn in registers CMOD and CCAPMn
interrupts are bits lEO and lEi in TCON. These flags respectively, in order for that flag to be able to cause an
are cleared by hardware when the service routine is interrupt.
vectored to only if the interrupt was transition-activat-
ed. If the interrupt was level-activated, then the extcr-
nal requesting source is what controls the request flag, 8.4 Serial Port Interrupt
rather than the on-chip hardware.
The serial port interrupt is generated by the logical OR
Since the external interrupt pins are sampled once each of bits RI and TI in register SCaN. Neither of these
machine cycle, an input high or low should hold for at flags is cleared by hardware whcn I hc service routine is
least 12 oscillator periods to ensure sampling. If the vectored to. The service routine will normally have to
external interrupt is transition-activated, the external determine whether it was RI or 1'1 that generated the
source has to hold the request pin h i~h for at least one interrupt, and the bit will have to be c1cared in soft-
cycle, and then hold it low for al least one cycle to ware.
ensure that the transition is seen so t hat interrupt re-
quest flag lEx will be set. lEx will be automatically
cleared by the CPU when the service routine is called. 8.5 Write Complete Interrupt
If external interrupt INTO or INT I is level-activated, The Write Complete Interrupt is generated by the WC
the external source has to hold the request active until hit (FCON.6) whenever a write operation to Flash
the requested interrupt is actually generated. Then it mcmory is concluded. The bit is automatically cleared
has to deactivate the request before t he interrupt serv- by hardware when the interrupt is serviced.
ice routine is completed, or else another interrupt will
be generated.
8.6 Interrupt Enable
Each of these interrupt sources can be individually en-
8.2 Timer Interrupts abled or disabled by setting or clearing a bit in the
Timer 0 and Timer I Interrupts are generated by TFO Interrupt Enable (IE) or Interrupt Enable A (lEA) reg-
and TFI in rcgistcr TCON, which are set by a rollover isters. (See Table 20.) Note that IE also contains a glob-
in their respective Timer/Counter registers (except see al disable bit, EA. If EA is set (I), the interrupts are
Timer 0 in Mode 3). When a timer interrupt is generat- individually enabled or disabled by their corresponding
ed, the flag that generated it is cleared by the on-chip bits in IE. If EA is clear (0), all interrupts are disabled.
hardware when the service routine is vectored to.
Timer 2 Interrupt is generated by the logical OR of bits 8.7 Priority Level Structure
TF2 and EXF2 in register T2CON. Neither of these
Each interrupt source can also be individually pro-
flags is cleared by hardware when the service routine is
grammed to one of four priority levels by setting or
vectored to. In fact, the service routine may have to
clearing bits in the four Interrupt Priority registers (IP,
determine whether it was TF2 or EXF2 that generated
IPH, IPA, IPHA) shown in Table 21. An interrupt can
the interrupt, and the bit will have to be cleared in
itself be interrupted by a higher priority interrupt, but
software.
not by another interrupt of the same or lower priority.
An interrupt of the highest priority cannot be interrupt-
ed by any other interrupt source. '
8.3 PCA Interrupt
The PCA interrupt is generated by the logical OR of
CF, CCFO, CCFI, CCF2, CCF3, and CCF4 in register
9-42
inter 8XF51FC
Table 20. IE and lEA: Interrupt Enable Registers
IE Address = OA8H Reset Value = 0000 OOOOB
Bit Addressable
EA EC ET2 ES ET1 EX1 ETO EXO
Bit 7 6 5 4 3 2 o
lEA Addross 00 OA7H Reset Value = XOXX XXXXB
Not Bit Addressable
[ - I ECW I
Bit 7 6 5 4 3 2 o
Enablo Bit = 1 enables tho interrupt.
Enablo Bit = 0 disables it.
Symbol Function
EA Global disable bit. IfEA = 0 all Interrupts are disabled. If EA = 1, each Interrupt can be
individually enabled or disabled by setting or clearing its enable bit.
EC PCA interrupt enable bit.
ET2 Timer 2 interrupt enable bit.
ES Serial Port interrupt enable bit.
ET1 Timer 1 interrupt enable bit.
EX1 External interrupt 1 enable bit.
ETO Timer 0 interrupt enable bit.
EXO External interrupt 0 enable bit.
EWC Write Complete interrupt enable bit.
Not implemented. Reserved for future use.'
NOTE:
'User software should not write 1s to reserved bits. These bits may be used in futuro 8051 family products to invoke
new features. In that case, the reset or inactive value of the new bit will be 0, and its active valuo will bo 1. Tho value
read from a reserved bit is indeterminate.
9·43
8XF51FC
Table 21. Interrupt Priority Registers
IP Address = OB8H Reset Value = XOOO OOOOB
Bit Addressable
PPC PT2 PS PT1 PX1 PTO PXO
IPA Address = OB6H Reset Value = XOXX XXXXB
Not Bit Addressable
PWC =-:J
IPH Address = OB7H Reset Value = XOOO OOOOB
Not Bit Addressable
PPCH PT2H PSH PT1H PX1H PTOH PXOH
IPAH Address = OB5H Reset Value = XOXX XXXXB
Not Bit Addressable
PWCH
IPH.x, IPAH.x IP.x,IPA.x Priority
0 0 lowest
0 1
1 0
1 1 highest
Symbol Function
Not implemented. Reserved for future use. *
PPC, PPCH PCS interrrupt priority bits.
PT2, PT2H Timer 2 interrupt priority bits.
PS, PSH Serial Port interrupt priority bits.
PT1, PT1 H Timer 1 interrupt priority bits.
PX1, PX1 H External interrupt 1 priority bits.
PTO, PTOH Timer 0 interrupt priority bits.
PXO, PXOH External interrupt 0 priority bits.
PWC, PWCH Write Complete interrupt priority bits.
NOTE:
'User software should not write Is to reserved bits. These bits may be used in future 8051 family products to invoke
new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value
read from a reserved bit is indeterminate.
9-44
intJ 8XF51FC
If two requests of different priority levels are received 2. The current (polling) cycle is not the final cycle in
simultaneously, the request of higher priority level is the execution of the instruction in progress.
serviced. If requests of the same priority level are re- 3. The instruction in progress is RETI or any write to
ceived simultaneously, an internal polling sequence de- the IE or IP registers.
termines which request is serviced. Thus within each
priority level there is a second priority structure deter- Any of these three conditions will block the generation
mined by the polling sequence shown in Table 22. of the LCALL to the interrupt service routine. Condi-
tion 2 ensures that the instruction in progress will be
Note that the "priority within level" structure is only completed before vectoring to any service routine. Con-
used to resolve simultaneous requests of the same priori- dition 3 ensures that if the instruction in progress is
ty level. RETI or any write to IE or IP, then at least one more
instruction will be executed before any interrupt is vec-
Table 22. Interrupt Priority tored to.
within Level Polling Sequence
1 (I:!ighest) INTO The polling cycle is repeated with each machine cycle,
2 Timer 0 and the values polled are the values that were present at
S5P2 of the previous machine cycle. If the interrupt
3 INT1
flag for a level-sensitive exterrulI interrupt is active but
4 Timer 1 not being responded to for one of the above conditions
5 PCA and is not still active when the blocking condition is
6 Serial Port removed, the denied interrupt will not be serviced. In
7 Timer 2 other words, the fact that the interrupt flag was once
a(Lowest) Write Complete active but not serviced is not remembered. Every poll-
ing cycle is new.
HOW INTERRUPTS ARE HANDLED The polling cycle/LCALL sequence is illustrated in
Figure 27.
The interrupt flags are sampled at S5P2 of every ma-
chine cycle. The samples are polled during the follow- Note that if an interrupt of a higher priority level goes
ing machine cycle. The Timer 2 interrupt cycle is active prior to SSP2 of the machine cycle labeled C3 in
slightly different, as described in the Response Time Figure 27, then in accordance with the above rules it
section. If one of the flags was in a set condition at will be vectored to during CS and C6, without any in-
S5P2 of the preceding cycle, the polling cycle will find struction of the lower priority routine having been exe-
it and the interrupt system will generate an LCALL to cuted.
the appropriate service routine, provided this hard-
ware-generated LCALL is not blocked by any of the
following· conditions:
1. An interrupt of equal or higher priority level is al-
ready in progress.
·······:---C1-_
IS5P21 S6
...' ... _-C2--_._-- • I C3 • I· C4 • I • C5--·····
........ ~':\-.--'------'t,t-------U--~--
11 '\\
..... A .....
f'71 '----
INTERRUPTS
ARE POLLED
" LONG CALL TO
INTERRUPT
~
INTERRUPT ROUTINE
INTERRUPT INTERRUPT VECTOR ADDRESS
GOES LATCHED
ACTIVE
270904-32
This is the fastest possible response when C2 is the final cycle of an instruction other than RETI or write IE or IP.
Figure 27. Interrupt Response Timing Diagram
9-45
intJ 8XF51FC
Thus the processor acknowledges an interrupt request 8.8 Response Time
by executing a hardware-generated LCALL to theap-
propriate servicing routine. The hardware-generated The INTO and INTI levels are inverted and latched
LCALL pushes the contents of the Program Counter into the Interrupt Flags lEO and lEI atS5P2 of every
onto the stack (but it does not save the PSW) and re- machine cycle. Similarly, the Timer 2 flag EXF2 and
loads the PC with an address. that depends on the the Serial Port flags RI and T! are set at S5P2. The
source of the interrupt being vectored to, as shown in values are not actually polled by the circuitry until the
Table 23. next machine cycle.
Table 23. Interrupt Vector Address The Timer 0 and Timer I flags, TFO and TFI, are set at
S5P2 of the cycle in which the timers overflow. The
Interrupt Interrupt Cleared by Vector
values are then polled by the circuitry in the next cycle.
Source Request Bits Hardware Address However, t he Timer 2 flag TF2 is set at S2P2 and is
INTO lEO No (level) 0003H polled in the same cycle in which the timer overflows.
Yes (trans.)
If a request is active and conditions arc right for it to be
Yes ''''knowledged, a hardware subroutine call to the re-
TIMER 0 TFO OOOBH
q nested service routine will be the next instruction to be
executed. The call itself takes two cycles, Thus, a mini-
INT1 IE1 No (level) 0013H l11um of three complete machine cycles elapses between
Yes (trans.) activation of art external interrupt request and the be-
ginning of execution of the service routine's first in-.
. TIMER 1 TF1 Yes ,. 001BH stl'llction. Figure 27 shows interrupt response timing .
SERIAL PORT RI,TI No 0023H A longer response time would result if the request is
blocked by one of the 3 previously listed conditions. If
an interrupt of equal or higher priority level is already
TIMER 2 TF2, EXF2 No 002BH
in progress, the additional wait time obviously depends
on the nature of the other interrupt's service routine. If
PCA CF, CCFn No 0033H the instruction in progress is not in its final cycle, the
(n = 0-4) additional wait time cannot be more than 3 cycles, since
Flash Memory WC Yes 0073H the longest instructions (MUL and DIY) are only 4
cycles long, and if the instruction in progress is RET!
Execution proceeds from that location until the RETI or write to IE or IP, the additional wait time cannot be
instruction is encountered. The RETI instruction in- more than 5 cycles (a maximum of one or more cycle to
forms the processor that this interrupt routine is no complete. the instruction in progress, plus 4 cycles to
longer in progress, then pops the top two bytes from the complete the next instruction if the instruction isMUL
stack and reloads the Program Coun ter. Execution of or DIY).
the interrupted program continues from where it left
off. Thus, in a single-interrupt system, the response time is
always more than 3 cycles and less than 9 cycles.
Note that a simple RET instruction would also have
retunied execution to the interrupted program, but it
would have left the interrupt control system thinking 9.0 RESET
interrupt was still in progress.
The reset input is the RST pin, which has a Schmitt
Note that the starting addresses of consecutive inter- Trigger input. A reset is accomplished by holding the
rupt service routines are only 8 bytes apart. That means . RST pin high for at least two machine cycles (24 oscil-
if consecutive interrupts are being used (lEO and TFO, lator periods) while the oscillator is running. The CPU
for example, or TFO and lEI), and if the first interrupt responds by generating an internal reset, with the tim~
routine is more than 7 bytes long, then that routine will ing shown in Figure 28.
have to execute a jump to some other memory location
where the service routine can be completed without The external reset signal is asynchronous to the internal
overlapping the starting address of the next interrupt clock. The RST pin is sampled during State 5 Phase 2
routine. of every machine cycle. The port pins, ALE, and PSEN
will maintain their current activities for the 19 oscilla-
tor periods after a logic I has been sampled at the RST
pin; that is, for 19 to 31 oscillator periods after the
external reset signal has been applied to the RST pin.
9-46
inter 8XF51FC
1--12 dsc. PERIODS ---'--+j
I 55 I 56 I 51 I 52 I 53 I 54 I 55 I 56 I 51 I52 153 I 54 I 55 I 56 I 51 I52 I 53 I 54 I
RST:
~
/ lllllllll /: ~
CINTERNALRESET SIGNAL
SAMPI.[ RST . ,
SAMPLE R5T
ALE: I ..-;-_--'n. __--'
P5EN:
PO:
,
..--11 OSC. PERIODS - - . ,....- - - - - - 1 9 OSC. PERIODS -~---..
"
270904-33
Figure 28. Reset Timing
While the RST pin is high, the port pins, ALE and
PSEN are weakly pulled high. After RST is pulled low, VCC--~~-----------------,
it will take I to 2 machine cycles for ALE and PSEN to
start clocking. For this reason, other devices can not be
synchronized to the internal timings of the 8XF5IFC. + VCC
Driving the ALE and PSEN pins to 0 while reset is 8XF51FC
active could cause the device to go into an indetermi-
nate state.
The internal reset algorithm redefines all the SFRs. Ta-
ble I lists the SFRs and their reset values. The internal
RAM is not affected by reset. On power up the RAM
content is indeterminate. -. 270904-34
Figure 29. Power on Reset Circuitry
9.1 Power-On Reset
valid reset the RST pin must bl! held high long enough
.For CHMOS devices, when VCC is turned on, an auto- to allow the oscillator to start up plus two machine
matic reset can be obtained by connecting the RST pin cycles.
to VCC through a I ,...F capacitor (Figure 29). The
CHMOS devices do not require an external resistor like On power up, Vee should rise within approximately
the HMOS devices because they have an internal pull- ten milliseconds. The oscillator start-up time will de-
down on the RST pin. pend on the oscillator frequency. For a 10 MHz crystal,
the start-up time is typically I ms. For a I MHz crystal,
When power is turned on, the circuit holds the RST pin the start-up time is typically 10 ms.
high for an amount of time that depends on the capaci-
tor value and the rate at which it charges. To ensure a
9-47
intJ 8XF51FC
With the given circuit, reducing Vee quickly to 0 caus- mode. In the Idle mode, the internal clock signal is
es the RST pin voltage to momentarily fall below OV. gated off to the CPU, but not to the Interrupt, Timer,
However, this voltage is internally limited and will not and Serial Port functions. The PCA can be pro-
harm the device. ' grammed either to pause or continue operating during
Idle (refer to the PCA section for more details). The
Note that the port pins will be in a random state until the CPU stalus is preserved in its entirety: the Stack Point-
oscillator has started and the internal reset algorithm er, Program Counter, Program Status Word, Accumu-
has written Is to them. lator, and all other registers maintain their data during
Idle. The port pins hold the logical states they had at
Powering up the device without a valid reset could the time Idle was activated. ALE and PSEN hold at
cause the CPU to start executing instructions from an logic high levels.
indeterminate location. This is because the SFRs, spe-
cifically the Program Counter, may not get properly There are two ways to terminate the Idle Mode. Activa-
initialized. tion of any enabled interrupt will cause PCON.O to be
cleared by hardware, terminating the Idle mode. The
interrupt will be serviced, and following RETI the next
10.0 POWER:-SAVING MODES OF instruction to be executed will be the one following the
OPER~TION instruction that put the device Into Idle.
For applications where power, consumption is critical, The nag bits (GFO and GFl) can be used to give an
the 8XF5lFC provides two power reducing modes of indication if an interrupt occurred during normal oper-
operation: Idle and Power Down. The input through ation or during Idle. For example, an instruction that
which backup power is supplied during these opera- activates Idle can also set one or both nag bits. When
tions is Vee. Figure 30 shows the internal circuitry Idle is terminated by an interrupt, the interrupt service
which implements these features. In the Idle mode routine can examine the nag bits.
(IDL = I), the oscillator continues to run and the In-
terrupt, Serial Port, PCA, and Timer blocks continue The other way of terminating the Idle mode is with a
to be clocked, but the clock signal is gated ofT to the hardware reset. Since the clock oscillator is still run-
CPU. In Power Down (PD = I), the oscillator is fro- ning, the hardware reset needs to be held active for only
zen. The Idle, and Power Down modes are activated by two machine cycles (24 oscillator periods) to complete
setting bits in Special Function Register PCON (Table the reset.
24).
The signal at the RST pin clears the IDL bit directly
and asynchronously. At this time the CPU resumes
10.1 Idle Mode program execution from where it left off; that is, at the
instruction following the one that invoked the Idle
An instruction that sets PCON.O causes that to be the Mode. As shown in Figure 28, two or three machine
last instruction executed before going into the Idle cycles of program execution may take place before the
~~
XTAL 2 = XTAL 1
INTERRUPT,
i'-+-OSERIAL PORT,
TIMER BLOCKS
CPU
270904-35
FIgure 30. Idle and Power Down Hardware
9-48
8XF51FC
Table 24. PCON: Power Control Register
PCON Address = 87H Reset Value = OOXX OOOOB
Not Bit Addressable
ISMOD1 ISMODO I POF GF1 GFO PO IDL
Bit 7 6 5 4 3 2 o
Symbol Function
SMOD1 Double Baud rate bit. When set to a 1 and Timer 1 is used to generate baud rates, and the
Serial Port is used in modes 1,2, or 3.
SMODO When set, Read/Write accesses to SCON.7 are to the FE bit. When clear, Read/Write
accesses to SCON.7 are to the SMO bit.
Not implemented, reserved for futuro use.·
POF Power Off Flag. Set by hardware on the rising edge of Vee. Set or cleared by software. This
flag allows detection of a power failure caused reset. Vee must remain above 3V to retain
this bit.
GF1 General-purpose flag bit.
GFO General-purpose flag bit.
PO Power Down bit. Setting this bit activates Power Down operation.
IDL Idle mode bit. Setting this bit activates idle modes operation.
If 1s are written to PO and IDL at the same time, PO takes precedence.
NOTE:
'User software should not write Is to unimplemented bits. These bits may be used in futuro 8051 family products to
invoke new features. In that case, the reset or inactive value of the new bit will bo 0, and its active value will be 1.
The value read from a reserved bit is indeterminate
internal reset algorithm takes control. On-chip hard- To properly terminate Power Down the reset or exter-
ware inhibits access to the internal RAM during this nal interrupt should not be executed before Vee is
time, but access to the port pins is not inhibited. To restored to its normal operating level and must be held
eliminate the possibility of unexpected outputs at the active long enough for the osci lIator to restart and sta-
port pins, the instruction following the one that invokes bilize (normally less than 10 illS).
Idle should not be one that writes to a port pin or to
external Data RAM. With an external interrupt, INT(l or INTI must be en-
abled and configured as level-sensitive. Holding the pin
low restarts the oscillator and bringing the pin back
10.2 Power Down Mode high completes the exit. After the RET! instruction is
executed in the interrupt service routine, the next in-
An instruction that sets PCON.I causes that to be the struction will be the one following the instruction that
last instruction executed before going into the Power put the device in Power Down.
Down mode. In this mode the on-chip oscillator is
stopped. With the clock frozen, all functions are
stopped, but the on-chip RAM and Special Function 10.3 Power Off Flag
Registers are held. The port pins output the values held
by their respective SRFs, and ALE and PSEN output The Power Off Flag (POF) is set by hardware when
lows. In Power Down Vee can be reduced to as low as Vee rises from OV to 5V. POF can also be set or
2V: Care must be taken, however, to ensure that Vee is cleared by software. This allows the user to distinguish
not reduced before Power Down is invoked. between a "cold start" reset and a "warm start" reset.
The 8XF51FC can exit Power Down with either a A cold start reset is one that is coincident with Vee
hardware reset or external interrupt. Reset redefines all being turned on to the device after it was turned off. A
the SFRs but does not change the on-chip RAM. An warm start reset occurs while Vee is still applied to the
external interrupt allows both the SFRs and the on- device and could be generated, for example, by a
chip RAM to retain their values. Watchdog Timer or an exit from Power Down.
9-49
inter 8XF51FC
Immediately after reset, the user's software can check 1. If WI' A is programmed, ou t -of-circuit programming
the status of the POF bit. POF = 1 would indicate a on array A is entirely disabled. Out-of-circuit pro-
cold start. The software then clears POF and com- gramming on array B is limited to programming 00.
mences its tasks. POF· = 0 immediately after reset Likewise, if WPB is programmed, out-of-circuit pro-
would indicate a warm start. gramming is disabled on array B and limited on ar-
ray A.
Vee must remain above 3V for POF to retain a O. 2. If WPA is programmed, programming array A by
executing external code is disabled. Programming ar-
ray B by executing external code is limited to pro-
11.0 FLASH MEMORY PROTECTION gramming 00. WPB disables programming of array
SCHEME B by external execution and limits programming of
array A by external execution to 00.
The 8XF51FC has 4 bits which can be programmed to
provide protection against software piracy. Two Read 3. If WPA is programmed, array A can no longer be
Protect bits prevent anything "outside" the chip from erased either through out-of-circuit erase operations
knowing its contents. Two Write Protect bits guard or through external code operation. Programming
against unwanted programming and erasure. WPA has no effect on the erasure of array B. WPB
disables olit-of-circuit and external code erasures on
Two of the bits (RPA and WPA) are associated with array B. WPB does not effect erasures of array A.
array A. The other bits (RPB and WPB) are associated
with array B. RPA and WPA are erased whenever ar- Tahle 25 defines the addresses of the protection bits.
ray A is erased. Erasing array B crases RPB and WPB. Table 26 summarizes the effects of programming these
hits.
These bits can be programmed from out-of-circuit us-
ing the control line levels given in t he data sheet. In-cir- Note that none of the protection bits prevent in-circuit
cuit programming is also available lIsing the algorithm accesses to the Flash memory. Even with both the
given in Section 2; be sure to set the AS bit (FCON.4) Write Protect bits programmed, the Flash arrays can be
since the protection bits reside in Special Flash Bit programmed and erased by executing internal code. (In
space. fact that is the only way the arrays can be erased when
both WP bits are set.) The 8XF51FC can always read
When programmed, the Read Protect bits act to pre- its own Flash memory using MOVC instructions from
vent anyone from knowing the contents of either the internal memory.
on-chip Flash memory or the on-chip RAM. The pro-
gramming of the RP bits has the following effects: Setting the protection bits affects only regular Flash
memory, not Special Flash Bit memory. Thus, the pro-
1. Execution from external memory is disabled if either tection bits can be programmed or verified regardless of
RPA or RPB is programmed. This prevents someone the states of the other protection bits. They cannot be
from reading the on-chip memory by executing erased. however, unless the array with which they are
MOVC instructions from external code. associated is erased.
2. If either RPA or RPB is programmed, out-of-circuit
programming of either array is limited to program- Table 25. Protection Bit Addresses
ming 00. This allows the user to prepare for an erase Address when Array Address when Array
operation but prevents anyone from programming
A Occupies OOaOh B Occupies OOOOh
one array with code that could read the other array.
3. If RPA is set, out-of-circuit verify operations on ar- RPA OOOOh 1000h
ray A will return 00 if the memory location in ques- WPA 0001h 1001h
tion contains 00, but will return FFh otherwise. RPB
has the same effect on array B. Again, this allows a RPB 1000h OOOOh
user to verify that an array is ready for erasure with- WPB 1001h 0001h
out allowing anyone to· explicitly know the memory
contents. NOTE:
Protection Bits are located in Special Flash Bit space.
The Write Protect bits guard against unauthorized or Some locations in this space are reserved for Intel use.
unintentional programming or erasure of the Flash Programming reserved locations could result in the dis-
memory. Programming of the WP bits has these effects: abling of some device features. Program only those loca-
tions defined for Protection and Swap bits.
9-50
8XF51FC
Table 26. Effects on Array A and Array B of Programming Protection Bits
Operation Program Erase Verify/Read
Out-of External Out-of External Out-of External
Method:
Circuit Execution Circuit Execution Circuit Execution
Effect on A B A B A B A B A A B
Array:
RPA LP LP D D D D LV D D
RPB LP LP D D D D LV D D
WPA D LP D LP D D
WPB LP D LP D D D
Key: LP- Limited Programming. Bytes of the affect cd array ~an only be programmed to 00 (as in preparation for
an erase operation). .
LV- Limited Verify. Program Verify opcrations on an affected array will return Os if the byte programmed
correctly. Erase Verify operations will return FFh if the byte is completely erased, otherwise the results
will be OOh.
0 - The operation is disabled.
Blank- The protection bit has no effect on the operation.
12.0 ONCE MODE 13.0 ON·CHIP OSCILLATOR
The ONCE (ON-Circuit Emulation) mode facilitates The on-chip oscillator for the CHMOS devices, shown
testing and debugging of systems using the 8XFSIFC in Figure 31, consists of a single stage linear inverter
without having to remove the device from the circuit. intended for use as a crystal-controlled, positive reac-
The ONCE mode is invoked by: tance oscillator. In this application the crystal is operat-
1. Pulling ALE low while the device is in reset and ing in its fundamental response mode as an inductive
PSEN is high; reactance in parallel resonance with capacitance exter-
nal to the crystal (Figure 32).
2. Holding ALE low as RST is deactivated.
The oscillator on the CHMOS devices can be turned off
While the device is in ONCE mode, the Port 0 pins go under software control by setting the PD bit in the
into a float state, and the other port pins, ALE, and PCON register. The feedback resistor Rr in Figure 31
PSEN are weakly pulled high. The oscillator circuit consists of paralleled n- and p-channel FETs controlled
remains active. While the device is in this mode, an by the PD bit, such that Rr is opened when PD = 1.
emulator or test CPU can be used to drive the circuit. The diodes Dl and 02, which act as clamps to Vee
and Vss, are parasitic to til<: Rr FETs.
Normal operation is restored after a valid reset is ap-
plied.
9-51
intJ 8XF51FC
The crystal specifications and capacitance values (CI A more in-depth discussion of crystal specifications, ce-
and C2 in Figure 32) are not critical. 30 pF can be used ramic resonators, and the selection of values for CI and
in these positions at any frequency with good quality C2 can be found in Application Note AP-ISS, "Oscilla-
crystals. In general, crystals used with these devices tors for Microcontrollers" in the Embedded Control
typically have the following specifications: Applications handbook.
ESR (Equivalent Series Resistance) see Figure 34
To drive the CHMOS parts with an external clock
Co (shunt capacitance) 7.0 pF maximum source, apply the external clock signal to XTALI and
CL (load capacitance) 30 pF ± 3 pF leave XTAL2floating as shown in Figure 33. This is an
Drive Level I MW important difference from the. HMOS parts. With
HMOS, the external clock source is applied to XTAL2,
Frequency, tolerance, and temperature range are deter- and XTAL 1 is grounded.
mined by the system requirements.
An external oscillator may encounter as much as a
A ceramic resonator can be used in place of the crystal 100 pF load at XTALI when it starts up. This is due to
in cost-sensitive applications. When a ceramic resona- interaction between the amplifier and its feedback ca-
tor is used, Cl and C2 are normally selected as higher pacitance. Once the external signal meets the VIL and
values, typically 47 pF. The manufacturer of the ceram- VIII specifications the .capacitance will not exceed
ic resonator should be consulted for recommendations 20 pF.
on the values of these capacitors.
TO INTERNAL Vec
nllNGCKTS
01
4000
XTALlrl~~Mr--1------+--1----¥~--~----r1XTM2
02
270904-36
Figure 31. OnoChip Oscillator Circuitry
9-52
8XF51FC
VCC
TO INTERNAL
nMING CKTS 500
V> 400
::>
:J:
0
300
.S
Vss '"
V>
200
BOCS1
XTAL1----- XTAL2------ "'
_ _.--QUARTZ CRYSTAL 100
OR CERAMIC
RESONATOR
4 8 12 16
CRYSTAL FREQUENCY in MHz
270904-37
270904-39
Figure 32. Using the CHMOS On-Chip Oscillator
Figure 34. ESR vs Frequency
8XF51FC Propagation delays are different for different pins. For
a given pin they vary with pin loading, temperature,
NC XTAL2 Vco and manufacturing lot. If the XTALl waveform
EXTERNAL is taken as the timing reference, propagation delays
OSCILLATOR ; > ( ) - - - - I XTAL1
SIGNAL may vary from 25 ns to 125 ns.
CMOS GATE The AC Timings section of the data sheets do not refer-
ence any timing to the XT ALl waveform. Rather, they
270904-38 relate the critical edges of control and input signals to
each other. The timings published in the data sheets
Figure 33. Driving the CHMOS Parts include the effects of propagation delays under the
with an External Clock Source specified test condition.
14.0 CPU TIMING ADDITIONAL REFERENCES
The internal clock generator defines the sequence of The following application notes provide supplemental
states that make up a machine cycle. A machine cycle information to this document and can be found in the
consists of 6 states, numbered S1 through S6. Each Embedded Control Applicatiolls handbook.
state time lasts for two oscillator periods. Thus a ma- 1. AP-125 "Designing Microcontroller Systems for
chine cycle takes 12 oscillator periods or 1 microsecond Electrically Noisy Environlllcnts"
if the oscillator frequency is 12 MHz. Each state is then
divided into a Phase 1 and Phase 2 half. 2. AP-155 "Oscillators for Microcontrollers"
3. AP-252 "Designing with thc 80C51BH"
Figure 4 and Figures 6 through 8 show when the vari- 4. AP-410 "Enhanced Serial Port on the 83C51FA"
ous strobe and port signals are clocked internally. The
figures do not show rise and fall times of the signals, 5. AP-415 "83C5IFA/FB PCA Cookbook"
nor do they show propagation delays between the 6. AB-41 "Software Serial Port Implemented with the
XT AL 1 signal and events at other pins. PCA"
7. AP-425 "Small DC Motor Control"
Rise and fall times are dependent on the external load-
ing that each pin must drive. They are approximately 8. The appropriate data sheet.
10 ns, measured between O.8V and 2.0V.
9-53
88F51FC
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
32 KBYTES USER PROGRAMMABLE FLASH MEMORY
88FS1FC-3.SMHzt012MHz,Vee = SV±10%
88FS1FC-1-3.S MHz to 16 MHz, Vee = 5V± 10%
• 32K On-Chip Flash Program Memory • Power Saving Idle and Power Down
(non-volatile Rd/Wr) Modes
• Two Independent Flash Banks • Three 16-Bit Timer/Counters
(4K and 28K Blocks)
• Programmable Counter Array
• In-Circuit Programming and Erase II 32 Programmable I/O Lines
• Protection Scheme for Each Bank • 8 Interrupt Sources, 4 Levels
• 256 Bytes of On-Chip Data RAM • Programmable Serial Channel
MEMORY ORGANIZATION
PROGRAM MEMORY: Up to 32 Kbytes of the program memory can reside in the on-chip Flash memory_ This
memory is divided into two separate blocks, one 4 Kbytes and the other 28 Kbytes. The 4K block and the
lower 4 Kbytes of the 28K block can swap addresses under program controJ. Thus initializing software and
interrupt vectors will always bo active even during erasure of either Flash bank. In addition, the device can
address up to 64K of program memory external to the chip.
DATA MEMORY: This micro controller has a 256 x 8 on-chip RAM. In addition, it can address up to 64 Kbytes
of external data memory.
The Intel 88F51 FC is a single-chip control-oriented microcontroller which is fabricated on Intel's reliable
CHMOS III-F technology. Being a member of the MCS®-51 family, the 88F51FC uses the same powerful
instruction set, has the same architecture, and is pin-for-pin compatible with the existing MCS-51 family of
products. The 88F51 FC is an enhanced version of the 87C51. Its added features make it an even more
powerful microcontroller for applications that require Non-Volatile Read/Write memory, Pulse Width Modula-
tion, High Speed I/O, and up/down counting capabilities. It has a versatile serial channel that facilitates multi-
processor communications by including automatic address re90gnition. It a.lso has framing error detection.
October 1990
9-54 Order Number: 270898-001
inter 88F51FC
P2.0 - P2.7
-----------,
PSEN
TIMING
ALE/W£
AND
£A/VPP CONTROL
RST
P1.0-P1.7 P3.0- P3.7
270898-1
Figure 1. 88F51FC Block Diagram
9-55
intJ 88F51FC
FLASH MEMORY GLOSSARY OF Write: Refers to both program and erase opera-
tions.
TERMS
FLASH: Non-volatile, random access, rewritable
memory. The term originated to describe the way PACKAGES
entire blocks of this memory can be very quickly Prefix Package Type
Part
erased.
88F51FC P 40-Pin Plastic DIP
In-circuit: Refers to programming or erasure of the N 44-Pin PLCC
flash memory during code execution.
Out-of-clrcuit: Refers to programming or erasure of
the flash memory by applying signals at the pins. PIN DESCRIPTIONS
Vee: Supply voltage.
Read: Access of flash memory while Vpp = Vee.
Read mode is used to examine the code at any time Vss: Circuit ground.
OTHER than during the programming and erasure
algorithms.
VSS1: Secondary ground (in PLCC only). Provided to
reduce ground bounce and improve power supply
Verify: Access of flash memory when Vpp = VpPH.
by-passing.
Verify modes are used to assure that a recently pro-
grammed memory location will hold its value through NOTE:
subsequent stress. Verify modes should be used im- This pin is not a sUbstitute for the Vss pin (pin 22).
mediately following the programming or erasure of
an address.
"": "! "! q Vioq~,,!'"1
INDEX (1)00000
(T2) PLO Vee CORNER
n. 0:: 0:: 0:: 0:: > > Q.. 0.. D.. Q..
(T2EX) Pl.l PO.O (ADO)
(ECI) P 1.2 PO. 1 (AD1) P1.S PO.4
(CEXO) Pl.3 PO.2 (AD2) P1.6 PO.5
(CEXI) P1.4 PO.3 (AD3) Pl.? PO.6
(CEX2) PI.S POA (AD4) RST PO.7
(CEX3) PI.6 PO.S (ADS) P3.0 EA/Vpp
(CEX4) P1.7 PO.6 (AD6) Ne Ne
RESET PO.? (AD?) P3.1 13 ALE/WE
P3.2 14 PSEN
(RXD) P3.0 EIi/vpp
P3.3 15 P2.7
(TXD) P3.1 ALE/WE
P3.4 16 P2.6
(INTO) P3.2 PSEN
P3.5 17 P2.5
(INTl ) P3.3 P2.7 (A1S)
(TO) P3.4 P2.6 (AI4)
.,f<"i .... ...
'" ~ ~ N'"n. Nn.
::i II) 0 0
(Tl) P3.S P2.S (A13) rt")
...J II) z N
n. n. ~ x~ > n.
(Wii) P3.6 P2.4 (AI2) x
(iiD) P3.? P2.3 (All) 270898-3
XTAL2 P2.2 (AI D) PLCC
XTAL1 P2.1 (A9)
.vss P2.0 (AB)
270898-2
DIP
Figure 2. Pin Connections
9-56
inter 88F51FC
Port 0: Port 0 is an 8-bit, open drain, bidirectionalI/O current (IlL, on the data sheet) because of the inter-
port. As an output port each pin can sink several LS nal pullups.
TTL inputs. Port 0 pins that have 1's written to them
float, and in that state can be used as high-imped- Port 2 emits the high-order address byte during
ance inputs. fetches from external Program Memory and during
accesses to external Data Memory that use 16-bit
Port 0 is also the multiplexed low-order address and addresses (MOVX @DPTR). In this application it
data bus during accesses to external Program and uses strong internal pull ups when emitting 1'so Dur-
Data Memory. In this application it uses strong inter- ing accesses to external Data Memory that use 8-bit
nal pullups when emitting1 's, and can source and addresses (MOVX @Ri), Port 2 emits the contents of
sink several LS TTL inputs. the P2 Special Function Register.
Port 0 also receives the code bytes during out-of-cir- Some Port 2 pins receive the high-order address bits
cuit programming, and outputs the code bytes during during out-of-circuit Flash writing and program verifi-
flash verification. External pullup resistors are re- cation.
quired during program verification.
Port 3: Port 3 is an 8-bit bidirectional I/O port with
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can drive
internal pullups. The Port 1 output buffers can drive .LS TTL inputs. Port 3 pins that have 1's written to
LS TTL inputs. Port 1 pins that have 1's written to them are pulled high by the internal pullups, and in
them are pulled high by the internal pull ups, and in that state can be used as inputs. As inputs, Port 3
that state can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source
pins that are externally being pulled low will source current (IlL, on the data sheet) because of the pull-
current (ilL, on the data sheet) because of the inter- ups.
nal pull ups.
Port 3 also serves tilo functions of various special
In addition, Port 1 serves the functions of the follow- features of the 8051 Family, as listed below:
ing special features of the 88F51 FC:
Port Pin Alternate Function
Port Pin Alternate Function
P3.0 RXD (soria I input port)
P1.0 T2 (External Count Input to Timer/ P3.1 TXD (sorial output port)
Counter 2), Clock-Out P3.2 INTO (oxtornal interrupt 0)
P1.1 T2EX (Timer/Counter 2 Capture/ P3.3 INT1 (oxturnal interrupt 1)
Reload Trigger and Direction Control) P3.4 TO (Timor 0 external input)
P1.2 ECI (External Count Input to the PCA) P3.5 T1 (Timor 1 external input)
P1.3 CEXO (External I/O for Compare/ P3.6 WR (oxtornal data memory write strobe)
Capture Module 0) P3.7 RD .(extomal data memory read strobe)
---
P1.4 CEX1 (External I/O for Compare/
Capture Module 1) Some Port 3 pins rocoive the high-order address bits
during out-of-circuit Flash writing and verification.
P1.5 CEX2 (External I/O for Compare/
Capture Module 2)
RST: Reset input. A iligh on this pin for two machine
P1.6 CEX3 (External I/O for Compare/ cycles while the oscillator is running resets the de-
Capture Module 3) vice. An internal pulldown resistor permits a power-
P1.7 CEX4 (External I/O for Compare/ on reset with only a capacitor connected to Vee.
Capture Module 4)
ALE: Address Latch Enable output pulse for latching
the low byte of the address during accesses to ex-
Port 1 receives the low-order address bytes during
ternal memory. This pin (ALE/WE) is also the write
out-of-circuit Flash writklg and verifying. .
pulse input during out-of-circuit writing to the
88F51FC.
Port 2: Port 2 is an 8-bit bidirectional I/O port with
internal pullups. The Port 2 output buffers can drive
In normal operation ALE is emitted at a constant
LS TTL inputs. Port 2 pins that have 1's written to rate of Ys the oscillator frequency, and may be used
them are pulled high by the internal pullups, and in
for external timing or clocking purposes. Note, how-
that state can be used as inputs. As inputs, Port 2 ever, that one ALE pulse is skipped during each ac-
pins that are externally being pulled low will source
cess to external Data Memory.
9-57
intJ 88F51FC
Throughout the remainder of this data sheet, ALE
will refer to the signal coming out of the ALE/WE C2
pin, and the pin will be referred to as the ALE/WE 1--~--1 XTAL 2
pin.
PSEN: Program Store Enable is the read strobe to
o
external· Program Memory. I--~--t XTAL 1
When the 88F51 FC is executing code from external ~--------1 vss
Program Memory, PSEN is activated twice e.ach ma-
chine cycle, except that two PSEN activations are 270898-4
Cl, C2~ 30 pF ± 10 pF for Crystals
skipped during each access to external Data Memo- = 10 pF for Ceramic Rosonators
ry.
Figure 3. Oscillator Connections.
EAlVpp: External Access enable. EA must be pulled
low in order to enable the device to fetch code from
. external Program Memory locations OOOOH to
OFFFFH.
N/C . XTAL2
EA should be pulled above VIH for internal program
executions. EXTERNAL
OSCILLATOR XTAL 1
SIGNAL
This pin also receives the programming supply volt-
age (VPPH) during Flash writing and verification.
XTAL 1: Input to the inverting oscillator amplifier.
270898-5
XTAL2: Output from the inverting oscillator amplifier.
Figure 4. External Clock Drive Configuration
OSCILLATOR CHARACTERISTICS IDLE MODE
XTAL 1 and XTAL2 are the input and output, respec-
The user's software can invoke the Idle Mode. When
tively, of a inverting amplifier which can be config-
the microcontroller is in this mode, power consump-
ured for use as an on-chip oscillator, as shown in tion is reduced. The Special Function Registers and
Figure 3. Either a quartz crystal or ceramic resonator
the onboard RAM retain their values during Idle, but
may be used. More detailed information concerning
the processor stops executing instructions, Idle
the use of the on-chip oscillator is available in Appli-
Mode will be exited if the chip is reset or if an en-
cation Note AP-155, "Oscillators for Microcontrol-
abled interrupt occurs. The PCA timer/counter can
lers".
optionally be left running or paused during Idle
Mode.
To drive the device from an external clock source,
XTAL 1 should be driven, while XTAL2 floats, as
shown in Figure 4. There are no requirements on the
duty cycle of the external clock signal, since the in- POWER DOWN MODE
put to the internal clocking circuitry is through a di- To save even more power, a Power Down mode can
vide-by-two flip-flop, but minimum and maximum be invoked by software, In this mode, the oscillator
high and low times specified on the data sheet must is stopped and the instruction that invoked Power
be observed. Down is the last instruction executed. The on-chip
RAM and Special Function Registers retain their val-
An. external oscillator may encounter as much as a ues until the Power Down mode is terminated.
100 pF load at XTAL 1 when it starts up. This is due
to interaction between the amplifier and its feedback On the 88F51 FC either a hardware reset or an exter-
capacitance. Once the external signal meets the VIL nal interrupt can cause an exit from Power Down.
and VIH specifications the capacitance will not ex- Reset redefines all the SFRs but does not change
ceed 20 pF. the on-chip RAM, An external interrupt allows both
the SFRs and on-chip RAM to retain their values,
9-58
88F51FC
Table 1. Status of the External Pins during Idle and Power Down
Program
Mode ALE PSEN PORTO PORn PORT2 PORT3
Memory
Idle Internal 1 1 Data Data Data Data
Idle External 1 1 Float Data Address . Data
Power Down Internal 0 0 Data Data Data Data
Power Down External 0 0 Float Data Data Data
NOTE:
For more detailed information on the reduced power modes refer to current Embedded Controller Handbook, and Applica-
tion Note AP-252, "Designing with the BOC51 BH".
To properly terminate Power down the reset or ox- In-circuit program/erase/verify is controlled by two
ternal interrupt should not be executed before Vee is new Special Function Registers. The Flash Timing
restored to its normal operating level and must be (FT) register resides at address OCFH. It is used to
held active long enough for the oscillator to restart compute fixed duration program/erase pulses from
and stabilize (normally less than 10 ms). the crystal frequency as follows:
With an external interrupt, INTO and INT1 must be Program pulse duration = (2 x Crystal period) x
enabled and configured as level-sensitive. Holding (4S) x (ft + 1)
the pin low restarts the oscillator but bringing the pin
back high completes the exit. Once the interrupt is Erase pulse duration = 1024 x program pulse
serviced, the next instruction to be executed after duration.
RETI will be the one following the instruction that put
the device into Power Down. where: s = binary value of FT.5-FTA
ft = binary value of FT.3-FT.0
DESIGN CONSIDERATION The programming pulse duration must meet the
TLLLHp spec given at the ond of this document. The
• When the idle mode is terminated by a hardware erase pulse duration must 11100t the T LLLHe spec.
reset, the device normally resumes program exe- With the above algorithm, tho user can meet these
cution, from where it left off, up to two machine requirements and still run at ,\ wide range of crystal
cycles before the internal reset algorithm takes frequencies.
control. On-chip hardware inhibits access to inter-
nal RAM in this event, but access to the port pins The Flash CONtrol (FCON) rogister is found at ad-
is not inhibited. To eliminate the possibility of an dress OCEH. It contains tllO Write Complete interrupt
unexpected write when Idle is terminated by re- flag and the Write Interrupt Enable bit. It is also used
set, the instruction following the one that invokes to select between two address spaces (user flash vs
Idle should not be one that writes to a port pin or protection bits) and to choose an address range (the
to external memory. 4 Kbyte array or the 28 Kbyte array). The lowest
three bits of this register are the High Voltage (HV),
WRite/ReaD (WR/RD), and ProGraM/ERaSe
FLASH MEMORY (PGM/ERS) bits. These bits are used to select from
among five possible flash memory accesses: code
The 88F51 FC offers 32K bytes of user Flash memo- fetch, program, erase, program verify, and erase ver-
ry plus four protection bits all of which can be read, ify.
written and verified both by external circuitry and in-
ternal code. Out-of-circuit program/erase/verify is
described later in this document.
9-59
88F51FC
MEMORY BLOCK SWAPPING ONCETM MODE
The 32 Kbytes of Flash memory on the 88F51 FC are The ONCE ("On-Circuit Emulation") Mode facilitates
broken into two arrays of 4 Kbytes (Array A) and testing and debugging of systems using the
28 Kbytes (Array 8). Array 8 is further broken in a 88F51 FC without the 88F51 FC having to be re-
4-Kbyte block (80) and a 24-Kbyte block (81). To moved from the circuit. The ONCE Mode is invoked
allow for maximum program/erase flexibility, either by:
Array A or 80 can reside at address O. 1) Pull ALE low while the device is in reset and
PSEN is high;
The structure of the memory is determined by two
bits associated with array A, SW1 A and SWOA. Fig- 2) Hold ALE low as RST is deactivated.
ure 5 shows how the bit values determine the loca-
tion of array A and the bit addresses. While the device is in ONCE Mode, the Port 0 pins
go into a float state, and the other port pins and ALE
and PSEN are weakly pulled high. The oscillator cir-
SWlll=O,SWAO=O cuit remains active. While the 88F51 FC is in this
SWAO=O
SWA1=1
OR mode, an emulator or test CPU can be used to drive
SWill X,SWAO=l the circuit. Normal operation is restored when a nor-
'--.
mal reset is applied.
Array B1 IIrray B1
Array BO
Address 2000h - -
IIrrayA
Address 1000h
Array A IIrray BO
.- Address OOOOh
Swap Bit Addro,;,,,',;: SWilP Bil Addresses,
SWAO-30h SWIIO-l030h
SWAl-3111 SWlll-l031h
Figure 5. Flash Block Configuration
9-60
88F51FC
ABSOLUTE MAXIMUM RATINGS* NOTICE: This document contains information on
products in the design phase of development. Do not
Ambient Temperature Under Bias .... O·C to + 70·C finalize a design with this information. Revised infor-
Storage Temperature .......... - 65·C to + 150·C mation will be published when the product is avail-
able.
Voltage on EA/vpp Pin to Vss ....... OV to + 12.6V
• WARNING: Stressing the device beyond the "Absolute
Voltage on Any Other Pin to Vss .. - O.5V to + 6.5V Maximum Ratings" may cause permanent damage.
IOL Per 1/0 Pin ........................... 15 mA These are stress ratings only. Operation beyond the
Power Dissipation .......................... 1.5W "Operating Conditions" is not recommended and ex-
tended exposure beyond the "Operating Conditions"
(based on PACKAGE heat transfer limitations, not
may affect device reliability.
device power consumption)
TARGETED D.C. CHARACTERISTICS TA = O·Cto +70·C;Vee = 5V ±10%;Vss = OV
Targeted
Targeted Targeted
Symbol Parameter Typ Unit Test Conditions
Min Max
(Note 4)
VIL Input Low Voltage -0.5 0.2Vee- 0.1 V
VIL1 Input Low Voltage (EA) 0 0.2Vee- 0.3 V
VIH Input High Voltage 0.2 Vee+0.9 Vee+ 0.5 V
(Except XTAL 1, RST)
VIH1 Input High Voltage (XTAL 1, RST) 0.7 Vee Vee+ 0.5 V
VOL Output Low Voltage (Note 5) 0.3 V IOL = 100 /J-A (Note 1)
(Ports 1, 2, and 3)
0.45 V IOl = 1.6 mA (Note 1)
1.0 V IOl = 3.5 mA (Note 1)
VOL1 Output Low Voltage (Note 5) 0.3 V IOL = 200 /J-A (Note 1)
(Port 0, ALE, PSEN)
0.45 V IOL = 3.2 mA (Note 1)
1.0 V IOL = 7.0 mA (Note 1)
VOH Output High Voltage Vee- 0.3 V IOH = -10 /J-A
(Ports 1, 2, and 3, ALE, PSEN)
Vee- 0.7 V IOH = -30/J-A
Vee- 1.5 V IOH = -60/J-A
VOH1 Output High Voltage Vee- 0.3 V IOH = -200/J-A
(Port 0 in Extemal Bus Mode)
Vee- 0.7 V IOH = -3.2mA
Vee- 1.5 V IOH = -7.0 mA
IlL Logical 0 Input Current -50 /J-A VIN = 0.45V
(Ports 1 , 2, and 3)
III Input Leakage Current (Port 0) ±10 /J-A 0.45 < VIN < Vee
III Logical 1 to 0 Transition Current -650 /J-A VIN = 2V
(Ports 1 , 2, and 3)
9-61
88F51FC
TARGETED D.C. CHARACTERISTICS
TA = O°C to + 70°C; VCC = 5V ±10%; VSS = OV (Continued)
Targeted
Targeted Targeted
Symbol Parameter Typ Unit Test Conditions
Min Max
(Note 4)
RRST RST Pulldown Resistor 40 225 kfl
CIO Pin Capacitance 10 pF @1 MHz, 25°C
Icc Power Supply Current: (Note 3)
Running at 12 MHz (Figure 6) 20 40 mA
Idle Mode at 12 MHz (Figure 6) 5 10 mA
Power Down Mode 15 100 p.A
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports
1, 2 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1
to 0 transitions during bus operations. In applications where capacitance loading exceeds 100 pFs, the noise pulse on the
ALE signal may exceed o.av. In theso cases, it may be desirablo to qualify ALE with a Schmitt Trigger, or use an Address
Latch with a Schmitt Trigger Strobe input.
2. Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the 0.9 Vee specification when the
address lines are stabilizing.
3. See Figures 7-10 for test conditions. Minimum Vcc for Power Down is 2V.
4. Typicals are based on limited numbor of samples and are not guaranteed. Tho values listod are at room temperature and
5V.
5. Under steady state (non-transient) conditions, IOL must be externally limitod as follows:
Maximum IOL per port pin: 10mA
Maximum IOL per a-bit port-
Port 0: 26 mA
Ports 1, 2 and 3: 15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
60mAr---------_r----------r-------~_r--------_,
50mAr---------+---------~--------_+------~~
40mAr---------_r----------r-------~~~------~
30mAr---------_r--------~~~------_r--------~
12MHz 16MHz
270898-6
ICC Max at other frequencies is given by:
Active Mode
Icc Max ~ (Ose Freq x 3) +4
Idle Mode
Icc Max ~ (Osc Freq X 0.5) + 4
Where Osc Freq is in MHz, IcC is in mAo
Figure 6_ Icc vs Frequency
9-62
inter 88F51FC
Vee
Ilee
Vee t Vee
Vee
Vee PO PO
RST EAI+--.....I RST EAI----.
88F51FC 88,51 FC
XTAL2 XTAL2
CLOCK (NC)
XTALI XTALI
SIGNAL
Vss Vss
270898-7 270898-8
All other pins disconnected All other pins disconnected
TCLCH = TCHCL = 5 ns TCLCH = TCHCL = 5 ns
Figure 7. Icc Test Condition, Active Mode Figure 8. Icc Test Condition Idle Mode
Vee
PO
RST EA t---..,
88,51FC
(NC) XTAL2
XTALt
Vss
270898-9
All other pins disconnected
Figure 9. Icc Test Condition, Power Down Mode
Vcc = 2.0V to 5.5V
Vee-O.5 • - - - - - -'.r~~---
0.7 Vee
0.45V ---'C0.2 Vee-a' 1
...
TCHCL
270898-10
Figure 10. Clock Signal Waveform for Icc Tests in Active and Idle Modes. TCLCH = TCHCL = 5 ns
9·63
intJ 88F51FC
EXPLANATION OF THE A.C. N: Control Pins for Program/EraselVerify
SYMBOLS P: PSEN
Q: Output Data
Each timing symbol has 5 characters. The first char-
acter is always a 'T' (stands for time). The other R: RD signal
characters, depending on their positions, stand for T: Time
the name of a signal or the logical status of that
V: Valid
signal. The following isa list of all the characters and
what they stand for. W: WR signal
X: No longer a valid logic level
A: Address
Z: Float
C: Clock
D: Input Data For example,
H: Logic level HIGH
TAVLL = Time from Address Valid to ALE Low
I: Instruction (program memory contents) TLLPL = Time from ALE Low to PSEN Low
L: Logic level LOW, or ALE
A.C. CHARACTERISTICS TA = O·C to + 70·C, Vee cc 5V ± 10%, Vss = OV, Load Capacitance for
Port 0, ALE/WE and PSEN = 100 pF, Load Capacitance for All Other Outputs = 80 pF
TARGETED EXTERNAL PROGRAM MEMORY CHARACTERISTICS
12 MHz Oscillator Variable Oscillator
Symbol Parameter Targeted Targeted Targeted Targeted Units
Min Max Min Max
1/TCLCL Oscillator Frequency 3.5 16 MHz
TLHLL ALE Pulse Width 127 2TCLCL-40 ns
TAVLL Address Valid to ALE Low 43 TCLCL-40 ns
TLLAX Address Hold After ALE Low 53 TCLCL-30 ns
TLLlV ALE Low to Valid Instruction In 234 4TCLCL-100 ns
TLLPL ALE Low to PSEN Low 53 TCLCL-30 ns
TPLPH PSEN Pulse Width 205 3TCLCL-45 ns
TPLIV PSEN Low to Valid Instruction In 145 3TCLCL-105 ns
TPXIX Input Instruction Hold After PSEN 0 0 ns
TPXIZ Input Instruction Float After PSEN 59 TCLCL-25 ns
TAVIV Address to Valid Instruction In 312 5TCLCL-105 ns
TPLAZ PSEN Low to Address Float 10 10 ns
TRLRH RD Pulse Width 400 6TCLCL-100 ns
TWLWH WR Pulse Width 400 6TCLCL-100 ns
TRLDV RD Low to Valid Data In 252 5TCLCL-165 ns
TRHDX Data Hold After RD 0 0 ns
TRHDZ Data Float After RD 107 2TCLCL-60 ns
TLLDV ALE Low to Valid Data In 517 8TCLCL-150 ns
9-64
inter 88F51FC
TARGETED EXTERNAL PROGRAM MEMORY CHARACTERISTICS (Continued)
.
12 MHz Oscillator Variable Oscillator
Symbol Parameter Targeted Targeted Targeted Targeted Units
Min Max Min Max
TAVDV Address to Valid Data In 585 9TCLCL-165 ns
TLLWL ALE Low to RD or WR Low 200 300 3TCLCL-50 3TCLCL+50 ns
TAVWL Address Valid to WR Low 203 4TCLCL-130 ns
TOVWX Data Valid before WR 33 TCLCL-50 ns
TWHOX Data Hold after WR 33 TCLCL-50 ns
TOVWH Data Valid to WR High 433 7TCLCL-150 ns
TRLAZ RD Low to Address Float 0 0 ns
TWHLH RD or WR High to ALE High 43 123 TCLCL-40 TCLCL+40 ns
EXTERNAL PROGRAM MEMORY READ CYCLE
ALE
-_oJ
TPXIZ
PORT a AO-A?
----'
A8-A15
PORT 2
--_oJ
270898-11
EXTERNAL DATA MEMORY READ CYCLE
ALE
PSEN
!------TLLDV 'I
---o~-- TRLRH - - - + I
RD
PORTO
~---TAVWL
PORT2 P2.0-P2.? OR AB-A15 FROM DPH AB-A15 FROM PCH
270898-12
9-65
inter 88F51FC
EXTERNAL DATA MEMORY WRITE CYCLE
ALE
TLLWL-~-+----TWLWH---I
I-----t---TOVWH - - - - I
PORTO rROt.l RI OR OPL OATA OUT INSTR. IN
I-----TAVWL----l
PORT2 _ _ _, ' -_ _ _ _..;..P.;;.2..;...0-....;.P.;;2..;...7...;O....;.R..;..A.;...B-_A....;.1,;.,5__
rR__O_t.l...;0_P_H_ _ _- - , , -_ _
AB_-_A_15_r_R_O_t.l_P__
CH_ _
270898-13
TARGETED SERIAL PORT TIMING - SHIFT REGISTER MODE
Test Conditions: TA = O°C to + 70°C; Vee = 5V ± 10%; Vss = OV; Load Capacitance = 80 pF
12 MHz Oscillator Variable Oscillator
Symbol Parameter Targeted Targeted Targeted Targeted Units
Min Max Min Max
TXLXL Sorial Port Clock Cycle Time 1 12TCLCL JLs
TOVXH Output Data Setup to Clock 700 1OTCLCL -133 ns
Rising Edge
TXHOX Output Data Hold after 50 2TCLCL-117 ns
Clock Rising Edge
TXHDX Input Data Hold After Clock 0 0 ns
Rising Edge
TXHDV Clock Rising Edge to Input 700 1OTCLCL -133 ns
Data Valid
SHIFT REGISTER MODE TIMING WAVEFORMS
INSTRUCTION I 0 2 3 4 5 7 B
I t
CLEAR RI SET RI
270898-14
9-66
inter 88F51FC
TARGETED EXTERNAL CLOCK DRIVE
Targeted Targeted
Symbol Parameter Units
Min Max
1/TClCl Oscillator Frequency
BBF51FC 3.5 12
MHz
8BF51 FC-1 3.5 16
TCHCX High Time 20 ns
TClCX low Time 20 ns
TClCH Rise Time 20 ns
TCHCl Fall Time 20 ns
EXTERNAL CLOCK DRIVE WAVEFORM
270898-15
A.C. TESTING INPUT
Input, Output Waveforms Float Waveforms
os
vce- •
O.4SV
=><. O9
_O_.2_V-'C:..:;C_+__._ _ _ _
0.2 Vcc-O.1
x=·
VLOAO+O.l V
VLOAO
r--------,.
>TIMING REFERENCE
POINTS
VLOAO-O.l V ' - _ _ _ _ _ _---J VOL +0.1 V
270898-17
270898-16
For timing purposes a pori pin i:; no longer floating when a
AC Inputs during testing are driven at Vee-0.5V for a Logic "1" 100 mV change from load volt"!I" OGcurs, and begins to float
and 0.45V for a Logic "0". Timing measurements are made at VIH when a 100 mV change frolll tilt! loaded VOHIVOL level occurs.
min for a Logic "1" and VIL max for a Logic "0". IOL/IOH ;, ± 20 mA.
9-67
88F51FC
+5V
40
vee
1-8 88F51FC 32-39
AO-A7 PI PGM DATA
21-26 31
P2.0-
A8-A13 EA/Vpp } PROGRAM
P2.5
30 SIGNALS
ALE/WE
14
A14 P3.4 29
PSEN
15 28
A15 P3.5 P2.7
27
18 P2.6
XTAL2 17
P3.7 CONTROL SIGNALS·
16
P3.6
19 13
XTAL 1 P3.3
20 9
Vss RST
270898-18
"'See Table 2 for proper input on theSf' pll1~;
Figure 11. Programming/Erasing the 88F51 Fe
Table 2. FI;]sh Program/Erase/Verify Modes (H VIH, L = Vld
ALE/ EAt
Mode RST PSEN P2.6 P2.7 P3.3 P3.6 P3.7
WE Vpp
Program Code Data I-I L -U VpPH L H H H H
Verify Prog. Code Data H
-_.
L H VPPH L H L H H
Read Code Data H L H H L H L H H
Verify Erase H L H VPPH L L L H H
Erase Array A or B' H L -U VPPH L L H H H
Read Signature Bytes H L H Vee L L L L L
Program Special Flash
H L -U VPPH L H H H L
Bits"
Verify Programmed Special
H L H VpPH L H L H L
Flash Bits
Read Special Flash Bits H L H H L H L H L
Verify Erased Special
H L H VPPH L L L H L
Flash Bits
*To select the array which will be erased. place the 'address of any byte from within that array on the address lines.
*'NOTE:
Special Flash Bits include the four protection bits (RPa. RPb. WPa. WPb). the swap bits (SWOA and SW1A) and the read·
only Memory Structure bit. Some addresses in the Special Flash bit space are reserved for Intel use. Programming these
reserved addresses could result in the disabling of further programming/erasure, Program only those addresses given in
Tab/e3.
9·68
88F51FC
Table 3, Special Flash Bit Addresses
Address when Array A Address when Array B
Bit
Begins at OOOOHh Begins at OOOOh
Read Protect Bit, Array A (RPa) OOOOh 1000h
Read Protect Bit, Array A (RPb) 1000h OOOOh
Write Protect Bit, Array A (WPa) 0OO1h 1001h
Write Protect Bit, Array A (WPb) 1001h 0OO1h
Swap Bit 0 (SWOA) 0030h 1030h
Swap Bit 1 (SW1A) 0031h 1031h
Memory Structuro Bit (Read Only) 0010h 0010h
NOTE:
The Special Flash bits occupy a space which is separate from flash code memory. Some addresses in the Special Flash bit
space are reserved for Intol uso. Programming these reserved addresses could result in the disabling of further program-
ming/erasure. Program only II/Oso addresses given above.
270898-19
Figure 12. 88F51FC Programming Algorithm
9-69
88F51FC
270898-20
Figure 13. 88F51FC Erase Algorithm
9-70
88F51FC
DEFINITION OF TERMS grammed before erasure if the user plans to use the
protection or swapping features. (If the user does
Address Lines: P1.0-P1.7, P2.0-P2.5, P3.4-P3.5 not ever plan to use these features, the bits may be
respectively for AO-A 15. ignored entirely). The Write Protect bit should NOT
be programmed, since programming that bit will dis-
Data Line: PO.0-PO.7 for 00-07. able future erasure. Erasing a block of memory eras-
es not only the code data associated with that block,
Control Signals: RST, PSEN, P2.6, P2.7, P3.3, but the Read Protect and Swap bits as well. .
P3.6, P3.7.
To erase a block, the sequence shown in Figure 13
Program Signals: ALE/WE, EAlVpp. should be exercised. Consider the block "unerasa-
ble" if it fails to erase completely after 1000 erase
pulses. Successful erasure leaves 1's in all memory
OUT-OF-CIRCUIT PROGRAMMING OF locations. Note that the programming of protection
THE FLASH MEMORY bits may alter erasability as explained in the protec-
tion bit section.
The part must be running with a 4 MHz to 6 MHz
oscillator. Apply the address of a target Flash mem-
ory location to the address lines and the data byte to FLASH MEMORY PROTECTION BITS
data lines. Hold control and program s!9!!..als at the
levels indicated in Table 2. The ALE/WE pin pro- The 88F51 FC provides two protection bits per mem-
vides the write strobe. Unlike standard EPROM pro- ory array to guard the on-chip memory against soft-
gramming, only one write pulse should be applied at ware piracy. Programming the Read Protect bits
a time and the programmed location should be veri- (RPa and RPb) prevents anything outside the chip
fied after every pulse. Since Vpp is held at VpPH from determining tho array contents. The Read Pro-
during program/erase verification, changing the Vpp tect bits limit program verify operations, inhibit exter-
level from VPPH to VIH between programming and nal execution and disable further out-of-circuit pro-
verification is optional. Consider the programming gramming of either array. Programming the Write
operation a failure if the memory location is not pro- Protect bits (WPa and WPb) inhibits out-of-circuit
grammed after 25 write pulses. programming and erasure. These bits are pro-
grammed externally using the control settings given
NOTE; in Table 2. They are erased whenever the array with
Exceeding the Vpp maximum for any amount of which they are associated is erased.
time could damage the device permanently. The
Vpp source must be well regulated and free of Data in RAM is protocted by using the Read Protect
glitches. bits to disallow exoGution from external memory.
Table 4 summarizc~; the protoction bit functions.
OUT-OF-CIRCUIT PROGRAMMING
ALGORITHM
MEMORY STRUCTURE BIT
Refer to Tables 2 and 3 and Figure 11 for address,
data, and control signals set up. To program the How can a user uetormine the memory configuration
88F51 FC the sequence shown in Figure 12 must be from "outside" the BUF51 FC? By reading a special
exercised. Do not apply more than 25 programming flash location, the Memory Structure bit. A read of
pulses to one memory location. Note that the pro- location 0010 (in the Special Flash Bit space which
gramming of protection bits may alter programmabil- also contains the protection bits and the swap bits)
ity as explained in the protection bit section. will return a "0" if array A occupies location 0 and a
"1" if array B occupies location O. Control line levels
are given in tables 2 and 3.
OUT-OF-CIRCUIT ERASURE OF THE
FLASH MEMORY Reading the Signature Bits
The flash memory is erased in blocks. Either the 4K
The 88F51 FC has three signature bytes in locations
array or the 28K array may be erased at one time.
30H, 31 Hand 60H. To read these bytes, activate the
control lines as shown in Table 2.
In order to avoid over-erasure, every memory loca-
tion in the block must be programmed (set to 0) be-
fore that block can be erased. The Read Protect bit Location: 30H = 89H
and the Swap bits (array A only) should also be pro- 31H = 58H
60H = 8CH
9-71
inter 88F51FC
Table 4 Protection Bit Functionality
Read
Program Verify Erase Read
(Using MOVC
(Out-of- (Out-of- (Out-of- (Out-of-
When Running
Circuit) Circuit) Circuit) Circuit)
Externally)
Read Protect Bit LP LV D A D
Write Protect Bit D A A D A
Both Read and Write
D D D D D
Protect Bits
Legend:
A: Allows full functionality of the operation
D: Disallows the operation completely
LP: limited programmin~n only program OOH in preparation for an erase operation:
LV: limited verify-Program Verify will produce 00 at port if byte is correctly programmed. Erase verify will produce FFh at
port if byte is correctly erased.
Read vs Verify locations or from variations in Vpp. Verify modes
must be used immediately following the program-
With FLASH memory there are two modes which al- ming or erasure of an address.
Iowa user to examine the memory array. In Verify
mode, the Vpp must be at VPPH. For Read mode, In Read mode, the part accesses the memory just as
Vpp = VIH. it would for internal code execution. Use this mode
for code dumps or other instances iri which the
Use Program Verify mode (and Erase Verify mode) memory is only being read, not wiitten.
to guarantee that a memory location will remain pro-
grammed (or erased) despite stross. Stress can re- The Verification timings given later in this document
sult from subsequent programming of other memory also apply to Read Mode.
TARGETED FLASH MEMORY PROGRAMMING/ERASE AND VERIFICATION
CHARACTERISTICS " .
TA = 21°C to 27°C; Vee = 5V :1 10%; Vss = OV
Targeted Targeted
Symbol Parameter Units
Min Max
VPPH Program/EraselVerify
11.4 12.6 V
Supply Voltage
Ipp Program/EraselVerify
30 rnA
Supply Current
1/TCLCL Oscillator Frequency 4 6 MHz
TAVWL Address Setup to WE Low 48TCLCL
TWHAX Address Hold after WE 48TCLCL
TDVWL Data Setup to WE Low 48TCLCL
TWHDX Data Hold after WE 48TCLCL
TEVWL Enable Setup to WE Low 48TCLCL
TWHEX Enable Hold after WE 48TCLCL
TSHWL Vpp Setup to WE Low 10 JoLs
TWHSL Vpp Hold after WE 10 JoLs
9-72
intJ 88F51FC
TARGETED FLASH MEMORY PROGRAMMING/ERASE AND VERIFICATION
CHARACTERISTICS
TA = 21'C to 27"C; Vee = 5V ± 10%; Vss = OV (Continued)
Targeted Targeted
Symbol Parameter Units
Min Max
TWLWHp WE Width (Programming) 10 25 fLs
TWLWHe WE Width (Erase) 5 15 ms
-
TAVQV Address to Data Valid 48TCLCL
TELQV Enable Low to Data Valid 48TCLCL
TEHQZ Data Float after Enable 48TCLCL
TARGETED ERASE AND PROGRAMMING PERFORMANCE
Targeted Targeted
Parameter Units
Min Typical
Erase/Program Cycles 10,000 100,000 cycles
DIFFERENCES BETWEEN THE and two Write Protect bits to allow for maximum
flexibility and protection. There is no encryption
88F51FC AND THE 87C51FC mechanism in the 88F51FC.
For the convenience of the experienced FC user, - Both parts can be programmed by applying sig-
here is a summary of the major differences between nals to their pins but the algorithms for accom-
the 88F51 FC and the 87C51 FC: plishing this differ greatly. For the 87C51 FC, five
- The 32 Kbytes of on-chip memory is UV erasable programming pulses are used and the code is
on the 87C51 FC. It is erased electrically on the usually programmed in blocks and then verified
88F51FC. in blocks. With the 88F51 FC only one program-
ming pulse is applied at a time and each memory
- The 32 Kbytes of on-chip memory can be both location should be verified immediately after it
programmed and erased during program execu- has been programmed.
tion on the 88F51 FC.
- The 32 Kbytes of on-chip memory on the
- The 87C51 FC uses an encryption array and 88F51 FC are broken into two blocks, either of
three protection bits to guard against software which can occupy address o.
piracy. The 88F51 FC has two Read Protect bits
9-73
inter 88F51FC
FLASH PROGRAM/ERASE AND VERIFICATION WAVEFORMS
Program/Erase Verify
AO-A15 ADDRESS ADDRESS
-TAVQV
DO-07
ALE/WE
,I Data In (program only)
TDVWL -
TAVWL
-- TWHDX
TWHAX
I-
DATA OUT
I..-.....<
- TWLWHp,
-TWLWHe
.
VpPH
I
EA/Vpp
Vee
~ -TWHSL-"~
:~ ,
.r::::
- - - - _ ..
-TWHEX'-~I TELQV __ I-- ..:::::J I-TEHQZ
,CONTROL
Signals"
(Enable)
)(
'I
XXXXXXXXX )( I
'I
'
270898-21
NOTES:
'Lowering EAlVpp from Vpp to Vee between program/era so and verify is optional.
"Control Signals include RST, PSEN, P2.6, P2.7, P3.3, P3.6, and P3.7.
Revision History
This is. the first version of the 88F51 Fe .data sheet.
9-74
88F51FC
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
32 KBYTES USER PROGRAMMABLE FLASH MEMORY
EXPRESS
II Extended Temperature Range (- 40°C II Power Saving Idle and Power Down
to +85°C) Modes
II 32K On-Chip Flash Program Memory II Three 16-Bit Timer/Counters
(Non-Volatile Read/Write)
II Programmable Counter Array
II Two Independent Flash Banks
II 32 Programmable 110 Lines
(4K and 28K Blocks)
II 8 Interrupt Sources, 4 Levels
II In-Circuit Programming and Erase
II Programmable Serial Channel
II Protection Scheme for Each Bank
II 256 Bytes of On-Chip Data RAM
The Intel EXPRESS system offers enhancements to the operation specifications of the MCS-51 family of
microcontrollers. These EXPRESS products are designed to meet the needs of those applications whose
operating requirements exceed commercial standards.
With the commercial standard temperature range, operational characteristics aro guaranteed over the temper-
ature range of O·C to + 70·C. With the extended temperature range option, operational characteristics are
guaranteed over the range of - 40·C to + 85·C.
The 88F51 FC EXPRESS is packaged in a 40-pin plastic DIP package and in a 44-pin PLCC package. In order
to designate a part as an EXPRESS part, a 'T' is added as a prefix to tho part number. For example,
TN88F51 FC denotes an EXPRESS part in a PLCC package.
All A.C. and D.C. parameters in the commercial data sheets apply to the EXPRESS devicos.
October 1990
9-75 Order Number: 270910-001
83C152 Hardware 10
Description and Data Sheets
III
August 1990
83C152 Hardware Description
Order Number: 270427-004
10-1
83C152 HARDWARE CONTENTS PAGE
DESCRIPTION 1.0 INTRODUCTION .................... 10-3
2.0 COMPARISON OF 80C152 AND
80C51BH FEATURES ............ ; 10-3
2.1 Memory Space .................. 10-3
2.2 Interrupt Structure .............. 10-11
2.3 Reset .......................... 10-12
2.4 Ports 4,5 and 6 ................. 10-13
2.5 Timers/Counters ............... 10-13
2.6 Package ........................ 10-13
2.7 Pin Description ................. 10-14
2.B Power Down and Idle ........... 10-17
2.9 Local Serial Channel ....... , .... 10-17
3.0 GLOBAL SERIAL CHANNEL ...... 10-17
3.1 Introduction ..................... 10-17
3.2 CSMA/CD Operation ........... 19c20
3.3 SDLC Operation ................ 10-27
3.4 User Defined Protocols ......... 10-34
3.5 Using the GSC .................. 10-34
3.6 GCS Operation ................. 10-42
3.7 Register Descriptions ........... 10-44
3.B Serial Backplane vs Network
Environment .................. 10-47
4.0 DMA OPERATION ................. 10-47
4.1 DMA with the BOC152 ........... 10-47
4.2 Timing Diagrams ................ 10-50
4.3 Hold/Hold Acknowledge ........ 10-50
4.4 DMA Arbitration ................. 10-55
4.5 Summary of DMA Control Bits . " 10-59
5.0 INTERRUPT STRUCTURE ......... 10-60
5.1 GSC Transmitter Error
Conditions .................... 10-62
5.2 GSC Receiver Error
Conditions .................... 10-63
6.0 GLOSSARY ........................ 10-64
10-2
83C152 HARDWARE DESCRIPTION
1.0 INTRODUCTION use of external program memory. The second difference
is that RESET is active low in the 83C152 and active
The 83CI52 Universal Communications Controller is high in the 80C51BH. This is very important to deSign-
an 8-bit microcontroller designed for the intelligent ers who may currently be using the80C5IBH and plan-
management of peripheral systems or components. The ning to use the 83C152, or are planning on using both
83CI52 is a derivative of the 80C51BH and retains the devices on the same board. The third difference is that
same functionality. The 83C152 is fabricated on the GFO and GF1, general purpose flags in PCON, have
same CHMOS III process as the 80C51BH. What been renamed GFIEN and XRCLK. GFIEN enables
makes the 83CI52 different is that it has added func- idle flags to be generated in SDLC mode, and XRCLK
tions and peripherals to the basic 80C5IBH architec- enables the receiver to be externally clocked. All of the
ture that are supported by new Special Functio!l Regis- previously unused bits are' now being used and inter-
ters (SFRs). These enhancements include: a high speed rupt vectors have been added to support the new en-
multi-protocol serial communication interface, two hancements. Programmers using old code generated for
channels for DMA transfers, HOLD/HLDA bus con- the 80C51BH will have to examine their programs to
trol, a fifth I/O port, expanded data memory, and ex- ensure that new bits are properly loaded, and that the
panded program memory. new interrupt vectors will not interfere with their pro-
gram.
In addition to a standard UART, referred to here as
Local Serial Channel (LSC), the 83CI52 has an on- Throughout the rest of this manual the 80C152 and the
board multi-protocol communication controller called 83C152 will be referred to generically as the "CI52".
the Global Serial Channel (GSC). The GSC interface
supports SDLC, CSMA/CD, user definable protocols, The C152 is based on the 80C5IBH architecture and
and a subset of HDLC protocols. The GSC capabilities utilizes the same 80C5IBH instruction set. Figure 1.1 is
include: address recognition, collision resolution, CRC a block diagram of the C152. Readers are urged to
generation, flag generation, automatic retransmission, compare this block diagram with the 80C51BH block
and a hardware based acknowledge feature. This high diagram. There have been no new instructions added.
speed serial channel is capable of implementing the All the new features and peripherals are supported by
Data Link Layer and the Physical Link Layer as shown an extension of the Special Function Registers (SFRs).
in the OSI open systems communication model. This Very little of the information pert aining specifically to
model can be found in the document "Reference Model the 80C51BH core will be discussed in this chapter.
.for Open Systems Interconnection Architecture", The detailed information on such functions as: the in-
ISOITC97/SCI6 N309. struction set, port operatioll, timer/counters, etc., can
be found'in the MCS~)-51 Architecture chapter in the
The DMA circuitry consists of two 8-bit DMA chan- Intel Embedded Controller Ilandbook. Knowledge of
nels with 16-bit addressability. The control signals; the 80C51BH is required to fully understand this man-
Read (RD), Write (WR), hold and hold acknowledge ual and the operation of the C 152. To gain a basic un-
(HOLD/HLDA) are used to access external memory. derstanding on the operatioll of the 80C5IBH, the
The DMA channels are capable of addressing up to reader should familiarize hilllself with the entire MCS-
64K bytes (16 bits). The destination or source address 51 chapter of the Embedded Controller Handbook.
can be automatically incremented. The lower 8 bits of
the address are multiplexed on the data bus Port 0 and Another source of information that the reader may find
the upper eight bits of address will be on Port 2. Data is helpful is Intel's LAN Components User's Manual, or-
transmitted over an 8-bit address/data bus. Up to 64K der number 230814. Inside arc descriptions of various
bytes of data may be transmitted for each DMA activa- protocols, application examples, and application notes
tion. dealing with different serial communication environ-
ments.
The new I/O port (P4) functions the same as Ports 1-3,
found on the 80C51BH.
2.0 COMPARISON OF 80C152 AND
Internal memory has been doubled in the 83C152. Data 80C51BH FEATURES
memory has been expanded to 256 bytes, and internal
program memory has been expanded to 8K bytes.
2.1 Memory Space
There are also some specific differences between the
83C152 and the 80C51BH. The first is that the number- A good understanding of the memory space and how it
ing system between the 83C152 and the 80C51BH is is used in the operation of MCS-51 products is essen-
slightly different. The 83C152 and the80C5IBH are tial. All the enhancements on the CI52 are implement-
factory masked ROM devices. The 80C152 and the ed by accessing Special Function Registers (SFRs),
80C31BH are ROMless devices which require the added data memory, or added program memory.
10-3
cl
SARL1
...........
SARH!
.... _....
DARL!
~ I-----II~ARH;
~
BCRLO BCRL!
LAiCH
CD
J}
(0)
(')
.....
UI
~
I\)
c ::r:
)0
; :!3
~ C
~
~
.... m
J: i5'
(')
:0:-
:!3
m
C
j... m
fJ)
(')
DI
3 :!3
=ti
-I
0Z
ADRD-3 Irs
BAUD TCDCNT
P1.0-P1.7 P3.0- P3.7
270427-7
83C152 HARDWARE DESCRIPTION
2.1.1 SPECIAL FUNCTION REGISTERS (SFRs) (IDA), Source Address Space bit (SAS), Increment
Source Address bit (ISA), DMA Channel Mode bit
The following list contains all the SFRs, their names (DM), Transfer Mode bit (TM), DMA Done bit
and function. All of the SFRs of the 80C51 BH are re- (DONE), and the GO bit (GO). DCONO is used to
tained and for a detailed explanation of their operation, control DMA Channel 0.
please refer to the chapter, "Hardware Description of
the 8051 and 8052" that is found in the Embedded DCONI - (93H) Same as DCONO except this is for
Controller Handbook. An overview of the new SFRs is DMA Channel 1.
found in Section 2.1.1.1, with a detailed explanation in
Section 3.7, Section 4.5, and 6.0. GMOD - (84H) Contains the. Protocol bit (PR), the
Preamble Length (PLl,O), CRC Type (CT), Address
Length (AL), Mode select (MI,O), and External Trans-
2.1.1.1 New SFRs mit Clock (TXC). This register is used for GSC opera-
The following descript ions arc quick overviews of the tion only.
new SFRs, and not inlcnded to give a complete under-
lENI - (OCSH) Interrupt enable register forDMA and
standing of their usc. The reader should refer to the GSC interrupts.
detailed explanation in Section 3 for the GSC SFRs,
and Section 4 for the DMA SFRs. IFS - (OA4H) Determines the number of bit times sepa-
rating transmitted frames.
ADR 0,1,2,3 - (95H, OASH, OB5H, OC5H) Contains
the four bytes for address matching during GSC opera- IPNI - (OF8H) Interrupt priority register for DMA
tion. and GSC interrupts.
AMSKO - (OD5H) Selects "don't care" bits to be used MYSLOT - (OF5H) Contains the Jamming mode bit
with ADRO. (DCI), the Deterministic Collision Resolution Algo-
rithm bit (DCR), and the DCR slot address for the
AMSKI - (OE5H) Selects "don't care" bits to be used
GSc.
with ADR1.
P4 - (OCOH) Contains the memory "image" of Port 4.
BAUD - (94H) Contains the programmable value for
the baud rate generator for the GSC. The baud rate will PRBS - (OE4H) Contains a pseudo-random number to
equal (fosc)/«BAUD+ I) X 8). be used in CSMA/CD back off algorithms. May be read
or written to by user software.
BCRLO - (OE2H) Contains the low byte of a count-
down counter that determines when the DMA access RFIFO - (F4H) RI-'IJ'() is llsed to access a 3-byte FIFO
for Channel 0 is complete. that contains the receive data from the GSC.
BCRHO - (OE3H) Contains the high byte for count- RSTAT - (OE8H) Contains the Hardware Based Ac-
down counter for Channel O. knowledge Enable hit (HAllEN), Global Receive En-
able bit (GREN), Receive 1-'11'"0 Not Empty bit
BCRLl - (OF2H) Same as BCRLO except for DMA (RFNE), Receive Done hit (RDN), CRC Error bit
Channell. (CRCE), Alignlllent Error bit (AE), Receiver Colli-
BCRHI - (OF3H) Same as BCRHO except for DMA sion/Abort deled hit «({("AliT), and the Overrun bit
Channell. (OVR), used with both DMA and GSc.
BKOFF - (OC4H) An 8-bit count-down timer used SARLO - (OA211) Contains the low byte of the source
with the CSMA/CD resolution algorithm. address for DMA transfers.
DARLO - (OC2H) Contains the low byte of the destina- SARHO - (OA3H) Contains the high byte of the source
tion address for DMA Channel O. address for DMA transfers.
DARHO - (OC3H) Contains the high byte of the desti- SARLI - (082H) Same as SARLO but for DMA Chan-
nation address for DMA Channel O. nell.
DARLl - (OD2H) Same as DARLO except for DMA SARHI - (OB3H) Same as SARHI but for DMA Chan-
Channell. nell.
DARHI - (OD3H) Same as DARHO except for DMA SLOTTM - (OB4H) Determines the length of the slot
Channell. time in CSMA/CD.
DCONO - (92H) Contains the Destination Address TCDCNT - (OD4H) Contains the number of collisions
Space bit (DAS), Increment Destination· Address bit in the current frame if using CSMA/CD GSc.
10-5
inter 83C152 HARDWARE DESCRIPTION
Old(O)/New(N) Name Addr Function
0 A OEOH ACCUMULATOR
N ADRO 095H GSC MATCH ADDRESS 0
N ADR1 OA5H GSC MATCH ADDRESS 1
N ADR2 OB5H GSC MATCH ADDRESS 2
N ADR3 OC5H GSC MATCH ADDRESS 3
N AMSKO OD5H GSC ADDRESS MASK 0
N AMSK1 OE5H GSC ADDRESS MASK 1
0 B OFOH B REGISTER
N BAUD 094H GSC BAUD RATE
N BCRLO OE2H DMA BYTE COUNT 0 (LOW)
N BCRHO OE3H DMA BYTE COUNT 0 (HIGH)
N BCRL1 OF2H DMA BYTE COUNT 1 (LOW)
N BCRH1 OF3H DMA BYTE COUNT 1 (HIGH)
N BKOFF OC4H GSC BACKOFF TIMER
N DARLO OC2H DMA DESTINATION ADDR 0 (LOW)
N DARHO OC3H DMA DESTINATION ADDR 0 (HIGH)
N DARL1 OD2H DMA DESTINATION ADDR 1 (LOW)
N DARH1 OD3H DMA DESTINATION ADDR 1 (HIGH)
N DCONO 092H DMA CONTROL 0
N DCON1 093H DMA CONTROL 1
0 DPH OS3H DATA POINTER (HIGH)
0 DPL OS2H DATA POINTER (LOW)
N GMOD OS4H GSCMODE
0 IE OA8H INTERRUPT ENABLE REGISTER 0
N IEN1 OC8H INTERRUPT ENABLE REGISTER 1
N IFS OA4H GSC INTERFRAME SPACING
0 IP OB8H INTERRUPT PRIORITY REGISTER 0
N IPN1 OF8H INTERRUPT PRIORITY REGISTER 1
N MYSLOT OF5H GSC SLOT ADDRESS
0 PO OSOH PORTO
0 P1 090H PORT 1
0 P2 OAOH PORT 2
0 P3 OBOH PORT 3
N P4 OCOH PORT 4
N P5 091H PORT 5
N P6 OA1H PORT 6
0 PCON 087H . POWER CONTROL
N PRBS OE4H GSC PSEUDO-RANDOM SEQUENCE
0 PSW ODOH PROGRAM STATUS WORD
N RFIFO OF4H GSC RECEIVE BUFFER
N RSTAT OE8H RECEIVE STATUS (OM A & GSC)
N SARLO OA2H DMA SOURCE AD DR 0 (LOW)
'N SARHO OA3H DMA SOURCE AD DR 0 (HIGH)
N SARL1 OB2H DMA SOURCE ADDR 1 (LOW)
N SARH1 OB3H DMA SOURCE ADDR 1 (HIGH)
0 SBUF 099H LOCAL SERIAL-CHANNEL (LSC) BUFFER
0 SCON 098H LOCAL SERIAL CHANNEL (LSC) CONTROL
N SLOTTM OB4H GSC SLOT TIME
0 SP 081H STACK POINTER
N TCDCNT OD4H GSC TRANSMIT COLLISION COUNTER
0 TCON ·08SH TIMER CONTROL
N TFIFO 085H GSC TRANSMIT BUFFER
0 THO 08CH TIMER 0 (HIGH)
0 TH1 08DH TIMER 1 (HIGH)
0 TLO 08AH TIMER 0 (LOW)
0 TL1 OSBH TIMER 1 (LOW)
0 TMOD 089H TIMER MODE
N TSTAT OD8H TRANSMIT STATUS (OM A & GSC)
10-6
inter 83C152 HARDWARE DESCRIPTION
TFIFO - (85H) TFIFO is used to access a 3-byte FIFO The addresses of the second !28 bytes of data memory
that contains the transmission data for the GSC. happen to overlap the SFR addresses. The SFRs and
their memory locations are shown in Figure 2.2. This
TSTAT - (OD8H) Contains the DMA Service bit means that internal data memory spaces have the same
(DMA), Transmit Enable bit (TEN), Transmit FIFO address as the SFR address. However, each type of
Not Full bit (TFNF), Transmit Done bit (TDN), memory is addressed differently. To access data memo-
Transmit Collision Detect bit (TCDT), Underrun bit ry above 80H, indirect addressing or the DMA chan-
(DR), No Acknowledge bit (NOACK), and the Re- nels must be used. To access the SFRs, direct address-
ceive Data Line Idle bit (LNI). This register is used ing is.used. When direct addressing is used, the address
with both DMA and GSc. is the source or destination, e.g. MOV A, lOH, moves
the contents of location lOH into the accumulator.
The general purpose flag bits (GFO and GFl) that exist When indirect addressing is used, the address of the
on the 80C5lBH are no longer available on the Cl52. destination or source' exists within another register, e.g.
GFO has been renamed GFIEN (GSC Flag Idle En- MOV A, @RO. This instruction moves the contents of
able) and is used to enable idle fill flags. Also GF! has the memory location addressed by RO into the accumu-
been renamed XRCLK (External Receive Clock En- lator. Directly addressing the locations 80H to OFFH
able) and is used to enable the receiver to be clocked will access the SFRs. Another form of indirect address-
externally. ing is with the use of Stack Pointer Operations. If the
Stack Pointer contains an address and a PUSH or POP
2.1.2 DATA MEMORY instruction is executed, indirect addressing is actually
used. Directly accessing an unused SFR address will
Internal data memory consists of 256 bytes as shown in give undefined results.
Figure 2.1. The first 128 bytes are addressed exactly
like an SOCSI BH, using direct addressing. Physically, there are separate SFR memory and data
memory spaces allocated on the chip. Since there are
separate spaces, the SFRs do not diminish the available
data memory space.
OFFH onlt
V
(.)
OVERLAPPING.
MEMORY
ADDRESSES
~(.)
SPECIAL FUNCTION REGISTER
SPACE
080H
(.)
02FH
BIT ADDRESSABLE
MEMORY SPACE
020H
01FH
REGISTER BANK 3
017H
REGISTER BANK 2
010H
REGISTER BANK 1
007H
REGISTER BANK 0
OOOH
USER DATA MEMORY SPACE 270427-1
'NOTE:. .
User data memory above BOH must be addressed indirectly. Using direct addressing above BOH accesses the SpeCial
Function Registers.
Figure 2.1. Data Memory Map
10-7
inter 83C152 HARDWARE DESCRIPTION
External data memory is accessed like an 80C5lBH, 2.1.2.1 Bit Addressable Memory
with "MOVX" instructions. Addresses up to 64K may
be accessed when using the Data Pointer (DPTR). The Cl52 has several memory spaces in which the bits
When accessing external data memory with the DPTR,. are directly addressed by their location. The directly
the address appears on Port 0 and 2. When using the addressable bits and their symbolic names are shown in
DPTR, if less than 64K of external data memory is Figure 2.3A, 2.3B, and 2.3C.
used, the address is emitted on all sixteen pins. This
means that when using the DPTR, the pins of Port 2 Bit addresses () to 7FH reside in on-board user data
not used for addresses cannot be used for general pur- RAM in bytl! addresses 20H to 2FH (see Figure 2,JA).
pose I/O. An alternative to using 16-bit addresses with
the DPTR is to use RO or RIta address the external Bit addresses HOH to OFFH reside in the SFR memory
data memory. When using the registers to address ex- space, but 11(11 every SFR is bit addressable, sec Figure
ternal data memory, the address range is limited to 256 2.3B. The addressable bits are scattered throughout the
bytes. However, software manipulation of I/O Port 2 SFRs. The addressable bits occur every eighth SFR ad-
pins as normal I/O, allows this 256 bytes restriction to dress starting at SOH and occupy the entire byte. Most
be expanded via bank switching. When using RO or RI of the bits that are addressable in the SFRs have been
as data pointers, Port 2 pins that arc not used for ad- given symbolic names. These names will often be reo
dressing, can be used as general purpose I/O. ferred to in this or other documentation on the C152.
Most assemblers also allow the use of the symbolic
names when writing in assembly language. These
names arc shown in Figure 2.3C.
(')IPN 1 PGSTE PDMA1 PGSTV I'Ot.!AO PGSRE PGSRV OfSH AOR2 0 BSH
'I. 'II. 'I I I 1.'1I. 'I I I I. 'III. 'III. SLOTIt.! 0B4H
MYSLOT OCJ OCR SA5 SA4 SA3 SA2 SAl SAO Of5H SARin 0 B3H
RflfO Of4H SARLI 0 B2H
BCRH 1 Of3H 'I. 'II. 'I. '77 '77 '777
BCRL 1 Of2H (')P3 RD WR T1 TO INTI INTO TXD RXD 0 BaH
'1.'1. 'II. 'II. 'III. 'I. 'I. 'II. '111.'111. fl. 'I. 'II. '77 rl7.
(')B OfOH (')IE EA ES ET1 EXt ETO EXO 0ASH
'I.
'I 'II. 'II. 'I
(')RSTAT OVR RCABT AE CRCE RON RrHE GREN HABEN OEBH ADRt 0ASH
'I. 'I. 'I. 'I. IfS OMH
AMSK 1 OESH SARHO OA3H
'III. 'II. 'II. 'III. 'I I I. 'I I I I. 'I. SARLO 0A2H
PRBS OE4H P6 0AtH
BCRHO OE3H (')P2 0AOH
BCRLO OE2H '777 711. 7T17. 'I I I I. '77 '777 '77
'I. SBUf 099H
(')A OEOH (')SCON SMO SMt SM2 REN TB8 RBS n RI098H
'III. 'I. ADRO 095H
(')TSTAT LNI NOACK UR TCDT TON lfNr TEN DMA OOSH BAUD 094H
'III. 'II. 'I. 'II. '1111. 'II. OCONt DAS lOA SAS ISA OM 1M CONE GO 093H
At.fSKO OOSH OCONO DAS lOA SAS ISA OM 1M CONE GO 092H
TCDCN T OD4H P5 09tH
DARH 1 OD3H (·)pt HLOA HLO !fie m !l[Jii GTXD GRXD 090H
DARL 1 OD2H 'II. 'III. 'I. 'I.
'III. 'II. 'II. 'I. '1,'11.'11 I I. 'III. THt 08DH
(.)psw Cf AC fO RSI RSO OV P OCOH THO 08CH
'I. '/1. 'I. 'I. 'I. 'III. 'II. TLt OSBH
(')IEN 1 EGSTE EDMAI EGSTV EDMAO EGSRE EGSRV OCSH TLO OaAH
'I. 1MOD GATE C loll MO GATE C Mt MO 089H
ADR3 OCSH (')TCON lft TRt lfO TRO lEt IT1 lEO ITO 088H
BKonr DC4H PCON SMOD ARB REQ GAREN XRCLK GfIEN PO IDL OS7H
DARHO DC3H (I fl I fill 'III fill fill 'III
DARLO OC2H lfIfO 08SH
'I GMOD IXTCLK Mt MO AL CT PL1 PLO PR OS4H
(')P4 DCOH DPH OS3H
DPL 082H
(')IP PS PTI PXl PTO PXO OB8H SP OStH
fl fl fI 'III 'II 'II (')PO OSOH
270427-2
• =BIT ADDRESSABLE
270427-3
Figure 2.2. Special Function Registers
10-8
intJ 83C152 HARDWARE DESCRIPTION
Data Memory Map (bits):
Byte BIT ADDRESSES
Address (MSB) (LSB)
020H 07 06 05 04 03 02 01 00
021H OF OE 00 OC 08 OA 09 08
022H 17 16 15 14 13 12 11 10
023H 1F 1E 10 1C 18 1A 19 18
024H 27 26 25 24 23 22 21 20
025H 2F 2E 20 2C 28 2A 29 28
026H 37 36 35 34 33 32 31 30
027H 3F 3E 3D 3C 38 3A 39 38
028H 47 46 45 44 43 42 41 40
029H 4F 4E 40 4C 48 4A 49 48
02AH 57 56 55 54 53 52 51 50
028H 5F 5E 50 5C 58 5A 59 58
02CH 67 66 65 64 63 62 61 60
020H 6F 6E 60 6C 68 6A 69 68
02EH 77 76 75 74 73 72 71 70
02FH 7F 7E 70 7C 78 7A 79 78
Figure 2.3A. Bit Addresses
Byte BIT ADDRESSES
Address (MSB) (LSB)
080H 87 86 85 84 83 82 81 flO (PO)
--
088H 8F 8E 80 8C 88 8A 89 88 (TCON)
--'-
090H 97 96 95 94 93 92 91 90 (P1)
------
098H 9F 9E 90 9C 98 9A 99 98 (SCON)
---
OAOH A7 A6 A5 A4 A3 A2 A1 AO (P2)
OA8H AF - - AC A8 AA A'J A8 (IE)
080H 87 86 85 84 83 82 81 80 (P3)
088H - - - 8C 88 8A 89 88 (IP)
OCOH C7 C6 C5 C4 C3 C2 C1 CO (P4)
OC8H - - CO CC C8 CA C9 C8 (lEN1)
OOOH 07 06 05 04 03 02 01 DO (PSW)
008H OF DE DO DC 08 OA 09 08 (TSTAT)
OEOH E7 E6 E5 E4 E3 E2 E1 EO (A)
OE8H EF EE ED EC E8 EA E9 E8 (RSTAT)
OFOH F7 F6 F5 F4 F3 F2 F1 FO (8)
OF8H - - FO FC F8 FA F9 F8 (IPN1)
Figure 2.3B. Bit Addresses
10-9
intJ 83C152 HARDWARE DESCRIPTION
Byte SYMBOLIC NAME BIT MAP
Address (MSB) (LSB)
080H PO.? PO.6 . PO.5 PO.4 PO.3 PO.2 PO.1 PO.O (PO)
088H TF1 TA1 TFO TAO IE1 IT1 lEO ITO (TCON)
090H P1.? P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.q (P1)
098H SMO SM1 SM2 AEN TB8 AB8 TI AI (SCON)
OAOH P2.? P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 (P2)
OA8H EA - - ES ET1 EX1 ETO EXO (IE)
OBOH P3.? P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 (P3) .
OB8H - - - PS PT1 PX1 PTO PXO (IP)
OCOH P4.? P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0 (P4)
OC8H - - EGSTE EOMA1 EGSTV EOMAO EGSAE EGSAV (IEN1 )
OOOH CY AC FO AS1 RSO
-
OV - P (PSW)
008H LNI NOACK UA TCOT TON TFNF TEN OMA (TSTAT)
OEOH (A)
OE8H OVA ACABT AE CACE AON RFNE GAEN HABEN (RSTAT)
OFOH (B)
OF8H - - PGSTE POMA1 PGSTV POMAO PGSAE PGSAV (IPN1)
Figure 2.3C. Bit Addresses
2.1.3 PROGRAM MEMORY
The 83C152 contains 8K of ROM program memory, . - - - - - - - - - , FF'FFH
and the 80C152 uses only external program memory.
Figure 2.4 shows the program memory locations and
where they reside. The user is allowed a maximum of EXTERNAL
64K of program memory. In the H3C152 program
memory fetches beyond 8K automatically access exter-
nal program memory. When program memory is exter-
nally addressed, all of the Port 2 pins emit the address.
Since all of Port 2 is affected by the address, unused
address pins cannot be used as normal 1/0 ports even if
less than 64K of memory is being accessed.
1---------1 lFFFH
EXTERNAL IF EA =0
INTERNAL IF EA =1
~--------' OOOOH
270427-4
Figure 2.4. Program Mem~ry
10-10
83C152 HARDWARE DESCRIPTION
2.2 Interrupt Structure interrupts and IPN! (FSH) for setting the priority. For
an explanation on how the priority of interrupts affects
The C I 52 retains all five interrupts of the SOC5IBH. In their operation please refer to the MCS-5! Architecture
addition, six new interrupts have been added for a total and Hardware Chapters in the Intel Embedded Con-
of II available interrupts. Two SFRs have been added troller Handbook. A detailed description on how the
to the C 152 for control of the new interrupts. These interrupts function is in the MCS®-5! Architectural
added SFRs are lEN! (CSH) for enabling the Overview.
IEN1 FUNCTIONS
Symbol Position Vector Function
- IEN1.7 RESERVED and do not exist on chip.
- IEN1.6 RESERVED and do not exist on chip.
EGSTE IEN1.5 04BH GSC TRANSMIT ERROR-The interrupt service routine at
4BH is invoked if NOACK or TCDT is set when the GSC is
under CPU control and EGSTE is enabled. This interrupt
service routine is invoked if NOACK, TCDT, or UR is set when
the GSC is under DMA control and EGSTE is enabled.
EDMA1 IEN1,4 053H DMA CHANNEL REQUEST 1-The interrupt service routine
at 53H is invoked when DCON1.1 (DONE) is set and EDMA1
is enabled.
EGSTV IEN1.3 043H GSC TRANSMIT VALID-The interrupt service routine at 43H
is invoked if TFNF is set when the GSC is under CPU control
and EGSTV is enabled. This interrupt service routine is
invoked if TON is set when the GSC is under DMA control and
EGSTV is enabled.
EDMAO IEN1.2 03BH DMA CHANNEL REQUEST 0-The interrupt service routine
at 3BH will be invoked when DCONO.1 (DONE) is set and
EDMAO is enabled.
EGSRE IEN1.1 033H GSC RECEIVE ERROR-The interrupt service routine at 33H
is invoked if CRCE, OVR, RCABT, or AE is set when the GSC
is under CPU or DMA control and EGSRE is enabled.
EGSRV IEN1.0 02BH GSC RECEIVE VALID-The interrupt service routine at 2BH
is invoked if RFNE is set when the GSC is under CPU control
and EGSRV is enabled. This interrupt service routine is
invoked if RON is set when the GSC is under DMA control and
EGSRV is enabled.
IPN! is used the same way the current SOC5!BH interrupt priority register (IP) is. By assigning a "I" to the
appropriate bit, that interrupt has a higher priority than an interrupt with a "0" assigned to it in the priority register.
The new interrupt priority register (IPN 1) contents are:
Symbol Position Function
PGSTE IPN1.5 GSC TRANSMIT ERROR
PDMA1 IPN1,4 DMA CHANNEL REQUEST 1
PGSTV IPN1.3 GSC TRANSMIT VALID
PDMAO IPN1.2 DMA CHANNEL REQUEST 0
PGSRE IPN1.1 GSC RECEIVE ERROR
PGSRV IPN1.0 GSC RECEIVE VALID
10-11
inter 83C152 HARDWARE DESCRIPTION
The eleven interrupts are sampled in the following order when assigned the same priority level in the IP and IPNI
registers:
Priority Priority Interrupt Interrupt
Priority Symbolic Symbolic Symbolic SymboliC Vector
Sequence Address Name Address Name Address
1 IP.D PXO lE.O EXO 03H (FIRST)
2 IPN1.0 PGSRV IEN1.0 EGSRV 2BH
3 IP.1 PTO IE.1 ETO OBH
4 IPN1.1 PGSRE IEN1.1 EGSRE 33H
5 IPN1.2 PDMAO IEN1.2 EDMAO 3BH
6 IP.2 PX1 IE.2 EX1 13H
7 IPN1.3 PGSTV IEN1.3 EGSTV 43H
8 IPN1.4 PDMA1 IEN1.4 EDMA1 53H
9 IP.3 PT1 IE.3 ET1 1BH
10 IPN1.5 PGSTE IEN1.5 EGSTE 4BH
11 IP.4 PS lEA ES 23H (LAST)
2.3 Reset
RESET performs the same operations in both the 80C51B1l and the Cl52 and those conditions that exist at the end
of a valid RESET are:
Register Contents Register Contents
ACC OOH PO-P6 OFFH
ADRO-3 OOH PCON OXXXOOOOB
AMSKO OOH PRBS OOH
AMSK1 OOH PSW OOH
B OOH RFIFO INDETERMINATE
BAUD OOH RSTAT OOOOOOOOB
BCRHO INDETERMINATE SARHO INDETERMINATE
BCRH1 INDETERMINATE SARH1 INDETERMINATE
BCRLO INDETERMINATE SARLO INDETERMINATE
CRL1 INDETERMINATE SARL1 INDETERMINATE
BKOFF INDETERMINATE SBUF INDETERMINATE
DARHO INDETERMINATE SCON OOH
DARH1 INDETERMINATE SLOTTM OOH
DARLO INDETERMINATE SP 07H
DARL1 INDETERMINATE TCDCNT INDETERMINATE
DCONO OOH TCON OOH
DCON1 OOH TFIFO INDETERMINATE
DPTR OOOOH THO OOH
GMOD XOOOOOOOB TH1 OOH
IE OXXOOOOOB TLO OOH
IEN1 XXOOOOOOB TL1 OOH
IFS OOH TMOD OOH
IP XXXOOOOOB TSTAT XXOO0100B
IPN1 XXOOOOOOB PC OOOOH
MYSLOT OOOOOOOOB
10-12
intJ 83C152 HARDWARE DESCRIPTION
The same conditions apply for both the 80C5lBH and to the Intel Embedded Controller Handbook which de-
CI52 for a correct reset pulse or "power-on" reset ex- scribes the timer/counters and their use. The user
cept that Reset is active low on the C 152. Please refer should bear in mind, when reading the Intel Embedded
to the 8051/52 Hardware Description Chapter of the Controller Handbook that the C152 does not have the
Intel Embedded Controller Handbook for an explana- third event timer named Timer 2, which is in the 8052.
tion on how to provide a proper power-on reset. Since
Reset is active low on the C152, the resistor should be 2.6 Package
tied to VCC and the capacitor should be tied to VSS.
The 83C152 is packaged in a 48 pin DIP and a 68 lead
Because the clocking on part of the GSC circuitry is PLCe. This differs from the 40 pin DIP and 44 pin
independent of the processor clock, data may still be PLCC of the 80C5 lBH. _The larger package is required
transmitted and DEN active for some time after reset is
applied. The transmission may continue for a _maxi-
mum of four machine cycles after reset is first pulled
low. Although Reset has to be held low for only three
machine cycles to be recognized by the GSC hardware,
to accommodate the extra 8 bit I/O port (P4). Figures
2.5A, 2.5B and 2.5C show the packages and the pin
names. -II
all of the GSC circuitry may not be reset until four (GRXD) PLO vee
machine cycles have passed. If it is important in the (GTXO) Pl.l P4.0
user application that all transmission and DEN be· (DEN) Pl.2 P4.1
comes inactive at the end of a reset, then Reset will
(TXC) Pl.3 P4.2
have to be held low for a minimum of four machine
(RXC) Pl.4 P4.3
cycles.
(HLD) Pl.5 P4.4
2.4 Ports 4, 5 and 6 (HLOA) Pl.6 P4.5
P1.7 P4.6
Ports 4, 5 and 6 operation is identical to Ports 1-3 on
RESET P4.7
the 80C51BH. The description of port operation can be
found in the 8051/52 Hardware Description Chapter of (RXO) P3.0 EA
the Intel Embedded Controller Handbook. Ports 5 and (TXO) P3.1 ALE
6 exist only on the "JB" and "JD" version of the C152 (INTO) P3.2 PSEN
and can either function as standard I/O ports or can be (INTI ) P3.3 P2.7 (AI5)
configured so that program memory fetches are per- (TO) P3.4 P2.6 (AU)
formed with these two ports. To configure ports 5 and 6 (Tl) P3.5 P2.5 (AI3)
as standard I/O ports, EBEN is tied to a logic low.
(WR) P3.6 P2.4 (AI2)
When in this configuration, ports 5 and 6 operation is
identical to that of port 4 except they are not bit ad- (Ri5) P3.7 P2.3 (All)
dressable. To configure ports 5 and 6 to fetch program (A/DO) PO.O P2.2 (AID)
memory, EBEN is tied to a logic high. When using (A/Ol) PO.1 P2.1 (AS)
ports 5 and 6 to fetch the program memory, the signal (A/D2) PO.2 P2.0 (AB)
EPSEN is used to enable the external memory device (A/03) PO.3 PO.7 (A/D7)
instead ofPSEN. Regardless of which ports are used to XTAL2 PO.6 (A/D6)
fetch program memory, all data memory fetches occur. XTALl PO.5 (A/D5)
over ports 0 and 2. The 80C152JB and 80C152JD are
available as ROMless devices only. ALE is still used to vss PO.4 (A/04)
latch the address in all configurations. Table 2.1 sum- 270427-5
marizes the control signals and how the ports may be
used. Figure 2.SA. DIP Pin Out
2.5 Timer/Counters
The 80C5lBH and C152 have the same pair of l6-bit
general purpose timer/counters. The user should refer
Table 2.1 Program Memory Fetches
Program
EBEN EA PSEN EPSEN Comments
Fetch via
0 0 PO,P2 Active Inactive Addresses O-OFFFFH
0 1 N/A N/A N/A Invalid Combination
1 0 P5, P6 Inactive Active Addresses O-OFFFFH
1 1 P5,P6 Inactive Active Addresses 0-1 FFFH
PO,P2 Active Inactive Addresses 2 2000H
10-13
inter 83C152 HARDWARE DESCRIPTION
P4,5
P4.6
N.C. P4.7
RESET N.C.
P3.0 14
,P3.1 ALE (TOP VIEW)
PSEN
N.C. BOC152JB
80C 152JA/JC N.C. 80C152JD
P3.4 83C152JA/JC
N.C. N.C.
N.C. N.C.
P2.7
N.C, P2.7 P3.S P2.6
P3.S P2.6 P3.6 P2.S
P3.6 P2.S P3.7 P2.4
P3.7 P2.4 N.C. P2.3
N.C. P2.3
270427-37
270427-6
Figure 2.58. PLCC Pin Out Figure 2.SC. PLCC Pin Out
2.7 Pin Description
The pin description for the 80C51B1l also applies to the C152 and is lisled below. Changes have been made to the
descriptions as they apply to the C 152.
PIN DESCRIPTION
Pin #
Description
DIP PLCC(1)
48 2 Vee-Supply voltage.
24 3,33(2) VSS-Circuit ground.
18-21, 27-30, Port O-Port 0 is an 8-bit open drain bi-directional 1/0 port. As an output port each
25-28 34-37 pin can sink 8 LS TTL inputs. Port 0 pins that have 1s written to them float, and in
that state can be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and data bus during accesses to
external program memory if EBEN is pulled low. During accesses to external Data
Memory, Port 0 always emits the low-order address byte and serves as the
multiplexed data bus. In these applications it uses strong internal pullups when
emitting 1s.
Port 0 also outputs the code bytes during program verification. External pullups are
required during program verification.
NOTES:
1. N.C. pins on PLCC package may be connected to internal die and should not be used in customer applications.
2. It is recommended that both Pin 3 and Pin 33 be grounded for PLCC devices.
10-14
intJ 83C152 HARDWARE DESCRIPTION
PIN DESCRIPTION (Continued)
Pin #
Description
DIP PLCC(1)
1-8 4-11 Port 1-Port 1 is an 8-bit bidirectional 110 port with internal pullups. Port 1 pins that
have 1 s written to them are pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 1 pins that are externally being pulled low will
source current (IlL, on the data sheet) because of the internal pullups.
Port 1 also serves the functions of various special features of the 8XC152, as listed
below:
Pin Name Alternate Function
P1.0 GRXD GSC data input pin
P1.1 GTXD GSC data output pin
Pt.2 DEN GSC enable signal for an external driver
P1.3 TXC GSC input pin for external transmit clock
P1.4 RXC GSC input pin for external receive clock
P1.5 HLD DMA hold input/output
P1.6 HLDA DMA hold acknowledge input/output
29-36 41-48 Port 2-Port 2 is an 8-bit bi-directionalllO port with internal pullups. Port 2 pins that
have 1s written to them are pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 2 pins that are externally being pulled low will
source current (IlL, on the data sheet) because of the internal pull ups.
Port 2 emits the high-order address byte during fetches from external Program
Memory if EBEN is pulled low. During accesses to external Data Memory that use
16-bit addresses (MOVX @ DPTR and DMA operations), Port 2 emits the high-order
address byte. In these applications it uses strong internal pull ups when emitting 1s.
During accesses to external Data Memory that use 8-bit address os (MOVX @ Ri),
Port 2 emits the contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits during program vorification.
10-17 14-16, Port 3-Port 3 is an 8-bit bi-directionall/O port with internal pullups. Port 3 pins that
18,19, have 1 s written to them are pulled high by the internal pullups, and in that state can
23-25 be used as inputs. As inputs, Port 3 pins that are externally boin~J pulled low will
source current (IlL, on the data sheet) because of the pullups.
Port 3 also serves the functions of various special featuros of tho MCS-51 Family,
as listed below:
._---_.--
Pin Name Alternate Function
P3.0 RXD Serial input line
P3.1 TXD Serial output line
P3.2 INTO External interrupt 0
P3.3 INT1 External interrupt 1
P3.4 TO Timer 0 external input
P3.5 T1 Timer 1 external input
P3.6 WR External Data Memory Write strobe
P3.7 RD External Data Memory Read strobe
47-40 65-58 Port 4-Port 4 is an 8-bit bi-directionall/O port with internal pullups. Port 4 pins that
have 1s written to them are pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 4 pins that are externally being pulled low will
source current (IlL, on the data sheet) because of the internal pullups. In addition,
Port 4 also receives the low-order address bytes during program verification.
NOTES:
1. N.C. pins on PLCC package may be connected to internal die and should not be used in customer applications.
2. It is recommended that both Pin 3 and Pin 33 be grounded for PLCC devices.
10-15
83C152 HARDWARE DESCRIPTION
PIN DESCRIPTION (Continued)
Pin #
Description
DIP PLCC(1)
9 13 RST-Reset input. A logic Iowan this pin for three machine cycles while the
oscillator is running resets the device. An internal pullup resistor permits a power-
on reset to be generated using only an external capacitor to VSS. Although the GSC
recognizes the reset after three machine cycles, data may continue to be
transmitted for up to 4 machine cycles after Reset is first applied.
38 55 ALE-Address Latch Enable output signal for latching the low byte of the address
during accesses to external memory.
In normal operation ALE is emitted at a constant rate of % the oscillator frequency,
and may be used for external timing or clocking purposes. Note, however, that one
ALE pulse is skipped during each access to external Data Memory. While in Reset,
ALE remains at a constant high level.
37 54 PSEN-Program Store Enable is the Read strobe to External Program Memory.
When ttle 8XC152 is executing from external program memory, PSEN is active
(low). When the device is executing code from External Program Memory, PSEN is
activated twice each machine cyclo, except that two PSEN activations are skipped
during each access to External Data Memory. While in Reset, PSEN remains at a
constant high level.
39 56 EA-External Access enable. EA must be externally pulled low in order to enable
the 8XC152 to fetch code from External Program Memory locations OOOOH to
OFFFH.
EA must be connected to Vcc for internal program execution.
23 32 XTAL I-Input to the inverting oscillator amplifier and input to the internal clock
generating circuits.
22 31 XTAL2-0utput from the oscillator amplifier.
N/A 17,20 Port 5-Port 5 is an 8-bit bi-directionall/O port with internal pullups. Port 5 pins
21,22 that have 1s written to them are pulled high by the internal pullups, and in that state
38,39 can be used as inputs. As inputs, Port 5 pins that are externally being pulled low will
40,49 source current (IlL, on the data sheet) because of the internal pullups.
Port 5 is also the multiplexed low-order address and data bus during accesses to
external program memory if ~BEN is pulled high. In this application it uses strong
pull ups when emitting 1s.
N/A 67,66 Port 6-Port 6 is an 8-bit bi-directionall/O port with internal pullups. Port 6 pins
52,57 that have 1s written to them are pulled high by the internal pullups, and in that state
50,68 can be used as inputs. As inputs, Port 6 pins that are externally pulled low will
1,51 source current (ilL, on the data sheet) because of the internal pull ups.
Port 6 emits the high-order address byte during fetches from external Program
Memory if EBEN is pulled high. In this application it uses strong pullups when
,
emitting 1s.
N/A 12 EBEN-E-Bus Enable input that designates whether program memory fetches take
place via Ports 0 and 2 or Ports 5 and 6. Table 2.1 shows how the ports are used in
conjunction with EBEN.
53 EPSEN-E-bus Program Store Enable is the Read strobe to external program
memory when EBEN is high. Table 2.1 shows when EPSEN is used relative to
PSEN depending on the status of EBEN and EA.
NOTES:
1. N.C. pins on PLCC package may be connected to internal die and should not be used in customer applications.
2. It is recommended that both Pin 3 and Pin 33 be grounded for PLCC devices.
10-16
inter 83C152 HARDWARE DESCRIPTION
2.8 Power Down and Idle 2.9 Local Serial Channel
Both of these operations function identically as in the The Local Serial Channel (LSC) is the name given to
80C51BH. Application Note 252, "Designing with the the UART that exists on all MCS-51 devices. The
80C5IBH" gives an excellent explanation on the use of LSC's function and operation is exactly the same as on
the reduced power consumption modes. Some of the the 80C51 BH. For a description on the use of the LSC,
items not covered in AP-252 are the considerations that refer to the 8051/52 Hardware Description Chapter in
are applicable when using the GSC or DMA in con- the Intel Embedded Controller Handbook, under Serial
junction with the power saving modes. Interface.
The GSC continues to operate in Idle as long as the
interrupts are enabled. The interrupts need to be en- 3.0 GLOBAL SERIAL CHANNEL
abled, so that the CPU can service the FIFO's. In order
to properly terminate a reception or transmission the
C152 must not be in idle when the EOF is transmitted 3.1 Introduction
or received. After servicing the GSC, user software will
need to again invoke the Idle command as the CPU The Global Serial Channel (GSC) is a multi-protocol,
does not automatically re-enter the Idle mode after high performance serial interface targeted for data rates
servicing the interrupts. up to 2 MBPS with on-chip clock recovery, and 2.4
MBPS using the external clock options. In applications
The GSC does not operate while in Power Down so the using the serial channel, the GSC implements the Data
steps required prior to entering Power Down become Link Layer and Physical Link Layer as described in the
more complicated. The sequence when entering Power ISO reference model for open systems interconnection.
Down and the status of the I/O is of major importance
in preventing damage to the C152 or other components The GSC is designed to meet the requirements of a
in the system. Since the only way to exit Power Down wide range of serial communications applications and is
is with a Reset, several problem areas become very sig- optimized to implement Carrier-Sense Multi-Access
nificant. Some of the problems that merit careful con- with Collision Detection (CSMA/CD) and Synchro-
sideration are cases where the Power Down occurs dur- nous Data Link Control (SDLC) protocols. The GSC
ing the middle of a transmission, and the possibility architecture is also designed to provide flexibility in de-
that other stations are not or cannot enter this same fining non-standard protocols. This provides the ability
mode. The state of the GSC I/O pins becomes critical to retrofit new products into older serial technologies,
and the GSC status will need to be saved before power as well as the development of proprietary interconnect
down is entered. There will also need to be some meth- schemes for serial backplane environments.
od of identifying to the CPU that the following Reset is
probably not a cold, start and that other stations on the The versatility of the GSC is demonst rated by the wide
link may have already been initialized. range of choices available to t he user. The various
modes of operation are sUlIlInarizcd in Table 3.1. In
The DMA circuitry stops operation in both Idle and subsequent sections, each available choice of operation
Power Down modes. Since operation is stopped in both will be explained in deta il.
modes, the process should be similar in each case. Spe-
cific steps that need to be taken include: notification to In using Table 3.1, the parameters listed vertically (on
other devices that DMA operation is about to cease for the left hand side) represent an option that is selected
a particular station or network, proper withdrawal (X). The parameters listed horizontally (along the top
from DMA operation, and saving the status of the of the table) arc alit he parameters that could theoreti-
DMA channels. Again, the status of the I/O pins dur- cally be selected (Y). The symbol at the junction of
ing Power Down needs careful consideration to avoid both X and Y determines the applicability of the option
damage to the C152 or other components. Y.
Port 4 returns to its input state, which is high level Note, that not all combinations are backwards compati-
using weak pullup devices. ble. For example, Manchester encoding requires half
duplex, but half duplex does not require Manchester
encoding.
10-17
inter 83C152 HARDWARE DESCRIPTION
Table 3.1
AVAILABLE
OPTIONS
- M
DATA
ENCODING
N N
FLAGS
0 1 N
CRC
1 3 H
DU·
PLEX
F
ACKNOW·
N
LEDGE
H U
ADDRESS
N
RECOG·
NITION
8 1
BACKOFF
N A D N
PRE·
AMBLE
8
A R R 1 1 0 6 2 A U 0 A S 0 B 6 0 L E 0 B
N~ NOT AVAILABLE N Z Z 1 I N B B L L N R E N I B R T T N I
M~MANDATORY C I 1 I E I I F L E D R E T I M E E E T
O~OPTIONAL H 1 D T T W D I T A R R
P ~ NORMALLY PREFERRED E 1 L C A A E A L N M
X~N/A S 1 E C U R F L A I
T 0 I T E I L T N
E T 0 N E I
R E S
D T
SELECTED I
! FUNCTION C
DATA ENCODING:
MANCHESTER(CSMAlCD) X N N 1 P 1 0 0 M N 0 0 0 0 0 0 0 0 0 N 0
NRZI (SDLC) N x N P 1 1 0 0 0 0 0 N P 0 0 0 N N N 0 0
NRZ (EXT CLK) N N X 0 0 1 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0
FLAGS:01111110 (SDLC) N P 0 X 1 1 0 0 0 0 0 N P 0 0 0 N N N 0 0
1111DLE P N 0 1 X 1 0 0 0 N 0 0 0 0 0 0 0 0 0 1 0
CRC:NONE 1 1 1 1 1 X N N 1 N 1 1 1 1 1 1 N N N 1 1
16-BIT CCITT 0 0 0 0 0 N X N 0 0 0 0 0 0 0 0 0 0 0 0 0
32-BIT AUTO DIN II 0 0 0 0 0 N N X 0 N 0 0 0 0 0 0 0 0 0 0 0
DUPLEX:HALF 0 0 0 0 0 1 0 0 X N 0 0 0 0 0 0 0 0 0 0 0
FULL N 0 0 M N N M N N X 0 N P 0 0 0 N N N 0 0
ACKNOWLEDGEMENT:NONE 0 0 0 0 0 1 0 0 0 0 X N N 0 0 0 0 0 0 0 0
HARDWARE 0 N N N 0 1 0 0 0 N N X N 0 0 0 N 0 0 N 0
USER DEFINED 0 P 0 0 0 1 0 0 0 P N N X 0 0 0 0 0 0 0 0
ADDRESS RECOGNITION:
NONE/ALL 0 0 0 0 0 1 0 0 0 0 0 0 0 X N N 0 0 0 0 0
8-BIT 0 0 0 0 0 1 0 0 0 0 0 0 0 N X N 0 0 0 0 0
16-BIT 0 0 0 0 0 1 0 0 0 0 0 0 0 N N X 0 0 0 0 0
COLLISION RESOLUTION:
NORMAL 0 N 0 N 0 N 0 0 M N 0 N 0 0 0 0 X N N N 0
ALTERNATE 0 N 0 N 0 N 0 0 M N 0 0 0 0 0 0 N X N N 0
DETERMINISTIC 0 N 0 N 0 N 0 0 M N 0 0 0 0 0 0 N N X N 0
PREAMBLE:NONE N 0 0 0 1 1 0 0 0 0 0 N 0 0 0 0 N N N X N
8-BIT 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 N X
32-BIT 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 N N
64-BIT 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 N N
JAM:D.C. M N N N 0 N 0 0 M N 0 0 0 0 0 0 0 0 0 N 0
CRC M N N N 0 N 0 0 M N 0 0 0 0 0 0 0 0 0 N 0
CLOCKING:EXTERNAL N M N 0 0 N 0 0 0 0 0 N 0 0 0 0 N N N 0 0
INTERNAL .0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CONTROL: CPU 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RAW RECEIVE: 1 1 1 1 1 1 1 1 1 N 1 1 1 1 1 1 0 0 0 1 1
RAW TRANSMIT: 1 1 1 1 1 1 1 1 1 N 1 1 1 1 1 1 N N N 1 1
CSMA/CD: 0 N N 1 P 1 0 0 M N 0 0 0 0 0 0 0 0 0 N 0
SDLC: N 0 0 P 1 1 0 0 0 0 0 N 0 0 0 0 N N N P 0
10-18
83C152 HARDWARE DESCRIPTION
Table 3.1 (Continued)
AVAILABLE PRE·
--+
OPTIONS AMBLE JAM CLOCK CONTROL
3 6 0 C E I C 0 R R C S
2 4 C R X N P M A A S D
N=NOTAVAILABLE B B C T T U A W W M L
M=MANDATORY I I I E E R T A C
0= OPTIONAL T T R R E R I
P = NORMALLY PREFERRED N N C A C
X=N/A A A E N D
L L I S
V M
SELECTED E I
t FUNCTION T
DATA ENCODING:
MANCHESTER
NRZI
NRZ
0
0
0
0
0
0
0
N
0
0
N
0
N
N
M
M
M
N
0
0
0
0
0
0
0
0
0
0
0
0
M
N
0
N
M
0
III
FLAGS:Oiii1110 0 0 N N 0 0 0 0 0 1 1 P
11/1DLE 0 0 0 0 0 0 0 0 0 1 P 1
CRC:NONE 1 1 N N 1 1 1 1 1 1 1 1
-
i6·BIT celTT 0 0 0 0 0 0 0 0 1 1 0 0
32-BIT AUTODIN II 0 0 0 0 0 0 0 0 1 1 0 0
DUPLEX:HALF 0 0 0 0 0 0 0 0 0 0 0 0
I
FULL 0 0 N N 0 0 0 0 N N N P
ACKNOWLEDGEMENT:NONE 0 0 0 0 0 0 0 0 0 a 0 0
HARDWARE 0 0 0 0 N a 0 a N N
- - I----
0 N
USER DEFINED 0 a 0 0 0 0 0 0 _.__a4_- a 0 1
ADDRESS RECOGNITION:
NONE 0 0 0 0 0 0 0 -..
0
~--,
a a 0 0
8-BIT 0 0 0 0 0 0 0 a --- .
1
-.--
1 0 0
i6-BIT 0 0 0 0 0 0 0 0 -_. _. I 1 a 0
COLLISION RESOLUTION:
NORMAL 0 0 0 0 N 0 0 0 _..._--- 0 N M N
ALTERNATE 0 0 0 0 N 0 0 0 0 N M N
DETERMINISTIC 0 0 0 0 N 0 0 0 0 N M N
PREAMBLE:NONE N N N N 0 0 0 0 0 0 N P
8-BIT N N 0 0 0 0 0 0 1 1 0 0
32-BIT X N 0 0 0 0 0 0 1 1 0 0
64-BIT N X 0 0 0 0 0 0 1 1 0 0
JAM:D.C. 0 0 X N N 0 0 0 0 N M N
CRC 0 0 N X N 0 0 0 0 N M N
CLOCKING:EXTERNAL 0 0 N N X N 0 0 0 0 N 0
INTERNAL 0 0 0 0 N X 0 0 0 0 0 0
CONTROL:CPU 0 0 0 0 0 0 X N 0 0 0 0
DMA 0 0 0 0 0 0 N X 0 0 0 0
RAW RECEIVE: 1 1 0 0 1 1 1 1 X N 1 1
RAW TRANSMIT: 1 1 N N 1 1 1 1 N X 1 1
CSMAlCD: 0 0 0 0 N 0 0 0 0 0 X N
SDLC: 0 0 N N 0 0 0 0 0 0 N X
10·19
intJ 83C152 HARDWARE DESCRIPTION
Note I: Programmable in Raw transmit or receive resolve the contention. There are three different modes
mode. of collision resolution made available to the user on the
C152. Re-transmission is attempted when a resolution
Almost all the options available from Table 3.1 can be algorithm indicates that a station's opportunity has ar-
implemented with the proper software to perform the rived.
functions that are necessary for the options selected. In
Table 3.1, a judgment has been made by the authors on Normally, in CSMA/CD, re-transmission slot assign-
which options are practical and which are not. What ments are intended to be random. This method gives all
this means is that in Table 3.1, an "N" should be inter- stations an equal opportunity to utilize the serial com-
preted as meaning that the option is either not practical munication link but also leaves the possibility of anoth-
when implemented with user software or that it cannot er collision due to two stations having the same slot
be done. An "0" is used when that function is one of assignment. There is an option on the CI52 which al-
several that can be implemented with the GSC without lows all the stations to have their slot assignments pre-
additional user software. viously determined by user software. This pre-assign-
ment of slots is called the deterministic resolution
The GSC is targeted to operate at bit rates up to 2.4 mode. This method allows resolution after the first col-
MBps using the external clock options and up to 2 lision and ensures the access of the link to each station
MBps using the internal baud rate generator; internal during the resolution. Deterministic resolution can be
data formatting and on-chip clock recovery. The baud advantageous when the link is being heavily used and
rate generator allows .most standard rates to be collisions are frequently occurring and in real time ap-
achieved. These standards include the proposed plications where determinism is required. Deterministic
IEEE802.3 LAN standard (1.0MBps) and the T1 stan- resolution may also be desirable if it is known before-
dard (1.544MBps). The baud rate is derived from the hand that a certain station's communication needs to be
crystal frequency. This makes crystal selection impor- prioritized over those of other stations if it is involved
tant when determining the frequency and accuracy of in a collision.
the baud rate.
The user needs to be aware that after reset, the GSC is 3.2.2 CSMAlCD FRAME FORMAT
in CSMA/CD mode, IFS = 256 bit times, and a bit
time equals 8 oscillator periods. The GSC will remain The frame format in CSMA/CD consists of a pream-
in this mode until the interframe space expires. If the ble, Beginning of Frame flag (BOF), address field, in-
formation field, CRC, and End of Frame flag (EOF) as
user changes to SDLC mode or the parameters used in
CSMA/CD, these changes will not take effect until the shown in Figure 3.1.
interframe space expires. A requirement for the inter-
frame space timer to begin is that the receiver be in an IPREAMBLE IBOF , ADDRESS 'INFO' CRC , EOF I
idle state. This makes it possible for the GSC to be in Figure 3.1 Typical CSMA/CD Frame
some other mode than the user intends for a significant
amount of time after reset. To prevent unwanted GSC PREAMBLE - The preamble is a series of alternating
errors from occurring, the user should not enable the Is and Os. The length of the preamble is programmable
GSC or the GSC interrupts for 170 machine cycles to be 0, 8, 32, or 64 bits. The purpose of the preamble is
«256 X 8)/12) after LNI bit is set. to allow all the receivers to synchronize to the same
clock edges and identifies to the other stations on-line
that there is activity indicating the link is being used.
3.2 CSMA/CD Operation For these reasons zero preamble length is not compati-
ble with standard CSMA/CD, protocols. When using
3.2.1 CSMAlCD OVERVIEW CSMA/CD, the BOF is considered part of the pream-
CSMA/CD operates by sensing the transmission line ble compared to SDLC, where the BOF is not part of
for a carrier, which indicates link activity. At the end of the preamble. This means that if zero preamble length
link activity, a station must wait a period of time, called were to be used in CSMA/CD mode, no BOF would be
the deference period, before transmission may begin. generated. It is strongly recommended that zero pream-
The deference period is also known as the interframe ble length never be used in CSMA/CD mode. If the
space. The interframe space is explained in Se~tion preamble contains two consecutive Os, the preamble is
3.2.3. considered invalid. If the CI52 detects an invalid pre-
amble, the frame is ignored.
With this type of operation, there is always the possibil-
ity of a collision occurring after the deference period BOF - In CSMA/CD the Beginning-Of-Frame is a part
due to line delays. If a collision is detected after trans- of the preamble and consists of two sequential Is. The
mission is started, a jamming mechanism is used to en- purpose of the BOF is to identify the end of the pream-
sure that all stations monitoring the line are aware of ble and indicate to the receiver(s) that the address will
the collision. A resolution algorithm is then executed to immediately follow.
10-20
83C152 HARDWARE DESCRIPTION
ADDRESS - The address field is used to identify which algorithm can be used but IEEE 802.3 uses a 32-bit
messages are intended for which stations. The user CRC. The generation polynomial the C152 uses with
must assign addresses to each destination and source. the 32-bit CRC is:
How the addresses are assigned, how they are main- G(X) = X32 + X26 + X23 + X22 + XI6 + X12 +
tained, and how each transmitter is made aware of Xli + XIO + X8 + X7 + X5 + X4 + X2
which addresses are available is an issue that is left to +X+l
the user. Some suggestions are discussed in Section
3.5.5. Generally, each address is unique to each station The CRC generator, as shown in Figure 3.2, operates
but there are special cases where this is not true. In by taking each bit as it is received and XOR'ing it with
these special cases, a message is intended for more than bit 31 of the current CRe. This result is then placed in
one station. These multi-targeted messages are called temporary storage. The result of XOR'ing bit 31 with
broadcast or multicast-group addresses. A broadcast the received bit is then XOR'd with bits 0, 1, 3, 4, 6, 7,
address consisting of all Is will always be received by 9,10, II, 15,21,22,25 asthe CRC is shifted right one
all stations. A multicast-group address usually is indi- position. When the CRC is shifted right, the temporary
cated by using a las the first address bit. The user can storage space holding the result of XOR'ing bit 31 and
choose to mask off all or selective bits of the address so the incoming hit is shifted into position O. The whole
that the GSC receives all messages or multicast-group process is then repeated with the next incoming or out-
messages. The address length is programmable to be 8 going bit.
or 16 bits. An address consisting of allIs will always be
received by the GSC on the C152. The address bits are The user has no access to the CRC generator or the bits
always passed from the GSC to the CPU. With user which constitute the CRC while in CSMA/CD. On
software, the address can be extended beyond 16 bits, transmission, the CRC is automatically appended to
but the automatic address recognition will only work the data being sent, and on reception, the CRC bits are
on a maximum of 16 bits. User software will have to not normally loaded into the receive FIFO. Instead,
resolve any remaining address bits. they are automatically stripped. The only indication the
user has for the status of the CRC is a pass/fail flag.
INFO - This is the information field and contains the The pass/fail flag only operates during reception. A
data that one device on the link wishes to transmit to CRC is considered as passing when the the CRC gener-
another device. It can be of any length the user wishes ator has 1100011100000100 11011010 01111011B as a
but needs to be in multiples of 8 bits. This is because remainder after all of the data, including the CRC
multiples of 8 bits are used to transfer data into or out checksum, from the transmitting station has been cy-
of the GSC FIFOs. The information field is delineated cled through the CRC generator. The preamble, BOF
from the rest of the components of the frame by the and EOF are not included as part of the CRC algo-
preceding address field and the following CRe. The rithm. An interrupt is available that will interrupt the
receiver determines the position of the end of the infor- CPU if the CRC of the receiver is invalid. The user can
mation field by passing the bytes through a temporary enable the CRC to be passed to the CPU by placing the
storage space. When the EOF is received the bytes in receiver in the raw receive mode.
temporary storage are the CRC, and the last bit re-
ceived previous to the CRC constitute the end of the This method of calculating the eRC is compatible with
information field. IEEE 802.3.
CRC - The Cyclic Redundancy Check (CRC) is an er- EOF - The End Of Frame indieates when the transmis-
ror checking algorithm commonly used in serial com- sion is completed. The end flag in CSMA/CD consists
munications. The C152 offers two types of CRC algo- of an idle condition. An idle condition is assumed when
rithms, a 16-bit and a 32-bit. The 16-bit algorithm is there is no transitions and the link remains high for 2 or
normally used in the SDLC mode and will be described more bit times.
in the SDLC section. In CSMA/CD applications either
10-21
inter 83C152 HARDWARE DESCRIPTION
270427-8
Figure 3.2. CRC Generator
3.2.3 INTERFRAME SPACE In most applications, the period of the interframe space
will be equal to or greater than the amount of time
The interframe space is the amount of time that trans- needed to turn-around the received frame~ The turn-
mission is delayed after the link is sensed as being idle around period is the amount of time that is needed by
and is used tll separate transmitted frames. In alternate user software to complete the handling of a received
backoff mode, the interframe space may also be includ- framc and be prepared to receive the next frame. An
ed in the ddermination of when rdransmissions may interframe space smaller than the required turn-around
actually begin. The C152 allows programmable inter- period could be 'used, but would allow some frames to
frame spaces of even numbers of bit times from 2 to be missed.
256. The hardware enforces the interframe space in
SDLC mode as well as in CSMA/CD mode. When a GSC transmitter has a new message to send, it
will first sense the link. If activity is detected, transmis-
The period of the interframe space is determined by the sion will be deferred to allow the frame in progress to
°
contents of IFS. IFS is an SFR that is programmable
from to 254. The interframe space is measured in bit
times. The value in IFS multiplied by the bit time
complete. When link activity ceases, the station contin-
ues deferring for one interframe space period.
equals the interframe spacc unless IFS equals 0. If IFS As mentioned earlier, the interframe space is used dur-
does equal 0, then the interframe space will equal 256 ing the collision resolution period as well as during nor-
bit times. One of the considerations when loading the mal transmission. The backoff method selected affects
IFS is that only even numbers (LSB must be 0) can be how the deference period is handled during normal
used because only the 7 most significant bits are loaded transmission. If normal backoff mode is selected, the
into IFS. The LSB is controlled by the GSC and deter- interframe space timer is reset if activity occurs during
mines which half of the IFS is currently being used. In approximately the first half of the interframe space. If
some modes, the interframe space timer is re-triggered alternate backoff or deterministic backoff is selected,
if activity is detected during the first half of the period. the timer is not reset. In all cases when the interframe
The GSC determines which half of the interframe space space timer expires, transmission may begin, regardless
is currently being used by examining the LSB. A one if there is activity on the link or not. Although the
indicates the first half and zero indicates the second C152 resets the interframe space timer if activity is de-
half of the IFS. tected during the first one-half of the interframe space,
this is not necessarily true of all CSMAlCD systems.
After reset IFS is 0, which delays the first transmission (IEEE 802.3 recommends that the interframe space be
for both SDLC and CSMA/CD by 256 bit times (after reset if activity is detected during the first two-thirds or
reset, a bit time equals 8 oscillator clock periods). less of the interframe space.)
10-22
inter 83C152 HARDWARE DESCRIPTION
3.2.4 CSMA/CD DATA ENCODING Narrow Pulses
Manchester encoding/decoding is automatically select- A valid Manchester waveform must stay high or low
ed when the user software selects CSMA/CD transmis- for at least a half bit-time, nominally 4 sample-times.
sion mode (See Figure 3.3). In Manchester encoding Jitter tolerance allows a waveform which stays high or
the value of the bit is determined by the transition in low for 3 sample-times to also be considered valid. A
the middle of the bit time, a positive transition is decod- sample sequence which shows a second transition only
ed as a 1 and a negative transition is decoded as a O. I or 2 sample-times after the previous transition is con-
The Address and Info bytes are transmitted LSB first. sidered to be the result of a collision. Thus, sample
The CRC is transmitted MSB first. sequences such as 0000110000 and 111101111 are inter-
preted as collisions.
If the external IX clock feature is chosen the transmis-
sion mode is always NRZ (see Section 3.5.11). Using The GSC hardware recognizes the collision to have oc- •
CSMA/CD with the external clock option is not sup- curred within 3/8 to 1/2 bit-time following the second I
ported because the data needs reformatting-from NRZ transition.
to Manchester for the receiver to be able to detect codc
violations and collisions.
Missing O-to-1 Transition
3.2.5 COLLISION DETECTION A O-to-I transition is expected to occur at the center of
any bit cell that begins with O. If the previous 1-to-0
The GSC hardware detects collisions by detecting Man- transition occurred at the bit cell edge, a jitter tolerance
chester waveform violations at its GRXD pin. Three of ± 1 sample is allowed. Sample sequences such as
kinds of waveform violations are detected: a missing 1111:0000 1111 and 1111:00000 1111 are valid, where
O-to-l transition where one was expected, a 1-to-0 tran- ":" indicates a bit cell edge. Sequences of the form
sition where none was expected, and a waveform that 1111 :OOOOOOXXX are interpreted as collisions.
stays low (or high) for too short a time.
For these kinds of sequences, the GSC recognizes the
collision to have occurred within 1 to I 1/8 bit-times
Jitter Tolerance after the previous I-to-O transition.
A valid Manchester waveform must have a transition at
If the previous I-to-O transition occurred at the center
the midpoint of any bit cell, and may have a transition
at the edge of any bit cell. Therefore, transitions will ofthe previous bit cell, a jith:r tolerance of ± 2 samples
nominally be separated by either 1/2 bit-time or 1 bit- is allowed. Thus, sample sequences such as
time. - 11110000:00001111 and III 100000:000001111 are val-
id. Sequences of the form IIIIOOOOO:OOOOOOXXX are
The GSC samples the GRXD pin at the rate of 8 x the interpreted as collisions.
bit rate. The sequence of samples for the received bit
sequence 001 would nominally be: For these kinds of sequcnccs, the GSC recognizes the
collision to have occurred within I S/B to I 3/4 bit-
samples: 1 1 1 1 0 0 0 0 : 1 1 1 100 0 0 : 0 0 0 0 1 1 1 1 : times after the previous I-to-O transition.
bit value: 0 0 1
: <-bit cell->: <-bit cell->: <-bit cell->: Unexpected 1-to-O Transition
The sampling system allows a jitter tolerance of ± 1 If the line is at a logic I during the first half of a bit cell,
sample for transitions that are 1/2 bit-time apart, and then it is expected to make a I-to-O transition at the
± 2 samples for transitions that are 1 bit-time apart. midpoint of the bit cell. If the transition is missed, it is
assumed that this bit cell is the first half of an EOF flag
o o o
. MANCHESTER
I BtT I
-TIME~
270427-14
Figure 3.3. Manchester Encoding
10-23
inter 83C152 HARDWARE DESCRIPTION
(line idle for two bit-times). One bit-time later (which (GREN = 0), and the Receive Error Interrupt flag
marks the midpoint of the next bit cell), if there is still RCABT is set. If DCR has been selected, the GSC
no I-to-O transition, a valid EOF is assumed and the participates in the resolution algorithm.
line idle bit (LNI in TSTA T) gets set.
Incoming bits take 1/2 bit time to get from the GRXD
However, if the assumed EOF flag is interrupted by a pin to the bi t decoder. The bit decoder strips off the
I -to-O transition in the bit-time following the first miss- preamble/BOF bits, and the first bit after BOF is shift-
ing transition, a collision is assumed. In that case the ed into a serial strip buffer. The length of the .strip
GSC hardware recognizes the collision to have oc- buffer is equal to the number of bits in the selected
curred within 1/2 to 5/8 bit-time after the unexpected CRC. It is within this buffer that address recognition
transition. takes place. If the address is recognized as one for
which reception should proceed, then when the first
address bit exits the strip buffer it is shifted into an 8-bit
3.2.6 RESOLUTION OF COLLISIONS shift register. When the shift register is full, its content
is transferred to RFIFO. That is the event that deter-
How the GSC responds to a detected collision depends
mines whether a collision sets RCABT or not.
on what it was doing at the time the collision was de-
tected. What it might be doing is either transmitting or
receiving a frame, or it might be inact ive. GSC Transmitting
If the GSC is in the process of transmitting a frame at
GSC Inactive the time the collision is detected, it will in every case
execute its jam/backoff procedure. Its reponse beyond
The collision is detected whether the USC is active or
not. If the GSC is neither transmitting nor receiving at t hat depends on whether the first byte of the frame has
the time the collision is detected, it takes no action un- becn transferred from TFIFO to the output shift regis-
ter yet or not. That transfer takes place at the beginning
less user software has selected thc Deterministic Colli-
sion Resolution (OCR) algorithm. If nCR has been of the first bit of the BOF; that is, 2 bit-times before the
selected, the GSC will participate in the resolution al- end of the preamble/BOF sequence.
gorithm.
If the transfer from TFIFO hasn't occurred yet, the
GSC hardware will try again to gain access to the line
GSC Receiving after its backoff time has expired. Up to 8 automatic
restarts can be attempted. If the 8th restart is interrupt-
If the GSC is already in the process of receiving a frame ed by yet another collision, the transmitter is disabled
at the time the collision is detected. its response de- (TEN = 0) and the Transmit Error Interrupt flag
pends on whether the first byte of t he frame has been TCDT is set.
transferred into RFI FO yet or not. I I' t hat hasn't oc-
curred, the GSC simply aborts the reception, but takes If the transfer from TFIFO occurs before a collision is
no other action unless DCR has been selected. If DCR detected, the transmitter is disabled (TEN = 0) and
has been selected, the GSC participates in the resolu- the TCDT flag is set.
tion algorithm.
The response of the GSC to detected collisions is sum-
If the reception has already progressed to the point marized in Figure 3.4.
where a byte has been transferred to RFIFO by the
time the collision is detected, the receiver is. disabled
What the GSC was dOing Response
nothing None, unless DCR = 1.
If DCR = 1,begin DCR countdown.
Receiving a Frame, first None, unless DCR = 1.
byte not in RFIFO yet. If DCR = 1, begin DCR countdown.
Receiving a Frame, first Set RCABT, clear GREN.
byte already in RFIFO. If DCR = 1, begin DCR countdown.
Transmitting a Frame, first Execute jam/backoff.
byte still in TFIFO Restart if collision count s 8.
Transmitting a Frame, first Execute jam/backoff.
byte already taken from TFIFO Set TCDT, clear TEN.
Figure 3·4. Response to a Detected Collision. References to DCR and the DCR Countdown
Have to Do with the Deterministic Collision Resolution Algorithm.
10-24
inter 83C152 HARDWARE DESCRIPTION
Jam In the Deterministic algorithm, the GSC backs off to
await its pre-determined turn.
The jam signal is generated by any 8XC152 that is in-
volved in transmitting a frame at the time a collision is
detected at its GRXD pin. This is to ensure that if one Random Backoff
transmitting station detects a collision, all the other sta-
In either of the random algorithms, the first thing that
tions on the network will also detect a collision.
happens after a collision is detected is that a 1 gets
shifted into the TCDCNT (Transmit Collision Detect
If a transmitting 8XC152 detects a collision during the
Count) register, from the right.
preamble/BOF part of the frame that it is trying to
transmit, it will complete the preamble/BOF and then
Thus if the software cleared TCDCNT before telling
begin the jam signal in the first bit time after BOF. If
the GSC to transmit, then TCDCNT keeps track of
the collision is detected later in the frame, the jam sig-
how many times the transmission had to be aborted
nal will begin in the next bit time after the collision was
because of collisions:
detected.
TCDCNT = OOOOOOOO first· attempt
The jam signal lasts for the same number of bit times as 00000001 first collision
the selected CRC lcngth-either 16- or 32-bit times.
00000011 second collision
The 8XC152 provides two types of jam signals that can 00000111 third collision
be selected by user software. If the node is DC-coupled 00001111 fourth collision
to the network, the DC jam can be selccted. In this case
the GTXD pin is pulled to a logic 0 for the duration of
the jam. If the node is AC-coupled to the network, then 11111111 eighth collision
AC jam must be selected. In this case the GSC takes
the CRC it has calculated thus far in the transmission, After TCDCNT gets a 1 shifted into it, the logical
inverts each bit, and transmits the inverted CRe. The AND of TCDCNT and PRBS is loaded into a count-
selection of DC or AC jam is made by setting or clear- down timer named BKOFF. PRBS is the name of an
ing the DC} bit, which resides in the SFR named SFR which contains the output of a pseudo-random
MYSLOT. binary sequence generator. Its function is to provide a
random number for use in the backoff algorithm.
When the jam signal is completed, the 8XC152 goes
into an idle state. Presumeably, other stations on the Thus on the first collision BKOFI: gets loaded random-
network are also generating their own jam signals, after ly with either OOOOOOOO or OOOOO(Xli. If there is a sec-
which they too go into an idle state. When the 8XC152 ond collision it gets loaded with t he random selection of
detects the idle state at its own GRXD pin, the backoff 00000000, 00000001, 00000010, or 00000011. On the
sequence begins. third collision there will be a random selection among 8
possible numbers. On the fOllrth, among 16, etc. Figure
Backoff
3.5 shows the logical arrangelllent of PRBS, TCDCNT,
and BKOFF.
There are three software selectable collision resolution
algorithms in the 8XC152. The selection is made by BKOFF starts counting down from its preload value,
writing values to 3 bits: counting slot times. At any tillie, thc current value in
BKOFF can be read by the CPU, but CPU writes to
OCR M1 MO Algorithm BKOFF have no effect. While BKOFF is counting
0 0 0 Normal Random down, if its current valuc is not 0, transmission is dis-
abled. The output signal "BKOFF = 0" is asserted
0 1 1 Alternate Random
when BKOFF rcaches 0, and is used to re-enable trans-
1 1 1 Deterministic mission.
Ml and MO reside in GMOD, and DCR is in At that time transmission can proceed, subject of
MYSLOT. course to IFS enforcement, unless:
• shifting a 1 into TCDCNT from the right caused a 1
In the Normal Random algorithm, the GSC backs off to shift out from the MSB of TCDCNT, or
for a random number of slot times and then decides
whether to restart the transmission. The backoff time • the collision was detected after TFIFO had been ac-
begins as soon as a line idle condition is detected. cessed by the transmit hardware.
The Alternate Random algorithm is the same as the
Normal Random except the backoff time doesn't start
until an IFS has transpired.
10-25
83C152 HARDWARE DESCRIPTION
SKOff = MYSLOT
270427-38
Figure 3.5. Backoff Timer Logic
In either of these cases, the transmitter is disabled most protocols, the slot period must be equal to or
(TEN = 0) and the Transmit Error flag TCDT is set. greater than the longest round trip propagation time
The automatic restart is canceled. plus the jam time.
Where the Normal and Alternate Random backofT al-
gorithms differ is that in Normal Random backofT ~he Deterministic Backoff
BKOFF timer starts counting down as soon as a hne
In the Deterministic backofT mode, the GSC is assigned
idle condition is detected, whereas in Alternate Ran-
(in software) a slot number. The slot assignment is wri~
dom backoff the BKOFF timer doesn't start counting
ten to the low 6 bits of the register MYSLOT, ThIS
down till the IFS expires.
same register also contains, in the 2 high bit positions,
the control bits DCJ and DCR.
The Alternate Random mode was designed for net-
works in which the slot time is less than the IFS. If the
Slot assignments therefore can run from 0 to 63. It will
randomly assigned backoff time for a given transmitter
turn out that the higher the slot assignment, the sooner
happens to be 0, then it is free to transmit as soon as the
the GSC will get to restart its transmission in the event
IFS ends. If the slot time is shorter than the IFS, Nor-
of a collision.
mal Random mode would nearly guarantee that if
there's a first collision there will be a second collision.
The highest slot assignment in the network. is written
The situation is avoided in Alternate Random mode,
by each station's software into its TCDCNT register.
since the BKOFF countdown doesn't start till the IFS
Normally the highest slot assignment is just the total
is over.
number of stations that are going to participate in the
backofT algorithm.
The unit of count to the BKOFF timer is the slot time.
The slot time is measured in bit-times, and is deter-
In deterministic backofT mode a collision will not cause
mined by a CPU write to the register SLOTTM. The
a I to be shifted into TCDCNT. TCDCNT will still be
slot time clock is a I-byte downcounter which starts its
ANDed with PRBS and the result loaded into BKOFF.
countdown from the value written to SLOTTM. It is
In order to insure that all stations have the same value
decremented each bit time when a backofT is in prog-
loaded into BKOFF, which determines the first slot
ress, and when it gets to I it generates one tick in the
number to occur, the PRBS should be loaded with
slot time clock. The next state after I is the reload value
OFFH' the PRBS will maintain this value until either
which was written to SLOTTM. If 0 is the value writ-
the 8XCI52 is reset or the user writes some other value
ten to SLOTTM, the slot time clock will equal 256 bit
into PRBS. After BKOFF is loaded it begins counting
times.
down slot times as soon as the IFS ends. Slot times are
defined by the user, the same way as before, by loading
A CPU write to SLOTTM accesses the reload register.
SLOTTM with the number of bit times per slot.
A CPU read of SLOTTM accesses the downcounter. In
10-26
inter 83C152 HARDWARE DESCRIPTION
When BKOFF equals the slot assignment (as defined in A transmitting station with HABEN enabled expects
MYSLOT), the signal "BKOFF = MYSLOT" in Fig- an acknowledge. It must receive one prior to the end of
ure 3.5 is asserted for one slot time, during which the the interframe space, or else an error is assumed and
GSC can restart its transmission. the NOACK bit is set. Setting of the TON bit is also
delayed until the end of the interframe space. Collisions
While BKOFF is counting down, if any activity is de- detected during the interframe space will also cause '
tected at the GRXO pin, the countdown is frozen until NOACK to be set.
the activity ends, a line idle condition is detected, and
an IFS transpires. Then the countdown resumes from If the user software has enabled OMA servicing of the
where it left off. GSC, an interrupt is generated when TON is set. TON
will be set at the end of the interframe space if a hard-
If a collision is detected at the GRXD pin while ware based acknowledge is required and received. If the
BKOFF is counting down, the collision resolution algo- GSC is serviced by the CPU, the user must time out the . .
rithm is restarted from the beginning. interframe space and then check TON before disabling I
the transmitter or transmit error interrupts. NOACK
In effect, the GSC "owns" its assigned slot number, but will generate a transmit error interrupt' if the transmit-
with one exception. Nobody owns slot number 0. ter and interrupts are enabled during the interframe
Therefore if the GSC is assigned slot number 0, then space.
when BKOFF = 0, this station and any other station
that has something to say at this time will have an
equal chance to take the line. 3.3 SOLe Operation
3.2.7 HARDWARE BASED ACKNOWLEDGE 3.3.1 SDLC OVERVIEW
Hardware Based Acknowledge (HBA) is a data link SOLC is a communication protocol developed by IBM
packet acknowledging scheme that the user software and widely used in industry. It is based on a primary/
can enable with CSMA/CO protocol. It is not an op- secondary architecture and requires that each second-
tion with SOLC protocol however. ary station have a unique address. The secondary sta-
tions can only communicate to the primary station, and
In general HBA can give improved system response then, only when the primary station allows communi-
time and increased effective transmission fates over ac- . cation to take place. This eliminates the possibility of
knowledge schemes implemented in higher layers of the contention on the serial line caused by the secondary
network architecture. Another benefit is the possibility station'S trying to transmit simultaneously.
of early release of the transmit buffer as soon as the
acknowledge is received. In the CIS2, sOl.e cau hl! l"Ilnli!)url!d to work in either
full or half duplex. When adhering to strict SDLC pro-
The acknowledge consists of a preamble followed by an tocol, full dupicK is n:quircd. Full dupleK is selected
idle condition. A receiving station with HABEN en- whenever a 16·bit CRe is selected. At the end of a valid
abled will send an acknowledge only if the incoming reset the 16-bit CRe is selected. To select half duplex
address is unique to the receiving station and if the with a 16-bit CRC, the receiver must be turned off by
frame is determined to be correct with no errors. For user software bdilre t I':lnsmission. The receiver is
the acknowledge to be sent, TEN must be set. For the turned off by clearinl\ the OREN bit (RSTAT.l). The
transmitting station to recognize the acknowledge receiver needs to be tu med off because the address that
GREN must be set. A zero as the LSB of the address is transmitted is the add ress of the secondary station's
indicates that the address is unique and not a group or receiver. If not turned off, the receiver could mistake
broadcast address. Errors can be caused by collisions, the outgoing messal)e as being intended for itself. When
incorrect CRC, misalignment, or FIFO overflow. The 32-bit CRCs are used, half duplex is the only method
receiver sends the acknowledge as soon as the line is available for transmission.
sensed to be idle. The user must program the interframe
space and the preamble length such that the acknowl-
edge is completed before IFS expires. This is normally
done by programming IFS larger than the preamble.
10-27
83C152 HARDWARE DESCRIPTION
3.3.2 SOLe Frame Format CONTROL - The control field is used for initialization
of the systelll, identifying the sequence of a frame, to
The format of an SDLC frame is shown in Figure 3.6. identify if the message is com plete, to tell .secondary
The frame consists of a Beginning of Frame flag, Ad- stations if a response is expected, and acknowledgement
dress field, Control Field, Information field (optional), of previously sent frames. The user software is responsi-
a CRC, and the End of Frame flag. ble for insertion of the control field as the GSC hard-
ware has no provisions for the management of this
IBOF IADDRESS ICONTROL IINFO ICRC IEOF I field. The interpretation and formation of the control
field must also be handled' by uscr software. The infor-
Figure 3.6. Typical SOLe Frame , mation following the control field is typically used for
information transfer, error reporting, and various other
BOF - The begin of frame flag for SDLC is 01111110. functions. These functions are accomplished by the for-
It is only one of two possible combinations that have six mat of the control field. There are three formats avail-
consecutive ones in SDLC. The other possibility is an able. The types of formats are Informational, Supervi-
abort character which consists of eight or more consec- sory, or Unnumbered. Figure 3.7 shows the various for-
utive ones. This is because SDLC utilizes a process mat types and how to identify thellI.
called bit stuffing. Bit stuffing is the insertion of a 0 as
the next bit every time a sequence of five consecutive 1s Since the user software is responsible for the implemen-
is detected. The receiver automatically removes a 0 af- tation of the control field, what follows is a simple ex-
ter every consecutive group of five ones. This removal planation on the control field and its functions. For a
of the 0 bit is referred to as bit stripping. Bit stuffing is c<lIlIplcte understanding and proper implementation of
discussed in Section 3.3.4. All the procedures required SDI.C, the user should refer to thc IBM document,
for bit stuffing and bit stripping arc automatically han- (rA27-3093-2, IBM Synchronous Data Link Control
dled by the GSc. (rencral Information, Within that document, is another
list of 111M doclllllents which go into detail on the
In standard SDLC protocol the BOF signals the start of SDI.C protocol and its usc.
a frame and is limited to 8 bits in length. Since there is
no preamble in SDLC the BOF is considered an entire The COJltrol licld is eight bits wide and the format is
separate field and marks th~ beginning of the frame. determined by bits 0 and I. If bit 0 is a zero, then the
The BOF also serves as the clock synchronization frame is an informational frame. If bit 0 is a one and bit
mechanism and the reference point lilr determining the I a zero, then it is a supervisory frame, and if bit 0 is a
position of the address and control liclds. one and bit I a one then the frame is an unnumbered
frame.
ADDRESS - The address field is used to identify which
stations the message is intended for. Each secondary In an informational frame' bits 3,2,1 contain the se-
station must ,have a unique address. The primary sta- quence count of the frame being sent.
tion must then be made aware of which addresses are
assigned to each station. The address !cngt h is specified Bit 4 is the P/F (Poll/Final) bit. 'If bit 4 equals 1 and
as 8-bits in standard SDLC protocols but it is expand- originates from the primary, then the secondary station
able to 16-bits in the C152. User software can further is expected to initiate a transmission. If bit 4 equals 1
expand the number of address bits, but the automatic and originates from a secondary station, then the frame
address recognition feature works on a maximum of 16- is the final frame in a transmission.
bits.
Bits .7,6,5 contain the sequence count a station expects
In SDLC the addresses are normally unique for each on the next transmission to it. The sequence count. can
station. However, there are several classes of messages vary from DOOB to 11 lB. The count then starts over
that are intended for more than one station. These mes- again at OOOB after the value IIIB is incremented. The
sages are called broadcast and group addressed frames. acknowledgement is recognized by the receiving station
An address consisting of all Is will always be automati- when it decodes bits 7,6,5 of an incoming frame. The
cally received by the GSC, this is defined as the broad- station sending the transmission is acknowledging the
cast address in SDLC. A group address is an address frames received up to the count represented in bits 7,6,5
that is common to more than one station. The GSC (sequence count-I). With this method, up to seven se-
provides address masking bits to provide the capability quential frames may be transmitted prior to an ac-
of receiving group addresses. knowledgement being received. If eight frames were al-
lowed to pass before an acknowledgement, the sequence
I f desired, the user software can mask off all the bits of count would roll over and this would negate the pur-
the address. This type of masking puts the GSC in a pose of the sequence numbers.
promiscuous mode so that all addresses are received.
10-28
infef 83C152 HARDWARE DESCRIPTION
7
. POSITIONS-.--_--,
M 6 5 432
_ _-.,._ _-,-_ _-r_ _....,-_ _..,-_ _..--_--, 1
RECEPTION SEN DING
SEQUENCE SEQUENCE
270427-15
RECEPTION SEQUENCE - The sequence expected in the SENDING SEQUENCE portion of the control byte
in the next received frame. This also confirms correct reception of up to seven frames prior to the sequence given.
POLL/FINAL - Identifies the frame as being a polling request from the master station or the last in a series of
frames from the master or secondary.
SENDING SEQUENCE - Identifies the sequence of the frame being transmitted.
°- bit ° °the frame is identified as a informational format type.
If =
INFORMATION FORMAT
m 7 6 5 432
POSITIONS-.--_--,_ _--,._ _-,-_ _-r_ _--,-_ _-.-_ _-,--_--, 0
RECEPTION
SEQU ENCE
POLL/
FINAL MODE
0 .:' 1
270427-16
RECEPTION SEQUENCE - Expected sequence of frame for next reception.
POLL/FINAL - Identifies frame as being a polling request from the master station or the last in a series of
frames from the master or secondary.
MODE - Identifies whether receiver is ready (00), not ready (10) or a frame was rejected (0 I). TIll: rejeeted frame
is identified by the reception sequence.
0,1 - If bits 1,0 = 0,1 the frame is identified as a supervisory format type.
SU PERVISORYFORMAT
M 7
POSITIONS-.--_---: 6 5 432
_ _---,-_ _-,-_ _-.-_ _....,-_--,-,-_ _ _ _--, 0
CdMMAND/
RESPONSE
270427-17
COMMAND/RESPONSE - Identifies the type of command or response.
POLL/FINAL - Identifies frame as being a polling request from the master station or the last in a series of
frames from the master or secondary.
1,1 - If bits 1,0 = 1,1 the frame is identified as an unnumbered format type.
NONSEQUENCED FORMAT 270427-18
Figure 3_7_ SOLC Control Field
10-29
83C152 HARDWARE DESCRIPTION
Following the informational control field comes the in- When the mode is 10, the sending station is indicating
formation to be transferred. that its receiver is not ready to accept frames.
In the supervisory format (bits 1,0 = 0,1) bits 3,2 de- Mode 11 is an illegal mode in SDLC protocol.
termine which mode is being used.
Bits 7,6,5 represent the value of the sequence the sta-
When the mode is 00 it indicates that the receive line of tion expects when the next transfer occurs for that sta-
the station that sent the supervisory frame is enabled tion. There is no information following the control field
and ready to accept frames. when the supervisory format is used.
When the mode is 01, it indicates that previously a In the unnumbered format (bits 1,0 = l,t) bits 7,6, 5,
received frame was rejected. The value in the receive 3, 2 (notice bit 4 is missing) indicate .commands from
count identifies which frame(s) need to be retransmit- the primary to secondary stations or requests of second-
ted. ary stations to the primary.
The standard commands are:
BITS 7 6 5 3 2 Command
o 0 0 0 0 Unnumbered Information (UI)
o 0 0 0 1 Set initialization mode (SIM)
o 1 0 0 0 Disconnect (DISC)
o 0 1 0 0 Response optional (UP)
1 1 0 0 1 Function descriptor in
information field (CFGR)
o 1 Identification in information field. (XID)
o 0 Test pattern in information field. (TEST)
The standard responses are:
BITS 7 6 5 3 2 Command
0 0 0 0 0 Unnumbered information (UI)
0 0 0 0 Request for initialization (RIM)
0 0 0 1 Station in disconnected mode (OM)
1 0 0 0 Invalid frame received (FRMR)
0 1 0 0 Unnumbered acknowledgement (UA)
1 1 1 Signal loss of input (BCN)
0 0 1 Function descriptor in information field (CFGR)
0 0 0 0 Station wants to disconnect (RD)
0 1 1 Identification in information field (XID)
1 0 0 Test pattern in information field (TEST)
10-30
83C152 HARDWARE DESCRIPTION
In an unnumbered frame, information of variable rithms, a 16-bit and a 32-bit. The 32-bit algorithm is
length may follow the control field if UI is used, or normally used in CSMA/CD applications and is de-
information of fixed length may follow if FRMR is scribed in section 3.2.2. In most SDLC applications a
used. 16-bit CRe is used and the hardware configuration that
supports 16-bit CRC is shown in Figure 3.8. The gener-
As stated earlier, the user software is responsible for the ating polynomial that the CRC generator uses with the
proper management of the control field. This portion of 16-bit CRC is:
the frame is passed to or from the GSC FIFOs as basic
informational type data. G(X) = X16 + X12 + X5 + 1
INFO - This is the information' field and contains the
data that one device on the link wishes to transmit to
another device. It can be of any length the user wishes,
but must be a multiple of 8 bits. It is possible t hat some
frames may contain no information field. The informa-
The way the CRC operates is that as a bit is received it
is XOR'd with bit IS of the current CRC and placed in
temporary storage. The result of XOR'ing bit IS with
the received bit is then XOR'd with bit 4 and bit II as
the CRC is shifted one position to the right. The bit in
II
I
tion field is identified to the receiving stations by the temporary storage is shifted into position O.
preceding control field and the following eRe. The
GSC determines where the last of the information field The required CRC length for SDLC is 16 bits. The
is by passing the bits through the eRC generator. CRC is automatically stripped from the frame and not
When the last bit or EOF is received the bits that re- passed on to the CPU. The last 16 bits are then run
main constitute the CRe. though the CRC generator to insure that the correct
remainder is left. The remainder that is checked for is
eRC - The Cyclic Redundancy Check (CRe) is an er- OOlllOlOOOOllllB (lDOF Hex). If there is a mis-
ror checking sequence commonly used in serial com- match, an error is generated. The user software has the
munications. The C152 offers two types of CRC algo- option of enabling this interrupt so the CPU is notified.
270427-19
Figure 3.8. 16-Bit CRC
10-31
83C152 HARDWARE DESCRIPTION
EOF - The End Of Frame (EOF) indicates when the 3.3.5 SENDING ABORT CHARACTER
transmission is complete. The EOF is identified by the
end flag. An end flag consists of the bit pattern An abort character is one of the exceptions to .the rule
01111110. The EOF can also serve as the BOF for the that disallows more than 5 consecutive Is. The abort
next frame. character consists of any occurrence of seven or more
consecutive ones. The simplest way for the C152 to
send an abort character is to clear the TEN bit. This
3.3.3 DATA ENCODING causes the output to be disabled which, in turn, forces it
to a constant high state. The delay necessary to insure
The transmission of data in SDLC mode is done via
that the link is high for seven bit times is a task that
NRZI encoding as shown in Figure 3.9. NRZI encod-
needs to be handled by user software. Other methods of
ing transmits data by changing the state of the output
sending an abort character are using the IFS register or
whenever a O. is being transmitted. Whenever a 1 is
using the Raw Transmit mode. Using IFS still entails
transmitted the state of the output remains the same as
clearing the TEN bit, but TEN can be immediately re-
the previous bit and remains valid for the entire bit
enabled. The next message will not begin until the IFS
time. When SDLC mode is selected it automatically
expires. The IFS begins timing out as soon as DEN
enables the NRZI encoding on the transmit line and
goes high which identifies the end of transmission. This
NRZI decoding on the receive line. The Address and
also requires that IFS contain a value equal to or great-
Info bytes are transmitted LSB first. The CRC is trans-
er than 8. This llIethod may have the undesirable effect
mitted MSB first.
that DEN goes high and disables the external drivers.
The other alternative i, to switch to Raw Transmit
3.3.4 BIT STUFFING/STRIPPING mode. Then, writing OFFII to TFIFO would generate a
high output for 8 bit tillles. This method would leave
In SDLC modc one of the primary rules of the protocol DEN active during the transmission of the abort char-
is that in any normal data transmission, there will never act cr.
be an occurrence of more than 5 consecutive Is. The
GSC takes care of this housekeeping chore by automat- When thc receiver detects seven or more consecutive Is
ically inserting a 0 after every occurrence of 5 consecu- and data has been loaded into the receive FIFO, the
tive Is and the receiver automatically removes a zero RCABT flag is set in RSTAT and that frame is ig-
after receiving 5 consecutive Is. All t he necessary steps nored. If no data has been loaded into the receive
required for implementing bit stuffing and stripping are FIFO, there are no abort flags set and that frame is just
incorporated into the GSC hardware. This makes the ignored. A retransmitted frame may immediately fol-
operation transparent to the user. About the only time Iowan abort character, provided the proper flags are
this operation becollles apparent to t he user, is if the used.
actual data on-the transmission mediulll is being moni-
tored by a device that is not aware of the automatic
insertion of Os. The bit stuffing/stripping guarantees
that there will be at least one transition every 6 bit
times while the line is active.
o o o
,
NRZ~ . I
BIT '
TIME ---
270427-20
Figure 3.9. NRZI Encoding
10-32
inter 83C152 HARDWARE DESCRIPTION
3.3.6 LINE IDLE passing the message to the downstream station. This
delay is necessary so that a station can decode its own
If 15 or more consecutive Is are detected by the receiv- address before the message is passed on. The various
er the Line Idle bit (LNI) in TSTAT is set. The seven networks are shown in Figure 3.10.
Is from the abort character may be included when sens-
ing for a line idle condition. The same methods used for
sending the Abort character can be used for creating 3.3.9 HDLC/SDLC COMPARISON
the Idle condition. However, the values would need to
HDLC (High level Oata Link Control) is a standard
be changed to reflect 15 bit times, instead of seven bit
times. adopted by the International Standards Organization
(ISO). The HOLC standard is defined in the ISO docu-
ment #ISO 6159 - HOLC unbalanced classes ofproce-
dures. IBM developed the SOLC protocol as a subset of
III
3.3.7 ACKNOWLEDGEMENT
HDLC. SDLC conforms to HDLC protocol require-
Acknowledgment in SDLC is an implied acknowledge ments, but is more restrictive. SDLC contains a more
and is contained in the control field. Part of the control precise definition on the modes of operation.
frame is the sequence number of the next expected
frame. This sequence number is called the Receive Some of the major differences between SOLC and
Count. In transmitting the Receive Count, the receiver HDLCare:
is in fact acknowledging all the previous frames prior to SDLC HOLC
the count that was transmitted. This allows for the Unbalanced (primary/ Balanced
transmission of up to seven frames before an acknowl- secondary) (peer to peer)
edge is required back to the transmitter. The limitation
Modulo 8 (no extensions Modulo 128 (up to 127
of seven frames is necessary because the Receive Count
in the control field is limited to three binary digits. This allowed, up to 7 out- outstanding frames
means that if an· eighth transmission occurred this standing frames before before acknowledge
would cause the next Receive Count to repeat the first acknowledge is required)' is required)
count that still is waiting for an acknowledge. This 8-bit addressing only Extended addressing
would defeat the purpose of the acknowledgement. The Byte aligned data Variable size of data
processing and general maintenance of the sequence
count must be done by the user software. The Hard- The C152 does not support HDLC implementation re-
ware Based Acknowledge option that is provided in the quiring data alignment othcr than byte alignment. The
C152 is not compatible With standard SDLC protocol. user will find that many of t he protocol parameters are
programmable in the CI52 whidl allows easy imple-
mentation of proprietary or ,tanoard HOLC network.
3.3.8 PRIMARY/SECONDARY STATIONS User software needs to implement the control field
All SDLC networks are based upon a primary/second- functions.
ary station relationship. There can be only one primary
station in a network and all the other stations are con- 3.3.10 USING A PREAMBLE IN SDLC
sidered secondary. All communication is between the
primary and secondary station. Secondary station to When transmitting a preamhll! in SDLC mode, the user
secondary station direct communication is prohibited. should be aware that thl! pattl!rn of 10101010 ... is
If there is a need for secondary to secondary communi- output. NRZI encoding is useo in SOLC when the in-
cation, the user software will have to make allowances ternal baud rate gcnerator is the clock source and this
for the master .to act as an intermediary. Secondary means that a transition will occur every two bit times,
stations are allowed use of the serial line only when the when a 0 is transmitted. This compares with some oth-
master permits them. This is done by the master polling er SDLC devices, most of which transmit the pattern
the secondary stations to see if they have a need to 00000000 ... which will cause a transition every bit
access the serial line. This should prevent any collisions time. Our past experience has shown that the CI52 pre-
from occurring, provided each secondary station has its amble does not cause a problem with most other devic-
own unique address. This arrangement also partially es. This is because the preamble is used only to define
determines the types of networks supported. Normal the relative bit time boundaries within some variation
SDLC networks consist of point-to-point, multi-drop, allowed by the receiving station, and the C152 pream-
or ring configurations and the CI52 supports all of ble fulfills this function. The C152 does not have any
these. However, some SOLC processors support an au- problems with receiving a preamble consisting of all Os.
tomatic one bit delay at each node that is not supported One note of caution however. If idle fill flags are used
by the C152. In a "Loop Mode" configuration, is is in conjunction with a preamble, the addresses OO(OO)H
necessary that the transmission be delayed from the re- and 55(55)H should not be assigned to any CI52 as the
ception of the frames from the upstream station before preamble following the idle fill flags will be interpreted
as an address.
10-33
83C152 HARDWARE DESCRIPTION
3.4 User Defined Protocols 3.5 Using the GSC
The explanation on the implementation of user defined
protocols would go beyond the scope of this manual, 3.5.1 LINE DISCIPLINE
but examining Table 3.1 should give the reader a con- Line discipline is how the management of the transfer
solidated list of most of the possibilities. In this manual, of data over the physical medium is controlled. Two
any deviation from the documents that cover the imple-
types of line discipline will be discussed in this section:
mentation of CSMA/CD or SDLC are considered user
full duplex and half duplex.
defined protocols. Examples of this would be the use of
SDLC with the 32-bit CRC selected or CSMA/CD
with hardware based acknowledge.
Point-to-Point Network
270427-21
Multi-Drop Network
270427-22
Ring Network
270427-23
Figure 3.10. SDLC Networks
10-34
intJ 83C152 HARDWARE DESCRIPTION
Full duplex is the simultaneous transmission and recep- expansion plans become a mute issue. However, it is
tion of data. Full duplex uses anywhere from two to strongly suggested .that there always be some allowance
four wires. At least one wire is needed for transmission for future modifications.
and one wire for reception. Usually there will also be a
ground reference on each signal if the distance from Some of the general areas that will impact the overall
station to station is relatively long. Full-duplex opera- scheme on how to incorporate future changes to the
tion in the Cl52 requires that both the receive and the system are:
transmit portion of the GSC are functioning at the
same time. Since both the transmitter and receiver are I) Communication of the change to all the stations or
operating, two CRC generators are also needed. The the primary station.
C152 handles this problem by having one 32-bit CRC
generator and one 16-bit CRC generator. When sup- 2) Maximum distance for communication. This will af-
porting full-duplex operation, the 32-bit CRC generator fect the drivers used and the slot time.
is modified to work as a 16-bit CRC generator. When-
ever the 16-bit CRC is selected, the GSC automatically 3) More stations may be on the line at one time. This
enters the full duplex mode. Half duplex with a 16-bit may impact the interframe space or the collision resolu-
CRC is discussed in the following paragraph. tion used.
Half duplex is the alternate transmission and reception 4) If using CSMA/CD without deterministic resolu-
of data over a single common wire. Only one or two tion, any increase in network size will have a negative
wires are needed in half-duplex systems. One wire is impact on the average throughput of the network and
needed for the signal and if the distance to be covered is lower the efficiency. The user will have to give careful
long there will also be a wire for the ground reference. consideration when deciding how large a system can
In half-duplex mode, only the receiver or transmitter ultimately be and still maintain adequate performance.
can operate at one time. When the receiver or transmit-
ter operates is determined by user software, but typical-
ly the receiver will always be enabled unless the GSC is 3.5.3 DMA SERVICING OF GSC CHANNELS
transmitting. When using the CI52 in half-duplex and There are two sources that can be used to control the
the receiver is connected to the transmitter it is possible GSC. The first is CPU control and the second is DMA
that a station will receive its' own transmission. This
control.
can occur if a broadcast address is sent, the address
mask register(s) are filled with all Is, or the address CPU control is used when user software takes care of
being sent matches the sending' stations address the tasks such as: loading the TFIFO, reading the RFI-
through the use of the address masking registers. The FO, checking the status flags, and general tracking of
receiver must be disabled by the user while transmitting the transmission process. As the number of tasks grow
if any of these conditions will occur, unless the. user and higher da:ta transfer rates arc used, the overhead
wants a station to receive its own transmission. The required by the CPU becomes the dominant consump-
receiver is disabled by clearing GREN (and GAREN if tion of time. Eventually, a point is reached where the
used). Half-duplex operation in the CI52 is supported CPU is spending 100% of its tillle responding to the
with either 16-bit. or 32-bit CRCs.. Whenever a 32-bit needs of the GSC. An alternative is to have the DMA
CRC is selected, only half-duplex operation can be sup- channels control the GSC.
ported by the GSC. It is possible to simulate full-duplex
operation with a 32-bit CRC, but this would require. A detailed explanation on the general use of the DMA
that the CRC be performed with software. Calculating channels is covered in Section 4. In this section only
the CRC with the CPU would greatly reduce the data those details required for the use of the DMA channels
rateS that could be used with the GSC. Whenever a 16- with the GSC will be covered.
bit CRC is selected, full-duplex operation is automati-
cally chosen and the GSC must be reconfigured if half- The DMA channels can be configured by user software
duplex operation is preferred. so that the GSC data transfers are serviced by the
DMA controller. Since there are two DMA channels,
3.5.2 PLANNING FOR NETWORK CHANGES one channel can be used to service the receiver, and one
AND EXilANSIONS channel can be used to service the transmitter. In using
the DMA channels, the CPU is relieved of much of the
A complete explanation on how to plan for network time required to do the basic servicing of the GSC buff-
expansion will not be covered in this manual as there ers. The types of servicing that the DMA channels can
are far too many possibilities that would need to be provide are: loading of the transmit FIFO, removing
discussed. But there are several areas that will have data from the receive FIFO, notification of the CPU
major impact when allowing for changes in the system. when the transmission or reception has ended, and re-
In cases where there will never be any changes allowed, sponse to certain error conditions. When using the
10-35
inter 83C152 HARDWARE DESCRIPTION
DMA channels the source or destination of the data that will be received, up to 64K. If not using the Done
intended for serial transmission can be internal data flag, then asc servicing would be driven by the receive
memory, external data memory" or any of the SFRs. Done (RDN) flag and/or interrupt: RDN is set when
the EOF is detected. When using the RDN flag, RFNE
The only tasks required after initialization of the DMA should also be checked to insure that all the data has
and GSC registers are enabling the proper interrupts been emptied out of the receive FIFO.
and informing the DMA controller when to start. After
the DMA channels are started all that is required of the The byte count register is used for all transmissions and
CPU is to respond to error conditions or wait until the this means that all packets going out will have to be of
end of transmission. the same length or the length of the packet to be sent
will have to be known prior to the start of transmission.
Initialization of the, DMA channels requires setting up When using the DMA channels to service the GSC
the control, source, and destination address registers. transmitter, there is no' practical way to disable the
On the DMA channel servicing the receiver, the con- Done flag. This is' because the transmit done flag
trol register needs to be loaded as follows: DCONn.2 = (TDN) is set when the transmit FIFO is empty and the
0, this sets the transfer mode so that response is to GSC last message bit has been transmitted. But, when using
interrupts and put the DMA control in alternate cycle the DMA channel to service the transmitter, loads to
mode; DCONn.3 = 1, this enables the demand mode; the TFIFO continue to occur until the byte count
DCONn.4 = 0, this clears the automatic increment reaches o. This makes it impossible to use TDN as a
option for the source address; and DCONn.5 = I, this flag to stop the DMA transfers to TFIFO. It is possible
defines the source as SFR. The DMA channel servicing 10 examine some other registers or conditions, such as
the receiver also needs its source address register to the current byte count, to determine when to stop the
contain the address of RFIFO (SARHN = XXH, DMA transfers to TFIFO, but this is not recommended
SARLN " OF4H). On the DMA channel servicing the as a way to service the DMA and GSC when transmit-
transmitter, the control register needs to be loaded as ting because frequent reading ofthe DMA registers will
follows: DCONn.2 = 0; DCONn.3 = I; DCONn.6 = cause the effective DMA transfer rate to slow down.
0, this clears the automatic increment option for the
destination address; and DCONn.7 = I, this sets the When using the DMA channels, initialization of the
destination as SFR. The ,DMA channel serving the GSC would be exactly the same as normal except that
transmitter also requires that its destination address TSTAT.O = 1 (DMA), this informs the GSC that the
register contains the address of TFIFO (DARHN = DMA channels are going to be used to service the GSC.
XXH, DARLN = 85H). Assuming that DCONO Although only TSTAT is written to, both the receiver
would be serving the receiver ami DCONI the trans- and transmitter use this same DMA bit.
mitter, DCONO would be load"d with XXIOIOXOB
and DCONI would be loaded with IOXXIOXOB. The The interrupts EGSTE (IEN1.S), GSC transmit error;
contents of SA RHO and DARHI do not have any im- EGSTV (lEN 1.3), GSC transmit valid; EGSRE
pact when using internal SFRs as the source or destina- (IEN1.l), GSC receive error; and EGSRV (IEN1.0),
tion. GSC receive valid; need to be enabled. The DMA inter-
rupts are normally not used when servicing the GSC
When using the DMA channels to service the GSC, the with the DMA channels. To ensure that the DMA in-
byte count registers will also need to be initialized. terrupts are not responded to is a function of the user
software and should be checked by the software to
The Done flag for the DMA channel servicing the re- make sure they are not enabled. Priority for these inter-
ceiver should be used if fixed packet lengths only are rupts 'can also be set at this'time. Whether to use high
being transmitted or to insure that memory is not over- or low priority needs to be decided by the user. When
written by long received data packets. Overwriting of responding to the GSC interrupts, if a buffer is being
data can occur when using a smaller buffer than the used to store the GSC information, then the DMA reg-
packet size. In these cases the servicing of the DMA isters used for the buffer will probably need updating.
and/or GSC would be in response, to the DMA Done
flag when the byte count reaches zero. After this initialization, all that needs to be done when
the GSC is actually going to be used is: load the byte
In some cases the buffer size is not the limiting factor count, set-up the source addresses for the DMA chan-
and the packet lengths will be unknown. In these cases nel servicing the transmitter, set-up the destination ad-
it wpuld be desirable to eliminate the function of the dresses for the DMA channel servicing the receiver,
Done flag. To effectively disable the Done flag for the and start ,the DMA transfer. The GSe enable bits
DMA channel servicing the receiver, the byte count should be set first and then the GO bits for the DMA.
should be set to some number larger than any packet This initiates the data transfers.
10-36
83C152 HARDWARE DESCRIPTION
This simplifies the maintenance of the GSC and can Initialization of the system can be broken down into
make the implementation of an external buffer for several steps. First, are the assumptions of each net-
packetized information automatic. work station.
An external buffer can be used as the source of data for The first assumption is that the type of data encoding
transmission, or the destination of data from the receiv- to be used is predetermined for the system and that
er. In this arrangement, the message size is limited to each station will adhere to the same basic rules defining
the RAM size or 64K, whichever is smaller. By using that encoding. The second assumption is that the basic
an external buffer, the data can be accessed by other protocol and line discipline is predetermined and
devices which may want access to the serial data. The known. This means that all stations are using CSMAI .
amount of time required for the external data moves CD or SDLC or whatever, and that all stations are
will also decrease. Under CPU control, a "MOVX" either full or half duplex. The third assumption is that
command would take 24 oscillator periods to complete. the baud rate is preset for the whole system. Although
Under DMA control, external to internal, or internal to the baud rate could probably be determined by the mi-
external, data moves take only 12 oscillator periods. croprocessor just by monitoring the link, it will make it
much simpler if the baud rate is known in advance.
3.5.4 BAUD RATE One of the first things that will be required during sys-
tem initialization is the assignment of unique addresses
The GSC baud rate is determined by the contents of the
for each station. In a two-station only environment this
SFR, BAUD, or the external clock. The formula used
is not necessary and can be ignored. However, keep in
to determine the baud rate when using the internal
clock is: mind, that all systems should be constructed for easy
future expansions. Therefore, even in only a two station
(fosc)/«BAUD+ 1)*8) system, addresses should be assigned. There are three
basic ways in which addresses can be assigned. The
For example if a 12 MHz oscillator is used the baud first, and most common is preassigned addresses that
rate can vary from: are loaded into the station by the user. This could be
done with a DIP-switch, through a keyboard. The sec-
12,000,000/((0+1)*8) = 1.5 MBPS ond method of assigning addresses is to randomly as-
sign an address and then check for its uniqueness
to: throughout the system, and the third method is to
make an inquiry to the system for the assignment of a
12,000,000/((255+ 1)'8) = 5.859 KBPS unique address. Once the method or address assignment
is determined, the method should become part of the
There are certain requirements that the external clock specifications for the system to which all additions will
will need to meet. These requirements are specified in have to adhere. This, then, is the linal assumption. .
the data sheet. For a description of the use of the GSC
with external clock please read Section 3.5.11. The negotiation process may IIllt be clear for some
readers. The following two procedures are given as a
guideline for dynamic address aSSi[\lIlllelll.
3.5.5 INITIALIZATION
In the first procedure, a station assumes a random ad-
Initialization can be broken down into two major com- dress and then checks for its uniquelless throughout the
ponents, I) initialization of the component so that its system. As a station is initialized into the system it
serial port is capable of proper communication; and 2) sends out a message containing its assumed address.
initialization of the system or a station so that intelligi- The format of the message should be such that any
ble communication can take place. station decoding the address recognizes it as a request
for initialization. If that address is already used, the
Most of the initialization of the component has already receiving station returns a message, with its own ad-
been discussed in the previous sections. Those items not dress stating that the address in question is already tak-
covered are the parameters required for the component en. The initializing station then picks another address.
to effectively communicate with other components. When the initializing station sends its inquiry for the
These types of issues are common to both system and address check, a timer is also started. If the timer ex-
component initialization and will be covered in the fol- pires before the inquiry is responded to, then that sta-
lowing text. tion assumes the address chosen is okay.
10-37
83C152 HARDWARE DESCRIPTION
In the second procedure, an initializing station asks for In Raw Receive, the transmitter should be externally
an address assignment from the system. This requires connected to the receiver. To do this a port pin should
that some station on the link take care of the task of be used to enable an external device to connect the two
maintaining a record of which addresses are used. This pins together. In Raw Receive mode the receiver acts as
station will be called station-I. When the initializing normal except that all bytes following the BOF are
station, called station-2, gets on the link, it sends out a loaded into the receive FIFO, including the CRe. Also
message with a broadcast address .. The format of the address recognition is not active but needs to be per-
message should be such that all other stations on the formed in software. IfSDLC is selected as the protocol,
link recognize it as a request for address assignment. zero-bit deletion is still enabled. The transmitter still
Part of the message from station-2 is a random number operates as normal and in this mode most of the trans-
generated by the station requesting the address. Sta- mitter functions and an external transceiver can be test-
tion-2 then examines all received messages for this ran- ed. This is also the only way that the CRC can be read
dom number. The random number could be the aadress by the CPU, but the CRC error bit will not be set.
of the received message or could be within the informa-
tion section of a broadcast frame. All t he stations, ex-
cept station-I, on the link should ignore the initializa- 3.5.7 EXTERNAL DRIVER INTERFACE
tion request. Station-I, upon receiving the initialization
A signal is provided from the CI52 to enable transmit-
request, assigns an address and returns it to station-2.
ter drivers for the serial link. This is provided for sys-
Station-I will be required to format t he message in such
tems that require more than what the GSC ports are
a manner so that all stations on the link recognize it as
capable of delivering. The voltage and currents that the
a response to initialization. This means that all stations
GSC is capable of providing are the same levels as those
except station-2 ignore the return message.
for normal port operation. The signal used to enable the
eXlernal drivers is DEN. No similar signal is needed for
3.5.6 TEST MODES 1he receiver.
There arc lwo test modes associated with the GSC that DEN is aClive one hil time before transmission begins.
arc made available to the user. The test modes are [n CSMA/CD DEN remains active for two bit times
named Raw Receive and Raw Transmit. The test after the CRC is transmitted. In SDLC DEN remains
modes arc sckcted by the proper setting of the two active until the last bit orthe EOF is transmitted.
mode bits in GMOD (MO = GMOD.5, MI =
GMOD.6). [I'M I.MO = 0,1 then Raw Transmit is se-
lected. If M I.MO = 1,0 then Raw Receive is enabled. 3.5.8 JITTER (RECEIVE)
The 32-bit eRC cannot be used in any of the test
Data jitter is the difference between the actual transmit-
modes, or else CRC errors will occur.
ted waveform and the exact calculated value(s). In
NRZI, data jitter would be how much the actual wave-
In Raw Transmit, lhe transmit output is internally con-
form exceeds or falls short of one calculated bit time. A
nected to the Receiver input. This is intended to be
bit time equals Ilbaud rate. If using Manchester encod-
used as a local loop-back test mode, so that all data
ing, there can be two transitions during one bit time as
written to the transmitter will be returned by the re-
shown in Figure 3.11. This causes a second parameter
ceiver. Raw Transmit can also be used to transmit user
to be considered when trying to figure out the complete
data. If Raw Transmit is used in this way the data is
data jitter amount. This other parameter is the half-bit
emitted with no preamble, flag, address, CRC, and no
jitter. The half-bit jitter is comprised of the difference in
bit insertion. The data is still encoded with whatever
time that the half-bit transition actually occurs and the
format is selected, Manchester with CSMAICD, NRZI
calculated value. Jitter is important because if the tran-
with SDLC or as NRZ if external clocks are used. The
sition occurs too soon it is considered noise, and if the
receiver still operates as normal and in this mode most
transition occurs too late, then either the bit is missed
of the receive functions can be tested.
or a collision is assumed.
10-38
intJ 83C152 HARDWARE DESCRIPTION
LOGICAL
VALUE
o o o
MANCHESTER
ENCODING
,
.. , - - - "1" BIT TIME ----_0---- "1" BIT TIME - - - - . , , ,
(8 X BAUD) , • "
RECEIVt
SAMPLING'
RATE
j-----..-...,.... ' •• ~r-...----...-y
I
... &-----_....
RECEIVED , ::: I
DATA' I' I' I ,
,,;..---
... "1" BIT TI~E - - - - - - - - "0" BIT TIME - - - - . , , ,
... ,
, ,
I
I
I
, I
• _____
,
RECEIVED I I
,
...
I , I
DATA
I
I , I
I , I , I
,I
270427-24
Figure 3.11. Jitter
3.5.9 Transmit Waveforms In CSMA/CD the preamble consists of alternating Is
and Os. Consequently, the preamble looks like the
The GSC is capable of three types of data encoding, waveform in Figure 3.13A and 3.lm.
Manchester, NRZI, and NRZ. Figure 3.12 shows ex-
amples of all three types of data encoding.
3.5.11 External Clocking
3.5.10 Receiver Clock Recovery To select external clocking, the user is given three
choices. External clocking can be used with the trans-
The receiver is always monitored at eight times the mitter, with the receiver, or with both. To select exter-
baud rate frequency, except when an external clock is nal clocking for the transmitter, XTCLK (GMOD.7)
used. When using an external clock the receiver is load- has to' be set to a 1. To select external clocking for the
ed during the clock cycle. receiver, XRCLK (PCON.3) has to be set to a 1. Set-
ting both bits to I forces external clocking for the re-
In CSMA/CD mode .the receiver synchronizes to the ceiver and transmitter. The minimum frequency the
transmitted- data during the preamble. If a pulse is de- GSC can be externally clocked at is 0 Hz (D.C.).
tected as being too short it is assumed to be' noise or a
collision. If a pulse is too long it is assumed to be a The external transmit clock is applied to pin 4 (TXC),
collision or an idle condition. P1.3. The external receive clock is applied to pin 5
(RXC), PIA. To enable the external clock function on
In SDLC the synchronization takes place during the the port pin, that pin has to be set to a 1 in the appro-
BOF flag. In addition, pulses less than four sample pe- priate SFR, PI.
riods are ignored, and assumed to be noise. This sets a
lower limit on the pulse size of received zeros.
• 10-39
83C152 HARDWARE DESCRIPTION
,
, BIT ,
:04-TIt.4E~:
'0 o o
NRZ
L
NRZj
"
270427-25
Figure 3.12. Transmit Waveforms
Whenever the external clock option is used, the format (AMSKO, AMSKI) in the C152. These function with
of the transmitted and received data is restricted to the GSC receiver only. The transmitted address is treat-
NRZ encoding and the protocol is restricted to SDLC. ed like any other data. The address is transmitted under
With external clock, the bit stuffing/stripping is still software control by placing the address byte(s) at the
active with SDLC protocol. proper location (usually first) in the sequence of bytes
to be output in the outgoing packet.
3.5.12 Determining Receiver Errors The C1S2 can have up to four different 8-bit addresses
It is possible that several receiver error bits will be set or two different l6-bit addresses assigned to each sta-
in response to a single cause. The multiple errors that tion. When using 16-bit addressing, ADRO:ADRI form
can occur are: one address and ADR2:ADR3 form the second ad-
dress. If the receiver is enabled, it looks for a matching
AE and CRCE may both be set when an alignment address after every BOF flag is detected. As the data is
error occurs due to a bad CRC caused by the mis- received, if the 8th (or 16th) bit does not match the
aligned frame. address recognition circuitry, the rest of the frame is
ignored and the search continues for another flag. If the
RCABT, AE, and CRCE may be set when an abort address does match the address recognition circuitry,
occurs. the address and all subsequent data is passed' into the
receive FIFO until the EOF flag or an error occurs.
OYR, AE, and CRCE may be set when a overrun oc- The address is not stripped and is also passed to
curs. RFIFO.
The address masking registers, AMSKO and AMSKl,
In order to determine the correct cause of the error a work in conjunction with ADRO and ADRI respective-
specific order should be followed when examining the ly to identify "don't care" bits. A 1 in apy position in
error bits. This order is: the AMSKn register makes the respective bit in the
ADRn register irrelevant. These combinations can then
I)OVR
be used for form group addresses. If the masking regis-
2) RCBAT ters are filled with all Is, the C152 will receive all pack-
3)AE ets, which is called the promiscuous mode. If I6-bit
4)CRCE addressing is' used, AMSKO:AMSKI form one 16-bit
address mask.
3.5.13 Addressing
There are four 8-bit address registers (ADRO, ADR1,
ADR2, ADR3) and two 8-bit address mask registers
10-40
83C152 HARDWARE DESCRIPTION
CSMA/CO Clock Recovery
I 0 o o o 0 0
IDEAL WAVEFORM
I
I I I I I I I I I I 1 I I I I I I
ax SAMPLING RATE 1111111111111111111111 1111111111111111 1111111111111111\111111111111111 !tllllill "IIIIIII!O III} 1111 11111111111111111111111111111111111111111111111
ACTUAL WAVEFORM
RECOVERED BIT
STREAM CLOCK
270427-26
Figure 3.13A. Clock Recovery
SOLC Clock Recovery
o 000 o I 0: 0:
IDEAL WAVEFORM
I I I I I I I I I I I I I I I I I
ax SAMPLING RATE 111111111111111111111111111111111111111 11111111111111111111111111111111111111111111111111111111111III III 1IIIIIIIIIIIIllllllillillllllllillll
ACTUAL WAVEFORM
RECOVERED BIT
STREAM CLOCK
270427-27
Figure 3.138. Clock Recovery
10-41
inter 83C152 HARDWARE DESCRIPTION
3.6 GSC Operation If the receiver detects a collision during reception in
CSMA/CD mode and if any bytes have been loaded
3.6.1 Determining Line Discipline . into the reccive FIFO, the RCABT flag is set. The GSC
hardware Ihen halts reception and resets GREN. The
In normal operation the GSC uses full or half duplex user software needs to filter any collision fragment data
operation. When using a 32-bit CRC (GM?D.3 = !~, which may have been received. If the collision occurre~
operation can only be half duplex. If usmg a l6-blt prior to the d.:ta being loaded into RFIFO the CPU IS
CRC (GMOD.3 =i' 0), full duplex is selected by de- not nolilied and the receiver is left enabled. At the end
fault. When using. a 16-bit CRC the receiver can be of a receplion Ihe RDN bit is set and GREN is cleared.
turned off while transmitting (RSTA T.! = 0), and the In HAllEN mode this causes an acknowledgement to
transmitter can be turned off during reception be Iran"llillcd if the frame did not have a broadcast or
(TSTAT.I = 0). This simulates half-duplex operation mulli-casl address. The user software can enable the
when using a I6-bit CRC. inicrrupl for RDN to determine when a frame is com-
plelcd.
Normally, HDLC uses a I6-bit CRC, so half duplex is
determined by turning off the receiver or transmitter.
In DMA mode the interrupts are generated by the in-
This is so that the receiver will not detect its own ad-
lernal "transmit/receive done" (TDN,RDN) condi-
dress as transmission takes place. This also needs to be
lions. When Ihe CPU responds to TDN or RDN,
done when using CSMA/CD with a 16-bit CRC for the
checks arc performed to see if the transmit underrun
same reason:
error has occnrred. The underrun condition is only
chccked when using the DMA channels.
3.6.2 CPU/DMA CONTROL OF THE GSC
Upon power up the CPU mode is initialized. General
The data for Iransmission or receplion can be handled DMA control is covcred in Section 4.0. DMA control
by either the CPU (TSTAT.O = 0) or DMA controller of the GSC is covered in Section 3.5.4. IfDMA is to be
(TSTAT.O = I). This allows the user two sets of flags used for serving the GSC, it must be configured into the
to control the FIFO. Associated with these flags are serial channel demand mode and the DMA bit in
interrupts, which may be enabled by the user software. TSTAT has to be set.
Either one or hoi h sets of flags may be used at the same
time.
3.6.3 COLLISIONS AND BACKOFF
In CPU control mode the flags (RFNE,TFNF) are gen-
The actions that are taken by the GSC if a collision
erated by the condition of the receive or transmit FI-
occurs while transmitting depend on where the colli-
FO's. After loading a byte into the transmit FIFO,
sion occurs. If a collision occurs in CSMA/CD mode
there is a one machine cycle latency until the TFNF
following the preamble and BOF flag, the TCDT flag is
flag is updated. Bccause of this latency, the status of
set and the transmit hardware completes a jam. When
TFNF should nol be checked immediately following
this type of collision occurs, there will be no automatic
the instruction to load the transmit FIFO. If using the
retry at transmission. After the jam, control is returned
interrupts to service the transmit FIFO,the one ma-
to the CPU and user software must then initiate what-
chine cycle of latency must be considered if the TFNF
ever actions are necessary for a proper recovery. The
flag is checked prior 10 leaving the subroutine.
possibility that data might have been loaded into or
from the GSC deserves special consideration. If these
When using the CPU for control, transmission normal-
fragments of a message have been passed on to other
ly is initiated by setting the TEN bit (TSTAT.l) and
devices, user software may have to perform some exten-
then writing to TFIFO. TEN must be set before load-
sive error handling or notification. Before starting a
ing the transmit FIFO, as setting TEN clears the trans-
new message, the transmit and receive FIFOs will need
mit FIFO. TCDCNT should also be checked by user
to be cleared. If DMA servicing is being used the point-
software and cleared if a collision occurred on a prior
ers must also be reinitialized. It should be noted that a
transmission.
collision should never occur after the BOF flag in a well
designed system, since the system slot time will likely
To' enable the receiver, GREN (RSTAT.!) is set. After
be less than the preamble length. The occurrence of
GREN is set, the GSC begins to look for a valid BOF.
such a situation is normally due to a station on the link
After detecting a valid BOF the GSC attempts to
that is not adhering to proper CSMA/CD protocol or
match the received address byte(s) against the address
is not using the same timings as the rest of the network.
match registers. When a match occurs the frame is
loaded into the GSC. Due to the CRC strip hardware,
A collision occurring during the preamble or BOF flag
there is a 40 or 24 bit time delay following the BOF
is the normal type of collision that is expected. When
until the first data byte is loaded into RFIFO if the 32
this type of collision occurs the GSC automatically
or 16 bit CRC is chosen. If the end offrame is detected
handles the retransmission attempts for as many as
before data is loaded into the receive FIFO, the receiver
eight tries. If on the eighth attempt a collision occurs,
ignores that frame.
10-42
inter 83C152 HARDWARE DESCRIPTION
the transmitter is disabled, although the jam and back- are more than 256 stations involved in the collision
off are performed. If enabled, the CPU is then inter- there would be no resolution since at least two of the
rupted. The user software should then determine what stations will always have the same backoff interval se-
action to take. The possibilities range from just report- lected.
ing the error and aborting transmission to reinitializing
the serial channel registers and attempt retransmission. All the stations monitor the link as long as that station
is active, even if not attempting to transmit. This is to
If less than eight attempts are desired TCDCNT can be ensure that each station always defers the minimum
loaded with some value which will reduce the number amount of time before attempting a transmission and so
of collisions possible before TCDCNT overflows. The that addresses are recognized. However, the collision
value loaded should consist of all Is as the least signifi- detect circuitry operates slightly differently.
cant bits, e.g. 7, OFH, 3FH. A solid block of Is is sug-
gested because TCDCNT is used as a mask when gen- In normal back-off mode, a transmitting station always •
erating the random slot number assignment. The monitors the link while transmitting. If a collision is I
TCDCNT register operates by shifting the contents olle detected one or more of the transmitting stations apply
bit position to the left as each collision is detected. As the jam signal and all transmitting stations enter the
each shift occurs a I is loaded into the LSB. When back-off algorithm. The receiving stations also con-
TCDCNT overflows, GSC operation stops and the stantly monitor for a collision but do not take part in
CPU is notified by the setting of the TCDT bit which the resolution phase. This allows a station to try to
can flag an interrupt. transmit in the middle of a resolution period. This in
turn mayor may not cause another collision. If the new
The amount of time that the GSC has before it must be station trying to transmit on the link does so during an
ready to retransmit after a collision is determined by unused slot time then there will probably not be a colli-
the mode which is selected. The mode is determined sion. If trying to transmit during a used slot time, then
MO (GMOD.5) and MI (GMOD.6). If MO and MI there will probably be a collision. The actions the re-
equal 0,0 (normal backoft) then the minimum period ceiver does take when detecting a collision is to just
before retransmission will be either the interframe stop receiving data if data has not been loaded into
space or the backoff period, whichever is longer. If MO RFIFO or to stop reception, clear receiver enable
and MI equal 1,1 (alternate backoft) then the minimum (REN) and set the .receiver abort flag (RCABT -
period before retransmission will be the interframe RSTAT.6).
space plus the backoff period. Both of these are shown
in Figure 3.4. Alternate backoff must be enabled if us- If deterministic resolution is used, the transmitting sta-
ing deterministic resolution. If the GSC is not ready to tions go through pretty much the same process as in
retransmit by the time its assigned slot becomes avail- normal back-off, except that the slots are predeter-
able, the slot time is lost and the station must wait until mined. All the receivers go through the back-off algo-
the collision resolution time period has passed. rithm and may only transmit during their assigned slot.
Instead of waiting for the collision resolution to pass,
the transmission could be aborted. The decision to 3.6.4 SUCCESSFUL ENDING OF
abort is usually dependent on the number of stations on TRANSMISSIONS AND RECEPTIONS
the link and how many collisions have already oc- In both CSMA/CD and SDLC modes, the TDN bit is
curred. The number of collisions can be obtained by set and TEN cleared at the end of a successful trans-
examining the register, TCDCNT. The abort is normal- mission. The end of the transmission occurs when the
ly implemented by clearing TEN. The new transmis- TFIFO is empty and the last byte has been transmitted.
sion begins by setting TEN and loading TFIFO. The In CSMA/CD the user shOUld clear the TCDCNT reg-
minimum amount of time available to initiate a retrans- ister after successful transmission.
mission would be one interframe space period after the
line is sensed as being idle. At the end of a successful reception, the RDN bit is set
and GREN is cleared. The end of reception occurs
As the number of stations approach 256 the probability when the EOF flag is detected by the GSC hardware.
of a successful transmission decreases rapidly. If there
10-43
inter 83C152 HARDWARE DESCRIPTION
The length includes the two bit Begin Of Frame (BOP)
3.7 Register Descriptions
flag in CSMA/CD but does not include the SDLC flag.
ADRO,I,2,3 (9SH, OASH, OBSH, OCSH) - Address In SDLC mode, the HOF is an SDLC flag, otherwise it
Match Registers 0,1,2,3 - Contains the address match is two consecutive ones. Zero length is not compatible
values which determines which data will be accepted as in CSMA/CD mode. The user software is responsible
valid. In 8 bit addressing mode, a match with any of the for setting or clearing these bits.
four registers will trigger acceptance. In 16 bit address-
ing mode a match with ADRI :ADRO or ADR3:ADR2 . GMOD.3 (CT) - CRC Type - If set, 32 bit AUTODIN-
will be accepted. Addressing mode is determined in II-32 is used. If cleared, 16 bit CRC-CCITT is used.
GMOD(AL). The user software is responsible for setting or clearing
this flag.
AMSKO,I (ODSH, OESH) - Address Match Mask 0,1 -
Identifies which bits in ADRO,I are "don't care" bits. GMOD.4 (AL) - Address Length - If set, 16 bit ad-
Writing a one to a bit in AMSKO,I masks out that dressing is used. If cleared, 8 bit addressing is used. In 8
corresponding bit in ADDRO,1. hit mode a match with any of the 4 address registers
will be accepted (ADRO, ADRI, ADR2, ADR3).
BAUD (94H) - GSC Baud Rate Generator - Contains "Don't Care" bits may be masked in ADRO and ADRI
the value of the programmable baud rate. The data rate with AMSKO and AMSKI. III 16 bit mode, addresses
will equal (frequency of the oscillator)/«BAUD + I) arc matched against "ADR I :ADRO" or "ADR3:
X (8». Writing to BAUD actually stores the value in a ADR2". Again, "Don't Care" bits in ADRI:ADRO
reload register. The reload register contents are copied can be masked in AMSK 1:AMSKO. A received address
into the BAUD register when the Baud register decre- of all ones will always be recognized in any mode. The
ments to OOH. Reading BAUD yields the current timer IIser software is responsible for setting or clearing this
value. A read during GSC operation will give a value flag.
that may not be current because the timer could decre-
ment between the time it is read hy the CPU and by the GMOD.5,6 (MO,MI) - Mode Select - Two test modes,
time the value is loaded into its destination. an optional "alternate backot'r' mode, or normal back-
off can be enabled with these two bits. The user soft-
BKOFF (OC4H) - Backoff Timer - The backoff timer is ware is responsible for setting or clearing the mode bits.
an eight bit count-down timer with a clock period equal
to one slot time. The backoO' time is used in the MI MO Mode
CSMA/CD collision resolution algorithm. The user 0 0 Normal
software may read the timer but the value may be inval- 0 1 Raw Transmit
id as the timer is clocked asynchronously to the CPU. 1 0 Raw Receive
Writing to OC4H will have no effect. 1 1 Alternate Hackoff
GMOD(84H) In raw receive mode, the receiver operates as normal
7 6 543 2 o except that all the bytes following the BOF are loaded
into the receive FIFO, including the CRC. The trans-
I XTCLK I M1 I MO I AL I CT I PL1 PLO PR mitter operates as normal.
Figure 3.14. GMOD
In raw transmit mode the transmit output is internally
GMOD.O (PR) - Protocol - If set, SDLC protocols with connected to the receiver' input. The internal connec-
NRZI encoding and SDLC flags are used. If cleared, tion is not at the actual port pin, but inside the port
CSMA/CD link access with Manchester encoding is latch. All data transmitted is done without a preamble,
used. The user software is responsible for setting or flag or zero bit insertion, and without appending a
clearing this flag. CRC. The receiver operates as normal. Zero bit dele-
tion is performed.
GMOD.1,2 (PLO,I) - Preamble length
In alternate backoff mode the standard backoff process
PLl PLO LENGTH (BITS) is modified so the the backoff is delayed until the end of
o 0 0 the IFS. This should help to prevent collisions con-
o 1 8 stantly happening because the IFS time is usually larger
I 0 32 than the slot time.
1 1 64
10-44
infef 83C152 HARDWARE DESCRIPTION
GMOD.7 (XTCLK) - External Transmit Clock - If set PCON(087H)
an external IX clock. is used for the transmitter. If 76543210
cleared the internal baud rate generator provides the
transmit clock. The input clock is applied to PI. 3
(T X C). The user software is responsible for setting or
clearing this flag. External receive clock is enabled by PCON contains bits for power control, LSC control,
setting PCON.3. DMA control, and GSC control. The bits used for the
GSC are PCON.2, PCON.3, and PCON.4.
IFS (OA4H) - Interframe Spacing - Determines the
number of bit times separating transmitted frames in
CSMA/CD and SDLC. A bit time is equal to Ilbaud
rate. Only even interframe space periods can be used.
The number written into this register is divided by two
and loaded in the most significant seven bits. Complete
PCON.2 (GFIEN) - GSC Flag Idle Enable - Setting
GFIEN to a 1 caused idle flags to be generated between
transmitted frames in SDLC mode. SDLC idle flags
consist of 01111110 flags creating the sequence
01111110011111110 ...... 011111110. A possible side
III
I
interframe space is obtained by counting this seven bit effect of enabling GFIEN is that the maximum possible
number down to zero twice. A user software read of latency from writing to TFlFO until the first bit is
this register will give a value where the seven most sig- transmitted increased from approximately 2 bit-times
nificant bits gives the current count value and the least to around 8 bit-times. GFIEN has no effect with
significant bit shows a one for the first count-down and CSMAlCD.
a zero for the second count. The value read may not be
valid as the timer is clocked in periods not necessarily PCON.3 (XRCLK) - GSC External Receive Clock En-
associated with the CPU read of IFS. Loading this reg- able - Writing a 1 to XRCLK enables an external clock
ister with zero results in 256 bit times. to be applied to pin 5 (Port 1.4). The external clock is
used to determine when bits are loaded into the receiv-
MYSLOT (OF5H) - Slot Address Register er.
76543210
PCON.4 (GAREN) - GSC Auxiliary Receiver Enable
Bit - This bit needs to be set to a I to enable the recep-
tion of back-to-back SDLC frames. A back-to-back
SDLC frame is when the EOF and Il( >I' is shared be-
Figure 3.15. MYSLOT tween two sequential frames intended I'lr the same sta-
tion on the link. If GAREN contains a 0 then the re-
MYSLOT.O, I, 2, 3, 4, 5 - Slot Address - The six ad- ceiver wilt be disabled upon reception of the EOF and
dress bits choose I of 64 slot addresses. Address 63 has by the time user software re-enables t he receiver the
the highest priority and address I has the lowest. A first bites) may have already passed. in the caSl! of back-
value of zero will prevent a station from transmitting to-back frames. Setting GAREN to a 1, prl!vents the
during the collision resolution period by waiting· until receiver from being disabled by the EOF but GREN
all the possible slot times have elapsed. The user soft- will be cleared and can be checke(l by user software to
ware normally initializes this address in the operating determine that an EOFhas been received. GAREN has
software. no effect if the GSC is in CSMA/CD mode.
MYSLOT.6 (DCR) - Deterministic Collision Resolu- PRBS (OE4H) - Pseudo-Random Binary Sequence -
tion Algorithm - When set, the alternate collision reso- This register contains a pseudo-random number to be
lution algorithm is selected. Retriggering of the IFS on used in the CSMA/CD backoff algorithm. The number
reappearance of the carrier is also disabled. When using is generated by using a feedback shift register clocked
this feature Alternate Backoff Mode must be selected by the CPU phase clocks. Writing all ones to the PRBS
and several other registers must be initialized. User will freeze the value at all ones. Writing any other value
software must initialize TCDCNT with the maximum to it will restart the PRBS generator. The PRBS is ini-
number of slots that are most appropriate for a particu- tialized to all zero's during RESET. A read of location
lar application. The PRBS register must be set to all OE4Hwill not necessarily give the seed used in the
ones. This disables the PRBS by freezing it's contents at backoff algorithm because the PRBS counters are
OFFH. The backoff timer is used to count down the clocked by internal CPU phase clocks. This means the
number of slots based on the slot timer value setting the contents of the PRBS may have been altered between
period of one slot. The user software is responsible for the time when the seed was generated and before a
setting or clearing this flag. READ has been internally executed.
MYSLOT.7 (DCJ) - D.C. Jam - When set selects D.C.
type jam, when clear, selects A.C. type jam. The user
software is responsible for setting or clearing this flag.
10-45
inter 83C152 HARDWARE DESCRIPTION
RFIFO (OF4H) - Receive FIFO - RFIFO is a 3 byte RSTAT.6 (RCABT) - Receiver Collision/Abort Detect
buffer that is loaded each time the GSC receiver has a - If set, indicates that a collision was detected after data
byte of data. Associated with RFIFO is a pointer that is had been loaded into the receive FIFO in CSMA/CD
automatically updated with each read of the FIFO. A mode. In SDLC mode, RCABT indicates that 7 consec-
read of RFIFO fetches the oldest data in the FIFO. utive ones were detected prior to the end flag but after
data has been loaded into the receive FIFO. AE may
RSTAT (OE8H) - Receive Status Register also be set. The setting of this flag is controlled by the
76543210 GSC.
IORIRCABTIAElcRCEIRDNIRFNEIGRENIHABENI RSTA T. 7 (OVR) - Overrun - If set, indicates that the
receive FIFO was full and new shift register data was
Figure 3.16. RSTAT
written into it. AE and/or CRCE may also be set. The
setting of this flag is controlled by the GSC and it is
RSTAT.O (HABEN) - Hardware Based Acknowledge
cleared by user software.
Enable - If set, enables the hardware based acknowl-
edge feature. The user software is responsible for setting SLOTTM (OBH) - Slot Time - Determines the length of
or clearing this flag. the slot time used in CSMA/CD. A slot time equals
(SLOTTM) X (1 / baud rate). A read of SLOTTM will
RSTAT.I (GREN) - Receiver Enable - When set, the
give the value of the slot time timer but the value may
receiver is enabled to accept incoming frames. The user
be invalid as the timer is clocked asynchronously to the
must clear RFIFO with software before enabling the
CPU. Loading SLOTTM with 0 results in 256 bit
receiver. RFIFO is cleared by reading the contents of
times.
RFIFO until RFNE = O. After each read ofRFIFO, it
takes one machine cycle for the status of RFNE to be TCDCNT (OD4H) - Transmit Collision Detect Count -
updated. Setting GREN also clears RON, CRCE, AE, Contains the number of collisions that have occurred if
and RCABT. GREN is cleared by hardware at the end probabilistic CSMA/CD is used. The user software
of a reception or if any receive errors are detected. The must clear this register before transmitting a new frame
user software is responsible for setting this flag and the so that the GSC backofT hardware can accurately dis-
GSC or user software can clear it. The status of GREN tinguish a new frame from a retransmit attempt.
has no effect on whether the receiver detects a collision
in CSMA/CD mode as the receiver input circuitry al- In deterministic backoff mode, TCDCNT is used to
ways monitors the receive pin. hold the maximum number of slots.
RSTAT.2 (RI.'NE) - Receive FIFO Not Empty - Uset, TFIFO (S5H) - GSC Transmit FIFO - TFIFO is a 3
indicates that the receive FIFO contains data. The re- byte buffer with an associated pointer that is automati-
ceive FIFO is a three byte buffer into which the receive cally updated for each write by user software. Writing a
data is loaded. A CPU read of the FIFO retrieves the byte to TFIFO loads the data into the next available
oldest data and automatically updates the FIFO point- location in the transmit FIFO. Setting TEN clears the
ers. Setting GREN to a one will clear the receive FIFO. transmit FIFO so the transmit FIFO should not be
The status of this flag is controlled by the GSc. It is written to prior to setting TEN. If TEN is already set
cleared if user empties receive .FIFO. transmission begins as soon as data is written to TFI-
FO.
RSTAT.3 (RDN) - Receive Done - If set, indicates the
successful completion of a receiver operation. Will not TSTAT (ODS) - Transmit Status Register
be set if a CRC, alignment, abort, or FIFO overrun
error occurred. The status of this flag is controlled by 76543210
the GSC. LNllNOACKluRITCDTITDNITFNFITENIDMAI
RSTATA (CRCE) - CRC Error - If set, indicates that a Figure 3.17. TSTAT
properly aligned frame was received with a mismatched
CRe. The status of this flag is controlled by the GSC. TSTAT.O (DMA) - DMA Select - If set, indicates that
DMA channels are used to service the GSC FIFO's and
RSTAT.5 (AE) - Alignment Error - In CSMA/CD GSC interrupts occur on TDN and RDN, and also en-
mode, AE is set if the receiver shift register (an internal ables UR to become set. If cleared, indicates that the
serial-to-parallel converter) is not full and the CRC is GSC is operating in its normal mode and interrupts
bad when an EOF is detected. In CSMA/CD the EOF occur on TFNF and RFNE. For more information on
is a line idle condition (see LNI) for two bit times. If DMA servicing please refer to the DMA section on
the CRC is correct while in CSMA/CD mode, AE is DMA serial demand mode (4.2.2.3). The user software
not set and any mis-alignment is assumed to be caused is responsible for setting or clearing this flag.
by dribble bits as the line went idle. In SDLC mode,
AE is set if a non-byte-aligned flag is received. CRCE
may also be set. The setting of this flag is controlled by
the GSc.
10-46
intJ 83C152 HARDWARE DESCRIPTION.
TSTAT.I (TEN) - Transmit Enable - When set causes 3.S Serial Backplane vs. Network
TDN, DR, TCDT, and NOACK flag to be reset and
the TFIFO cleared. The transmitter will clear TEN af-
Environment
ter a successful transmission, a collision during the The C152 GSC port is intended to fulfill the needs of
data, CRC, or end flag. The user software is responsible both serial backplane environment and the serial com-
for setting but the GSC or user software may clear this munication network environment. The serial backplane
flag. If cleared during a transmission the GSC transmit is where typically, only processor to processor commu-
pin goes to a steady state high level. This is the method nications take place within a self contained box. The
used to send an abort character in SDLe. Also DEN is communication usually only encompasses those items
forced to a high level. The end of transmission occurs which are necessary to accomplish the dedicated task
whenever the TFI FO is emptied. for the box. In these types of applications there may not
be a need for line drivers as the distance between the
TSTAT.2 (TFNF) - Transmit FIFO not full - When transmitter and receiver is relatively short. The net-
set, indicates that new data may be written into the work environment; however, usually requires transmis-
transmit FIFO. The transmit FIFO is a three byte buff- sion of data over large distances and requires drivers
er that loads the transmit shift register with data. The and/or repeaters to ensure the data is received on both
status of this flag is controlled by the GSC. ends.
TSTAT.3 (TDN) - Transmit Done - When set, indi-
cates the successful completion of a frame transmission .. 4.0 DMA Operation
If RABEN is set, TDN will not be set until the end of
the IFS following the transmitted message, so that the The C152 contains DMA (Direct Memory Accessing)
acknowledge can be checked. If an acknowledge is ex- logic to perform high speed data transfers between any
pected and not received, TDN is not set. An acknowl- two of
edge is not expected following a broadcast or multi-cast
packet. The status of this flag is controlled by the GSC. Internal Data RAM
Internal SFRs
TSTAT.4 (TCDT) - Transmit Collision Detect - If set, External Data RAM
indicates that the transmitter halted due to a collision.
It is set if a collision occurs during the data or CRC or If external RAM is involved, the Port 2 aJ~)ort 0 ~
if there are more than eight collisions. The status of this are used as the address/data bus, and RD and WR
flag is controlled by the GSC. signals are generated as required.
TSTAT.5 (DR) - Dnderrun - If set, indicates that in Hardware is also implement cd to generate a Hold Re-
DMA mode the last bit was shifted out of the transmit quest signal and await a Hold Acknowledge response
register and that the DMA byte count did not equal before commencing a DMA that involves external
zero. When an underrun occurs, the transmitter halts RAM.
without sending the CRC or the end flag. The status of
this flag is controlled by the GSC. Alternatively, the Hold/Hold Acknowledge hardware
can be programmed to acccpt a llold Rcquest signal
TSTAT.6 (NOACK) - No Acknowledge - If set, indi- from an external device and generatc a Iioid Acknowl-
cates that no acknowledge was received for the previous edge signal in response, to indicate to the requesting
frame. Will be set only if HABEN is set and no ac- device that the Cl52 will not commcnce a DMA to or
knowledge is received prior to the end of the IFS. from external RAM while the Hold Request is active.
NOACK is not set following a broadcast or a multi-
cast packet. The status of this flag is controlled by the
GSC. 4.1 DMA with the SOC 152
TSTAT.7 (LNI) - Line Idle - If set, indicates the re- The C152 contains two identical general purpose 8-bit
ceive line is idle. In SDLC protocol it is set if 15 consec- DMA channels with 16-bit addressability: DMAO and
utive ones are received .. In CSMA/CD protocol, line DMAI. DMA transfers can be executed by either chan-
idle is set ifGRXD remains high for approximately 1.6 nel independent ofthe other, but only by one channel at
bit times. LNIis cleared after a transition on GRXD. a time. During the time that a DMA transfer is being
The status of this flag is controlled by the GSC. executed, program execution is suspended. A DMA
transfer takes one machine cycle (12 oscillator
10-47
intJ 83C152 HARDWARE DESCRIPTION
DMA CHANNEL 0 DMA CHANNEL 1
.I DARHO .. I DARlO I, DARHl I I DARll I,
DESTINATION ADDRESS DESTINATION ADDRESS
.I SARHO II
SOURCE ADDRESS
SARLO I, .I SARHl II
SOURCE ADDRESS
SARL1 I,
BCRHO II BeRlO I, BCRHI I I BCRll I.
BYTE COUNT BYTE COUNT
I DCONO I I DCONl I
DMAO CONTROL DMA 1 CONTROL
PCON
'--'
\.. Two new bits In .PCON control
Hold/Hold Acknowledge logic
270427-28
Figure 4.1. DMA Registers
periods) per byte transferred, except when the destina- Two other bits in DCONn specify the physical source
tion and source are both in External Data RAM. In of the data to be transferred. These are SAS (Source
that case Ihe transfer takes two machine cycles per Address Space) and ISA (Increment Source Address).
byte. The term DMA Cycle will be used to mean the If SAS = 0, the source is in data memory external to
transfer of a single data byte, whether it takes 1 or 2 the C152. If SAS = I, the source is internal. If SAS =
machine cycles. 1 and .ISA = 0, the internal source is an SFR. If SAS
= 1 and ISA = I, the internal source is in the 256-byte
Associated with each channel are seven SFRs, shown in data RAM.
Figure 4.1. SARLn and SARRn holds the low and high
bytes of the source address. Taken together they form a In any case, ifISA = I, the source address is automati-
f6-bit Source Address Register. DARLn and DARHn cally incremented after each byte transfer. If ISA = 0,
hold the low and high bytes of the destination address, it is not.
and together form the Destination Address Register.
BCRLn and BCRHn hold the low and high bytes ofthe The functions of these four control bits are summarized
number of bytes to be transferred, and together form below: '
the Byte Count Register. DCONn contains control and
flag bits. DAS IDA Destination Auto-Increment
0 0 External RAM no
Two bits in DCONn are used to specify the physical 0 1 External RAM yes
destination of the data transfer. These bits are DAS
(Destination Address Space) and IDA (Increment Des- 1 0 SFR no
tination Address). If DAS = 0, the destination is in 1 1 Internal RAM yes
data memory external to the C152. If DAS = I, the SAS ISA Source Auto-Increment
destination is internal to the C152. If DAS = 1 -and
IDA = 0, the internal destination is a Special Function 0 0 External RAM no
Register (SFR). If DAS = 1 and IDA = I, the inter- 0 1 External RAM yes
nal destination is in the 256-byte data RAM. 1 0 SFR no
1 1 Internal RAM yes
In any case, if IDA = I, the destination address is
automatically incremented inter each byte transfer. If
IDA = 0, it is not.
10-48
inter 83C152 HARDWARE DESCRIPTION
There are four modes in which the DMA channel can dress. On-chip hardware then clears the flag (RI, TI,
operate. These are selected by the bits DM and TM RFNE, or TFNF) that initiated the DMA, and decre-
(Demand Mode and Transfer Mode) in DCONn: ments BCRn. Note that since the flag that initiated the
DMA is cleared, it will not generate an interrupt unless
DM TM Operating Mode DMA servicing is held off or the byte count equals O.
0 0 Alternate Cycles Mode DMA servicing may be held off when alternate cycle is
being used or by the status of the HOLD/HLDA logic.
0 1 Burst Mode
In these situations the interrupt for the LSC may occur
1 0 Serial Port Demand Mode before the DMA can clear the RI or TI flag: This is
1 1 External Demand Mode because the LSC is serviced according to the status of
RI and TI, whether or not the DMA channels are being
The operating modes are described below. used for the transferring of data. The GSC does not use
RFNE or TFNF flags when using the DMA channels
so these do not need to be disabled. When using the
4.1.1 ALTERNATE CYCLE MODE DMA channels to service the LSC it is recommended
that the interrupts (RI and TI) be disabled. If the dec-
In Alternate Cycles Mode the DMA is initiated by set- remented BCRn is OOOOH, on-chip hardware then
ting the GO bit in DCONn. Following the instruction
clears the GO bit and sets the DONE bit. The DONE
that set the GO bit, one more instruction is executed,
bit flags an interrupt.
and then the first data byte is transferred from the
source address to the destination address. Then another
instruction is executed, and then another byte of data is 4.1.4 EXTERNAL DEMAND MODE
transferred, and so on in this manner.
In External Demand Mode the DMA is initiated by
Each time a data byte is transferred, BCRn (Byte one of the External Interrupt pins, provided the GO bit
Count Register for DMA Channel n) is decremented. is set. INTO initiates a Channel 0 DMA, and INTl
When it reaches OOOOH, on-chip hardware clears the initiates a Channel 1 DMA.
GO bit and sets the DONE bit, and the DMA ceases.
The DONE bit flags an interrupt. If the external interrupt is configured to be transition-
activated, then each I-to-O transition at the interrupt
pin sets the corresponding external interrupt flag, and
4.1.2 BURST MODE generates one DMA Cycle. Then, BCRn is decrement-
ed. No more DMA Cycles tah place until another
Burst Mode differs from Alternate Cycles mode only in I-to-O transition is seen at the external interrupt pin. If
that once the data transfer has begun, program execu- the decremented BCRn = ()()(Xl II , on-chip hardware
tion is entirely suspended until BCRn reaches OOOOH, clears the GO bit and sets the DONE bit. If the exter-
indicating that all data bytes that were to be transferred
nal interrupt is enabled, it wiIl be serviced.
have been transferred. The interrupt control hardware
remains active during the DMA, so interrupt flags may If the external interrupt is conligured to be level-acti-
get set, but since program execution is suspended, the vated, then DMA Cycles comlllenee when the interrupt
interrupts will not be serviced while the DMA is in pin is pulled low, and continue I"l' as long as the pin is
progress. held low and BCRn is not ()(XXlll. If BCRn reaches 0
while the interrupt pin is still low, the GO bit is cleared.
4.1.3 SERIAL PORT DEMAND MODE the DONE bit is set, alld the DMA ceases. If the exter-
nal interrupt is enabled. it will be serviced.
In this mode the DMA can be used to service the Local
Serial Channel (LSC) or the Global Serial Channel If the interrupt pill is pulled up before BCRn reaches
(GSC). OOOOH, then the DMA ceases, but the GO bit is still 1
and the DONE bit is still O. An external interrupt is not
In Serial Port Demand Mode the DMA is initiated by generated in this case, since in level-activated mode,
any of the following conditions, if the GO bit is set: pulling the pin to a logical 1 clears the interrupt flag. If
Source Address = SBUF .AND. RI = 1 the interrupt pin is then pulled low again, DMA trans-
fers will continue from where they were previously
Destination Address = SBUF .AND. TI = 1
stopped.
Source Address' = RFIFO .AND. RFNE = 1
Destination Address = TFIFO .AND. TFNF = 1 The timing for the DMA Cycle in the transition-acti-
vated mode, or for the first DMA Cycle in the level-ac-
Each time one of the above conditions is met, one tivated mode is as follows: If the l-to-O transition is
DMA Cycle is executed; that is, one data byte is trans-
ferred from the source address to the destination ad-
10-49
83C152 HARDWARE DESCRIPTION
detected before the final machine cycle of the instruc- and RD and/or WR signals are generated as needed, in
tion in progress, then the DMA commences as soon as the same manner as in the execution of a MOVX
the instruction in progress is completed. Otherwise, one @DPTR instruction.
more instruction will be executed before the DMA
starts. No instruction is executed during any DMA Cy-
cle: 4.3 Hold/Hold Acknowledge
Two operating modes of Hold/Hold Acknowledge log~
4.2 Timing Diagrams ic are available, and either or neither may be invoked
by software. In one mode, the Cl52 generates a Hold
Timing diagrams for single-byte DMA transfers are Request signal and awaits a Hold Acknowledge re-
shown in Figures 4.2 through 4.5 for four kinds of sponse before commencing a DMA that involves exter-
DMA Cycles: internal memory to internal memory, in- nal RAM. This is called the Requester Mode.
ternal memory to external memory, external memory
to internal memory, and external memory to external In the other mode, the Cl52 accepts a Hold Request
memory. In each case we assume the C152 is executing signal from an external device and generates a Hold
out of external program memory. If the C152 is execut- Acknowledge signal in response, to indicate to the re-
ing out of internal program memory. then PSEN is in- questing device that the Cl52 will not commence a
active, and the Port 0 and Port 2 pins emit PO and P2 DMA to or from external RAM while the Hold Re-
SFR data. If External Data Memory is involved, the quest is active. This is called the Arbiter mode.
Port 0 and Port 2 pins are used as the address/data bus,
I - - - - 1 2 OSC. PERIODS - - - - -~·1
ALE~ ; - \ ' - -_ __
PD~-----------------rWAT--------·----~~OA~INST
..::..:;;.;..J. _____ • __________________________ ___ _
.
~
P2~~____________~P~2~SF~R________~----JX~--P~CH~----
,~_ _ _ _ _ _ DMA CYCLE _ _ _ _ _ _ _ 1 RESUME PROGRAM
1- • - EXECUTION
270427-29
Figure 4.2. DMA Transfer from Internal Memory to Internal Memory
1, . . . - - - - - - 1 2 DSC. PERIODS ------1·1
ALE ~'-- _ _ _ _ _ _ _ _ --J;-\'-___
PO INST :::x DARLn X DMA DATA OUT
P2~~______________
DA_R_H_n______________JX~ ___
P_C_H______
,'-_____.J/
~------DMA CYCLE _ _ _ _ _ _ _.1_ RES~~E~~~g~RAM
270427-30
Figure 4.3. DMA Transfer from Internal Memory to External Memory
10-50
83C152 HARDWARE DESCRIPTION
1 1 - - - - - - - 1 2 OSC. PERIODS - - - - - - 1 ' 1
ALE~_ _ _ _ _ _ _ _ _ -..JI\.I...___
r>srNJ
P2~_______________
SA_R_Hn______________JX~ __~PC~H _____
\ .....____-JI
1_ _ _ _ _ _ _ O~A CYCLE _ _ _ _ _ _ _ 1- RES~:E~~~g~RAM
270427-31
Figure 4.4. DMA Transfer from External Memory to Internal Memory
t------12 osc. PERIODS-----I~----12 osc. PERIODS----I
ALE
P2~____________S~A~RH~n~_________'x~ __________~D~A~RH~n ________JX~ ___ P_C_H___
'I..._____ 1 .J
\ .....____-11
I--------~--DMA CYCLE -------~-----I- R[S~:[~Gfl~~RAM
270427-32
Figure 4,5. DMA Transfer from External Memory to External Memory
4.3.1 REQUESTER MODE 4.3.2 ARBITER MODE
The Requester Mode is selected by setting the control For DMAs that are to be driven by some device other
bit REQ, which resides in PCON. In that mode, when than the C152, a different version of the Hold/Hold
the Cl52 wants to do a DMA to External Data Memo- Acknowledge protocol is available. In this version, the
ry, it first generates a Hold Request signal, HLD, and device which is to drive the DMA sends a Hold Re-
waits for a Hold Acknowledge signal, HLDA, before quest signal, HLD, to the C152. If the C152 is current-
commencing the DMA operation. Note that program ly performing a DMA to or from External Data Memo-
execution continues while HLDA is awaited. The ry, it will complete this DMA before responding to the
DMA is not begun until a logical 0 is detected at the Hold Request. When the Cl52 responds to the Hold
HLDA pin. Then, once the DMA has begun, it goes to Request, it does so by activating a Hold Acknowledge
completion regardless of the logic level at HLDA. signal, HLDA. This indicates that the Cl52 will not
commence a new DMA to or from External Data
The protocol is activated only for DMAs (not for pro- Memory while HLD remains active.
gram fetches or MOVX operations), and only for
DMAs to or from External Data Memory. If the data Note that in the Arbiter Mode the Cl52 does not sus-
destination and source are both internal to the C152, pend program execution at all, even if it is executing
the HLD/HLDA protocol is not used. from external program memory. It does not surrender
use of its own bus.
The HLD output is an alternate function of port pin
P1.5, and the HLDA input is an alternate function of The Hold Request input, HLD, is at P1.5. The Hold
port pin P1.6. Acknowledge output, HLDA, is at P 1.6. This
10-51
infef 83C152 HARDWARE DESCRIPTION
version of the Hold/Hold Acknowledge feature is se- es are done only through DMA operations, not by
lected by setting the control bit ARB in PCON. MOVX instructions.
The functions of the ARB and REQ bits in PCON, One CPU is programmed to be the Arbiter and the
then, are other, to be the Requester. The ALE Switch selects
which CPU's ALE signal will be directed to the address
ARB REQ Hold/Hold Acknowledge Logic latch. The Arbiter's ALE is selected if HLDA is high,
0 0 Disabled and the Requester's ALE is selected if HLDA is low.
0 1 C152 generates HLD, detects HLDA
1 0 C152 detects HLD, generates HLDA
1 1 Invalid ALE _ _ J"""_
(ARB)
ALE (ARB)
4.3.3 USING THE HOLD/HOLD ACKNOWLEDGE IF HCliA = 1
ALE (REO)
IF HrnA =0
The HOLD/HOLDA logic only affects DMA opera-
tion with external RAM and doesn't affect other opera- ALE
tions with external RAM, such as MOVX instruction. (REO).--.... 1
270427-34
Figure 4.6 shows a system in which two 83Cl52s are
sharing a global RAM. In this system, both CPUs are Figure 4.7. ALE Switch Select
executing from internal ROM. Neither CPU uses the
bus except to access the shared RAM, and such access· The ALE Switch logic can be implemented by a single
74HCOO, as shown in Figure 4.7.
Vee
"fSX10kfi
PO
83C152
ARB P2
r-- WR
- 7
-Rii
ALE - -A.
4
L
S -
HLD HLDA
:-v' 3
7
3
LJ
HLD HLDA
83C152
REO
~
ALE
ALE
SWITCH
~ WR PO
fo-Rii P2 -
-.!
DATA
:1
LOW HIGH
'----'
OE SHARED ADDR
WE RAM
270427-33
Figure 4.6. Two 83C152s Sharing External RAM
10-52
infef 83C152 HARDWARE DESCRIPTION
4.3.4 INTERNAL LOGIC OF THE ARBITER When the arbiter wants to DMA the XRAM, it first
activates DMXRQ. This signal prevents Q2 from being
The internal logic of the arbiter is shown in Figure 4.8. set if it is not already set. An output low from Q2 en-
In operation an input low at HLD sets Q2 if the arbi- ables the arbiter to carry out its DMA to XRAM, and
ter's internal signal DMXRQ is low. DMXRQ is the maintains an output high at HLDA. When the arbiter
arbiter's "DMA to XRAM Request". Setting Q2 acti- completes its DMA, the signal DMXRQ goes to 0,
vates HLDA through Q3. Q2 being set also disables which enables Q2 to accept signals from the HLD input
any DMAs to XRAM that the arbiter might decide to again.
do during the requester's DMA.
Figure 4.9 shows the minimum response time, 4 to 7
CPU oscillator periods, between a transition at the
HLD input and the response at HLDA.
Inhibit Arbiter's
DMXRO DMA to XRAM
HLD Input
(P1.5) . -.....--I D
01 Q3
HLDA Output
(P1.6)
Clock 1 Clock 2 Clock 1
270427-39
Figure 4.8. Internal Logic of the Arbiter
10-53
infef 83C152 HARDWARE DESCRIPTION
~
HLD Input
I ,
I I
CPU Osc. Periods 111111111,1111111111
Clock 1
Clock 2
HLDA Output
.._I~
'2 Osc.' ... Osc. I
Period, Periods
270427-40
Figure 4.9. Minimum HLD/HLDA Response Time
Inhibit Roquester's
DMXRO DMA to XRAM
HLDA Input
(Pl.6)
LrD--O~+-_-I
01
Clock 1
Clock 2
270427-41
Figure 4.10. Internal Logic of the Requester
(Clock 1 and Clock 2 are Shown in Figure 4.9)
10-54
inter 83C152 HARDWARE DESCRIPTION
4.3.5 Internal Logic of the Requester the request and receive another acknowledge before an-
other DMA cycle to XRAM can proceed. Obviously in
The internal logic of the requester is shown in Figure this case, the "alternate cycles" mode may consist of
4.10. Initially, the requester's internal signal DMXRQ single DMA cycles separated by any number of ins truc-
(DMA to XRAM Request) is at 0, so Q2 is set and the tion cycles, depending on how long it takes the request-
HLD output is high. As long as Q2 stays set, the re- er to regain the bus.
quester is inhibited from starting any DMA to XRAM.
A channel I DMA in progress will always be overrid-
When the requester wants to DMA the XRAM, it first den by a DMA request of any kind from channel O. If a
activates DMXRQ. This signal enables Q2 to be cleared channel I DMA to XRAM is in progress and is over-
(but doesn't clear it), and, if HLDA is high, also acti- ridden by a channel 0 DMA which does not require the
vates the IILD output. bus, DMXRQ will go to 0 during the channel 0 DMA,
thus de-activating HLD. Again, the requester must r e - I I I
A I-to-O Iransition from HLDA can now clear Q2, new its request for the bus, and must receive a new 1- I
which will enable the requester to commence its DMA to-O transition in HLDA before channel 1 can continue
to XRAM. Q2 being low also maintains an output low its DMA to XRAM.
atHLD. When the DMA is completed, DMXRQ goes
to 0, which sets Q2 and de·aetivates HLD.
4.4 DMA Arbitration
Only DMXRQ going to 0 can sct Q2. That means once
Q2 gets cleared, enabling the requesler's DMA to pro- The DMA Arbitration described in this section is not
ceed, the arbiter has no way to stop the requester's arbitration between two devices wanting to access a
DMA in progress. At this point, de-activating HLDA shared RAM, but on·chip arbitration between the two
will have no effect on the requester's use of the bus. DMA channels on the 8XC152.
Only the requester itself can stop the DMA in progress,
and when it does, it de-activates both DMXRQ and The 8XC152 provides. two DMA channels, either of
HLD. which may be called into operation at any time in re-
sponse to real time conditions in the application circuit.
If the DMA is in alternate cycles mode, then each time Since a DMA cycle always uses the KXCI52's internal
a DMA cycle is completed DMXRQ goes to 0, thus de- bus, and there's only one internal bus, only one DMA
activating HLD. Once HLD has been de-activated, it channel can be serviced during a singk DMA cycle.
can't be re-asserted till after HLDA has been seen to go Executing program instructions also requires the inter-
high (through flip-flop QIA). Thus every time the nal bus, so program execution will also be suspended in
DMA is suspended to allow an instruction cycle to pro- order for a DMA 10 lake place.
ceed, the requester gives up the bus and must renew
r - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -..-.-.... - - - - - - - - ,
o 2
270427-42
Figure 4.11. Internal Bus Usage
10-55
inter 83C152 HARDWARE DESCRIPTION
Figure 4.11 shows the three tasks to which the internal The return value is based on the condition of the GO
bus of the 8XC 152 can be dedicated. In this figure, bit for each channel, and on the value returned by an-
Instruction Cycle means the complete execution of a other function, named mode_logic (). The algorithm
single instruction, whether it takes I, 2 or 4 machine for mode_logic ( ) is the same for both channels. The
cycles. DMA Cycle means the transfer of a single data function is shown in Figure 4.13 as a pseudo-HLL
byte from source to destination, whether it takes 1 or 2 function, mode_logic (n), where n = 0 when the func-
machine cycles. Each time a DMA Cycle or an Instruc- tion is invoked for DMA channel 0, and n = I when
tion Cycle is executed, on-chip arbitration logic deter- it's invoked for DMA channel I. The value returned by
mines which type of cycle is to be executed next. this function is either 0 or I, and will be passed on to
the DMA arbitration logic in Figure 4.12.
Note that when an instruction is executed, if the in-
struction wrote to a DMA register (defined in Figure Note that the arbitration logic as shown in Figure 4.12
4.1 but excluding PCON), then another instruction is always gives precedence to channel 0 over channel 1. If
executed without further arbitration. Therefore, a sin- GOO is set and mode_logic (0) returns a 1, then a
gle write or a series of writes to DMA registers will OMAO cycle is called without further reference to the
prevent a DMA from taking place, and will continue to situation in channel 1. That is not to say a DMAI Cy-
prevent a DMA from taking place until at least one cle will be interrupted once it has begun. Once a cycle
instruction is executed which docs not write to any has begun, be it an Instruction Cycle or a DMA Cycle,
DMA register. it will be completed without interruption.
The logic that determines whether t he next cycle will be The statements in mode_logic (n), Figure 4.13, are ex-
a DMAO cycle, a DMAI cycle, or all Instruction Cycle ccuted sequentially until an "if' condition, based on the
is shown in Figure 4.12 as a pseudo-I I I.L function. The DMA mode programmed into DCONn, is satisfied.
statements in Figure 4.12 are executed sequentially un- For example, if the channel is configured to Burst
less an "if' condition is satisfied, ill which case the cor- mode, thell the first if-condition is satisfied, so the "re-
responding "return" is executed alld t he remainder of turn I" expression is cxecuted and the remainder of the
the function is not. The return value of 0, 1, or 2 is fUllction is not.
passed to the arbitration logic block ill Figure 4.11 to
determine which exit path from the block is used.
arbitration_logic:
if (GOO 1 .AND. mode_logic(O) 1) return 0;
if (GOl 1 .AND. mods_logic(l) 1) return 1;
else return 2;
end arbitration_logic;
Figure 4.12. DMA Arbitration Logic
10-56
83C152 HARDWARE DESCRIPTION
mode_logic(n) :
if (DCONn indicates burst_mode) return 1:
if (DCONn indicates extern_demand_mode)
if (demand_flag = 1) return 1;
a
else return 0;
if (DCONn indicates SP_demand_mode)
i f (SARn = SBUF .AND. RI = 1) return 1;
i f (DARn = SBUF .AND. TI = 1) return 1 ;
i f (SARn = RFIFO .AND. RFNE = 1) return 1 ;
if (DARn = TFIFO .AND. TFNF = 1 .AND.
previous_cycle = instruction_cycle-) return 1;
else return 0;
if (DCONn indicates alt_cycles_mode)
if (DCONm indicates .NOT. alt_cycles_mode
.OR. GOm = 0)
if (previous_cycle = instruction_cycle)
return 1;
else return 0;
if (previous_cycle = instruction_cycle
.AND. previous_dma_cycle = .NOT. DMAn)
return 1;
return 0;
end mode_logic(n) ;
Figure 4.13. DMA Mode Logic
10·57
intJ 83C152 HARDWARE DESCRIPTION
If the channel is configured to External Demand mode, For example, consider the situation where channel 0 is
then the first if-condition is not satisfied but the second configured to service TFIFO .lIld channel I is config-
one is. In that case the block of statements following ured to Alternate Cycles mode. Then DMAs to TFIFO
that if-condition and delimited by [ ... J is executed: if will always override the alternate cycles of channell. If
the demand flag (lEO for channel 0 and lEI for chan- TFIFO needs more than I byte it will receive them in
nel I) is set, the "return I" expression is executed and precendence over channel I, but each DMA to TFIFO
the remainder of the function is not. If the demand flag must be preceded by an Instruction cycle. The sequence
is not set, the "return 0" expression is executed and the of cycles might be:
remainder of the function is not.
DMAI cycle
If the channel is configured to Serial Port Demand Instruction cycle
mode, the source and destination addresses, SARn and DMAI cycle, during which TFNF gets set
DARn, have to be checked to see which Serial Port Instruction cycle
buffer is being addressed, and whether its demand flag DMAO cycle
is set. Instruction cycle
DMAO cycle, as a result of which TFNF gets cleared
SARn refers to the l6-bit source address for "this chan- I nst ruction cycle
ne1." Note that the condition DMA I cycle
Inst ruction cycle
SARn = SBUF DMAI cycle
cannot be true unless the SAS and ISA bits in DCONn Instruction cycle
are configured to select SFR spacc. If SARn is numeri-
cally equal to the address of SBUF (99H), and SAS and
ISA arc configured to select internal RAM rather than The requirement that a DMA to TFIFO be preceded
SFR spacc, thcn SARn refers to location. 99H in the by an Instruction cycle can result in the normal prece-
"uppcr 128" of internal RAM, not to SBUF. dcnce of channel 0 over channel I being thwarted. Con-
sider for example the situation where channel 0 is con-
If thc test for SARn = SBUF is truc, and if the flag RI figured to service TFIFO, and is in the process of doing
is set, mode_logic (n) returns as I and the remainder so, and channel I decides it wants to do a Burst mode
of the function is not executed. Ot herwise, execution DMA. The sequence of events might be:
proceeds to the next if-condition, testing DARn against
SBUF and TI against I. Instruction cycle (sets GO bit in DCONI)
Instruction cycle (during which TFNF gets set)
The same considerations regarding SAS and ISA in the DMAO cycle
SARn test are now applied to DAS and IDA in the DMAI cycle
DARn test. If SFR space isn't selected, no Serial Port DMAI cycle
buffer is being addressed. DMAI cycle
Note that ifDMA channel n is configured to Alternate DMAI cycle (completes channel I burst)
Cycles mode, the logic must examine the other DCON Instruction cycle .
register, DCONm, to determine if the other channel is DMAO cycle
also configured to Alternate Cycles mode and whether Instruction cycle
its GO bit is set. In Figure 4.13, the symbol DCONn
refers to the DCON register for "this channel," and
DCONm refers to "the other channe1." This sequence begins with two Instruction cycles. The
first one accesses a DMA register (DCONI), and there-
A careful examination of the logic in Figure 4.13 will fore is followed by another Instruction cycle, which
reveal some idiosyncracies that the user should be presumably does not access a DMA register. After the
aware of. First, the logic allows sequential DMA cycles second Instruction cycle both channels are ready to
to be generated to service RFIFO, but not to service generate DMA cycles, and channel 0 of course takes
TFIFO. This idiosyncracy is due to internal timing precedence. After the DMAO cycle, channel 0 must
conflicts, and results in each individual DMA cycle to wait for an Instruction cycle before it can access
TFIFO having to be immediately preceded by an In- TFIFO again. Channell, being in Burst mode, doesn't
struction cycle. The lpgic disallows that there be two have that restriction, and is therefore granted a DMAI
DMAs to TFIFO in a row. cycle. After the first DMAI cycle, channel 0 is still
waiting for an Instruction cycle and channell still does
If the user is ullaware of this idiosyncracy, it can cause not have that restriction. There follows another DMAI
problems in situations where one DMA channelis serv- cycle.
icing TFIFO and the other is configured to a complete-
ly different mode of operation.
10-58
83C152 HARDWARE DESCRIPTION
The result is that in this particular case channel 0 has Function Register (SFR).If DAS = I and IDA = 1,
to wait until channel 1 completes its Burst mode DMA, the destination is in Internal Data RAM.
and then has to wait for an Instruction cycle to be gen-
erated, before it can continue its own DMA to TFIFO. IDA (Increment Destination Address) If IDA = 1, the
The delay in servicing TFIFO can cause an Underflow destination address is automatically incremented after
condition in the GSC transmission. . each byte transfer. If IDA = 0, it is not.
The delay will not occur if channel I is configured to SAS specifies the Source Address Space. If SAS = 0,
Alternate Cycles mode, since channel 0 would then see the source is in External Data Memory. If SAS = 1
the Instruction cycles it needs to complete its logic re- and ISA = 0, the source is an SFR. If SAS = I and
quiremcnts for asserting its request. ISA = I, the source is Internal Data RAM.
ISA (Increment Source Address) If ISA = 1, the
4.4.1 DMA Arbitration with Hold/Hold Ack source address is automatically incremented after each
The Hold/Hold Acknowledge feature is invoked by set- byte transfer: If ISA = 0, it is not.
ting either the ARB or REQ bit in PCON. Their effect
is to add the requirements of the Hold/Hold Ack pro- OM (Demand Mode) If DM = 1, the DMA Channel
tocol to mode_logic ( ). This amounts to replacing ev- operates in Demand Mode. In Demand Mode the
ery expression "return I" in Figure 4.13 with the ex- DMA is initiated either by an external signal or by a
pression "return hld_hlda_logic ()", where Serial Port flag, depending on the value of the TM bit.
hldJld~logic ( ) is a function which returns I if the
If DM = 0, the DMA is requested by setting the GO
HoldIHold Ack protocol is satisfied, and returns 0 oth- bit in software.
erwise. A suitable definition for hld_hlda~ogic ( ) is
shown in Figure 4.14. TM (Transfer Mode) If OM = I then TM selects
whether a DMA is initiated by an external signal (TM
= I) or by a Serial Port flag (TM =, 0). If DM = 0
then TM selects whether the data transfers are to be in
4.5 Summary of DMA Control Bits bursts (TM = I) or in alternate cycles (TM = 0).
DeONn I DAS I IDA I SAS liSA " OM I TM I DONE I GO I
DONE indicates the completion of a DMA operation
DAS specifies the Destination Address Space. If DAS and flags an interrupt. It is set 10 1 hy on-chip hardware
= 0, the destination is in External Data Memory. If when BCRn = 0, and is cleared to () hy Oil-chip hard-
DAS = I and IDA = 0, the destination is a Special ware when the interrupt is vectored to. It can also be
set or cleared by soft ware.
hold_holda( }:
if (ARB =° .AND. REQ =O) return 1;
if SARn = XRAM .OR. DARn = XRAM}
if (ARB =1 .AND. HLDA = 1) return 1;
if (REQ =1 .AND. HLDA = O) return 1;
else return 0;
return 1;
end hold_holda( };
Figure 4.14. Hold/Hold' Acknowledge Logic as a Pseudo·HLL Function
10-59
inter 83C152 HARDWARE DESCRIPTION
GO is the enable bit for the DMAChannel itself. The Note that setting the DMA bit does not itself configure
DMA Channel is inactive if GO = O. the DMA channels to service the GSC. That job must
be done by software writes to the DMA registers. The
I I
PCON SMOD I ARB REO I GAREN I XRCLK I GFIEN I PDN IIDL I
DMA bit only selects whether the GSCRV and
GSCTV interrupts are flagged by a FIFO needing serv-
ARB enables the DMA logic to detect HLD and gener- ice or by an "operation done" signal.
ate HLDA. After it has activated HLDA, the CI52 will
not begin a new DMA to or from External Data Mem- The Receive and Transmit Error interrupt flags are
ory as long as HLD is seen to be active. This logic is generated by the logical OR of a number of error condi-
disabled when ARB = 0, and enabled when ARB = 1. tions, which are described in Section 3.6.5.
REQ enables the DMA logic to generate HLD and de- Each interrupt is assigned a fixed location in Program
tect HLDA before performing a DMA to or from Ex- Memory, and the interrupt causes the CPU to jump to
ternal Data Memory. After it has activated HLD, the that location. All the interrupt flags are sampled at
CI52 will not begin the DMA until HLDA is seen to be S5P2 of every machine cycle, and then the samples are
active. This logic is disabled when REQ = 0, and en- sequentially polled during the next machine cycle. If
abled when REQ = 1. more than one interrupt of the same priority is active,
the one that is highest in the polling sequence is serv-
iced first. The interrupts and their fixed locations in
5.0 INTERRUPT STRUCTURE Program Memory are listed below in the order of their
polling sequence.
The 8XCI52 retains all five interrupts ()fthe 80C5IBH.
Six new interrupts are added in thc ~XC152, to support
its GSC and the DMA features. They are as listed be- RFNEiDMA=O
low, and the flags that generate thcllI are shown in Fig-
ure 5.1. ~GSCRV
GSCRV - GSC Receive Valid
RDN --1 DM.A = 1
270427-43
GSCRE - GSC Receive Error
GSCTV - GSC Transmit Valid
GSCTE - GSC Transmit Error CRCE~
DMAO - DMA Channel 0 Done AE . GSCRE
RCABT
DMAI - DMA Channell Done OVR .
270427-44
As shown in Figure 5.1, the Receive Valid interrupt can
be signaled either by the RFNE flag (Receive FIFO
Not Empty), or by the RDN flag (Receive Done). TFNFiDMA=O
Which one of these flags causes the interrupt depends
on the setting of the DMA bit in the SFR named ~GSCTV
TSTAT. TON --1 DMA= 1 .
270427-45
DMA = 0 means the DMA hardware is not config-
ured to service the GSC, so the CPU will service it in TCDT3[)--+
software in response to the Receive FIFO not. being UR GSCTE
NOACK
empty. In that case, RFNE generates the Receive Valid
270427-46
interrupt.
DONE
DMA = I means the DMA hardware is configured to (DCONO.l)
.DMAO
service the GSC, in which case the CPU need not be 270427-47
interrupted till the receive is complete. In that case,
RDN generates the Receive Valid interrupt. DONE
.DMAI
(DCON1.1)
270427-48
Similarly the Transmit Valid interrupt can be signaled
either by the TFNF flag (Transmit FIFO Not Full), or Figure 5.1. Six New Interrupts in the 8XC152
by the TDN flag (Transmit Done), depending on
whether the DMA bit is 0 or 1.
10-60
inter 83C152 HARDWARE DESCRIPTION
The two Interrupt Priority registers in the 8XC152 are
Interrupt Location Name
as follows:
lEO 0003H External Interrupt a 7 6 5 4 3 2 1 0
GSCRV
TFO
002BH
OOOBH
GSC Receive Valid
Timer a Overflow
IP: I-I -I -I PS I PT1 I PX1 I PTO I PXO I
GSCRE 0033H GSC Receive Error
DMAO 003BH Address of IP in SFR space = OB8H (bit-addressable)
DMA Channel a Done
IE1 0013H External Interrupt 1 7 6 5 4 3 2' 1 0
GSCTV
DMA1
0043H
0053H
GSC Transmit Valid
DMA Channel 1 Done
IPN1 :HdpGSTElpDMA 1IPGSTVlpDMAOlpGSRElpGSR~
TF1 001BH Timer 1 Overflow
Address of IPNI in SFR space = OF8H (bit-address-
GSCTE 004BH GSC Transmit Error able)
TI+RI 0023H UART Transmit/Roceive
The bits in IP are unchanged from the standard 8051
Note that the locations of the basic 8051 interrupts are IP register. The bits in IPNI are as follows:
the same as in the rest of the MCS-51 Family. And PGSTE = 1 GSC Transmit Error Interrupt Priority
relative to each other they retain their same positions in to High
the polling sequence. = 0 Priority to Low
PDMAI = 1 DMA Chanqel I Done Interrupt Priori-
The locations of the new interrupts all follow the loca- ty to High
tions of the basic 8051 interrupts in Program Memory, ;= 0 Priority to Low
but they are interleaved with them in the polling se- PGSTV = 1 GSC Transmit Valid Interrupt Priority
quence. to High
= 0 Priority to Low
To support the new interrupts a second Interrupt En- PDMAO = 1 DMA ('hannel 0 Done Interrupt Priori-
able register and a second Interrupt Priority register are ty to High
implemented in bit-addressable SFR space. The two In- = 0 Priority to Low
terrupt Enable registers in the 8XC152 are as follows: PGSRE = 1 GSC Receive Error Interrupt Priority to
76543210 High
= 0 Priority to I.ow
IE: I EA I -I -I ES I ET1 I EX1 I ETa I EXO I PGSRV = 1 GSC Receive Valid Interrupt Priority to
High
Address of IE in SFR space = OA8H (bit-addressable) = 0 Priority to I.ow
76 5 4 3 2 1 0 Note that these registers all have unimplemented bits
IEN1 F-F1EGSTEIEDMA 1IEGSTVIEDMAOIEGSREIEGSR~ ("-"). If these bits are reali, t hey will return unpredict-
able values. If they an' written to, the value written
goes nowhere.
Address pF lEI in SFR space = OC8H (bit-address-
able) It is recommell(led that UScI' software should never
write Is to unimplemented bits in MCS-51 devices. Fu-
The bits in IE are unchanged from the standard 8051 ture versions of the device may have new bits i~stalled
IE register. The bits in IENI are as follows: in these locations. If so, their reset value will be O. Old
EGSTE = I Enable GSC Transmit Error Interrupt software that writes Is to newly implemented bits may
, = 0 Disable unexpectedly invoke new features.
EDMAI = 1 Enable DMA Channell Done Interrupt
= 0 Disable The MCS-51 interrupt structure pro\fides hardware
EGSTV = 1 Enable GSC Transmit Valid Interrupt support for only two priority levels, High and Low.
= 0 Disable With as many interrupt sources as the 8XC152 has, it
EDMAO = 1 Enable DMA Channel a Done Interrupt may be helpful to know how to augment the priority
= 0 Disable structure in software. Any number of priority levels can
EGSRE = 1 Enable GSC Receive Error Interrupt be implemented in software by saving and redefining
= 0 Disable . the interrupt enable registers within the interrupt serv-
EGSRV = I Enable GSC Receive Valid Interrupt ice routines. The technique is described in the "MCS-
= 0 Disable 51" Architectural Overview" chapter in this handbook.
10-61
inter 83C152 HARDWARE DESCRIPTION
5.1 GSC Transmitter Error Conditions The TCDT bit can get set only if the GSC is configured
to CSMA/CD mode. In that case, the GSC hardware
The GSC Transmitter section reports three kinds of sets TCDT when a collision is detected during a trans-
error conditions: . mission, and the collision was detected after TFIFO has
been .accessed. Also, the GSC hardware sets TCDT
TCDT - Transmitter Collision Detector
when a detected collision causes the TCDCNT register
UR. - Underrun in Transmit FIFO to overflow.
NOACK - No Acknowledge
The UR bit can get set only if the DMA bit in TSTAT
These bits reside in the TSTAT register. User software is set. The DMA bit being set informs the GSC hard-
can read them, but only the GSC hardware can write to ware that TFIFO is being scrviced byDMA. In that
them. The GSC hardware will set them in response to case, iftheGSC goes to fetch another byte from TFIFO
the various error conditions that they represent. When and finds it empty,and the hyte count register of the
user software sets the TEN bit, the GSC hardware will DMA channel servicing TFIFO is not zero, it sets the
at that time clear these flags. This is the only way these URbit.
flags can be cleared.
If the DMA hardware is not heing used to service
The logical OR of these three bits flags the GSC Trans- TFIFO, the UR bit cannot gct sct. If the DMA bit is 0,
mit Error interrupt (GSCTE) and clears the TEN bit, then when the GSC finds TFIFO empty, it assumes
as shown in Figure 5.2. Thus any detcctederror condi- that the transmission of data is cmnplete and the trans-
tion aborts the transmission. No CRC bits are transmit- mission of CRC bits can begin .
. ted. In SDLC mode, no EOF flag is generated. In
CSMAlCD mode, an EOF is gcncrated by default, The NOACK bit is functiollal only in CSMA/CD
since the GTXD pin is pulled to a logic 1 and held mode, and only when the HAllEN bit in RSTAT is set.
there. The HABEN bit turns on thc Hardware Based Ac-
knowledge feature, as described in Section 3.2.6. If this
feature is not invoked, the NOACK bit will stay at O.
NOAg~
TC;:O
TEN
.
~
ED..: ::::E
TEN
....._ _ _ _ _-+Set
TRANSMIT
EOF TON
270427-49
Figure 5.2. Transmit Error Flags (Logic for Clearing TEN, Setting TDN)
10-62
83C152 HARDWARE DESCRIPTION
>-~.--- .......- - -.. GSCRE
>-__.Clear
.----.._, GREN
270427-50
Figure 5.3. Receive Error Flag (Logic for Clearing GREN, setting RON)
If the NOACK bit gets set, it means the GSC has com-
pleted a transmission, and was expecting to receive a
hardware based acknowledge from the receiver of the
The logical OR of these four bits flags the GSC Receive
Error interrupt (GSCRE) and clears the GREN bit, as
shown in Figure 5.3. Note in this figure that any error
III
message, but did not receive the acknowledge, or at condition will prevent RON from being set.
least did not receive it cleanly. There arc three ways the
NOACK bit can get set: A CRC Error means the CRC generator did not come
1. The acknowledge signal (an unattached preamble) to its correct value after calculating the CRC of the
was not received before the IFS was completed. message plus received CRC. An Alignment Error
means the number of bits received between the BOF
2. A collision was detected during the IFS. and EOF was not a multiple of 8.
3. The line was active during the last bit-time of the
IFS. In SOLC mode, the CRCE bit gets set at the end of any
frame in which there is a CRC Error, and the AE bit
The first condition is an obvious reason for setting the gets set at the end of any frame in which there is an
NOACK bit, since that's what the hardware based ac- Alignment Error.
knowledge is for. The other two ways the NOACK bit
can get set are to guard against the possibility that the In CSMA/CO mode, if there is no CRC Error, neither
transmitting station might mistake an unrelated trans- CRCE nor AE will get seL If there is a CRC Error and
mission or transmission fragment for an acknowledge no Alignment Error, the CRCE bit will get set, but not
signal. the AE bit. If there is both a CRe Error and an Align-
ment Error,the AE bit will gel set, but not the CRCE
bit. Thus in CSMA/CO mode, I he CRCE and AE bits
5.2 GSC Receiver Error Conditions are mutually exclusive.
The GSC Receiver section reports four kinds of error The Receive Abort flag, RCi\IlT, gets sci if an incom-
conditions: ing frame was interrupted alkr received data had al-
CRCE - CRC Error ready passed to the Receive 1'11'0, [n SOLC mode, this
can happen if a line idle condilion is detected before an
AE - Alignment Error
EOF flag is. In CSMA/('I) lIIode, it can happen if
RCABT - Receive Abort there is a collision. In either case, the CPU will have to
OVR - Overrun in Receive FIFO re-initialize whatever poinlers and counters it might
have been using.
These bits reside in the RSTAT register. User software
can read them, but only the GSC hardware can write to The Overrun Error Ilag, ()VR, gets set if the GSC Re-
them. The GSC hardware will set them in response to ceiver is ready to push a newly received byte onto the
the various error conditions that they represent. When Receive FIFO, but the FIFO is full.
user' software sets the GREN bit, the GSC hardware
will at that time clear these flags. This is the only way Up to 7 "dribble bits" can be received after the EOF
these flags can be cleared. without causing an error condition.
10-63
83C152 HARDWARE DESCRIPTION
6.0 GLOSSARY DAS - Destination Address Space, see DCON.·
ADRO,I,2,3 (95H, OA5H, OB5H, OC5H) - Address DCJ - D.C. Jam, see MYSLOT.
Match Registers 0,1,2,3 - The contents of these SFRs
are compared against the address bits from the serial DCONO/I (092H,093H)
data on the GSc. If the address matches the SFR, then 76543210
the C 152 accepts that frame. If in 8 bit addressing
mode, a match with any of the four registers will trigger
acceptance. In 16 bit addressing mode, a match with
ADRI:ADRO or ADR3:ADR2 will be accepted. Ad- The DCON registers control the operation of the DMA
dress length is determined by GMOD (AL). channels by determining the source of data to be trans-
ferred, the destination of the data to be transfer, and the
AE - Alignment Error, see RSTAT. various modes of operation.
AL - Address Length, see GMOD.
DCON.O (GO) - Enables DMA Transfer - When set it
AMSKO,1 (OD5H, OE5H) - Address Match Mask 0,1 - enables a DMA channel. If block mode is set then
Identifies which bits in ADRO,I are "don't care" bits. DMA transfer starts as soon as possible under CPU
Setting a bit to I in AMSKO,I identifies the corre- control. If demand mode is set then DMA transfer
sponding bit in ADDRO, I as not to be examined when starts when a demand is asserted and recognized.
comparing addresses.
DCON.l (DONE) - DMA Transfer is Complete -
BAUD - (94H) Contains the programmable value for
When set the DMA transfer is complete. It is set when
the baud rate generator for the GSc. The baud rate will
equal (fosc)/«BAUD+ I) X 8).
HCR cquals ° and is automatically reset when the
DMA vectors to its interrupt routine. If DMA inter-
BCRLO,I (OE211, OF2H) - Byte COllnt Register Low rupt is disabled alld the lIscr software executes a jump
011 the DONE bit, thcn the user software must also
0,1 - Contains t he lower byte of the byte count. Used
reset the donc bit. If DONE is not set, then the DMA
during DMA transfers to identify to the DMA chan-
nels when the transfer is complete. transfer is not complete.
BCRHO,I (OE31-1, OF3H) - Byte COllnt Register High DCON.2 (TM) - Transfer Mode - When set, DMA
0, I - Contains the upper byte of the byte count. burst transfers are used if the DMA channel is config-
ured in b)ock· mode or external interrupts are used to
BKOFF (OC4H) - BackoffTimer - The backofftimer is initiate a transfer if in Demand Mode. When TM is
an eight bit count-down timer with a dock period equal cleared, Alternate Cycle Transfers are used if DMA is
to one slot time. The backoff time is used in the in the Block Mode, or Local Serial channellGSC inter-
CSMA/CD collision resolution algorithm. rupts are used to initiate a transfer if in Demand Mode.
BOF - Beginning of Frame flag - A term commonly DCON.3 (DM) - DMA Channel Mode - When set,
used when dealing with packetized data. Signifies the Demand Mode is used and when cleared, Block Mode
beginning of a frame. is used.
CRC - Cyclic Redundancy Check - An error checking DCONA (ISA) - Increment Source Address - When
routine that mathematically manipulates a value depen- set, the source address registers are automatically incre-
dent on the incoming data. The purpose is to identify mented during each transfer. When cleared, the source
when a frame has been received in error. address registers are not incremented.
CRCE - CRC Error, sec RSTAT. DCON.5 (SAS) - Source Address Space - When set, the
source of data for the DMA transfers is internal data
CSMA/CD - Stands for Carrier Sense, Multiple Ac- memory if autoincrement is also set. If autoincrement is
cess, with Collision Detection. not set but SAS is, then the source for data will be one
of the Special Function Registers. When SAS is cleared,
CT - CRC Type, see GMOD. the source for data is external data memory.
DARLO/I (OC2H, OD2H) - Destination Address Reg- DCON.6 (IDA) - Increment Destination Address
ister Low 011 - Contains the lower byte of the destina- Space - When set, destination address registers are in-
tions' address when performing DMA transfers. cremented once after each byte is transferred. When
cleared, the destination address registers are not auto-
DARHO/I (OC3H, OD3H) - Destination Address Reg- matically incremented.
ister Low 0/1 - Contains the upper byte of the destina-
tions' address when performing DMA transfers.
10-64
intJ 83C152 HARDWARE DESCRIPTION
DCON.7 (DAS) - Destination Address Space - When GMOD(84H)
set, destination of data to be transferred is internal data 76543210
memory if autoincrement mode is also set. If autoincre-
ment is not set the destinationwill be one of the Special
Function Registers. When DAS is cleared then the des-
IXTCLK I M1 I MO I AL I CT I PL1 I PLO I PR I
tination is external data memory. The bits in this SFR, perform most of the configuration
on the type of data transfers to be used with the GSC.
DCR - Deterministic RI.'solution, see MYSLOT. Determines the mode, address length, preamble length,
protocol select, and enables the external clocking of the
DEN - An alternate function of one of the port 1 pins transmit data.
(P1.2). Its purpose is to enable external drivers when
the GSC is transmitting data. This function is always GMOD.O (PR) - Protocol- Ifset, SDLC protocols with •
active when using the GSC and if P1.2 is programmed
to a 1.
NRZI encoding, zero bit insertion, and SDLC flags are I
used. If cleared, CSMA/CD link access with Manches-
ter encoding is used.
DM - DMA Mode, sec DCONO.
GMOD.I,2 (PLO,l) - Preamble length
DMA - Direct Memory Access mode, see TSTAT.
PLl PLO LENGTH (BITS)
DONE - DMA done bit, sec DCONO. 000
o 1 8
DPH - Data Pointer High, all SFR that contains the 1 0 32
high order byte of a general purpose pointer called the 1 1 64
data pointer (DPTR).
The length includes the two bit Begin Of frame (BOF)
DPL - Data Pointer Low, an SFR that contains the low flag in CSMA/CD but does not include the SDLC flag.
order byte of the data pointer. In SDLC mode, thc BOF is an SDLC flag, otherwise it
is two consecutive ones. Zero length is not compatible
EDMAO - Enable DMA Channel 0 interrupt, see in CSMA/CD mode.
IENl.
GMOD.3 (CT) - CRC Typc - lfset, 32-bit AUTODIN-
EDMAI - Enable DMA Channel I interrupt, see 11-32 is used. If cleared, 16-bit CRC-CCITT is used.
IENl.
GMOD.4 (AL) - Address Length - If set, 16-bit ad-
EGSRE - Enable GSC Receive Error interrupt, see dressing is used. If cleared, 8-bit addressing is used. In
lEN 1. 8-bit mode, a match with any of the 4 address registers
will allow that frame to be accepted (ADRO, ADRl,
EGSRV - Enable GSC Receive Valid interrupt, see ADR2, ADIU). "Don't Care" bits may be masked in
IENl. ADRO and ADRI with AMSKO and AMSKl. In 16-
bit modc, addresses are matched against"
EGSTE - Enable GSC Transmit Error interrupt, see "ADRI:ADRO" or "ADR3:ADR2". Again, "Don't
IENl. Care" bits in ADRl:ADRO can "be masked in
AMSKl:AMSKO. A received address of all ones will
EGSTV - Enable GSC Transmit Valid interrupt, see always be recognized in any mode.
IENl.
GMOD.5, 6 (MO,Ml) - Mode Select - Two test modes,
EOF - A general term used in serial communications. an optional "alternate backofl" mode, or normal back-
EOF stands for End Of Frame and signifies when the off can be enabled with these two bits.
last bits of data are transmitted when uSing packetized
data. MI MO Mode
o 0 Normal
ES - Enable LSC Service interrupt, see IE. o I Raw Transmit
I 0 Raw Receive
ETO - Enable Timer 0 interrupt, see IE. 1 1 Alternate BackotT
ETI - Enable Timer I interrupt, see IE. GMOD.7 (XTCLK) - External Transmit Clock - If set
an external IX clock is used for the transmitter. If
EXO - Enable External interrupt 0, see IE. cleared the internal baud rate generator provides the
EXI - Enable External interrupt I, see IE.
10-65
83C152 HARDWARE DESCRIPTION
transmit clock. The input clock is applied to PI.3 IE.2 (EX!) - Enables the external interrupt INTI on
(TxC). The user software is responsible for setting or P3.3.
clearing this flag. External receive clock is enabled by
setting PCON.3. IE.3 (ETl) - Enables the Timer 1 interrupt.
GO - DMA Go bit, see DCONO. IE.4 (ES) - Enables the Loca 1 Serial Channel interrupt.
GRxD - GSC Receive Data input, an alternate function IE.7 (EA) - The global interrupt enable bit. This bit
of one of the port I pins (PI.O). This pin is used as the must be set to a I for any other interrupt to be enabled.
receive input for the GSC. PI.O must be programmed
to a I for this function to operate. IENI - (OGII)
76 5 4 3 2 1 0
GSC - Global Serial Channel - A high-level, multi-pro-
tocol, serial communication controller added to the IIIEGSTEIEDMA1IEGSTV1ED~AOIEGSREIEGSRg
80C51BH core to accomplish high-speed transfers of
packetized serial data. Interrupt enable register for DMA and GSC interrupts.
A 1 in any bit position enables that interrupt.
GTxD - GSC Transmit Data output, an alternate func-
tion of one of the port I pins (PI.l). This pin is used as lEN 1.0 (EGSRV) - Enables the GSC valid receive in-
the transmit output for the GSc. 1'1.1 must be pro- terrupt.
grammed to a I for this function to operate.
IEN 1.1 (EGSRE) - Enables the GSC receive error in-
HBAEN - Hardware Based Acknowledge Enable, see terrupt.
RSTAT.
IEN1.2 (EDMAO) - Enables the DMA done interrupt
HLDA - Hold Acknowledge, an alternate ftinction of for Channd n.
one of the port I pins (PI.6). This pin is used to per-
form the "HOLD ACKNOWLEDC,E" function for IEN1.3 (EGSTV) - Enables the GSC valid transmit in-
DMA transfers. HLDA can be an input or an output, terrupt.
depending on the configuration of the DMA channels.
P1.6 must be programmed to a I fill' this function to IENI.4 (EDMAI) - Enables the DMA done interrupt
operate. for Channel 1.
HOLD - Hold, an alternate function of one of the port IENI.5 (EGSTE) - Enables the GSC transmit error in-
I pins (PI.5). This pin is used to perfill"ll1 the "HOLD" terrupt
function for DMA transfers. HOLD can he an input or
an output, dependingon the configuration of the DMA IFS - (OA4H) Interframe Space, determines the number
channels. PI.5 must be programmed to a I for this of bit times separating transmitted frames in CSMA/
function to operate. CD and SDLC.
IDA - Increment Destination Address, see DCONO. IP (OB8H)
IE (OA8H) 7 6 5 4 3 2 o
7 6 5 4 3 2 o PS I PT1 I PX1 I PTO PXO
EA I ES I ET1 I EX1 I ETO EXO
Allows the user software two· levels of prioritization to
be assigned to each of the interrupts in IE. A I assigns
Interrupt Enable SFR, used to individually enable the the .corresponding interrupt in IE a higher interrupt
Timer and Local Serial Channel interrupts. Also con- than an interrupt with a corresponding O.
tains the global enable bit which must be set to a I to
enable any interrupt to be automatically recognized by IP.O (PXO) - Assigns the priority of external interrupt,
the CPU. INTO.
IE.O (EXO) - Enables the external interrupt INTO on IP.I (PTO) - Assigns the priority of Timer 0 interrupt,
1'3.2. TO.
IE. I (ETO) - Enables the Timer 0 interrupt.
10-66
83C152 HARDWARE DESCRIPTION
IP.2 CPXI) - Assigns the priority of external interrupt, Determines which type of Jam is used, which backoff
INTI. algorithm is used, and the DCR slot address for the
GSC.
IP.3 CPT1) - Assigns the priority of Timer I interrupt,
Tl.. MYSLOT.O,I,2,3,4,5 (SAO, 1;2,3,4,5) - These bits deter-
mine which slot address is assigned to the C152 when
IP.4 CPS) - Assigns the priority of the LSC interrupt, using deterministic backoff during CSMA/CD opera-
SBUF. tions on the GSC. Maxunum slots available is 63. An
address of OOH prevents that station from participating
II'N I - COF8H) in the backoff process.
76 5 4 3 2 1 0
I I I PGSTE I PDMA 1 I PGSTV I PDMAO I PGSRE I PGSRV I MYSLOT.6 (OCR) - Determines which collision reso-
lution algorithm is used. If set to a I, then the determi-
Allows the user software two levels of prioritization to . nistic backoff is used. If cleared, then a random slot
be assigned to l:aeh of thl: interrupts in IENI. A I as- assignment is used.
signs the corresponding interrupt in IENI a higher in-
terrupt than an interrupt with a corresponding o. MYSLOT.7 (OCJ) - Determines the type of Jam used
during CSMA/CD operation when a collision occurs.
IPNI.O CPGSRV) - Assigns the priority of GSC receive If set to a 1 then a low D.C. level is used as the jam
valid interrupt. signal. If cleared, then CRC is used as the jam signal.
The jam is applied for a length of time equal to the
IPNl.l (pGSRE) - Assigns the priority of asc error CRC length.
receive interrupt.
NOACK - No Acknowledgment error bit, see TSTAT.
IPNI.2 CPDMAO) - Assigns the priority of DMA done
interrupt for Channel O. NRZI - Non-Return to Zero inverted, a type of data
encoding where a 0 is represented by a change in the
IPN1.3 (PGSTV) - Assigns the priority of GSC trans- level of the serial link. A 1 is represented by no change.
mit valid interrupt.
OVR - Overrun error bit, see RSTAT.
IPNI.4 (PDMAI) - Assigns the priority of DMA done
interrupt for Channel 1. PR - Protocol select bit, see GMOD. PCON (87H)
76543210
IPNI.5 (PGSTE) - Assigns the priority of GSC trans-
mit error interrupt. ISMoolARSIREOIGARENIXRCLKIGFIENlpollOLI
ISA - Increment Source Address, see DCONO. PCON.O (IDL) - Idle bit, used to place the C152 into
the idle power saving mode.
LNI - Line Idle, see TSTAT.
PCON.I (PD) - Power Down bit, used to place the
LSC - Local Serial Channel - The asynchronous serial C152 into the power down power saving mode.
port found on all MCS-51 devices. Uses start/stop bits
and can transfer only 1 byte at a time. PCON.2 (GFIEN) - GSC Flag Idle Enable bit, when
set, enables idle flags (01111110) to be generated be-
MO - One of two GSC mode bits, see TMOD. tween transmitted frames in SDLC mode.
M1 - One of two GSC mode bits, see TMOD PCON.3 (XRCLK) - External Receive Clock bit, used
to enable an external clock to be used for only the re-
MYSLOT - (OFSH) ceiver portion of the GSC.
76543210
PCON.4 (GAREN) - GSC Auxiliary Receive Enable
1~locRI~I~I~I~I~I~1 bit, used to enable the GSC to receive back-to-back
SDLC frames. This bit has no effect in CSMAlCD
mode.
10-67
inter 83C152 HA.RDWARE DESCRIPTION
PCON.5 (REQ) - Requester mode bit, set to a I when RI - LSC Receive Interrupt bit. see SCON.
Cl52 is to be operated as the requester station during
DMA transfers. RFIFO - (F4H) RFIFO is a 3-byte FIFO that contains
the receive data from the GSc.
PCON.6 (ARB) - Arbiter mode bit, set to a I when
Cl52 is to be operated as the arbiter during DMA RSTAT (OE8H) - Receive Status Register
transfers. 76543210
PCON.7 (SMOD) - LSC mode bit, used to double the IOVRI RCASTIAElcRCE! RON! RFNE!GREN! HASEN I
baud rate on the LSC.
RSTAT.O (HBAEN) - Hardware Based Acknowledge
PDMAO - Priority bit for DMA Channel 0 interrupt, Enable - If set, enables the hardware based acknowl-
see IPNl. edge feature.
PDMAI - Priority bit for DMA Channel I interrupt, RSTAT.I (GREN) - Receiver Enable - When set, the
see IPNl. receiver is enabled to accept incoming frames. The user
must clear RFIFO with software before enabling the
PGSRE - Priority bit for GSC Receive Error interrupt, receiver. RFIFO is cleared by rcading the contents of
see IPNI. RFIFO until RFNE = O. After each read ofRFIFO, it
takes one machine cycle for the status of RFNE to be
PGSRV- Priority bit for GSC Rcceive Valid interrupt, updated. Setting GREN also dears RDN, CRCE, AE,
see IPNI. and RCABT. GREN is cleared by hardware at the end
of a reception or if any receive crrors are detected. The
PGSTE - Priority bit ,for GSC Transmit Error inter- status of GREN has no effect on whether the receiver
rupt, see IPNI. detects a col1ision in CSMA/CD mode as the receiver
input circuitry always monitors the receive pin.
PGSTV - Priority bit for GSC Transmit Valid inter-
rupt, see IPN 1. RSTAT.2 (RFNE) - Receive FIFO Not Empty - If set,
indicates that the receive FIFO contains data; The re-
PLO - One of two bits that determines the Preamble ceive FIFO is a three byte buffer into which the receive
Length, see GMOD. data is loaded. A CPU read of the FIFO retrieves the
oldest data and automatically updates the FIFO point-
PLI - One of two bits that determines the Preamble ers. Setting GREN to a one will clear the receive FIFO.
Length, see GMOD. The status of this flag is controlled by the GSC. This bit
is cleared if user software empties receive FIFO.
PRBS - (OE4H) Pseudo-Random Binary Sequence, gen-
erates the pseudo-random number to be used in RSTAT.3 (RDN) - Receive Done - If set, indicates the
CSMA/CD backoff algorithms. successful completion of a receiver operation. Will not
be set if a CRC, alignment, abort, or FIFO overrun
PS - Priority bit for .the LSC service interrupt, see IP. error occurred.
PTO - Priority bit for Timer 0 interrupt, see IP. RSTAT.4 (CRCE) - CRC Error - If set, indicates that a
properly aligned frame was received with a mismatched
PTl - Priority bit for Timer I interrupt, see IP. CRC. .
PXO - Priority bit for External interrupt 0, see IP. RSTAT.5 (AE) - Alignment Error - In CSMA/CD
mode; AE is set if the receiver shift register (an internal
PXI - Priority bit for External interrupt I, see IP. serial-ta-parallel converter) is not full and the CRC is
bad when an EOF is detected. In CSMA/CD the EOF
RCABT - GSC Receiver Abort error bit, see RSTAT. is a line idle condition (see LNI) for two bit times. If
the CRC is correct while in CSMA/CD mode, AE is
RDN - GSC Receiver Done bit, see RSTAT. not set and any mis-alignment is assumed to be caused
by dribble bits as' the line went idle. In SDLC mode,
GREN - GSC Receiver Enable bit, see RSTAT. AE is set if a non-byte-aligned flag is received. CRCE
may also be set. The setting of this flag is controlled by
RFNE - GSC Receive FIFO Not Empty bit, see the GSC.
RSTAT.
10-68
83C152 HARDWARE DESCRIPTION
RSTAT.6 (RCABT) - Receiver Collision/Abort Detect SCON.7 (SM2) - LSC mode specifier.
- If set, indicates that a collision was detected after data
had been loaded into the receive FIFO in CSMA/CD SDLC - Stands for Synchronous Data Link Communi-
mode. In SDLC mode, RCABT indicates that 7 consec- cation and is a protocol developed by IBM.
utive ones were detected prior to the end flag but after
data has been loaded into the receive FIFO. AE may SLOTTM - (OB4H) Determines the length of the slot
also be set if RCABT is set. time in CSMAlCD.
RSTAT.7 (OVR) - Overrun - If set, indicates that the SP (OBIH) - Stack Pointer, an eight bit pointer register
receive FIFO was full and new shift register data was used during a PUSH, POP, CALL, RET, or RET!.
written into it. It is cleared by user software. AE
and/or CRCE may also be set if OVR is set. TCDCNT - (OD4H) Contains the number of collisions
in the current frame if using probabilistic CSMA/CD
SARHO (OA3H) - Source Address Register IIigh 0, and contains the maximum number of slots in the de-
contains the high byte of the source address filr DMA terministic mode.
ChannelO.
TCDT - Transmit,Collision Detect, see TSTAT.
SARHI (OB3H) - Source Address Register High I,
contains the high byte of the source address for DMA TCON(OBBH)
Channel 1. 7 6 5 4 3 2 1 0
SARLO (OA2H) - Source Address Register Low 0, COIl- I TF1 I TR1 I TFO I TRO IIE1 IIT1 lEO liTO I
tains the low byte of the source address for DMA
Channel O. TCON.O (ITO) - Interrupt 0 mode control bit.
SARLI (OB2H) - Source Address Register Low I, con- TCON.I (lEO) - External interrupt 0 edge flag.
tains the low byte of the source address for DMA
Channell. TCON.2 (IT!) - Interrupt 1 mode control bit.
SAS - Source Address Space bit, see DCONO. TCON.3 (lEI) - External interrupt 1 edge flag.
SBUF (099H) - Serial Buffer, both the receive and TCONA (TRO) - Timer 0 nlll control bit.
transmit SFR location for the LSC.
CON.5 (TFO) - Timer 0 ovcrlluw flag.
SCON(09SH)
76543210 TCON.6 (TRI) - TillieI'I run control bit.
ISMO I SM1 15M2 I REN I TBB I RBB I TI I RI I TCON.7(TFI) - TillieI'I ovcrllow flag.
SCON.O (RI)- Receive Interrupt flag. TDN - Transmit DOlle nag, see TSTAT.
SCON.I (TI) - Transmit Interrupt flag. TEN - Transmit Enable hit. see TSTAT.
SCON.2 (RBS) - Receive Bit S, contains the ninth bit TFNF - Transmit FIFO Not Full flag, see TSTAT.
that was received in Modes 2 and 3 or the stop bit in
Mode 1 if SM20. Not used in Mode O. TFIFO -(B5H) TFIFO is a 3-byte FIFO that contains
the transmission data for the GSC.
SCON.3 (TBS) - Transmit Bit B, the ninth bit to be
transmitted in Modes 2 and 3. THO (OBCH) - Timer 0 High byte, contains the high
byte for timer/counter O.
SCONA (REN) - Receiver Enable, enables reception
for the LSC.
SCON.5 (SM2) - Enables the multiprocessor communi-
cation feature in Modes 2 and 3 for the LSC.
SCON.6 (SMI) - LSC mode specifier.
10-69
intJ 83C152 HARDWARE DESCRIPTION
THI (OSDH) - Timer I High byte, contains the high ter a successful transmission. a collision during the
byte for timer/counter 1. data, CRC, or end flag. If cleared during a transmission
the GSC transmit pin goes to a steady state high level.
TI - Transmit Interrupt, see SCON. This is the method used to send an abort character in
SDLC. Also DEN is forced to a high level. The end of
TLO (OSAH) - Timer 0 Low byte, contains the low byte transmission occurs whenever the TFIFO is emptied.
for timer/counter O.
TSTAT.2 (TFNF) - Transmit FIFO not full - When
TLI (OSBH) - Timer I Low byte, contains the low byte set, indicates that new data may be written into, the
for timer/counter 1. transmit FIFO. The transmit FIFO is a three byte buff-
er that loads the transmit shift register with data.
TM - Transfer Mode, see, DCONO.
TSTAT.3 (TDN) - Transmit Done - When set, indi-
TMOD(OS9H) cates the successful completion of a frame transmission.
76543210 If HBAEN is set, TDN will not be set until the end of
the IFS following the transmitted message, so that the
IGATE I clf IM1 I MO I GATE I CIT I M1 I MO I acknowledge can be checked. If an acknowledge is ex-
pected and not received, TDN is -not set. An acknowl-
TMOD.O (MO) - Mode selector bit for Timer O. edge is not expected following a broadcast or multi-cast
packet.
TMOD.I (MI) - Mode selector bit for Timer O.
TSTAT.4 (TCDT) - Transmit Collision Detect -Ifset,
TMOD.2 (clf) - Timer/Counter sclcctorbit for indicates that the transmitter halted due to a collision.
TimerO. It is set if a collision occurs during the data or CRC or
if there arc more than eight collisions.
TMOD.3 (GATE) - Gating Mode bit for Timer O.
TSTAT.5 (UR) - Underrun - If set, indicates that in
TMOD.4 (MO) - Mode selector bit for Timer I. DMA mode the last bit was shifted out of the transmit
register and that the DMA byte count did not equal
TMOD.5 (MI) - Mode selector bit for Timer 1. zero. When an underrun occurs, the transmitter halts
without sending the CRC or the end flag.
TMOD.6 (clf) - Timer/Counter selector bit for
Timer I. TSTAT.6 (NOACK) - No Acknowledge - If set,indi-
cates that no acknowledge was received for the previous
TMOD.7 (GATE) - Gating Mode bit for,Timer I. frame. Will be set only if HBAEN is set and no ac-
knowledge is received prior to the end of the IFS.
TSTAT (ODS) - Transmit Status Register NOACK is not set following a broadcast or a multi-
cast packet. '
76543210
I LNII NOACK I UR I TCDT I TONI TFNF I TEN DMA I I TSTAT.7 (LNI) - Line Idle - If set, indicates the re-
ceive line is idle. In SDLC protocol it is set if 15 consec-
utive ones are received. In CSMAlCD protocol, line
TSTAT.O (DMA) - DMA Select - If set, indicate~ that idle is set irGRXD remains high for approximately 1.6
DMA channels are used to service the GSC FIFO's and bit times. LNI is cleared after a transition on GR X D.
GSC interrupts,occur on TON and RDN, and also en-
ables UR to become set. If cleared, indicates that the TxC - External Clock input for GSC transmitter.
GSC is operating in it normal mode and interrupts oc-
cur on TFNE and RFNE.For more information on UR - Underrun flag, see TSTAT.
DMA servicing please refer to the DMA section on
DMA serial demand mode (4.2.2.3). ' XRCLK: - External GSC Receive Clock Enable bit, see
PCON.
TSTAT.I (TEN) - Transmit Enable - When set causes
TDN, UR, TCDT, and NOACK flags to be reset and XTCLK - External GSC Transmit Clock Enable bit,
the TFIFO cleared. The transmitter will clear TEN af- seeGMOD.
10-70
inter
8XC152JA/JB/JC/JD
UNIVERSAL COMMUNICATION CONTROLLER
8-BIT MICROCONTROLLER
• 8K Factory Mask Programmable ROM Available
• Superset of 80C51 Architecture • 64KB Data Memory Addressing
• Multi-Protocol Serial Communication • 256 Bytes On-Chip RAM
I/O Port (2.048 Mbps/2.4 Mbps Max)
• Dual On-Chip DMA Channels
- SDLC/HDLC Only
- CSMA/CD and SDLC/HDLC • Hold/Hold Acknowledge
- User Definable Protocols • Two General Purpose Timer/Counters
• Full Duplex/Half Duplex • 5 or 7 I/O Ports
.. MCS®-51 Compatible UART • 56 Special Function Registers
• 16.5 MHz Maximum Clock Frequency • 11 Interrupt Sources
• Multiple Power Conservation Modes • Available in 48 Pin Dual-in-Line Package
• 64KB Program Memory Addressing and 68 Pin Surface Mount PLCC
Package
(See Packaging Spec. Order #231369)
The 80C152, which is based on the MCS®-51 CPU, is a highly integrated single-chip 8-bit microcontroller
designed for cost-sensitive, high-speed, serial communications. It is well suited for implementing Integrated
Services Digital Networks (ISDN), emerging Local Area Networks, and user defined serial backplane applica-
tions. In addition to the multi-protocol communication capability, the 80C152 offers traditional microcontroller
features for peripheral I/O interface and control.
Silicon implementations are much more cost effective than multi-wire cables found in board level parallel-to-
serial and serial-to-parallel converters. The 83C152 contains, in silicon, all the features needed for the serial-
to-parallel conversion. Other 83C152 benefits include: 1) better noise immunity through differential signaling or
fiber optic connections, 2) data integrity utilizing the standard, designed in CRC checks, and 3) better modulari-
ty of hardware and software designs. All of these-cost, network parameter and real estato improvements-
apply to 83C152 serial links between boards or systems and 83C152 serial links on a single board.
October 1989
10-71 Order Number: 270431-003
inter 8XC152JAI JBI JCI JD
INO£X II'! .... '1 C"f "":
~ ~ ~ ~ ~ ~ > >
ce = H cJz ~ ~ ~ i t iii
(GRXD) Pl.0 Vee CORNER'\,.
(GTOX) P1.1 P'.O
(iilN) Pl.2 3 P'.1
P',6 P••5
(Wc) Pl.3 P'.2
Pl.7 P4.6
(RiC) P... P'.3 P4.7
(litO) Pl.5 8 P••' N.C.
(IIIJIl) P1.6 7 P'.5 P3.0 £A
Pl.7 P4.6 P3.1 ALE
(TOP Vlrw)
IIlSI.'T P'.7 P3.2 ffiN
(RXD) P3.0 £A N.C. N.C.
. (TXD) P3.; ALE 80C152JA
P3.3 N.c.
83C152JA
(iiffii) P3.2 PSEii P3.' N.C.
80C152JC
(iNTi) P3.3 P2.7 (A15) N.C. N.C.
83C152JC
(TO) P3•• P2.6 (A14) N.C. N.C.
(TI) P3.5 P2.5 (AI3) N.C. P2.7
(1'iR) P3.6 P2." (AI2) P3.5 P2.6
(1iIi) P3.7 P2.3 (AI1) P3.6 P2.5
(A/OO) PO.O P2.2 (AID) P3.7 P2.'
(A/Dl) PO.l P2.1 (A9) N.C. P2.3
(A/D2) PO.2 P2.0 (AS)
(A/03) PO.3 PO.7 (A/D7)
!l - :I ....
XTAL2 PO.n (A/D6)
~ "": C"f
~~~~~~>~ ~ ~
'1
g~ ~ ~ ~ ~ ~
XTALI PO.5 (A/D5)
Vss rD.", (A/D') 270431-2
270431-1
pus P".5
PI.7 P4.6
EO[N P4.7
mIl PI.3
P3.0 £A
P3.1 ALE
(TOP VIEW)
P3.2 PSEN
P5.0 fPSEN
80C152JB
P3.3 P6.2
80C152JD
P3.4 P6.7
P5.1 PI.'
P5.2 PS.7
PS.3 P2.7
P3.5 P2.6
P3.6 P2.5
P3.7 P2.4
N.C. P2.3
270431-3
Figure 1. Connection Diagrams
10·72
8XC152JA/JB/JC/JD
RXD
TXD
SPE-
GLOBAL
B kBYTE CIAL 256
8 BIT SERIAL
ROM/ FUNC- BYTES
CPU
8 CHANNEL
EPROM TION RAM
REGIS-
TERS
HLD/HLDA
._---------
INPUT INT
'On 80C152JBI JD Only 270431-18
Figure 2. Block Diagram
10-73
8XC152JA/JB/JC/JD
EPSEN is used in conjunction with Port 5 and Port 6
80C152JB/JD General Description program memory operations. EPSEN functions like
The 80C152JB/JD is a ROMless extension of the PSEN during program memory operation, but sup-
80C152 Universal Communication controller. The ports Port 5 and Port 6. EPSEN is the read strobe to
80C152JB has the same five 8-bit I/O ports of the external program memory for Port 5 and Port 6.
80C152, plus an additional two 8-bit I/O ports, Port 5 EPSEN is activated twice during each machine cycle
and Port 6. The 80C152JB/JD also has two addi- unless an external data memory operation occurs on
tional control pins, EBEN (EPROM Bus ENable), and Port(s) 0 and Port 2. When external data memory is
EPSEN (EPROM bus Program Store ENable). accessed the second activation of EPSEN is
skipped, which is the same as when using PSEN.
EBEN selects the functionality of Port 5 and Port 6. Note that data memory fetches cannot be made
When EBEN is low, these ports are strictly I/O, simi- through Ports 5 and 6.
lar to Port 4. The SFR location for Port 5 is 91 Hand
Port 6 is OA 1H. This means Port 5 and Port 6 are not When EBEN is high and EA is low, all program mem-
bit addressable. With EBEN low, all program memo- ory operations take place via Ports 5 and 6. The high
ry fetches take place via .Port o and Port 2. (The byte of the address goes out on Port 6, and the low
80C152 is a ROMless only product). When EBEN is byte is output on Port 5. ALE is still used to latch the
high, Port 5 and Port 6 form an address/data bus address on Port 5. Next, the op code is read on Port
called the E-Bus (EPROM-Bus) for program memory 5. The timing is the same as when using Ports 0 and
operations. . 2 for external program memory operations.
Table 1 Program Memory Fetches
Program
EBEN EA PSEN EPSEN Comments
Fetch via
0 0 PO,P2 Active Inactive Addresses O-OFFFFH
0 1 N/A N/A N/A Invalid Combination
1 0 P5,P6 Inactive Active Addresses O-OFFFFH
1 1 P5,P6 Inactive Active Addresses 0-1 FFFH
PO,P2 Active Inactive Addresses :<: 2000H
Table 2. 8XC152 Product Oifferences
CSMAICO ROM PLCC
ROM less HOLC/SOLC PLCC 5110 7110
and Version and
Version Only Only Ports Ports
HOLC/SOLC Available OIP
80C152JA
* *(83C152JA) * *
80C152JB
* * *
80C152JC
* *(83C152JC) * *
80C152JD
* * *
NOTES:
* = options available
o standard frequency range 3.5 MHz to 12 MHz
o "-1" frequency range 3.5 MHz to 16.5 MHz
10-74
infef 8XC152JAI JBtJCt JD
Pin # Pin Description
DIP PLCC(I)
48 2 Vcc-Supply voltage.
24 3,33(2) Vss-Circuit ground.
18-21, 27-30, Port O-Port 0 is an 8-bit open drain bidirectional 1/0 port. As an output port each pin
25-28 34-37 can sink 8 LS TIL inputs. Port 0 pins that have 1s written to them float, and in that
state can be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and data bus during accesses to
external program memory if EBEN is pulled low. During accesses to external Data
Memory, Port 0 always emits the low-order address byte and serves as the multiplexed
data bus. In these applications it uses strong internal pullups when emitting 1s.
Port 0 also outputs the code bytes during program verification. External pullups are
requ~red during program verification.
1-8 4-11 Port I-Port 1 is an 8-bit bidirectional 1/0 port with internal pullups. Port 1 pins that
havo 1s written to them are pullod high by the internal pullups, and in that state can be
used as inputs. As inputs, Port 1 pins that are externally being pulled low will source
curront (IlL, on tho data sheet) because of the internal pullups.
Port 1 also sorvos the functions of various special features of the 8XC152, as listed
below:
Pin Name Alternate Function
Pl.0 GRXD GSC data input pin
Pl.l GTXD GSC data output pin
Pl.2 DEN GSC enable signal for an external driver
Pl.3 TXC GSC input pin for external transmit clock
Pl.4 RXC GSC input pin for external receive clock
Pl.5 HLD DMA hold input/output
Pl.6 HLDA DMA hold acknowledge input/output
29-36 41-48 Port 2-Port 2 is an 8-bit bidirectional 1/0 port with internal pullups. Port 2 pins that
have 1s written to them are pulled high by the internal pullups, and in that state can be
used as inputs. As inputs, Port 2 pins that are externally being pullod low will source
current (IlL, on the data sheet) because of the internal pullups.
Port 2 emits the high-order address byte during fetches from extornal Program
Memory if EBEN is pulled low. During accesses to external Data Momory that use 16-
bit addresses (MOVX @ DPTR and DMA operations), Port 2 emits tho high-order
address byte. In these applications it uses strong internal pull ups whon emitting 1s.
During accesses to external Data Memory that use 8-bit addrossos (MOVX @ Ri),
Port 2 emits the contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits during program verification.
10-17 14-16, Port 3-Port 3 is an 8-bit bidirectional 1/0 port with internal pullups. Port 3 pins that
18,19, have 1s written to them are pulled high by the internal pullups, and in that state can be
23-25 used as inputs. As inputs, Port 3 pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the pull ups.
Port 3 also serves the functions of various special features of the MCS-51 Family, as
listed below:
Pin Name Alternate Function
P3.0 RXD Serial input line
P3.1 TXD Serial output line
P3.2 INTO External Interrupt 0
P3.3 INTI External Interrupt 1
P3.4 TO Timer 0 external input
P3.5 Tl Timer 1 external input
P3.6 WR External Data Memory Write strobe
P3.7 RD External Data Memory Read strobe
10-75
inter 8XC152JAlJB/JC/JD
Pin Description (Continued)
Pin # Pin Description
47-40 65-58 a
Port 4-Port 4 is an 8-bit bidirectional If port with internal pullups. Port 4 pins that
have 1s written to them are pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 4 pins that are externally being pulled low will
source current (IlL, on the data sheet) because of the internal pullups. In addition,
Port 4 also receives the low-order address bytes during program verification.
9 13 RST-Reset input. A logic low on this pin for three machine cycles while the
oscillator is running resets the device. An internal pullup resistor permits a power-on
reset to be generated using only an external capacitor to Vss. Although the GSC
recognize.s the reset after three machine cycles, data may continue to be
transmitted for up to 4 machine cycles after Reset is first appliod.
38 55 ALE-Address Latch Enable output signal for latching the low byte of the address
during accesses to external memory.
. In normal operation ALE is emitted at a constant rate of % tho oscillator
frequency, and may be used for external timing or clocking purposes. Note,
however, that one ALE pulse is skipped during each access to external Data
Memory. \fI!hile in Reset, ALE remains at a constant high levol.
37 54 PSEN-Program Store Enable is the Read strobe to External PrQ,gram Memory.
When the BXC152 is executing from external program memory, PSEN is active
(low). When the device is executing code from External Program Memory, PSEN is
activated twice each machine cycle, except that two PSEN activations are skipped
during each access to External Data Memory. While in Reset, PSEN remains at a
constant high level.
39 56 EA-External Access enable. EA must be externally pulled low in order to enable
the 8XC152 to fetch code from External Program Memory locations OOOOH to
OFFFH.
EA must be connected to Vee for internal program execution.
23 32 XTAL 1-lnput to the inverting oscillator amplifier and input to the internal clock
generating circuits.
22 31 XTAL2-0utput from the inverting oscillator amplifier.
NfA 17,20 a
Port 5-Port 5 is an 8-bit bidirectional If port with internal pullups. Port 5 pins that
21,22 have 1s written to them are pulled high by the internal pullups, and in that state can
38,39 be used as inputs. As inputs, Port 5 pins that are externally being pulled low will
40,49 source current (IlL, on the data sheet) because of the internal pull ups.
Port 5 is also the multiplexed low-order address and data bus during accesses to
external program memory if EBEN is pulled high. In this application it uses strong
pullups when emitting 1s.
NfA 67,66 a
Port 6-Port 6 is an 8-bit bidirectional If port with internal pullups. Port 6 pins that
52,57 have 1s written to them are pulled high by the internal pull ups, and in that state can
50,68 be used as inputs. As inputs, Port 6 pins that are externally pulled low will source
1,51 current(IIL, on the data sheet) because of the internal pullups.
Port 6 emits the high-order address byte during fetches from external Program
Memory if EBEN is pulled high. In this application it uses strong pullups when
emitting 1s.
NfA 12 EBEN-E-Bus Enable .input that designates whether program memory fetches take
place via Ports 0 and 2 or Ports 5 and 6. Table 1 shows how the ports are used in
conjunction with EBEN.
NfA 53 EPSEN-E-bus Program Store Enable is the Read strobe to external program__
memory when EBEN is high. Table 2 shows when EPSEN is used relative to PSEN
depending on the status of EBEN and EA.
10-76
8XC152JAI JBtJCtJD
OSCILLATOR CHARACTERISTICS
XT AL1 and XTAL2 aro the input and output, respec- NC - XTAL2
tively, of an inverting amplifier which can be config-
EXTERNAL
ured for use as an on-chip oscillator, as shown in , OSCILLATOR ---I XTAL 1
Figure 3. SIGNAL
To drive the device from an external clock source, .r-,-v_s_s__
XTAL1 should be driven, while XTAL2 is left uncon-
nected, as shown in Figure 4. There are no require-
270431-6
ments on the duty cycle of the external clock signal,
since the input to the internal clocking circuitry is Figure 4. External Clock Drive
through a divide-by-two flip-flop, but minimum and
maximum high and low times specified on the Data
Sheet must be observed.
An external oscillator may encounter as much as a
100 pF load at XT AL1 when it starts-up. This is due
IDLE MODE
In Idle Mode, the CPU puts itself to sleep while most
of the on-chip peripherals remain active. The major
III
to interaction between the amplifier and its feedback peripherals that do not remain active during Idle, are
capacitance. Once the external signal meets the VIL the DMA channels. The Idle Mode is invoked by
and VIH specifications the capacitance will not ex- software. The content of the on-chip RAM and all
ceed 20 pF. the Special Function Registers remain unchanged
during this mode. The Idle Mode can be terminated
by any enabled interrupt or by a hardware reset.
XTAL2
POWER DOWN MODE
XTAL 1 In Power Down Mode, the .oscillator is stopped and
all on-chip functions cease except that the on-Chip
t - - - - - - - I vss RAM contents are maintained. The modo Power
Down is invoked by software. Tho Power Down
Mode can be terminated only by a hardware reset.
270431-5
Figure 3. Using the On-Chip Oscillator
Table 3. Status of the External Pins During Idle and Power Down Modes
80C152JA/83C152JA/80C152JC/83C152JC
---~--
Program
Mode ALE PSEN PortO Port 1 Port 2 Port 3 Port 4
Memory
Idle Internal 1 1 Data Data Data Data Data
Idle External 1 1 Float Data Address Data Data
- ---
Power Down Internal 0 0 Data Data Data Data Data
Power Down External 0 ot Float Data Data Data Data
80C152JB/80C152JD
Instruction
Mode ALE PSEN EPSEN PortO Port 1 Port 2 Port 3 Port 4 Port 5 PortS
Bus
Idle PO,P2 1 1 1 Float Data Address Data Data OFFH OFFH
Idle P5,P6 1 1 1 Data Data Data Data Data OFFH Address
Power Down PO,P2 0 0 1 Float Data Data Data Data OFFH OFFH
Power Down P5,P6 0 1t 0 Data Data Data Data Data OFFH OFFH
NOTE:
For more detailed information on the reduced power modes refer to the Embedded Controller Handbook, and Application
Note AP-252, "Designing with the 80C51BH." .
tNote difference of logic level of PSEN during Power Down for ROM JA/JC and ROM emulation mode for JC/JD,
10-77
intJ axc 152JAI JBI JCI JD
ABSOLUTE MAXIMUM RATINGS* NOTICE: This data sheet contains preliminary infor-
mation on new products in production. The specifica-
AmbientTemperature Under Bias .... O°C to + 70°C tions are subject to change without notice.
Storage Temperature .......... - 65°C to + 150°C • WARNING: Stressing the device beyond the "Absolute
Voltage on Any pin to VSS .. - 0.5V to (Vee + 0.5V) Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
Voltage on Vee to VSS ........... -0.5V to + 6.5V "Operating Conditions" is .not recommended and ex-
Power Dissipation ....................... 1.OW(9) tended exposure beyond the "Operating Conditions"
may affect device reliability.
D.C. CHARACTERISTICS (TA= O°Cto + 70°C; Vee = 5V ±10%;Vss = OV)
Typ
Symbol Parameter Min Max Unit Test Conditions
(Note 3)
VIL Input Low Voltage -0.5 0.2Vee- 0.1 V
(All Except EA, EBEN)
VIL1 Input Low Voltage -0.5 0. 2Vee- 0.3 V
(EA, EBEN)
VIH Input High Voltage 0.2Vee+ 0.9 Vee+ 0.5 V
(Except XTAL 1, RST)
VIH1 Input High Voltage 0.7Vee Vee+ 0.5 V
(XTAL 1, RST)
-
VOL Output Low Voltage 0.45 V IOL = 1.6 mA
(Ports 1, 2, 3, 4, 5, 6) (Note 4)
VOL1 Output Low Voltage 0.45 V IOL = 3.2mA
(Port 0, ALE, PSEN, EPSEN) (Note 4)
VOH Output High Voltage 2.4 V IOH = -60/LA
(Ports 1, 2, 3, 4, 5, 6 COMM9 Vee = 5V ±10%
ALE, PSEN, EPSEN)
0.9Vee V IOH = -10/LA
VOH1 Output High Voltage 2.4 V IOH = -400/LA
(Port 0 in External Vee = 5V ±10%
Bus Mode)
0.9Vee V IOH = - 40 /LA (Note 5)
IlL JlcalO Input -50 /LA VIN = 0.45V
Current (Ports 1, 2, 3, 4, 5, 6)
ITL Logical 1 to 0 -650 /LA VIN = 2V
Transition Current
(Ports 1, 2, 3, 4, 5, 6)
III Input Leakage ±10 /LA 0.45 <VIN <Vee
(Port 0, EA)
RRST Reset Pullup Resistor 40 k.l1
IIH Logical 1 Input Current (EBEN) +60 /LA
lee Power Supply Current:
Active (16.5 MHz) 31 41.1 mA (Note 6)
Idle (16.5 MHz) 8 15.4 mA (Note 6)
Power Down Mode 10 /LA Vee = 2.0V to 5.5V
10-78
inter 8XC152JAt JBt Jct JD
MAX Icc (ACTIVE) = (2.24 X FREQ) + 4.16 (Note 6)
MAX Icc (IDLE) = (0.8 x FREQ) + 2.2 (Note 6)
45
40 MAX ICC (ACTIVE)
35 7
V TYPICAL Icc
30
""'
« 25 /' 7 (ACTIVE) (NOTE 1)
5u 20 ./ /1'
.2
15
10
5
0
./
,-::::
/' V
/
t::---" - .!---
MAX Icc (IDLE)
TYPICAL Icc
IDLE (NOTE 1)
4 8 12 16
FREQUENCY (MHz)
270431-7
Figure 5. Icc vs Frequency
EXPLANATION OF THE AC SYMBOLS P: PSEN.
Q: Output data.
Each timing symbol has 5 characters. The first char- R: READ signal.
acter is always a 'T' (stands for time). The other T: Time.
characters, depending on their positions, stand for V: Valid.
the name of a signal or the logical status of that W: WRITE signal.
signal. The following is a list of all the characters and X: No longer a valid logic level.
what they stand for. Z: Float.
A: Address. For example,
C: Clock
D: Input data. TAVLL = Time for Address Valid to ALE Low.
H: Logic level HIGH. TLLPL = Time for ALE Low to PSEN Low.
I: Instruction (program memory contents).
L: Logic level LOW, or ALE.
10-79
8XC152JA/JB/JC/JD
A.C. CHARACTERISTICS (TA = O°C to + 70°C; Vee = 5V ± 10%; VSS = OV; Load Capacitance for
Port 0, ALE, and PSEN = 100 pF; Load Capacitance for All Other Outputs = 80 pF)
EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS (Note 7, 10)
16.5 MHz Variable Oscillator
Symbol Parameter Unit
Min Max Min Max
1/TCLCL Oscillator Frequency 3.5 12 MHz
80C152JAlJC
83C152JAlJC
80C152JB/JD
80C152JAlJC-1 3.5 16.5 MHz
83C152JAI JC-1
80C152JB/JD-1
TLHLL ALE Pulse Width 81 2TCLCL-40 ns
TAVLL Address Valid to ALE Low 5 TCLCL-55 ns
TLLAX Address Hold After ALE Low 25 TCLCL-35 ns
TLLlV ALE Low to Valid 142 4TCLCL-100 ns
Instruction In
TLLPL ALE Low to PSEN Low 20 TCLCL-40 ns
TPLPH PSEN Pulse Width 137 3TCLCL-45 ns
TPLIV PSEN Low to Valid 77 3TCLCL-105 ns
Instruction In
TPXIX Input Instruction 0 0 ns
Hold After PSEN
TPXIZ Input Instruction_ 35 TCLCL-25 ns
Float After PSEN
TAVIV Address to Valid 198 5TCLCL-105 ns
Instruction In
TPLAZ PSEN Low to Address 10 10 ns
Float
TALAH AD Pulse Width 263 6TCLCL-1QO ns
TWLWH WA Pulse Width 263 6TCLCL-100 ns
TALDV AD Low to Valid 138 5TCLCL-165 ns
Data In
TAHDX Data Hold After AD 0 0 ns
TAHDZ Data Float After AD 51 2TCLCL-70 ns
TLLDV ALE Low to Valid 335 8TCLCL-150 ns
Data In
TAVDV Address to Valid 380 9TCLCL-165 ns
Data In
TLLWL ALE Low to AD or 132 232 3TCLCL-50 3TCLCL+50 ns
WALow
TAVWL Address to AD or 112 4TCLCL-130 ns
WALow
TQVWX(8) Data Valid to WA 196 6TCLCL-167 ns
Transition
TWHQX Data Hold After WA 10 TCLCL-50 ns
TALAZ AD Low to Address 0 0 ns
Float
TWHLH RD or WA High to 20 100 TCLCL-40 TCLCL+40 ns
ALE High
10-80
inter 8XC152JAt JBtJCt JD
EXTERNAL PROGRAM MEMORY READ CYCLE
ALE
--..I
PORTO/PORT 5
----'
PORT 2/PORT 6 A8-A15
---..I
270431-8
EXTERNAL DATA MEMORY READ CYCLE
ALE
PSEN
1 - - - - - - TLLDV ------1'1
- - - - l - - - - TRLRH - - - - - I
RD
PORTO INSTR. IN
PORT 2 P2.0-P2.7 OR A8-A 15 FROM DPH A8-lIl ~ fROM PCH
270431-9
10-81
8XC152JAI JBI JCI JD
EXTERNAL DATA MEMORY WRITE CYCLE
ALE
, I /
H- TWHLH
PSEN /
WR
I--- TLLWL
, TWLWH
~
.1
-- TAVLL I--- TLLAX----+j
TOVWX
-00
r- TWHOX
PORTO
~ AD-A? FROM R. OR DPL ) DATA OUT )( AD-A? FROM PCL INSTRo IN
TAVWL
PORT2 :::J. P200-P20? OR AB-A 15 FROM DPH X AB-A 15 FROM PCH
270431-10
EXTERNAL CLOCK DRIVE
Symbol Parameter Min Max Units
1/TClCl Oscillator Frequency 305 1605 MHz
TCHCX High Time 20 ns
TClCX low Time 20 . ns
TClCH Rise Time 20 ns
TCHCl Fall Time 20 ns
EXTERNAL CLOCK DRIVE WAVEFORM
270431-11
10·82
8XC152JAt JBtJCt JD
LOCAL SERIAL CHANNEL TIMING-SHIFT REGISTER MODE
16.5 MHz . Variable Oscillator
Symbol Parameter Units
Min Max Min Max
TXLXL Serial Port Clock Cycle 727 12TCLCL ns
Time
TQVXH Output Data Setup to 473 10TCLCL-133 ns
Clock Rising Edge
TXHQX
TXHDX
TXHDV
Output Data Hold After
Clock Rising Edge
Input Data Hold After
Clock Rising Edge
Clock Rising Edge to
Input Data Valid
4
473
2TCLCL-117
10TCLCL-133
ns
ns
ns
..
SHIFT REGISTER MODE TIMING WAVEFORMS
INSTRUCTION I 4 5
ALE
CLOCK
r-TQVXH~ r- TXHQX
OUTPUT DATA ''---';;'--r' '--";"'-..,-J '---..;.--'X'-_--'X'-_---'X 5 X'-_--'X'-____I
t t
WRITE TO SBUF SET TI
INPUT DATA _ _ _ _ _--'r-..:..:.~"-..J.-.;;,;;::;J'.'__J'\,;,;,;,;;;J '\._J~~''-_'''\,;.=''---I'''\,;.;~''
t t
CLEAR RI SET RI
270431-12
A.C. TESTING:
INPUT, OUTPUT WAVEFORMS FLOAT WAVEFORM
Vee- 0 . 5 = X 0.2Vee+0.9
0.2Vee-0.1
>C
0.45 v -...;,~-----
270431-13 270431-14
For Timing Purposes a Port Pin is no Longer Floating when a
AC Inputs During Testing are Driven at Vee-O.S for a Logic "1·' 100 mV change from Load Voltage Occurs. and Begins to Float
and OASV for a Logic "0". Timing Measurements are made at VIH
when a 100 mV change from the Loaded VOHIVOL Level occurs
Min for a Logic "I" and VIL Max for a Logic "0".
IOL/IOH ~ ± 20 mAo
10-83
inter 8XC152JA/JB/JC/JD
GLOBAL SERIAL PORT TIMINGS-Internal Baud Rate Generator
16.5 MHz (BAUD = 0) Variable Oscillator
Symbol Parameter Unit
Min Max Min Max
HBTJR Allowable jitter on 0.0375 (0.125 x /Jos
the Receiver for % (BAUD+1)X
bit time (Manchester 8TCLCL)
encoding only) -25 ns
FBTJR Allowable jitter on 0.10 (0.25 x /Jos
the Receiver' for one (BAUD+1)X
full bit time (NRZI 8TCLCL)
and Manchester) -25ns
HBTJT Jitter of data from ±10 ±10 ns
Transmitter for %
bit time (Manchester
encoding only)
FBTJT Jitter of data from ±10 ±10 ns
Transmitter for one
full bit time (NRZI
and Manchester)
--
DRTR Data rise time for 20 20 ns
Receiver(11 )
DFTR Data fall time for 20 20 ns
Receiver(12)
GSC RECEIVER TIMINGS (INTERNAL BAUD RATE GENERATOR)
I' BT -,
MANCHESTER : : : J (
I
I
~ , ~.
X·
I~~
I
~~:~I
X ~ x::::
I
I
GRxD
I HBTJR I FBTJR I
NRZI:::J(
~ )K
-I' .~ GRxD
" FBTJR
270431-15
8XC152JAI JBt JCt JD
GSC TRANSMIT TIMINGS (INTERNAL BAUD RATE GENERATOR)
~I'--------BT--------~'I I
I I
MANCHESTER ==:J(---"'~"'*'-9~,"----I..-""""~r>---J* ~ c:: GTxD
: '7s~' '-r;t;:;~-,:
~--------------_~~--~I~--~~~--------------~
________~ GTxD
NRZI--..A\______________'t~::.::::~'%.~::::::::.~f'
'1 1
FBTJT
270431-16
GLOBAL SERIAL PORT TIMINGS-External Clock
16.5 MHz Variable Oscillator
Symbol Parameter Unit
Min Max Min Max
1/ECBT GSC Frequency with an 2.4 0.009 FosC x 0.145 MHz
External Clock
ECH External Clock High 170 2TCLCL ns
+ 45 ns
ECL(13) External Clock Low 170 2TCLCL ns
+ 45 ns
ECRT External Clock Rise 20 20 ns
Time(11)
ECFT External Clock Fall 20 20 ns
Time(12)
ECDVT External Clock to Data ns
Valid Out - Transmit 150 150
(to External Clock
Negative Edge)
ECDHT External Clock Data ns
Hold - Transmit 0 0
(to External Clock
Negative Edge)
ECDSR External Clock Data 45 45 ns
Set-up - Receiver
(to External Clock
Positive Edge)
ECDHR External Clock to Data 50 50 ns
Hold - Receiver
(to External Clock
Positive Edge)
10-85
inter 8XC152JAlJB/JC/JD
GSC TIMINGS (EXTERNAL CLOCK)
I' ECBT 'I
1
~I )1
X"' ____..,I
II
EXTERNAL CLOCK \ f..
I . - - E C L - - ' : : - - ECH - - : 1
1 -J : - ECDYT
TRANSMIT DATA ---:r"\X :X,.---------,.--
. ECDHT -+t ~-
~I.~---------ECBT----------~.I 1
1 1 1
EXTERNAL CLOCK
~r~r
'-
_ _ _J/,r':----~\...
.
,I
'\
_ _ _ _~/~----~~
. I\.--
~ ECDSR '-ECDHR~
RECEIVE DATA ::::::::::X~; _____-':~::::::::::::::::::::::::::::
270431-17
NOTES:
1. N.C. pins on PLCC package may be connected to internnl die and should not be used in customer applications.
2. It is recommended that both Pin 3 and Pin 33 be groundod for PLCC dovices.
3. "Typicals" are based on samples taken from early manufacturing lots and are not guarantoed. The measurements were'
made with Vee = 5Vat room temperature.
4. Capacitive loading on Ports 0 and 2 may cause spurious noise pulsos to bo superimposed on the VOLS of ALE and Ports
1 and 3. The noise is due to external bus capacitance discllarging into the Port 0 and Port 2 pins when these pins make 1-
to-O transitions during bus operations. In the worst cases (capacitivo loading > 100 pF), the noise pulse on the ALE pin may
exceed O.BV. In such cases it may be. desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt
Trigger STROBE input.
5. Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9Vee specifi-
cation when the address bits are stabilizing.
6. lee is measured with all output pins disconnected; XTAL 1 driven with TCLCH, TCHCL = 5 ns, ~ = VSS + 0.5V, VIH =
Vee - 0.5V; XTAL2 N.C.; Port 0 pins connected to Vee. "Operating" current is measured with EA connected to Vee and
RST connected to Vss. "Idle" current is measured with EA connected to Vss, RST connected to Vee and GSC inactive.
7. The specifications relating to external data memory characteristics are also applicable to DMA operations.
B. TaVWX should not be confused with TaVWX as specified for BOC51 BH. On BOC152, TaVWX is measured from data
valid to rising edge of WR. On BOC51BH, TaVWX is measured from data valid to falling edge of WR. See timing diagrams.
9. This value is based on the maximum allowable die temperature and the thermal resistance of the package.
10. All specifications relating to external program memory characteristics are applicable to:
EPSEN for PSEN
Port 5 for Port 0
Port 6 for Port 2
when EBEN is at a Logical 1 on the BOC152JBI JD.
11. Same as TCLCH, use External Clock Drive Waveform.
12. Same as TCHCL, use External Clock Drive Waveform.
13. When using the same external clock to drive both the receiver and transmitter, the minimum ECL spec effectively
becomes 195 ns at all frequencies (assuming 0 ns propagation delay) because ECDVT (150 ns) plus ECDSR (45 ns) re-
quirements must also be met (150 + 45 = 195 ns). The 195 ns requirement would also increase to include the maximum
propagation delay between receivers and transmitters.
10-86
inter 8XC152JA/JB/JC/JD
DESIGN NOTES
Within the 8XC152 thero exists a race condition that may set both the RDN and AE bits at the end of a valid
reception. This will not cause a problem in the application as long as the following steps are followed:
-Never give the receivo error interrupt a higher priority than the valid reception interrupt
-Do not leave the valid reception interrupt service routine when AE is set by using a RETI instruction until AE
is cleared. To clear AE sot the GREN bit, this enables the receiver. If the user desires that the receiver remain
disabled, clear GREN after setting it before leaving the interrupt service routine.
-If the AE bit is checked by user software in response to a valid reception interrupt, the status of AE should
be considered invalid.
The race condition is dependent upon both the temperature that the device is currently operating at and the
processing the devico roceived during the wafer fabrication.
When the idle modo is terminated by a hardware resot, the device normally resumes program execution, from
where it left off, up to two machine cycles before tho internal reset algorithm takes control. On-chip hardware
inhibits access to intornal RAM in this event, but access to the port pins is not inhibited. To eliminate the
possibility of an unexpected write when Idle is terminated by reset, the instruction following the one that
invokes Idle should not be one that writes to a port pin or to external memory.
DATA SHEET REVISION SUMMARY
The following represent the. key differences between the "-003" and the "-002" version of the
80C152/83C152 data sheet. Please review this summary carefully.
1. Removed minimum GSC frequency spec when used with an external clock.
2. Change figure "External Program Memory Read Cycle" to show Port O/Port 5 address floating after PSEN
goes low.
3. Added design note on terminating idle with reset.
4. Added status of PSEN during Power Down mode to Table 3.
5. Moved all notes to back of data sheet.
6. Changed microcomputer to microcontroller.
7. Added External Oscillator start-up capacitance note.
The following represent the key differences between the "-002" and the "-00 t" version of the 80C152/
83C152 data sheet. Please review this summary carefully.
1. Status of data sheet changed from "ADVANCED" to "PRELIMINARY".
2. 80C152JC, 83C152JC, and 80C152JD were added.
3. Added AE/RDN design note.
4. This revision summary was added.
5. Note # 13 was added (Effective ECl spec at higher clock rates).
6. Table #2 changed to Table #3 (Status of pins during Idle/Power Down).
7. Current Table #2 was added (JA vs. JB vs. JC vs. JD matrix).
8. Transmit jitter spec changed from ± 35 ns and ± 70 ns to ± 10 ns.
10-87
8XC152JA/JB/JC/JD
UNIVERSAL COMMUNICATION CONTROLLER
8-BIT MICROCOMPUTER
EXPRESS
8XC152JA/JB/JC/JO-1-3.5 MHz to 16.5 MHz Vee = 5V ± 10%
8XC152JA/JB/JC/JD-3.5 MHz to 12 MHz Vee = 5V ± 10%
• Extended Temperature·Range • Burn-In
The Intel EXPRESS system offers enhancements to the operational specifications of the 8XC152 microcon-
trolier. These EXPRESS products are designed to meet the needs of those applications whose operating
requirements exceed commercial standards. . .
The EXPRESS program includes the commercial standard temperature range with burn-in and an extended
temperature range.
With the commercial standard temperature range, operational characteristics are guaranteed over the temper-
ature range of O·C to + 70·C. With the extended temperature range option, operational characteristics are
guaranteed over the range of - 40·C to + 85·C.
The optional burn-in is dynamic for a minimum time of 160 hours at 125·C with Vee = 6.9V ± 0.25V, following
guidelines in MIL-STD-883, Method 1015.
Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part number. The
prefixes are listed in Table 1.
For the extended temperature range option, this data sheet specifies the parameters which deviate from their
commercial temperature range limits. The commercial temperature range data sheets are applicable for all.
parameters not listed here. This data sheet is valid in conjunction with the commercial data sheet, 270431-
003.
October 1990
10-88 Order Number: 270540-003
inter 8XC152JAlJB/JC/JD
Electrical Deviations from Commercial Specifications for Extended Temperature
Range
D.C. and A.C. parameters not included here are the same as in the commercial temperature range data
sheets, Maximum oscillator frequency for express products is 12 MHz.
D.C. CHARACTERISTICS TA = -40°C to +85°C;Vcc = 5V ±10%;Vss = OV
Limits Test
Symbol Parameter Unit
Min Max Conditions
VIL Input Low Voltage (Except EA, EBEN) -0.5 0.2VCC - 0.15 V
VIL1 EA, EBEN -0.5 0,2VCC - 0.35 V
VIH Input High Voltage (Except XTAL 1, RST) 0.2VcC + 1.0 VCC + 0.5 V
VIH1 Input High Voltage to XTAL 1, RST 0.7Vcc + 0.1 VCC + 0.5 V
IlL Logical 0 Input Current (Port 1, 2, 3, 4, 5, 6) -75 p.A Vin = 0.45V
ITL Logical 1 to 0 transition -750 p.A Vin = 2.0V
Current (Ports 1, 2, 3, 4, 5, 6)
Table 1. Prefix Identification
Prefix Package Type Temperature Range Burn-In
P Plastic Commercial No
C Ceramic Commercial No
N PLCC Gommercial No
LP Plastic Extended . __ ._- Yes
LC Ceramic Extended Yes
.-
LN PLCC Extended Yes
._--
NOTE:
• Commercial temperature range is O°C to 70'C. Extended temperature range is -40°C to + 85"C;.
• Burn-in is dynamic for a minimum time of 160 hours at 125'C, Vee = 6.9V t· 0.25V, followino Ould(}linos in MIL-STO-883
Method 1015 (Test Condition OJ.
Examples:
P80C152JA indicates 80C152JA in a plastic package and specified for commercial temperature range, without
burn-in.
LC83C152JA indicates 83C152JA in a ceramic package and specified for extended temperature range with
burn-in.
DATA SHEET REVISION SUMMARY
The following represents the key differences between this data sheet and the "-001" version of the Express
80C152/83C152 data sheet. Please review this summary carefully.
1. Status of data sheet changed from "ADVANCED" to "PRELIMINARY".
2. 80C152JC, 83C152JC, and 80C152JD were added.
3. This revision summary was added.
The following represents the key differences between this data sheet and the "-002!' version of the Expross
8XC152JAI JBI JCI JD data sheet.
1. Data sheet status changed from "Preliminary" to "Production".
10-89
UPI,,452 CHMOS 11
Programmable I/O Processor
UPI-452
CHMOS PROGRAMMABLE I/O PROCESSOR
83C452 - 8K x 8 Mask Programmable Internal ROM
80C452 - External ROM/EPROM
• 83C452/80C452:3.5 to 14 MHz Clock
Rate • Two 16-Bit Timer/Counters
• Software Compatible with the MCS-51 • Boolean .Processor
Family • Bit Addressable RAM
• 128-Byte Bi-Directional FIFO Slave • 8 Interrupt Sources
Interface • Programmable Full Duplex Serial
Channel
• Two DMA Channels
• 64KProgram Memory Space
• 256 x 8-Bit Internal RAM
• 64K Data Memory Space
• 34 Additional Special Function
Registers • 68-Pin PGA and PLCC
•
(See Packaging Spec., Order: # 231369)
40 Programmable I/O Lines
The Intel UPI-452 (Universal Peripheral Interface) is a 68 pin CHMOS Slave I/O Processor with a sophisticated
bi-directional FIFO buffer interface on the slave bus and a two channel DMA processor on-chip. The UPI-452
is the newest member of Intel's UPI family of products. It is a general.purpose slave 1/0 Processor that allows
the designer to grow a customized interface solution.
The UPI-4S2 contains a complete 80CS1 with twice the on-chip data and program memory. The sophisticated
slave FIFO module acts as a buffer between the UPI-452 internal CPU and the external host CPU. To both the
external host and the internal CPU, the FIFO module looks like a bi-directional bottomless buffer that can both
read and write data. The FIFO manages the transfer of data independent· of the UPI-4S2 cora CPU and
generates an interrupt or DMA request to either CPU, host or internal, as a FIFO service requost.
The FIFO consists of two channels:the Input FIFO and the Output FIFO. The division of tho FIFO module
array, 128 bytes, between Input channel and Output channel is programmable by the usor. Each FIFO byte
has an additional logical ninth bit to distinguish betWeen a data byte and a Data Stream Command byte.
Additionally, Immediate Commands allow direct, interrupt driven, bi-directional communication between the
UPI-4S2 internal CPU and external host CPU, bypassing the ~IFO.
The on-chip DMA processor allows high speed data transfers from one writeable memory space to another.
As many as 64K bytes can be transferred in a Single DMA operation. Three distinct momory spaces may be
used in DMA operations; Internal Data Memory, External Data Memory, and the Special Function Registers
(including the FIFO IN, FIFO OUT, and Serial Channel Special Functions Registers).
October 1990
11-1 Order Number: 231428·005
o ~s
o
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o0
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l
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,
ID r- g I FIFO mo f"lFO HOST- I IMMEDIATE HOST DMA
I INPUT MODULE OUTPUT f"lFO COMMAND AND
..
:-"
~
n
2:
'" ::.. I
I
CHANNEL SLAVE-
FIFO
INTERFACE
CHANNEL INTERFACE
SFR'S
I
I
I SFR'S
INTERRUPT
REQUEST
CONTROL
"'"
N -
;-
n
c
ii!.
ID
I
I
I
SFR'S
f"lN I CIN
IRPR IIWPR
SFR'S
.-.... ITHR IOTHR ..........
SLCONI MODE
SSTAT I CBP
SFR'S
FOUT I COUT
ORPR 10WPR
HCON
HSTAT
, '.
':1
:
f~
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-,.,lo. .. , .. .110. II
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I HOLD/
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ARBITRAnON
... j>.
A
-r-
II.
V
DCONO
DMA TIMING
AND CONTROL
SFR'S
DCON 1 _
SARO SAR 1
DAR 0 DAR 1
..
BCRO BCR 1
",L - '-r- - - - r-- - - - - - - - - - - - - - - - - - - - -
...~ @) @ @
Sl l.I / /
.!..
inter UPI-4S2
r--------------------- -- ,
PSEN
ALE
EA
RST
L~::::::::::::::::::::::::::::::::::::~ ..~ffi
02:
~
.,.,
I
C!
a:
-~~----------------~
VS~CCI
231428-2
Figure 1. Architectural Block Diagram (Continued)
11·3
UPI·452
TABLE OF CONTENTS
CONTENTS PAGE
Introduction ............................... ~ ........................................ '" 11-1
Table of Contents.................................... ................. . ............... 11-4
List of Tables and Figures ............................................................... 11-5
Pin Description .......................................................................... 11-8
Architectural Overview ................................................................. 11-11
Introduction ..... ; ...,.. .' ............................................................. 11-11
FIFO Buffer Interface ................................................................ 11-11
FIFO programmable Features ....................................................... 11-12
Immediate Commands .............................................................. 11-13
'DMA ...... '.......................................................................... 11-13
FIFO/Slave Interface FunctionalDescription ............................................ 11-13
Overview ..... ,..... : ................................................................. 11-13
Input FIFO Channel •................................................................ 11-13
Output FIFO ,Channel ................................................................ 11-15
Immediate Commands .............................................................. 11-16
Host & Slave Interface Special Function Registers ................................... 11-18
Slave Interface Special Function Registers ....................................... 11-18
External Host Interface Special Function Registers ................................ 11-20
FIFO Module-External Host Interface ............................................... 11-22
Overview ......................................................................... 11-22
Slave Interface Address Decoding ................................................ 11-22
Interrupts to the Host ............................................................. 11-22
DMA Requests to the Host ....................................................... 11-24
FIFO Module-Internal CPU Interface ............................................... 11-24
Overview ..............•....•..... " ... , .......................... '................. 11-24
Internal CPU Access to FIFO via Software Instructions ............................ 11-24
General Purpose DMA Channels ....................................................... 11-25
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-25
, Architecture ................ '..........................'............................... 11-25
DMA Special Function Registers ..................................................... 11-26
DMA Transfer Modes ................................................................ 11-27
External Memory DMA .............................................................. 11-29
Latency ....... ; ..................................................................... 11-29
DMA Interrupt Vectors ............................................................... 11-29
Interrupts When DMA is Active ...................................................... 11-30
DMA Arbitration ..................................................................... 11-30
Interrupts .............................................................................. 11-32
Overview ............................................................................ 11-32
FIFO Module Interrupts to Internal CPU .............................................. 11-32
Interrupt Enabling and Priority ....................................................... 11-33
FIFO-External Host Interface FIFO DMA Freeze Mode ................................. 11·35
Overview ............................................................................ 11-35
Initialization .......................................................................... 11-35
Invoking FIFO DMA Freeze Mode During Normal Operation .......................... 11-36
FIFO Module Special Function Register Operation During FIFO DMA Freeze Mode ... 11-37
Internal CPU Read & Write of the FIFO During FIFO DMA Freeze Mode .............. 11-41
Memory Organization ............................................................. 11-41
Accessing External Memory .............. : .......................................... 11-41
Miscellaneous Special Function Register Descriptions ............................... 11·43
11-4
intJ UPI-4S2
LIST OF TABLES AND FIGURES
Figures:
1. Architectural Block Diagram. . . . .. . . . . . . . . .. . . . . . . . . . . . . . . . .. . . . . . . ... . . . . . . . . .. 11-2
2. UPI-452 68-Pin PGA Pinout Diagram ............................................. 11-6
2a. UPI452 68-Pin PLCC Pinout Diagram ............... : ............................ 11-7
3. UPI-452 Conceptual Block Diagram ............................................ 11-11
4. UPI-452 Functional Block Diagram ............................................. 11-12
5. Input FIFO Channel Functional Block Diagram .................................. 11-14
6. Output FIFO Channel Functional Block Diagram ................................ 11-15
7a. Handshake Mechanisms for Handling Immediate Command IN Flowchart ....... 11-17
7b. Handshako Mechanisms for Handling Immediate Command OUT Flowchart .... 11-17
8. DMA Transfer from: External to External Memory ............................... 11-31
9. DMA Transfer from: External to Internal Memory ................................ 11-31
10. DMA Transfer from: Internal to External Memory ................................ 11-31
11. DMA Transfer Waveform: Internal to Internal Memory ........................... 11-32
12. Disabling FIFO to Host Slave Interface Timing Diagram ......................... 11-36
Tables:
1. Input FIFO Cllannel Registers .................................................. 11-13
2. Output FIFO Channel Registers ................................................ 11-15
3. UPI-452 Address Decoding ..................................................... 11-23
4. DMA Accossible Special Function Registers .................................... 11-26
5. DMA Modo Control - PCON SFR ............................................... 11-29
6. Interrupt Priority ................................................................ 11-32
7. Interrupt Vector Addresses ..................................................... 11-32
8. Slave Bus Interface Status During FIFO DMA Freeze Mode ..................... 11-35
9. FIFO SFR's Characteristics During FIFO DMA Freeze Mode .................... 11-38
10. Threshold SFRs Range of Values and Number of Bytes to be Transferred ....... 11-39
11 a. Internal Memory Addressing ................................................... 11-41
11 b. 80C51 Special Function Registers ............................................. 11-42
11 c. UPI-452 Additional Special Function Registers .................................. 11-42
12. Program Status Word (PSW) ................................................... 11-44
13. PCON Special Function Register ............................................... 11-44
11-5
UPI-4S2
~
~
..... N
t. ...
q
~ ""
>
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C; @@ @ @ @ @ @ @ @
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0
P4.7 XTAL' ® @ @ @ PO.? PO.6
E
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<J
XTAL2 AO @ @ @ @ ro.s ·PO.4
"
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g Vss cs @ @ @ ® ro., Vss
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DROOUT!
'" WRiTE @ @ ® ® Pl.l Pl.2
1
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INTROOUT
INTRO @ @ 0 0 P1.3 P'.4
'E~
.. .0
OB7 DBS
® @@ @ ® ® @ @ @ CD CD Pl.5 Pl.6
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.., ..,.;
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"
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!>HRO @ @ 0 0 0 Pl.3 P1.4
£
ORQOUT!
wmrr @ @ ® ® PLI Pl.2
~-e INTllQOUT
-'"
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~ Q)
.~ :5
> c: Vss cs @ @ @ ® PO.I Vss
'" 0
'fNc:
~
Al A2 @ @ @ @ PO.3 PO.2
.,"
._ 0
>E XTAL2 AO @ @ @ @ PO.5 PO.4
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~~
P4.7 XTALI @ @ @ @ PO.7 PO.6
c:_
., c:
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o c: P4.5 P4.6 @ @@ @ @ @ @ @ @@) @ PSEN EA
0. 0
EO.
o E
uS
@@ @ @ @ ® @ @ @
. ...., .
U>
II. II. II.
0
oj
II.
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oj
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8 <I
231428-18
Figure 2. UPI-452 68-Pin PGA Pinout Diagram
11-6
intJ UPI-452
P.C. Board View-As' Viewed from the Component Side of the P.C. Board
(Underside of Socket)
0- :::E
0- C)
~~
"-
-.t N 0 U)
~
.,f
"-
.,f
"-
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.,f .,f .,f c-i c-i c-i c-i c-i
a.. a.. "- "- "- "-
@@@@@@@@@
P4.5 P4.6 @)@)@)@@®®@@@@ PSEN EA
P4.7 XTAL1 ®® @@) PO.7 PO.6
XTAL2 AO @@) e@ PO.5 PO.4
Al A2 @@ @@ PO.3 PO.2
Vss CS @@ €>® PO.l Vss
. DACK READ @)@ @0 PO.O Pl.0
WRITE DRaOUT!
INTRQOUT @@ @® P1.1 Pl.2
DRaIN/
INTRQIN
INTRa @@) 00 P1.3 P1.4
DB7 DB5 €!)@@€>€>@@@)@)<D0 P1.5 P1.6
€>9@@>@@@>@@ ~
I/')
III
'"c
III iii .... U) N 0 ...
II"!
c ..; ,.; ,.; ,.; ..; Ii:
PIN NO. 1 MARK
c "- "- "- "- "-
U)
III
...
III
N
III
0
III ~ ~
'",.; ,.; ":
C 0 0 c > '"
a.. "- "- a::
67 65 63 61 59 57 55 53
68 66 64 62 60 58 56 54 52
51
50
49
48
47
46
45
68 LEAD PLCC 44
43
TOP VIEW 42
41
40
39
38
37
36
35
18 20 22 24 26 28 30 ·32 34
19 21 23 25 27 29 31 33
231428-32
Figure 2A. UPI 452 S8-Pln PLCC Pinout Diagram
11-7
inter UPI-4S2
These UPI Microcontrollers are fully supported by
UPI MICROCONTROLLER FAMILY
Intel's development tools (ICE, ASM and PLM).
The UPI-452 .joins the current members of the UPI
microcontroller family. UPI's are derivatives of the
MCSTM family of microcontrollers. Because of their Packaging
on-chip system bus interface, UPI's are designed to
be system bus "slaves", while their microcontroller The 80C452/83C452 is available in either a 68-pin
counterparts are intended as system bus "masters". PGA (Pin Grid Array) or 68-pin PLCC package.
UPI Family MCSFamily
RAM ROM
(Slave (Master Speed
(Bytes) (Bytes)
Configuration) Configuration)
80C452 80C51 12MHz 256 -
83C452 80C51 12 MHz 256 8K
80C452-1 80C51 14 MHz 256 -
83C452-1 80C51 14MHz 256 8K
UPI-4S2 PIN DESCRIPTIONS
Symbol Pin # Type Name and Function
Vss 9/43 I Circuit Ground.
Vee 60 I + 5V power supply during normal and idle mode operation. It is also
the standby power pin for power down mode.
XTAL1 38 I Input to the oscillator's high gain amplifier. A crystal or external
source can bo used.
XTAL2 39 0 Output from tho high gain amplifier.
Port 0 I/O Port 0 is an 8-bit open drain bi-directionall/O port. Port 0 can sink
(ADO-AD?) eight LS TTL inputs. It is also the multiplexed low-order address and
PO.O 8 data local expansion bus during accesses to external memory.
.1 10
.2 11
.3 12
.4 13
.5 14
.6 15
PO.? 16
11-8
UPI-452
UPI-4S2 PIN DESCRIPTIONS (Continued)
Symbol Pin # . Type Name and Function
Port 1 liD Port 1 is an 8-bit quasi-bi-directionaII/O port. Port 1 can sink four
(AO-A~ LS TTL inputs. The alternate functions can only be activated if the
(HLD, HLDA) corresponding bit latch in the port SFR contains a 1. Otherwise, the
P1.0 7 port pin is stuck at O. Pins P1.5 and P1.6 are multiplexed with HLD
and HLDA respectively whose functions are defined as below:
.1 6 Port Pin Alternate Function
.2 5 P1.5 HLD -Local bus hold
.3 4 input! output signal
.4 3 P1.6 HLDA-Local bus hold
.5 2 acknowledge input
.6 1
P1.7 68
Port 2 1/0 Port 2 is an 8-bit quasi-bi-directionaII/O port. It also emits the high-
(A8-A15) ordor B bits of address when accessing local expansion bus
P2.0 29 oxtornal memory. Port 2 can sink four LS TTL inputs.
.1 28
.2 27
.3 25
.4 24
.5 23
.6 22
.7 21 .. ~
Port 3 1/0 Port 3 is an 8-bit quasi-bi-directionaII/O port. It is also multiploxed
P3.0 67 with the interrupt, timer, local serial channel, RD/ and WRI
.1 66 functions that are used by various options. The alternate functions
.2 65 can only be activated if the corresponding bit latch in the port SFR
.3 64 contains a 1. Otherwise, the port pin is stuck at O. Port 3 can sink
.4 63 four LS TTL inputs. The alternate functions assignod to the pins of
.5 62 Port 3 are as follows:
.6 61 Port Pin Alternate Function
P3.7 59 P3.0 RxD - Serial input port
P3.1 TxD - Serial output port
P3.2 INTO - Interrupt 0 Input
P3.3 INT1 -Interrupt 1 Input
P3.4 TO - Input to counter 0
P3.5 T1 -Input to counter 1
P3.6 WRf - The write control sinnallatchos the
data from Port 0 outputs into the
External Data Memory on the
local bus.
P3.7 RDI - The read control signal latches the
data from Port 0 outputs on the
local bus.
11-9
inter UPI-452
UPI-452 PIN DESCRIPTIONS (Continued)
Symbol Pin # Type Name and Function
Port 4 1/0 Port 4 is an 8-bit quasi-bi-directionaII/O port. Port 4 can sinkl
P4.0 30 source four TTL inputs.
.1
.2 32
.3 33
.4 34
.5 35
.6 36
.7 37
RST 20 I A high level on this pin for two machine cycles while the oscillator is
running resets the device. An internal pulldown resistor permits
Power-on reset using only a capacitor connected to Vee.
This pin does not receive the power down voltage as is the case for
HMOS MCS-51 family members. This function has been transferred
to the Vee pin. .
ALE 18 0 Provides Address Latch Enable output used for latching the
address into external memory during normal operation. ALE can
sink/source eight LS TTL inputs.
PSEN 19 0 The Program Store Enable output is a control signal that enables
the extern~..!"Q9ram Memory to the bus during normal fetch
operation. PSEN can sink/source eight LS TTL inputs.
EA 17 I When held at TTL high level, the UPI·452 executes instructions
from the internal ROM when the PC is less than 8192 (8K, 2000H).
When held at a TTL low level, the UPI-452 fetches all instructions
from external Program Memory.
080 58 1/0 Host 8us Interface is an 8-bit bi-directional bus. It is used to transfer
081 57 data and commands between the UPI-452 and the host processor.
082 56 This bus can sink/source eight LS TTL inputs.
083 55
084 54
DB5 53
DB6 52
DB? 51
CS 44 I This pin is tho Chip Select of the UPI-452.
AO 40 I These three address lines are used to interface with the host
A1 41 system. They define the UPI-452 operations. The interface is
A2 42 compatible with the Intel microprocessors and the MULTIBUS.
READ 46 I This pin is the read strobe from the host CPU. Activating this pin
causes the UPI-452 to place the contents of the Output FIFO (either
a command or data) or the Host Status/Control SpeCial Function
Register on the Slave Data Bus.
WRITE 47 I This pin is the write strobe from the host. Activating this pin will
cause the value on the Slave Data 8us to be written into the register
specified by AO-A2.
DROINI 49 0 This pin requests an input transfer from the host system whenever
INTRQIN the Input Channel requires data.
DROOUTI 48 0 This output pin requests an output transfer whenever the Output
INTROOUT Channel requires service. If the external host to UPI-452 DMA is
enabled, and a Data Stream Command is at the Output FIFO,
DROOUT is deactivated and INTRO is activated (see 'GENERAL
PURPOSE DMA CHANNELS' section).
11-10
inter UPI-4S2
UPI-4S2 PIN DESCRIPTIONS (Continued)
Symbol Pin # Type Name and Function
INTRQ 50 0 This output pin is used to interrupt the host processor when an
Immediate Command Out or an error condition is encountered. It is
also used to interrupt the host processor when the FIFO requests
service if the DMA is disabled and INTRQIN and INTRQOUT are
not used.
DACK 45 I This pin is the DMA acknowledge for the host bus interface Input
and Output Channels. When activated, a write command will cause
the data on the Slave Data Bus to be written as data to the Input
Channel (to the Input FIFO); A read command will cause the Output
Channol to output data (from the Output FIFO) on to the Slave Data
Bus. This pin should be driven high (+ 5V) in systems which do not
havo a DMA controller (see Address Decoding).
Vee 26 I I- 5V pow~r supply during operation.
ARCHITECTURAL OVERVIEW scription of the UPI-452's core CPU functional
blocks including;
- Timers/Counters
Introduction -I/O Ports
The UPI-452 slave microcontroller incorporates an - Interrupt timing and control (other than FIFO and
80C51 with double the program and data memory, a DMA interrupts)
slave interface which allows it to be connected di- - Serial Channel
rectly to the host system bus as a peripheral, a FIFO
buffer module, a two channel DMA processor, and a - Local Expansion Bus
fifth I/O port (Figure 3). The UPI-452 retains all of - Program/Data Memory structure
the 80C51 architecture, and is fully compatible with '--- Power-Saving Modes of Operation
the MCS-51 instruction set.
- CHMOS Features
The Special Function Register (SFR) interface con- - Instruction Set
cept introduced in the MCS-51 family of microcon-
trollers has been expanded in the UPI-452. To the Figure 3 contains a conceptual block diagram of the
20 Special Function Registers of the MCS-51, the UPI-452. Figure 4 provides <l functional block dia-
UPI-452 adds 34 more. These additional Special gram.
Function Registers, like those of the MCS-51, pro-
vide access to the UPI-452 functional elements in-
cluding the FIFO, DMA and added interrupt capabili- FIFO Buffer Interface
ties. Several of the 80C51 core Special Function
Registers have also been expanded to support add- A unique feature of the UPI-452 is the incorporation
ed features of the UPI-452. of a 128 byte FIFO array at the host-slave interface.
The FIFO allows asynchronous bi-directional trans-
This data sheet describes the unique features of the fers between the host CPU and the internal CPU.
UPI-452. Refer to the 80C51 data sheet for a de-
231428-7
Figure 3. UPI-4S2 Conceptual Block Diagram
11-11
inter UPI-452
ADDITIONAL FEATURES: I
-SERIAL CHANNEL :
-EXTERNAL INTERRUPTS
-HLD/HLD ACK
-LOCAL EXPANSION
BUS
-RD
-WR
-EXTERNAL
COUNTER INPUT
-EPROt.! PROGRAt.!
AND VERIFY
I10 _ _CONTROL
__________ _
231428-8
Figure 4. UPI-452 Functional Block Diagram
The division of the 128 bytes between Input and nel Boundary Pointer (CBP) SFR. This register con-
Output channels is user programmable allowing tains the number of address locations assigned to
maximum flexibility. If the entire 128 byte FIFO is the Input channol. The remaining address locations
allocated to the Input channel, a high performance are automatically assigned to the Output FIFO. The
Host can transfer up to 128 bytes at one time, then CBP SFR can only be programmed by the internal
dedicate its resources to other functions while· the CPU during FIFO DMA Freeze Mode (See FIFO-Ex-
internal CPU processes the data in the FIFO. Vari- ternal Host Interface FIFO DMA Freeze Mode de-
ous handshake signals allow the external Host to scription). The CBP is initialized to 40H (64 bytes)
operate independently and without frequent monitor- upon reset
ing of the UPI-452 internal CPU. The FIFO Buffer
insures that the slave processor receives data in the The number in the Channel Boundary Pointer SFR is
same order that it was sent by the host without the actually the first address . location of the Output
need to keep track of addresses. Three slave bus FIFO. Writing to the CBP SFR reassigns the Input
interface handshake methods are supported by the and Output FIFO address space. Whenever the CBP
UPI-452: DMA, Interrupt and Polled. is written, the Input FIFO pointers are reset to zero
and the Output FIFO pointers are set to the value in
The FIFO is nine bits wide. The ninth bit acts as a the CBP SFR.
command/data flag. Commands written to the FIFO
All of the FIFO space may be assigned to one chan-
by either the host or internal CPU are called Data
nel. In such a situation the other channel's data path
Stream Commands or DSCs. DSCs are written to
consists of a single SFR (FIFO IN/COMMAND IN or
the input FIFO by the Host via a unique external
FIFO OUT/COMMAND OUT SFR) location.
address. DSCs are written to the output FIFO by the
internal CPU via the COMMAND OUT Special Func- CBP Input FIFO Output FIFO
tion Register (SFR). When encountered by the host Register Size Size
or internal CPU a Data Stream Command can be 0 1 128
used as an address vector to user defined service 1 1 128
routines. DSCs provide synchronization of data and 2 2 126
commands between the Host and internal CPU. 3 3 125
4 4 124
FIFO .PROGRAMMABLE FEATURES 7B
•
123
• •
5
7C 124 4
Size of Input/Output Channels 7D 125 3
7E 128 1
The 128 bytes of FIFO space can be allocated be- 7F 128 1
tween the Input and Output channels via the Chan-
11-12
UPI-4S2
FIFO Read/Write Pointers of the three writeable memory spaces: Internal Data
Memory, External Load Expansion Bus Data Memo-
These normally operate in auto-increment (and auto- ry and the Special Function Register array. The Spe-
rollover) mode, but can be reassigned by the internal cial Function Register array appears as a set of
CPU during FIFO DMA Freeze Mode (See FIFO-Ex- unique dedicated memory addresses which may be
ternal Host Interface FIFO DMA Freeze Mode de- used as either the source or destination address of a
scription). DMA transfer. Each DMA channel is independently
programmable via dedicated Special Function Reg-
isters for mode, source and destination addresses,
Threshold Register and byte count to be transferred. Each DMA channel
has four programmable modes:
The Input FIFO Threshold SFR contains the number
of empty bytes that must be available in the Input - Alternate Cycle Mode
FIFO to generate a Host interrupt. The Output FIFO - Burst Mode
Threshold SFR contains the number of bytos, data - FIFO or Serial Channel Demand Mode
and/or DSC(s), that must be in the FIFO boforo an
interrupt is generated. The Threshold featuro pre- - External Demand Mode
vents the Host from being interrupted oacll time the
FIFO needs to load or unload one by to of data. The A complete description of each mode and DMA op-
thresholds, therefore, allow the FIFO's operation to eration may be found in the section titled "General
be adjusted to the speed of the Host, optimizing the Purpose DMA Channels".
overall interface performance.
FIFO/SLAVE INTERFACE
Immediate Commands FUNCTIONAL DESCRIPTION
The UPI-452 provides, in addition to data and DSCs,
a third direct means of communication between the Overview
external Host and internal CPU called Immediate
Commands. As the name implies, an Immediate The FIFO is a 128 Byte RAM array with recirculating
Command is available to the receiving CPU immedi- pointers to manage the read and write accesses.
ately, via an interrupt, without being entered into the The FIFO consists of an Input and an Output chan-
FIFO as are Data Stream Commands. Like Data nel. Access cycles to the FIFO by the internal CPU
Stream Commands, Immediate Commands are writ- and external Host are interleaved and appear to be
ten either via a unique external address by the host occurring concurrently to both the internal CPU and
CPU, or via dedicated SFR by the internal CPU. oxtornal Host. Interleaving access cycles ensures
officient use of this shared resource. The internal
The DSC and/or Immediate Command interface CPU accesses the FIFO in the same way it would
may be defined as either Interrupt or Polled under access any of the Special Function Registers e.g.,
user program control via the Interrupt Enable (IE), direct and register indirect addressing as well as ar-
Slave Control Register (SLCON), and Interrupt En- ithmetric and logical instructions.
able Priority (lEP) SpeCial Function Registers, for the
internal CPU and via the Host Control SFR for the
external Host CPU. Input FIFO Channel
The Input FIFO Channel provides for data transfer
DMA from the external Host to the internal CPU (Figure 5).
The registers associated with the Input Channel dur-
The UPI-452 contains a two channel internal DMA ing normal operation are listed in Table 1*.
controller which allows transfer of data between any
Table 1. Input FIFO Channel Registers'
Register Name Description
1) Input Buffer Latch Host CPU Write only
2) FIFO IN SFR Internal CPU Read only
3) COMMAND IN SFR Internal CPU Read only
4) Input FIFO Read Pointer SFR Internal CPU Read only
5) Input FIFO Write Pointer SFR Internal CPU Read only
6) Input FIFO Threshold SFR Internal CPU Read only
~-
'See "FIFO~EXTERNAL HOST INTERFACE FIFO DMA FREEZE MODE" seclion for FIFO DMA Freeze Mode SFR charactenslic,; d"';CflpIIOfi.
11-13
inter UPI-452
EXTERNAL HOST
CPU
EXTERNAL
ADDRESS HOST DATA
BUS
INPUT WRITE
POINTER (IWPR)
THRESHOLD SFR INPUT FIFO
(ITHR)
INPUT READ
POINTER (IRPR)
231428-9
Figure 5. Input FIFO Channel Functional Block Diagram
The host CPU writes data and Data Stream Com- The Input FIFO Channel addressing is controlled by
mands into the Input Suffer Latch on the rising edge the Input FIFO Read and Write Pointer SFRs. These
of the external WR signal. External addressing de- SFRs are read only registers during normal opera-
termines whether the byte is a data byte or Data tion. However, during FIFO DMA Freeze Mode (See
Stream Command and the FIFO logic sets the ninth FIFO-External Host Interface FIFO DMA Freeze
bit of the FIFO accordingly as the byte is moved Mode description), the internal CPU has writeac-
from the Input Suffer Latch into the FIFO. A "1" in cess to them. Any write to these registers in normal
the ninth bit indicates that the incoming byte is a mode will have. no effect. The Input Write Pointer
Data Stream Command. The internal CPU reads SFR contains the address location to which datal
data bytes via the FIFO IN SFR, and Data Stream commands are written from the Input Suffer Latch.
Commands via the COMMAND IN SFR. The write pointer is automatically incremented after
each write and is reset to zero if equal to the CSP,
A Data Stream Command will generate an interrupt as the Input FIFO operates as a circular buffer.
to the internal CPU prior to being read and after
completion of the previous operation. The DSC can If a write is performed on an empty FIFO, the first
then be read via the COMMAND IN SFR. Data can byte is also written into the FIFO IN or COMMAND
only be read via the FIFO IN SFR and Data Stream IN SFR. If the Host continues writing while the Input
Commands via the COMMAND IN SFR. Attempting FIFO is full, an external interrupt, if enabled, is sent
to read Data Stream Commands as data by address- to the host to signal the overrun condition. The
ing the FIFO IN SFR will result in "OFFH" being writes are ignored by the FIFO control logic. Similar-
read, and the Input FIFO Read Pointer will remain ly, an internal CPU read of an empty FIFO will cause
intact. (This prevents accidental misreading of Data an underrun error interrupt to be generated to the
Stream Commands.) Attempting to read data as internal CPU and a value of "OFFH" will be read by
Data Stream Commands will have the same corise- the internal CPU.
quence.
11·14
UPI-4S2
The Read Pointer SFR holds the address of the next number of bytes assigned to the Input FIFO (CBP)
byte to be read from the Input FIFO. An Input FIFO minus the number of bytes programmed in the Input
read operation post-increments the Input Read FIFO Threshold SFR. With this feature the Host is
Pointer SFR and loads a new data byte into the assured that it can write at least a threshold number
FIFO IN SFR or a Data Stream Command into the of bytes to the Input FIFO channel without worrying
COMMAND IN SFR at the end of the read cycle. about an overrun condition. Once the Request for
Service is generated it remains active until the Input
An Input FIFO Request for Service (via DMA, Inter- FIFO becomes full.
rupt or a flag) is generated to the Host whenever
more data can be written into the Input FIFO. For
efficient utilization of the Host, a "threshold" value Output FIFO Channel
can be programmed into the Input FIFO Threshold
SFR. The range of values of the Input FIFO Thresh- The Output FIFO Channel provides data transfer
old SFR can be from 0 to (CBP-3). The Request for from the UPI-452 internal CPU to the external Host
Service Interrupt is generated only after the Input (Figure 6).
FIFO has room to accommodate a threshold number
of bytes or more. The threshold is equal to the total The registers associated with the Output Channel
during normal operation are listed in Table 2*.
231426-10
Figure 6. Output FIFO Channel Functional Block Diagram
Table 2. Output FIFO Channel Registers
Register Name Description
1) Output Buffer Latch Host CPU Read only
2) FIFO OUT SFR Internal CPU Read and Write
3) COMMAND OUT SFR Internal CPU Read and Write
4) Output FIFO Read Pointer SFR Internal CPU Read only
5) Output FIFO Write Pointer SFR Internal CPU Read only
6) Output FIFO Threshold SFR Internal CPU Read only
'See "FIFO-EXTERNAL HOST INTERFACE FIFO DMA FREEZE MODE" section for FIFO DMA Freeze Mode register characteristic" oo"crlpllon.
11-15
inter UPI-4S2
The UPI-452 internal CPU transfers data to the Out- 2.) The second type of Request for Service is called
put FIFO via the FIFO OUT SFR and commands via "Flush Mode" and occurs when the internal CPU
the COMMAND OUT SFR. If the byte is written to writes a Data Stream Command into the Output
the COMMAND OUT SFR, the ninth bit is automati- FIFO. Its purpose is to ensure that a data block
cally set (= 1) to indicate a Data Stream Command. entered into the Output FIFO, which is less than
, If the byte is written to the FIFO OUT SFR the ninth the programmed threshold, will generate a Re-
bit is cleared (=0). Thus the FIFO OUT and COM- quest for Service interrupt, if enabled, and be
MAND OUT SFRs are the same but the address de~ read, or "Flushed" from the Output FIFO, by the
termines whether the byte entered in the FIFO is a external host CPU regardless of the status of the
DSC or data byte. OTHR SFR.
The Output FIFO preloads a byte into the Output
Buffer Latch. When the Host issues a RD! signal, Immediate Commands
the data is immediately read from the Output Buffer
Latch. The next data byte is then loaded into the Immediate Commands provide direct communica-
Output Buffer Latch, a flag is set and an interrupt, if tion between the external Host and UPI-452. Unlike
enabled, is generated if the byte is a DSC (ninth bit Data Stream Commands which are entered into the
is set). The operation is carefully timed such that an FIFO, the Immediate Command is available to the
interrupt can be generated in time for it to be recog- receiving CPU directly, bypassing the FIFO. The Im-
nized by the Host before its next read instruction, mediate Command can serve as a program vector
Internal CPU write and external Host read opera- pointing into a jump table in the recipients software.
tions are interleaved at the FIFO so that they appear Immediate Command Interrupts are generated, if en-
to be occurring concurrently. abled, and a bit in the appropriate Status Register is
set wilen an Immediate Command is input or output.
The Output FIFO read and write pointer operation is A similar bit is provided to acknowledge when an
the same as for the Input ChanneL Writing to the Immediate Command has been read and whether
FIFO OUT or COMMAND OUT SFRs will increment the register is available to receive another com-
the Output Write Pointer SFR but reading from it will mand. The bits are reset when the Immediate Com-
leave the write pointer unchanged. A rollover of the mands are read. Two Special Function Registers are
Output FIFO Write Pointer causes the pointer to be dedicated to the Immediate Command interface. Ex-
reset to the value in the Channel Boundary Pointer ternal addressing determines whether the Host is
(CBP) SFR. accessing the, Input FIFO or the Immediate Com-
mand IN (IMIN) SFR. The internal CPU writes Imme-
If the external host attempts to read a Data Stream diate Commands to the Immediate Command OUT
Command as a data byte it will result in invalid data (IMOUT) SFR.
(OFFH) being read. The DSCis not lost because the
invalid read does not increment the pointer. Similarly Both processors have the ability to enable or disable
attempting to read a data byte as a Data Stream Immediate Command Interrupts. By disabling the in-
Command has the same result. terrupt, the recipiel]t of the Immediate Command
can poll the status SFR and read the Immediate
A Request for Service is generated to the external Command at its convenience. 'Immediate Com-
Host under the following two conditions: mands should only be written when the appropriate
1.) Whenever the internal CPU has written a thresh- Immediate Command SFR is empty (as indicated in
old number of bytes or more into the Output FIFO the appropriate status SFR:HSTAT/SSTAT). Simi-
(threshold = (OTHR) + 1). The threshold num- larly, the Immediate Command SFR should only be
ber should be chosen such that the bus latency read when there is data in the Register.
time for the external Host does not result in a
FIFO overrun error condition on the internal CPU The flowcharts in Figure 7a and 7b illustrate the
side. The threshold limit should be large enough proper handshake mechanisms between the exter-
to make a bus request by the UPI-452 to the ex- nal Host and internal CPU when handling Immediate
ternal host CPU worthwhile. Once a request for Commands.
service is generated, the request remains active
until the Output FIFO becomes empty. The range
of values of the FIFO Output Threshold (OTHR)
SFR is from 2 to (80H-CBP)-1). The threshold
number can be programmed via the OTHR SFR.
11-16
intJ UPI-4S2
SET SET
Q
\::Y
III
.
,
GENERATES INTERRUPT
,
.It
GENERATES
TO INTE,RNAL CPU INTERRU~T TO HOST
, ,
,,
> >
SET SET
Q
\::Y
, ,
.iii .iii
GENERATES GENERATES INTERRUPT
INTERRUfT TO HOST TO INTERNAL CPU
,, ,,
231428-11 231428-12
Figure 7a. Handshake Mechanisms for Handling Figure 7b. Handshake Mechanisms for Handling
Immediate Command IN Flowchart Immediate Command OUT Flowchart
11-17
intJ UPI·452
HOST & SLAVE INTERFACE SPECIAL FUNCTION REGISTERS
Slave Interface Special Function Registers
The Internal CPU interfaces with the FIFO slave module via the following registers:
1) Mode Special Function Register (MODE)
2) Slave Control Special Function Register (SLCON)
3) Slave Status Special Function Register (SSTAD
Each register resides in the SFR Array and is accessible via all direct addressing modes except bit. Only the
Slave Control Register (SLCON) is bit addressable.
1) MODE Special Function Register (MODE)
The MODE SFR provides the primary control of the external host-FIFO interface. It is included in the SFR
Array so that the internal CPU can configure the external host-FIFO interface should the user decide that the
UPI-452 slave initialize itself independent of the external host CPU.
The MODE SFR can be directly modified by the internal CPU through direct address instructions. It can also be
indirectly modified by the external host CPU by setting up a MODE SFR service routine in the UPI-452 program
memory and having the host issue a Command, either Immediate or DSC, to vector to that routine.
SymbOlic Physical
Address Address
MODE MD6 MD5 MD4 OF9H
(MSB) (LSB)
Status On Reset:
1* o o o 1* 1* 1* 1*
MD7 (reserved)"
MD6 Request for Service to external CPU via;
1 DMA (DRQIN/DRQOUT) request to external host when the Input or Output FIFO channel re-
quests service
o = Interrupt (INTRQIN/INTRQOUT or INTRQ) to external host when the Input or Output FIFO
channel requests service or a DSC is encountered in the I/O Buffer Latch
MD5 Configure DRQINIINTRQIN and DRQOUT /INTRQOUT to be either;
1 = Enable (Actively driven)
o = Disable (Tri-state)
MD4 Configure INTRQ to be either;
1 = Enable (Actively driven)
o= Disable (Tri-state)
MD3 (reserved)"
MD2 (reserved)"
MD1 (reserved)"
MDO (reserved)"
2) Slave Control SFR (SLCON)
The Slave Control SFR is used to configure the FIFO-internal CPU interface. All interrupts are to the internal
CPU.
11-18
inter UPI-4S2
Symbolic Physical
Address Address
SLCON IFI OFI ICII ICOI FRZ IFRS OFRS OE8H
(MSB) (LSB)
Status On Reset:
0 o. 0 0 0 1"
I 0 0
IFI Enable Input FIFO Interrupt (due to Underrun Error Condition, Data Stream Command or Request
Service)
1 = Enable
0= Disable
OFI Enable Output FIFO Interrupt (due to Ovorrun Error Condition or Request Service)
1 =Enable
o= Disable
Note: If the DMA is configured to sorvico a FIFO demand, then the Request for Service Interrupt is
not generated.
ICII Generate Interrupt when a command is written to the Immediate Command in Register
1 = Enable
0= Disable
ICOI Generate Interrupt when Immediate Command Out Register is Available
1 = Enable
0= Disable
FRZ Enable FIFO DMA Freeze Mode
1 = Normal operation
o= FIFO DMA Freeze Mode
SC2 (reserved) ."
IFRS Input FIFO Channel Request for Service
1 = Request when Input FIFO not empty
o = Request when Input FIFO full
OFRS Output FIFO Channel Request for Service
1 = Request when Output FIFO not full
o= Channel Request when Output FIFO empty
NOTES:
"A '1' will be read from all SFR reserved locations except HCON SFR, HCO and HC2.
"'reserved'-these locations are reserved for future use by Intel Corporation.
3) Slave Status SFR (SSTAT)
The bits in the Slave Status SFR reflect the status of the FIFO-internal CPU interface. It can be read during an
internal interrupt service routine to determine the nature of the interrupt or read during a polling sequence to
determine a course of action.
Symbolic Physical
Address Address
SSTAT OE9H
o o o
(MSB) (LSB)
11-19
inter UPI-4S2
SST? Output FIFO Overrun Error Condition
1 = No Error
o = Error (latched until Slave Status SFR is read)
SST6 Immediate Command Out Register Status
1 = Full (i.e. Host CPU has not read previous Immediate Command Out sent by internal CPU)
o= Available
SST5 FIFO DMA Freeze Mode Status
1 = Normal Operation
o = FIFO DMA Freeze Mode in Progress
SST4 Output FIFO Request for Service Flag
1 =Output FIFO does not request service
o= Output FIFO requests service
SST3 Input FIFO Underrun Error Condition Flag
1 = No Underrun Error
o= Underrun Error (latched until Slave Status SFR is read)
SST2 Immediate Command In SFR Status
1 = Empty
o = Immediate Command received from host CPU
SSTl Data Stream Command/Data at Input FIFO Flag
1 = Data (not DSC)
o= DSC (at COMMAND IN SFR)
SSTO Input FIFO Request For Service Flag
1 = Input FIFO Does Not Request Service
o= Input FIFO Request for Service
EXTERNAL HOST INTERFACE SPECIAL FUNCTION REGISTERS
The external host CPU has direct access to the following SFRs:
1) Host Control Special Function Register
2) Host Status Special Function Register
It can also access other SFRsby commanding the internal CPU to change them accordingly via Data Stream
Commands or Immediate Commands. The protocol for implementing this is entirely determined by the user.
1) Host Control SFR (HCON)
By writing to the Host Control SFR, the host can enable or disable FIFO interrupts and DMA requests and can
reset the UPI-452. .
Symbolic Physical
Address Address
HCON HC? HC6 HC5 HC4 HC3 HC1 OE?H
(MSB) (LSB)
Status On Reset:
0 0 0 0 0 O' 0 O'
11-20
inter UPI-4S2
HC? Enable Output FIFO Interrupt due to Underrun Error Condition, Data Stream Command or Service
Request .
1 = Enable
0= Disable
HC6 Enable Input FIFO Interrupt due to Overrun Error Condition, or Service Request
1 = Enable
0= Disable
HC5 Enable the generation of the Interrupt due to Immediate Command Out being present
1 = Enable
0= Disable
HC4 Enable the Interrupt due to tho Immediate Command In Register being Available for a new Immediate
Command by to
1 = Enablo
o= Disable
HC3 Reset UPI-452
1 = Software RESET
o= Normal Operation
HC2 (reserved) **
HC1 Select between INTRO and INTROIN/INTROOUT as Request for Service interrupt signal when DMA is
disabled
1 = INTRO
o= INTROIN or INTROOUT
HCO (reserved) * *
NOTES:
*A '1' will be read from all SFR reserved locations except HCON SFR, HCO and HC2.
**'reserved'-theselocations are reserved for future use by Intel Corporation.
2) Host Status SFR (HSTAT)
The Host Status SFR provides information on the FIFO-Host Interface and can be usud to dotormine the,
source of an external interrupt during polling. Like the Slave Status SFR, the Host Status SFR reflects the
current status of the FIFO-external host interface.
Symbolic Physical
Address Address
HSTAT OE6H
1/0'
(MSB) (LSB)
11-21
UPI-4S2
HST7 Output FIFO Underrun Error Condition FIFO MODULE - EXTERNAL HOST
1 = No Underrun Error INTERFACE
o = Underrun Error (latched until Host
Status Register is read) Overview
HST6 Immediate Command Out SFR Status
The FIFO-external Host interface supports high
1 = Empty
speed asynchronous bi-directional 8-bit data trans-
o = Immediate Command Present fers. The host interface is fully compatible with Intel
HSTS Data Stream Command/Data at Output microprocessor local busses and with MULTIBUS.
FIFO Status The FIFO has two specialized DMA request pins for
1 = Data (not DSC) Input and Output FIFO channel DMA requests.
o = DSC (present at Output FIFO COM- These are multiplexed to provide a dedicated Re-
MAND OUT SFR) quest for Service interrupt (DRQIN/INTRQIN,
(Note: Only if HST4 = 0, if HST4 = 1 then un- DRQOUT /INTRQOUT).
determined)
The external Host can program, under user defined
HST4 Output FIFO Request for Service Status
protocol, thresholds into the FIFO Input and Output
1 = No Request for Service
Threshold SFRs which determine when the FIFO
o = Output FIFO Request for Service due to: Request for Service interrupt is generated to the
a. Output FIFO containing the threshold Host CPU. The FIFO module external Host inter,face
number of bytes or more is configured by the internal CPU via the MODE
b. Internal CPU sending a block of data ter- SFR. "The external Host can enable and disable
minated by a DSC (DSC Flush Mode) Host interface interrupts via the Host Control SFR."
HST3 Input FIFO Overrun Error Condition Data Stream Commands in the Input FIFO channel
allow tho Host to influence the processing of data
1 = No Overrun Error
blocks and are sent with the data flow to maintain
o = Overrun Error (latched until Host Status synchronization. Data Stream Commands in the
Register is read)
Output FIFO Channel allow the internal CPU to per-
HST2 Immediate Command In SFR Status form the same function, and also to set the Output
1 = Full (i.e. Internal CPU has not read pre- FIFO Request Service status logic to the host CPU
vious Immediate Command sent by Host) regardless of the programmed value in the Thresh-
o = Empty old SFR.
* Reset value;
'1' - if read by the external Host Slave Interface Address Decoding
'0' - if read by internal CPU (reads shadow The UPI-4S2 determines the desired Host function
latch - see FIFO DMA Freeze Mode descrip- through address decoding .. The lower three bits of
tion) the address as well as the READ, WRITE, Chip Se-
lect (CS) and DMA Acknowledge (DACK) are used
HST1 FIFO DMA Freeze Modo Status
for decoding. Table 3 shows the pin states and the
1 = Freeze Mode in progress.
(In Freeze Mode, the bits of the Host Status Read or Write operations associated with each con-
figuration.
SFR are forced to a '1' initially to prevent the
external Host from attempting to access the
FIFO. The definition of the Host Status SFR Interrupts to the Host
bits during FIFO DMA Freeze Mode can be The UPI-4S2 interrupts the external Host via the
found in FIFO DMA Freeze Mode descrip- INTRQ pin. In addition, the DRQIN and DRQOUT
tion) pins can be multiplexed as interrupt request lines,
o = Normal Operation INTRQIN and INTRQOUT respectively, when DMA
HSTO Input FIFO Request Service Status is disabled. This provides two special FIFO "Re-
1 = Input FIFO does not request service quest for Service" interrupts.
o = Input FIFO request service due to the
Input FIFO containing enough space for the There are eight FIFO-related interrupt sources; two
host to write the threshold number of bytes from The Input FIFO; three from The Output FIFO;
or more one from the Immediate Command Out SFR; one
from the Immediate Command IN SFR; and one due
to FIFO DMA Freeze Mode.
INPUT FIFO: The Input FIFO interrupt is generated
whenever:
a. The Input FIFO contains space for a threshold
number of bytes.
11-22
UPI·452
Table 3. UPI-452 Address Decoding
DACK CS A2 A1 AO Read Write
1 1 X X X No Operation No Operation
1 0 0 0 0 Data or DMA from Output FIFO Channel Data or DMA to Input FIFO Channel
1 0 0 0 1 Data Stream Command from Output FIFO Channel Data Stream Command to Input FIFO Channel
1 0 0 1 0 Host Status SFR Read Reserved
--
1 0 0 1 1 Host Control SFR Read Host Control SFR Write
1 0 1 0 0 Immediate Command SFR Read Immediate Command to SFR Write
--
1 0 1 1 X Roserved Reserved
0 X X X X DMA Data from Output FIFO Channel DMA Data to Input FIFO Channel
II
1 0 1 0 1 Hoserved Reserved
NOTES:
1. Attempting to read a DSC as a data byte will result in invalid data being read. The read pointers are not incremented so
that the DSC is not lost. Attompting to read a data byte as a DSC has the same result.
2. If DACK is active the UPI-452 will attempt a DMA operation when RD or WR becomes active regardless of the DMA
enable bit (MD6) in the MODE SFR. Care should be taken when using DACK. For proper operation, DACK must be driven
high (+ 5V) when not using DMA.
b. When an Input FIFO overrun error condition ex- b. An Immediate Command IN interrupt is generat-
ists. The appropriate bits in the Host Status SFR ed, if enabled, to the Host when the internal CPU
are set and the interrupt is generated only if en- has read a byte from the Immedfate Command IN
abled. (IMIN) SFR. The read operation clears the Host
Status SFR Immediate Command IN Status bit
OUTPUT FIFO: The Output FIFO Request for Serv- (HSTAT HST2) indicating· that the Immediate
ice Interrupt operates in a similar manner as the In- Command IN SFR is empty. The corresponding
put FIFO interrupt: Slave Status (SSTAT) SFR bit is also set to indi-
a. When the FIFO contains the threshold number of cate an empty status. Setting the Slave Status
bytes or more. SFR bit generates a FIFO-Slave Interface inter-
rupt, if enabled, to the internal CPU. (See Figure
b. Output FIFO error condition interrupts are gener-
7a, Immediate Command IN Flowchart.)
ated when the Output FIFO is underrun.
c. Data Stream Command present in the Output NOTE:
Buffer Latch. Immediate Command IN and OUT intorrupts are ac-
tually specific Request For Sorvico interrupts to the
A Data Stream Command interrupt is used to halt
Host.
normal processing, using the command as a vector
to a service routine_ When DMA is disabled, the user FIFO DMA FREEZE MODE: When the internal CPU
may program (through HC1) INTRa to include FIFO invokes FIFO DMA Freeze Mode, for example at re-
Request for Service Interrupts or use INTRalN and set or to reconfigure the FIFO interface, INTRa is
INTRaOUT as Request for Service Interrupts. activated. The INTRa can only be deactivated by
IMMEDIATE COMMAND INTERRUPTS: the external Host reading the Host Status SFR
(HST1 remains active until FIFO DMA Freeze Mode
a. An Immediate Command Out Interrupt is generat- is disabled by the internal CPU).
ed, if enabled, to the Host and the corresponding
Host Status SFR bit (HSTAT HST6) is cleared, Once an interrupt is generated, INTRa will remain
when the internal CPU writes to the Immediate high until no interrupt generating condition exists.
Command OUT (IMOUT) SFR. When the Host For a FIFO underrun/overrun error interrupt, the in-
reads the Immediate Command OUT (IMOUT) terrupt condition is deactivated by the external Host
SFR the corresponding bit in the Host Status reading the Host Status SFR. An interrupt is serv-
(HSTAT) SFR is set. This causes the Slave Status iced by reading the Host Status SFR to determine
Immediate Command OUT Status bit (SSTAT the source of the interrupt and vectoring the appro-
SST6) to be cleared indicating that the Immediate priate service routine.
Command OUT (IMOUT) SFR is empty. If en-
abled, a FIFO-Slave Interface will also be gener-
ated to the internal CPU. (See Figure 7b, Immedi-
ate Command OUT Flowchart.)
11-23
inter UPI-452
DMA Requests to the Host mition via the DMAO/DMA1 Source Address or Des"
tination Address Special Function Registers. The
The UPI-4S2 generates two DMA requests, DRQIN FIFO module manages the transfer of data between
and DRQOUT, to facilitate data transfer between the the external host and FIFO SFRs.
Host and the Input and Output FIFO channels. A
DMA acknowledge, DACK, is used as a chip select
and initiates a data transfer. The external READ and Internal CPU Access to FIFO Via
WRITE signals select the Input and Output FIFO re- Software Instructions
spectively. The CS and address lines can also be
used as a DMA. acknowledge for processors with The internal CPU has access to the Input and Out-
onboard DMA controllers which do not generate a put FIFOs via the FIFO IN/COMMAND IN and FIFO
DACK signal. OUT/COMMAND OUT SFRs which reside in the
Special Function Register Array. At the end of every
The internal CPU can configure the UPI-4S2 to re- instruction that.involves a read of the FIFO IN/COM-
quest service from the external host via DMA or in- MAND IN SFR, the SFR is written over by a new
terrupts by programming Mode SFR MDB bit. In ad- byte from the Input FIFO channel when available. At
dition the external Host enables DMA requests the end of every instruction that involves a write to
through bits Band 7 of the Host Control SFR. When the FIFO OUT/COMMAND OUT SFR, the new byte
a DMA request is invoked the number of bytes trans- is written into the Output FIFO channel and the write
ferred to the Input FIFO is the total number of bytes pointer is incremented after the write operation (post
in the Input FIFO (as determined by the CBP SFR) incremented).
minus the value programmed in the Input FIFO
Threshold SFR. The DMA request line is activated The internal CPU reads the Input FIFO by using the
only when the Input FIFO has a threshold number of FIFO IN/COMMAND IN SFR as the source register
bytes that can be transferred. in an instruction. Those instructions which read the
Input FIFO are listed below:
The Output FIFO DMA request is activated when a
DSC is written by the internal CPU at the end of a ADD A,FIFO IN/COMMAND IN
less than threshold size block of data (Flush Mode) ADDC A,FIFO IN/COMMAND IN
or when the Output FIFO threshold is reached. The PUSH FIFO IN/COMMAND IN
request remains active until the Input FIFO becomes
ANL A,FIFO IN/COMMAND IN
full or the Output FIFO becomes empty. If a DSC is
encountered during an Output FIFO DMA transfer, ORL A,FIFO IN/COMMAND IN
the DMA request is dropped until the DSC is read. XRL A,FIFO IN/cdMMAND IN
The DMA request will be reactivated after the DSC is CJNE A,FIFO IN/COMMAND IN, rei
read and remains active until the Output FIFO be- SUBB A,FIFO IN/COMMAND IN
comes empty or another DSC is encountered.
MOV direct,FIFO IN/COMMAND IN
MOV @Ri,FIFO IN/COMMAND IN
FIFO MODULE - INTERNAL CPU MOV Rn,FIFO IN/COMMAND IN
INTERFACE MOV A,FIFO IN/COMMAND IN
After each access to these registers, they are over-
Overview written by a new byte from the FIFO.
The Input and Output FIFOs are accessed by the NOTE:
internal CPU through direct addressing of the FIFO Instructions which use the FIFO IN or COMMAND
IN/COMMAND IN and FIFO OUT/COMMAND OUT IN SFR as both a source and destination register
Special Function Registers. All of the 80CS1 instruc- will have the. data destroyed as the next data byte
tions involving direct addressing may be used to ac- is rewritten into the FIFO IN register at the end of
cess the FIFO's SFRs. The FIFO IN, COMMAND IN the instruction. These instructions are not· support~
and Immediate.Command In SFRs are actually read ed by the UPI-4S2 FIFO. Data can only be read
only registers, and their Output counterparts are through the FIFO IN SFR and DSCs through the
write only. Internal DMA transfers data between In- COMMAND IN SFR. Data read through the COM-
ternal memory, External Memory and the Special MAND IN SFR will be read as OFFH, and DSCs
Function Registers. The Special Function Registers read through the FIFO IN SFR will be read as
appear as another group of dedicated memory ad- OFFH. The Immediate Command in SFR· is read
dresses and are programmed as the source or desti- with the same instructions as the FIFO IN and
COMMAND IN SFRs. .
11-24 .
inter UPI-452
The FIFO IN, COMMAND IN and Immediate Com- dress Register (DAR). (Note: Since the FIFO IN SFR
mand In SFRs are read only registers. Any write op- is a read only register, the DMA transfer will be ig-
eration performed on those registers will be ignored nored if it is used as a DMA DAR. This is also true if
and the FIFO pointers will remain intact. the FIFO OUT SFR is used as a DMA SAR.)
The internal CPU uses the FIFO OUT SFR to write Each DMA channel is software programmable to op-
to the Output FIFO and any instruction which uses erate in either Block Mode or Demand Mode. In the
the FIFO OUT or COMMAND OUT SFR as a desti- Block Mode, DMA transfers can be further pro-
nation will invoke a FIFO write. DSCs are differenti- grammed to take place in Burst Mode or Alternate
ated from data by writing to the COMMAND OUT Cycle mode. In Burst Mode, the processor halts its
SFR. In the FIFO, Data Stream Commands have the execution and dedicates its resources to the DMA
ninth bit associated with the command byte set to transfer. In Alternate Cycle Mode, DMA cycles and
"1 ". The instructions used to write to the Output instruction cycles occur alternately.
FIFO are listed below:
In Demand Mode, a DMA transfer occurs only when
MOV FIFO OUT /COMMOUT, A it is demanded. Demands can be accepted from an
MOV FIFO OUT /COMMOUT, direct external device (through External Interrupt pins,
MOV FIFO OUT/COMMOUT, Rn EXTO/EXT1) or from either the Serial Channel or
FIFO flags. In this way, a DMA transfer canbe syn-
POP FIFO OUT /COMMOUT
chronized to an external device, the FIFO or the Se-
MOV FIFO OUT/COMMOUT, #data rial Port. If the External Interrupt is configured in
MOV FIFO OUT/COMMOUNT, @Ri Edge Mode, a single byte transfer occurs per tran-
sition. The external interrupt itself will occur if en-
NOTE: abled. If the External Interrupt is configured in Level
Instructions which use the FIFO OUT/COMMAND Mode, DMA transfers continue until the Extornal In-
OUT SFRs as both a source and destination regis- terrupt request goes inactive or the byte count be-
ter cause invalid data to be written into the Output comes zero. The following flags activate Demand
FIFO. These instructions are not supported by the Mode transfers of one byte to/from the FIFO or Seri-
UPI-452 FIFO. al Channel:
RI - Serial Channel Receiver Buffer FlIll
GENERAL PURPOSE DMA CHANNELS TI - Serial Channel Transmit\or Suitor I:rllpty
Overview Architecture
There are two identical General Purpose DM/\ Chan- There are three 16 bit and one Obit Spocral I'unction
nels on the UPI-452 which allow high speou data Registers associated with each DM/\ Ch<lllliOI.
transfer from one writeable memory space to anoth- • The 16 bit Source Addres!; SI:ll (S/\Il) points to
er. As many as 64K bytes can be transferred in a the source byte.
single DMA operation. The following memory
spaces can be used with DMA channels: • Tho 16 bit Destination Aduross SFR (DAR) points
to tho destination.
o Internal Data Memory
• The 16 bit Byte Count SFR (SCR) contains the
• External Data Memory number of bytes to bo transferred and is decre-
• Special Function Registers mented when a byte transfer is accomplished.
• The DMA Control SFR (DCON) is eight bits wide
The Special Function Register array appears as a and specifies the source memory space, destina-
limited group of dedicated memory addresses. The tion memory space and the mode of operation.
Special Function Registers may be used in DMA
transfer operations by specifying the SFR as the In Auto Increment mode, the Source Address and/
source or destination address. The Special Function or Destination Address is incremented when a byte
Registers which may be used in DMAtransfers are is transferred. When a DMA transfer is complete
listed in Table 4. Table 4 also shows whether the (BCR = 0), the DONE bit is set and a maskable
SFR may be used as Source or Destination only, or interrupt is generated. The GO bit must be set to
both. start any DMA transfer (also, the Slave Control SFR
FRZ bit must be set to disable FIFO DMA Freezo
The FIFO can be accessed during DMA by using the Mode). The two DMA channels are designated as
FIFO IN SFR as the DMA Source Address Register DMAO and DMA 1, and their corresponding registors
(SAR) or the FIFO OUT SFR as the Destination Ad- are suffixed by 0 or 1; e.g. SARO, DAR 1, etc.
11-25
UPI·452
Table 4 DMA Accessible Special Function Registers
Source Destination
SFR Symbol Address Either
Only Only
Accumulator AlACC OEOH Y
B Register B OFOH Y
FIFO IN FIN OEEH Y
COMMAND IN CIN OEFH Y
FIFO OUT FOUT OFEH Y
COMMAND OUT COUT OFFH Y
Serial Data Buffer SBUF 099H Y
Port 0 PO 080H Y
Port 1 P1 090H Y
Port 2 P2 OAOH Y
Port 3 P3 OBOH Y
Port 4 P4 OCOH Y
DMA Special Function Registers
DMA Control SFR: DCONO, DCON1
Symbolic Physical
Address Address
DCONO 092H
DCON1 093H
Reset Status: DCONO and DCON1 = OOH
Bit Definition:
DAS IDA Destination Address Space
0 0 External Data Memory without Auto-Increment
0 1 External Data Memory with Auto-Increment
1 0 Special Function Register
1 1 Internal Data Memory
SAS ISA Source Address Space
0 0 External Data Memory without Auto-Increment
0 1 External Data Memory with Auto-Increment
1 0 Special Function Register
1 1 Internal Data Memory
DM TM DMA Transfer Mode
0 0 Alternate-Cycle Transfer Mode
0 1 Burst Transfer Mode
1 0 FIFO or Serial Channel Demand Mode
1 1 External Demand Mode
11-26
inlel" UPI-452
DONE DMA transfer Flag: service request is generated. DMA transfer cycles
are alternated with instruction execution cycles.
o DMA transfer is not completed. DMA transfers are terminated as in FIFO Demand
DMA transfer is complete. M~a .
NOTE:
This flag is set when contents of the Byte Count Output Channel
SFR decrements to zero. It is reset automatically The DMA is configured as in FIFO Demand Mode
when the DMA vectors to its interrupt routine. and transfers are initiated whenever an Output FIFO
GO Enable DMA Transfer: requests service. DMA transfer cycles are alternated
with instruction execution cycles. DMA transfers are
o Disable DMA transfer (in all modes). terminated as in FIFO Demand Mode.
1 Enable DMA transfer. If the DMA is in
the Block mode, start DMA transfer if The FIFO logic resets the interrupt flag after trans-
possible. If it is in the Demand mode, ferring the byte, so the interrupt is never generated.
enable the channel and wait for a de-
mand. Once the DMA is programmed to service the FIFO,
the request for service interrupt for the FIFO is inhib-
NOTE: ited until the DMA is done (BCR = 0).
The GO bit is reset when the BCR decrements to
zero.
2. BURST MODE
In BURST mode tho DMA is initiated by setting the
DMA Transfer Modes GO bit in the DCON SFR. The DMA operation con-
The following four modes of DMA operation are pos- tinues until BCR decrements to zero (zero byte
sible in the UPI-452. count), then an interrupt is generated (if enabled).
No interrupts are recognized during this DMA opera-
tion once it has started.
1. ALTERNATE-CYCLE MODE
General Input Channel
Alternate cycle mode is useful when CPU process- The FIFO Input Channel can be used in burst mode
ing must occur during the DMA transfers. In this by specifying the FIFO IN SFR as the DMA Source
mode, a DMA cycle and an instruction cycle occur Address. DMA transfers bO[Jin when the GO bit in
alternately. The interrupt request is generated (if en- the DMA Control SFR is sot. The number of bytes to
abled) at the end of the process, i.e. when BCR dec- be transferred must be spocified in the Byte Count
rements to zero. The transfer is initiated by setting SFR (BCR) and auto-incromonting of the SAR must
the GO bit in the DCON SFR. be disabled. Once the GO bit is set nothing can in-
~errupt the transfer of data until the BCR is zero. In
Alternate-Cycle FIFO Demand Mode this mode, a Data Stream Command encountered in
the FIFO will be held in tho COMMAND IN SFR with
Alternate cycle demand mode is useful for FIFO the pointers frozen, and invalid data (FFH) will be
transfers of a less urgent nature. As mentioned be- read through the FIFO IN SFR. If the input FIFO
fore, CPU instruction cycles are interleaved with becomes empty during the block transfer, an OFFH
DMA transfer cycles, allowing true parallel process- will be read until BCR decrements to zero.
ing.
This mode differs from FIFO Demand Mode in that Output Channel
CPU instruction cycles must be interleaved with
DMA transfers, even if the FIFO is demanding DMA. The Output FIFO Channel can be used in burst
In FIFO Demand Mode, CPU cycles would never oc- mode by specifying the FIFO OUT or COMMAND
cur if the FIFO demand was present. OUT SFR as the DMA Destination Address. DMA
transfers begin when the GO bit is set. This mode
can be used to send a block of data or a block of
Input Channel Data Stream Commands. If the FIFO becomes full
The DMA is configured as in FIFO Demand Mode during the block transfer, the remaining data will bo
and transfers are initiated whenever an Input FIFO lost.
11-27
inter UPI-452
NOTE: is not full or empty. DMA transfers begin when the
All interrupts including FIFO interrupts are not rec- Request For Service Flag is activated by the FIFO
ognized in Burst Mode. Burst Mode transfers logic and continue as long as the flag is active. The
should be used to service the FIFO only when the Flag remains active until one of the following occurs:
user is certain that no Data Stream Commands are 1) The FIFO becomes full
in the block to be transferred (Input FIFO) and that
the FIFO contains enough space to store the block 2) BCR = 0 (this generates a DMA interrupt and
to be transferred. In all other cases Alternate .Cycle . the DONE. bit)..
sets .
or Demand Mode should be used.
As in Alternate Cycle FIFO Demand Mode, the FIFO
logic resets the interrupt flag after transferring the
3. FIFO AND SERIAL CHANNEL DEMAND byte, so the interrupt is never generated.
MODES
After the GO bit is set, the DMA is activated if one of
NOTES: the following conditions takes place:
1. If the output FIFO is configured as a one byte SAR(0/1) = FIFO IN and HIFRS flag is set
buffer and the user program consists of two-cycle DAR(0/1) = FIFO OUT and HOFRS flag is set
instructions only, then Alternate-Cycle Mode should
be used. The HIFRS and HOFRS signals arc internal flags
2. In non-auto increment mode for internal to exter- which are not accessible by software. These flags
nal, or external to internal transfers, the lower 8 bits are similar to the SSTO and SST4 flags in the Slave
of the external address should not correspond to
Status Register except that they are of the opposite
the FIFO or Serial Port address.
polarity and once set they are not cleared until the
Input FIFO becomes empty (HI FRS) or the Output
FIFO Demand Mode FIFO becomes full (HOFRS).
Although any DMA mode is possible using the FIFO
buffer, only FIFO Demand and Alternate Cycle FIFO Serial Channel Demand Mode
Demand Modes are recommended. FIFO Demand
Mode DMA transfers using the input FIFO Channel Serial Channel Demand Mode is the logical choice
are set-up by setting the GO bit and specifying the when using the Serial Port. The DMAs can be acti-
FIFO IN register as the DMA Source Address Regis- vated by one of the Serial Channel Flags. Receiver
ter. The BCR should be set to the maximum number interrupt (RI) or Transmitter Interrupt (TQ.
of expected transfers. The user must also program
bit 1 of the Slave Control Register (SC1) to deter- SAR(0/1) = SBUFand RI flag is'5et .
mine whether the Slave Status (SSTAT) SFR FIFO DAR(0/1) = SBUF and.TI flag is set
Request For Service Flag will be activated when the
FIFO becomes not empty or full. Once the Request NOTE:
For Service Flag is activated by the FIFO, the DMA TI flag must be set by software to initiate the first
transfer begins, and continues until the request flag transfer.
is deactivated. While the request is active, nothing
can interrupt the DMA (i.e. it behaves like burst When the DMA transfer begins, only one byte is
mode). The DMA Request is held active until one of transferred at a time. The serial port hardware auto-
the following occurs: matically resets the flag after completion of the
transfer, so an interrupt will not be' generated unless
1) The FIFO becomes empty.
DMA serviCing is held off due to the DMA being
2) A Data Stream Command is encountered (this done (BCR = 0) or when the Hold/Hold Acknowl-
generates a FIFO interrupt and DMA operation edge logic is used and the DMA does not own the
resumes after the Data Stream Command is bus. In this case a Serial Port interrupt may be gen-
read). erated if enabled because of the status of the RI or
3) BCR = 0 (this generates a DMA interrupt and TI flags.
sets the DONE bit). .
In FIFO demand mode, Alternate cycle FIFO de-
DMA transfers to the Output FIFO Channel are simi- mand mode or Serial Port demand mode only one of
lar. The FIFO OUT or COMMAND OUT SFR is the the following registers (SBUF, FIN or FOUT) should
DMA Destination Address SFR and a transfer is be used as either the SAR or DAR registers to pre-
started by setting the GO bit. The user programs bit vent undesired transfers. For example if SARO' =
o of the Slave Control SFR (SCO) to determine FIN and DARO =SBUF in demand mode, the DMA
whether a demand occurs when the Output FIFO transfer will start if eitherthe HIFRS or TI flags are
set.
11-28
infef UPI-452
4. EXTERNAL DEMAND MODE ARBITER MODE: In this mode, the UPI-452 is the
bus master. It configures port pin P1.5 as HLD input
The DMA can be initiated by an external device via and pin P1.6 as HLDA output. When a device as-
External interrupt 0 and 1 (INTOIINT1) pins. The serts the HLD signal to use the local bus, the UPI-
INTO pin demands DMAO (Channel 0) and INT1 de- 452 asserts the HLDA signal after current instruction
mands DMA 1 (Channel 1). If the interrupts are con- execution is complete. If the UPI-452 needs an ex-
figured in edge mode, a single byte transfer is ac- ternal access via a DMA channel, it waits until the
complished for every request. Interrupts also result requester releases the bus, HLD goes inactive.
(INTO and INT1) after every byte transfer (if en-
abled). If the interrupts are configured in level mode, DISABLE MODE: When external program memory is
the DMA transfer continues until the request goes accessed by an instruction or by program counter
inactive or BCR = o. In either case, a DMA interrupt overflow beyond the internal ROM address or exter-
is generated (if enabled) whon BCR = o. The GO bit nal data memory is accessed by MOVX instructions,
must be set for the transfer to begin. it is a local memory access and the HLD/HLDA logic
is not initiated. When a DMA channel attempts data
transfer tolfrom the external data memory, the
EXTERNAL MEMORY DMA HLD/HLDA logic is initiated as described below.
DMA transfers from the internal memory space to
When transferring data to or from external memory the internal memory space does not initiate the
via DMA, the HOLD (HLD) and HOLD-ACKNOWL- HLD/HLDA logic.
EDGE (HLDA) signals are used for handshaking.
The HOLD and HOLD-ACKNOWLEDGE are active The balance of the PCON SFR bits are described in
low signals which arbitrate control of the local bus. the "80C51 Register Description: Power Control
The UPI-452 can be used in a system where multi- SFR" section below.
masters are connected to a single parallel Address/
Data bus. The HLD/HLDA signals are used to share
resources (memory, peripherals, etc.) among all the Latency
processors on the local bus. The UPI-452 can be
configured in any of three different External Memory When the GO bit is set, the UPI-452 finishes the
Modes controlled by bits 5 and 6 (REQ & ARB) in current instruction before starting the DMA opera-
the PCON SFR (Table 5). Each mode is described tion. Thus the maximum latency is 3.5 microseconds
below: (at 14 MHz).
REQUESTER MODE: In this mode, the UPI-452 is
not the bus master, but must request the bus from
DMA Interrupt Vectors
another device. The UPI-452 configures port pin Each DMA channel has a unique voctorod interrupt
P1.5 as a HLD output and pin P1.6 as a HLDA input. associated with it. There are two voctorod intorrupts
The UPI-452 issues a HLD signal when it needs ex- associated with the two DMA channols. Tho DMA
ternal access for a DMA channel. It uses the local interrupts are enabled and prioritios sot via tho Inter-
bus after receiving the HLDA signal from the bus rupt Enable and Priority SFR (soo "Intorrupts" sec-
master, and will not release the bus until its DMA tion). The interrupt priority schomo is similar to the
operation is complete. scheme in 80C51.
Table 5. DMA MODE CONTROL - PCON SFR
Symbolic Physical
Address Address
PCON -* ARB REQ -* -* -* -' -* 87H
(MSB) (LSB)
*Defined as per MLS-51 Data Sheet
Reset Status: OOH
Definition:
ARB REO
0 0 HLD/HLDA logic is disabled.
0 1 The UPI-452 is in the Requester Mode.
1 0 The UPI-452 is in the Arbiter Mode.
1 1 Invalid
--
11-29
infef UPI-452
When a DMA operation is complete (BCR decre- If the UPI-4S2 (as a Requester) asserts a HLD signal
ments to zero), the DONE flag in the respective to request a DMA transfer (see "External Memory
DCON (DCONO or DCON1) SFR is set. If the DMA DMA")and its other DMA Channel requests a trans-
interrupt is enabled, the DONE flag is reset automat- fer before the HLDA signal is received, the channel
ically upon vectoring to the iriterrupt routine. having higher priority is activated first. A Burst Mode
transfer on channel 0 can not be interrupted since
DMAO has the highest priority. A Demand Mode
Interrupts When DMA is Active transfer on channel 0 is the only type of activity that
can interrupt a block transfer on DMA 1.
If a Burst Mode DMA transfer is in progress, the in-
terrupts are not serviced until the DMA transfer is If, while executing a DMA transfer, the Arbiter re-
complete. This is also true for level activated Exter- ceives a HLD signal, and then before it can acknowl-
nal Demand DMA transfers. During Alternate Cycle edge, its other DMA Channel requests a transfer, it
DMA transfers, however, the interrupts are serviced then completes the second DMA transfer before
at the end pf the DMA cycle. After that, DMA cycles sending the HLDA signal to release the bus to the
and instruction execution cycles occur alternately. In HLD request.
the case of edge activated External Demand Mode
DMA transfers, the interrupt is serviced at the end of DMA transfers may be held off under the following
DMA transfer'of that single byte. conditions:
1. A write to any of the DMA registers inhibits the
DMAfor one instruction cycle.
DMA Arbitration
Only one,of the two DMA channels is active at a NOTE:
time, except when both are configured in the Alter- An instruction cycle may be executed in 1, 2 or 4
nate Cycle mode. In t~is caso, the DMA cycles and machine cycles dependont on the instruction being
Instruction Execution cycles occur in the following executed. DMA transfers are only executed after
order: the completion of an instruction cycle never be-
tween machine cycles of a single instruction cycle.
1. DMA Cycle O. Similarly instruction cycles are only executed upon
2. Instruction execution. completion of a DMA transfer whether it be a one
3. DMA Cycle 1. machine cycle transfer or two machine cycles (for
ext. to ext. memory transfers).
4. Instruction execution.
2. A single machine cycle DMA register read opera-
DMAO has priority over DMA 1 during simUltaneous tion (Le. MOV A, DCONO) will inhibit the DMA for
activation of the two DMA channels. If one DMA one instruction cycle. However a two cycle DMA
channel is active, the other DMA channel, if activat- register read operation will not inhibit the DMA
ed, waits until the first one is complete. (i.e. MOV P1, .DCONO).
If DMAO is already in the Alternate Cycle mode and If the HOLD/HOLD Acknowledge logiC is enabled in
DMA 1 is activated in Alternate Cycle Mode, it will requestor mode the hold request will go active once
take two instruction cycles before DMA 1 is activated the go bit has been set (for burst mode) and once
(due to the priority of DMAO). Once DMA 1 becomes the demand flag is set (for demand mode) regard-
active, the exec~tion will follow the normal se- less of whether the DMA is held off by one of the
quence. above conditions.
If DMAO is already in the Alternate Cycle mode and The DMA Transfer waveforms are in Figures 8-11.
DMA 1 is activated in Burst Mode, the DMA 1 Burst
transfer will follow the DMAO Alternate Cycle trans-
fer (after the completion of the next instruction).
11-30
inter UPI-452
51 52 53 55 56 51 52 53 s. 55 56
a5e
..JL fL.JLf1.J1..fl.fl..I1-rl.f"Lfl..I1-ruLruL~r-
ALE
r h r """"\.
PORT2
- S( UReE ADDR ~5 A15-A )t DE5 NATION ADD E55 A15 A8
PORTO "7-"0
- DATA IN )-- A7- 0 X DATA OUT
•
V
. " - OMA CYCLE
231428-13
Figure 8. DMA Transfer from External Memory to External Memory
OMA CYCLE -----"----1
51 52 U I ~ I ~ I ~ I ~ 52
(l.OCK
ALE
PORT2-1__~-Jl'-----f_--~_f~~~----~------t_----JI~----_t----
PORTO
RD
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ """" _ _ _ _ _ _ _ _ _ _" _ _ _ _ ___J
'
-
-
-
_
~
Figure 9. DMA Transfer from External Memory to Internal Memory
51 52 53 5. 55 56 S1 S2 53
CLOCK
ALE
PO~2~~~-Jr-____f_--~DE~5~T1N~A~T1~aN~A~D~DR~E~55~A~1~5-~A~8----_t-----1~----t_---
PORTO DATA OUT
i--------DMA CyCLE---------\
231428-15
Figure 10. DMA Transfer from Internal Memory to External Memory
11-31
intJ UPI-4S2
S1 S2 S3 S4 S5 S6 S1 S2 S3
CLOCK
ALE
PSEN
PORT2
PORTO
INSTRUCTION
DMA CYCLE- .
EXECUTION
231428-16
Figure 11. DMA Transfer from Internal Memory to Internal Memory
INTERNAL INTERRUPTS Table 6. Interrupt Priority
Interrupt Source Priority Level
(highest)
Overview External Interrupt 0 o
The UPI·452 provides a total of eight interrupt sourc- Internal Timer/Counter 0
es (Table 6). Their operation is the same as in the DMA Channel 0 Request 2
80C51 , with the addition of three new interrupt External Interrupt 1 3
sources for the UPI-452 FIFO and DMA features. DMA Channel 1 Request 4
These added interrupts have their enable and priori- Internal Timer/Counter 1 5
ty bits in the Interrupt Enable and Priority (lEP) SFR. FIFO - Slave Bus Interface 6
The IEP SFR is in addition to the 80C51 Interrupt Serial Channel 7
Enable (IE) and Interrupt Priority (IP) SFRs. The add- (lowest)
ed interrupt sources are also globally enabled or dis-
abled by the EA bit in the Interrupt Enable SFR. Ta- Table 7. Interrupt Vector Addresses
ble 6 lists the eight interrupt sources in order of pri- Interrupt Source Starting Address
ority. Table 7 lists the eight interrupt sources and External Interrupt 0 3 (003H)
their respective address vector location in program Internal Timer/Counter 0 11 (OOBH)
memory. (DMA interrupts are discussed in the "Gen- External Interrupt 1 19 (013H)
eral Purpose DMA Channels" section. Additional in-
Internal Timer/Counter 1 27 (01 BH)
terrupt information for Timer/Counter, Serial Chan-
Serial Channel 35 (023H)
nel, External Interrupt may be found in the Microcon-
troller Handbook for the 80C51.) FIFO - Slave Bus Interface 43 (02BH)
DMA Channel 0 Request 51 (033H)
DMA Channel 1 Request 59 (03BH)
FIFO Module Interrupts to Internal CPU
The FIFO module generates interrupts to the inter- FIFO requests service when it becomes empty or
nal CPU whenever the FIFO requests service or not full as determined by bit 0 of the Slave Control
when a Data Stream Command is in the COMMAND SFR (OFRS). Request for Service interrupts are
IN SFR. The Input FIFO will request service whenev- generated only if enabled by the internal CPU via the
er it becomes full or not empty depending on bit 1 of Interrupt Enable SFR, and the Slave Control Regis-
the Slave Control SFR (IFRS). Similarly, the Output ter.
11-32
UPI-4S2
A Data Stream Command Interrupt is generated Immediate Command OUT bit (SSTAT SST6) to
whenever there is a Data Stream Command in the be set and the corresponding Host Status bit
COMMAND IN SFR. The interrupt is generated to (HSTAT HST6) to be cleared indicating the SFR is
ensure that the internal interrupt is recognized be- empty. When the internal CPU writes to the Imme-
fore another instruction is executed. diate Command OUT SFR, the Host Status bit is
set and Slave Status bit is cleared to indicate the
SFR is full. (See Figure 7b, Immediate Command
Immediate Command Interrupts OUT Flowchart.)
a. An Immediate Command IN interrupt is generat-
ed, if enabled, to the internal CPU when the Host NOTE:
has written to the Immediate Command IN (IMIN) Immediate Command IN and OUT interrupts are ac-
SFR. The write operation clears the Slave Status tually specific FIFO-Slave Interface interrupts to the
SFR bit (SSTAT SST2) and sets the Host Status internal CPU.
SFR bit (HSTAT HST2) to indicate that a byte is
present in the Immediate Command IN SFR. One instruction from the main program is executed
When the internal CPU reads the Immediato Com- between two consecutive interrupt service routines
mand IN (IMIN) SFR the Siavo Status SFFl status as in the 80C51. However, if the second interrupt
bit is set, and the Host Status SFR status bit is service routine is due to a Data Stream Command
cleared indicating the IMIN SFR is empty. Clear- Interrupt, the main program instruction is not execut-
ing the Host Status SFR bit will cause a Request ed (to prevent misreading of invalid data).
For Service (INTRO) interrupt, if onabled, to signal
the Host that the IMIN SFR is ompty. (Soo Figure
7a, Immediate Command INFlowcllart.) Interrupt Enabling and Priority
b. An Immediate Command OUT interrupt is goner- Each of the three interrupt special function registers
ated, if enabled, to the internal CPU wilen the (IE, IP and IEP) is listed below with its corresponding
Host has read the Immediate Command OUT bit definitions.
SFR. The Host read causes the Slave Status
Interrupt Enable SFR(IE)
Symbolic Physical
Address Address
IE EA ES ET1 EX1 ETO EXO OA8H
(MSS) (LSD)
Symbol Position Function
EA IE.7 Enables all interrupts. If EA = 0, no intorrupt will be
acknowledged. If EA = 1, each interrupt source is
individually enabled or disabled by setting or clearing its
enable bit.
- IE.6 (reserved)
- IE.5 (reserved)
ES lEA Serial Channel interrupt enable
ET1 IE.3 Internal Timer/Counter 1 Overflow Interrupt
EX1 1E.2 External Interrupt Request 1.
ETO 1E.1 Internal Timer/Counter 0 Overflow Interrupt
EXO lE.O External Interrupt Request O.
11-33
UPI-4S2
Interrupt Priority SFR (IP)
A priority level of 0 or 1 may be assigned to each interrupt source, with 1 being higher priority level, through the
IP and the IEP (Interrupt Enable and Priority) SFR. A priority level of 1 interrupt can interrupt a priority level 0
service routine to allow nesting of interrupts.
Symbolic Physical
Address Address
IP PS PT1 PX1 PTO PXO OB8H
(MSB) (LSB)
Priority Within
Symbol Position Function
A Level
(lowest)
- IP.7 (reserved) -
- IP.6 (reserved) -
- IP.5 (reserved) -
PS IPA Local Serial Channel 0.7
PT1 IP.3 Internal Timer/Counter 1 0.5
PX1 IP.2 External Interrupt Request 1 0.3
PTO IP.1 Internal Timer/Counter 0 0.1
PXO IP.O Externallntorrupt Request 0 0.0
(highest)
Interrupt Enable and Priority SFR (IEP)
The Interrupt Enable and Priority Register establishes tho enabling and priority of those resources not covered
in the Interrupt Enable and Interrupt Priority SFRs.
Symbolic Physical
Address Address
IEP I PFIFO I EDMAO I EDMA1 I PDMAO I PDMA1 I EFIFO I OF8H
(MSB) (LSB)
Priority
Symbol Position Function Within a
Level
- IEP.7 (reserved)
- IEP.6 (reserved)
PFIFO IEP.5 FIFO Slave Bus Interface Interrupt Priority 0.6
EDMAO IEPA DMA Channel 0 Interrupt Enable
EDMA1 IEP.3 DMA Channel 1 Interrupt Enable
PDMAO IEP.2 DMA Channel 0 Priority 0.2
PDMA1 IEP.1 DMA Channel 1 Priority 0.4
EFIFO IEP.O FIFO Slave Bus Interface Interrupt Enable
• 11-34
intJ UPI-452
FIFO-EXTERNAL HOST INTERFACE Special Function Registers and their default power
FIFO DMA FREEZE MODE on reset values;
SFR Name Label Value
Overview Channel Boundary Pointer CBP 40H /64D
During FIFO DMA Freoze Mode the internal CPU Output Channel Read Pointers ORPR 40H /64D
can reconfigure the FIFO interface. FIFO DMA Output Channel Write Pointers OWPR 40H /64D
Freeze Mode is provided to prevent the Host from Input Channel Read Pointers IRPR OOH / OOD
accessing the FIFO during a reconfiguration se- Input Channel Write Pointers IWPR OOH /OOD
quence. The internal CPU invokes FIFO DMA Input Threshold ITHR BOH / 12BD
Freeze Mode by clearinu bit 3 of the Slave Control Output Threshold OTHR 01H / 10
SFR (SC3). INTRQ becornes active whenever FIFO
DMA Freeze Mode is invoked to indicate the freeze
status. The interrupt can only be deactivated by the The Input and Output FIFO channels can be recon-
Host reading the Host Status SFR. figured by programming any of these SFRs while the
UPI-452 is in the Freeze Mode. The Host is notified
During FIFO DMA Freezo Mode only two operations when the Freeze Mode is active by a "1" in HST1 of
are possible by the Host to the UPI-452 slave, the the Host Status Register (HSTAT). The Host should
balance are disabled, as sllOwn in Table B. The in- interrogate HST1 to determine the status of the
ternal DMA is disabled during FIFO DMA Freeze FIFO interface following reset before attempting to
Mode, and the internal CPU has write access to all read from or write to the UPI-452 FIFO buffer.
of the FIFO control SFRs (Table 9).
NOTE:
During the initialization sequence of the UPI-452
Initialization FIFO SFRs, the OTHR should be changed from the
default setting of 1 to a value between 2 and
At power on reset the FIFO Host interface is auto- I (BOH-CBP)-11. Please refer to the section on Input
matically frozen. The Slave Control Enable FIFO and Output FIFO threshold SFRs for furthor infor-
DMA Freeze Mode bit defaults to FIFO DMA Freeze mation.
Mode (SLCON FRZ=O). Below is a list of the FIFO
Table 8. Slave Bus Interface Status During FIFO DMA Freeze Mode
' - ' .-
Interface Pins; - --- Operation In Status In
CS A2 A1 AD READ WRITE
DACK Normal Mode FIFO DMA Freeze Mode
..
1 0 0 1 0 0 1 Read Host Status SFR Oporational
1 0 0 1 1 0 1 Read Host Control SFR Oporational
1 0 0 1 1 1 0 Writo Host Control SFR lJi!;abled
1 0 0 0 0 0 1 Data or DMA Data from Disabled
Output Channel
1 0 0 0 0 1 0 Data or DMA Data to Disabled
Input Channel
1 0 0 0 1 0 1 Data Stream Command from Disabled
Output Channel
1 0 0 0 1 1 0 Data Stream Command to Disabled
Input Channel
1 0 1 0 0 0 1 Read Immediate Command Disabled
Out from Output Channel
1 0 1 0 0 1 0 Write Immediate Command Disabled
In to Input Channel
0 X X X X 0 1 DMA Data from Output Disabled
Channel
.--
0 X X X X 1 0 DMAData to Input Channel Disabled
.-
11-35
inter UPI-452
The UPI-4S2, can also be programmed to interrupt FIFO DMA Freeze Mode without first stopping the
the Host following power on reset in order to indi- external Host from accessing the UPI-4S2 will not
cate to the Host that FIFO DMA Freeze Mode is in guarantee a clean break with the external Host.
progress. This is done by enabling the INTRO inter-
rupt output pin via the MODE SFR (MD4) before the The proper way to invoke FIFO DMA Freeze Mode is
Slave Control SFR Enable FIFO DMA Freeze Mode by issuing an Immediate Command to the external
bit is set to Normal Mode. At power on reset the host indicating that FIFO DMA Freeze Mode will be
Mode SFR is forced to zero. This disables all inter- invoked. Upon receiving the Immediate Command,
rupt and DMA output pins (INTRO, DRQIN/ the external Host should complete servicing all
INTRQIN and DROOUT /INTRQOUT). Because the pending interrupts and,DMA requests, then send an
Host Status SFR FIFO DMA Freeze Mode In Prog- Immediate Command back to the UPI-4S2 acknowl-
ress bit is set, a Request For Service, INTRO, inter- edging the FIFO DMA Freeze Mode request. After
rupt is pending until the Host Status SFR is read. issuing the first Immediate Command, the internal
This is because the FIFO DMA Freeze Mode inter- CPU should not perform any action on the FIFO until
rupt is always enabled. If the Slave Control FIFO FIFO DMA Freeze Mode is invoked.
DMA Freeze Mode bit (SLCON FRZ) is set to Nor-
mal Mode before the MODE SFR INTRO bit is en- If FIFO DMA Freeze Mode is invoked without stop-
abled, the INTRO output will not go active when the ping the Host during Host transfers, only the last two
MODE SFR INTRQ bit is enabled if the Host Status bytes of data written into or read from the FIFO will
SFR has been read. be valid. The timing diagram for disabling the FIFO
module to the external Host interface is illustrated in
The default values for the FIFO and Slave Interface Figure 12. Due to this synchronization sequence, the
represents minimum UPI-4S2 internal initialization. UPI-4S2 might not go into FIFO DMA Freeze Mode
No specific Special Function Register initialization is immediately after SC3 is cleared. A special bit in the
required to begin operation of the FIFO Slave Inter- Slave Status Register (SSTS) is provided to indicate
face. The last initialization instruction must always the status of the FIFO DMA Freeze Mode. The FIFO
set the UPI-4S2 to Normal Mode. This causes the DMA Freeze Mode operations described in this sec-
UPI-4S2 to exit FIFO DMA Freeze Mode and en- tion are only valid after SSTS is cleared.
ables Host read/write access of the FIFO.
As FIFO DMA Freeze Mode is invoked, the DROIN
Following reset, either hardware (via the RST pin) or or DROOUT will be deactivated (stopping the trans-
software (via HCON SFR bit HC3) the UPI-4S2 re- ferring of data), bit 1 of the Host Status SFR will be
quires 2 internal machine cycles (24 TCLCL) to up- set (HST1 = 1), and SSTS will be cleared (SSTS = 0)
date all internal registers. to indicate to the external Host and internal CPU
that the slave interface has been frozen. After the
freeze becomes effective, any attempt by the exter-
Invoking FIFO DMA Freeze Mode nal Host to access the FIFO will cause the overrun
During Normal Operation and underrun bits to be activated (bits HST7 (for
reads) or HST3 (for writes)). These two bits, HST3
When the UPI-4S2 is in normal operation, FIFO DMA and HST7, will be set (deactivated) after the Host
Freeze Mode should not be arbitrarily invoked by Status SFR has been read. If INTRQ is used to re-
clearing SC3 (SC3 = 0) because the external Host quest service, the FIFO interface is frozen upon
runs asynchronously to the internal CPU. Invoking completion of any Host read or write operation in
progress.
DRQIN/
DRQOUT
.-I
I
: FIFO INTERNALLY STOPPED FROM
ACCEPTING OR OUTPUTIING DATA
SC3
HST1 __________________________ ~
231428-17
Figure 12. Disabling FIFO to Host Slave Interface Timing Diagram
11-36
UPI-452
External Host writing to the Immediate Command In HCON, the Input Channel error condition flag
SFR and the Host Control SFR is also inhibited (HST3) will be cleared.
when the slave bus interface is frozen. Writing to
these two registers after FIFO DMA Freeze Mode is
invoked will also cause HST3 (overrun) to be activat- Input FIFO Pointer Registers
ed (HST3 = 0). Similarly, reading the Immediate (IRPR & IWPR)
Command Out Register by the external Host is dis-
abled during FIFO DMA Freeze Mode, and any at- Once the FIFO module is in FIFO DMA Freeze
tempt to do so will cause the clearing (deactivating, Mode, error flags due to overrun and underrun of the
"0") of HST7 bit (underrun). Input FIFO pointers will be disabled. Any attempt to
create an overrun or underrun condition by changing
. After the slave bus interface is frozen, tho internal the Input FIFO pointers. would result in an inconsist-
CPU can perform the following operations on the ency in performance between the status flag and the
FIFO Special Function Registers (those oporations threshold counter.
are allowed only during FIFO DMA Freeze Mode).
To enhance the speed of the UPI-452, read opera-
For FIFO 1. Changing tl10 Channel tions on the Input FIFO will look ahead by two bytes.
Reconfiguration Boundary Pointor SFR. Hence, every time the IRPR is changed during FIFO
2. Changing tho Input and DMA Freeze Mode, two NOPs need to be executed
Output Throshold SFR. so that the two byte pipeline can be updated with the
new data bytes pointed to by the new IRPR. The
To. Enhance the 3. Writing to the read and write Threshold Counter SFR also needs to change by the
same number of bytes as the IRPR (increase
Testability pointers of the Input and
Threshold Counter if IRPR goes forward or decrease
Output FIFO's. if IRPR goes backward). This will ensure that future
4. Writing to and reading the interrupts will still be generated only after a thresh-
Host Control SFRs. old number of bytes are available. (See "Input and
5. Controlling some bits of Host Output FIFO Threshold SFR" section below.)
and Slave Status SFRS.
6. Reading the Immediate In· FIFO DMA Freeze Mode, the internal CPU can
Command Out SFR and also change the content of IWPR, and each change
Writing to the Immediate of IWPR also requires an update of the Threshold
Counter SFR.
Comand In SFR.
Normally, the internal CPU cannot writo into tho In-
put FIFO. It can, however, during FIFO OMA Freoze
Description of each of these special Mode by first reconfiguring tl10 FIFO as an Output
functions are as follows: FIFO (Refer to "Input and Output FIFO Tl1roshold
SFR" section below). CI1LH1!lin!1 tl10 IRPR to be
equal to IWPR generates LUI empty condition while
FIFO Module SFRs During changing IWPR to be equal to IRPR generates a full
FIFO DMA Freeze Mode condition. The order in which the pointers are written
determines whether a full or empty condition is gen-
Table 9 summarizes the .characteristics of all the
erated.
FIFO Special Function Registers during normal and
FIFO DMA Freeze Modes. The registers that require
special treatment in FIFO DMA Freeze Mode are:
HCON, IWPR, IRPR, OWPR, ORPR, HSTAT, Output FIFO Pointer SFR
SSTAT, MIN & MOUT SFRs. They can be described (ORPR and OWPR)
in detail as follows:
In FIFO DMA Freeze Mode the contents of OWPR
can be changed by the internal CPU, but each
change of OWPR or ORPR requires the Threshold
Host Control SFR (HCON) Counter SFR to be updated as described in the next
During normal operation, this register is written to or section. A NOP must be executed whenever a new
read by the external Host. However, in FIFO DMA value is written into ORPR, as just described for
Freeze Mode (i.e. SST5=0) the UPI-452 internal changes to IRPR. As before, changing ORPR to bo
CPU has write access to the Host Control SFR and equal to OWPR will generate an empty condition,
write operations to this SFR by the external Host will Output FIFO overrun or underrun condition cannot
not be accepted. If the. Host attempts to write to be generated though. The FIFO pointers should not
be set to a value outside of its range.
11-37
intJ UPI-452
Table 9. FIFO SFR's Characteristics During FIFO DMA Freeze Mode
Normal FIFO DMA Freeze Mode
Label Name Operation Operation
(SST5 = 1) (SSTS = 0)
HCON Host Control Not Accessible Read & Write
HSTAT Host Status Read Only Read & Write 4
SLCON Slave Control Read & Write Read & Write
SSTAT Slave Status Read Only Read & Write 4
IEP Interrupt Enable & Priority Read & Write Read & Write
MODE Mode Register. Read & Write Read & Write
IWPR Input FIFO Write Pointer Read Only Read & Write 5
IRPR Input FIFO Read Pointer Read Only Read & Write 1, 5
OWPR Output FIFO Write Pointer Read Only Read & Write 6
ORPR Output FIFO Read Pointer Read Only Read & Write 2, 6
-.
CBP Channel Boundary Pointer Read Only Read & Write 3
IMIN Immediate Command In Read Only Read & Write
..
-
IMOUT Immediate Command Out Read & Write Read & Write
FIN FIFO IN Read Only Read Only
CIN COMMAND IN Read Only Read Only
FOUT FIFO OUT Read & Write Read & Write
COUT COMMAND OUT Read & Write Read & Write
ITHR Input FIFO Threshold Read Only Read & Write
OTHR . Output FIFO Threshold Read Only Read & Write
...
NOTES:
1. Writing of IRPR will automatically cause the FIFO IN SFR to load the contents of the Input FIFO from that location.
2. Writing to ORPR will automatically cause the IOBL SFR to load the contents of the Output FIFO at that ORPR address.
3. Writing to the CBP SFR will cause automatic reset of the four pointers of the Input and Output FIFO channels.
4. The internal CPU cannot directly change the status of these registers. However, by changing the status of the FIFO
channels, the internal CPU can indirectly change the contents of the status registers.
5. Changing the Input FIFO Read/Write Pointers also requires that a consistent update of the Input FIFO Threshold Counter
SFR.
6. Changing the Output FIFO Read/Write Pointers also requires that a consistent update of the Output FIFO Threshold
Counter SFR.
11-38
inter UPJ-4S2
Input and Output FIFO Threshold SFR . Correspondingly, the OTHR should be programmed
.(ITHR & OTHR) in the range from 2 to ! {80H-CBP)-11. An OTHR
value of 1 could result in a failure to set the Output
The Input and Output FIFO Threshold SFRs are also FIFO service request after subsequent writes by the
programmable by the internal CPU during FIFO DMA UPI-452 have filled the Output FIFO.
Freeze Mode. For proper operation of the Threshold
feature, the Threshold SFR should be changed only NOTE:
when the Input and Output FIFO channels are emp- When programming the ITHR SFR, the eighth bit
ty, since they reflect the current number of bytes should be set to 1 (OR'd with 80H). This causes
available to read/write before an interrupt is gener- HSTAT SFR HSTO = 0, Input FIFO Request For
ated. Service. If ITHR bit 7 = 0 then HSTAT HSTO = 1,
Input FIFO Does Not Request Service, and no in-
Table 10 illustrates the Threshold SFRs range of terrupt will be generated.
values and the number of bytes to be transferred
when the Request For Service Flag is activated:
Host Status SFR (HSTAT)
Table 10. Threshold SFRs Range of Values and
Number of Bytes to be Transferred When in FIFO DMA Freeze Mode, some bits in the
Host Status SFR are forced high and will not reflect
ITHR No. of Bytes OTHR No_of Bytes the new status until the system returns to normal
(lower Avaliableto (lower Available to operation. The definition of the register in FIFO DMA
seven bits) be Written seven bits) be Read Freeze Mode is as follows:
0 CBP 2 3
NOTE:
1 CBP-1 3 4 The internal CPU reads this shadow latch value
2 CBP-2 • • when reading the Host Status SFR. The shadow
• • • • latch will keep the information for these bits so nor-
• • • • mal operation can be resumed with the right status.
• • {80H-CBP)-3 (80H-CBP)-2 The following bits are set (= 1) when FIFO DMA
CBP-3 3 (80H-CBP)-2 (80H-CBP)-1 Freeze Mode is invoked;
{80H-CBP)-1 (80H-CBP) HST7 Output FIFO Error Condition Flag
1 = No error.
The eighth bit of the Input and Output FIFO Thresh-
old SFR indicates the status of the service requests o = An invalid read has boen dono on tho
regardless of the freeze condition. If the eighth bit is output FIFO or tho Irnmodialo Command
a "1 ", the FIFO is requesting service from the exter- Out Register by Iho host CPU.
nal Host. In other words, when the Threshold SFR
value goes below zero (2's complement), a service NOTE:
request is generated'. 'The 8th bit of the ITHR SFR The normal underrun orror condition status is dis-
must be set during initialization if the Host interrupt abled. If an Immediato Cornrnund Oul (IMOUT)
request is desired immediately upon leaving Freeze SFR read is attempted during FIFO DMA Free,ze
Mode. Normally the ITHR SFR is decremented after Mode, .the contents of tho IMOUT SFR is output on
each external Host write to the Input FIFO and incre- the Data Buffer and tho error status is cleared
mented after each internal CPU read of the Input (= 0).
FIFO. The OTHR SFR is decremented by internal HST6 Immediate Command Out SFR Status
CPU writes and incremented by external Host reads. During normal operation, this bit is cleared
Thus if the pointers are moved when the FIFO's are (= 0) when the IMOUT SFR is written by the
not empty, these relationships can be used to calcu- UPI-452 internal CPU and set (= 1) when the
late the offset for the Threshold SFRs. It is best to IMOUT SFR is read by the external Host.
change the Threshold SFRs only when the FIFO's Once the host-slave interface is frozen (Le.
are empty to avoid this complication. The threshold SST5 = 0), this bit will be read as a 1 by the
registers should also be updated after the pointers host CPU. A shadow latch will keep the infor-
have been manipulated. mation for this bit so normal operation can be
resumed with the correct status.
NOTE:
The ITHR should only be programmed in the range Shadow latch:
from 0 to (CBP-3). An ITHR value of (CBP-2) could 1 = Internal CPU reads the IMOUT SFR
result in a failure to set the Input FIFO service re- o= Internal CPU writes to the IMOUT SFR
quest signal after the Input FIFO has been emptied.
11-39
UPI-4S2
HST5 Data Stream Command at Output FIFO Slave Status SFR (SSTAT)
This bit is forced to a "1" during FIFO DMA
Freeze Mode to prevent the external host The Slave Status SFR is a read-only SFR. However,
CPU from trying to read the DSC. Once nor- once the slave interface is frozen, most of the bits of
mal operation is resumed, HST5 will reflect this SFR can be changed by the internal CPU by
the Data/Command status of the current byte reconfiguring the FIFO and accessing the FIFO Spe-
in the Output FIFO. cial Function Registers.
Shadow Latch (read by the internal CPU): SST7 Output FIFO Overrun Error Flag
1 = No Data Stream Command (DSC) Inoperative in FIFO DMA Freeze Mode.
0= Data Stream Command at Output FIFO SST6 Immediate Command Out SFR Status
HST4 Output FIFO Service Request Status In FIFO DMA Freeze Mode, this bit will be
cleared when the internal CPU reads the Im-
When FIFO DMA Freeze Mode is invoked, mediate Command Out SFR and set when
this bit no longer reflects the Output FIFO Re- the internal CPU writes to the Immediate
quest Service Status. This bit wll be forced to Command Out Register.
a "1".
SST5 FIFO-External Interface FIFO DMA Freeze
HST3 Input FIFO Error Condition Flag Mode Status
1 = No error. This bit indicates to the internal CPU that
o = One of the following operations has FIFO DMA Freeze Mode is in progress and
been attempted by the external host and that it has write access to the FIFO Control,
is invalid: Host control and Immediate Command SFRs.
1) Write into the Input FIFO SST4 Output FIFO Request Service Status
2) Write into the Host Control SFR During normal operation, this bit indicates to
3) Write into the Immediate Command In the internal CPU that the Output FIFO is
SFR ready for more data. The status of this bit re-
flects the position of the Output FIFO read
NOTE: and write pointers. Hence, in, FIFO, DMA
The normal Input FIFO overrun condition is dis- Freeze Mode, this flag can be changed by the
abled. ' internal CPU indirectly as the read and write
pointers change.
HST2 Immediate Command In SFR Status
SST3 Input FIFO Underrun Flag'
This bit is normally cleared when the internal
CPU reads the IMIN SFR and set when the Inoperative during FIFO DMA Freeze Mode.
external host CPU writes into the IMIN SFR. During normal operation, a read operation
When the host-slave interface is frozen, read- clears (= 0) this bit when there are no data
ing and writing of the IMIN by the internal bytes in the Input FIFO and deactivated (= 1)
CPU will change the shadow latch of this bit. when the Slave Status SFR is read. In FIFO
This bit will be read as a "1" by the external DMA Freeze Mode, this bit will not be cleared
Host. by an Input FIFO read underrun error condi-
Shadow latch. tion, nor will it be reset by the reading of the
Slave Status SFR.
1 = Internal CPU writes into IMIN SFR
SST2 Immediate,Command In SFR Status
o = Internal CPU reads the IMINSFR
This bit is normally activated (= 0) when the
HST1 FIFO DMA Freeze Mode Status
external host CPU writes into the Immediate
1 = FIFO DMA Freeze Mode. Command In SFR and deactivated (= 1)
i
o = Normal Operation (non-FIFO DMA when it is read by the internal CPU. In FIFO
Freeze Mode). DMA Freeze Mode, this bit will not be activat-
ed (= 0) by the external Host's writing of the
NOTE: Immediate Command IN SFR since this func-
This bit is used to indicate to the external Host that tion is disabled. However, this bit will be
the host-slave interface has been frozen and hence cleared (= 0) if the internal CPU writes to the
the external Host functions are now reduced as Immediate Command In SFR and it will be set
shown in Table 8. = 1) if it reads from the register.
HSTO Input FIFO Request Service Satus
When' slave interface is froze'n this bit no
longer reflects the Input FIFO Request Serv-
ice Status. This bit will be forced to a "1".
11-40
intJ UPI-4S2
SST1 Data Stream Command at Input FIFO Flag ORPR SFR to zero. This generates a FIFO empty
In FIFO DMA Freeze Mode, this bit operates signal and allows internal CPU write operations to all
normally. It indicates whether the next byte of 128 bytes of the FIFO. The Threshold registers also
data from the Input FIFO is a DSC or data need to be adjusted when the pointers are changed.
byte. If it is a DSC byte, reading from' the (See "Input and·Output FIFO Threshold SFR" sec-
FIFO IN SFR will result in reading invalid data tion below.)
(FFH) and vice versa. In FIFO DMA Freeze
Mode, this bit still reflects the type of data
byte available from the Input FIFO. MEMORY ORGANIZATION
SSTO Input FIFO Service Request Flag The UPI-452 has separate address spaces for Pro-
During normal operation, this bit is activated gram Memory and Data Memory like the 80C51. :rhe
(= 0) when the Input FIFO contains bytos that Program Memory can be up to 64K bytes. The lower
can be read by the internal CPU and doacti- 8K of Program Memory may reside on-chip. The
vated (=1) when the Input FIFO doos not Data Memory consists of 256 bytes of on-chip RAM,
need any service from the intornal CPU. In up to 64K bytes of off-chip RAM and a number of
FIFO DMA Freeze Mode, the status of this bit "SFRs" (Special Function Registers) which appear
should not change unless tho pointors of the as yet another set of unique memory addresses.
Input FIFO are changed. In this modo, tho in- Table 11a.lnternal Memory Addressing
ternal CPU can indirectly change this bit by
changing the read and write pointers of the Memory Space . Addressing Method
Input FIFO but cannot change it directly. Lower 128 Bytes of Direct or Indirect
Internal RAM
Immediate Command InlOut SFR Upper 128 Bytes Indirect Only
(IMINIIMOUT) of Internal RAM
If FIFO DMA Freeze Mode is in progress, writing to UPI-452 SFR's Direct Only
.-
the Immediate Command In SFR by the external
host will be disabled, and any such attempt will The 80C51 Special Function Registers aro listed in
cause HST3 to be cleared (= OJ. Similarly, the Imme- Table 11 a, and the additional UPI·452 SFRs are list-
diate Command Out SFR read operation (by the ed in Table 11 b. A brief description of tho 80C51
. host) will be disabled internally and read attempts core SFRs is also provided below.
will cause HST7 to be cleared(=O}.
Accessing External Memory
Internal CPU Read and Write of the
FIFO During FIFO DMA Freeze Mode As in the 80C51 , accesses to oxtornal II1UlnOry are
of two types: Accesses to extornal Pro!Jrnm Memory
In normal operation, the Input FIFO can only be read and accesses to external Data Momory.
by the internal CPU and similarly, the Output FIFO
can only be written by the internal CPU. During FIFO External Program Memory is accessed under two
DMA Freeze Mode, the internal CPU can read the conditions:
entire contents of the Input FIFO by programming 1) Whenever signal EA = 0; or
the CBP SFR to 7FH, setting the IRPR SFR to zero,
and then the IWPR SFR to zero .. Programming the 2) Whenever the' program counter (PC) contains a
pointer registers in this order generates a FIFO full number that is larger than 1FFFH.
signal to the FIFO logiC and enables Internal CPU
read operations. If the IWPR and IRPR are already This requires that the ROMless versions have' EA
zero, the write pointer should be changed to a non- wired low to enable the lower 8K 'program bytes to
zero value to clear the empty status then the point- be fetched from externaL memory.
ers can be set to zero. Writing to the .IRDR SFR
automatically ,updates the look ahead registers. External Data Memory is accessed using either the
MOVX @DPTR (16 bit address) or the MOVX @Ri (8
In a similar manner, the internal CPU can write to all bit address) instructions, or during external data
128 bytes of the FIFO by setting the CBP SF-R to memory transfers.
zero, setting OWPR SFR to zero, and then setting
11-41
inter UPI-4S2
Table 11b. 80C51 Special Function Registers Table 11c. UPI-452 Additional Special
Symbol Name Address Contents Function Registers (Continued)
'ACC Accumulator OEOH OOH Symbol Name Address Contents
'S S Register OFOH OOH DARLO Low Bytel OC2H I
"PSW Program Status ODOH OOH DARHO Hi Bytel OC3H I
Word
Channel 0
SP Stack Pointer 81H 07H
DPTR Data Pointer 82H OOOOH DARL1 Low Bytel OD2H I
(consisting of DPH DARH1 Hi Bytel OD3H I
and DPL) Channel 1
"PO Port 0 80H OFFH
DCONO DMAO Control 92H OOH
"P1 Port 1 90H OFFH
"P2 Port 2 OAOH OFFH DCON1 DMA 1 Control 93H OOH
'P3 Port 3 OBOH OFFH FIN FIFO IN OEEH I
*IP Interrupt Priority OB8H OEOH
FOUT FIFO OUT OFEH I
Control
"IE Interrupt Enable OA8H 60H HCON Host Control OE7H OOH
Control HSTAT Host Status OE6H OFBH
TMOD Timer ICounter 89H OOH
'IEP Interrupt Enable OFBH OCOH
Mode Control
and Priority
"TCON Timer/Counter 88H OOH
Control 1M IN Immediate Command OFCH I
THO Timer/Counter 8CH OOH In
o (high byte) IMOUT Immediate Command OFDH I
TLO Timer ICounter 8AH OOH Out
o (low byte) IRPR Input Read OEBH OOH
TH1 Timer/Counter 8DH OOH
Pointer
1 (high byte)
TL1 Timer/Counter BSH OOH ITHR Input FIFO OF6H BOH
1 (low byte) Threshold
"SCON Serial Control 98H OOH IWPR Input Write OEAH OOH
SBUF Serial Data Buff 99H I Pointer
PCON Power Control 87H IOH
MODE Mode Register OF9H 8FH
I = Indeterminate
The SFRs marked with an asterisk (*) are both bit· and ORPR Output Read OFAH 40H
byte· addressable. The functions of the SFRs are as fol- Pointer
lows: OTHR Output FIFO OF7H 01H
Table 11c. UPI-452 Additional Threshold
Special Function Registers OWPR Output Write OFBH 40H
Symbol Name Address Contents Threshold
BCRLO DMA Byte OE2H I "P4 Port 4 OCOH OFFH
Count Low Bytel DMA Source Address
BCRHO High Bytel OE3H I SARLO Low Bytel OA2H I
Channel 0 SARHO Hi Bytel OA3H I
BCRL1 Low Bytel OF2H I Channel 0
BCRH1 Hi Bytel OF3H I SARL1 Low Sytel OB2H I
Channel 1
SARH1 Hi Bytel OB3H I
CSP Channel Boundary OECH 40H
Pointer Channel 1
CIN COMMAND IN OEFH I 'SLCON Slave Control OE8H 04H
COUT COMMAND OUT OFFH I SSTAT Slave Status OE9H 08FH
DMA Destination I = Indeterminate
Address The SFRs marked with an asterisk (*) are both bit- and
byte- addressable. The functions of the SFRs are as fol-
lows:
11-42
UPI-4S2
Miscellaneous Special Function DATA POINTER
Register Description
The Data Pointer. (DPTR) consists of a high byte
80C51 SFRs (DPH) and a low byte (DPL). Its intended function is
to hold a 16-bit address. It may be manipulated as a
16-bit register or as two independent 8-bit registers.
ACCUMULATOR
ACC is the Accumuator SFR. The mnemonics for PORTS 0 TO 4
accumulator-specific instructions, however, refer to
the accumulator simply as A. PO, P1, P2, P3 and P4 are the SFR latches of Ports
0, 1, 2, 3 and 4, respectively.
B REGISTER SERIAL DATA BUFFER
The B SFR is used during multiply and divide opera-
The Serial Data Buffer is actually two separate regis-
tions. For other instructions it can be treated as an-
ters, a transmit buffer and a receive buffer register.
other scratch pad regster.
When data is moved to SBUF, it goes to the transmit
buffer where it is held for serial transmission. (Mov-
ing a byte to SBUF is what initiates the
PROGRAM STATUS WORD transmission.) When data is moved from SBUF, it
The PSW SFR contains program status information comes from the roceive buffer.
as detailed in Table 12.
TIMER/COUNTER SFR
STACK POINTER Registor pairs (THO, TLO), and (TH1, TL 1) are the
16-bit counting registers for Timer/Counters 0 and 2.
The Stack Pointer register is 8 bits wide. It is incre·
mented before data is stored during PUSH and
CALL executions. While the stack may reside any· POWER CONTROL SFR (PCON)
where in on-chip RAM, the Stack Pointer is initialized
to 07H after a reset. This causes the stack to begin The peON Register (Table 13) controls 1110 powor
at location 08H. down and idle modes in the UPI-452, as woll as pro-
viding the ability to double the Serial Channel baud
rate. There are also two general purpose flag bits
available to the user. Bits 5 and 6 are used to set the
HOLD/HOLD Acknowledge mode (see "General
Purpose DMA Channels" section), and bit 4 is not
used.
11-43
inter UPI-4S2
Table 12. Program Status Word
Symbolic Physical
Address Address
PSW CY AC FO RS1 RSO OV P ODOH
(MSB) (LSB)
Symbol Position Name
CY PSW.7 Carry Flag
AC PSW.6 Auxiliary Carry (For BCD operations)
Fa PSW.5 Flag 0 (user assignable)
RS1 PSW.4 Register Bank Select bit" l '
RSO PSW.3 Register Bank Select bit o·
OV PSW.2 Overflow Flag
- PSW.1 (reserved)
P PSW.O Parity Flag
'(RS1, RSO) enable Internal RAM register banks as follows:
RS1 RSO Internal RAM Register Bank
0 0 BankO
0 1 Bank 1
1 0 Bank 2
1 1 Bank 3
Table 13. peON Special Function Register
Symbolic Physical
Address Address
PCON I SMOD 1 ARB REO GF1 GFO pO ·1 IDL 087H
(MSB) (LSB)
Symbol Position Function
SMOD PCON7 Double Baud rate bit. When set to a
1, the baud rate is doubled when the
serial port is being used in either
Mode 1, 2 or 3.
ARB PCON6 HLD/HLDA Arbiter control bit •
REO PCON5 HLD/HLDA Requestor control bit •
- PCON4 (reserved) \
GF1 PCON3 General-purpose flag bit
GFO PCON2 General-purpose flag bit
PO PCON1 Power Down bit. Setting this bit
activates power down operation.
IDL PCONO Idle Mode bit. Setting this bit
activates idle mode operation.
,See . Ext Memory DMA.. descnpllon
. . .
NOTE:
If 1's are written to PO and IOL at the same time, PO takes precedence. The reset value of peON is (OOOXOOOO).
11-44
UPI-4S2
ABSOLUTE MAXiMUM RATINGS* NOTICE: This is a production data sheet. The specifi-
cations are subject to change without notice.
Ambient Temperature Under Bias ..... O'C to 70'Ct
* WARNING: Stressing the device beyond the "Absolute
Storage Temperature .......... - 65'C to + 150'C Maximum Ratings" may cause permanent damage.
Voltage on Any These are stress ratings only. Operation beyond the
Pin to Vss ............... -0.5V to Vee + 0.5V "Operating Conditions" is not recommended and ex-
tended exposure beyond the "Operating Conditions"
Voltage on Vee to Vss ........... -0.5V to + 6.5V may affect device reliability.
Power Dissipation ........................ 1.0W*·
D.C. CHARACTERISTICS TA = O'Cto 70'C; Vee = 5V ±10%;Vss = OV
Symbol Parameter Min Max Units Test Conditions
VIL Input Low Voltage -0.5 0.8 V
VIH Input High Voltage 2.0 Vee + 0.5 V
(except XTAL 1, RST)
VIH1 Input High Voltage 3.9 Vee + 0.5 V
(XTAL 1, RST)
VOL Output Low Voltage 0.45 V IOL = 1.6 rnA (Note 1)
(Ports 1, 2, 3, 4)
VOL1 Output Low Voltage 0.45 V IOL = 3.2 rnA (Note 1)
(except Ports 1, 2, 3, 4)
--
VOH Output High Voltage 2.4 V IOH = -60 /LA, Vee = 5V J 10%
(Ports 1, 2, 3, 4)
--
0.9 Vee V IOH = -10/LA
----".
VOH1 Output High Voltage 2.4 V IOH = -400 /LA, Vee = 5,! I 10'::.
(except Ports 1,2, 3, 4 and
0.9 Vee V IOH = - 40 /LA (Note 2)
Host Interface (Slave) Port)
VOH2 Output High Voltage 2.4 V IOH = -400 /LA. Vee = 5V ± 10%
(Host Interface (Slave) Port)
Vee - 0.4 V IOH = -10 /LA
IlL Logical 0 Input Current -50 /LA VIN = 0.45V
(Ports 1,2, 3, 4)
ITL Logical 1 to 0 Transition -650 /LA VIN = 2V
Current (Ports 1, 2, 3, 4)
11-45
intJ UPI·452
D.C. CHARACTERISTICS TA = 0·Ct070·C;Vcc = 5V ±10%;Vss = OV(Continued)
Symbol Parameter Min Max Units Test Conditions
III Input Leakage Current ±10 /LA 0.45V < VIN < Vcc
. (except Ports 1, 2, 3, 4) ..
loz Output Leakage Current ±10 /LA 0.45V < VOUT < Vcc
(except Ports 1,2,3,4)
IcC Operating Current 50 mA Vcc = 5.5V, 14 MHz (Note 4)
Icci Idle Mode Current 25 mA Vcc = 5.5V, 14 MHz (Note 5)
IpD Power Down Current 100 /LA VCC = 2V (Note 3)
RRST Reset Pulldown Resistor 50 150 .Kfi
CIO Pin Capacitance 20 pF 1 MHz, T A= 25·C
(sampled, not tested on all parts)
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports
1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1-
to-O transitions during bus operations. In the worst cases (capacitive loading> 100 pF), the noise pulse on the ALE line may
exceed O.BV. In such cases it may bo dosirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt
Trigger STROBE input.
2. Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall before the 0.9 Vee
specification when the address bits aro stabilizing.
3. Power DOWN lee is meas~d with all output pins disconnocted; EA = Port 0 = Vee; XTAL2 N.C.; RST = Vss; DB =
Vee; WR = RD = DACK = CS' AO -- Al = A2 = Vee. Power Down Mode is not suppprted on the B7C452P.
4. lee is measured with all output pins disconnected; XTAL 1 driven with TCLCH, TCHCL = 5 ns, VIL = Vss + 0.5V, VIH =
Vee - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = Vee; WR = RD = DACK = CS = AO = Al = A2 = Vee. Icc would bEi
slightly higher if a crystal oscillator is used. .
5. Idle lee is measured with all output pins disconnected; XTALl driven with TCLCH, TCHCL = 5 ns, VIL = Vss + 0.5V,
VIH = Vee - O.5V; XTAL2 N.C.; Port 0 = Vee; EA = RST = Vss; WR = RD = DACK = CS = AO = Al = A2 = Vee.
EXPLANATION OF THE AC SYMBOLS Q: Output data.
R: READ signal.
.Each timing symbol has 5 characters. The first char-
acter is always a 'T' (stands for time). The other T: Time.
characters, depending on their positions, stand for V: Valid.
the name of a signal or the logical status -of that W: WRITE signal.
-Signal. The following is a list of all the characters and
what they stand for: X: No longer a valid logic level.
A: Address. Z: Float.
C: Clock.
D: Input data. EXAMPLE
H: Logic level HIGH. TAVLL = Time for Address Valid to ALE Low.
I: Instruction (program memory contents). TLLPL = Time for ALE Low to PSEN Low.
L: Logic level LOW, or ALE.
P: PSEN.
11-46
UPI-4S2
A.C. CHARACTERISTICS TA = O°C to 70°C, Vee = 5V ± 10%, VSS = OV, Load Capacitance for
Port 0, ALE, and PSEN = 100 pF, Load Capacitance for All Other Outputs = 80 pF
EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS
14 MHz Osc Variable Oscillator
Symbol Parameter Units
Min Max Min Max
1/TCLCL Oscillator Frequency 3.5 14 MHz
TLHLL ALE Pulse Width 103 2TCLCL-40 ns
TAVLL Address Valid to ALE Low
25 TCLCL-55 ns
(Note 1)
--
TLLAX Address Hold after ALE Low 36 TCLCL-35 ns
TLLlV ALE Low to Valid Instr In 185 4TCLCL-100 ns
TLLPL
TPLPH
TPLIV
ALE Low to PSEN Low
PSEN Pulse Width
PSEN Low to Valid Instr In
31
169
110
TCLCL-40
3TCLCL-45
3TCLCL-105
ns
ns
ns
III
TPXIX Input Instr Hold after PSEN 0 0 ns
TPXIZ Input Instr Float after PSEN
57 TCLCL-25 ns
(Note 1)
TAVIV Address to Valid Instr In 252 5TCLCL-105 ns
TPLAZ PSEN Low to Address Float 10 10 ns
TRLRH RD Pulse Width 329 6TCLCL-100 ns
TWLWH WR Pulse Width 329 6TCLCL-100 ns
TRLDV RD Low to Valid Data In 192 5TCLCL -- 165 ns
TRHDX Data Hold after RD 0 0 ns
TRHDZ Data Float after RD 73 2TCLCL --70 ns
TLLDV ALE Low to Valid Data In 422 8TCLCL 150 ns
--
TAVDV Address to Valid Data In 478 9TCLCL-165 ns
TLLWL ALE Low to RD or WR Low 164 264 3TCLCL-50 3TCLCL+50 ns
TAVWL Address Valid to RD or WR Low 156 4TCLCL -130 ns
TOVWX Data Valid to WR Transition 11 TCLCL-60 ns
TWHOX Data Hold after WR 21 TCLCL-50 ns
TRLAZ RD Low to Address Float 0 0 ns
._-
TWHLH RD or WR High to ALE High 31 111 TCLCL-40 TCLCL+40 ns
--
TOVWH Data Valid to WR (Setup Time) 350 7TCLCL-150 ns
--
NOTE:
1. Use the value of 14 MHz specification or variable oscillator specification, whichever is greater.
11-47
inlef UPI-4S2
EXTERNAL DATA MEMORY READ CYCLE
ALE~ TWHLH~
--- r----------~------~IJ ~------~
I
\,-_ _~I
j.1.---- TLLDV - - - - - 1
PORTO
PORT2 P2.0 - P2.7 OR A8 - A 15 FROM DPH A8-A15 FROM PCH
---'
231428-19
EXTERNAL PROGRAM MEMORY READ CYCLE
ALE
~:-::-<-I+---- TPLPH - - - - i
TPXIZ
TPXIX-
PORTO INSTR IN
PORT2 _ _-1~__________________________- , , -__________A~8~-~Al~5~________
231428-20
11-48
intJ UPI-4S2
EXTERNAL DATA MEMORY WRITE CYCLE
ALEJf
PSEN,J ',--_.oJ I
I---+---TQVWH - - - - I t - !
PORT-a DATA OUT
PORT2 ____-J,~----~P~2-.0---P-2.-7~O-R-A-8---A-15-r-R-O-M-D-P_H______J ,__A_8_-_A_15~rR_O_M_P_CH___
231428-21
SHIFT REGISTER MODE TIMING WAVEFORMS
11-49
inter UPI-452
EXTERNAL CLOCK DRIVE
Symbol Parameter Min Max Units
1/TCLCL Oscillator Frequency 3.5 14 MHz
TCHCX High Time 20 ns
TCLCX Low Time 20 ns
TCLCH Rise Time 20 ns
TCHCL Fall Time 20 ns
NOTE:
External clock timings are sampled, not tested on all parts.
SERIAL PORT TIMING-8HIFT REGISTER MODE
Test Conditions: TA = O·C to 70·C; Vee = 5V ± 10%; Vss .~ OV; Load Capacitance = 80 pF
14 MHz Osc Variable Oscillator
Symbol Parameter Units
Min Max Min Max
TXLXL Serial Port Clock Cycle Time 857 12TCLCL ns
TOVXH Output Data Setup to Clock Rising Edge 581 1OTCLCL -133 ns
TXHOX Output Data Hold after Clock Rising Edge 26 2TCLCL-117 ns
TXHDX Input Data Hold after Clock Rising Edge 0 0 ns
_
TXHDV ..•
Clock Rising Edge to Input Data Valid 581 1OTCLCL -133 ns
EXTERNAL CLOCK DRIVE WAVEFORM
231426-23
AC TESTING INPUT, OUTPUT WAVEFORMS FLOAT WAVEFORMS
VCC- O . 5 - V - 0 •2 Vcc +O.9 V- TIMING REFERENCE
O.45V --A. . tL-
O_._2_V,.;;c;;,c-_O_._1 _ _ _ _
POINTS
231426-24 231426-25
AC inputs during testing are driven at Vcc -0.5V for a logic "1" For timing purposes a port pin is no longer floating when a
and 0.45V for a logic "0". Timing measurements are made at VIH 100 mV change from load voltage occurs, and begins to float
min. for a logic "I" and Vil max. for a logic "0". when a 100 mV change from the loaded VOHIVOl level occurs.
IOl/lOH ;, ± 20 mAo
11-50
inter UPI-452
HLD/HLDA WAVEFORMS
Arbiter Mode
HLD _ _ _-,-~~.----THMIN ------1· V-----------
I-- THLAL =\I ____________________________ l
\~
I - THHAH
~V~----------
231428-26
Requestor Mode
. -I"'~----TAMIN-----IC
HLDA \'--_________ ..
HLD _ _ _ _ _ --11 • """' =1""'___ 231428-31
•
'---------
HLD/HLDA TIMINGS
Test Conditions: TA = O·C to +70·C; Vee = 5V ± 10%, Vss 0.0 OV; Load Capacitance = 80 pF
..
14 MHzOsc Variable Oscillator
Symbol Parameter .- Units
Min Max ...
Min Max
THMIN HLD Pulse Width 386 4TCLCL+100 ns
...
THLAL HLD to HLDA Delay if
186 672 4TCLCL-100 8TCLCL+100 ns
HLDA is Granted
THHAH HLD to HLDA Delay 186 672 4TCLCL-100 8TCLCL+100 ns
TAMIN HLDA Pulse Width 386 4TCLCL+100 ns
TAHHL I-!LDA Inactive to
186 4TCLCL~100 ns
HLDActive
11-51
UPI-4S2
HOST PORT WAVEFORMS
Tee
}
TRV
TOR
Tee
f
~TDH
DATA
DROIN
1 )
DRQOUT
231428-27
HOST PORT TIMINGS
.
Test Conditions: TA = O°C to 70n C; Vee = 5V ± 10%; Vss = OV; Load Capacitance = 80 pF
14 MHz Osc Variable Oscillator
Symbol Parameter ... -- Units
Min Max Min Max
TCC Cycle Time 429 6TCLCL ns
TPW Command Pulse Width 100 100 ns
TRV Recovery Time 60 60 ns
TAS Address Setup Time 5 5 ns
TAH Address Hold Time 30 30 ns
TDS WRITE Data Setup Time 30 30 ns
TDHW WRITE Data Hold Time 5 5 ns
TDHR READ Data Hold Time 5 40 5 40 ns
TDV READ Active. to Read 92 92 , ns
Data Valid Delay
TDR WRITE Inactive to Read 343 4.8TCLCL ns
Data Valid Delay
(Applies only to Host
Control SFR)
TRO READ or WRITE Active 150 150 ns
to DROIN or DRaOUT
.
Inactive Delay
11-52
UPI-4S2
REVISION HISTORY
DOCUMENT: UPI-452 Data Sheet
OLD REVISION NUMBER: 231428-004
NEW REVISION NUMBER: 231428-005
1. Maximum Clock Rate was changed from 16 MHz to 14 MHz. This change is reflected in all Maximum Timing
specifications.
2. The proper range of values for ITHR has been changed from [0 to (CBP-2) 1 to [ 0 to (CBP-3) 1 to ensure
proper setting of the Input FIFO request for service bit. See the following sections: INPUT FIFO CHANNEL,
and INPUT AND OUTPUT FIFO THRESHOLD SFR (lTHR & OTHR).
3. The proper range of values for OTHR has been changed from [ 1 to {(80H-CBP)-111 to [ 2 to {(80-CBP)-111
to ensure proper setting of the Output FIFO request for service bit. See the following sections: OUTPUT
FIFO CHANNEL, FIFO-EXTERNAL HOST INTERFACE FIFO DMA FREEZE MODE, and INPUT AND OUT-
PUT FIFO THRESHOLD SFR (ITHR & OTHR).
4. The following D.C. Characteristics were deleted from the data sheet:
VOH = 0.75* VCC @ IOH = -25/LA,
VOH1 = 0.75* Vcc @ IOH = 150 /LA,
VOH2 = 3.0V @ IOH = 1 mA, and
Icc1 = 15 mA @ Vce = 5.5V (87C452P).
See D.C. CHARACTERISTICS TABLE.
5. The parameter descriptions for THHAH and THLAL has been reversed and their maximum specification for
clock rates less than 14 MHz has been changed from [4TCLC + 100 nsl to [8TCLC + 100 nsl. See
HLD/HLDA TIMINGS.
6. TAMIN specification has been removed from the Arbiter Mode waveform diagram and added to the Request-
or Mode waveform diagram. See HLD/HLDA WAVEFORMS.
11-53
MCS®-51 Development 12
Support Tools·
8051 SOFTWARE DEVELOPMENT PACKAGES
II
;'11011\11··\
COMPLETE SOFTWARE DEVELOPMENT SUPPORT FOR THE
MCS®·51 FAMILY OF MICROCONTROLLERS
Intel supports application development for its MCS®·51 family of microcontrollers with u
complete set of development languages and utilities. These tools include a
macroassembler, a PL/M compiler, linker/relocator program, a librarian utility, and an
object·to·hex utility. Develop code in the language(s) you desire, then combine object
modules from different languages into a single, fast program. These tools were designed
to work with each other, with the MCS-51 architecture, and with the Intel ICE5100 in-
circuit emulator.
FEATURES
• Support for all members of the Intel • Library utility
MCS-51 family of embedded • ObjeCt to hexadecimal converter
microcontrollers • Hosted on IBM PC XTI AT V.3.0 or later
• ASM-51 Macroassembler • Worldwide service and support
• PLlM-51 high-level language
• Linker/Relocator program
November 1990
12-1 Order Number: 280819-001
inter
FEATURES
Create and
Maintain
Ubraries WHh
~p~ 1]]~1
~ rn1)-I_LlnkModul
:S:51
· . 0
.
Write
Soureo
I TogetherBnd
Assign Absolute
=-
Addresses With
rn- ~[j]_J
.......
...."
0
6BConvert
To Hex
Lt °;
--------~.~
PROM
Loadable
Code
280819-2
Figure 1: MCS®-51 Application Development Process
ASM-51 MACROASSEMBLER • Data types facilitate various common
functions. PL/M-51 supports three data
ASM-51 is the macroassembler for the MCS-51
types to facilitate various arithmetic, logic
family of micro controllers. ASM-51 provides
and add ress functions. The language also
fuJI and accurate support for all ofthe specific
uses BASED variables that map more than
compollPnt's instructions. It also provides
one variable to the same memory location to
symholic access to the many features of the
save memory space.
MCS-Ii I family of microcontrollers. Also
provi(kd is an "include" file with all the • Interrupt attribute speeds coding effort.
The INTERRUPT attribute allows you to
appropriate component registers and memory
spaces defined. easily define interrupt handling procedures.
The compiler will generate code to save and
The macro facility in ASM-51 saves restore the program status word for
development and maintenance tim(~, since INTERRUPT procedures.
common code sequences need only 1)(' • Code optimization reduces memory
developed once. requirements. The PL/M-51 compiler has
four different levels of optimization for
PL/M-51 COMPILER significantly reducing the size of the
PLlM-51 is a high-level language designed to program.
support the software requirements of the MCS- • Language compatibility saves
51 family of microcontrollers. The PL/M-51 development time. PL/M-51 object modules
compiler translates PL/M high-level language are compatible with object modules
statements into MCS-51 relocatable object generated by all other MCS-51 language
code. Major features of the PL/M-51 compiler translators. This compatibility allows for
include: easy linking of all modules and the ability to
• Structured programming for case of do symbolic debugging with the Intel
maintenance and enhancement. The PLI ICE5100 in-circuit emulator.
M-51 language supports modular and
structured programming, making programs
easier to understand, maintain, and debug.
12-2
FEATURES
RL-51 LINKERIRELOCATOR SERVICE, SUPPORT, AND
Intel's RL-51 utility is used to link multiple TRAINING
MCS-51 object modules into a single program, Intel augments its MCS-51 architecture family
resolve all references between modules and of development tools with a full array of
assign absolute addresses to all relocatable seminars, classes, and workshops; on-site
segments. Modules can be written in either consulting services; field application
ASM-51 or PL/M-51. engineering expertise; telephone hot-line
support; and software and hardware
LIB-51 maintenance contracts. This full line of
The Intel LIB-51 utility creates and maintains services will ensure your design success.
libraries of software object modules. Standard
modules can be placed in a library and linked
into your applications programs using RL-51.
When using libraries, the linker will link only
those modules that are required to satisfy
external references.
OH OBJECT TO HEXADECIMAL
CONVERTER
The OH utility converts Intel OMF-51 object
modules into standard hexadecimal format.
This allows the code to be loaded directly into
PROM via non-Intel PROM programmers.
ORDERING INFORMATION
DS6ASM51* MCS-51 Assembler for PC XT or
AT system (or compatible),
running DOS 3.0 or higher
DS6PLM51* PL/M-51 Software Package for
PC XT or AT system (or
compatible), running DOS 3.0 or
higher
* Also includes: Relocator/Linker, Object-to-
hex converter, and Librarian.
For direct information on Intel's Development
Tools, or for the number of your nearest sales
office or distributor, callSOO-S74-6835 (U.S.).
For information or literature on additional
Intel products, callSOO-54S-4725 (U.S. and
Canada).
12-3
inter
AEDIT SOURCE CODE AND TEXT EDITOR
280804-1
PROGRAMMER SUPPORT
AEDIT is a full-screen text editing system designed specifically for software engineers
and technical writers. With the facilities for automatic program block indentation, HEX
display and input, and full macro support, AEDIT is an essential tool for any
programming environment. And with AEDIT, the output file is the pure ASCII text (or
HEX code) you input-no special characters or proprietary formats.
Dual iIle editing means you can create source code and its supporting documents at the
same time. Keep your program listing with its errors in the background for easy
reference while correcting the source in the foreground. Using the split-screen windowing
capability, it is easy to compare two files, or copy text from one to the other. The DOS
system-escape command eliminates the need to leave the editor to compile a program, get
a directory listing, or execute any other program executable at the DOS system level.
There are no limits placed on the size of the file or the length of the lines processed with
AEDIT. It even has a batch mode for those times when you need to make automatic string
substitutions or insertions in a number of separate text files.
AEDIT FEATURES
• Complete range of editing support-from • Full macro support for complex or
document processing to HEX code entry repetitive editing tasks
and modiiIcation • Hosted on PC-DOS and RMX operating
• Supports system escape for quick systems
execution of PC-DOS System level • Dual file support with optional split-
commands screen windowing
• No limit to file size or line length
October 1990
12-4 Order Number: 280804-002
FEATURES
• Quick response with an easy to use menu configure AEDIT to work with almost any
driven interface terminal. This along with user-definable
• Configurable and extensible for complete macros and full adjustable tabs, margins, and
control of the editing process case sensitivity combine to make AEDIT one of
the most flexible editors available today.
POWERFUL TEXT EDITOR
As a text editor, AEDIT is versatile and MACRO SUPPORT
complete. In addition to simple character AEDIT will create macros by simply keeping
insertion and cursor positioning commands, track of the command and text that you type,
AEDIT supports a number of text block "learning" the function the macro is to
processing commands. Using these commands perform. The editor remembers your actions
you can easily move, copy, or delete both small for later execution, or you may store them in a
and large blocks of text. AEDIT also provides file to use in a later editing session.
facilities for forward or reverse string Alternatively, you can design a macro using
searches, string replacement and query AEDIT's powerful macro language. Included
replace. with the editor is an extensive library of useful
AEDIT removes the restriction of only macros which you may use or modify to meet
inserting characters when adding or modifying your individual editing needs.
text. When adding text with AEDIT you may
choose to either insert characters at the TEXT PROCESSING
current cursor location, or over-write the For yom- documentatioll needs, paragraph
existing text as you type. This flexibility filling or justificatioll ~ill1plifies the chore of
simplifies the creation and editing of tables document formatting. Automatic carriage
and charts. return insertion means you can focus on the
content of what you are typing instead of how
USER INTERFACE close you are to the edge of the screen.
The menu-driven interface AEDIT provides
makes it unnecessary to memorize long lists of SERVICE, SUPPORT, AND
commands and their syntax. Instead, a TRAINING
complete list of the commands or options
Intel augments its development tools with a
available at any point is always displayed at full array of seminars, classes, and workshops;
the bottom of the screen. This makes AEDIT
on-site consulting services; field application
both easy to learn and easy to use. engineering expertise; telephone hot-lim'
support; and software and hardware
FULL FLEXIBILITY maintenance contracts. This full line of
In addition to the standard PC terminal services will ensure your design success.
support provided with AEDIT, you are able to
SPECIFICATIONS
HOST SYSTEM 122716 AEDIT-DOS Users Guide
AEDIT for PC-DOS has been designed to run 122721 AEDIT-DOS Pocket
on the IBM· PC XT, IBM PC AT, and Reference
compatibles. It has been tested and evaluated RMX864WSU AEDIT for iRMX I Operating
for the PC-DOS 3.0 or greater operating System
system.
R286EDI286EU AEDIT for iRMX II/III
Versions of AEDIT are available for the Operating System
iRMXTM-86 and iRMX II Operating System.
ORDERING INFORMATION
D86EDINL AEDIT Source Code Editor
Release 2.2 for PC-DOS with
supporting documentation
12-5
ICETM-51/PC IN-CIRCUIT EMULATOR
280883-1
CUT COSTS, NOT CORNERS
The ICETM-511PC family in-circuit emulators for the MCS®-51 family of microcontrollers
are easy to use, powerful, and attractive in price. A windowed user interface and source
level debugging simplify use. The sophisticated event recognition features, the ability to
access debug information during emulation, and performance analysis functions provide
debugging power. Intel's long standing expertise in emulator design delivers impressive
features for a very respectable price.
ICETM·SllPC FAMILY FEATURES
• Color windowed user interface • 4096 frame trace buffer accessible during
• Source level debugging with symbolic emulation
referencing and display • Emulation and event timers for
• Recognition of internal data write, performance analysis
external data read/write, instruction • User-definable debug and test
fetch, exeCution address, external input procedures with variables and literal
line state, and trace buffer full events definitions
• AND/OR combination of events • Zero wait state mappable emulator
• Qualification of an event by number of memory to 64K bytes code plus 64K
occurrences bytesxdata
• Arming of an event conditional on the • On-eircuit emulation of surface mounted
occurrence of another event components
• Access to microcontroller contentsl • Four input logic pins to capture external
memory during emulation events
November 1990
12-6 Order Number: 280883-001
FEATURES
WINDOWED USER INTERFACE disassembled (in the Memory Window) or
For ease of use and learning, the ICE-511PC within the trace buffer (in the Trace Window).
user works through a windowed interface.
Each window, such as Memory, Source, EVENTRECOGNITIONAND
Register, and Watch (user variable display), TRACE
presents a different view of the system. And a To speed the debugging process, the ICE-511PC
Custom Window performs a user-defined user has access to very sophisticated event
function. Within each window, option menus, recognition capabilities. Internal data write,
pop-up fill-in-the-blank forms, and scroll keys external data read/write, instruction fetch,
control the view. As expected, windows may be execution address, external input line state,
added, sized, zoomed to full screen, or removed and trace buffer full events may be used as
completely. triggers. Compound triggers may be .
Pull-down menus and function keys streamline constructed through AND/OR combinations of
emulator use by providing convenient access to events. The recognition of an event may be
common functions. On the other hand, the armed based on the occurrence of another
Command Line Window provides the power event. Events may be further qualified by a
user the most efficient access to all emulator number of occu rrc,nces. Since this
functions. Augmenting command entry is a sophistical iOIl l!lay lead to complex breakl
syntax guide and recall I editing of prior trace defllliLiom;, Break Registers are available
commands. Of course, command syntax is to store definitions for reuse.
compatible with prior non-windowed Intel The Fastbreaks feature ofICE-511PC emulator
emulators. allows the user to execute emulator commands
Help is at your fingertips. One keystroke pops with minimal intrusion on emubtion.
up the help menu. Help is available by subject Fastbreaks are typically used for accesses to
index or for the current window's operation, microcontroller contents or 1l1l·1!l<lrv. A
function keys, pull-down menus, and error Fastbreak halts emulation, 1)('1'1',,,·,,',,; Lhe
messages. In addition, a Key Reference Line requested memory access, reSll/llt·:; "Illulal i<l/l,
displays a list of the currently active function and reports back to the user. Emul,,( i<l" i;;
keys as well as brief help text for menus and halted only for the few machine cycles
forms. necessary to perform the access.
Similarly, the trace buffer is accessible durilW
SOURCE LEVEL DEBUGGING (!ll1ulation. The buffer produces 4096 frames of
Source level debugging features are synergistic execution address, opcode in hex and
with the windowed user interface. For mnemonic formats, operands in hex and
example, simply use a pull-down menu to load symbolic formats, bus activity, external line
the program. Breakpoints are set by pointing (clips) states, and source code.
to a line of code within the Source Window and To aid performance analysis, an event timer
pressing a function key. Set trace records the time from Ito specified events while
specifications through the pop-up fill-in-the- an emulation timer records the total duration
blank form in the Trace Window. And with the of emulation.
current execution point and breakpoints
highlighted in color, press a function key to GENUINE INTEL TOOLS
begin emulation. The ICE-51/PC provides the most
Scroll to another line in the Source Window comprehensive support for Intel's MCS®-5l
and press a function key to execute to that family of inicrocontrollers. When you trust
point, bypassing yet retaining the previously your component selection to Intel, why trust
set breakpoints. From there, use a pull-down its emulation to someone else? And the ICE-
menu to add a variable, referenced 5l/PC emulators work better because they
symbolically, to the Watch Window; with each work together with products, such as C
press of another function key the program is compilers, from leading Independent Software
executed one source line at a time and the Vendors such as Archimedes, Franklin, and
Watch Window display is updated. Micro Computer Control as well as Intel's own
Source statements and symbolic information macro assembler and PL/M compiler.
are also displayed when memory is
12-7
inter
SPECIFICATIONS
EMULATOR ELECTRICAL CHARACTERISTICS
The AC characteristics for all pins except PO, P2, ALE, and PSEN / are mairitained with a
maximum capacitive target load lSpf less than specified in the component data sheet for the
SxCSIGB. . .
The AC timing degradations for PO, p2, ALE, and PSEN / are maintained with a maximum
capacitive target load of 70pf.
The maximum rise and fall times for ALE and PSEN / with a target load of 20pf are 7ns and 2ns
respectively.
The maximum rise and fall times for·PO and P2 with a target load of SOpf are 27ns and IOns
respectively. Rise and fall times are specified at the 10% and 90% points.
The emulation processor requires 2 to 3 clock cycles longer to respond to reset.
For external program memory characteristics involving RD' and WR', observe the following
degradations:
• Setup time to RD' is Uns longer (max.).
• It takes 30ns longer for data to appear on the bus with respect to WRo (max.).
• The falling edges ofRD* and WR' can be delayed by 70ns (max.).
Table C-l shows the characteristics for external program memory.
12-8
intJ
SPECIFICATIONS.
Table C-I. External Program Memory Characteristics
Symbol Parameter Minimum Maximum Units
TAVLL Address Valid to ALE Low .85TCLCL-19 ns
TLLAX Address Hold after ALE Low 10 ns
TLLIV ALE Low to Valid Instruction In 3. 15TCLCL-18 ns
TLLPL ALE Low to PSEN lLow .85TCLCL-1 ns
TPLIV PSEN ILow to Valid Instruction In 2.15TCLCL-18 ns
TPXIZ Input Instr Float after PSEN I 24 ns
TPXAV PSEN I to Address Valid TCLCL+20 ns
TAVIV Address to Valid Instruction In 4. 15TCLCL-66 ns
TPLAZ PSEN I Low to Address Float 4 ns
TLLDV ALE Low to Valid Data In 7.15TCLCL-18 ns
TAVDV Address to Valid Data In 8.15TCLCL-66 ns
TOP VIEW
PROCESSOR MODULE ~ P7
[rmo~~_"~.
1
H '16 1
l~.l
I
CABLE 000'1'
36" . I 3.25" J
SIDE VIEW
/ 1'lfIll I.:;SOR MODULE
/ 4----'
bgj= Ld~'
280883-3
Figure 1: Processor Module Dimensions.
NOTE: Processor module dimensions will vary for the ICE-51FXfPC
12-9
intJ
SPECIFICATIONS
CONFIGURATION AND ORDERING INFORMATION
The ICE-511PC emulator utilizes an IBM PC XT, PC AT, or compatible personal computer with
hard disk drive, 640 Kbytes of memory, and DOS 3.x as the host system. Emulator host software
is provided on both 5.25 and 3.5 inch flexible disk media.
The ICE-51GB/PC in-circuit emulator provides emulation for the 87C51GB A-I step device in 68
lead PLCC packaging.
The ICE-51FX/PC emulator supports the 8031,8 X 51, 8032,8 X 52, 80C31, 8 X C51, 80C32, 80C52,
8 X C51FA, 8 X C51FB, and 8 X C51FC components in either 40 lead DIP or 44 lead PLCC package
(the target interface board directly supports 40L DIP, an adapter to support 44L PLCC is
included).
An ICE-511PC emulator utilizes a common emulation controller card with interchangeable target
interface boards (TIB). An ICE-51FX/PC may be converted to support the 87C51GB A-I step
microcontroller by installing a probe kit. Likewise, an ICE-51GB/PC may be converted to an
ICE-51FX/PC by installing a probe kit.
A standard ICE-51/PC emulator includes 16 Kbytes of mappable code/xdata memory. Additional
memory is optionally available to bring the total to 128 Kbytes, 64 Kbytes code/64 Kbytes xdata.
A Crystal Power Accessory (CPA) is optionally available for testing the TIB to target system
connection. Standalone software execution does not require a CPA.
Product Code Description
ICE51FXPC Complete ICE-51FX/PC emulator. Includes PC XT form factor emulation
controller card, controller to TIB cable, TIB for MCS-51 microcontrollers, PC
DOS host software on 5.25 and 3.5 inch media, and product manuals
ICE5HmpC Complete ICE-51GB/PC emulator. PC XT form factor emulation controller
card, controller to TIB cable, TIB for the 68 lead PLCC 87C51GB A-I step
device, l'C DOS host software on 5.25 and 3.5 inch media, and product
manuals
ICE51FXl'HOBE ICE-51FX/PC conversion kit. Includes TIB for MCS-51 family of
microcontrollers, PC DOS host software on 5.25 and 3.5 inch media and
product manuals
ICE51GBPHOBE ICE-51GB/PC conversion kit. Includes TIB for the 68 lead PLCC 87C51GB
A-I step (kvice, PC DOS host software and 5.25 and 3.5 inch media, and
product man uals
ICE51MEMOHY ICE-51/PC additional memory to bring the total mappable emulator
memory to 128K bytes
ICE51FXCPA ICE-51FX/PC crystal power accessory
ICE51GBCPA ICE-51GB/PC crystal power accessory
ADPTONC68PLCC ICE-51GB/PC on-circuit emulation adaptor for 68 Pin PLCC devices
D86ASM51NL MCS-51 macro assembler, linker/locator utility, object code librarian, and
object to hex convertor
D86PLM51NL MCS-51 PL/M compiler, linker/locator utility, object code librarian, and
object to hex convertor
12-10
ICETM·5100/252 IN·CIRCUIT EMULATOR
IN-CmCUIT EMULATOR FOR THE MCS®-51 FAMILY OF
MICROCONTROLLERS '
The ICETM-5100/252 In-Circuit Emulator is a complete hardware/software debug
environment for developing embedded control applicatiolls based on the Intel MCS"'-51
family of microcontrollers. With high-performance 11i MHz emulation, symbolic
debugging, and flexible memory mapping, the ICE-5100/252 emulator expedih'H ull
stages of development: hardware development, software development, system
integration, and system test; shortening your project's time to market.
FEATURES
• Full speed to 16 MHz • Source code display
• 64KB of emulation mapped memory • ASM-51 and PL/M-51 language support
• 254 frames of execution trace • Pop-up help
• Symbolic debug • DOS shell escape
• Serial link to an mM PC XT, AT, PS/2, • On-line tutorial
or 100% compatible • Built-in CRT based editor
• Four address breakpoints with in-range, • System self-test diagnosticS
.out-of-range, and page breaks • Worldwide service and support
• On-line disassembler and single line
assembler
MCS" is a registered trademark of Intel Corporation.
ICETM is a trademark of Intel Corporation.
IBM" and PC AT" are registered trademarks of International Business Machines Corporation.
PC XTTM and PS/2TM are of International Business Machines Corporation.
November 1990
12-11 Order Number: 280798-002
inter
FEATURES
ONE TOOL FOR ENTIRE PATCH CODE WITHOUT
DEVELOPMENT CYCLE RECOMPILING
The ICE-5100/252 emulator speeds target Code-patching is easy with the ICE-5100/252
system development by allowing hardware and emulator's single-line assembler, Machine code
software design to proceed simultaneously. can be disassembled to mnemonics for
You can develop software even before significantly easier debugging and project
prototype hardware is finished. And because. development.
the ICE-5100/252 emulator precisely matches
the component's electrical and timing EASY TO LEARN AND USE
characteristics, it's a valuable tool for The ICE-5100/252 is accompanied by a full
hardware development and debug. Thus, the t.ut.orial that explains all system functions and
ICE-5100/252 emulator can debug a prototype provides many examples. Additional features
or production system at any stage in its slich as on-line help, a built-in CRT-based
development, without introducing extraneous ('ditor, and DOS shell escape make the
hardware or software test tools. emulator fast and easy to use for both novice
and experienced users. You can develop your
HIGH·SPEED,REAL·TIME own test suites or save frequently-used debug
EMULATION routines as debug procedures (PROCs) that can
The ICE-5100/252 emulator provides full- be invoked with a single command.
speed, real-time emulation up to 16 MHz.
Because the emulator is fully transparent to WORLDWIDE SERVICE AND
the target system, you have complete control SUPPORT
over hardware and software debug and system The ICE-5100/252 emulator is supported by
in tegration. Intel's worldwide service and support
64I<B of zero wait-state emulation memory is organization. In addition to an extended
available to replace target system code warranty, you can choose from hotline support,
memory, allowing software debug to begin on-site system engineering assistance, and a
even before prototype hardware is finished. variety of hands-on training workshops.
ICETM-5100/252 Emulator Supported
FLEXIBLE BREAKPOINTING Components
FOR QUICK PROBLEM
ISOLATION Product ROM/EPROM RAM
The ICE-5100/252 emulator supports three 80C51FA ROMLESS 256
different types of break specifications: specific 83C51FA 8KROM 256
address breaks on up to 64,000 possible 87C51FA 8KEPROM 256
addresses; range breaks, both within and 83C51FB 16K ROM 256
outside a user-defined range; and page breaks, 87C51FB 16K EPROM 256
up to 256 pages on 256-byte boundaries. 254 80C32 ROMLESS 256
frames of execution trace memory provide
ample debug information, with each frame 80C52 8KROM 256
divided into 16 bits of program ex;ecution 80C3IBH ROMLESS 128
address and 8 bits of external event 80C51BH 4KROM 128
information. A maximum offour tracepoints 80C5IBHP 4KROM 128
allows qualified trace for a variety of debug 87C51 4KEPROM 128
conditions. 8032AH ROMLESS 256
8052AH 8KROM 256
SYMBOLIC DEBUGGING FOR 8752BH 8KEPROM 256
FAST DEVELOPMENT 8031AH ROMLESS 128
Design team productivity is enhanced by the 8051AH 4KROM 128
use of symbolic debug references to program 8051AHP 4KROM 128
line, high-level statements, and module and 8751H 4KEPROM 128
variable names. The terms used to develop 875IBH 4KEPROM 128
programs are the same used for system
debugging. .
12·12
inter
SPECIFICATIONS
ELECTRICAL CONSIDERATIONS
The emulation processor's user-pin timings and loadings are identical to the 80C51FA component
except as follows.
Maximum Operating ICC and Idle ICC (rna)"
Maximum Operating ICC (rna)" Maximum Idle ICC (ma)--
Vee
4V 5V 6V 4V 5V 6V
Frequency
0.5 MHz 0.87 1.62 3.0 0.58 1.21 2.5
3.5 MHz 4.8 6.82 9.76 2.2 4.97 6.33
8.0 MHz 10.5 15.0 20.5 6.0 8.98 11.76
12.0 MHz 15.2 22.2 30.2 9.2 13.34 17.46
16.0 MHz 19.4 28.6 38.7 11.8 17.4 23.4
"'ICC IS measured wlth all output pins disconnected
XTAL1 driven with TCLCH, TCHCL ~ 10 ns, Vii ~ Vss + .5V, Vih ~ Vee - .5V. XTAL2 not connected.
For maximum operating ICC
EA ~ RST ~ PortO ~ Vee.
'" "'For maximum idle ICC
EA ~ Port 0 ~ Vee, RST ~ Vee, internal clock to PCA gated off.
• Up to 25 pf of additional pin capacitance is • Pins 18 and 19, XTALI and XTAL2,
contributed by the processor module and respectively, have approximately 15 to 16 pf
target adaptor assemblies. of additional capacit nllce when configured
• Pin 31, EA, has approximately 32 pf of for cryst.al operation.
additional capacitance loading due to sensing
circuitry.
PROCESSOR MODULE DIMENSIONS
101' VIUI'
}[uCC_""jl~~~I};
-----.J--I-(10.~'~m)---I
. ~ "00''''"'''"
~L!J~~2"
~m)
TARGE:T
ADAPTOR
280796-02
Figure 1. Processor Module Dimensions
CHMOS AND HMOS DESIGN DIFFERENCES
HMOS CHMOS
Chip Function Component 8031 Component 80C31
RST trigger threshold 2.5V 70% Vee (3.5V @ Vee = 5V)
RST input impedance 4K-10Kohms 50K-150K ohms
Port Iii -800/LA -50/LA
Clock threshold 2.5V 70% Vee (3.5V @ Vee = 5V)
12-13
inter
SPECIFICATIONS
HOST REQUIREMENTS
IBM PC XT, AT, PS/2, or 100% compatible
PC-DOS3.x
512KRAM
One floppy drive and hard disk
PHYSICAL CHARACTERISTICS
The ICE-5100/252 emulator consists of the following components:
Width Height Length
Unit
Inch Cm Inch Cm . Inch Cm
Controller Pod 8.25 21.0 1.5 3.8 13.5 34.3
User Cable 39.0 99.0
Processor Module' 3.8 9.7 1.5 3.8 4.0 10.2
Power Supply 7.6 18.1 4.0 10.2 11.0 28.0
Serial Cable 144.0 360.0
'wlth Hupphed target adaptor.
ELECTRICAL ENVIRONMENTAL
'CHARACTERISTICS CHARACTERISTICS
Power supply Operating temperature: + 10" to + 40°C (50° to
100·120V or 220-240V selectable 104°F)
50-(j() Hz Operating humidity: Maximum of 85%
2 amps (AC max) @ 120V relative humidity, non-condensing
1 amp (AC max) @ 240V
ORDERING INFORMATION
Order Code Description pC252KITD Conversion kit for ICE-5100/452,
pI252KITAD Kit contains ICE-5100/252 user ICE-5100/451,orICE-5100/044
probe assembly, power supply running PC-DOS 3.0 or later, to
and cables, serial cables, target provide emulation support for
adapter, crystal power accessory, MCS-51 components (requires
emulator controller pod, software license).
emulator software, DOS host TA252D Target adaptor converting 48-
communication, ASM-51 and pin DIP to 44-pin PLCC package.
AEDIT text editor (requires D86ASM51 ASM/RL 51 package for PC-DOS
software license). (requires software license).
pI252KITD Kit contains the same D86PLM51 PL/M/RL 51 package for PC-
components as pI252KITAD, DOS (requires software license).
excluding ASM-51 and the
AEDIT text editor (requires D86EDINL AEDIT text editor for PC-DOS.
software license).
12-14
ICETM·5100/452 IN· CIRCUIT EMULATOR
:,?II()I!I'··\
IN·CIRCUIT EMULATOR FOR 1'111'; UPITM·452 FAMILY OF
PROGRAMMABLE I/O PROCESSORS
The ICETM-5100/452 In-Circuit Emulator is a ('olllplete hardware/software debur;
environment for developing embedded control applications based on the Intel UPl'1'M-452
family ofl/O peripherals. With high-performance full-speed emulation, symbolic
debugging, and flexible memory mapping, the lCE-5100/452 emulator expedites all
stages of development: hardware development, software development. system
integration, and system test; shortening your project's time to market.
Features
• Full speed to the speed ofthe component. • Source code display.
• 64 KB of emulation mapped memory. o ASM-51 and PLlM-51 language support.
• 254 frames of execution trace. o Pop-up help.
• Symbolic debug. • DOS shell escape.
• Serial link to an IBM PC XT, AT, 100% o On-line tutorial.
compatible. • Built-in CRT based editor.
o Four address breakpoints with in-range, o System self-test diagnostics.
out-of-range, and page breaks. o Worldwide service and support.
o On-line disassembler and single line
assembler .
• Full emulation and debug support for the
FIFO Buffer. -
Mes is a registered trademark and ICE is a trademark of Intel Corporation.
IBM and PC AT are registered trademarks and PC XT is a trademark of International Business Machines Corporation.
November 1990
12-15 Order Number: 280817-001
FEATURES
ONE TOOL FOR ENTIRE SYMBOLIC DEBUGGING FOR
DEVELOPldENT CYCLE FAST DEVELOPMENT
The ICE-5100/452 emulator speeds target Design team productivity is enhanced by the
system development by allowing hardware and use of symbolic debug references to program
software design to proceed simultaneously. line, high-level statements, and module and
You can develop software even before variable names. The terms used to develop
prototype hardware is finished. And because programs are the same used for system
the ICE-5100/452 emulator precisely matches debugging.
the component's electrical and timing
characteristics, it's a valuable tool for PATCH CODE WITHOUT
hardware development and debug. Thus, the RECOMPILING
ICE-5100/452 emulator can debug a prototype
or production system at any stage in its Code-patching is easy with the ICE-5100/452
development, without introducing extraneous emulator's single-line assembler. Machine code
hardware or software test tools. can be disassembled to mnemonics for
si~llificantly easier debugging and project
HIGH-SPEED, REAL-TIME development.
EMULATION EASY TO LEARN AND USE
The ICE-5100/452 emulator provides full- The ICE-5100/452 is accompanied by a full
speed, real-time emulation up to the speed of tutorial that explains all system functions and
the component. Because the emulator is fully provides many examples. Additional features
transparent to the target system, you have such as on-line help, a built-in CRT-based
complete control over hardware and software editor, and DOS shell escape make the
debug and system integration. emulator fast and easy to use for both novice
64 KB of zero wait-state emulation memory is and experienced users. You can develop your
available to replace target system code own test suites or save frequently-used debug
memory, allowing software debug to begin routines as debug procedures (PROCs) that can
even before prototype hardware is finished. be invoked with a single command.
FLEXIBLE BREAKPOINTING WORLDWIDE SERVICE AND
FOR QUICK PROBLEM SUPPORT
ISOLATION The ICE-5100/452 emulator is supported by
The ICE-5100/452 emulator supports three Intel's worldwide service and support
different types of break specifications: specific organization. In addition to an extended
address breaks on up to 64,000 possible warranty, you can choose from hotline support,
addresses; range breaks, both within and on-site system engineering assistance, and a
outside a user-defined range; and page breaks, variety of hands-on training workshops.
up to 256 pages on 256-byte boundaries. 254
frames of execution trace memory provide
ample debug information, with each frame
divided into 16 bits of program execution
address and 8 bits of external event
information. A maximum offour tracepoints
allows qualified trace for a variety of debug
conditions.
12-16
inter
SPECIFICATIONS
ELECTRICAL
CONSIDERATIONS
The emulation processor's user-pin timings
and loadings are identical to the 452
component except as follows:
• Up to 25 pF of additional pin capacitance is
contributed by the processor module and
ta~get adaptor assemblies.
PROCESSOR MODULE DIMENSIONS
TOP VIEW
/ CONTROLLER POD CONNECTOR
~~1________________- .
PROCESSOR MODULE'\. r PIN 1
.. >
~~~~~ f--;1
~ 1313/16"
~U ~~a~ ~ Jem)
IJ.'-----------CAB\~.~ODY..,.._--------_t,14- - (10.~·em)----I
_____,.
(9gem)
~CJCJ~_
.
TARGET
"=~ I'R;CESSOR MODULE
C:_=;::::;::=?_~ (3.8
11/2"
_ ----1
em)
ADAPTOR
;'110817-2
Figure 1: Processor Module Dimensions
Host Requirements Electr;("(I{ Character;Htics
IBM PCXT, AT or compatible Power supply
PC-DOS 3.0 or later 100-120V or 220-240V selectable
512KRAM 50-60 Hz
One floppy drive and hard disk 2 amps (AC max) @ 120V
1 amp (AC max) @ 240V
Environmental Characteristics
Operating temperature: + lOoC to + 40°C·
(50"F to + 104°F)
Operating humidity: Maximum of 85%
relative humidity,
non-condensing
12-17
ORDERING INFORMATION
Physical Characteristics
The ICE-5l00/452 emulator consists ofthe following components:
Width Height Length
Unit
Inch Cm Inch Cm Inch Cm
Controller Pod S.25 21.0 1.5 3.S 13.5 34.3
User Cable 39.0 99.0
Processor Module' 3.S 9.7 1.5 3.S 1.0 10.2
Power Supply 7.6 IS. 1 4.0 10.2 11.0 2S.0
Serial Cable 144.0 360.0
\ "'wIth supphed target adapter.
Order Code Description
pI452KITAD Kit contains ICE-5l00/452 user 'l'A452E Target adapter for 6S-pin PLCC
probe assembly, power supply packagl'support.
and cables, serial cables, target DS6ASM5l ASMIHL Gl package for PC-
adapter, crysl al power DOS (requires software license).
accessory, ('Illulator controller DS6PLM5l PL/M/RL 51 package for PC-
pod, emulator software, DOS DOS (requires software license).
host com mUll ication cables,
ASM-5l and 1\ EDIT text editor DS6EDINL AEDIT text editor for PC-DOS.
(requires soflware license). For direct information on Intel's Development
pI152KITD Kit contains I he same Tools, or for the number of your nearest sales
components:ls pI452KITAD, ojTi('(~ or distributor, callSOO-S74-6S35 (U.S.).
excluding ASM-5l and the For information or literature on additional
AEDIT text (·<lilor (requires Int,·] products, callSOO-54S-4725 (U.S. and
software license). Can:l<]a).
pC452KITD Conversion kil for ICE-5l001
451, ICE-5100/252, or ICE-5l001
044 running P( '-DOS 3.0 or
later, to provid" C'mulation
support for SOC152 components
(requires software I icens(').
12-18
RUPITM.,44 Family
13
October 1988
The RUPITM_44 Family:
Microcontroller with On-Chip
Communication Controller
Order Number: 296163-001
13-1
THE RUPITM·44 FAMILY: CONTENTS PAGE
MICROCONTROLLER WITH INTRODUCTION ........................ 13-3
ON·CHIP COMMUNICATION 1.0 ARCHITECTURE OVERViEW ....... 13-3
CONTROLLER
2.0 THE HOLC/SDLC PROTOCOLS ... ; 13-5
2.1 HOLe/SOLe Advantages over
Async '......................... 13-5
2.2 HOLe/SOLe Networks .......... 13-6
2.3.Frames .......................... 13-6
2.4 Zero Bit Insertion ................ 13-6
2.5 Non-Return to Zero Inverted
(NR21) ........................ 13-7
2.6 References ...................... 13-7
3.0 RUPITM-44 DESIGN SUPPORT ..... 13-7
3.1 Oesign Tool Support ............. 13-7
3.28051 Workshop .................. 13-8
13-2
intJ THE RUPITM-44 FAMILY
INTRODUCTION real-time control applications such as instrumentation,
industrial control, and intelligent computer peripherals.
The RUPI-44 family is designed for applications re- The microcontroller features on-chip peripherals such
quiring local intelligence at remote nodes, and commu- as two 16-bit timer/counters and 5 source interrupt ca-
nication capability among these distributed nodes. The pability with programmable priority levels. The micro-
RUPI-44 integrates onto a single chip Intel's highest controller's high performance CPU executes most in-
performance microcontroller, the 80S I-core, with an structions in I microsecond, and can perform an 8 X 8
intelligent and high performance Serial communication multiply in 4 microseconds. The CPU features a Boole-
controller, called the Serial Interface Unit, or SIU. See an processor that can perform operations on 256 direct-
Figure 1. This dual controller architecture allows com- ly addressable bits. 192 bytes of on-chip data RAM can
plex control and high speed data communication func- be extended to 64K bytes externally. 4K bytes of on-
tions to be realized cost effectively. chip program ROM can be extended to 64K bytes ex-
ternally. The CPU and SIU run concurrently. See Fig-
The RUPI-44 family consists of three pin compatible ure 2.
parts:
• 8344-8051 Microcontroller with SIU The SIU is designed to perform serial communications
with little or no CPU involvement. The SIU supports
• 8044-An 8344 with 4K bytes of on-chip ROM pro- data rates up to 2.4 Mbps, externally clocked, and
gram memory 375 Kbps self clocked (i.e., the data clock is recovered
• B744-An 8344 with 4K bytes of on-chip EPROM by an on-chip digital phase locked loop). SIU hardware
program memory supports the HDLC/SDLC protocol: zero bit inser-
tion/deletion, address recognition, cyclic redundancy
check, and frame number sequence check are automati-
1.0 ARCHITECTURE OVERVIEW cally performed.
The 8044's dual controller architecture enables lilt" The SIU's Auto mode greatly reduces communication
RUPI to perform complex control tasks and high :'I1(T<I software overhead. The AUTO mode supports the •
communication in a distributed network cnvironml"nl. SDLC Normal I~csponse Mode, by performing second-
ary station responses in hardware withoul any CPU
The 8044 microcontroller is the B051-corc, and nJ;,in- involvemcnl. The Auto mode's ini<"rrupt control and
tains complete software compatibility with it. The mi- frame sequence nllillbering capabilily eliminates soft-
crocontroller contains a powerful CPU with on-chip ware overhead nllnllally required in convl"ntional sys-
peripherals, making it capable of serving sophisticated tems. By lIsilI!: II".: Auto mode, the (:PU is free to con-
centrate Oil n':" limc control of Ihe applicalion.
r---------------· -·----1
~~ m. H .=' H '" I· i
I1_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ JI
.. ImLC/SDLC
COMMUNICATION
2U61G:I-l
Figure 1. RUPITM-44 Dual Controller Architecture
13-3
cf
REFERENCE
OSCIlLATOII
r ---- ----------------------,
5. ~--- I
!! I
IQ ~-- TWO .. IYTES aPORT I
!;i I GROUND TIllER PROGRAM OATARAM
COUNTEIIS MEMORY
ID
~
I -I
I %
!e. m
3 I ::u
'2. c:
:5 I "a
~
ID
~
(..)
Q.
QI
I I
~ 0 SElltAl.
I ~
~ ~
~ 1051
aI CPU
INTVIFACE
HDLC/SDl.C I ~
0' I
n
~
UNIT (StUI
~
PROGRAMMA8LE I r-
0 IUS
EXPANSION ItO -<
.
iii"
IQ
DI
I
_ _ _ _ _ _ _ _ _ _ _ JI
31 L. -----.---- ----
INTERRUPTS
296163-2
inlef THE RUPITM·44 FAMILY
2.0 THE HOLC/SOLC PROTOCOLS • EFFICIENT: Well Defined Message-Level Opera-
tion
• RELIABLE: Frame Check Sequence and Frame
2.1 HOLC/SOLC Advantages over Numbering
Async
The SDLC reduces system complexity. HDLC/SDLC
The High Level Data Link Control, HDLC, is a stan- are "data transparent" protocols. Data transparency
dard communication link control established by the In- means that an arbitrary data stream can be sent with-
ternational Standards Organization (ISO). SDLC is a out concern that some of the data could be mistaken for
subset of HDLC. a protocol controller. Data transparency relieves the
communication controller having to detect special
HDLC and SDLC are both well recognized standard characters.
serial protocols. The Synchronous Data Link Control,
SDLC, is an IBM standard communication protocol. SDLC/HDLC provides more data throughout than
IBM originally developed SDLC to provide efficient, Async. SDLC/HDLC runs at Message-level Operation
reliable and simple communication between terminals which transmits multiple bytes within the frame,
and computers. whereas Async is based on character-level operation.
Async transmits or receives a character at a time. Since
The major advantages of SDLC/HDLC over Asyn- Async requires start and stop bits in every transmis-
chronous communications protocol (Async): sion, there is a considerable waste of overhead com-
• SIMPLE: Data Transparency pared to SDLC/HDLC.
I
i PRIMARY
J
8044 CONTROLLED
SECONDARY
296163-3
a) Point to Point, Half Duplex
i I PRIMARY I
I I 1 I
8044 CONTROLLED' 8044 CONTROLLED 8044 CONTROLLED
SECONDARY SECONDARY SECONDARY
2D6163-4
b) Multipoint. Half Duplex
~ h
PRIMARY
,
8044 CONTROLLED 8044 CONTROLLED
SECONDARY SECONDARY
t
8044 CONTROLLED 8044 CONTROLLED
SECONDARY I- SECONDARY,
296163-5
c) SDLC Loop Configuration
Fig~re 3. RUPITM·44 Supported Network Configurations
13-5
THE RUPITM-44 FAMILV
Due to SDLC/HDLC's well delineated field (see Fig- 2.3 Frames
ure 4) the CPU does not have to interpret character by
character to determine control field and information An HDLC/SDLC frame consists of five basic fields:
field. In the case of Async, CPU must look at each Flag, Address, Control, Data and Error Detection. A
character to interpret what it means. The practical ad- frame is bounded by flags-opening and closing flags.
vantage of such feature is straight forward use of DMA An address field is 8 bits wide in SDLC, extendable to 2
for information transfer. or more bytes in HDLC. The control field is also 8 bits
wide, extendable to two bytes in HDLC. The SDLC
In addition, SDLC/HDLC further improves Data data field or information field may be any number of
throughput using implied Acknowledgement of trans- bytes. The HDLC data field mayor may not be on an 8
ferred information. A station using SDLC/HDLC may bit boundary. A powerful error detection code called
acknowledge previously received information while Frame Check Sequence contains the calculated CR.C
transmitting different information in the same frame. (Cycle Redundancy Code) for all the bits between the
In addition, up to 7 messages may be outstanding be- flags. See Figure 4.
fore an acknowledgement is required.
In HDLC and SDLC are three types of frames; an In-
The HDLC/SDLC protocol can be used to realize reli- formation Frame is used to transfer data, a Supervisory
able data links. Reliable Data transmission is ensured a I Frame is used for control purposes, and a Nonse-
the bit level by sending a frame check sequence, cyclic quenced Frame is usedJor initialization and control of
redudancy checking, within the frame. Reliable frame the secondary stations.
transmission is ensured by sending a frame number
identification with each frame. This means that a re- For a more detailed discussion of higher level protocol
ceiver can sequentially count received frames and al functions interested readers may refer to the references
any time infer what the number of the next frame to be listed in Section 2.6.
received should be. More imporlant, it provides a
means for the receiver to identify to the sender some
particular frame that it wishes to have resent because of 2.4 Zero Bit Insertion
errors.
In data communications, it is desirable to transmit data
whieh can be of arbitrary content. Arbitrary data trans-
2.2 HOLC/SOLC Networks n1ission requires that the data field cannot contain
characters which are defined to assist the transmission
In both the HDLC and SDLC line proloeols a (Master) protocol (like opening flag in HDLC/SDLC communi-
. primary station eon trois the overalincllVork (data link) cations). This property is referred to as "data transpar-
and issues commands to the secondary (Slave) stations. ency". In HDLC/SDLC, this code transparency is
The latter complies with instructions ;lIld responds by made possible by Zero Hi t Insertion (ZBI).
sending appropriate responses. Whenever a transmit-
ting station must end transmission prematurely, it The flag has a unique bit pattern: 01111110 (7E HEX).
sends an abort character. Upon detecting an abort char- To eliminate the possibility of the data field containing
acter, a receiving station ignores the transmission block a 7E HEX pattern, a bit stuffing technique called Zero
called a frame. Bit Insertion is used. This technique specifies that dur-
ing transmission, a binary 0 be inserted by the transmit-
RUPI-44 supported HDLC/SDLC network configura- ter after any succession of five contiguous binary 1's.
tions are point to point (half duplex) multipoint (half This will ensure that no pattern of 0 1 1 1 1 I lOis ever
duplex), and loop. In the loop configuration the sta- transmitted between flags. On the receiving side, after
tions themselves act as repeaters, so that long links can receiving the flag, the receiver hardware automatically
be easily realized, see Figure 3. deletes any 0 following five consecutive l's. The 8044
performs zero bit insertion and deletion automatically.
OPENING ADDRESS CONTROL INFORMATION FRAME CHECK CLOSING
FLAG FIELD FIELD FIELD SEQUENCE (FCS) FLAG
VARIABLE LENGTH
01111110 BBITS BBITS (ONLY IN I FRAMES) 18 BITS 01111110
296163-6
Figure 4. Frame Format
13-6
inter THE RUPITM-44 FAMILY
2.5 Non-return to Zero Inverted (NR21)
NRZI is a method of clock and data encoding that is
well suited to the HDLC/SDLC protocol. It allows
HDLC/SDLC protocols to be used with low cost asyn-
chronous modems. NRZI coding is done at the trans-
mitter to enable clock recovery from the data at the
receiver terminal by using standard digital phase locked
loop (DPLL) techniques. NRZI coding specifies that
the signal condition does not change for transmitting a
I, while a 0 causes a change of state. NRZI coding
ensures that.an active data line will have a transition at
least every 5-bit times (recall Zero Bit Insertion), while
contiguous O's will cause a change of state. Thus, ZBI
and NRZI encoding makes it possible for the 8044's on-
chip DPLL to recover a receive clock (from received
data) synchronized to the received data and at the same
time ensure data transparency.
296163-7
2.6 References Figure 5. RUPITM-44 Development Support
Configuration Intellec® System, ICETM-44 Buffer
1. IBM Synchronous Data Link Control General Infor-
Box, and ICE-44 Module Plugged
mation GA27-3093-2 File No. GENL-09.
into a User Prototype Board
2. Standard Network Access Protocol Specification, DA-
TAPAC Trans-Canada Telephone System CCG111. A primary tool is the S044 In 9rcnit Emulator, called . .
3. IBM 3650 Retail Store System Loop Interface OEM ICE-44. See Figure 5. In conjunction with Intel's Intel-
Information, IBM, GA27-3098-0. lec® Microprocessor Development System. the ICE-44
4. Guidebook to Data Communications, Training Man- emulator allows hardware and software development to
ual, Hewlett-Packard 5955-1715. proceed interactively. This approach is more effective
than the traditional met hod of independenl hardware
5. "Serial Backplane Suits Multiprocessor Arcllitec- and software devel0Plllent followed hy syskm integra-
tures': Mike Webb, Computer Design, July 1984, pp. tion. With the ICE--14 lIloduIe, prototype hardware can
85-96. be added to the system as it is designed. Software and
6. "Serial Bus Simplifies Distributed Control': P.D. hardware integration occurs while the product is being
MacWilliams, Control Engineering, June 1984, pp. developed.
101-104.
7. "Chips Support Two Local Area Networks", Bob The ICE-44 emulator assists four stages 01' develop-
Dahlberg, Computer Design, May 1984, pp. 107-114. ment:
8. ''Build a VLSI-based Workstation for the Ethernet 1) Software Dcbugging
Environment", Mike Webb, EDN, 23 February 1984, It can be operated without being connected to the
pp. 297-307. user's system bel'ore any of t he user's hardware is
9. "Networking With the 8044': Young Sohn & Charles available. In this stage ICE-44 debugging capabilities
Gopen, Digital Design, May 1984, pp. 136-137. can be used in conjunction with the Intellcc text edi-
tor and 8044 macroassembler to facilitate program
development.
3.0 RUPITM·44 DESIGN SUPPORT 2) Hardware Development
The ICE-44 module's precise emulation characteris-
tics and full-speed program RAM make it a valuable
3.1 Design Tool Support tool for debugging hardware, including the time-crit-
ical SDLC serial port, parallel port, and timer inter-
A critical design consideration is time to market. Intel
faces.
provides a sophisticated set of design tools to speed
hardware and software development time of 8044 based
products. These include ICE-44, ASM-51, PL/M-51,
and EMV-44.
13-7
THE RUPITM-44 FAMILY
3) System Integration
Integration of software and hardware can begin
when any functional element of the user system
hardware is connected to the 8044 socket. As each
section of the user's hardware is completed, it is add-
ed to the prototype. Thus, each section of the hard-
ware and software is system tested in real-time oper-
ation as it becomes available.
4) System Test
When the user's prototype is complete, it is tested
with the final version of the user system software.
The ICE-44 module is then used for real-time emula-
tion of the 8044 to debug the system as a completed
unit.
The final product verification test may be performed
296163-8
using the 8744 EPROM version of the 8044 micro-
computer. Thus, the ICE-44 module provides the Figure 6. RUPI-44 iPDS Personal Development
user with the ability to debug a prototype or produc- System, EMV-44 Buffer Box, and EMV-44 Module
tion system at any stage in its development.
Plugged into a User Prototype Board
A conversion kit, ICE-44 CON, is available to upgrade
Integration, and System Test. The iPDS's rugged porta-
an ICE-Sl module to ICE-44.
bility and ease of use also make it an ideal system for
production tests and field service of your finished de-
Intel's ASM-Sl Assembler supports the 8044 special
sign. In addition, the iPDS offers EPROM program-
function registers and assembly program development.
ming module for the 8744, and direct communications
PL/M-Sl provides designers with a high level language
with the 8044-based BITBUS via an optional iSBX-344
for the 8044. Programming in PL/M can greatly re-
distributed control module.
duce development time, and ensure quick time to mar-
ket.
These tools have recently been expanded with the addi- 3.28051 Workshop
tion of the EMV-44CON. This conversion kit allows Intel provides 80S1 training to its customers through
you to convert an EMV-Sl into an EMV-44 emulation the S-day 80S1 workshop. Familiarity with the 80S1
vehicle. The resultant low cost emlliator is designed for and 8044 is achieved through a combination of lecture
use with an iPDS Personal Development System, which and laboratory exercises.
also supports the ASM-Sl assembler and PL/M-Sl. See
Figure 6. For designers not familiar with the 80S1, the workshop
is an clTective way to become proficient with the 80S 1
Emulation support is similar to the ICE-44 with sup- architecture and capabilities.
port for Software and Hardware Development, System
13-8
October 1988
8044 Architecture
Order Number: 296164-001
13-9
8044 ARCHITECTURE CONTENTS PAGE
GENERAL ............................. 13-11
1.0 MEMORY ORGANIZATION
OVERVIEW ...................... 13-11
1.1 Special Function Registers ...... 13-11
1.2 Interrupt Control Registers ...... 13-13
2.0 MEMORY ORGANIZATION
DETAILS ........................ 13-14
2.1 Operand Addressing ............ 13-15
2.2 Register Addressing ............ 13-16
2.3 Direct Addressing .............. , 13-16
3.0 RESET ............................. 13-18
4.0 RUPITM-44 FAMILY PIN
DESCRIPTION ................... 13-18
13-10
8044 ARCHITECTURE
GENERAL same byte as the opcode of an instruction. Thus, a large
number of instructions are one-byte instructions.
The 8044 is based on the 8051 core. The 8044 replaces
the 8051's serial port with an intelligent HDLC/SDLC The next higher 16 bytes of the internal RAM (loca-
controller called the Serial Interface or SIU. Thus the tions 20H through 2FH) have individually addressable
differences between the two result from the 8044's in- bits. These are provided for use as software flags or for
creased on-chip RAM (192 bytes) and additional spe- one-bit (Boolean) processing. This bit-addressing capa-
cial function registers necessary to control the SIU. bility is an important feature of the 8044. In addition to
Aside from the increased memory, the SIU itself, and the 128 individually addressable bits in RAM, twelve of
<iifferences in 5 pins (for the serial port), the 8044 and the Special Function Registers also have individually
8051 are compatible. addressable bits.
This chapter describes the differences between the H044 A memory map is shown in Figure 2.
and 8051. Information pertaining to the 8051 core, eg.
instruction set, port operation, EPROM programming,
etc. is located in the 8051 sections of this manual. 1.1 Special Function Registers
A block diagram of the 8044 is shown in Figure 1. The The Special Function Registers are as follows:
pinpoint is shown on the inside front cover. • ACC Accumulator (A Register)
B B Register
PSW Program Status Word
1.0 MEMORY ORGANIZATION SP Stack Pointer
OVERVIEW DPTR Data Pointer (consisting of DPH
AND DPL)
The 8044 maintains separate address spaces for Pro- PO Por[ 0
gram Memory and Data Memory. The Program Mem- PI Port I
ory can be up to 64K bytes long, of which the lowest P2 Port 2
4K bytes are in the on-chip ROM. P3 Port 3
IP In Ierrupt Priori Iy
If the EA pin is held high, the 8044 executes out of IE Interrupt Enable
internal ROM unlwess the Program Counter exceeds TMOD Timer/Counter Mode
OFFFH. Fetches from locations !OOOH through • TCON Timer/Counter Conlrol
FFFFH are directed to external Program Memory. THO Timer/Counter (J (high byte)
TLO Timer/Counter Il (low byte)
If the EA pin is held low, the 8044 fetches all instruc- THI Timer/Counler I (high byte)
tions from external Program Memory. TLl Timer/Coun"'!" I (low bYle)
SMD Serial Mode
The Data Memory consists of 192 bytes of on-chip STS Status/Comlll:lIHI
RAM, plus 35 Special Function Registers, in addition NSNR Send/Receive COlllII
to which the device is capable of accessing up to 64K STAD Station Address
bytes of external data memory. TIlS Transmit BulTer Slart Addres,;
TBL Transmit Bulrer Lcngth
The Program Memory uses 16-bit addresses. The exter- TCB Transmit Control Byte
nal Data Memory can use erither 8-bit or 16-bit ad- RBS Receive BufTcr Start Address
dresses. The internal Data Memory uses 8-bit address- RBL Receive Buffer Length
es, which provide a 256-location address space. The RFL Received Field Length
lower 192 addresses access the on-chip RAM. The Spe- RCB Received· Control Byte
cial Function Registers occupy various locations in the DMAcNT DMA Count
upper 128 bytes of the same address space. FIFO FIFO (three bytes)
SIUST SIU State Counter
The lowest 32 bytes in the internal RAM (locations 00 PCON . Power Control
through IFH) are divided into 4 banks of registers,
each bank consisting of 8 bytes. Anyone of these banks The registers marked with • are both byte- and bit-ad-
can be selected to be the "working registers'~' of the dressable.
CPU, and can be accessed by a 3-bit address in the
13-11
PSEN ~lE
i
CSC
10
TIMING '·5.0
I
PROGRAM
TIMER/ INTERRUPT MEMORY
,.---.. CPU COUNTERS INTI CONTROL
~
."
I RD.WR 1 TO. TI
..
INTO
ifi INTI
c
CD
(
I )-
0)
o.,..
.,..
:'"
»
.....
U)
.....
21
c:
'1J
':::j J 1 IJ 1 I 1J ::D
o
:z:
L
0 I:
til ADlRIIiO lI'- L..., :::j
I\J
0" rn
n ( PORT I~
PORT
2
SIU
HAROWARE
PORT
3
Ir- PORT c:=:)F o
lJI;' 0
REGISTERS [\0- 1 -I
~ C
C
::D
..
i»
IC
III
r'
INTERNAL
TWO PORT
DATA 51 f1
rn
3 RAM
( P3
ADOR/OATAIIiO
SClR
DATA
I/O
SlU
,1
RTS
CTS
296164-1
inter 8044 ARCHITECTURE
FFFF
FFFF
EXTERNAL
1000
.1
( 1
OFFF OFFF
/ \ OVERLAPPED
EXTERNAL
I " SPACE
INTERNAL
lEA 1) lEA 0)
~BOOFF .---------1 1 F~~~~:6LN
FlI (liSTERS
I
INIERNAL
1
DA fA RAM 0000 L -_ _ _ _- '
0000 0000
, ~ ________~y~---------JI .
•
J
Y EXTERNAL
PROGRAM MEMORY INTERNAL DATA
DATAMEMOHY MEMmw
296164-2
Figure 2. RUPITM-44 Memory Map
Stack Pointer External Interrupt control bits ITO and ITI arc in
TCON.O and TCON.2, respectively. Reset leaves all
The Stack Pointer is S bits wide. The stack can reside flags inactive, with ITO and ITI cleared.
anywhere in the 192 bytes of on-chip RAM. When the
S044 is reset, the stack pointer is initialized to 07H. All the interrupt !lags can be set or cleared by software,
When executing a PUSH or a CALL, the stack pointer with the same dYed as by hardware.
is incremented before data is stored, so the stack would
begin at location OSH. The Enable and Priority Control Registers arc showll
below. All of thesc control bits arc set or cleared hy
software. All arc cleared by reset.
1.2 Interrupt Control Registers
The Interrupt Request Flags are as listed below: IE: Interrupt Enable Register (bit-addressable)
Bit: 7 6 5 4 3 2 0
Source Request Flag Location
I I
EA X X ES ET1 EX1 ETO EXO
External Interrupt ° lEO,
INTO, if ITO = °
if ITO = I
P3.2
TCON.l where:
Timer °Overflow TFO TCON.5
eEA disables all interrupts. If EA = 0, no interrupt
will be acknowledged. If EA = I, each inter-
External Interrupt I INTl, if ITl =
lEI, if ITl = I
° P3.3
TCON.3
rupt source is individually enabled or disabled
by setting or clearing its enable bit.
enables or disables the Serial Interface Unit in-
Timer 1 Overflow TFI TCON.7 terrupt. If ES = 0, the Serial Interface Unit
interrupt is disabled.
Serial Interface Unit SI STS.4 enables or disables the Timer 1 Overflow inter-
rupt. If ETl = 0, the Timer I interrupt is
disabled.
13-13
infef 8044 ARCHITECTURE
• EX! enables or disables External Interrupt 1. If all Program Memory fetches arc from external memo-
EX! = 0, External Interrupt ! is disabled. ry. The execution speed of the 8044 is the same regard-
• ETO enables or disables the Timer 0 Overflo~ inter- less of whether fetches arc from internal or external
rupt. If ETO = 0, the Timer 0 interrupt is Program Memory. If all program storage is on-chip,
disabled. byte location 4095 should be left vacant to prevent an
undesired prefetch from external Program Memory ad-
dress 4096.
IP: Interrupt Priority Register (bit-addressable)
Bit: 765 4 3 2 o Certain locations in Program Memory are reserved for
specific programs. Locations 0000 through 0002 are re-
x x·Ix PS I PT1 PX1PTO PXO served for the initialization program. Following reset,
the CPU always begins execution at location 0000. Lo-
where: cations 0003 through 0042 are reserved for the five in-
defines the Serial Interface Unit interrupt pri- terrupt-request service programs. Each resource that
• PS can request an interrupt requires that its service pro-
ority level. PS =! programs it to the higher
priority level. gram be stored at its reserved location.
defmes the Timer I interrupt priority level. The 64K-byte External Data Memory address space is
PT! = I 'programs it to the higher priority automatically accessed when the MOVX instruction is
level. executed.
• PX! defines the External Interrupt priority level.
PXI = ! programs it to the higher priority Functionally the Internal Data Memory is the most
level. flexible ofthe address spaces. The Internal Data Mem-
• PTO defines the Timer 0 interrupt priority level. ory space is subdivided into a 256-hyte Internal Data
PTO = ! programs it to the higher priority RAM address space and a 128-byte Special Funetiori
level. . Register address space as shown in Figure 3.
• PXO defines the External Interrupt o priority level. SPECIAL
PXO = I programs it to t he higher priority FUNCTION
REGISTERS
level. ~
i55 255 248 FBII
FOfl
EBH
'0
2.0 MEMORY ORGANIZATION EOfi
DBH
DETAILS RAM DOH
ADDRESS·
,.--"----0. CBH
ABLE
~~~
In the 8044 family the memory is organized over three BITS IN
SFR.
address_spaces 'and the program COlllltcr. The memory 191 DOH (128 BITS)
spaces shown in Figure 2are the: • AOH
AOH
• 64K-byte Program Memory address space 99H
90H
• 64K-byte .External Data Memory address space 88H
-=~12=B~I~3:::.5_1::::2::.18 80H
• 320-byte Internal Data Memory address space 127 ,..
The !6-bit Program Counter register provides the 8044
with its 64K addressing capabilities. The Program ~~~~ESS. !! "'12""7-""12:::10
BITS IN
Counter allows the user to execute calls and branches SFR. 32 7 0
(128 BITS) - R7
to any' location within the Program Memory space. 24 RO BANK3
There are no instructions that permit program execu- - R7 BANK2
tion to move from the Program Memory space to any REGISTERS
:!! RO
of the data memory spaces. 8 :~ BANKI
- R7
..! RO BANKO
In the 8044 and 8744 the lower.4K of the 64K Program
Memory address. space is filled by internal ROM and INTERNAL SPECIAL FUNCTION
EPROM, respectively. By tying the EA. pin high, the DATA RAM' REGISTERS
processor can be forced to fetch from the internal 296164-3
ROM/EPROM for Program Memory addresses 0
through 4K. Bus expansion for accessing Program Figure 3. Internal Data Memory Address Space
Memory beyond 4K is automatic since external instruc-
tion fetches occur automatically when the Program
Counter increases above 4095. If the EA pin is tied low
13-14
8044 ARCHITECTURE
The Internal Data RAM address space is 0 to 255. access the SFR's. The SFR's at addresses 192-255 are
Four 8-Register Banks occupy locations 0 through 31. also accessed using direct addressing. The Special
The stack can be located anywhere in the Internal Data Function Registers are listed in Figure 4. Their map-
RAM address space. In addition, 128 bit locations of ping in the Special Function Register address space is
the on-chip RAM are accessible through Direct Ad- shown in Figures 5 and 6.
dressing. These bits reside in Internal Data RAM at
byte locations 32 through 47. Currently locations 0 Performing a read from a location of the Internal Data
through 191 of the Internal Data RAM address space memory where neither a byte of Internal Data RAM
are filled with on-chip RAM. (i.e., RAM addresses 192-255) nor a Special Function
Register exists will access data of indeterminable value.
The stack depth is limited only by the available Internal
Data RAM, thanks to an 8-bit reloadable Stack Point- Architecturally, each memory space is a linear se-
er. The stack is used for storing the Program Counter quence of 8-bit wide bytes. By Intel convention the
during subroutine calls and may be used for passing storage of multi-byte address and data operands in pro-
parameters. Any byte of Internal Data RAM or Special gram and data memories is the least significant byte at
Function Register accessible though Direct Addressing the low-order address and the most significant byte at
can be pushed/popped. t he high-order address. Within byte X, the most signifi-
cant bit is represented by X. 7 while the least significant
The Special Function Register address space is 128 to hit is X.O. Any deviation from these conventions will be
255. All registers except the Program Counter and the explicitly stated in the text.
four 8-Register Banks reside here. Memory mapping
the Special Function Registers allows them to be ac·
cessed as easily as internal RAM. As such, they can be 2.1 Operand Addressing
operated on by most instructions. In the overlapping
memory space (address 128-191), indirect addressing is There are five methods of addressing source operands.
used to access RAM, and direct addressing is used to They are Register Addressing, Direct Addressing,
Register-Indirect Addressing, Iml1lediate Addressing
ARITHMETIC REGISTERS: ARITHMETIC REGISTERS:
Accumulator', B register*, Accumulator*, B register',
Program Status Word' Program Status Word*
POINTERS: POINTERS:
Stack Pointer, Data Pointer (high & low) Stack Pointer, Data Pointer (high & lllw)
PARALLEL I/O PORTS: PARALLEL I/O PORTS:
Port 3*, Port 2*, Port 1*, Port 0' Port 3*, Port r, Port 1*, Pllrt 0+
INTERRUPT SYSTEM: INTERRUPT SYSTEM:
Interrupt Priority Control*, Interrupt Priority Control',
Interrupt Enable Control * Interrupt Enable Control'
TIMERS: TIMERS:
Timer Mode, Timer Control', Timer 1 Timer Mode, Timer Control', Timer 1
(high & low), Timer 0 (high & low) (high & low), Timer 0 (high & low)
.SERIAL INTERFACE UNIT: SERIAL INTERFACE UNIT:
Transmit Buffer Start, Serial Mode, Status/Command',
Transmit Buffer Length, Send/Receive Count', Station Address,
Transmit Control Byte, Transmit Buffer Start Address,
Send Count Receive Count', Transmit Buffer Length,
DMA Count, Transmit Control Byte,
Station Address Receive Buffer Start Address,
Receive Field Length' Receive Buffer Length,
. Receive Buffer Start Receive Field Length,
Receive Buffer Length Receive Control Byte,
Receive Control Byte, DMA Count,
Serial Mode, FIFO (three bytes),
Status Register. * SIU Controller State Counter
'Bits in these registers are bit addressable. 'Bits in these registers are bit-addressable.
Figure 4. Special Function Registers Figure 5. Mapping of Special Function Registers
13-15
intJ 8044 ARCHITECTURE
and Base-Register-plus Index-Register-Indirect Ad- 2.2 Register Addressing
dressing. The first three of these methods can also be
used to address a destination operand. Since operations Register Addressing permits access to the eight regis-
in the 8044 require 0 (Nap only), I, 2, 3 or 4 operands, ters (R7-RO) of the selected Register Bank (RB). One of
these five addressing methods are used in combinations the four 8-Registcr Banks is selected by a two-bit field
to provide the 8044 with its 21 addressing modes. in the PSW. The registers may also be accessed through
Direct Addressing and Register-Indirect Addressing,
Most instructions have a "destination, source" field since the four Register Banks are mapped into the low-
that specifies the data type, addressing methods and est 32 bytes of internal Data RAM as shown in Figures
operands involved. For operations other than moves, 9 and 10. Other Internal Data Memory locations that
the destination operand is also a source operand. For are addressed as registers are A, B, C, AB and DPTR.
example, in "subtract-with-borrow A,#5" the A regis-
ter receives the result of the value in register A minus 5,
minus C. 2.3 Direct Addressing
Most operations involve operands that are located in Direct Addressing provides the only means of accessing
Internal Data Memory. The selection of the Program the memory-mapped byte-wide Special Function Regis-
Memory space or External Data Memory space for a ters and memory mapped bits within the Special Func-
second operand is determined by the operation mnc- tion Registers and Internal Data RAM. Direct Ad-
monic unless it is an immediate operand. The subset of dressing of bytes may also be used to access the lower
the Internal Data Memory being addressed is deter- 128 bytes of Internal Data RAM. Direct Addressing of
mined by the addressing method and address value. For bits gains access to a 128 bit subset of the Special Func-
example, the Special Function Registers can be ac- tion Registers as shown in Figurcs 5, 6, 9, and 10.
cessed only through Direct Addressing with an address
of 128-255. A summary of the operand addressing
methods is shown in Figure 6. The following para-
graphs describe the five addressine methods.
SYMBOLIC BYTE
REGISTER NAMES ADDRESS BIT ADDRESS ADDRESS
~ -----,
,~
B REGISTER B 247 through 240 (FOH)
ACCUMULATOR ACC 231 through 224 (EOH)
"THRE( BYTE FIFO' FIFO .,- 223 (DFH)
FIFO 222 (DEH)
FIFO "- 221 (DOH)
TRANSMIT BUFFER START TBS 220 (DCH)
TRANSMIT BUFFER LENGTH TDL 219 (DBH)
TRANSMIT CONTROL BYTE TCB 218 (DAH)
"SIU STATE COUNTER SIUST 217 (D9H)
SEND COUNT RECEIVE COUNT NSNR 223 .hrough 116 216 (D8H)
PROGRAM STATUS WORD PSW 215 Iftraugh 208 208 (DOH)
"DMA COUNT DMA CNT 207 (CFH)
STATION ADDRESS STAD 206 (CEH)
RECEIVE FIELD LENGTH RFL 205 (CDH)
RECEIVE BUFFER START RDS 204 (CCH)
RECEIVE BUFFER LENGTH RBL 203 (CBH) SFR's CONTAINING
RECEIVE CONTROL BYTE RCB 202 (CAH) DIRECT ADDRESSABLE BITS
SERIAL MODE SMD 201 (C9H)
STATUS REGISTER STS 'hl'OUGh 200 (CBH)
INTERRUPT PRIORITY CONTROL IP 184 (B8H)
*
PORT 3 P3 I- 176 (BOH)
INTERRUPT ENABLE CONTROL IE
l- 168 (ABH)
I- 160 (AOH)
PORT 2 P2
PORT 1 PI 'hl'OUGh 144 (90H)
TIMER HIGH 1 THI 141 (8DH)
TIMER HIGH 0 THO 140 (8CH)
TIMER LOW 1 TL1 139 (8BH)
TIMER LOW 0 TLO 138 (8AH)
TIMER MODE TMOD 137 (89H)
TIMER CONTROL TCON 143 throuah ~. 136 (88H)
DATA POINTER HIGH DPH 131 (83H)
DATA POINTER LOW DPL 130 (82H)
STACK POINTER SP 129 (81H)
PORTO PO 128 128 (80H)
296164-4
Figure 6" Mapping of Special Function Registers
13-16
inter 8044 ARCHITECTURE
Direct BilAddress Hardware
• Register Addressing
Byte Register" R7-RO
Address (MSB) (LSB) Symbol
A, B, C (bit), AB (two bytes), DPTR (double
240 F7 I F6 I F5 I F4 I F3 I F2 I F1 I FO byte)
• Direct Addressing
224 E7 I E6 I E5 I E4 I E3 I E2 I El I EO ACC
NS2 NS1 NSO SES NR2 NRI NRO SER
Lower 128 bytes of Internal Data RAM
216 OF I OE I 00 I OC I OB I OA I 09 I OB NSNR Special Function Registers
CY AC FO RS1 RSO OV P 128 bits in subset of Special Function Register
204 07 I 06 I 05 I 04 I 03 I 02 I 01 I DO PSW address space
TBF RE RTS SI BV CPB AM RBP
200 CF I CE I CO I cc I C[J I CA I C9 I CB, STS
• Register-Indirect Addressing
PS I'TI PXl PTO PXO Internal Data RAM [@Rl, @RO, @SP (PUSH
184 - I - I - I [Je I 8B I BA I B9 I BB 1P and,POP only)]
Least Significant Nibbles in Internal Data
176 87 I 86 I B5 I B4 I 83 I 82 I 81 I BO RAM (@Rl, @RO)
EA E5 ET1 EX1 ETO EXO
168 AF I - I - I AC I AB I AA I A9 I A8 1E
External Data Memory (@RI, @RO, @DPTR)
o Immediate Addressing
160 A7 I A6 I A5 I A4 I A3 I A2 I A1 I AO P2
- Program Memory (in-code constant)
144 97~96J95J94J 93192.191 190 PI • Base-Register-plus Index-Rc!\ister-Indireet Ad-
TFI TR1 TFO TRO IE1 IT1 lEO ITO dressing
136 8F I 8E I 80 I 8C I 8B I 8A I 89 I 88 TCON Program Melllory (@ DPTR -I- A, @ PC + A)
I 86 I I I I I I Figure 8. Operand Addressing Methods
III
128 87 85 84 83 82 81 80 PO
SPECIAL
FUNCIION
REGI~" US,
255 FIlIt~
248
24. '" '" FOII~
lllll~
m
'24 ,
lOti.
'16 , )111 . .
["'0
'08 ,
'00
192
184
176
168
: : . .,
:1114
, :J~~gn
I
,lott...
Alit,.
DIRECT
IDIT~l
INDIREC 180 AOH ...
ADOREsrG~ ,..
152 IIH ...
OOH ...
136 IOH ...
128 135
127
, , '" IIIH'"
~
DIRECT 121 120
ADDRESSING
(8ITS)
..!!
, •
R'
BANK 3
.!!. R•
A7 BANK 2
REGISTER .1! R•
ADDRESSING A'
..!. A. BANK 1
Al BANK 0
R.
J!.
~
~ DIRECT ADORESSING
STACK-POINTER REGISTER-INDIRECT AND
REGISTER-INDIRECT ADDRESSING
296164-6
Figure 10. Addressing Operands
in Internal Data Memory
intJ 8044 ARCHITECTURE
Register-Indirect Addressing using the content of RI TBS OOH
or RO in the selected Register Bank, or using the con- TBl OOH
tent of the Stack Pointer (PUSH and POP only), ad- TCB OOH
dresses the Internal Data RAM. Register-Indirect Ad- RBS OOH
dressing is also used for accessing the External Data
RBl OOH
Memory. In this case, either RI or RO in the selected
Register Bank may be used for accessing locations RFl OOH
within a 256-byte block. The block number can be pre- RCB OOH
selected by the contents of a port. The 16-bit Data DMACNT OOH
Pointer may be used for accessing any location within FIF01 OOH
the full 64K external address space. " FIF02 OOH
FIF03 OOH
SIUST 01H
3.0 RESET PCON (OXXXXXXX)
Reset is accomplished by holding the RST pin high for
The internal RAM is not affected by reset. When VCC
at least two machine cycles (24 oscillator periods) while
is turned on, the RAM content is indeterminate unless
the oscillator is running. The CPU responds by execut-
VPD was applied prior to VCC being turned off (see
jng an "internal reset. It also configures the ALE and
Power Down Operation.)
PSEN pins as inputs. (They are quasi-bidirectional.)
The internal reset is executed during the second cycle in
which RST is high and is repeated every cycle until
RST goes low. It leaves the internal registers as follows: 4.0 RUPITM-44 FAMILY PIN
Register Content DESCRIPTION
PC OOOOH VSS: Circuit ground potential.
A OOH
B OOH vce: Supply voltage during programming (of the
PSW OOH 8744), verification (of the 8044 or 8744), and normal
SP 07H operation.
DPTR OOOOH
PO-P3 OFFH Port 0: Port 0 is an 8-bit open drain bidirectional 1/0
IP (XXXOOOOO) port. It is also the multiplexed low-order address and
data bus during accessses to external memory (during
IE (OXXOOOOO) which accesses it activates internal pullups). It also out-
TMOD OOH puts instruction bytes during program verification. (Ex-
TCON OOH ternal pullups are required during program verifi-
THO OOH cation.) Port 0 can sink eight LS TTL inputs.
TlO OOH
TH1 OOH Port 1: Port I is an 8-bit bidirectional 1/0 port with
Tl1 OOH internal pu1luj>s. It receives the low-order address byte
SMD OOH during program verification in the 8044 or 8744. Port I
STS OOH can sinklsource four LS TTL inputs, It can drive MOS
inputs without external pullups."
NSNR OOH
STAD OOH Two of the Port pins serve alternate functions, as
listed below:
Port Pin Alternate Function
P1.6 RTS (Request to Send). In a non-loop configu-
ration, RTS signals that the 8044 is ready to
transmit data.
13-18
October 1988
The RUPITM -44
Serial Interface Unit
Order Number: 296165-001
13-19
THE RUPITM-44 SERIAL CONTENTS PAGE
INTERFACE UNIT 1.0 DATA LINK CONFIGURATIONS ... 13-21
2.0 DATA CLOCKING OPTIONS ...... 13-21
3.0 DATA RATES ....................... 13-21
4.0 OPERATIONAL MODES ........... 13-24
4.1 AUTO Mode .................... 13-24
4.2 FLEXIBLE Mode ................ 13-27
5.0 8044 FRAME FORMAT
OPTIONS ........................ 13-27
5.1 Standard SDLC Format ......... 13-27
5.2 No Control Field
(Non-Buffered Mode) ......... 13-27
5.3 No Control Field and No Address
Field ......................... 13-27
5.4 No FCS Field ................... 13-28
6.0 HLDC .............................. 13-29
7.0 SIU SPECIAL FUNCTION
REGISTERS ..................... 13-29
7.1 Control and Status Registers .... 13-29
7.2 Parameter Registers ............ 13-30
7.3 ICESupport Registers .......... 13-31
8.0 OPERATION ....................... 13-33
8.1 Initialization ..................... 13·33
8.2 AUTO Mode .................... 13-34
8.3 FLEXIBLE Mode ................ 13-34
8.4 8044 Data Link Particulars ...... 13·34
8.5 Turn Around Timing ............. 13-34
9.0 MORE DETAILS ON SIU
HARDWARE ..................... 13-51
9.1 The Bit Processor ............... 13-51
9.2 The Byte Processor ............. 13-51
10.0 DIAGNOSTiCS ................... 13-53
13-20
inter THE RUPITM·44 SERIAL INTERFACE UNIT
SERIAL INTERFACE Externally Clocked Mode
The serial interface provides a high-performance com- In the externally clocked mode, a common Serial Data
munication link. The protocol used for this communi- Clock (SCLK on pin \5) synchronizes the serial bit
cation is based on the IBM Synchronous Data Link stream. This clock signal may come from the master
Control (SDLC). The serial interface also supports a CPU or primary station, or from an external phase-
subset of the ISO HDLC (International Standards Or- locked loop local to the 8044. Figure 3 illustrates the
ganization High-Level Data Link Control) protocol. timing relationships for the serial interface signals when
the externally clocked mode is used in point-to-point
The SDLC/HDLC protocols have been accepted· as and multipoint data link configurations.
standard protocols for many high-level teleprocessing
systems. The serial interface performs many of the Incoming data is sampled at the rising edge of SCLK,
functions required to service the data link without in- and outgoing data is shifted out at the falling edge of
tervention from the 8044's own CPU. The progra~mer SCLK. More detailed timing information is given in the
is free to concentrate on the 8044's function as a periph- 8044 data sheet.
eral controller, rather than having to deal with the de-
tails of the communication process.
Self Clocked (Asynchronous) Mode
Five pins on the 8044 are involved with the serial inter-
face: The self clocked mode allows data transfer without a
common system data clock. Using an on-chip DPLL
Pin 7 RTS/PI6
(digital phase locked loop) the serial interface recovers
Pin 8 CTS/PI7 the data clock froIll the data stream itself. The DPLL
Pin 10 I10/RXD/P30 requires a reference clock equal to either 16 times or 32
times the data rak. This reference clock may be exter-
Pin II DATA/TXD/P31
nally supplied or internally generated ..When the serial
Pin 15 SCLK/Tl//P35 interface generates Ihis clock internally, it uses either
the 8044's internal I, 'I',ic clock (half t he crystal frequen-
Figure I is a functional block diagram of the serial in- cy's PH2) or the "tilner 1" overflow. Figure 4 shows
terface unit (SIU). More details on the SIU hardware the serial interface signal timing n,lationships for the
are given later in this chapter. loop configuration, when the unc10ckcd mode is used.
The DPLL monitors the received data in order to de-
1.0 DATA LINK CONFIGURATIONS rive a data clock thai is centered 0" Ihe received bits.
Centering is achieved by detecting :lil transitions of the
The serial interface is capable of operating in three seri- received data, and then adjusting tit" dock transition
al data link configurations: (in increments of 1/", bit period) IowaI'd the center of
I) Half-Duplex, point-to-point the received bit. The DPLL COI1VCf/',CS to the nominal
2) Half-Duplex, multipoint (with a half-duplex or fu11- bit center within eil'.ht bit transitions, worst case.
duplex primary)
To aid in the phase locked loop capture process, the
3) Loop 8044 has a NRZI (non-return-to-zero inverted) data en-
coding and decoding option. NRZI coding specifies
Figure.2 shows these three configurations. The R TS that a signal does not change state for a transmitted
(Request to Send) and CTS (Clear to Send) hand-shak- binary 1, but does change state for a binary O. Using the
ing signals are available in the point-to-point and multi- NRZI coding with zero-bit insertion, it can be guaran-
point configurations. teed that an active signal line undergoes a transition at
least every six bit times.
2.0 DATA CLOCKING OPTIONS
The serial interface can operate in an externally clocked
3.0 DATA RATES
mode or in a self clocked mode. . The maximum data rate in the externally clocked mode
is 2.4M bits per second (bps) a half-duplex configura-
tion, and 1.0M in a loop configuration.
13-21
(
BIT PROCESSOR BYTE PROCESSOR
SYNCHRONIZED
"
DIGITAL
PHASE
LOCK
LOOP
RXD~ .1 CONTROL
-I
:J:
ITI
::JJ
C
"'1'1 't:I
..
Q
c ~
~ TXD
J,..
S/UST ~
:-"
en
... (Jj
E
ITI
::JJ
C.:>
N ID :;
I\J 0" r-
0
~
c z
-I
iii' ITI
IQ ::JJ
iil
3 ~
(')
ITI
C
Z
::::j
SIU
HARDWARE
INTERNAL REGISTER
TWO (2 PORT)
PORT
RAM
lB
296165-1
THE RUPITM-44 SERIAL INTERFACE UNIT
8044
MASTER!
CONTROLLED
PRIMARY
SECONDARY
296165-2
1) HALF-DUPLEX, POINT-TO-POINT
MASTER!
PRIMARY -
! l
8044 8044
CONTROLLED CONTROLLED
SECONDARY SECONDARY
296165-3
2) HALF-DUPLEX, MULTIPOINT
MASTI'R!
II
PRIMARY
8044 8044
CONTROLLED CONTROLLED
SECONDARY SECONDARY
8044
CONTROLLED
SECONDARY
296165-4
3) LOOP
Figure 2. RlIPI-44 Data Link Configurations
13-23
THE RUPITM·44 SERIAL INTERFACE UNIT
In the self clocked mode with an external reference 4.1 AUTO Mode
clock, the maximum data rate is 375K bps.
To enable the SIU to receive a frame in AUTO mode,
In the self clocked mode with an internally generated the 8044 CPU sets up a receive buffer. This is done by
reference clock, and the 8044 operating with a 12 MHz writing two registers-Receive Buffer Start (RBS) Ad-
crystal, the available data rates are 244 bps to 62.5K dress and Receive Buffer Length (RBL).
bps, 187.5K bps and 375K bps.
The SIU receives the frame, examines the control byte,
For more details see the table in the SMO register de- and takes the appropriate action. If the frame is an
scription, below. information frame, the SIU will load the receive buffer,
interrupt the CPU (to have the receive buffer read), and
make the required acknowledgement to the primary
4.0 OPERATIONAL MODES station. Details on these processes are given in the Op-
eration section, below.
The Serial Interface Unit (SIU) can operate in either of
two reSponse modes: In addition to receiving the information frames, the
SIU in AUTO mode is capable of responding to the
1) AUTO mode iilllowing commands (found in the control field of su-
2) FLEXIBLE (NON-AUTO) mode pervisory frames) from the primary station:
In the AUTO mode, the SIU performs in hardware a RR (Receive Ready): Acknowledges that the Primary
subset of the SOLC protocol called the normal re- station has correctly received numbered frames up
sponse mode. The AUTO mode enables the SIU to rec- through NR - 1, and that it is ready to receive frame
ognize and respond to certain kinds of SOLC frames NR·
without intervention from the 8044's CPU. AUTO
mode provides a faster turnaround time and a simpli- HNR (Receive Not Ready): Indicates a temporary busy
fied software interface, whereas NON-AUTO mode condition (at the primary station) due to buffering or
provides a greater flexibility with regard to the kinds of ot her internal constraints. The quantity NR in the con-
operation permitted. t rol field indicates the number of the frame expected
after the busy condition ends, and may be used to ac-
In AUTO mode, the 8044 can act only as a normal knowledge the correct reception of the frames up
response mode secondary station-that is, it can trans- through NR - I.
mit only when instructed to do so hy the primary sta-
tion. All sllch AUTO mode responses adhere strictly to R EJ (Reject): Acknowledges the correct reception of
IBM's SDLC definitions. frames up through N R -- I, and requests transmission
or retransmission starting at frame NR. The 8044 is
In the FLEXlIlLE mode, reception or transmission of capable of retransmitting at most the previous frame,
each frame by the SIU is performed under the control and then only if it is still available in the transmit buff-
of the CPU. In this mode the 8044 can be either a er.
primary station or a secondary station.
UP (Unnumbered Poll): Also called NSP (Non-Se-
In both AUTO and FLEXIBLE modes, short frames, quenced Poll) or ORP (Optional Response Poll). This
aborted frames, or frames which have had CRC's are command is used in the loop configuration.
ignored by the SIU.
To enable the SIU to transmit an information frame in
The basic format of an SDLC frame is as follows: AUTO mode, the CPU sets up a transmit buffer. This
is done by writing two registers-Transmit Buffer Start
(TBS) Address and Transmit Buffer Length (TBL), and
! Flag! Address! Control !Information ! FCS ! Flag I filling the transmit buffer with the information to be
transmitted.
Format variations consist of omitting one or more of
the fields in the SDLC frame. For example, a superviso- When the transmit buffer is full, the SIU can automati-
ry frame is formed by omitting the information field. cally (without CPU intervention) send an information
Supervisory frames are used to confirm received frame (I-frame) with the appropriate sequence num-
frames, indicate ready or busy conditions, and to report bers, when the data link becomes available (when the
errors. More details on frame formats are given in the 8044 is polled for information). After the SIU has
SDLC Frame Format Options section, below. transmitted the I-frame, it waits for acknowledgement
from the receiving station. If the acknowledgement is
13-24
inter THE RUPITM-44 SERIAL INTERFACE UNIT
negative, the SIU retransmits the frame. If the ac- CPU, to indicate that the transmit buffer may be re-
knowledgement is positive, the SIU interrupts the loaded with new information.
\J
RTs 7
CTS
TRANSCEIVER/BUFFER 8
1/6 . 8044
10
~
-
I) DATA
11
<J
SCLK
15
296165-5
DATA RECEIVE DATA lfMITDTA RECEIVE DATA XMIT RECEIVE
/
1;15
- 1\ J '7
m
- \
\\
- n
.t=-.. ]
II
ffi
- /
TiIANSMIT
AIIORTEDBV
d'5-1
296165-6
Figure 3. Serial Interface Timing-Clocked Mode
13-25
l
8044
"TI RXD
ca'r::: 10
-I
Cil ::J:
p. TXO m
11 JJ
(IJ
~
::!,
c:
!!!.
S'
....
16X/32X
15
"~•
~
~
~
::l
AI (A
~
()
III m
c.> -I
296165-7 JJ
r\,
3" :;
0>
S' r-
(Q
Z
~ -I
m
[." X X X X
III JJ
:;: DATA GA ONE'S SHUT-OFF SEQ DATA
(')
o ~
0' 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 o
()
~
m
~ c:
Co
iii:
z
::::j
[~,
0
Co OATA (BIT-DELAYED) GA CHANGED TO FLAG TRANSMIT FRAME DATA (BIT-DELAYED)
III
0 1 1 1 0 1 1 1 1 0 1 0 1 1 1 1 a A D 0 R E S S CON T R 0 L
TRANSMISSION
ABORTED BY
EXTRA "1" SHUT-OFF
INSERTED SEQUENCE
296165-8
inter THE RUPITM-44 SERIAL INTERFACE UNIT
In addition to transmitting the information frames, the SMD Bit 1: NB (Non-Buffered Mode-No Control
SIU in AUTO mode is capable of sending the following Field)
responses to the primary station: STS Bit 1: AM (AUTO Mode or Addressed Mode)
RR (Receive Ready): Acknowledges that the 8044 has Figure 5 shows how these three bits control the frame
correctly received numbered frames up through format.
NR - 1, and that it is ready to receive frame NR.
The following paragraphs discuss some properties of
RNR (Receive Not Ready): Indicates a temporary busy the standard SDLC format, and the significance of
condition (at the 8044) due to buffering or other inter- omitting some of the fields.
nal constraints. The quantity NR in the control field
indicates the number of the frame expected after the
busy condition ends, and acknowledges till: correct re- 5.1 Standard SOLe Format
ception of the frames up through NR .... I.
The standard SDLC format consists of an opening flag,
an 8-bit address field, an 8-bit control field, an n-byte
4.2 FLEXIBLE Mode information field, a 16-bit Frame Check Sequence
(FCS), and a closing flag. The FCS is based on the
In the FLEXIBLE (or non-auto) 1II0de, all reception CCITT-CRC polynominal (X16 + X12 + X5 + 1).
and transmission is under the conll'lll or the CPU. The The address and control fields may not be extended.
full SDLC and HDLC protocob l'an he implemented, Within the 8044, the address field is held in the Station
as well as any bit-synchronous variants of these proto- Address (STAD) register, and the control field is held
cols. in the Receive Control Byte (RCB) or Transmit Con-
tml Byte (TCB) register. The standard SDLC format
FLEXIBLE mode provides nmr" l1exibility than lIIay be used in eilher AUTO mode or FLEXIBLE
AUTO mode, but it requires lII(lI'l: ('I'U overhead, and mode.
much longer recognition and response times. This is
'especially true when the CPU is sCl'vidng an interrupt
that has higher priority than the inlerrupts from the 5.2 No Control Field (Non-Buffered
SIU. Mode)
In FLEXIBLE mode, when the Sl U receives a frame, it When the control lield is not present, Ihe RCB and
interrupts the CPU. The CPU then reads the control TCB registers arc not used. The inform at ion field be-
byte from the Receive Control Byte (ReB) register. If gins immediately after the address field, or, if the ad-
the received frame is an information frame, the CPU dress field is also ab.,ent, immediately aft,:1' Ihe opening
also reads the information from the receive buffer, ac- flag. The cntire inli>nnation field is stored in the 8044's
cording to the values in the Receive Buffer Start (RBS) on-chip RAM. If Ihere is no control field, FLEXIBLE
address register and the Received Field Length (RFL) mode must be med. Control infi.lfInalion may, of
register. course, be prescnt in the information tield, and in this
manner the No Control Field option may be used for
In FLEXIBLE mode, the 8044 can initiate transmis- implementing extended control fields.
sions without being polled, and thus it can act as the
primary station. To initiate transmission or to generate 5.3 No Control Field and No Address
a response, the CPU sets up and enables the SIlJ. The
SIU then formats and transmits the desired frame.
Field
Upon completion of the transmission, without waiting The No Address Field option is available only in con-
for a positive acknowledgement from the receiving sta- juction with the No Control Field option. The STAD,
tion, the SIU interrupts the CPU. RCB, and TCB registers are not used. When both these
fields are absent, the information field begins immedi-
ately after the opening flag. The entire information field
5.0 8044 FRAME FORMAT OPTIONS is stored in on-chip RAM. FLEXIBLE mode must be
used. Formats without an address field have the follow-
As mentioned above, variations on the basic. SDLC ing applications:
frame consist of omitting one or more of the fields. The
choice of which fields to omit, as well as the selection of Point-to-point data links (where no addressing is neces-
AUTO mode versus FLEXIBLE mode, is specified by sary)
the settings of the following three bits in the Serial
Mode Register (SMD) and the Status/Control Register Monitoring line activity (receiving all messages regard-
(STS): less of the address' field)
SMD Bit 0: NFCS (No Frame Check Sequence) Extended addressing
13-27
infef THE RUPITM·44 SERIAL INTERFACE UNIT
FRAME OPTION NFCS NB AM FRAME FORMAT
Standard SOLC o o o F A C FCS F
FLEXIBLE Mode
Standard SOLC o o F A C FCS F
AUTO Mode
No Control Field o F A FCS F
FLEXIBLE Mode
No Control Field o o F FCS F
No Address Field
FLEXIBLE Mode
No FCS Field 0 0 F A C F
FLEXIBLE Mode
No FCS Field
AUTO Mode
0
L! A C F
No FCS Field
No Control Field
L~ A F
FLEXIBLE Mode
NoFCS Field
No Control Field
0 IF' F
I
No Address Field
FLEXIBLE Mode
Key to Abbreviations:
F = Flan (01111110)
A = Addross Field
C= Control Field
I = Information Field
FCS = Frarno Check Sequence
NOTE:
The AM bit is AUTO mode control bit when NB = 0, and Address Mode control bit when NB = 1.
Figure 5. Frame Format Options
5.4 No FCS Field in the on-chip" RAM. No FCS checking is done on the
received frames, and no FCS is generated for the trans-
In the normal case (NFCS = 0), the last 16 bits before mitted frames. The No FCS Field option may be used
the closing flag are the Frame Check Sequence (FCS) in conjunction with any of the other options. It is typi-
field. These bits are not stored in the 8044's RAM. cally used in FLEXIBLE mode, although it does not
Rather, they are used to compute a cyclic redundancy strictly include AUTO mode. Use of the No FCS Field
check (CRC) on the data in the rest of the frame. A option AUTO Mode may, however, result in SDLC
received frame with a CRC error (incorrect FCS) is. protocol violations, since the data integrity is not
ignored. In transmission, the FCS field is 'automatically checked by the SIU.
computed by the SIU, and placed in the transmitted
frame just prior to the closing flag. Formats without an FCS field have the following appli-
cations:
The NFCS bit (SMD Bit 0) gives the user the capability
of overriding this automatic feature. When this bit is set Receiving and transmitting frames without verifying
(NFCS = I), all bits from the beginning of the infor- data integrity.
mation field to the beginning of the closing flag are
treated as part of the information field, and are stored Using an alternate data verification algorithm.
13-28
THE RUPITM-44 SERIAL INTERFACE UNIT
Using an alternate CRC-16 polynomial (such as X l6 + SMD: SERIAL MODE REGISTER
XIS + X2 + I), or a 32-bit CRC (BYTE-ADDRESSABLE)
Bit: 7 6 5 4 3 '2 1 0
Performing data link diagnosis by forcing false CRCs
to test error detection mechanisms I
\ SCM2\ SCM1 \ SCMO \ NRZI\ LOOP PFS \ NB NFCS I I
In addition to the applications mentioned above, all of The Serial Mode Register (Address C9H) selects the
the format variations are useful in the support of non- operational modes of the SIU. The 8044 CPU can both
standard bit-synchronous protocols. read and write SMO. The SIU can read SMO but can-
not write to it. To prevent conflict between CPU and
SIU access to SMO, the CPU should write SMO only
6.0 HOLe when the Request To Send (RTS) and Receive Buffer
Empty (RBE) bits (in the STS register) are both false
In addition to its support of SOLC communications, (0). Normally, SMO is accessed only during initializa-
the 8044 also supports some of the capabili ties of tion.
HOLC. The following remarks indicate the principal
differences between SOLC and HOLC. The individual bits of the Serial Mode Register are as
follows:
HOLC permits any number of bits in the information Bit# Name Description
field, whereas SOLC requires a byte structure (multiple
of 8 bits). The K044 itself operates on byte boundaries, SMD.O NFCS No FCS field in the SDLC
frame.
and thus it restricts fields to multiples of 8 bits.
SMD.1 NB Noon-Bufforod mode. No
control fiold in the SDLC
HOLC provides functional extensions to SOLC: an un- frame.
limited address lield is allowed, and extended frame
SMD.2 PFS Pro·Framo Sync mode. In
number sequencing. tili!; modo, the 8044
tral1!;1l1ib two bytes before
HOLC do<:s not support IIp<:ration in loop configura- tho lirst fI;l!) of a frame, for
tions. DPLL !;Yl1chronization. If
NRZI i!; tJllabled, OOH is
sent; otiHJlwise, 55H is sent.
7.0 SIU SPECIAL FUNCTION In either c;1!;e,16 pre-frame
transition!; are guaranteed.
REGISTERS SMD.3 LOOP Loop cOllflquration.
The 8044 CPU communicat<:s with and controls the SMD.4 NRZI NRZI codil1g option.
SIU through hardware registers. These registers are ac- SMD.5 SCMO Select Clock Mode-Bit 0
cessed using direct addressing. The SIU special func- SMD.6 SCM1 Select Clock Mode-Bit 1
tion registers (SIU SFRs) arc of three types: SMD.7 SCM2 Select Clock Mode-Bit 2
Control and Status Registers The SCM bits de<:od<: as follows:
Parameter Registers SCM
Clock Mode Data Rate
ICE Support Registers (Bits/sec)"
210
000 Externally clocked 0-2.4M"
7.1 Control and Status Registers 001 Undefined
010 Self clocked, timer overflow 244-62.5K
There are three SIU Control alld Status Registers:
011 Undefined
Serial Mode Register (SMO) 1 o0 Self clocked; external 16x 0-375K
1 o1 Self clocked, external 32x 0-187.SK
Status/Command Register (STS)
1 1 0 Self clocked, internal fixed 375K
Send/Receive Count Register (NSNR) 1 1 1 Self clocked, internal fixed 187.5K
The SMO, STS, and NSNR registers are all cleared by "Based on a 12 MHz crystal frequency
"0-1 M bps in toop configuration
system reset. This assures that the SIU will power up in
an idle state (neither receiving nor transmitting).
These registers and their bit assignments are described
below (see also the More Oetails on Registers section).
13-29
intJ THE RUPITM-44 SERIAL INTERFACE UNIT
Bit# Name Description
STS: STATUS/COMMAND REGISTER
(BIT-ADDRESSABLE) STS.7 TBF Transmit Buffer Full. Written by
Bit: 7 6 5 4 3 2 1 0 the CPU to indicate that it has
filled the transmit buffer. TBF
I rBF I RBE I Rrs I SI I BOV I OPB I AM I RBP I may be cleared by the SIU.
The Status/Command Register (Address CSH) pro-
vides operational control of the SIU by the 8044 CPU, NSNR: SEND/RECEIVE COUNT REGISTER
and enables the SIU to post status information for the (BIT-ADDRESSABLE)
CPU's access. The SIU can read STS, and can alter Bit: 7 6 5 4 3 2 1 0
certain bits, as indicated below. The CPU can both read
and write STS asynchronously. However, 2-cycle in- INS21 NS1 I NsolsESI NR21 NR1 I NROlsERI
structions that access STS during both cycles ('JBC/B,
REL' and 'MOY /B,C.') should not be used, since the The Send/Receive Count Register (Address DSH) con-
SIU may write to STS between the two CPU accesses. tains the transmit and receive sequence numbers, plus
tally error indications. The SIU ean both read and
The individual bits of the Status/Command Register write NSNR. The 8044 CPU can both read and write
are as follows: NSNR asynchronously. However, 2·cycle instructions
Bit# Name Description that access NSNR during both cycles ('JBC /B, REL',
STS.O RBP Receive Buffer Protect. Inhibits and 'MOY /B,C') should not he used, since the SIU
writing of data into the receive may write to NSNR between the two 8044 CPU access-
buffer. In AUTO mode, RBP es.
forces an RNR response
instead of an RR. The individual bits of the Send/Receive Count Register
STS.1 are as follows:
AM AUTO Model Addressed Mode.
Selects AUTO mode where BII# Name Description
AUTO mode is allowed. If NB is NSNR.O SER Receive Sequence Error:
true, (= 1), the AM bit selects NS (P) *- NR (S)
the addressed mode. AM may
be cleared by the SIU. NSNR.1 NRO Receive Sequence Counter-Bit 0
STS.2 OPB Optional Poll Bit. Determines NSNR.2 NR1 Receive Sequence Counter-Bit 1
whether the SIU will generate NSNR.3 NR2 Receive Sequence Counter-Bit 2
an AUTO response to an
NSNR.4 SES Send Sequence Error:
optional poll (UP with P = 0).
OPB may be set or cleared by
NR (P) * NS (S) and
NR (P) f NS (S) + 1
the SIU.
STS.3 BOV NSNR.5 NSO Send Sequence Counter-Bit 0
Receive Buffer Overrun. BOV
may be set or cleared by the NSNR.6 NS1 Send Sequence Counter-Bit 1
SIU. NSNR.7 NS2 Send Sequence Counter-Bit 2
STS.4 SI SIU Interrupt. This is one of the
five interrupt sources to the
CPU. The vector location =
23H. SI may be set by the SIU. 7.2 Parameter Registers
It should be cleared by the CPU
There are eight parameter registers that are used in
before returning from an
connection with SIU operation. All eight registers may
interrupt routine.
be read or written by the 8044 CPU. RFL and RCB are
STS.5 RTS Request To Send. Indicates normally loaded by the SIU.
that the 8044 is ready to
transmit or is transmitting. RTS The eight parameter registers are as follows:
may be read or written by the
CPU. RTS may be read by the
SIU, and in AUTO mode may STAD: STATION ADDRESS REGISTER
be written by the SIU. (BYTE-ADDRESSABLE)
STS.6 RBE Receive Buffer Empty. RBE
can be thought of as Receive The Station Address register (Address CEH) contains
Enable. RBE is set to one by the station address. To prevent access conflict, the CPU
the CPU when it is ready to
receive a frame,or has just
read the buffer, and to zero by
the SIU when a frame has been
received.
13-30
THE RUPITM-44 SERIAL INTERFACE UNIT
should access ST AD only when the SIU is idle (RTS = RFL: RECEIVE FIELD LENGTH REGISTER
o and RBE = 0). Normally, STAD is accessed only (BYTE-ADDRESSABLE)
during initialization.
The Received Field Length register (Address CDH)
contains the length (in bytes) of the received I-field that
TBS: TRANSMIT BUFFER START ADDRESS has just been loaded into on-chip RAM. RFL is loaded
REGISTER (BYTE-ADDRESSABLE) by the SIU. RFL = 0 is valid. RFL should be accessed
The Transmit Buffer Start address register (Address by the CPU only when RBE = O.
DCH) points to the location in on-chip RAM for the
beginning of the I-field of the frame to be transmitted. RCB: RECEIVE CONTROL BYTE REGISTER
The CPU should access TBS only when the SIU is not (BYTE-ADDRESSABLE)
transmitting a frame (when TBF = 0).
The Received Control Byte register (Address CAH)
contains the control field of the frame that has just been
TBL: TRANSMIT BUFFER LENGTH REGISTER received. RCB is loaded by the SIU. The CPU can only
(BYTE-ADDRESSABLE) read RCB, and should only access RCB when RBE =
O.
The Transmit Buffer Length register (Address DBH)
contains the length (in bytes) of the I-field to be trans-
mitted. A blank I-field (TBL = 0) is valid. The CPU
should access TBL only when the SIU is not transmit- 7.3 ICE Support Registers
ting a frame (when TBF = 0).
The 8044 In-Circuit Emulator (ICE-44) allows the user
to exercise the 8044 application system and monitor the
NOTE:
execution of instructions in real time.
The transmit and receive buffers arc not allowed to
"wrap around" in the on-chip RAM. A "buffer end"
The emulator operates with Intel's Intellcc® develop-
II
is automatically generated if address 191 (BFH) is
ment system. The development system inlerfaces with
reached.
I he user's 8044 systelll through an in-cable buffer box.
The cable terminates in a 8044 pin-colllpatible plug,
TCB: TRANSMIT CONTROL BYTE REGISTER which fits into the 8044 socket in the user's system.
(BYTE-ADDRESSABLE) With the emulator plug in place, the USer can exercise
his system in real time while collecling up to 255 in-
The Transmit Control Byte register (Address DAH) struction cycles of real-time data. In addilion, he can
contains the byte which is to be placed in the control single-step the program.
field of the transmitted frame, during NON-AUTO
mode transmission. The CPU should access TCB only Static RAM is available (in the in-cable bulTer box) to
when the SIU is not transmitting a frame (when TBF emulate the 8044 internal and external program memo-
= 0). The Ns and NR counters are not used in the ry and external data memory. The designCl" can display
NON-AUTO mode. and alter the contents of the replacemenl memory in
the buffer box, the internal data memory, and the inter-
nal 8044 registers, including the SFRs.
RBS: RECEIVE BUFFER START ADDRESS
REGISTER (BYTE-ADDRESSABLE) Among the SIU SFRs are the folJowing registers that
support the operation of the ICE:
The Receive Buffer Start address register (Address.
CCH) points to the location in on-chip RAM where the
beginning of the I-field of the frame being received is to DMA CNT: DMA COUNT REGISTER
be stored. The CPU should write RBS only when the (BYTE-ADDRESSABLE)
SIU is not receiving a frame (when RBE = 0).
The DMA Count register (Address CFH) indicates the
number of bytes remaining in the information block
RBL: RECEIVE BUFFER LENGTH REGISTER that is currently being used.
(BYTE-ADDRESSABLE)
The Receive Buffer Length register (Address CBH) FIFO: THREE-BYTE (BYTE-ADDRESSABLE)
contains the length (in bytes) of the area in on-chip
RAM allocated for the received I-field. RBL = 0 is The Three-Byte FIFO (Address DDH, DEH, and
valid. The CPU should write RBL only when RBE = DFH) is used between the eight-bit shift register and
O. the information buffer when an information block is
received.
13-31
THE RUPITM-44 SERIAL INTERFACE UNIT
SIUST: SIU STATE COUNTER (BYTE- SIUST Function
ADDRESSABLE) Value
28H Waiting for I field byte. This state can be
The SIU State Counter (AddressD9H) reflects the
entered from state 20H or from states
state of the internal logic which is under SIU control.
01 H, 08H, or 10H depending upon the
Therefore, care must be taken not to write into this
SIU's mode configuration. (Each time a
register.
byte is received, it is pushed onto the top
of the FIFO and the byte at the bottom is
The SIUST register can serve as a helpful aid to deter-
put into memory. For no FCS formatted
mine which field of a receive frame that the SIU ex-
frames, the FIFO is collapsed into a
pects next. The table below will help in debugging 8044
single register).
reception problems.
30H Waiting for the closing flag after having
SIUST overflowed the receive buffer. Note that
Function even if the receive frame overflows the
Value
assigned receive buffer length, the FCS
01H Waiting for opening flag. is still checked.
08H Waiting for address field.
10H Waiting for control field. Examples ofSIUSTsiallis sequences for different frame
18H Waiting for first byte of I field. This state formats are shown belol\". Nolc thai slatus changes af-
is only entered if a FCS is expected. It ter acceptance of the received licld hyte.
pushes the received byte onto the top of
the FIFO.
20H Waiting for second byte of I field. This
state always follows state 18H.
Table 1. SIUST Status Sequences
Frame Option
NFCS NB AM
Example 1:
Frame Format 1 (Idle) 1 Fill 1 C 1 I I FCS I F -I o o
SIUST Value 1 01 1 01 1 08 1 10 1 18 1 20 I 28 28 01 .
Example 2:
~~~~; ~~~:at I (I~~e) I ~ I ~ 1118 I 20 I o
Example 3:
Frame Format I (Idle) I OF1 I I I FCS I F I o o
SIUST Value ~.~0~1~~.~~=~.=1~8=1=2~0==1~2~8~=~2~8=~=0~1=~
Example 4:
Frame Format 1 (Idle) 1 F -I A 1 I 1 F 1
SIUSTValue I. 01 1 01 1 08 1 28 1 01 1
Example 5:
Frame Format I (Idle) I F I I IF I o
SIUST Value ~.~0=1~==.=01=~.==~2=8==~=0=1~
ExampleS:
Frame Format I (Idle) I F I I I I OVERFLOW I FCS.l F 1 o o
SIUSTValue 1 01 1 01 1 18 1 20 1 28 I 30 I 30 I 01 J
13-32
THE RUPITM·44 SERIAL INTERFACE UNIT
8.0 OPERATION TBS, TBL - to define the area in RAM allocated for
the Transmit Buffer.
The SIU is initialized by a reset signal (on pin 9), fol-
lowed by write operations to the SID SFRs. Once ini- Once these registers have been initialized, the user may
tialized, the SID can function in ADTO mode or NON- write to the STS register to enable the SID to leave the
ADTO mode. Details are given below. idle state, and to begin transmits and/or receives.
Setting RBE to 1 enables the SID for receive. When
8.1 Initialization RBE = 1, the SID monitors the received data stream
for a flag pattern. When a flag pattern is found, the SID
Figure 6 is the SIU. Registers SMD, STS, and NSNR enters Receive mode and receives the frame.
are cleared by reset. This puts the 8044 into an idle
state-neither receiving nor transmitting. The follow- Setting RTS to 1. enables the SID for transmit. When
ing registers must be initialized before the 8044 leaves RTS = 1, the SID monitors the received data stream
the idle state: for a GA pattern (loop configuration) or waits for a
STAD - to establish the 8044's SDLC station ad- CTS (non-loop configuration). When the GA or CTS
dress. arrives, the SID enters Transmit mode and transmits a
frame.
SMD ~ To configure the 8044 for the proper op-
erating mode. [n ADTO mode, the SID sets RTS to enable automatic
RBS, RBL - to define the area in RAM allocated for I ransmissions
of appropriate responses.
the Receive Buffer.
END-OF- END-OF-
FRAME FRAME
FLEXIBLE
MODE
AUTO
MODE
STRTREC STRTXMIT
FLEXIBLE
MODE
END-Of-FRAME
AUTO MODE
END-OF-
FRAME
STRT REG ~ RBE. FLAG
STRT XMIT ~ RTS. (GTS. LOOP + GA. LOOP)
WAIT ~ NOT (STRT REG + STRT XMIT) 296165-9
Figure 6. SIU State Diagram
13-33
THE RUPITM-44 SERIAL INTERFACE UNIT
8.2 AUTO Mode 2) In a non-loop configuration, one to eight extra drib-
ble bits are transmitted after the closing flag. These
Figure 7 illustrates the receive operations in AUTO bits are a zero followed by ones.
mode. The overall operation is shown in Figure 7a. Par- 3) In a loop configuration, when a GA is received and
. ticular cases are illustrated in Figures 7b through 7j. If the 8044 begins transmitting, the sequence is
any Unnumbered Command other than UP is received, 01111110101111110 ... (FLAG, I, FLAG, AD-
the AM bit is cleared and the SIU responds as if in the DRESS, etc.). The first flag is created from the GA.I
FLEXIBLE mode, by interrupting the CPU for super- The second flag begins the message.
vision. This will also happen if a BOY or SES condition
4) CTS is sampled after the rising edge of the serial
occurs. If the received frame contains a poll, the SIU
data, at about the center of the bit cell, except dur-
sets the RTS bit to generate a response.
ing a non-loop, externally clocked mode transmit, in
which case it is sampled just after the falling edge.
Figure 8 illustrates the transmit operations in AUTO
mode. When the SIU gets the opportunity to transmit, 5) The SIU does not check for illegal I-fields. In partic-
and if the transmit buffer is full, it sends an I-frame. ular, if a supervisory command is received in AUTO
Otherwise, it sends an RR if the buffer is free, or an mode, and if there is also an I-field, it will be loaded
RNR if the buffer is protected. The sequence counters into the receive burt'cr (if RBP = 0), but it cannot
NS and NR are used to construct the appropriate con- cause a BOY.
trol fields. 6) In relation to the Receive Buffer Protect facility, the
user should set RFL to 0 when clearing RBP, such
Figure 9 shows how the CPU responds to an SI (serial that, if the SIU is in the process of receiving a
interrupt) in AUTO mode. The CPU tests the AM bit frame, RFL will indicate the proper value when re-
. (in the STS register). If AM = I. it indicates that the ception of the frame has been completed.
SIU has received either an I-frame, or a positive re-
sponse to a previously transmitted I-frame.
8.5 Turn Around Timing
8.3 FLEXIBLE Mode In AUTO mode, the SIU generates an RTS immediate-
ly upon being polled. Assuming that the 8044 sends an
Figure 10 illustrates the receive operations in NON- information frame in response to the poll, the primary
AUTO mode. When the SIU succl'ssfully completes a station sends back an acknowledgement. If, in this ac-
task, it clears RBF and interrupts the CPU by setting knowledgement, the 8044 is polled again, a response
SI to 1. The exact CPU response to sr is determined by may be generated even before the CPU gets around to
software. A typical response is shown in Figure II. processing the interrupt caused by the acknowledge. In
such a case, the response would be an RR (or RNR),
Figure 12 illustrates the transmit operations in FLEX- since TBF would have been set to 0 by the SIU, due to
IBLE mode. The SIU does not wait for a positive ac- the acknowledge.
knowledge response to the transmitted frame. Rather, it
interrupts the CPU (by setting sr to 1) as soon as it If the system designer docs not wish to take up channel
finishes transmitting the frame. The exact CPU re- time with RR responses, but prefers to generatc a new
sponse to SI is determined by software. A typical re- I-frame as a response, there are several ways to accom-
sponse is shown in Figure 13. This response results in plish this:
another transmit frame being set up. The sequence of
operations shown in Figure 13 can also be initiated by I) Operate the 8044 in FLEXIBLE mode.
the CPU, without an S1. Thus the CPU can initiate a 2) Specify that the master should never acknowledge
transmission in FLEXIBLE mode without a poll, sim- and poll in one message. This is typically how a loop
ply by setting theRTS bit in the STS register. The RTS system operates, with the poll operation confined to
bit is always used to initiate a transmission, but it is the UP command. This leaves plenty of time for the
applied to the RTS pin only when a non-loop configu- 8044 to get its transmit butTer loaded with new in-
ration is used. formation after an acknowledge.
3) The 8044 CPU can clear RTS. This will prevent a
response from being sent, or abort it if it is already
8.4 8044 Data Link Particulars in progress. A system using external RTS/CTS
handshaking could use a one-shot delay RTS or
The following facts should be noted: CTS, thereby giving the CPU more time to disable
1) In a non-loop configuration, one or two bits are the response.
transmitted before the opening flag. This is neces-
sary for NRZI synchronization.
13-34
THE RUPITM·44 SERIAL INTERFACE UNIT
RECEIVE
NEXT BYTE
NO
ABORT. SHORT FRAME.
OR INVALID
I FRAME CTRl FIELD • Rce
NO
YES
•
IFIELD ~RFCBUF
BAD
S.. Flgu.... 7c thtu 71
296165-10
Figure 7a. SIU AUTO Mode Receive Flowchart-General
13·35
inter THE RUPITM·44 SERIAL INTERFACE UNIT
"AM"
"SI" ~1
-+-.
"RBE"-+-'
"SES"-+-'
"SER"-+-'
296165-11
Figure 7b. SIU AUTO Mode Receive Flowchart-Unknown Command
13-36
THE RUPITM-44 SERIAL INTERFACE UNIT
YES
"AM" -.- 0
"RBE"-'- 0
IISI" 4-1
II
296165-12
Figure 7c. SIU AUTO Mode Receive Flowchart-Unnumbered Poll
13-37
THE RUPITM·44 SERIAL INTERFACE UNIT
NO
..AM ...... O
"5." _ ,
"RBE"_O
"SER"_O
"SES"_'
296165-13
Figure 7d. SIU AUTO Mode Receive Flowchart-Supervisory ,Command
13·38
THE RUPITM-44 SERIAL INTERFACE UNIT
BAD
I COMMAND
HR(P) - HS(S) + 1
HS(P) - HR(S)
"AM" - 1, "HB" - •
"RBE"_'
"TBF"_'
Hs-HS+ 1
"SES"-.
"SER"_,
"51" _ 1
296165-14
Figure 7e. SIU AUTO Mode Receive Flowchart~1 Command: Prior
Transmittetll-Field Confirmed, Current Received I-Field in Sequence
13·39
inlef THE RUPITM-44 SERIAL INTERFACE UNIT
BAD
I COMMAND
NR(P) ~ NS(S)
NS(P) ~ NR(S)
"AM" ~ 1, "NB" - ,
"RBE"_,
"SES"_e
"SER"_e
"SI" _1
296165-15
Figure 71. SIU AUTO Mode Receive Flowchart-I Command: Prior
Transmitted I-Field Not Confirmed, Current Received I-Field in Sequence
13-40
THE RUPITM-44 SERIAL INTERFACE UNIT
BAD
I COMMAND
NA(P) " Ns(S) + 1
NA(P) " NS(S)
Ns(P) ~ NA(S)
"AM" - 1, "NB" = 0
"AM" ....
"SES"-4-1
"SER"-4-0
"RBE"""'O
"SI" ""'1
296165-16
Figure 7g. SIU AUTO Mode Receive Flowchart-I Command:
Sequence Error Send, Current Received I-Field in Sequence
13-41
inter THE RUPITM·44 SERIAL INTERFACE UNIT
BAD
I COMMAND
NR(P) - NS(S) + 1
NS(P) .. NR(S)
"AM" - 1. "NB" - 0
"BOV"~1
"AM" _ .
"RBE"_'
"TBF"_'
NS~Ns+1
"SES"_.
"SER" ... 1
1'51" _1
296165-17
Figure 7h. SIU AUTO Mode Receive Flowchart-I Command:
Prior Transmitted I-Field Confirmed Sequence Error Receive
13-42
THE RUPITM-44 SERIAL INTERFACE UNIT
I COMMAND
NR(P) ~ Ns(S)
N.(P) .. NR(S)
"AM" ~ I, "NB" ~ 0
II
"AM" _ _
"BOV"_1
"AM" .... _
"RBE" .... _ "RBE" .....
SI _1
"SI" .... 1
296165-18
Figure 7i. SIU AUTO Mode Receive Flowchart-I Command:
Prior Tran~mitted I-Field Not Confirmed, Sequence Error Receive
13-43
intJ THE RUPITM·44 SERIAL INTERFACE UNIT
BAD
I COMMAND
HAIP) .. NIlS) .. ,
NAIP) .. NelS)
HaIP) .. NAIP)
"AM" .- " "NB" = 0
"AM" ....
"R8E""',
"SES"_'
"SER""'1
"SI" ...,
296165-19
Figure 71. SIU AUTO Mode Receive Flowchart-I Command:
Sequence Error Send and Sequence Error Receive.
13-44
inter THE RUPITM·44 SERIAL INTERFACE UNIT
··0
YES
X MIT
I
XMIT
RR
FRAME
X MIT
RNR
II
FRAME FRAME
296165-20
Figure 8. SIU AUTO Mode Transmit Flowchart
13-45
intJ THE RUPITM-44 SERIAL INTERFACE UNIT
LOAD I·FIELD
INTO
XMIT BUFFER
PROCESS
INFORMATION
OR
SET "RBP"
296165-21
Figure 9. AUTO Mode Response to "SI"
13-46
THE RUPITM·44 SERIAL INTERFACE UNIT
RECEIVE,
NEXT BYTE
NO -----j
I
YES
I
I
ABORT, I
II
SHORT FRAME
OR INVALID I
RECEIVE MESSAGE
CTRL FIELD __ RCB,
I FIELD __ REC BUF, - --i I RBE- 0
(ABORT FROM CPU)
SET BOV ON OVERRUN
BAD
GOOD
CLEAR "RBE"
SET "SI"
L---------i_ - - ~ - - - -.J
296165-22
Figure 10. SIU FLEXIBLE Mode Receive Flowchart
13-47
inter THE RUPITM-44 SERIAL INTERFACE UNIT
PROCESS MESSAGE,
SET UP RESPONSE
IF NECESSARY
296165-23
Figure 11. FLEXIBLE Mode Response to Receive "SI"
13-48
inter THE RUPITM-44 SERIAL INTERFACE UNIT
!§l:tUT-OFF· LOOP) +
CTS·LOOP
r----------------
TBF ~.
TRANSMIT MESSAGE
USING TCB FOR
CONTROL FIELD
-- -- -- -- .,
[ABORT FROM PRIMARY]
.
I (ABORT FROM CPU)
I
~
____
>-~_1 ~
CLEAR "TBF"
________________-.++ __ __ __ __ __ __ __ __ ~
II
CLEAn "RTS"
seT "51"
TRANSMIT
ABORT
SEQUENCE
296165-24
Figure 12. SIU FLEXIBLE Mode Transmit Flowchart
13-49
THE RUPITM·44 SERIAL INTERFACE UNIT
CLEAR "SI"
XMIT
~ 1,PENDING
TBF INDICATES
BUFFULL LAST TRANSMIT
ABORTED BY CPU
OR PRIMARY,
BUFEMPTY
CTRL FIELD ....TCB
I-FIELD . . XMIT BUF
SET "TBF"
SET "RTS"
296165-25
Figure 13_ FLEXIBLE Mode Response to Transmit "SI"
13-50
intJ THE RUPITM·44 SERIAL INTERFACE UNIT
9.0 MORE DETAILS ON SIU The zero insert/delete circuitry (ZID) performs zero
HARDWARE insertion/deletion, and also detects flags, GA's (Go-
Ahead's), and aborts (same as GA's) in the data
The SIU divides functionally into two sections-a bit stream. The pattern 1111110 is detected as an early
processor (BIP) and a byte processor (BYP)-sharing GA, so that the GA may be turned into a flag for loop
some common timing and control logic. As shown in mode transmission.
Figure 14, the BIP operates between the serial port pins
and the SIU ~us, and performs all functions necessary The shut-off detector monitors the receive data stream
to transmit/receive a byte of data to/from the serial for a sequence of eight zeros, which is a shut-off com-
data stream. These operations include shifting, NRZI mand for loop mode transmissions. The shut-off detec-
encoding/decoding, zero'insertion/deletion, and FCS tor is a three-bit counter which is cleared whenever a
generation/checking. The BYP manipulates bytes of one is found in the receive data stream. Note that the
data to perform message. formatting, and other trans- ZID logic could not be used for this purpose, because
mitting and receiving functions. It operates between the the receive data must be monitored even when the ZID
SIU bus (SIB) and the 8044's iuternal bus (IB). The is being used for transmission.
interface between the SIU and t he CPU involves an
interrupt and some locations in on-chip RAM space As an example of the operation of the bit processor, the
which are managed by the BYI'. following sequence occurs in relation to the receive
data:
The maximum possible data rate fur the serial port is I) RXD is sampled by SCLK, and then synchronized
limited to '/2 the internal clock rate. This limit is im- to the internal processor clock (IPC).
posed by both the maximum rate of DMA to the on- 2) If the NRZI mode is selected, the incoming data is
chip RAM, and by the requirements of synchronizing NRZI decoded.
to an external clock. The internal cluck rate for an 8044
running on a 12 MHz crystal is (, M lIz. Thus the maxi- 3) When receiving other than the flag pattern, the ZID
mum 8044 serial data rate is .\ M liz. This data rate deletes the '0' after 5 consecutive 'l's (during trans-
drops down to 2.4 MHz when tinle is allowed for exter- mission this zero is inserted). The ZID locates the . .
nal clock synchronization. byte boundary for the rest of the circuitry. The ZID
deletes the 'O's by preventing the SR (shift register)
from receiving a clocking pulse.
9.1 The Bit Processor 4) The FCS (which is a function of the data between
the nags-not including the nags) is initialized and
In the asynchronous (self clocked) nl<lI\cs the clock is started at the detection of the byte boundary at the
extracted from the data stream llsing the on-chip digital end of the opening flag. The H'S is l'umputed each
phase-locked-loop (DPLL). The DI'L1. requires a clock bit boundary until the closing !lag is detected. Note
input at 16 times the data rate. This I h :< clock may that the received FCS has gone through the ZID
originate from SCLK, Timer I Overflow, or PH2 (one during transmission.
half the oscillator frequency). The extra divide by-two
described above allows these sources to be treated alter-
natively as 32 X clocks. 9.2 The Byte Processor
The DPLL is a free-running four-bit counter running Figure 15 is a block diagram of the byte processor
off the 16 X clock. When a transition is detected in the (BYP). The BYP contains the registers and controllers
receive data stream, a count is dropped (by suppressing necessary to perform the data manipulations associated
the carry-in) if the current count value is greater than 8. with SDLC communications. The BYP registers may
A count is added (by injecting a carry into the second be read or written by the CPU over the 8044'5 internal
stage rather than the first) if the count is less than 8. No bus (IB), using standard 8044 hardware register opera-
adjustment is made if the transition occurs at the count tions. The 8044 register select PLA controls these oper-
of 8. In this manner the counter locks in on the point at ations. Three of the BYP registers connect to the IB
which transitions in the data stream occur at the count through the IBS, a sub-bus which also connects to the
of 8, and a clock pulse is generated when the count CPU interrupt control registers.
overflows to O.
In order to perform NRZI decoding, the NRZI decod-
er compares each bit of input data to the previous bit.
There are no clock delays in going through the NRZI
decoder.
13-51
inter THE RUPITM·44 SERIAL INTERFACE UNIT
INTERRUPT
,
IB
1
RAM CPU
r - ---- ------- I-- - - - - - - - - - - - SIU""
I
I
:--1
SHARED
REGISTERS
h I
I
•
I I/O/ RXD
•
~
'--- BYP OIP .. I OATA/TXD
•
SIB I
I
L ____________ _
296165-26
Figure 14. The Bit and Byte Processors
Simultaneous access ofa register by both the IB and the 2) Assuming that there is a control field in the frame,
SIB is prevented by timing. In particular, RAM access the BYP takes the next hyte and loads -it into the
is restricted to alternate internal processor cycles f(lI- RCB register. The ReB register has the logic to
the CPU and the SIU, in such a way that collisions do update the NSNR register (increment receive count,
not occur. set SES and SER flags, ctc.).
3) Assuming that there is an information field, the next
As an example of the operation of the byte processor, byte is dumped into RAM at the RBS location. The
the following sequence occurs in relation to the receive DMA CNT (RBL at the opening flag) is loaded
data: from the DMA CNT register into the RB register
I) Assuming that there is an address field in the frame, and decremented. The RFL is then loaded into the
the BYP takes the station address from the register RB register, incremented, and stored back into the
file into temporary storage. After the opening flag, register file.
the next field (the address field) is compared to the 4) This process continues until the DMA CNT reaches
station address in the temporary storage. If a match zero, or until a closing flag is received. Upon either
occurs, the operation continues. event, the BYP updates the status, and, if the CRC
is good, the NSNR register.
13-52
THE RUPITM~44 SERIAL INTERFACE UNIT
ir---------------,
I
I . I
I I
I I
I I
I I
I I
I I RAM
I I
I I
I I
I I
I I
I SIB I
BYP
TIMING SHARED .IB
AND REGISTERS
CONTROL 1\,--,------- - -
I
I
I
~ I
I
L _______________ . ~P~
2!mi65-27
Figure 15. The Byte Processor
10.0 DIAGNOSTICS stream to the SIU by writing to 1'3.0. The transmit data
stream can be monitored by reading P3.1. Each succes-
An SID test mode has been provided, so that the on- sive bit is transmitted from the SIU by writing to any
chip CPU can perform limited diagnostics on the SIU. bit in Port 3, which generates SCLK.
The test mode utilizes the output latches for P3.0 and
P3.1 (pins to and 11). These port 3 pins.are not useful In test mode, the P3.0 and P3.1 pins are placed in a
as out-put ports, since the pins are"taken up by the high voltage, high impedance state. When the CPU
serial port functions. Figure 16 shows the signal routing reads P3.0 and P3.1 the logic level applied to the pin
associated with the SID test mode. will be returned. In the test mode, when the CPU reads
3.1, the transmit data value will be returned, not the
Writing a 0 to P3.1 enables the serial test mode (p3.1 is voltage on the pin. The transmit data remains constant
set to 1 by reset). In test mode the P3.0 bit is mapped for a bit time. Writing to P3.0 will result in the signal
into the received data stream, and the 'write port 3' being ,outputted for a short period of time. However,
control signal is mapped into the SCLK path in place of since the signal is not latched, P3.0 will quickly return
T1. Thus, in test mode, the CPU can send a serial data to a high voltage, high impedance state.
13-53
(
CPU
BUS
TIMER 1 OVF
SYSCLK
SIUSERIAL
DATA CLOCK
....
J:
m
::c
c:
"tI
~
"T1 PIN "
I/O/
rC RXD/ I
c PH .c.
iil .c.
...
CD
tJ)
m
c;; in ::c
~ 2: SIU :;
.I:> -I ---. RECEIVE
DATA
r-
<D STREAM
!!l. Z
....
~
Co
m
::c
<D ."
lim
c:
Z
::j
READPDRT3
WRITE PORT 3
PINlI
DATA/ SIU
TXD/ TRANSMIT
P31 DATA
STREAM
296165-28
THE RUPITM-44 SERIAL INTERFACE UNIT
The serial test mode is disabled by writing a 1 to P3.1. transmits a supervisory frame. This frame consists of an
Care must be taken that a 0 is never written to P3.1 in opening flag, followed by the station address, a control
the course of normal operation, since this causes the field indicating that this.is a supervisory frame with an
test mode to be entered. RNR command, and then a closing flag.
Figure 17 is an example of a simple program segment Each byte of the frame is transmitted by writing that
that can be imbedded into the user's diagnostic pro- byte into the A register and then calling the subroutine
gram. That example shows how to put the 8044 into XMIT8. Two additional SCLKs are generated to guar-
"Loop-back mode" to test the basic transmitting and antee that the last bits in the frame have been clocked
receiving functions of the SID. into the SID. Finally the CPU reads the status register
(STS). If the operation has proceeded correctly, the
Loop-back mode is functionally equivalent to a hard- status will be 072H. If it is not, the program jumps to
wire connection between pins 10 and lion the 8044. the ERROR loop and terminates.
In this example, the 8044 CPU plays the role of the The SIU generates an SI (SIU interrupt) to indicate
primary station. The SIU is in the AUTO mode. The that it has received a frame. The CPU clears this inter-
CPU sends the SIU a supervisory frame with the pol1 rupt, and then begins to monitor the data stream that is
bit set and an RNR command. The SIU responds with being generated by the SIU in response to what it has
a supervisory frame with the poll bit set and an RR received. As each bit arrives (via P3.1), it is moved into
command. the accumulator, and the CPU compares the byte in the
accumulator with 07EH, which is the opening flag.
The operation proceeds as follows: When a match occurs, the CPU identifies this as byte
boundary, and thereafter processes the information
Interrupts are disabled, and the self test mode is en- byk-to-byte.
abled by writing a zero to P3.1. This establishes P3.0 as
the data path from the CPU to the SIU. CTS (clear-to-
send) is enabled by writi'ng a zero to l' I. 7. The station
address is initialized by writing 08AlI into the STAD
(station address register).
The CPU cal1s the RCV8 subroutine to get each byte
into the accumulator. The CPU performs compare op-II
erations on (successively) the station address, the con-
trol field (which contains the RR response), and the
closing flag. If any of these do not COlJlpare, the pro-
The SIU is configured for receive operation in the gram jumps to the ERROR loop. If no error is found,
clocked mode and in AUTO mode. The CPU then the program jumps to the DONE loop.
13-55
inter THE RUPITM-44 SERIAL INTERFACE UNIT
I'1CS-:il MACRO ASSEMBLER DATA
ISIS-II I"ICS-~H f'lACRQ ASSEMBLER V2.0
OBJECT f'KlDULE PLACED IN . Fl: DATA. OBJ
ASSEMBLER INVOKED BY: .... 51 '1: d.t •. II." d.vic.(44)
LOC OSJ LINE SOUACE
I
2
0000 75eeoo 3 INIT: Mey BTS.lOOH
0003 C291
0005 C297 •
5
CLR
CLR
P3.1
Pi. 7
j
I
En.bh . . 1' t •• t .ode
Enebl. ers
0007 75CESA 0 I<OV 5T"D. lSAH IniU.llre addre ••
7
a CONFIgURE RECEIVE OPERATION
9
OOOA 75086A 10 I<OV NSNR. 16ltH NS(S)-3. SE9-0. HACEI)·', SER-O
0000 75C901 11 I<OV 91D. tKtlH I weS-l
0010 75C8C2 I<OV
.
.2 6TS. IOCilH TBF-l. RBE-t • ...".1
13 /
I. TRANSP1lT A SUPERVISORV FRME FROI'I THE PAII1AAY STATION WITH THE POLL
0013 747E
0015 120066
0018 748A
10
17
la
19
SEND:
8IT SET AND It RMI Cc::JI'tf1AND
I<OV
CALL
I<OV
A. 17EH
Xt1JT8
A. oaAH
The StU "ec. " ....
The .ddr ••• i . " •• t
. 'h. fIi .... 1:
001A 120066 20 CALL Xf1I TO
0010 7495 21 I<OV A. 109'H I ANA SUP FRME wUPt P/F-l. NRfP)-4
00IF 120066 22 CALL XP1lTB
0022 747E 23 MOIl A. 17EH Aeceive closing fl1.ll
0024 120066 24 CALL IU11TB
0027 0210
0029 02BO
2'
20
SETS
SETB
P3 0 O.".".t. s.t",. GClK'. t .
P3 0 I Ini tiet. reee Iv. ec t ion
27
0'028 E,ce 2a "OV A. UTS I Ch_eII for apprDpriate statu.
002D 84722A 29 CJNE A. 172H. ERROR
30
3. PREPARE TO RECEive RUPI'9 RESPONCE TO PRI"ARV'S R'-
32
33
34
0030 t;lee 30 RECV: CLR J Cl •• " 91
0032 7400 3b I<OV I C1 •• r ACe
0034 780C 37 m!V j r,,1W 12 ti •••
3a
39 LOOK FOR Tt-£: {)fI£NJNO FLAO
40
0036 0280 41 WFLAQ1: SETB PJ.O SelK
0039 "'281
0030'\ 13
0038 847E03
003£ 020046
0041 DBF3
42
43
44
4'
4b WFLQ1:
m!V
RRC
CJNE
J""
D~NI
..
c.
•
CNTINU
P3.1
I07EH. WFUH
R3. WFLAQI
I T.,.an •• ,tted d.t.
0043 02005. 47 ,,"P [RROR
4a
....
49
0046 1200~ '0 CNTINU: CALL Rcve I o.t BIU's T".n •• Ut.d .d.r ••• 'ieU
0049 84SAOE
004C 1200,C "
'2
C~NE
CALL Rcva
'OBAH, ERROR
I Pri •• rv .xp.cts to r.c .1v. RR 'ro. stu
004F 84810B
00'2 12005e
0o" 847E02
",.
,.,.
CJNE
CALL
C.JNE ....
Rcva
IOOlH, ERROR
I R.c.iv. closing 11.11
~. I07EH. ERROR
0058 80FE 07 DONE,
'a
~"" DONE
OO,A 90FE '9 ERROR: .JPIP ERROR
00
01
oo,e 1808 02 RCVS: "OV RO. loa I Jni U.li Ie the bit counte"
005E 0280 03 GETBIT: SETB P3.0 SCLK
0060 "'281
0062 13 ••
0'
HOV
RRC
C. P3.1
•
Tr.nslfti tted d.t •
0063 DBF9 b. D~NI RO. CETBIT
0065 22 07 RET
.e
09
70
OObb 7809 71 I(I'1IT8: "OV RO. 09 Initi..Un the bit count.r
0068 13 72 L3: RRC A Put the bit to be ''''.n ..11 tt.d
73 in the C."'''V
0069 0901 7. DJNZ RO. LI When .11 bit. h.ve be.n ..nt
006B 22
"
70
RET r.tu",n
OObe 400 .. 77 Ll: JC L2 I f tho c.,.",
V bit io •• t. •• t
006E C280
0070 BOF6
7a
79
eo
CLR P3.0
L3
. h.,.
part P3.0 .1 ••
c port P3.0
007~ 1)290
a.
a2 L2·
"""
SETB P3.0
0074 80F2 a3 J"P L3
a. .n.
296165-29
Figure 17. Loop-Back Mode Software
13-56
November 1989
II
8044 Application Examples
Order Number: 296166-001
13-57
8044 APPLICATION CONTENTS PAGE
EXAMPLES 8044 APPLICATION EXAMPLES
1.0 INTERFACING THE 8044 TO A
MICROPROCESSOR ................ 13-59
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-59
The Interface ........................... 13-59
The Software .......................... 13-59
Conclusion ............................. 13-60
A HIGH PERFORMANCE NETWORK
USING THE 8044 .................... 13-68
2.0 INTRODUCTION ................... 13-68
2.1 Hardware .......................... 13-68
2.2 SDLC Basic Repertoire ............. 13-69
2.3 Secondary Station Driver Using AUTO
Mode ................................ 13-72
2.4 Application Module; ASYNC to SDLC
Protocol Converter ............ : ...... 13-80
2.5 Primary Station ..................... 13-84
APPENDIX A: 8044 SOFTWARE
FLOWCHARTS ...................... 13-88
APPENDIX B: LISTINGS OF
SOFTWARE MODULES ............ 13-108
13-58
inter 8044 APPLICATION EXAMPLES
1.0 INTERFACING THE 8044 TO A ure 3 shows the 8088 and support circuitry; the memo-
MICROPROCESSOR ry and decoders are not shown. It is a basic 8088 Min
Mode system with an 8:i.37A DMA controller and an
The 8044 is designed to serve as an intelligent control- 8259A interrupt controller.
ler for remote peripherals. However, it can also be used
as an intelligent HDLC/SDLC front end for a micro- DMA Channel One transfers a block of memory to the
processor, capable of extensively off-loading link con- tri-state latch, while Channel Zero transfers a block of
trol functions for the CPU. In some applications, the data from the latch to 8088's memory. The 8044's In-
8044 can even be used for communications preprocess- terrupt 0 signal vectors the CPU into a routine which
ing, in addition to data link control. reads from the internal RAM and writes to the .latch.
The 8044's Interrupt 1 signal causes the chip to read
This section describes a sample hardware interface for from the latch and write to its on-chip data RAM. Both
attaching the 8044 to an 8088. It is general enough to DMA requests and acknowledges are active low.
be extended to other microprocessors such as the 8086
or the 80186. Initially, when the power is applied, a reset pulse com-
ing from the 8284A initializes the SR flip-flops. In this
initialization state, the 8044's transmit interrupt and
OVERVIEW the 8088's transmit DMA request are active; however,
the software keeps these signals disabled until either of
A sample interface is shown in Figure 1. Transmission the two processors are ready to transmit. The software
occurs when the 8088 loads a 64 byte block of memory leaves the receive signals enabled, unless the receive
with some known data. The 8088 then enables the buffers are full. In this way either the 8088 or the 8044
8237A to DMA this data to the 8044. When the 8044 are always ready to receive, but they must enable the
has received all of the data from the 8237 A, it sends the transmit signal when they have prepared a block to
data in a SDLC frame. The frame is captured by the transmit. After a block has been transmitted or re-
Spectron Datascope™* which displays it on a CRT in ceived, the DMA and interrupt signals rdurn to the
hex format. initial state.
In reception, the Datascope sends a SDLC information The receive and transmit buffer sizes for t he blocks of
frame to the 8044. The 8044 receives the SDLC frame, data sent between the 8044 and the HOXH have a maxi-
buffers it, and sends it to the 8088's memory. In this IllUIII lixed length. In this case the bull'er size was 64
example the 8044 is being operated in the NON-AUTO hytes. The buffer size must be less t han I n bytes to
mode; therefore, it does not need to be polled by a pri- enaht..: 8044 to buffer the data in its (lll·dlip RAM. This
mary station in order to transmit. desigll allows blocks of data that arc less than 64 bytes,
and accommodates networks that allow frames of vary-
THE INTERFACE ing size. The first byte transferred between the 8088
and the 8044 is the byte count to follow; thus the 8044
The 8044 does not have a parallel slave port. The knows how many bytes to receive beli)re it transmits
8044's 32 I/O lines can be configured as a local micro- the SDLC frame. However, when the 8044 sends data
processor bus master. In this configuration, the 8044 to the 8088's memory, the 8237 A will not know if the
can expand the ROM and RAM memory, control pe- 8044 will send less than the count the 8237 A was pro-
ripherals, and communicate with a microprocessor. grammed for. To solve this problelll, the 8237A is oper-
ated in the single mode. The 8044 uses an I/O bit to
The 8044, like the 80S 1, does not have a Ready line, so generate an interrupt request to the 82S9A. In the
there is no way to put the 8044 in wait state. The clock 8088's interrupt routine, the 8237A's receive DMA
on the 8044 cannot be stopped. Dual port RAM could channel is. disabled, thus allowing blocks of data less
still be used, however, software arbitration would be than 64 bytes to be received.
the only way to prevent collisions. Another way to in-
terface the 8044 with another CPU is to put a FIFO or
queue between the two processors, and this was the
THE SOFTWARE
method chosen for this design, The software for the 8044 and the 8088 is shown in
Table 1. The 8088 software was written in PL/M86,
Figure 2 shows the schematic of the 8044/8088 inter- and the 8044 software was written in assembly lan-
face. It involves two 8-bit tri-state latches, two SR flip- guage.
flops, and some logic gates (6 TTL packs). The circuit-
ry implements a one byte FIFO. RS422 transceivers arc The 8044 software begins by initializing the stack, in-
used, which can be connected to a multidrop link. Fig- terrupt priorities, and triggering types for the inter-
'Datascope is a trademark of Spectron Inc. rupts. At this point, the SID parameter registers are
13-59
intJ 8044 APPLICATION EXAMPLES
,------
I
r------.
I
I
I
I
I
I
I
DATASCOPE
296166-1
Figure 1. Block Diagram of 8088/8044 Interface Test
initialized. The receive and transmit buffer starting ad- Normally this interrupt remains disabled. However, if a
dresses and lengths are loaded for the on-chip DMA. serial interrupt occurs, and the SERIAL INT routine
This DMA is for the serial port. The serial station ad- detects that a frame has been received, it calls the
dress and the transmit control bytes are loaded too. SEND subroutine. The SEND subroutine loads the
number of bytes which were received in the frame into
Once the initialization has taken place, the SID inter- the receive buffer. Register R I points to the receive
rupt is enabled, and the external interrupt which re- buffer and R2 is loaded with the count. The TRANS-
ceives bytes from the 8088 is enabled. Setting the 8044's MIT DMA interrupt is enabled, and immediately upon
Receive Buffer Empty (RBE) bit enables the receiver. If returning from the SERIAL INT routine, the interrupt
this bit is reset, no serial data can be received. The 8044 is acknowledged. Each time the TRANSMIT DMA in-
then waits in a loop for either RECEIVE DMA inter- terrupt occurs, a byte is read from the receive buffer,
rupt or the SERIAL INT interrupt. written to the latch, and R2 is decremented. When R2
reaches 0, the TRANSMIT DMA interrupt is disabled,
The RECEIVE DMA interrupt occurs when the the SID receiver is re-enabled, and the 8044 interrupts
8237 A is transferring a block of data to the 8044. The the 8088.
first time this interrupt occurs, the 8044 reads the latch
and loads the count value into the R2 register. On sub-
sequent interrupts, the 8044 reads the latch, loads the CONCLUSION
data into the transmit buffer, and decrements R2.
For the software shown in Table 1, the transfer rate
When R2 reaches zero, the interrupt routine sends the
from the 8088's memory to the 8044 was measured at
data in an SDLC frame, and disables the RECEIVE
75K bytes/sec. This transfer rate largely depends upon
DMA interrupt. After the frame has been transmitted,
the number of instructions in the 8044's interrupt serv-
a serial interrupt is generated. The SERIAL INT rou-
ice routine. Fewer instructions result in a higher trans-
tine detects that a frame has been transmitted and re- fer rate.
enables the RECEIVE DMA interrupt. Thus, while the
frame is being transmitted through the SID, the 8237A
There are many ways of interfacing the 8044 locally to
is inhibited from sending data to the 8044's transmit
buffer. - another microprocessor: FIFO's, dual port RAM with
software arbitration, and 8255's are just a few. Alterna-
tive approaches, which may be more optimal for certain
The TRANSMIT DMA routine sends a block of data
applications, are certainly possible.
from the 8044's receive buffer to the 8088's memory.
13-60
DREQI
DREOI
DACKI
l
"II CD
IE o
01:0
...CD
c 01:0
):0
~ "D
aI "D
C r-
""
~
...""
S
£
-
c.:l
~ ...CD (5
DI
()
~KI z
CD
oJ2.!!. m
><
...
S'
:::T
~Kl
~IOW
):0
s::
CD
aI
C
aI
...m
"D
aI CJ)
RUPI EXPANSION BUS 2128
PI
296166-2
C5
~
~
TTTTTTTT
08000FOH
2.2K
'5
lK
(
R~~~iN914
B~~~O
v
rT-.. .,"',...
*
o..........
PClK I I
r~
. - AJ
-~"
~
U
~
04
~~
~
MEMW
~
::n
CSYNC
~:fY2
AFMl
ClK r----~_D
RST - ClK U
+5
B15257
~ _ro
B3
MOC •
f
+5Y
~
co
0
,j>,
(Q
...
c AEN2 ROV
IK I ,j>,
fI)
!N
co
c ' ,.
RESET
K07.~·
lllll
MR MU~ CS
r II
OREQf
t5Y
-CJ 8237 CS
> OREQ,
l>
'0
'0
I
co +5
I
'~:OA :J OACKe (;
co +5 5Y"gK ICR lOW OACK. > OREQ,
-" • '.;!. ROY RESET ClK ClR 0 1 ALE CI OREQI :J OACK' l>
w R~ f---J g~~~~ -I
en s'5: 560K L- MNIMX
101M - - l
PR
74lS74
v
RESEli
ClK
RESET
6237·2
OACK2
> OREQ2
:J OACK2
0
f\)
I~ WA - - - ' I Q
5:
r Z
INTR 110 Te>--, A7 AS A3 AT ASIB 07.05 OJ OT OREQ3
0
c. or.............. ~ NMI HOlOp-----J I·AI61IA41~IA' I 106 \04\02\0' m
><
~=, i ~f;'1 ~Jr ~
fI) lui E3 HIOA 1IIII
1/1 ~ C1 Al E -;::::J..... > AO·A7 l>
'< :s::
!!l.
fI)
'0
AEN I
3 ~ m
en
11111111 V
~d AI3 Al,ADe
IA15 A12 A9
11111 01' De (((((((( ,II JJJ JJll) 000·07
IAUl !Al1 \Ai
,I ---., ( 0 A15·A8
• 81;
0~ES:7
016 GI 006
DIS 005
~ gg;
gl~ ~ gg~
011 Dot
IT
296166-3
8044 APPLICATION EXAMPLES
Table 1. Transmit and Receive Software for an 8044/8088 System'
LOC OBJ LINE SOURCE
I Sdebug title (8044/8088 INTERFACE)
2
0000 4 FIRSLBYTE BIT 0 ; FLAG
0000 6 ORG 0
00008024 SJMP INIT
0026 9 ORG 26H
10
0026 7581AA II INIT: MOV SP, #170 ; INITIALIZE STACK
0029 75B800 12 MOV IP, #00 ; ALL INTERRUPTS ARE EQUAL PRIORITY
002C 75C954 1.1 MOV SMD, #54H ; TIMER I OVERFLOW, NRZI, PRE-FRAME SYNC
002F 758844 14 MOV TCON, #44H ; EDGE TRIGGERED EXTERNAL INTERRUPT I
15 ; LEVEL TRIGGERED EXTERNAL INTERRUPT 0
16 ;TIMER I ON
0032 758DEC 17 MOV THI, #OECIl ; INITIALIZE TIMER, 3125 BPS
0035 758920 18 MOV TMOD,H20H ; TIMER I AUTO RELOAD
19
0038 75DC6A 20 MOV TBS, #106 ; SET UP SIU PARAMETER REGISTERS
003B 75DB40 21 MOV TBL, #64
003E 75CC2A 22 MOV RBS, #42
0041 75CB40 23 MOV RBL,664
0044 75CE55 24 MOV STAD, #55H
0047 75DAII 25 MOV TCB, #00010001 B; RR, PjF= I
26
004A 901000 27 MOV DPTR, # 100011 ; DPTR POINTS TO TRI-STATE I.ATCH
004D D200 28 SETB FIRSLBYTE ; FLAG TO INDICATE FIRST IIYTE
29 ; FOR RECEIVE INTERRUPT ROUTINE
004F D2CE 30 SETB RBE ; READY TO RECEIVE
0051 75A894 31 MOV IE, #IOOIOIOOB ; ENABLE RECEIVE DMA AND SIU INTERRUPT
32
0054 80FE 33 SJMP S ; WAIT HERE FOR INTERRUI'TS
34
0056 80FE 35 ERROR: SJMP ERROR
36 + I SEJ
37 ;.......................... SUBROUTINES •••••••••••••••••••••••••••••••
38
0058 85CD29 39 SEND: MOV 41, RFL ; FIRST BYTE IN BLOCK IS COUNT
005B 7929 40 MOV RI, #41 ; POINT TO BLOCK OF DATA
005D AACD 41 MOV R2, RFL ; LOAD COUNT
005F OA 42 INC R2
0060 D2A8 43 SETB EXO ; ENABLE DMA TRANSMIT INTERRUPT
0062 22 44 RET
45
46
47
48 .................... INTERRUPT SERVICE ROUTINES .....................
49
0063 50 LOCTMPSET S ., ; SET UP INTERRUPT TABLE JUMP
0013 51 ORG oOlm
0013 020063 52 LJMP RECEIVLDMA
0063 53 ORG LOCTMP
54
55 RECEIVLDMA:
296166-69
13-63
8044 APPLICATION EXAMPLES
Table 1. Transmit and Receive Software for an 8044/8088 System (Continued)
56
0063 10000E 57 JBC FIRST_BYTE, II ; THE FIRST BYTE TRANSFERRED IS THE COUNT
58
0066 EO 59 MOVX A,@DPTR ; READ THE LATCH
0067 F6 60 MOV @RO,A ; PUT IT IN TRANSMIT BUFFER
0068 08 61 INC RO
0069 DA08 62 DJNZ R2, L2 ; AFTER READING BYTES,
63
006B D2CF 64 SETB TBF ;SEND DATA
006D D2CD 65 SETB RTS
006F 0200 66 SETB FIRST_BYTE
0071 C2AA 67 CLR EXI
68
0073 32 69 L2: RET!
70
0074 78M 71 L1: MOV RO, #106 ; RO IS A POINTER TO THE TRANSMIT
72 ; BUFFER STARTING ADDRESS
0076 EO 73 MOVX A, (rdll'TR ; PUT THE FIRST BYTE INTO
0077 FA 74 MOV R2, A ; R2 FOR THE COlJNT
0078 32 75 RETI
76
0079 77 LOCTMPSET
0003 78 ORG 000.111
0003 020079 79 LJMP TRANSMILDMA
0079 80 ORG 1.0(' IMP
81
82 TRANSMILDMA
83
0079 E7 84 MOV A, (r'\( I ;READ BYTI: OUT OF THE RECEIVE BUFFER
007A FO 85 MOVX (a'[)PTR, A ; WRITE IT TO THE LATCH
0078 09 86 INC RI
007C DA08 87 DJNZ R2, U ; WHEN AI.I. BYTES HAVE BEEN SENT
88
007E C2A8 89 CLR IE. () ; DISABLE INTERRUPT
0080 C294 90 CLR' PI. 4 ; CAUSE 8088 INTERRUPT TO TERMINATE DMA
0082 D294 91 SETB PI. 4
0084 D2CE 92 SETB RBE ; ENABLE RECEIVER AGAIN
93
0086 32 94 U: RETI
95
96
97
0087 98 LOCTMPSET $
0023 99 ORG 0023H
0023 020087 100 LJMP SERIALINT
0087 101 ORG LOCTMP
102
103 SERIALINT:
104
0087 30CE06 105 JNB RBE, RCV ; WAS A FRAME RECEIVED
008A 30CFOB 106 JNB TBF,XMIT ; WAS AFRAME TRANSMITTED
008D 020056 107 LJMP ERROR ; IF NEITHER ERROR
108
0090 20CBC3 109 RCV: JB BOV, ERROR ; IF BUFFER OVERRUN THEN ERROR
0093 1158 110 CALL SEND ; SEND THE FRAME TO THE 8088
0095 C2CC III CLR SI
0097 32 112 RETI
113
0098 C2CC 114 XMIT: CLR SI
296166-70
13'64
inter 8044 APPLICATION EXAMPLES
Table 1. Transmit and Receive Software for an 8044/8088 System (Continued)
009A D2AA 115 SETB EXI
009C 32 116 RETI
117
liS END
SYMBOL TABLE LISTING
---
NAME TYPE VALUE ATTRIBUTES
BOV II ADDR OOCSH.3 A
ERROR C ADDR 0056H A
EXO II ADDR OOASH.O A
EXI II ADDR OOASH.2 A
FIRSLBYTE II ADDR 0020H.O A
IE () ADDR OOASH A
INIT C ADDR 0026H A
IP D ADDR OOBSH A
LI C ADDR 0074H A
l2 C ADDR 0073H A
L3 C ADDR OOS6H A
lOCTMP C ADDR OOS7H A
PI D ADDR 0090H A
•
RBE B ADDR OOC8H.6 A
RBl D A[)()R OOCBH A
RBS D ADDR OOCCH A
RCV C ADDR 0090H A
RECEIVE-DMA C ADDR 0063H A
RFl D ADDR OOCDH A
RTS B ADDR 00CSH.5 A
SEND C ADDR 0058H A
SERIALINT C ADDR 0087H A
SI B ADDR 00C8H.4 A
SMD D ADDR OOC9H A
SP D ADDR 0081H A
STAD D AD DR OOCEH A
TBF B ADDR OOC8H.7 A
TBl D ADDR OODBH A
TBS D ADDR OODCH A
TCB D ADDR OODAH A
TCON D ADDR OOSSH A
THI D ADDR 008DH A
TMOD D ADDR 0089H A
TRANSMILDMA C ADDR 0079H A
XMIT C ADDR 0098H A
REGISTER BANK(S) USED: 0, TARGET MACHINE(S): 8044
ASSEMBLY COMPLETE, NO ERRORS FOUND
296166-71
13-65
8044 APPLICATION EXAMPLES
Table 2. PL/M-86 Compiler RUPI/8088 Interface Example
SERIES-III PL/M-86 VI.O COMPILATION OF MODULE RUPI_88
OBJECT MODULE PLACED IN :Fl:R88.0BJ
COMPILER INVOKED BY: PLMB6.86 :FI:R88. SRC
'DEBUG
STITLE ('RUPI/8088 INTERFACE EXAMPLE')
2 DECLARE
LIT LITERALLY 'LITERALLY' ,
TRUE LIT lOtH',
FALSE LIT 'OOH' ,
RECV.BUFFER(64) BYTE,
XM IT :::BUFFER ( 64 ) BYTE.
I BYTE,
WAIT BYTE,
1* 8237 PORTS*I
MASTER _CLEAR_37 LIT 'OFFDDH' ,
COMMAND_37 LIT 'OFFD8H',
ALL_MASK_37 LIT 'OFFDFH',
SINgLE_MASK_37 LIT 'OFFDAH',
STATUS 37 LIT 'OFFDBH',
REOUEST_REG_37 LIT 'OFFD9H',
MODE_REQ_37 LIT 'OFFDBH',
CLEAR_8YTEJ'TR _37 LIT 'OFFDCH' ,
CHO ADDR LIT 'OFFDOH',
CHO::::COUNT LIT 'OFFDIH' ,
CHl_ADDR LIT 'OFFD01H' ,
CHI -,OUNT LIT 'OFFD3H',
CH2_ADDR LIT 'OFFD4H' ,
CH2_COUNT LIT 'OFFD:5H',
CH3_ADDR LIT 'OFFD6H',
CH3_COUNT LIT 'OFFD7H',
1* 8237 BIT ASSIONMENTS .,
CHO_SEL LIT 'OOH',
CHI_SEL LIT 'OIH',
CH2_SEL LIT '02H',
CH3_SEL LIT '03H',
WRITE_XFER LIT '04H',
READ_X FER LIT '08H',
DEMAND_MODE LIT 'OOH',
SINGLE MODE LIT '40H',
BLOCK_HODE LIT '80H',
SET_MASK LIT '04H',
'EJECT
STATUS_POLL :59
'* 8259 PORTS
LIT
"I
'OFFEOH',
ICWI _:59 - LIT 'OFFEOH',
OCWI_59 LIT 'OFFEIH',
OCW2_:59 LIT 'OFFEOH',
OCW3_59 LIT 'OFFEOH',
ICW2_:59 LIT 'OFFEIH',
ICW3_:59 LIT 'OFFEIH',
ICW4_:59 LIT 'OFFE1H' J
,. INTERRUPT SERVICE ROUTINE *1
3 PROCEDURE INTERRUPT 32,
OUTPUT(SINQLE_MAS~_37)-40H'
WAIT-FALSE,
END,
296166-4
13-66
inter 8044 APPLICATION EXAMPLES
Table 2. PL/M-86 Compiler RUPII8088 Interface Example (Continued)
7 DISABLE,
'* INITIALIZE B237 *'
B 1 OUTPUT(MASTER_CLEAR_37) -0,
9 1 OUTPUT (COHMAND_37) -04OH.I
10 1 DUTPUT(ALL_HASK_37) -OFHJ
11 1 DUTPUT(MDDE_REg_37) -(BINgLE_MODE DR WRITE_XFER DR CHO_SEL),
12 1 OUTPUT (MODE_REg_37) -(SINgLE_HODE DR READ_XFER DR CHI_SEU,
13 I OUTPUT(CLEAR_DYTE_PTR_37) -0,
14 I OUTPUT(CHO_ADDR) -OOH;
I' 1 OUTPUT(CHO ADDR) -40HI
Ib 1 OUTPUT (CHO=CDUNT) -641
17 I OUTPUT(CHO_COUNT) -001
IB I OUTPUT(CH1_ADDR) -40H,
1'1 1 OUTPUT(CH1_ADDR) -40H,
20 1 OUTPUT (CHI_COUNT) -641
21 1 OUTPUT(CH1_COUNT) -OOi
,* INITIALIZE a;i!:)9 -I
22 OUTPUT< ICWI_'9) -13H, '*SINgLE MODE, EDgE TRiggERED
INPUT, BOBb INTERRUPT TYPE*I
23 OUTPUT< ICW2_'9) -:ZOH, '*INTERRUPT TYPE 32*,
24 OUTPUT< ICW4_'9) -03H, '<AUTO-EOI<I
2' OUTPUTWCWI_'9) -OFEH, '<ENABLE INTERRUPT LEVEL 0*,
SE.JE:CT
2b CALL SET. INTERRUPT (32,OFF_RECV_DMA), '*LOAD INTERRUPT VECTOR LOCATION*I
27 XMIT_BUFFERCO)-b4, ,*THE FIRST DYTE IN THE BLOCK OF DATA IS THE NUMBER
OF BYTES TO DE TRANSFERED, NOT INCLUDINg THE FIRST BYTE*'
2B 1 DO 1- 1 TO b4, '* FILL UP THE XNIT_BUFFER WITH DATA *1
29 2 XMIT BUFF!:R CI )-1,
30 2 END, -
31 OUTPUT CI\LL_MASK_37)-OFCH, '*ENABLE CHANNEL I AND 2 *'
32 ENABLE,
33 I WAIT-TRUE,
34 I DO WHILE WAIT,
3' 2 END, '* A BLOCK OF DATA WILL BE TRANSFERRED TO THE RUPI.
WHEN THE RUPI RECEIVES A BLOCK OF DATA IT WILL
SEND IT TO THE BOBB MEMORY AND INTERRUPT THE BOBB.
THE INTERRUPT· BERVICE ROUTINE WILL SHUT OFF HIE DMA
CONTROLLER AND SET 'WAIT' FALSE *'
3b I DO WHILE II
37 2 END,
3B END,
MODULE INFORMATION:
CODE AREA SIZE - 00D7H 21'0
CONSTANT AREA SIZE - OOOOH 00
VARIABLE AREA SIZE - 00B2H 1300
MAXIMUM STACK SIZE - 001EH 300
124 LINES READ
o PROgRAM WARNINgS
o PROGRAM ERRORS
END OF PL'M-Sb COMPILATION
296166-5
13-67
intJ 8044 APPLICATION EXAMPLES
A HIGH PERFORMANCE NETWORK
USING THE 8044
2.0 INTRODUCTION The user interface to the driver provides four functions:
OPEN CLOSE, TRANSMIT, and SIU_RECV. Us-
This section describes the design of an SDLC data link ing the~e four functions properly will allow any appli.ca-
using the 8044 (RUPI) to implement a primary station tion software to communicate over this SDLC data Imk
and a secondary station. The design was implerriented without knowing the details of SDLC. The secondary
and tested. The following discussion assumes that the station driver uses the R044's AUTO mode.
reader understands the 8044 and SDLC. This section is
divided into two parts. First the data link design exam- The second module is an example of application soft-
ple is discussed. Second the software modules used to ware which is linked to the secondary station driver.
implement the data link are described. To help the This module drives the 8215A, buffers data, and inter-
reader understand the discussion of the software, flow faces with the secondary station driver's user interface.
charts and software listings are displayed in Appendix
A and Appendix B, respectively. The third module is a primary station, which is a stand-
alone program (i.e., it is not linked to any other mod-
ule). The primary station lIses the 8044's NON-AUTO
APPLICATION DESCRIPTION or FLEXIBLE modc. In addition to controlling the
data link it acts as a message switch. Each time a sec-
This particular data link design example uses a tm I
ondary station transmits a frame, it places the destina-
wire half-duplex multidrop topology as shown in Fig-
tion address of the rraille in the first byte of the infor-
ure 4. In an SDLC multidrop topology the primary
mation or I field. Whcn t he primary station receives a
station communicates with each secondary station. The
frame, it removes the first bytc in the I field and re-
secondary stations communicate only to the primary.
transmits the fralllc to the sccondary station whose ad-
Because of this hierarchial architecture, the logical t 11·
dress matches this hyte.
pology for an SDLC multidrop is a star as shown in
Figure 5. Although the physical topology of this data This network provides two complete layers of the OSI
link is multidrop, the easiest way to understand the
(Open Systems Interconnection) reference model: the
information flow is to think of the logical (star) topoll1·
physical layer and the data link layer. The physical lay-
gy. The term data link in this case refers to the logil'al
er implementation lIses the RS-422 electrical interface.
communication pathwaysbetwecn the primary station
The mechanical nledillm consists of ribbon cable and
and thc secondary stations. The data links are shown in
connectors. The data link layer is defined by SDLC.
Figure 5 as two way arrows. SDLC's usc of acknowledgements and frame number-
ing guarantees that messages will be received in the
The application example uses dumb async terminals. to
same order in which they were sent. It also guarantees
interface to the SDLC network. Each secondary station
message integrity over the data link. However this net-
has an async terminal connected to it. The secondary
work will not guarantee secondary to secondary mes-
stations are in effect protocol converters which allows
sage delivery, since there are acknowledgements be-
any async terminal to communicate with any other
tween secondary stations.
async terminal on the network. The secondary stations
use an 8044 with a UART to convert SDLC to async.
Figure 6 displays a block diagram of the data link. The
primary station, controls the data link. In addition to 2.1 Hardware
data link control the primary provides a higher level The schematic of the hardware is given in Figure 7. The
layer which is a path control function or networking 8251A is used as an async communications controller,
layer. The primary serves as a message exchange or in support of the 8044. TxRDY and RxRDY on the
switch. It receives information from one secondary sta- 8251A are both tied to the two available external inter-
tion and retransmits it to another secondary station. rupts of the 8044 since the secondary station driver is
Thus a virtual end to end connection is made between totally interrupt driven. The 8044 buffers the data and
any two secondary stations on the network. some variables in a 2016 (2K x 8 static RAM). The
8254 programmable interval timer is employed as a
Three separate software modules were written for this programmable baud rate generator and system clock
network. The first module is a Secondary Station Driv- driver for the 8251A. The third output from the 8254
er (SSD) which provides an SDLC data link interface could be used as an external baud rate generator for the
and it user interface. This module is a general purpose 8044. The 2732A shown in the diagram was not used
driver which requires application software to run it.
13-68
8044 APPLICATION EXAMPLES
since the software for both the primary and secondary 2.2 SOLe Basic Repertoire
stations used far less than the 4K bytes provided on the
8744. For the async interface, the standard RS-232 me- The SDLC commands and responses implemented in
chanical and electrical interface was used. For the the data link include the SDLC Basic Repertoire as
SDLC channel, a standard two wire three state RS-422 defined in the IBM SDLC General Information manu-
driver is used. A DIP switch connected to one of the al. Table 3 shows the commands and responses that the
available ports on the 8044 allows the baud rate, parity, primary and the secondary station in this data link de-
and stop bits to be changed on the async interface. The sign recognize and send.
primary station hardware does not use the USART,
8254, nor the RS-232 drivers.
PRIMARY
STATION
SECONOARY SECONDARY SECONDARY
STATION STATION STATION
296166-6
Figure 4. SOLC Multidrop Topology
SECONDARY SECONDARY
STATION STATION
.-
PRIMARY
STATION
SECONDARY SECONDARY
STATION STATION
296166-7
Figure 5. SOLC Logical Topology
13-69
inlef 8044 APPLICATION EXAMPLES
>
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g
z
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ow
VI
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i~ 00 ~
OC
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.
.,
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ilia:
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Figure 6. Block Diagram of the Data Link Application Example
13-70
8044 APPLICATION EXAMPLES
Figure 7. Schematic of Async/SDLC Secondary Station Protocol Converter
13-71
8044 APPLICATION EXAMPLES
Table 3. Data Link Commands and nal. The SSD is independent of the main application, it
Responses Implemented for This Design just provides the SDLC communications. Existing 8051
applications could add high performance SDLC com-
Primary Station munications capability by linking the SSD to the exist-
ing software and providing additional software to be
Responses Commands able to communicate with the SSD.
Recognized Sent
Unnumbered UA SNRM DATA LINK INTERFACE AND USER
OM DISC INTERFACE STATES
FRMR
'RD The SSD has two software interfaces: a data link inter-
face and a user interface as shown in Figure 8. The data
Supervisory RR RR link interface is the part of the software which controls
RNR RNR the SDLC communications. It handles link access,
command recognition/response, acknowledgements,
Information I I and error recovery. The user interface provides four
functions: OPEN, CLOSE, TRANSMIT, and SIU_
Secondary Station RECV. These are the only four functions ·which the
application software has to interface in order' to com-
Commands Responses
municate using SDLC. These four functions are com-
Recognized Sent mon to many 1/0 drivers like floppy and hard disks,
Unnumbered SNRM UA keyboard/CRT, and async communication drivers.
DISC OM
'TEST FRMR The data link and the user interface each have their
own states. Each interface can only be in one state at
'RD
any time. The SSD uses the states of these two interfac-
'TEST es to help synchronize the application module to the
Supervisory RR RR data link.
RNR RNR
REJ There are three states' which the secondary station data
._- link interface can be in: Logical Disconnect State
Information I I (L_D_S), Frame Reject State (FRMR_S), and the
•not Included In tho SDLe BasIc Repertoire Information Transfer State (I_T_S). The Logical
Disconnect Stale is when a station is physically con-
The term command specifically means all frames which nected to the channel but either the primary or second-
the primary station transmits and the secondary sta- ary have not agreed to enter the Information Transfer
tions receive. Response refers to frames which the sec- State. Both the primary and the secondary stations syn-
ondary stations transmit and the primary station re- chronize to enter into the Information Transfer State.
ceives. Only when the secondary station is in the I_T_S is it
able to transfer data or information to the primary. The
Frame Reject State (FRM~S) indicates that the sec-
NUMBER OF OUTSTANDING FRAMES ondary station has lost software synchronization with
the primary or encountered some kind of error condi-
This particular data link design only allows one out- tion. When the secondary station is in the FRMR_S,
standing frame before it must receive an acknowledge- the primary station must reset the secondary to resyn-
ment. Immediate acknowledgement allows the second- chronize. .
ary station drivers to use the AUTO mode. In addition,
one outstanding frame uses less memory for buffering, The user interface has two states, open or closed. In the
and the software becomes easier to manage. closed state, the user program does not want to com-
municate over the network. The communications chan-
nel is closed and not available for use. The secondary
2.3 Secondary Station Driver using station tells the primary this by responding to all com-
AUTO Mode mands with DM. The primary continues to poll the
secondary in case it wants to enter the I_T_S state.
The 8044 secondary station driver (SSD) was written as When the user program begins communication over the
a general purpose SDLC driver. It was written to be data link it goes into the open state. It does this by
linked to an application module. The application soft- calling the OPEN procedure. When the user interface is
ware implements the actual application in addition to in the open state it may transfer information to the
interfacing to the SSD. The main application could be, primary.
a printer or plotter, a medical instrument, or a termi-
13-72
8044 APPLICATION EXAMPLES
SECONDARY STATION
APPLICATION SECONDARY
MODULE STATION
DRIVER
MODULE
DATA
LINK
INTERFACE
SSD
INTERFACE USER DATA LINK
11 to. INTERFACE STATES
V
1. LOGICAL
V USER STATES DISCONNECT
SSD
~ 1. OPEN
STATE
2. INFORMATION
TRANSFER
INTERFACE 2. CLOSED STATE
PROCEDURES oJ
3. FRAME W
REJECT Z
STATE
z
«
OPEN :I:
U
CLOSE oJ
TRANSMIT «
SIU RECV u
en
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II.
296166-10
Figure 8. Secondary Station Software Modules
13-73
intJ 8044 APPLICATION EXAMPLES
SECONDARY STATION COMMANDS, - There is a buffer overrun.
RESPONSES AND STATE TRANSITIONS - The Nr that was received from the primary station
is invalid.
Table 4 s,hows the commands which the secondary sta-
tion recognizes and the responses it generates, The first The secondary station cannot leave the FRM~S until
row in Table 4 displays commands the secondary sta- it receives a SNRM or a DISC command.
tion recognizes and each column shows the potential
responses with respect to secondary station, For exam-
ple, if the secondary is in the Logical Disconnect State SOFTWARE DESCRIPTION OF THE SSD
it will only respond with DM, unless it receives a
SNRM command and the user state is open, If this is To aid in following the description of the software, the
the case, then the response will be UA and the second- reader may either look at the flow charts which are
ary station will move into the I_T_S, given for each procedure, or read the PL/M-51 listing
provided in Appendix A,
Figure 9 shows the state diagram of the secondary
station. When power is first applied to the seconda ry A block diagram of the software structure of the SSD is
station, it goes into the Logical Disconnect State. As given in Figure 10. A complete module is identified by
mentioned above, the I_T_S is entered when the sec- the dotted box, and a procedure is identified by the
ondary station receives a SNRM command and the solid box. Therefore the SIU_RECV procedure is not
user state is open. The seco~dary responds with UA to included in the SSD module, it exists in the application
let the primary know that it has accepted the SNRM software. Two or more procedures connected by a solid
and is entering the I_T_S. The I_T_S can go into line means the procedure above calls the procedure be-
either the L_D_S or the FRMR_S. The I T S low. Transmit, Power_on_D, Close, and Open are all
goes into the L_D_S if the primary sends the sec~ called by the application software. Procedures without
ary DISC. The secondary has to respond with UA, and any solid lines connected above are interrupt proce-
then goes into the L_D_S. If the user interface dures. The only interrupt procedure in the SSD module
changes from open to close state, then the secllndary is the SIU_INT.
sends RD. This causes the primary to send a DISC.
The entire SSD module is interrupt driven. Its design
The FRMR_S is entered when a secondary station is allows the application program to handle real time
in the I_T_S and either one of the following <"<'lIdi· events or just dedicate more CPU time to the applica-
tions occurs. tion program, The SIU_INT is the only interrupt pro-
cedure in the SSJ), It is automatically entered when an
A command can not be recognized by the secolld· SIU interrupt occurs. This particular interrupt can be
ary station. the lowest priority interrupt in the system.
Table 4. Secondary Station Responses to Primary Station Commands
Data Link Primary Station-Commands
States I RR RNR SNRM DISC TEST
Information I I I
Transfer State RR RR RR
RNR RNR RNR
RD RD RD RD RD
FRMR FRMR FRMR
UA UA
Test
Logical
Disconnect State OM OM OM OM OM OM
UA
Frame FRMR FRMR FRMR FRMR
Reject State UA UA
13-74
8044 APPLICATION EXAMPLES
296166-11
Figure 9. State Diagram of Secondary Station
13-75
inter 8044 APPLICATION EXAMPLES
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1._._.-.- _._._._. ._._._.1
Figure 10. Secondary Station Driver
13-76
8044 APPLICATION EXAMPLES
SSD INITIALIZATION reasons for the SIU to automatically leave the AUTO
mode. The following is a list of these reasons, and the
Upon reset the application software is entered first. The responses given by the SSD based on each reason.
application software initializes its own variables then I. The SIU has received a command field it does not
calls Power_On_D which is the SSD's initialization recognize.
routine. The SSD's initialization sets up the transmit
and receive data buffer pointers (TBS and RBS), the Response: If the CPU recognizes the command, it
receive buffer length (RBL), and loads the State vari- generates the appropriate response. If neither the
ables. The STATION_STATE begins in the L_D_S SIU nor the CPU recognize the command, then a
state, and the USER_STATE begins in the closed FRMR response is sent.
state. Finally Power_On_D initializes XMIT_ 2. The SIU has received a Sequence Error Sent
BUFFER_EMPTY which is a bit flag. This flag (SES = I in NSNR register). Nr(P)* Ns(S) + I, and
serves as a semaphore between the SSD and the appli- Nr(P)*Ns(S).
cation software to indicate the status of the on chip Response: Send FRMR.
transmit buffer. The SSD does not set the station ad-
dress. It is the application software's responsibility to J. A buffer overrun has occurred. BOV= I in STS reg-
do this. After initialization, the SSD is read to respond ister.
to all of the primary station commands. Each time a Response: Send FRMR.
frame is received with a matching station address and a .\. An I frame with data was received while RPB = 1.
good CRC, the SIU_INT procedure is entered.
Response: Go back into AUTO mode and send an
AUTO mode response
SIU_INT PROCEDURE
III addition to the above reasons, there is one condition
The first thing the SIU_INT procedure clears is the where the CPU forces the SIU out of the AUTO mode.
serial interrupt_bit (SI) in the STS register. If the This is discussed in the SSD's User IlIkri'ace Proce-
•
SIU_INT procedure returns with this bit set, another dmes section in the CLOSED procedure dl'scription
SI interrupt will occur.
Finally, case three is when the STAT I( )N .STATE is
The SIU_INT procedure is branches three indepen- in the I_T_S and the AUTO nHltk. Thl' CPU tirst
dent cases. The first case is entered if the STATION_ looks at the TBF bit. If this bit is () th"11 Ihe interrupt
STATE is not in the I_T_S. If this is true, then the may have been caused by a frame whie-h II':IS transmit-
SIU is not in the AUTO mode, and the CPU will have ted and acknowledged. Therefore 1111' :\MIT_BUFF-
to respond to the primary on its own. (Remember that E1~_EMPTY flag is set again, indil':Ililll'. that the ap-
the AUTO mode is entered when the STATION_ plication software can transmit anol kr i'rame.
STATE enters into I_T_S.) If the STATION_
STATE is in the I_T_S, then either the SIU has just The other reason this section of code L'ould be entered
left the AUTO mode, or is still in the AUTO mode. is if a valid I frame was received. WIH'II a good I frame
This is the second and third case, respectively. is received the RBE bit equals O. This means that the
receiver is disabled. If the primary were to poll the 8044
In the first case, if the STATION_STATE is not in while RBE= 0, it would time out since no response
the LT_S, then it must be in either the L_D_S or would be given. Time outs reduce nclwork throughput.
the FRMR-S. In either case a separate procedure is To improve network performance, the CPU first sets
called based on which state the station is in. The In_ RBP, then sets RBE. Now when the primary polls the
Disconnect_State procedure sends to the primary a 8044 an immediate RNR response is given. At this
DM response, unless it received a SNRM command point the SSD calls the application software procedure
and the USER_STATE equals open. In that case the SIU_RECV and passes the length of the data as a
SIU sends a UA and enters into the I_T_S. The In_ parameter. The SIU_RECV procedure reads the data
FRMR_State procedure will send the primary the out of the receive buffer then returns to the SSD mod-
FRMR response unless it received either a DISC or an ule. Now that the receive information has been trans-
SNRM. If the primary's command was a DISC, then ferred, RBP can be cleared.
the secondary will send a UA and enter into the L_
D_S. If the primary's command was a SNRM, then
the secondary will send a UA, enter into the I_T_S, COMMAND_DECODE PROCEDURE
and clear NSNR register.
The Command_Decode procedure is called from the
For the second case, if the STATION_STATE is in SIU_INT procedure when the STATION_STATE
the I_T_S but the SIU left the AUTO mode, then the = I_T_S and the SIU left the AUTO mode as a
CPU must determine why the AUTO mode was exited, result of not being able to recognize the receive control
and generate a response to the primary. There are four byte. Commands which the SIU AUTO mode does not
13-77
inter 8044 APPLICATION EXAMPLES
C-FIELD OF THE REJECfED COMMAND, AS RECEIVED
I
THIS STATION'S PRESENT Ns
, , o
I THIS STATION'S PRESENT Nr
o
~
W X y Z o o
..
o o
HIGH-ORDER
RECEIVED DISAGREES WITH TRA NSMITTED Ns
I I
BUFFER OVERRUN (I-FIELD IS TO o LONG)
PROHIBITED I-FIELD RECEIVED
INVALID OR NONIMPLEMENTED COMMAND
296166-13
Figure 11_ Information Field of the FRMR Response, as Transmitted
recognize are handled here. The commands recognized field. Figure J I displays the format for the three data
in this procedure are: SNRM, DISC, and TEST. AllY bytes in the I field of a FRMR response. The XMIT_
other command received will generate a Frame Reject FRMR procedure sets up the Frame Reject response
with the nonimplemented command bit set in the third frame based Oil the parameter REASON which is
data byte of the FRMR frame. Any additional unnum- passed to it. Each place in the SSD code that calls the
bered frame commands which the secondary station is XMIT_FRMR procedure, passes the REASON that
going to implement, should be implemented in this pro- this procedure was called, which in turn is communi-
cedure. cated to the primary station. The XMIT_FRMR pro-
cedure uses three bytes of internal RAM which it ini-
IF an SNRM is received the command_decode proce- tializes for the correct response. The TBS and TBL reg-
. dure calls the SNRM_Response procedure. The isters are then changed to point to the FRMR buffer so
SNRM_Response procedure sets the STATION_ that when a response is sent these three bytes will be
STATE = I_T_S, clears the NSNR register and re- included in the I field.
sponds with a UA frame. If a DISC is received, the
command_decode procedure sets the STATION_ The IN_FRMR....STATE procedure is called by the
STATE = L_D_S, and responds with a UA frame. SIU_INT procedure when the STATION_STATE
When a TEST frame is received, and there is no buffer already is in the FRMR state and a response is re-
overrun, the command_decode procedure responds quired. The IN_FRMR....STATE procedure will only
with a TEST frame retransmitting the same data it re- allow two commands to remove the secondary station
ceived. However if a TEST frame is received and there from the FRMR state: SNRM and DISC. Any other
is a buffer overrun, then a TEST frame will be sent command which is received while in the FRMR state
without any data, instead of a FRMR with the buffer will result in a FRMR response frame.
overrun bit set.
XMIT_UNNUMBERED PROCEDURE
FRAME REJECT PROCEDURES
This is a general purpose transmit procedure, used only
There are two procedures which handle the FRMR in the FLEXIBLE mode, which sends unnumbered re-
state: XMIT_FRMR and IN_FRMR_STATE. sponses to the primary. It accepts the control byte as a
XMIT_FRMR is entered when the secondary station parameter, and also expects the TBL register to be set
first goes into the FRMR state. The frame reject re- before the procedure is called. This procedure waits un-
sponse frame contains the FRMR response in the com- til the frame has been transmitted before returning. If
mand field plus three additional data bytes in the I
13-78
8044 APPLICATION EXAMPLES
this procedure returned before the transmit interrupt application software thinks that the SDLC channel is
was generated, the SIU_INT routine would be en- now open and it can transmit. This is not the case. For
tered. The SIU_INT routine would not be able tp dis- the channel to be open, the SSD must receive an
tinguish this condition. SNRM from the primary and respond with a UA.
However, the SSD does not want to hang up the appli-
SSD's User Interface Procedures-OPEN, CLOSE, cation software waiting for an SNRM from the primary
TRANSMIT, SIU_RECV-are discussed in the fol- before returning from the OPEN procedure. When the
lowing section. TRANSMIT procedure is called, the SSD expects the
STATION_STATE to be in the I_T_S. If it isn't,
The OPEN procedure is the simplest of all, it changes the SSD refuses to transmit the data. The TRANSMIT
the USER_STATE to OPEN_S then rdurns. This procedure first checks to see if the USER_ST ATE is
lets the SSD know that the user wants to open the open. If not, the USER-STATE_CLOSED parame-
channel for communications. When the SSD receives a ter is passed back to the application module. The next
SNRM command, it checks the USER_STATE. If the thing TRANSMIT checks is the STATION_STATE.
USER_STATE is open, then the SSD will respond If this is not open, then TRANSMIT passes back
with a VA, and the STATION_STATE enters the LINK_DISCONNECTED. This means that the
I_T_S. USER_STATE is open, but the SSD hasn't received
an SNRM command from the primary yet. Therefore,
The CLOSE procedure is also simple, it changes. the the application software should wait awhile and try
USER_STATE to CLOSED_S and sets the AM bit again. Based on network performance, one knows the
to O. Note that when the CPU sets the AM bit to 0 it maximum amount of time it will take for a station to be
puts the SIU out of the AUTO mode. This event is polled. If the application software waits this length of
asynchronous to the events on the network. As a result time and tries again but still gets a LINK_DISCON-
an I frame can be lost. This is what can happen. NECTED parameter passed back, higher level recovery
1. AM is set to 0 by the CLOSE Procedure.
2. An. I frame is received and an SI interrupt occurs.
3. The SIU_INT procedure enters case 2 (STA-
TION_STATE = I_T_S, and AM = 0).
must be implemented.
Before loading the transmit buffer and calling the
TRANSMIT procedure, the application software must
check to see that XMIT_BUFFER_EMPTY I.
II
4. Case 2 detects that the USER-STATE This flag tells the application software that it can write
CLOSED_S, sends an RD response and ignores the new data into the transmit buffer and call the TRA NS-
fact that an I frame was received. MIT procedure. At'!er the application sot'! ware has va-
itied that XMIL BUFFER_EMPTY I, it lills the
Therefore it is advised to never call the CLOSE proce- transmit bufTer with the data and calls the TRANS-
dure or take the SIU out of the AUTO mode when it is MIT procedure passing the length of' the bulTer as a
receiving I frames or an I frame will be lost. parameter. The TRANSMIT procedure checks for
three reasons why it might not be able to transmit the
For both the TRANSMIT and SIU_RECV proce- frame. If any of these three reasons arc true, the
dures, it is the application software's job to put data TRANSMIT procedure returns a parameter explaining
into the transmit buffer, and take data out of the re- why it couldn't send the frame. If the application soft-
ceive buffer. The SSD does not transfer data in or out ware receives one of these responses, it must rectify the
of its transmit or receive buffers because it does not problem and try again. Assuming these three condi-
know what kind of buffering the application software is tions are false, then the SSD clears XMIT_BUFF-
implementing. What the SSD does do is notify the ap- ER_EMPTY, attempts to send the data and returns
plication software when the transmit buffer is empty, the parameter DAT~TRANSMITTED. XMIT_
XMIT_BUFFER_EMPTY = 1, and when the re- BUFFER_EMPTY will not be set to 1 again until the
ceive buffer is full. data has been transmitted and acknowledged.
One of the functions that the SSD performs to synchro- The SIU_RECV procedure must be incorporated into
nize the application software to the SDLC data link. the application software module. When a valid I frame
However some of the synchronization must also be . is received by the SIU, it calls the SIU_RECV proce-
done 'by the application software. Remember that the dure and passes the length of the received data as a
SSD does not want to hang up the application software parameter. The SIU_RECV procedure must remove
waiting for some event to occur on the SDLC data link, all of the data from the receive buffer before returning
therefore the SSD always returns to the application to the SIU_INT procedure.
software as soon as possible.
For example, when the application software calls the
OPEN procedure, the SSD returns immediately. The
13-79
inter 8044 APPLICATION EXAMPLES
LINKING UP TO THE SSD· The SSD module uses the $REGISTERBANK(I) attri-
bute. Some procedures are modified with the USING
Figure 12 shows the necessary parts to include in a attribute based on the register bank level of the calling
PL/M-S I application program that will be linked to the procedure.
SSD module. RLS I is used to link and locate the SSD
and application modules. The command line used to do
this is: 2.4 Application Module; ASYNC to
SOLC Protocol Converter
RL51 SSD.obj,filename.obj,PLM51.LIB TO One of the purposes of this application module is to
filename & RAMSIZE(192) demonstrate how to interface software to the SSD. An-
other purpose is to implement and test a practical appli-
$registerbank(O) cation. This application software performs I/O with an
user$mod: do; async terminal through a USART, buffers data, and
$include (reg44.dcl) also performs I/O with the SSD. In addition, it allows
declare the user on the async terminal to: set the station ad-
lit Ii terally 'literally', dress, set the destination address, and go online and
buffer_length lit 'SO', omine. Setting the station address sets the byte in the
siu_xmiLbuffer STAD register. The destination address is the first byte
(buffer_length) byte external idatn, in the I field. Going online or omine results in either
siu_recv_buffer calling the OPEN or CLOSE procedure respectively.
(buffer_length) byte external,
xmit_buffer_empty bit external; After the secondary station powers up, it enters the
'terminal mode', which accepts data from the terminal.
/* external procedures '/ However, before any data is sent, the user must con-
figure the station. The station address and destination
power_on_d: procedure extornal; address must he set, and the station must be placed
end powor_on_d; online. To configure the station the ESC character is
entered at the terminal which puts the protocol con-
close: procodure ext a rnal using 1; verter into the 'configure mode'. Figure 13 shows the
end clo:;o; menu which appcars on the terminal screen.
opon: procodure exte rna 1 using 1;
and opon; (1)8044 Sccondary Station
/
transmit: procedure
(xmit_buffer_length) byte external; 1- Set the Station Address
declare xmit_buffer_length byte; 2- Set the Destination Address
end transmit; 3- Go Online
4- Go Omine
/' local procedures '/ S- Return to terminal mode
Enter option _
siu_recv: procedure (length) using 1;
public' Figure 13. Menu for the Protocol Converter
declare length byte,
In the terminal mode data is buffered up in the second-
'. ary station. A Line Feed character 'LF' tells the sec-
ondary station to send an I frame. If more than 60 bytes
are buffered in the secondary station when a 'LF' is
received, the applications software packetizes the data
Figure 12. Applications Module Link Information into 60 bytes or less per frame. If a LF is entered when
the station is omine, an error message comes on the
screen which says 'Unable to Get Online'.
PL/M-51 AND REGISTER BANKS
The 8044 has four register banks. PL/M-SI assumes The secondary station also does error checking on the
that an interrupt procedure never uses the same bank as async interface for Parity, Framing Error, and Overrun
the procedure it interrupts. The USING attribute of a Error. If one of these errors are detected, an error mes-
procedure, or the $REGISTERBANK control, can be sage is displayed on the terminal screen.
used to ensure that.
13-80
inter 8044 APPLICATION EXAMPLES
MULTIO RO P
SOLC OATALINK
.
w ....
-~.;,
0: ....
.... 0:
0: 0:
w w
u. u.
u. u.
::> ::::>
GI CD
W 0-
> i
iii
0
w
0:
'"z<!
a:
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II:
...J
GI CD 0:
W
t-
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W
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iii
0
~ ....'" 0-
i
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C
0:
....I
W
II: --z
C
6u.
0-
6u.
0:
w
I-
iL )(
iL w
0 w ....
Z
>
III
- ....
0:'"
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C .. 0:
I-
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ro~;
...J
C
o~
Z~
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IIlw
CI-
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117
. t I'"
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Figure 14. Block Diagram of Secondary Station Protocol Converter illustrating Buffering
13-81
inter 8044 APPLICATION EXAMPLES
BUFFERING next loop which polls the XMIT_BUFFER_EMP-
TY bit. When XMIT_BUFFER_EMPTY equals I,
There are two separate buffers in the application mod- the SIU_XMIT_BUFFER can be loaded. The first
ule: a transmit buffer and a receive buffer. The transmit byte in the buffer is loaded with the destination address
buffer receives data from the USART, and sends. data while the rest of the buffer is loaded with the data.
to the SSD. The receive buffer receives data from the Bytes are removed from the transmit FIFO and placed
SSD, and transmits data to the USART. Each buffer is into the SIU_XMIT_BUFFER until one of three
a 256 byte software FIFO. If the transmit FIFO be- things happen: 1. a 'LF' character is read out of the
comes full and no 'LF' character is received, the sec- FIFO, 2. the number of bytes loaded equals the size of
ondary station automatically begins sending the data: the SIU_XMIT_BUFFER, or 3. the transmit FIFO
In addition, the application modules will shut off the is empty.
terminal's transmitter using CTS until the FIFO has
been partially emptied. A block diagram of the buffer- After the SIU_XMIT_BUFFER is filled, the SSD
ing for the protocol converter is given in Figure 14. TRANSMIT procedure is called and the results from
the procedure are checked. Any result other than·
DAT~TRANSMITTED will result in several retries
APPLICATION MODULE SOFTWARE within a finite amount of time. If all the retries fail,
then the LINK_DISC procedure is called which sends
A block diagram of the application module software is
a message to the terminal, 'Unable to Get Online'.
given in Figure 15. There are three interrupt routines in
this module: USART_RECV_INT, USART__
XMIT_INT, and TIMEIL-O_INT. The first two arc
for servicing the USART. TIMER_O_INT is used if
the TRANSMIT procedure in the SSD is called and When the 8251A receives a character, the RxRDY pin
does not return with the DATA_TRANSMITTED on the 8251A is activated, and this interrupt procedure
parameter. TIMEIL-O_INT employs Timer to wait °
a finite amount of time before trying to transmit again.
is entered. The routine reads the USART status register
to determine if there are any errors in the character
The highest priority interrupt is USART_RECV. _ received. If there are, the character is discarded and the
INT. The main program and all the procedures it calls ERROR procedure is called which prints the type of
use register bank 0, USART_XMIT.-INT and TIM- error on the screen. If there arc no errors, the received
ER_O_INT and FIFO_IL-OUT use bank I, while character is checked to see if it's an ESC. If it is an
USART_RECV_INT and all the procedures it calh ESC, the MENU procedure is called which allows the
use register bank 2. user to change t he configuration. If neither one of these
two conditions exists, the received character is inserted
into the transmit I'lFO. The received character mayor
POWER_ON PROCEDURE may not be echoed back to the terminal based on the
dip switch settings. .
The Power_On procedure initializes all of the chips in
the system including the 8044. The 8044 is initialized to
use the on-chip DPLL with NRZI coding, PreFrame TRANSMIT FIFO
Sync, and Timer I auto reload at a baud rate of
62.5 Kbps. The 8254 and the 8251A are initialized ncxt The transmit FIFO consists of two procedures: FIFO_
based on the DIP switch values attached to port I on T_IN and FIFO_T_OUT. FIFO_T_IN inserts a
the 8044. Variables and pointers are initialized, then the character into the FIFO, and FIFO_T_OUT re-
SSD's Power-Up Procedure, Power_On_D, is called. moves a character from the FIFO. The FIFO itself is
Finally, the interrupt system is enabled and the main an array of 256 bytes called FIFO_T. There are two
program is entered. pointers used as indexeS in the array to address the
characters: IN_PTIL-T and OUTJTR_T. IN_
PTIL-T points to the location in the array which will
MAIN PROGRAM store the next byte of data inserted. OUT_PTIL-T
The main program is a simple loop which waits for a points to the next byte of data removed from the array.
frame transmit command. A frame transmit command Both IN_PTIL-T and OUT_PTR_T are declared
is indicated when the variable SEND_DATA is great- as bytes. The FIFO_T_IN procedure receives a char-
er than 0. The value of SEND_DATA equals the acter from the USART_RECV _INT procedure and
number of'LF' characters in the transmit FIFO, hence stores it in the array location pointed to by IN_PTIL-
it also indicates the number of frames pending trans- T, then IN_PTR_T is incremented. Similarly, when
mission. Each time a frame is sent, SEND_DATA is FIFO_T_OUT is called by the main program, to
decremented by one. Thus when SEND_DATA is load the SIU_XMIT_BUFFER, the byte in the array
greater than 0, the main program falls down into the
13-82
8044 APPLICATION EXAMPLES
----------------------------~-------1
I
I
a: I
~
a:
I
w I
I
I
I
I
I
I
-,
z
I-
I
I
0' I
IL
iL I
I
I
o(,) I
I
I
~
a:
I
I
i
Go I
z
I I
C
:Ii
I
::>
z I
w
:Ii I
I
I
--, I
I
L _____ ,
'------, I
Q
I
Z
o W
I
ri:
<II I
w
~ I
~
Go
I
I
I
L
Figure 15. Block Diagram of User Software
13-83
inter 8044 APPLICATION EXAMPLES
pointed to by OUT_PTR_T is read, then OUT_ stations and receives responses from them. The primary
PTR_T is incremented. Since IN_PT~T and station controls link access, link level error recovery,
OUT_PTR_T are always incremented, they must be and the flow of information. Secondaries can only,
able to roll over when they hit the top of the 256 byte transmit when polled by the primary.
address space. This is done automatically by having
both IN_PTR_T and OUT_PTR_T declared as Most primary stations are either micro/minicomputers,
bytes. Each character inserted into the transmit FIFO or front end processors to a mainframe computer. The
is tested to see if it's a LF. If it is a LF, the variable example primary station in this design is standalone. It
SEND_DATA is incremented, which lets the main is possible for the 8044 to be used as an intelligent front
program know that it is time to send an I frame. Simi- end processor for a microprocessor, implementing the
larly each character removed from the FIFO is tested. primary statioll functions. This latter type of design
SEND_DATA is decremented for every LF character would extensively off-load link control functions for the
removed from the FIFO. microprocessor. The code listed in this paper can be
used as the basis for t his primary station design. Addi-
IN_PTR_T and OUTJTR_T are also used to in- tional software is required to interface to the micro-
dicate how many bytes are in the FIFO, and whether it processor. A hardw:lrc design example for interfacing
is full or empty. When a character is placed into Ihe the 8044 to a microprocessor can be found in the appli-
FIFO and IN_PTR_T is incremented, the FIl-() is cations section of Ihis 1':llldbook.
full if IN_PTR_T equals OUT_PTR_T. Whell :I
character is read from the FIFO and OUT_PTI{ T The primary statioll III list know the addresses of all the
is incremented, the FIFO is empty if OUT_PTI{ T stations which will hl' on Ihe network. The software for
equals IN_PTR_T. If the FIFO is neither full 1ltlJ" this primary needs 10 know this before it is compiled,
empty, then it is in use. A byte called BUFFFI{ however a more flexible syslem would download these
STATUS_T is used to indicate one of these threc l',",· parameters.
ditions. The application module uses the buffer sl:llllS
information to control the flow of data into and 0111 01' From the listing of the software it can be seen that the
the FIFO. When the Iransmit FIFO is empty, the "':lill variable NUMBER_OF_STATIONS is a literal dec-
program must stop loading bytes into the S 1\ J_ laration, which is 2 in this design example. There were
XMIT_BUFFER. Just before the FIFO is full. Ihe three stations tested on this data link, two secondaries
async input must be shut off using CTS. Also. if the and one printary. Following the NUMBER_OF_
FIFO is full and SEND_DATA = 0, then SFNJ) __ STATIONS declaration is a table, loaded into the ob-
DATA must be incremented to automatically selld Ihe ject code file at COlli pile time, which lists the addresses
(\:It:l without an LF. of each secondary station on the network.
RECEIVE FIFO REMOTE STATION DATABASE
The receive FIFO operates in a fashion similar lot he The primary station keeps a record of each secondary
transmit FIFO. Data is inserted into the receive FIFO station on the network. This is called the Remote Sta-
from the SIU_RECV procedure. The SIU._RECV tionDatabase (RSD). The RSD in this software is an
procedure is called by the SIU_INT procedure when a array of structures, which can be found in the listing
valid I frame is received. The SIU_RECV procedure and also in Figure 16. Each RSD stores the necessary
merely polls the receive FIFO status to see if it's full information about that secondary station.
before transferring each byte from the SIU_RECV_
BUFFER into the receive FIFO. If the receive FIFO is To add additional secondary stations to the network,
full, the SIU_RECV procedure remains polling the one simply adjusts the NUMBER_OF_STATIONS
FIFO status until it can insert the rest of the data. In declaration, and adds the additional addresses to the
the meantime, the SIU AUTO mode is responding to SECONDARY_ADDRESSES table. The number of
all polls from the primary with a RNR supervisory RSDs is automatically allocated at compile time, and
frame. The USART_XMIT_INT interrupt proce- the primary automatically polls each station whose ad-
dure removes data from the receive FIFO and trans- dress is in the SECONDARY_ADDRESSES table.
mits it to the terminal. The USART transmit interrupt
remains enabled while the receive FIFO has data in it. Memory for the RSDs resides in external RAM. Based
When the receive FIFO becomes empty, the USART on memory requirements for each RSD, the maximum
transmit interrupt is disabled. number of stations can be easily buffeted in external
RAM. (254 secondary stations is the maximum number
SDLC will address on the data link; i.e. 8-bit address,
2.5 Primary Station FF H is the broadcast address, and 0 is the null ad-
dress. Each RSD uses 70 bytes of RAM. 70 x 254
The primary station is responsible for controlling the 17,780.)
data link. It issues commands to the secondary
13-84
8044 APPLICATION EXAMPLES
The station state, in the RSD structure, maintains the PRIMARY STATION SOFTWARE
status of the secondary. If this byte indicates that the
secondary is in the DISCONNECT_S, then the pri- A block diagram of the primary station software is
mary tries to put the station in the LT_S by sending shown in Figure 17. The primary station software con-
an SNRM. If the response is a UA then the station sists of a main program, one interrupt routine, and sev-
state changes into the I_T_S. Any other frame re- eral procedures. The POWER-ON procedure begins
ceived results in the station state remaining in the DIS- by initializing the SIU's DMA and enabling the receiv-
CONNECT_S. When the RSD indicates that the sta-
tion state is in the LT_S, the primary will send either
an I, RR, or RNR comniand, depending 011 the local
°
er. Then each RSD is initialized. The DPLL and the
timers are set, and finally the TIMER interrupt is
enabled.
and remote buffer status. When the station state equals
GO_TO_DISC the primary will s.:nd a DISC com- .The main program consists of an iterative do loop with-
mand. If the response is a UA fram.:, the station state in a do forever loop. The iterative do loop polls each
will change to DISCONNECT_S, else the station s.:condary station once through the do loop. The vari-
state will remain in GO_TO_DISC. The station stat.: able STATION_NUMBER is the counter for the iter-
is set to GO_TO_DISC wh.:n one of the following ative do statement which is also used as an index to the
responses occur: array ofRSD structures. The primary station issues one
1. A receive buffer overrun in til<! primary. command and receives one response from every second-
a ry station each time through the loop. The first state-
2. An I fram.: is recd ved and N r(l') =1= Ns(S). lI1.:nt in the loop loads the secondary station address,
3. An I frame or a Supervisory frame is received and indexed by STATION_NUMBER into the array of
Ns(P) + 1 *- Nr(S) and Ns(J') *- Nr(S). th.: RSD structures. Now when the primary sends a
4. A FRMR response is received. command, it will have the secondary's address in the
address field of th.: fram.:. Th.: automatic address rec-
5. An RD response is received. ognition feature is us.:,1 by the primary to recognize the
6. An unknown response is received. response from'th.: secondary.
The send count (Ns) and receive count (Nr) are also
maintained in the RSD. Each time an I frame is sent by
the primary and acknowledged by the secondary, Ns is
incremented. Nr is incremented each time a valid I
N.:xt, the main program determines the secondary sta-
tion's state. Based on this state, the primary knows
what command to s.:nd. If the station is in the DIS-
CONNECT_S, the primary t.:alls til<! SNRM.......:P pro-
II
frame is received. BUFFER-STATUS indicates the t.:edure to try and put the secondary in thl" I_T_S. If
status of the secondary station's buffer. If an RR re- the station state is in the GO_H>... DISC state, the
sponse is received, BUFFER_STATUS is set to DISC_P is called 10 try and pul th.: sel"tlndary in the
BUFFER..;...READY: If a RNR response is received, L_D_S. If the secondary is in neither one of the
BUFFER-STATUS is set to BUFFER-NOT_ above two staks, then it is in the I. :I"_S. When th.:
READY. secondary is in the I_T_S, the primary could send
one of three commands: I, RR, or RNR. If the RSD's
buffer has data in it, indicated by INFO_LENGTH
BUFFERING being greater than zero, and the secondary's BUFF-
ER-STATUS equals BUFFER_READY, then an I
The buffering for the primary station is as follows:
frame will be sent. Else if RPB = 0, an RR supervisory
within each RSD is a 64 byte array buffer which is
frame will be sent. If neither one of these cases is true,
initially empty. When the primary receives an I frame,
then an RNR will be sent. The last statement in the
it looks for a match between the first byte of the I frame
main program checks the RPB bit. If set to one, the
and the addresses of the secondaries on the network. If
BUFFER-TRANSFER procedure is called, which
a match exists, the primary places the data in the RSD
transfers the data from the SIU receive buffer to the
buffer of the destination station. The INFO_
appropriate RSD buffer.
LENGTH in the RSD indicates how many bytes are in
the buffer. If INFO_LENGTH equals 0, then the
buffer is empty. The primary can buffer only one I
frame per station. If a second I frame is received while
the addressed secondary'S RSD buffer is full, the pri-
mary cannot receive any more I frames. At this point
the primary continues to poll the secondaries using
RNR supervisory frame.
13-85
inter 8044 APPLICATION EXAMPLES
maximum frame length time comes from the fact the
RSD STATION-ADDRESS 8044 does not generate an interrupt from a received
STATION-STATE frame until it has been completely received, and the
CRC is verified as correct. This means that the time-
NS
out is bit rate dependent.
NR
BUFFER-STATUS
INFO-LENGTH
Ns AND Nr CHECK PROCEDURES
DATA (0) Each time an I frame or supervisory frame is received,
the Nr field in the control byte must be checked. Since
this data link only allows one outstanding frame, a val-
id Nr would satisfy either one of two equations;
Ns(P) + I = Nr(S) the I frame previously sent by the
primary is acknowledged, Ns(P) = Nr(S) the I frame
previously sent is not acknowledged. If either one of
these two cases is true, the CHECK_NR procedure
returns a parameter of TRUE; otherwise a FALSE pa-
rameter is returned. If an acknowledgement is received,
DATA (63)
the Ns byte in the RSD structure is incremented, and
the Information buffer may be cleared. Otherwise the
Figure 16. Remote Station Database Structure information buffer remains fulL
RECEIVE TIME OUT When an I fmmc is received, the Ns field has to be
checked also. If Nr(P) = Ns(S), then the procedure
Each time a frame is transmitted, the primary sels a returns TRUE, otherwise a FALSE is returned.
receive time out timer; Timer O. If a response is nol
received within a certain time, the primary returns to
thc main program and continues polling the rest of the RECEIVE PROCEDURE
stations. The minimum length of time the primary The receive procedurc is called when a supervisory or
should wait for a response ean be calculated as the sum information fram" is scnt, and a response is received
of the following parameters_ before the tilllc-out period. The RECEIVE procedure
I. Propagation time to the secondary station can be brokcn down into three parts. The first part is
2. Clear-to-send at the secondary station's DCE entered if an I frame is received. When an I frame is
received, Ns, Nr ano buffer overrun are checked. If
3. Appropriate time for secondary station processing there is a buffer overrun, or there is an error in either
4. Propagation time from the secondary station Ns or Nr, then the station state is set to GO_TO_
5. Maximum frame length time DISC. Otherwise Nr in the RSD is incremented, the
receive field length is saved, and the RPB bit is set. By
The clear-to-send time and the propagation time arc incrementing the Nr field, the I frame just received is
negligible for a local network at low bit rates. However, acknowledged the next time the primary polls the sec-
the turnaround time and the maximum frame length ondary with an I frame or a supervisory frame. Setting
time are significant factors. Using the 8044 secondaries RBP protects the received data, and also tells the main
in the AUTO mode minimizes turnaround time. The program that there is data to transfer to one of the RSD
buffers.
13-86
inter 8044 APPLICATION EXAMPLES
MAIN PROGRA.M
BUFFER TRANSFER·
ITIMER _ 0 _ INT I
296166-16
Figure 17. Block Diagram of Primary Station Software Structure
If a supervisory frame is received, the Nrfield is
checked. If a FALSE is returned, Ihen the station state
is set to GO_TO~ISC. If the supervisory frame re-
ceived was an RNR, buffer status is set to not ready. If
the response is not an I frame, 1101' a supervisory frame,
state is set to GO_TO_DISC. However, if the frame
received is a FRMR, Nr ill the second data byte of the I
field is checked to see if the secondary acknowledged an
I frame n:ceived before it went into the FRMR state. If
this is 1I0t done and the secondary acknowledged an I
II
then it must be an Unnumbered frame. frame which the primary did not recognize, the pri-
mary transmits the I frallle when the secondary returns
The only Unnumbered frames the primary recognizes to the I T. S. In this case, the secondary would re-
are UA, DM, and FRMR. In any event, the station ceive duplicate I frames.
13-87
inter 8044 APPLICATION EXAMPLES
APPENDIX A
8044 SOFTWARE FLOWCHARTS
POWER-ON-D PROCEDURE
USER-STATE = CLOSED-S
STATION-STATION = DISCONNECT-S
TBS = SIU-XMIT-BUFFER STARTING ADDRESS
RBS = SIU-RECV·BUFFER STARTING ADDRESS
RBL = BUFFER LENGTH
ENABLE SIU RECEIVER: RBE '= 1
XMIT-BUFFER-EMPTY = 1
RETURN
296166-17
CLOSE PROCEDURE
RETURN
OPEN PROCEDURE
RETURN
296166-18
Figure 18_ Secondary Station Driver Flow Chart
13-88
8044 APPLICATION EXAMPLES
XMIT-UNNUMBERED PROCEDURE
296166-19
TRANSMIT PROCEDURE
STATUS
LINK
~ USER·STATE·ClOSE
STATUS
DISCONNECTED
•
STATUS ~
OVERFLOW
XMIT·BUFFER·EMPTY = 0
TBl = XMIT·BUFFER·lENGTH
I·FRAME·lENGTH = XMIT·BUFFER·lENGTH
STATUS = DATA·TRANSMITTED
RETURN STATUS
296166-20
Figure 19. Secondary Station Driver Flow Chart
13-89
intJ 8044 APPLICATION EXAMPLES
XMIT-FRMR PROCEDURE
FRMR-BUFFER (2) = REASON
STATION-STATE = FRMR-S
SEND FRMR
FRAME
296166-21
Figure 20_ Secondary Station Driver Flow Chart
13·90
inter 8044 APPLICATION EXAMPLES
IN·DISCONNECT-5TATE PROCEDURE
296166-22
SNRM·RESPONSE PROCEDURE
II
29U166-23
Figure 21. Secondary Station Driver Flow Chart
13·91
8044 APPLICATION EXAMPLES
IN-FRMR-STATE PROCEDURE
296166-24
Figure 22. Secondary Station Driver Flow Chart
13-92
8044 APPLICATION EXAMPLES
COMMAND DECODE PROCEDURE
RETURN
296166-25
Figure 23. Secondary Station Driver Flow Chart
13-93
SIU·INT PROCEDURE
(
~
I ~ Y
..
C
III
- Y
~ CALL COMMAND-DECODE co
N 1 1-1- - - - - - - ,
o
f>
(JI
III
(')
y
""""
~
XMIT·BUFFER·EMPTY
""
0 = 1
:::I
.
C-
D!
CALL Xr~~~~~~~BERED I • I r
(;
c.J
cD
-I>- -
'<
(JI
~
0-
N
~
oZ
.<
:::I
C
CALL XMIT·FRMR rn
><
..
III
~
3:
"T'I
0-
~
"
r
rn
en
0
:::r CALL COMMAND DECODE
II)
::t
296166-26
8044 APPLICATION EXAMPLES
MAIN PROGRAM
LOAD DESTINATION
ADDRESS IN FIRST
BYTE OF SIU-XMIT
BUFFER
LOAD INFORMA liON
INTO SIU_XMIT-BUFFER
SIU BUFFER LENGTH
OR FIFO-T EMPTY
OUTPUT MESSAGE
TO TERMINAL
'UNABLE TO GET ON LINE'
296166-27
Figure 25_ Application Module Flow Chart
13-95
inter 8044 APPLICATION EXAMPLES
USART-RECV-INT INTERRUPT PROCEDURE
296166-28
Figure 26_ Application Module Flow Chart
13-96
8044 APPLICATION EXAMPLES
MENU PROCEDURE
OUTPUT MENU
TO TERMINAL
CALL OUTPUT·MESSAGE
'ENTER THE STATION ADDRESS:_'
CALL GET·HEX
SHIFT TO LEFT BY FOUR
N •
CALL OUTPUT·MESSAGE
'ENTER THE DESTINATION ADDRESS:
CALL GET·HEX
SHIFT TO LEFT BY FOUR
LOAD ADDRESS
INTO DESTINATION·ADDRESS
RETURN
296166-29
Figure 27. Application Module Flow Chart
13-97
inter 8044 APPLICATION EXAMPLES
ERROR PROCEDURE
RESET ERROR FLAGS ON USART
296166-30
Figure 28. Application Module Flow Chart
13-98
infef 8044 APPLICATION EXAMPLES
FIFO·T·OUT PROCEDURE
296166-31
Figure 29. Application Module Flow Chart
13·99
inter 8044 APPLICATION EXAMPLES
FIfO..T-IN PROCEDURE
I. RETURN
296166-32
Figure 30. Application Module Flow Chart
13-100
inter 8044 APPLICATION EXAMPLES
SIU·RECV PROCEDURE
TRANSFER A BYTE FROM
SIU·RECV·BUFFER
INTO FIFO·R·IN
. Figure 31. Application Module Flow Chart
POWER ON
-
296166-33
•
I INITIALIZE SIU REGISTERS I
I
FOR EACH STATION
INITIALIZE RSD RECORDS
1. STATION·ADDRESS
2. STATIQN·STATE =
DISCONNECT
3. BUFFER-STATE = BUFFER·NOT·READY
4. INFO-LENGTH =
0
I
I RETURN I 296166-34
Figure 32. Primary Station Flow Charts
13·101
8044 APPLICATION EXAMPLES
PRIMARY STATION MAIN PROGRAM
ADDRESS NEXT STATION
SET STAD
Y
CALL SEND-SNRM
y
CALL SEND-DISC
y
CALL XMIT I T S
(T-I-FRAME) -
CAll XMIT-I-T-S Y
(T-RR)
Y
CAll BUFFER-TRANSFER
296166-35
Figure 33. Primary Station Flow Charts
13-102
8044 APPLICATION EXAMPLES
SEND-SNRM PROCEDURE
296166-36
SEND-DISC PROCEDURE
STATION-STATE = DISCONNECT-S
BUFFER-STATUS =BUFFER-NOT-READY
296166-37
Figure 34_ Primary Station Flow Charts
13-103
inter 8044 APPLICATION EXAMPLES
XMIT-T-S PROCEDURE
BUILD CONTROL
FIELD USING EITHER
I, RR, RNR
AND NR AND/OR NS .
y
CALL RECEIVE
296166-38
XMIT PROCEDURE
296166-39
Figure 35. Primary Station Flow Charts
13-104
intJ 8044 APPLICATION EXAMPLES
BUFFER-TRANSFER PROCEDURE
MOVE DATA FROM
SIU·RECV·BUFFER
TO nSD BUFFER
29GIG6-40
Figure 36. Primary Station Flow Charts
13-105
inter 8044 APPLICATION EXAMPLES
CHECLNR PROCEDURE
296166-41
CHECK_NSPROCEDURE
296166-42
Figure 37. Primary Station Flow Charts
13-106
cl
REMOTE BUFFER-STATUS = BUFFER-READY
~ (1)
c g
iil .c.
to)
>
..3"
!=
."
"D
"D
r-
..... DI
o
to)
..:..
.c!
til
~
o
-..j
..
~
5z
o m
=
"'1'1
~
~ s:::
-a
n r-
.
::r
DI
;- I STATION-STATE
m
en
= GD-TD-DISC
296166-43
iii
8044 APPLICATION EXAMPLES
APPENDIX B
LISTINGS OF SOFTWARE MODULES
PL/..-'l CDtPILEA 20: 24: 47 09/20/83 PAGE
1818-1 I PL/"-51 \11.0
COI'IPJLER INVOKED BY: : F2: PUI:U : F2: APNDTE. SAC
tTITLE ('RUPI-44 Suondarv St.tion DT'ivn')
'DEBUG
tREQISTEA8ANK( 1)
MIN'troD: DOl
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'* Tou . . .•• v. p.p."
the AUPI l'e,hte"s ap. not list.d.
to inc Iud. th •• : 'INCLUDE (: F2: RE04 ... DCl) *' but this is the st.t ••• nt
DECLARE LIT LITERALLY 'LITERALLY',
TRUE LIT 'OFFH',
FALSE LIT 'DOH',
FORE\I£R LIT 'WHILE 1 'I
DECLARE SHR" LIT '83H',
" UA
DISC
LIT
LIT
'73H',
'4:tH',
LIT
""
FRotA
AEOiJ'ISC
LIT
LIT
'IFH "
'97H',
'5JH',
UP LIT '33H',
TEST LIT '0E3f-I',
'QOH',
'OHf',
DISCONNECT S LIT 'DOH'. ,- LOgICALLY OrSCor.ECTED BTATE*,
FRI'M a
I_T_8
- LIT
LIT
'OIH'.
'Q2H'.
,- FRAttE RE.JECT STAT[
'* *'
UFOAf1ATlON TRANSFER B1ATE . ,
USER_BTATE_CLOSED II T 'OOH',
LINM..JUSCONIECTED LIT 'OIH',
OVERFLOW LIT 'O::lH',
DAT"_TRANS"JTTED LIT '03H'.
UNASSIONED_C LJT 'OCH',
NO_IJIELDJll-LOW£I) LIT '01H',
BUFF_OVERRUN LIT '02H',
SES_ERR LIT '03H',
296166-44
13-108
inter 8044 APPLICATION EXAMPLES
IIL/"-S, CGfWtn.aJl :20: :24: 47 09/20/113 PAGE a
USERJlTATE BYTE MlULIAltV.
BTATIONJITATE IVTE AU.ILIMIV I
I..FRME.J.ENOTH IVTE AUXILIARY.
IUFFERJ-ENOTH LIT '60',
SIU-"KIT...BUFFER IIUFFER..J..ENOTHI BYTE ,vaLle IDAT....
SIU.../IECY...BUFFERI BUFFER...LENOTHI BYTE PUILIC.
F1UtR...JlUFFRR (3) IYTE.
X.. I T.....UP'FE.. ....E ..1Y In PuaLIC,
7 2 SIUJlECV: ' .. OC£DUlltE (LENGTH) EX1'EIUML1
•
9
2
1
DECLME LENGTH IVTE.
END BIUJl£CV,
10 2 OPEN: PIIDCEDUftE 'UILIC UBI_ a.
11 2 UBERJlTATE-OIEN_81
12 1 END maEN,
13
14
15
2
2
2
_0.
CLDSE: PROCEDURE ,.UILIC USING ;jih
U8ER_IITATE-CL08ED_B.
16 1 END CLOSE.
17 2 PDWER_ONJ): PROCEDURE PUiLIC UBINO O.
1. 2 UBERJI'"'E-<:L08ED_SI
- 1. 2 BrA'UlN_BTA,e:-DIBCCNrECTJl,
20 2 TaB-. 8IU_)( .. 1T JI.FFER(O),
21 2 AIa-. BIU.../IlCVJlUFFEAIOIi
22 2 RIL-Iur'IR..J..IENClTHI
23 2 R.E-l, ,_ Enable th;. SIU'. ,..cdvn ./
24 2 IMITJUFFl:ftJ:. .,V-I,
25 END POWERJlNJl.
26 2 TRANStIIT: PROCEDUftf. U"n ,JUFFERJ,.ENCITH) BYTE PUILlt \IIIINO 01
27 2 OECLME '"IT JI""'ER...LENOTH IYTE,
I IVTE AUULJMV.
BTATU!II IVTE AUXlLINlV.
211 2 IF UBEA_BTATE.-CUMlED_B
THEN STATIJtI-utIEII_8TAn:-.CUISElh
30 2 ELSE IF STATIOH...BTAT~·DI8CONNECTJI ,
T~N 8TATus-LINlUlI8CIINNECTED.
32 2 ELSE IF '"IT _"UF"R...LENOTlQllFFERJ-ENOTH
THEN 8T"TUS-oYERFLtII.
34 3 ELSE 1lO.
296166-45
13-109
II"n+_f
I'ell 8044 APPLICATION EXAMPLES
PL'''-51 COPIP ILER :20: 24: 47 09/20/83 PME 3
3' 3 X"ITJlUFFEIt~"TY-OI
36 3 TBL-Xr1ZTJlUFFER_LENOTHI
I_FRNEJ..EfCTH-xtUTJlUFFER_LENOTHI /. Sto ... length in c ••• st_UDn
37
38
3
3 TIF-l,
is r.~.t by FRI"IR •• SNRf'I .te. *'
39 3 BTATUB-DATA_TRI\NBttITTEDI
40 3 END.
41 2 RETURN STATUS,
42 I END TRANSPfIT,
43 2 X"IT_UNNU"IERED: PROCEDURE CCONTRDLJlYTE) I
44 2 DECLARE CONTRtL.JIYTE BYTE,
4. 2 TCa-CONTADLJlVTEI
46 2 TIF-I,
47 2 RrBaS,
48 3 DO WHILE NOT BII
49 3 END.
00 2 81-0,
.1 END ."IT_..".,...ERED,
02 2 _".-RESPONSE: PROCEDURE I
03 2 STATIDNJlTATE-I_TJh
04 2 NBNR-O,
•• 2 IF (Rei Nfl)
TfEN DC.
JOH)
TlL-O,
<> 0 ,_ R•• pond if palled . ,
07 3
OIl 3 CALL I"IT_UNNUI'IIIERED r U,tll) I
.9
60
3
2
END,
IF Xf1ITJlUFFERJt1PTY-o '* I f en J 'n,.. w.. h,t pending tr.ns.hahn
then r •• tn"a it *'
THEN DO.
62 3 TBL-IJRNIE_LENOTHI
63 3 TBF-l,
64 3 END,
6' 2
66
67 2 .f1ITJRPm: PROCEDURE CREASON) I
68 2 DCCLME REAsoN BYTE,'
6. TCD-FRI'IR,
70 2 TBS-, FRttRJlUFFERCOJ,
71 2 TIIL-3,
72
73
2
2
'*
FRI'tR.JIUFFERCO)-RCI,
SWep nibbl •• in NBNR . /
FRI'IIJlUFFER( 1 )-CBHLC (NBNR AND OEH'.4) DR SHRC CNSNR ANn n[OH). 4»)1
74 3 DO CABE REASON.
70 3 FRf1R...JIWFERUZ)-OlH, I. UNASSJONED_C . ,
296166-46
13-110
inter 8044 APPLICATION EXAMPLES
PL./pt-51 COl1PJLER 20: 24: 47 09/20/83 PAOE 4
16 3 FRJ'IIRJlUFFER (iI)-OaH, , - ND_IJIELDfi.,LDWED *'
11
18
3
3
FRMRJlUFFER (2)-o4HI
FRI'tRJlUFFEA (2) -DSHI
'* BUFF.JJYEARVN
/. BESJ;RR . /
*'
19 3 END.
80 :. STATION_STATE-FRtm_B.
8. :. IF (ACB AND lOH) <>0
THEN DO,
.
83
8.
85
81
8B
3
3
••
3
3
T8F-l,
RTa-S.
DO WHILE NOT BII
ENDI
91-0,
ENOl
89
•
90 :. INJ)ISCOMECTJlTIITE: PROCEDURE J /. C.l~.d '1'0. SIU_1NT ,T'ocedu.,. • • /
9. :. IF CUJSERJlTATE-oPEN_SJ AND «RCB AND OEFHI-SNR")>>
llEN CALL SNt"JlESPDNBE.
93 :. ELSE IF (RCB AND lOH) 0. 0
THEN DOl
95 3 T8L.-01
96 3 CALL lC"IT _UNNUI'IBEREDC D"» I
91 3 END.
98
• END IN."DlSCONNECTJlTATE.
99 2
..hen in the FAI'IR st.,,_ *'
INJRI'IR_STATE: PROCEDURE I / . C.U.d b;' SIU_INT .. hen. ,,. ••• h•• b .. n "'eceiv.d
.00 2 IF (RCB AND OEFH)-SNA"
Tt£N DO.
.02
.03
.00
3
3
3
C"'-L 8NA".-RESPONSEI
TI&-. BIU_X"ITJlUFFERCO',
END.
/. A. . 'or. '''.n •• U bu.fe . . ,ta,.t .d',. ••• *'
.05
• 07
.OB
.09
ll.
ll2
ll3
114
115
116
2
3
3
3
••
4
3
3
3
ELSE IF lRCa AND OEFHl-DlSC
THEN DO.
ELSE DO.
BTATUIN_BTATE-DIBCONI£CT_B •
TIS-. SIU_XHITJlUFFERCO)1
IF (RCD AND 101'1)0 0
THEN DO,
'*
TBL-o,
/* R•• tor. tran •• i t bu'''", .t • .,., _dd" . . . e/
CALL. Xt'llTJJ*UI'IBEREDCUA'1
END,
Rlceiv. cant,.aJ bUh h
IF cRCa AND .0tI) 0 0
THEN DOl
sallithing other \h.n DISC a1" SNR" *'
•
118 4 TDF-I.
119 4 RTB-li
296166-47
13-111
inter 8044 APPLICATION EXAMPLES
lii!D: 24: 47 09/20/83 PAQE
"'" ••
DO WHILE NOT SI.
121 END.
122 4 ENOl
123 3 ENDI
124 END INJRtoIR_STATEI
12. 2 CDf1P1ANDJ)ECODE: PROCEDURE I
126 2 IF (RCB AND OEFH)-SNU.
THEN CALL SNRMJlESPDNSEI
128 2 ELSE IF (RCB AND OEFH»-DISC
THEN DOl
130 3 STATION_ST ATE-DISCDNIIIECT _9:
131 3 IF (RCD AND lOH'<>O
THEN DO,
133 4 TIL-o,
134 4 CALL XptIT_UNNUttBEREDCUAII
13. 4 END,
136 3 END.
137 2 ELSE IF (RCB AND O£FH)_TEST
139 3
TI£N DO,
IF (RCB AND 10H)O ,- Rnpond if! polhd
. THEN DO,
*'
,_ FOR DOY-I. SEND THE TEST RESPONSE WITHOUT AN I FIELD *'
141 IF (BOY-II
THEN DO,
143
144 •• TSl-O,
CALL X"IT_UNNUf1BEREDfTEST OR IOHb
14'
146 •• ELSE DO,
[NO,
'*If no BOY• • • nd r.cdyed I 'hld b.d to pri •• rlJ *'
•••
147 TlL-RFLi
148 TOO-RBS,
149 CALL XMIT_UNNUttBEREDCTEBT DR lOH),
100
101 •• TlB-. BIUj:"n....UFFERCOI'
ENOl
/. Reatne T88 . /
102 IF XI1]T _DUFFER_EI'IPTV-O
THEN DO,
10.
I," •• TBL-I_FRNEJ-ENQTHI
TBF-l,
10.
107 4• END.
I.NDI
lOB 3 Af1-.,
u. 3 ENOl
160 ELSE IF CACB AND 01H) • 0 , . Kicked aut o' the AUTO lIad. b.e.u . .
• n I ,,. ••• ••• "eceived lllhi h flPO - I . /
THEN DO.
162 3 N1 • 11
'.3 3 IF Xl1lT _BUFFEAJ:"TV - 1
THEN Tal. 01
16. 3 TBF • II /. S.nd .n AUTO _ade ,. •• pan •• -,
296166-48
13-112
inter 8044 APPLICATION EXAMPLES
PL./t1-S1 COf'tPlLER 20: 24: 47 09/20/93 PAGE
166 RTB .. 11
167 ENOl
16B
, .. EL.SE CALL Xt1IT_FRI'1R(UNASS1QN£D_C)J
END COf9tAHD_OECODE,
/e ROCRivod an und.finod CT' not illph ... nt.d co.and *1
170
171 DECLARE BYTE AUXILIARV,
51-a,
172
173 IF STATJON_9T ... TEC> I_T_8
THEN 00,
'* Must b. in NON-AUTO lIIodo *1
170 IF' RDE-O , . R.c.lvod • INU... ? Qive T • • pon •• */
THEN 001
•••
177 DO CASE STATION STATE)
17B CALL IN_DISCONNECT _STATE,
17' (NOI CALL IN_FR~_STATE'
lItO
IBI •• ROE-II
IB2
IB3 3• RETURNi
(NO,
ENOl
lB' 3
,_ It the progr",111 roach •• thit point,
whlch 1II • • n. tho SIU eith~r III ••• or
OT"TJON_BTATE-I..;.T_S
ItI,lI is in tho AUTO P1CIDE *'
\0. IF ,,11 .. 0
TH[N 001
107 3 IF (RCB AND OEFH)-O]SC
THEN CALL COt1HAND_DECtll>t;.
\B. 3 (LGE IF' USER_STATE-CL08ED_O
THEN DOl
....
\01 TBL-O,
\.2
\03
•• CALl. Xt1IT _UNt.tJMnU1EOCREQ_DISC),
ENDI
\ 3 [LU[ IF 8ES-l
THEN CALl. XHlTYRMR(la !i.tllllh
\ [U1E IF BOY-1
THEN DOl 1* DON'T GEND I "/111 IF A TEST WAS RECEIVED-'
,.a IF (RCD AND au til-TEST
THEN CALL Cl~D_DECQDEj
2O<l
201 •• ENOl
ELSE CALL ~111T FRMR(BUFF OVERRUN) I
- -
202 3 t:LU[ C~LL CO.....ANOJ)ECODEI
203 3 nD["1 j
20. 3 (NO.
20' 3 ELSE 001 ,_ I'1UUT Of ILL BE IN AUTO MODE -,
20. 3 IF TUF-O
THEN )(111T.JJUFFER~t1PTY.lj ,_ THAN!lMITTED A FRAME -I
20a IF RDE-O
THEN lllJI
296166-49
PL/I't-!U CaMP ILER RUPI-44 Sot:ondarij Bt. t l on Dt'ivot' 20: 24: 47 09'20'B3 PACilE
RBP-ll , . RNR STATE _,
210
211
212
4
4
4
RBE-1i '*
RE-ENABLE RECEIVER
CALL SIU,JtECV(RFl)J
*'
213
214
..
4
RBP-OI
ENOl
'*
RR STATE *'
21' 3 ENOl
;Ub 1 END SIU_INTI
217 END t1AINtI'lDDI
WAftNINQ8:
4 18 THE HICilHEST USED INTERRUPT
I'tODULE INFORMATION: (STATJC+OVERLAVABLE 1
_ 02SFH 6~~D
CODE SIZE
_ OOOOH 00
CONSTI\NT 81 IE
DIRECT VARIABLE SIZE 3FH+02H 630+ 20
INDIRECT VARIABLE sIZE 3CH+OOH bOO+ 00
lIT SUE 01H+00H 10+ 00
lIT-ADDRESSABLE SIZE OOH+OOH 00+ 00
AUXILIARY VARIABLE SIZE • 0006H 60
AAXII"lUt1 STACK SUE • 0017H 2JD
REQISTER-BANKtS) USED: o I 2
460 UNES READ
o PROQRAI1 ERROR (8)
END OF PL/t1-" COPIPILATION
296166-50
13-113
8044 APPLICATION EXAMPLES
PL/P1-:U CDl'lPILER ",plic_Ucn l'Ioduh: "."nc/SDLe Protocol convert." 10: ~O; ~3 09/19/93 PAGE
rSls-u PLitt-51 V1. 0
COI'PILER INVOKED 8V: : f2: pl.:n : #2: unoh. ST'C
tTITLE ('Applle.tion "odul.: "'s",nc/SDLe Protocol conv.rt.,,')
.debug
...... hhrhn .. (O)
u •• "O.od: dOl
tNOLISr
5 DECLARE LIT LITERALLY 'LITERALLY',
TRUE LIT 'OFFH I .
FALSE LIT 'OOH'.
FOREVER LIT 'WHILE I',
ESC LIT 'ISH',
LF LIT 'OAH'.
eR LIT 'ODH',
8S LIT 'OSH',
IEL LIT '07H',
Ept:lTV LIT 'ooH',
INUSE LIT 'OtH',
FULL LIT ' 02H' •
USER_STATE_CLOSED LIT 'OOH'.
LINK_DISCONNECTED LIT '01H',
OVERFLOW LIT ' 02H' •
DATA_TRANSI'ITTED LIT '03H',
1* BUFFERS *1
BUFFER_LENGTH LIT 'bO',
8IU_X'1XT JJUFFER (8UFFER ...LENOTH) BYTE EXTERNAL 100TA.
81 U_RECVJlUFFER (BUFFER_LENOTH) BYTE EXTERNAL.
FIFO_T<2~6) BVl[ AUXILIARY.
INJTR_T BVTE AUXILIMV.
OUT J'TR_T Byn: AUXILIARY.
BUFFER_STATUS_T BVTe: AUXILIARV,
FlFOJH2SO} BVT[ AUXILIARY.
INJTR_R BVT[ AUXILIARY.
OUT J'TR_R BVn: AUXILIARY.
IIUFFER_STATUSJl BVT[ AUXILIARY.
LENOTH BVn: AUXILIARY.
C..... 8Vl[ AUXILIARY.
r BVTE: AUXILIARY.
UBART_CI'1D BVTr: AUXILIARY.
DESTINATlON...ADDAEBB B'fT[ AUXILIARY,
SEND_DATA B'nl: AUXILIARY.
RESULT BY1[ AUXILIARY.
E~RJ1EBBAOE_rNDEX BYTe: AUXILIARY.
ERRJtESBAOEJTR WOOID AUXILJARY.
PARITY'.) BYTE CDNSTANT<LF.CR. 'P",UV E,. .. o,. O.hchd·,LF,CR.OOH).
FRAI1E(.) BYTE CQNSTANTCLF. CR. 'F,. •• in. E,.,..oT' D.t.c; hd', LF. CR. OOHJ.
296166-51
13-114
8044 APPLICATION EXAMPLES
PL/"'-Sl COtIPIL.ER App 1 ication t1aduh: " • .,nc/SOLe P1'o1:ocol conv .. rt.,. IB: 50:'3 o./~9/B3 PACE 2
OYER..RUNC.) BVTE CONSTANTCLF. CR. 'Ov.,."un E,.,.or n.t.ct.d LF. CR. OJ. I.
L.I"Ca) BYTE CONSTANTtLF.CR. 'Unable to 0., Onlin.'.LF.CR,OOH),
DEBTfoDAC.J BYTE CQNSTANTCCR.LF.LF.
'Ent.T' th. d •• tin_tiDn I'd dr ••• : _'I DS. DS. 0)'
DflDR.j\CKC*) BYTE CONSTANTCCA. LF. LF.
'Th. nn, d •• t1n.1:10n .dd,.. ••• i . ',01.
9TATJlDDR(.) BYTE CDNSTANT(CR. LF. LF.
'Ent.,. th • • t.-tlan .dd,. ••• : " as. 89. OJ.
S./tDDR,jICKC.) BYTE CONSTANTCCR. LF. LF.
'lh. nl'lII ,tatlan .dd ..... i . ' , 0),
SION ONC_) BYTE CONSTANICCR. Lr. LF,
'(\/) RUPl-44 O.cond.,,1,1 9t.t'ul1', CR. LF •
• \/', CR. LF. LF.
'I - S.t thl' Dt.tion Addr ••• •• Lt', CII.
'2 - Sl't th. D•• tin.tian Add,. ••• ', C", L.F.
'3 - go Onl1n.', CR. LF,
'4 - go OffUn.',CR,LF.
'5 - R.tuT'n to t.T'min.l _od.', (:1«. If, U",
, Ent.T' aptian: _'I BS. 0).
FINe.) BYTE CONSTANTCCR.LF,LF.OI.
HEX_TABLE(17) BYTE CONSTANTC ·OI;":14:U,"IW/AUCDEF'. BEL).
t1ENU_CHARC6J BYTE CONSTANTC'12:14:)',III!.I,
'*
II
X"IT _DUFFER~TY BIT [KTI.lINAl.. S ••• phoT'e faT' RUPI SIOU TT'anaCilit Buf'hr -,
STm'_DIT BIT AT'14/1 lIl:g, /* TeT'lIIinal paT'alll_t_T'. -/
ECHO BIT ATCOll4111 m::o,
WAIT aIT, /* n ... out fl.g */
ERROR...FL.AO OIT. /_ E...... o......... g. Flag -,
USAnr _EJTATUEJ BVTE ATCOUOHII AUUL.IARY.
USART _DATA BYTE AT CODOOU I AUXILIARV.
TlKER_CONTROl. BVTE ATC lOO"JHI AUXILIARY.
T1HER_O BYTE ATC 10001-11 AUUl.JARY.
TlI1ER_1 BVTE ATC1001H1 AUXlL.1ARVi
TltlER.;! BYTE ATC 10O;2HI AUKlUARYi
296166-52
13-115
8044 APPLICATION EXAMPLES
Pll"-SI CDr1PJLER lB: 50: ~3 0.,/19/83 PAGE
6 2 Pot.ER_ON_D: PROCEDURE EXTERNM..
7 I END POWER_ONJ)i
•• 2
I
CLDSE: PROCEDURE EXTERNAL USING 2 •
END CLOSE,
10 2 OPEN: PROC~DUAE EXTERNAL USING 21
II I END OPENI
12 2 TRANsttIT: PROCEDURE (Xf1ITJtUFFERJ,.ENOTH) BYTE EXTERNAL.
13 2 DECLARE Xt1l.T_BUFFER_LENOTH BYTE.
I. I END TRANSMIT, -
I' 2 TltER_O_INT: PROCEDURE INTERRUPT J USING I.
16 2 WAJT-o,
17 I END Tlf'ER_O_INTI
18 2 POWER_ON: PROCEDURE USINQ 0,
I' 2 DECLARE TEI'W BVTE AUJllLlARY,
20 2 sttD-'4H, , . U.inll DPLL. NUl. PFO. TlI'tER 1• • t:Nii!. , Kbp. *1
21
22
2
2
TNJD-21HJ
TH1-oFFH.
/. Tt •• " 0 It. bU. Ti •• r 1 .ute r.lo.d *'
23 2 lCDN-40H.
2.
2'
2
2
TlfER_CDNTRDL-37H,
Tlf1ER_O-o4HI
/ . lniU.Un Un,.RT'. 'v.t •• cJoclo
8254 *'
26 2 TJf£R_O-ooHi
27 2 TltER_CONTROL-77H, ,_ Initi.U I f T.C, RIC 0/
/. Definition foT' clip .witch thd to PI. o to PI. b
au Rat.
300 an on
1200
2.00
an
an
on
aff
0"
on
.100
'600
an
aff
a ••
an
0"
on
.'200 a" on 0"
Stop bit
on
off
P."itV 6
.n
...
a"
a ••
a"
an
0" ."
on
a ••
296166-53
13-116
8044 APPLICATION EXAMPLES
PL/ .... 51 COl'tPlLER 19: SO: 53 09/19/83 PAGE
Echo
on on
off off
2S
2'f
2
2
TE....... 1 N4D 07HI
IF TEI'W'>S
/ . R •• d th. dip switch to deter.i.n. the bit .... t. *'
THEN TEr1P-Oi
31 3 DO CASE TEHP I
3:2 4
/ . 300 *' DO.
33 4 TltER_l-83H,
34 4 TlttER_l-;2OW,
35 4 END.
:u.
37
4
4
'* 10l00./ DO.
TU1ER_l-:20Hi
3B 4 TlfER_l-oSHI
4 END.
""
40 4
41 4 Tlt1ER_l-oOW,
42 4 TltER_l-O:i!HI
43 4 END.
44 4 / . 4800./ DO.
45 4 TlttER_1-3OH,
4.
47 •
4 END.
TII'tER_1-01HI
4S
49
4
4
'* 9000./ DO.
TUtER_l-o'H,
4 TUtER_I-O,
""
51 4 END.
52 4
53 4 TII1ER_1-33HI
54 4 Tlf1ER_l-Oi
55 4 END.
S. 3 END.
57
sa
2
2
UBltRT_BTATlIB-OI
USART _STATUS-O,
'* Boftll..u". pow."-on .,. ••• t '01'" 82'IA *'
59 2 USART _STATUS-OJ
~ 2 USAflT _STA1US-40H,
61
6:2
2
2
T£tI"-oAHI '*
Det.".i.n* ttl•• p.,.U.., .nd • 0' .tup bih . /
T£... -TE. . OR (PI I\ND 30Hli
63 2 IF STOP JIIT·,
..
THEN TEt1P-TEt1P OR oeO""
65 2 ELSE Ta.-TEf1P OR 40HI
67
2
2
UBAAT STATUS-tErtP, '* USART "ode Word *'
USAAT:STATUS. USART_C"D-27H,I*USAA:T Co_and WOf'd "'U. RIE. DTR. lIEN-l-'
.a 2 STAD-OFFH,
296166-54
13-117
inter 8044 APPLICATION EXAMPLES
PL/I'I-:U COJVIllER Application Module: Asvnc/SDLC Protocol -converte" 18: 00:,3 09/1'9/83 PAgE
6' 2
70 INJlTR_T. DUTJTR_T. IN_PTR_R. OUT_PTR_R - OJ I*Initi_liu FIFO PTRs.1
71 2 BUFFER_STATUS_T, BUFFER_STATUS_R- EI'fPTY,
72 2 CALL POWER_ON_D;
73 2
'*'*
1* USNn'. RIRdlj h *'
the higll . . t prloritll
Both e.ternal int.rrupts are level trigger.d.1
70 2 Enable UBART RIRd",.BI. and Tl •• " 0 interrupt.-,
7' ERRORj'LAg-OI
7. END POWER_ON,
77
7B •
2
FIFO_R_IN: PROCEDURE (CHAR) USING 1-,
DECLARE CHAR BYTE,
7' FIFO_R ( IN_PTR_R )-CHAR.
BO INJ TR.-R-INJTR_R+ll
Bl 2 IF BUFFER_STATUS_R-EMPTY
THEN DOl
B3 3 EA-O,
BO
B'
B.
3
3
3
EXl-!1
EA-l,
'*
DUFFER_BTATUS_R-INUSE.
Enabh USAAT', TID interrupt *'
B7 3 END,
BB 2 ELSE IF « BUFFER_STATUS_R-INUSE) AND (IN_PTR_R-oUT"pTR_R) )
1"I-I;:N DUFFER_STATUS_R-FULL,
90 END FIFO-fl_IN'
., 2 FIFO_R_OUT: PROCEDURE BVTE USINO 1,
•• 2 DECLARE CHAR BVTE AUXILIARV,
..
.3
'0
.7
2
2
2
3
CHAR-FIFD..R (OUT J'TR_R)'
OUT _PTR_R-OUT _PTR_R+l,
IF OUTJTR_R-INJTR_R
TI-£N DO,
EX1-O, 1* Shut off hO intnrupt */
.8 3 BUFFER_STATUS_R-EP'tf' TV,
••
100
3
2
END'
ELSE IF «BUFFER_STATUS_R-FULL) Nm COUT_PTR_R-20-INJ'TR_R»)
THEN BUFFER_BTATU9._R-INVlJt~j
102 RETURN CHAR'
103 END FIFO_R_OUT.
laO UBART _XHlT _INT: PROCEDURE INTERRUPT OJ! USINO 1,
296166-55
13-118
infef 8044.APPLICATION EXAMPLES
PL/I"I-Sl COI'1f'ILER Application MOdule: "sync/SDLe Protocol convert;a,.. IS: ~O:,3 0'1/19/93 PAgE 0
10' 2 DECLARE
BYTE CONSTANT;
106 IF ERROR_FLAG
lOB 3
THEN 00,
IF HESSAOE(ERRJ1E99AOE_INDEX)()O
THEN DO,
'* Than continua to nnd the ••••• g. */
•••
110 USART_DATA -, 1'£8SAQECERR_I'1ESSAQE_INDEX Ii
111 ERR_t1ESSAOE_I NDEX-eRR_MESSAQE_INDEX+ 11
112 ENOl
113
114 •
4
ELSE DO. , . If ,. •••• g. i . done
ERROR_FLAO-O,
l" • • • t ERROR_FLAO and shut off int.,."upt if FIFO is empty */
11. • IF DUFFER_STATUS_R -
THEN EXl-O,
EMPTY
117
11B
•
3 ENOl
ENOl
119
120
121 SlU_RECV: PROCEDURE (LENgTH) PUBLIC USINg 11
122 DECLARE LENOTH BYTE.
I BYTE AUXILIARY,
123
124
12.
3
4
4
DO I-a TO LENOTH-II
DO WHILE BUFFER_STATUS~.FULLI
ENOl
'* Chae ~ In ••• i f fifo is full *,
126 3 CALL FIFO_R_INCSIU.-RECV_BUFFER (1»)1
127 3 ENOl
12B
129 2 FIFO_T_IN: PROCEDURE (CHAR) USlNO 21
130 DECLARE CHAR BVTEI
131
132
133
135
FIFO_T( IN_PTR_T )-CHARI
IN_PTR_T-IN_PTR_T+ll
IF CHAA-LF
TtEN SEND_DATA-5END_DATA+l J
IF BUFFER_STATUS_T-EttPTV
THEN BUFFER_STATU8_T-lNUSEI
ELSE IF t tBUFFER_STATUS_T-lNUSE) "ND (lNJTH_.T,*;.!O-OUT_PTR_T})
II
137
139 3
THEN DO, '*
Stop ,,_,.phon uling ell) -,
USART _STATUS. USART _CI1D-UONIT _CHD AND NOT C20H) I
140 3 BUFFER_STATUB_T-FULLJ
141 3 IF SEND_DATA-O
THEN SEND DATA-ll/*I' the bu".r h full and nQ LF
- h •• b •• n r.c.i .... d th.n •• nd data */
143 ENOl
144
296166-56
13-119
8044 APPLICATION EXAMPLES
19: ~O: ~3 09/19/83 PAGE
14' 2 FIFO_T _OUT: PROCEDURE BYTE I
146 DECLARE CHAR BYTE AUXILIARY,
147 2 CHAR-FJFO_TCOUTJTR_T) j
148 2 OUT _PTR_T-ouT _PTR_T+11
14. 2 IF OUT JTR_T-IN_PTR_T ,- Th.n FIFO_T 11 .ltptV -,
THEN DO,
1.1
1.2 •• £A-O,
BUFFER_STATUS_T-EHPTY,
1'3
• SEND_DATA-O.
••
I" EA-ll
I" ENOl
1.6 2 ELSE IF «BUFFER_STATUS_T-FULL) AND CDUT_PTR_T-SG-IN_PTR_T)'
Tt£N DO.
•••
I .. USART_STATUS. USART_CHO-USART_CI'ID OR .OHi
I'. BUFFER_STATUB_T-INUSEI
160 END,
161 2 IF (CHAR-LF AND SEND D"T">O) THEN SENDJ)ATA-BENDJ>ATA-I,
16. 2 RETURN CHARI -
164 I END FIFO_T _our,
16. ERROR: PROCEDURE (STATUS) USINO ill
I.. DECLARE STATUS BVTE,
167 2 IF (STATUB Nro OBH)<>O
TI£N ERR_I'ESSAOE.jITR-. PARITY'
16. 2 ELSE IF (STATUS AND 10H)(>O
HEN ERR_"ESSAOE_PTR-. OVER_RUN!
171 ELSE IF (STATUS AND 20H)<>O
Tt-EN ERR-"IESSAOEJTR-. FRMEI
17' 2
174 2 ERRJ1ESBAQE_INDEX • 0,
175
176
2
2
ERROR J·LAQ- J,
EXt-t. '* TU1'n on T. Intnrupt *1
177 END ERROR,
17B LINK_DISC: PROCEDURE I
'7' 2 DECLARE I'IE6SAGE_PTR
f1ESSAQE
WORD
BASED
AUXH.IAAV.
P£OGAO£:_PTR (1) BYTE CON!lTANT.
J BYTE AUXll.IMV.
EXl_STORE BITI
IBO
IBI
2
2
EXl_STORE-EXJJ
EXt-OJ
'* Shut 0'1 •• !Jnc t1'ans"'it inte1'rupt */
IB2 2 MESSAgE_PTR-. LI NKI
lB. 2 ..I-OJ
184
• DO WHILE CI1ESSAQE(..I)<>O)J
296166-57
13-120
inter 8044 APPLICATION EXAMPLES
Pl../I1-:U COI'IP ILER 18: 50: 53 09/19/83 PAOE
'* *'
••
Ie. DO WHILE eUSART_STATUS AND 01H)-Ol Watt flo1' T.RDY on USART
leb END.
187 3 UBART J)ATA-t1ESSAQE I J ) ;
18e 3 J-J+l1
I""
190
191
3
2
I
ENOl
EXI-EXt_STOREi
END LINK_DISCI
'* R•• tore .slJnc transmit intlt"1'upt *1
19.
193 •
2
CD: PROCEDURE (CHNO USING 21
DECLARE CHAR BYTE,
19_ 3 DO WHILE (uSART STATUS AND OUt! - 01
19. 3 ENOl -
19b 2 USItAT _DATA-CHARI
197 END cal
196 el: PROCEDURE BVTE USING 21
199 3 DO WHILE (USART_STATUS AND 02H) • 01
200 3 END.
201 2 RETURN USART.-DATAJ
202 END ell
203 OET.)£X: PROCEDURE BVTE USINg 21
20_ DECLARE CHAR BYTE IIUXlLlARY.
I BYTE AUXILIARY,
20.
20b DO 1-0 10 I"
207 IF CHAR-HEX_TABLE( I)
THeN 0010 Lil
209 3
210 U: CALL COIH(:X_TABLECI»l
lEI
211 IF I-UI
THEN OOTO LO,
213 RETl.mN II
21_ END OETJ£X,
210 2 OUTPUTJ'ESSAOE: PIIOCEDURE (l1E6SAOE_PTR) USINO ;,jj
21b 2 DECLARE HEDBAOI::JTR WORD.
I1(OUAO[ DABED t1ESSACEYTR ( 1 ) 0"" rt CONSTANT.
I BYTE AUXlLIARYl
217 2
21S 3 DO WHILE t1EDIlAQC 111 <> O.
219 3 CALL CD I I'I:OQAQ(( I I ••
220 3 1-1+1.
296166-58
13-121
8044 APPLICATION EXAMPLES
Pl/~'l COf'PILER AppUc_Uon'P1oduh: "s\lnc/BDLt PT'otocol convert.,.. 18; '0:'3 09/19/83 PAGE 9
221 3 ENOl
22a END OUTPUT _t'tEBBAOEJ
2:13 a I'tENU: PROCEDURE USINQ 21
aa4 DECLARE I BYTE AUXILIARY,
CHAR BYTE AUXILIARY,
STATIONjlDDRESS BYTE AUXILIARY,
aa. a START;
CALL OUTPUT_1'tESSAOEC. SION_ON),
2:1. a
227 DO [-0 TD 4.
228 IF CHAR-PIENU CHAR ([)
THEN 00,.0 1"11,
230 END,
231 ttl: CALL CO(P1ENU_CHARCI»,
232 IF 1-'
TI£N OOTO I'tOI
234 DO CASE II
23. DO,
236 CALL OUTPUT _f'lESBAOE (. STAT _"COR J,
237 STATlCIfC~DRESS.SHL(QET_H£:)(, 41,
239 STATION_ADDRESS-CSr....TION...,ADOO[OB OR gET_HEXl'
239 STAD-ST"'TIDtCADDREBS,
240 CM..L DUTPUTJlESBItOEC. 8_ADOft _,*,Ct( I,
241 CALL COC!£X_TABlE(8HR (STATJ ON_ADDREBS. 4)),
242 CALL. CO(HEX_TABLE(OFH AND OTATION_ADDRESS»!
243 Co\l.L OUTPUTJESSAOEC. ADDRj\CK_FJN1'
244 END,
240 DO,
24. C"l.L DUTPUTJ'lESSAQEC. DEBT _AODR I,
247 DESTlNATJDN_ADDRESS-sHLCOf:T _HeX, 4},
240 DESTINATJON_ADDRESS-(DE8TJNATlONjlDDRESS OR GET_HEX ),
249 CALL OUTPUT_I1ESSAQE(. D_ADDR_ACK)J
296166-59
13-122
inter 8044 APPLICATION EXAMPLES
PLitt-51 CII'PILER IS: '0: 53 09/19/B3 PAGE 10
2SO CM.L COCHE1C_TA8LECSI*tCDEBTINATlDN_ADDREBS. 4»),
251 CALL COCHEX_TABLEtOFH I\ND DESTINATION_ADDRESS»;
252 4 CIILL DUTPUTJESSMEC. AODR..ACK..FIN)J
253 4 END.
2,4 4 DD.
2'5 4 CALL OUTPUTJESSAQEC. FIN),
256 4 CALL OPENl
257 4 END.
258 4 DO.
259 4 CALL OUTPUT.J'ESSAQEC FIN),
260 4 CALL CLOBE.
261 4 ENOl
262 3 CALL OUTPUT_HESOAOEC. FIN),
263 3 ENOl/- 00 C"SE -,
264 END I1ENUI
265 2 USART..REC"_lHT: PRDCErxME INTERRUPT 0 USING ;I,
266 2 1lECLAAE CHM BYTE AUXlL.IARY.
6T"TUO BVTE AUXlL.IMY,
267 2 CHAR-usART ..DATA'
268 2 STATUS-UBNlT_STATUn AND 3SHI
26" 2 IF STATUB()O
TIEN CALL ERRDRCOTATUSJ,
271 2 ELSE If CHAR-EDC
THEN CALL t'lENUI
273 3 ELSE 001
274 3 CALL FIFO_l_INCCHARJ,
275 3 If ECHQ-O
THEN C,.\l,L CO (CHM) I
277 3 END,
27a
27'9 BEQIN:
CALL POWER_ONI
2BO 2 DO FOREVER I
2al 2 IF BENDJlATA)O
THEN DO,
283 4 DO WHiLt NOT CXt1ITJlUFFERJ:J1PTV) , I_W.it untt.l SIU..xttIT_OUFFn
l ....pt'l -,
284 4 ENOl
285 3 LENOTti. CHAR -II
2B6 3 BIU_KHI T _8UFFERCO)_DESTINATIDN_ADDRE661
287 4 DO WHIU: I CCHAR<>LF) ....ND (LENQTH<BUFFER_LENOTH. AND CDUFFER-.ST....TUS-:'T<>EfUlTV»1
296166-60
13-123
intJ 8044 APPLICATION EXAMPLES
18: ~W:'3 09119/83 PAOE 11
_
288 4 Ctt.\ft-FIFD_T_OUTI
8IU_X"1 TJlUFFER (LENGTH )-CHAR,
2'fO 4 LENOTtt-LENOTH+l,
291 4 END.
'* II the lin. Intl"ld at th. "'I".tntl t. 1.,. •• '1" titan BUFFER_LENOTH cttl" • • • nd the
*'
292 3 Ll: 1-0. '* t"ans.it_ *'
first BUFFER_LENGTH (ha", than . . nd the r •• t, sinct the SIU ~uf"r :h onlv 8UFFER_LENQTH bvt . .
U•• I to count tho nUM.o", of un.uee •• lul
293
294
3
3
RETRY: R~SULT-TRANSI1IT(LENOTH)1 '*
Send the . . . . .g.
IF REBUL T<>OATA_TRANSttITTED
*'
296 4
'* THEN DO,
Wait 50 ••• c 'or link to connlet then t,,'11 _,_in */
WAIT-I,
297 4 THO-XH'
298 4 TLO-O#!FH.
299
300
301
,,
4 TRD-l,
DO WHILE WAlT,
END.
302 4 lRo-OJ
303
304 ,
4 1-1+1,
IF 1)100 THEN 00. '* Wait 5 lee to ,.t Dn I in. I •••
•• nd .,,"or ••••••• to torllinal
306 , and tT'V ••• in
CALL LINK_DISC;
I'
307
30Il ,• QOTO LlJ
END.
"""
310
311
4
4
3 END,
END.
gorD R[TII'V.
312 2
313 1
WMNIH08:
il 18 THE HIGHEST USED INTERRUPT
I10DUlE INFOR.....TIDN: (STATlC+OYERLAV"ILE I
CDDE SIZE - 0682H 1714D
CONSTANT SUE • OICFH 463D
DlltECT VARIABLE SIZE OOH+OSH 00. 'D
INDIRECT YARIABLE SUE OOH+OOH 00+ 00
In BUE 02H+01H :lO" 10
I,T-Id)DRESSItILE SIZE OOH+OOH OD" OD
AUXILIARY YMIf&lLE SUE • 021FH '''3D
"-,XI,..". STACK SIZE - 0028H "DO
REGISTER-IANKes) USED: o 1 2
713 LINES READ
o PROQRAI1 ERRDR (9)
END OF PL/f1-51 COf'tP ILATlDN
296166-61
13-124
inter 8044 APPLICATION EXAMPLES
Pl/H-51 CDHPlLER RUPI-t4 Prilllu", Shtian 20: 41: 13 09/26/83 PAQE
ISIS-II PL./1't-51 Yl.0
CDl'PJLER INVOKED IV: : F2: PU". : Fa: PNOTE. SRC
.TlTLE ('RUPI-44 Pri".1"\1 St.tiDn·)
tDEBUG
'REQISTERBANK(O)
""'IN'~D: DDi
'* To ••v. p.p." the RUPI .... i .. '." • •1'. nat li"ted.
u •• d to include thelll: elNCLUDE C: ';Z: RECiJ44. OCL) *,
but this i . the .t.t ••• nt
'NOLlsr
DECL.AAE LIT LITERALLY 'L.ITEHAL.l.V't
TRUE CIT 'OFFH',
FH.,.SE CIT 'OOH',
FOREVER CIT 'WHILE I',
/ . SDL.e CQf'1f1ANQS AND RESPONSES *1
6 DECLARE SNA" CIT "3H',
UA CIT '73H',
DISC CIT -'3M',
DK CIT 'lFH',
FRI1R CIT -97H',
REGJllSC CIT "3H',
UP CIT '33H',
TEST CIT 'OF3H',
RR CIT 'ItH',
RNR CIT '15H',
'* REI'IOTE STATION BUFFER OTMlJlJ -,
BUFFER_READY CIT '0',
BUFFER_NOT_READY CIT '1',
•
'*
STATION STATES . /
DISCONNECT_S LIT 'OOH', /- lllUICALLV DISCONNECTED STATE./
OD_TOJUSC LIT ·OtH'.
I_T_S L.IT '02H', ,_ INtUflHATIDN TRANSFER STATE ,,'
/ . P~RAI1ETERS PASSED TO XHIT _1_T_S
T_IJ'RAHE LIT 'OOH',
*'
T-"R LIT 'OlH',
TJU'" LIT '02H',
'* SECONDARV STATION lDENTlFICATlON ./
NVI'IBER_OF _STATIONS LIT '2',
SECONDMV~DDRESSES("'UI'IBER_DF _STATIONS)
BVTE CONSTANTU'H,4JH),
296166-62
13-125
intJ 8044 APPLICATION EXAMPLES
PL/f1-S1 COMPILER 20' 47, 13 09/26/83 PAGE ::2
RSDlNUI'1BER_OF _STATIONS) STRUCTURE
CSTATlON.-ADDRESS BVTE.
STATION_STATE BVTE,
NS BYTE.
NR
BUFFER_STATUS
INFO_LENCHH
BYTE.
BYTE. The
BY.TE.
'* .t.tu. of th • • • tond.,. .... tation. bu'f.,. ./
DA1A(64) , BVTE) AUXILIARY.
'*
VARIABLES
STATlON_NUtfBER 8Y.TE
*' AUXILIARY.
RECV J'JELD~ENQTH BYTE AUXILIARY.
WAIT BIT.
'* BUFFERS . /
SIU_XMITJlUFFERC64J BYTE IDATA.
SIU-flECV.JIUFFER(64) BVTE,
POWER_DN: PROCEDURE I
8 DECLARE I BYTE AUXILIARY,
•
10
2
2
T8S-. SIU_XMITJlUFFERCO)I
RBS-. SIU~ECV_8UFFER(O)'
11
12
2
2
RBL-64,
R8E-ll
'* 64 8\190. 1'ecelv. buffer
, . Enabl. the SIU'. rlrUv.1' . /
*'
13 DO r- 0 TO NUMBER_OF_STATIDNS-l.
I" 3 RSD ( I ). STATION_ADDREssaSEcmw",,,v •. ADDRESSES I I);
RGDe r). STATION..BTATE-DISCONNI:C T_:;,
"
1.
17
3
3
3
RnOf r). DUFFER_STATUS_BUFFE'~_tj(JT _I!EAOVI
RnO I I ). INFO_lENgTH-OI
18 3 ENOl
1. 2 SMO-,4H, 1* U.ing DPLL. NRZI. ,,' Ii. TrMER I. I 6.2.' Kbp. _/
20 2 TMOD-21HI
21 2 THI-OFFHI
22 2· TCON-40H, 1* U •• time" 0 for r.r.l",. time out interrupt _I
23 2 u:-n:lH,
2. END POWER_ON.
2' XP1IT: PROCEDURE (CONTROLJlYTE);
2. DECLARE CONTROL_BYTE BYTE;
27 2 TCa-CONTROL_BYTE;
28 2 TBF-l;
296166-63
13-126
inter 8044 APPLICATION EXAMPLES
Pl/M-:H COMPILER RUPI-44 PT'imaT'1,J Station 20: 47: 13 09/2b/83 PAGE
2' 2 RTS-ll
30 3 DO WHILE NOT 51 j
31 3 END,
32 2 SI-O,
33 END XMITI
3' 2 TIMER_o_tNT: PROCEDURE INTERRUPT 1 UStNG 1;
3. 2 WAIT-O,
30 1 END TIMER_O_INTi
37 TIME_OUT: PROCEDURE BYTEJ /- T11u out ".turns true if there 1.11115" 't
• frame r.cwi .... d within 200 InS.C.
l ' there wa. II frame received within
200 m.lle then timlt_out returns falslt. *1
3. DECLARE BYTE AUXILIARY,
3. DO 1-0 TO 3,
40 3 WAIT-I;
41 3 THO-3CH;
..
42 3 TLO-OAFHI
43
4'
,
3 TRO-li
DO WHILE WAlTl
IF 51-1
4
THEN OOTO T _011
47 END,
4. ENOl
4' 2 RETURN TRUE;
.0 2
SI=Q.
51 RETURN FALSEI
.2
..
03 SEND_DISC: PROCEDURE,
•• TBL ..OJ
CALL XMITCDIGC) I
.0 IF TIME_OUr-FALGE
THEN IF RCO-UA OR RCO-OM
.7 3 THEN 001
••
00
3
3
RSDCSTATIQN NUMBER) llUFFER_!3TATUS-BUFFER_NOT_READYI
RSOCSTATlON:NUHDER). mAT ION ..~) rATE-DISCONNECT _Si
01 3 ENOl
62 2
63
6' SENO_SNRH: PROCEDUREi
O.
296166-64
13-127
inter 8044 APPLICATION EXAMPLES
PL/I'I-:U CQHPIlER 20: 47: 13 09/:l6/B3 PAOE
66 2 CALL XHJ:T(SNRf'1)1
67 2 IF (TIt1E_OUT-FALSEJ AND (Rca-UAl
THEN DO;
69 3 RBDCSTATlDN_NUf'lDERI . STATlON_STATE-I_T _5;
70 3 RSDCSTATION_NUf'lBER). NSzOI
71 3 RSDCSTATION_NUI'IBERJ. NR=OI
72 3 ENDi
73 2
74
7S 2 CHECK,J4S: PROCEDURE BYTE;
76 2 IF (RSDCSTATlDN NUKBER). NR-CSHRCRCD.ll AND 07H)
THEN RETURN -TRUE;
7S . ELSE RETURN F ALBE.
~9 END CHECK_NSi
SO 2 CHECK~: PROCEDURE BYTE;
'* Chull the Nr flield 0' the receivl'd 'rami. IF Ns{P)+l-NT"(SI thl'n th. frame
*'
h., b •• n acknowledged. else if U,n""Nr(S) thl'n th. 'T'ame he, nDt bit."
.-cknowledged. el •• ,. ••• t the '.'Clnderl,j
SI IF «CRSD(STATIDN_NUI'1DERLNS + II AND 07HJ I I SHRIRCB.5)
THEN DOi
S3 3 RSD(STATIOt~J"UMBERJ. Nn .. c I RSDCSTATION_NUMOERI. NS+l) AND 07H)1
S4 3 RSDCSTATION_NUHBER),INrO_LENQTH-OJ
S' 3 ENOl
S6 2 ELSE IF (RSDCSTATION_NUI'IBERL NS ,'.> ~;IfRIRCB. 5))
THEN RETURN FALSEl
SS 2 RETURN TRUEI
90 2 RECEIVE: PROCEDURE J
91 2 DECLARE BYTE AUXII,IMlY.
92 RSD (ST~TION_NUI1BER), BUFFER_r. TItt. TUG-DUFFER_READY,
'* I' an RNR '!HIS received buf'er_"t.t". will be chang.d in the ."furvisor ..
frallle decode .ection futher do"'n PI this procedure. an\l nth." r •• pons.
m•• n" the remote st.Uons bu'fe,. I, r"ld~ *'
93 2 IF (RCB AND 01H)-O
9. 3
THEN 001 '*
I Fr.me Recuv.d *'
JF (CHECK~S·TRU[ AND BOV-O AND CHECK_NR-TIIUI'I
THEN 001
97 4 RSDISTATlON_NUI'IBER). NR"" IRSDf!iTAT ION_NlIf'IBER)' NR+l) AND 07H);
9S 4 RDP" ••
296166-65
13-128
inter 8044 APPLICATION EXAMPLES
PL./M-5t COMPILER RUPI-44 Primary Station 20: 47: 13 09/20/83 PAGE
••
100
REC\! _F IELD _LENCTH=RFL-l;
END;
101 :3 ELSE RSO(STATION_NUMBER). STATION_STATE=GO_TO_DI5C;
102 3 END;
103 :2 ELSE IF (RCB AND 03HI""OlH
10.
THEN DO; '*
5up.T'vi50r~ fram. T'lIcl!ived *1
IF CHECK_NR::FALSE
THEN RSO(STATION_NUMDERL STATION_STATE=gO_TO_OISC,
107 ELSE IF «(RCD AIm OFIIl-O:H~1 ,* th.n RNR *1
THEN RSD (OTATION_NUMBER I. BUFFER_STATUS .. eUFFER_NOT _READY;
10' ENOl
110 3 ELSE 001 /* Unnumbered 'r.m. or unknown h'ame received */
111 3 IF RCB-FRHR
THEN DO; 1* If FRHR "'.5 received check NT' foT' an
acknowledged I h'aml' *1
113 4 RCB-SIU_RECV_BUFFER( 11 j
114 4 I=CHECI<._NRj
END;
"'
11.
117
4
3
3 ENOl
RSO( STATION_NUMBER). STATlON_STATE",QO_TOJ)ISCj
l1B
END RECEIVE;
"'
"0
12i DECLARE TEMP DYTE;
IF TEMP-T _I _FRAME
'" THEI~ DOl 1* Transmit I frame *1
I_ Transftl'r the station buff_r into internal ram *1
124 DO TEMP"O TO RSD(STATION_NUMOCHl. INFO_LENGTH-1;
12. SIU XMIT BUFFER<TEMP) .. RSD(STATION NUMBER). DATAlTEHP);
12. ENO;- - -
1* Build ttle I frilml' control '1.1d *1
"7 3 TEMP .. tGHL(RSD<STATION NUMDER).lm.~) OR SHL<RSO<STATION NUHULll l NS. 1) OR 10H)j
,,.
12B 3
3
TDl"RGDt STATION_NUMBER). INFO_LENGTH;
CAll XHlTlTEMPl,
IF TINE OUT .. FALSE
-
130 3
THEN CALL RECEIVEi
13' 3 ENOl
133 3 ELSE DOi 1* Tr4n.ml t RR or RNR*I
134 3 IF TENP .. r _llR
THEN Tf:MP-RR;
13. 3 ELSE TEMp"UNfll
296166-66
13-129
intJ 8044 APPLICATION EXAMPLES
Pl/1'I-51 COI1PILER 20: 47 13 09/26/83 PACE 6
137 3 TEMP-CSHL.(RSDCSTATIDN_NUf'lBEA). HR.:n OR TEMP) I
138 3 TBl-O.
139 3 CALL XI'1ITCTEf1Pll
140 3 IF TUfE_DUT-FALSE
THEN CALL RECEIVE;
142 3 ENOl
143 1 END XttIT _I_T _81
144 2 BUFFER_TRANSFER: PROCEDUREI
145 2 DECLARE I BYTE AUXILIARV,
J BYTE AUXILIARY,
146 3 DO 1-0 TO NUf1BER_OF _STATJONS-I,
147 3 IF RSDC I). STATION_ADDRESS-SJU_"CCV..:..BUFFERcOt
THEN OOTD T 1 J
149 3 ENDI
100 2 11; '* If t.he .ddr •••• d .t.tion da .. s nat .. lit.,.,
the" d lsc.rd the data */
THEN 001
152 3 RBP-O,
153 3 RETURNI
154 3 END;
155 2 ELSE IF RSD ( I). INFO_LENCTH-O
THEN DOl
157 3 RSOC I J. INFD_LENCTH-lIreV_FIELD_LENOTHi
158 4 DO "-I TO RECV_FJEU). LENCHHI
159 4 RSOC I J. DATAC.J-ll-nlU_RECY_BUFFERhJl;
160
161 •
3
END.
RBP-=O;
162 3 ENO,
163
16. SEOIN:
CALL POWDf _ON;
165 2 DO FOREVr.R,
166 3 DO fiTATlON.-NUf"lBER-O TO NUf"lDDf.JW_r.TATIDNS-ll
167 3 r.T~D-RSD(STATlON_NUftBER' IiTATION_"OORESSJ .
168 3 IF RSO(STATION.-NUMBERI. GTATION_STATE - DISCDNNECT_~
THEJII CALL SEND_SHAM,
170 ELSE IF RSD(STATlDN_NUMnr U) £iTATIDN_STATE • GO_TO_Ollie
THEN CALL SEND_nne.
172 3 ELSE IF I (RSDISTATlON_NUMUI.II) INFO_LENGTH>O) AND
(RSD(STATJON ..NU11BER). BUFFER_STATUS-BUFFER_READY))
THEN CALL XMIT_I .•T_!>IT_IJRAME);
17. ELSE IF RBP-O
THEN CALL XMIT_J •.T_SIT_RR);
176 3 ELSE CALL XMIT_I_T_SIT_RNrI),
177 3 IF ROP-1
THEN CALL BUFFER_TRANSFER i
296166-67
PLItt-51 COMPILER RUPI-44 Prim.t'll Station 20: 47: 13 09/26/83 PAC£:
179 3 END;
ISO END.
t91 END MAIN_MODI
WARNINQS:
1 IS THE HIGHEST USED INTERRUPT
MODULE " ..FORMATlDN: CSTATIC+QVERlAVABLE)
. CODE SIlE .. 093DH 13410
CONSTANT 61 ZE • 0002H 20
DIRECT VARIABLE SIZE 40H+02H 640+ 20
INDIRECT VARIABL.E SIlE 40H+OOH 640+ 00
BIT SIZE 0IH+OOH 10+ 00
DIT-ADDRESSABLE 51 ZE OOH+OOH 00+ 00
AUXILIARY VARIABLE SIZE .. 0093H 1470
MAX U'IV" STACK SIZE .. 001lj1H 250
REGISTER-BANK IS) USED: o I
4:56 LINES READ
o PROGRAM ERRORCS) .
END OF PL/I'1-51 COMPILATION
296166-68
13-130
8044AH/8344AH/8744H
HIGH PERfORMANCE 8-B~T MICROCONTROLLER
WITH ON-CHIP SERIAL COMMUNICATION CONTROLLER
a 8044AH-lncludes Factory Maslc Programmable ROM
iii 8~44AH-For Use with /External Program Memory
iii 8744H-lncludes User Programmable/Eraseable EPROM
8051. MICROCONTROLLER CORE SERIAL INTERFACE UNIT (SIU)
ill Optimized for Real Time Control 12 Ill! Serial Comm'unication Processor that
MHz Clock, Priority Interrupts, 32 Operates Concurrently to CPU
Programmable I/O Lines, Two 16-bit II\) 2.4 Mbps Maximum Data Rate
TimerICounters
III 375 Kbps using On-Chip Phase Locked
1m Boolean Processor Loop
IlIl 4K x 8 ROM, 192 x 8 RAM Il:l Communication Software in Silicon:
0 64K Accessible /E),ternal Program - Complete Data Link Functions
Memory - Automatic Station Response
[JJ 64K Accessible External Data Memory [j Operates as an SDLC Primary or
Secondary Station
Lit 4 p,s Multiply and Divide
The RUPI-44 family integrates a hi~lh performance 8-bit Microcontroller, the Intel 8051 Core, with an Intelli··
gent/high performance HOLC/SOLe serial communication controller, called the Serial Interface Unit (SIU),
See Figure 1. This dual architecture allows complex control and high speed data communication functions to
be realized cost effectively.
Specifically, the 8044's Microcontrollur features: 4K byte On·Chip program memory space; 32 110 lines; two
16-bit timerlevent counters; a 5-sourcu; 2-level interrupt structure; a full duplex serial channel; a Boolean
processor; and on-chip oscillator and clock circuitry. Standard TTL and most byte-oriented MCS-80 and MCS-
85 peripherals can be used for 1/0 amd memory expansion.
The Serial Interface Unit (SIU) manage!; the interface to a high speed serial link. The SIU offloads the On-Chip
8051 Microcontroller of communicatioll tasks, thereby freeing the CPU to concentrate on real time control
tasks.
The RUPI-44 family consists of the 8044, 8744, and 8344. All three devices are identical except in respect of
on-Chip program memory. The 8044 contains 4K bytes of mask-programmable ROM. User programmable
EPROM replaces ROM in the 8744. The 8344 addresses all program memory externally.
The RUPI-44 devices are fabricated with Intel's reliable + 5 volt, silicon-gate HMOSII technology and pack-
aged in a 40-pin DIP.
The 8744H is available in a hermetically sealed, ceramic, 40-lead dual in-line package which includes a
window that allows for EPROM erasure when exposed to ultraviolet light (See Erasure Characteristics). During
normal operation, ambient light may adversely affect the functionality of the chip. Therefore applications which
expose the 8744H to ambient light may require an opaque label over the window.
8044's Dual Controller Architecture
HOLCI
SOLC
port
231663-1
Figure 1. Dual Controller Architecture
September 1990
13-131 Order Number: 2:11663-004
8044AH/8344AH/8744H
Table 1. RUPITM·44 Family Pin Description
VSS - DATA TxD (P3.1) In point-to-point or multipoint
configurations, this pin functions as data input!
Circuit ground potential. output. In loop mode, it serves as transmit pin.
A '0' written to this pin enables diagnostic
mode.
vee
- INTO (P3.2): Interrupt 0 input or gate control
+ 5V power supply during operation and program input for counter O.
verification. - INT1 (P3.3). Interrupt 1 input or gate control
input for counter 1.
PORT 0 - TO (P3.4). Input to counter O.
Port 0 is an 8-bit open drain bidirectional I/O port.
It is also the multiplexed low-order address and - SCLK T1 (P3.5). In addition to I/O, this pin pro-
data bus when using external memory. It is usod vides input to counter 1 or serves as SCLK (se-
for data output during program verification. Port 0 rial clock) input.
can sink/source eight LS TTL loads (six in 8744). - WR (P3.6). The write control signal latches the
data byte from Port 0 into the External Data
Memory.
PORT 1
- RD (P3.7). The read control signal enables Ex-
Port 1 is an 8-bit quasi-bidirectional I/O port. It is ternal Data Memory to Port O.
used for the low-order address byte during pro·
gram verification. Port 1 can sink/source four LS
TTL loads. RST
A high on this pin for two machine cycles while the
In non-loop mode two of the I/O lines serve altor·
oscillator is running resets the device. A small ex-
nate functions: ternal pulldown resistor (;::; 8.2Kfi) from RST to
- RTS (P1.6). Request-to-Send output. A low in- Vss permits power-on reset when a capacitor
dicates that the RUPI-44 is ready to transmit. (;::; 10ftf) is also connected from this pin to Vcc.
- CTS (P1.7) Clear-to-Send input. A low indicates
that a receiving station is ready to receive.
ALE/PROG
Provides Address Latch Enable output used for
PORT 2 latching the address into external memory during
Port 2 is an 8-bit quasi-bidirection I/O port. It also normal operation. It is activated every six oscillator
emits the high-order address byte when accessing periods except during an external data memory ac-
external memory. It is used for the high-order ad- cess. It also receives the program pulse input for
dress and the control signals during program verifi- programming the EPROM version.
cation. Port 2 can sink/source four LS TTL loads.
PORT 3
The Program Store Enable output is a control sig-
Port 3 is an 8-bit quasi-bidirectional I/O port. It also nal that enables the external Program Memory to
contains the interrupt, timer, serial port and RD the bus during external fetch operations. It is acti-
and WR pins that are used by various options. The vated every six oscillator periods, except during
output latch corresponding to a secondary function external data memory accesses. Remains high
must be programmed to a one (1) for that function during internal program execution.
to operate. Port 3 can sink/source four LS LTT
loads.
EAlVPP
In addition to I/O, some of the pins also serve al- When held at a TTL high level, the RUPI-44 exe-
ternate functions as follows: cutes instructions from the internal ROM when the
- I/O RxD (P3.0). In point-to-point or multipoint PC is less than 4096. When held at a TTL low
configurations, this pin controls the direction of level, the RUPI-44 fetches all instructions from ex-
pin P3.1. Serves as Receive Data input in loop ternal Program Memory. The pin also receives the
and diagnostic m9des. 21V EPROM programming supply voltage on the
8744.
13-132
8044AH/8344AH/8744H
Table 1. RUPITM-44 Family Pin Description (Continued)
XTAL 1 XTAL 2
Input to the oscillator's high gain amplifier. Re- Output from the oscillator's amplifier. Input to the
quired when a crystal is used. Connect to VSS internal timing Circuitry. A crystal or external source
when external source is used on XTAL 2. can be used.
Pl.D vee
VI Pl,1 PO.O ADO
Pl.2
i=}!
PO.' AD'
P'1 PO.2 AD2
~:: ~
Q. ..
Pl.'
P'.S
PO.3
PO.O
AD3
ADO
__ V I
w
VI RTS Pl.e PO.S ADS
'" ffi Pl.7 PO.a Alii
i[.~
RST PO.T ADT
110 RXO P3.D Eli ·vpp
DATA TKO P3,1 ALE PiiOG
INTO Pl,2 Pmi
r' . '-~
INT1 Pl,) P2.1 A'S
_ CT5 TO P3,4 P2.0 A'O
•
'" Sel" f. P3.S P2.5 11.'3
~}~'
fi DATA ~~
WR PM P2.4 A'2
AD P3.T P2.3 Al1
~ ::~~~ ~ "'-'" XTAl2 P2.2 A'O
~ TO~ ~ ~ ---. ~ XTAl1 P2.l A9
~ SClK T' ....... a.. _ c
- 0
Q VSS P2.0 A8
~ WA~
~ iffi .....
VI 231663-:1
231663-2
Figure 2. Logic Symbol Figure 3A. DIP Pin Configuration
"": "1 "! -: q oq N
ci ci '"
U
Cl: Cl: Cl: Cl: Cl: "-
z >0 0 ci
a. a. a. a.
P1.5 7 39 PO.4
P1.6 8 38 PO.5
P1.7 9 37 PO.6
RST/VPD 10 36 PO.7
P3.0 11 35 EA
N/C 12 8044 34 N/C
P3.1 13 8344 33 ALE
P3.2 14 32 PSEN
P3.3 15 31 P2.7
P3.4 16 30 P2.6
P3.5 P2.5
.:::; N ....
'"a.t<i ""a.t<i N
...
UlU
£
0
'"
-'
f0-
x
~ >VI
x '" '" '" '"
~ a. a. a. a.
231663-21
Figure 36. PLCC Pin Configuration
13-133
inter 8044AH/8344AH/8744H
FREQUENCE
REFERENCE
r--
I DATA
I HI·-~.. ~gLC/SDLC
I '-T--...... II SERIAL
COMMUNICATIONS
I
I I
I Lr-r-~ I
I I
I I
I INTERRUPTS '---T"'T-.....
L 1----
INTERRUPTS CONTROL PARALLEL PORTS COUNTERS
.J
I
ADDRESS DATA BUS
AND 1/0 PINS 231663-4
Figure 4. Block Diagram
FUNCTIONAL DESCRIPTION • 4K bytes of ROM
• 192 bytes of RAM
General • 32110 lines
Tho 8044 integrates the powerful 8051 microcontrol· • 64K address space for external Data Memory
ler with an intelligent Serial Communication Control· • 64K address space for external Program Memory
ler to provide a single·chip solution which will effi· • two fully programmable 16-bit timer/counters
ciently implement a distributed processing or distrib·
uted control system. The microcontroller is a self· • a five-source interrupt structure with two priority
sufficient unit containing ROM, RAM, ALU, and its levels
own peripherals. The 8044's architecture and in· • bit addressability for Boolean processing
struction set are identical to the 8051 'so The 8044
replaces the 8051 's serial interface with an intelli- SPECIAL
FUNCTION
gent SOLC/HOLC Serial Interface Unit (SIU). 64 REGISTERS
~
more bytes of RAM have been added. to the 8051
RAM array. The SIU can communicate at bit rates up
to 2.4 M bps. The SIU works concurrently with the
Microcontroller so that there is no throughput loss in RAM
rn 255 24' F8H
FOH
.IH
.OH
OIH
DOH
C.H
1
ADDRESS·
{D
either unit. Since the SIU possesses its own intelli- ~;;; COH
A8lE
gence, the CPU is off-loaded from many of the com- .'H
.OH
BITS IN
SFRI
(12I1BIT5)
·munications tasks, thus dedicating more of its com- INDIRECT "H
AOH
ADDRESS-
puting power to controlling local peripherals or some ING "H
90H
external process. "H
!!! 135 1:111 BOH
DIRECT
'" ADDRESS·
ING
The Microcontroller
The microcontroller is a stand-alone high-perform-
ance single-chip computer intended for use .in so-
phisticated real-time application such as instrumen-
tation, industrial control, and intelligent computer pe-
ripherals.
INTERNAL SPECIAL FUNCTION
The major features of the micro controller are: DATA RAM REGISTERS 231663-5
• 8-bit CPU Figure 5. Internal Data Memory Address Space
• on-chip oscillator
13-134
8044AH/8344AH/8744H
• 1 /-ts instruction cycle time for 60% of the instruc- Parallel 1/0
tions 2 p.s instruction cycle time for 40% of the
instructions The 8044 has 32 general-purpose I/O lines which
• 4 p.s cycle time for 8 by 8 bit unsigned Multiply/ are arranged into four groups of eight lines. Each
Divide group is called a port. Hence there are four ports;
Port 0, Port 1, Port 2, and Port 3. Up to five lines
from Port 3 are dedicated to supporting the serial
INTERNAL DATA MEMORY channel when the SIU is invoked. Due to the nature
of the serial port, two of Port 3's I/O lines (P3.0 and
Functionally the Internal Data Memory is the most P3.1) do not have latched outputs. This is true
flexible of the address spaces. The Internal Data whether or not the serial channel is used.
Memory space is subdivided into a 256-byte Internal
Data RAM address space and a 128-bit Special Port 0 and Port 2 also have an alternate dedicated
Function Register address space as shown in Figure function. When placed in the external access mode,
5. Port 0 and Port 2 become the means by which the
8044 communicates with external program memory.
The Internal Data RAM address space is 0 to 255. Port 0 and Port 2 are also the means by which the
Four 8-Register Banks occupy locations 0 through 8044 communicates with external data memory. Pe-
31. The stack can be located anywhere in the Inter- ripherals can be memory mapped into the address
nal Data RAM address space. In addition, 128 bit space and controlled by the 8044.
locations of the on-chip RAM are accessible through
Direct Addressinq. These bits reside in Internal Data
RAM at byte locations 32 through 47. Currently loca-
tions 0 through 191 of the Internal Data RAM ad-
dress space aro filled with on-chip RAM.
Table 2. MCS®-S1 Instruction Set Description
Mnemonic Description Byte Cyc Mnemonic Description Byte Cyc
ARITHMETIC OPERATIONS ARITHMETIC OPERATIONS (Continued)
ADD A,Rn Add register to SUIH] A,@Ri Subtract indirect
Accumulator RAM from A with
ADD A,direct Add direct byte Borrow
to Accumulator 2 SUBB A,#data Subtract immed
ADD A,@Ri Add indirect data from A with
RAM to Borrow 2
Accumulator INC A Increment
ADD A,#data Add immediate Accumulator
data to INC Rn Increment
Accumulator 2 register
AD DC A,Rn Add register to INC direct Increment direct
Accumulator byte 2
with Carry INC @Ri Increment
AD DC A,direct Add direct byte indirect RAM
to A with Carry INC DPTR Increment Data
flag 2 Pointer 2
AD DC A,@Ri Add indirect DEC A Decrement
RAM to A with Accumulator
Carry flag DEC Rn Decrement
AD DC A,#data Add immediate register
data to A with DEC direct Decrement
Carry flag 2 direct byte 2
SUBB A,Rn Subtract register DEC @Ri Decrement
from A with indirect RAM
Borrow MUL AB Multiply A & B 4
SUBB A,direct Subtract direct DIV AB DivideAby B 4
byte from A with DA A Decimal Adjust
Borrow 2 Accumulator
13-135
inter B044AH/B344AH/B744H
Table 2. MCS®·51 Instruction Set Description (Continued)
Mnemonic Description Byte Cyc Mnemonic Description Byte Cyc
LOGICAL OPERATIONS LOGICAL OPERATIONS (Continued)
ANL A,Rn AND register to RL A Rotate
Accumulator Accumulator
ANL A,direct AND direct byte Left
to Accumulator 2 RLC A Rotate A Left
ANL A,@RI AND indirect through the
RAM to Carry flag
Accumulator RR A Rotate
ANL A,#data AND immediate Accumulator
data to Right
Accumulator 2 RRC A Rotate A Right
ANL direct,A AND through Carry
Accumulator to flag
direct byte 2 SWAP A Swap nibbles
ANL direct,#data AND immediate within the
data to direct Accumulator 1 - 1
byte 3 2 DATA TRANSFER
ORL A,Rn OR register to MOV A,Rn Move register to
Accumulator Accumulator
ORL A,direct OR direct byte to MOV A,direct Move direct byte
Accumulator 2 to Accumulator 2
ORL A,@Ri OR indirect RAM MOV A,@RI Move indirect
to Accumulator RAM to
ORL A,#data OR immediate Accumulator
data to MOV A,#data Move immediate
Accumulator 2 data to
ORL direct,A OR Accumulator Accumulator 2
to direct byte 2 MOV Rn,A Move
ORL direct, # data OR immediate Accumulator to
data to direct register
byte 3 2 MOV Rn,direct Move direct byte
XRL A,Rn Exclusive-OR to register 2 2
register to MOV Rn,#data Move immediate
Accumulator data to register 2
XRL A,direct Exclusive-OR MOV direct,A Move
direct byte to Accumulator to
Accumulator 2 direct byte 2
XRL A,@RI Exclusive-OR MOV direct,Rn Move register to
indirect RAM to direct byte 2 2
A MOV direct,direct Move direct byte
XRL A,#data Exclusive-OR to direct 3 2
immediate data MOV direct,@Ri Move indirect
toA 2 RAM to direct
XRL direct,A Exclusive-OR byte 2 2
Accumulator to MOV direct,#data Move immediate
direct byte 2 data to direct
XRL direct,#data Exclusive-OR byte 3 2
immediate data MOV @Ri,A Move
to direct 3 2 Accumulator to
CLR A Clear indirect RAM
Accumulator MOV @Ri,direct Move direct byte
CPL A Complement to indirect RAM 2 2
Accumulator
13-136
intJ 8044AH/8344AH/8744H
Table 2. MCS®·51 Instruction Set Description (Continued)
Mnemonic Description ByteCyc Mnemonic Description Byte Cyc
DATA TRANSFER (Continued) BOOLEAN VARIABLE MANIPULATION
MOV @Ri,#data Move immediate (Continued)
data to indirect ANL C,/bit AND
RAM 2 complement of
MOV DPTR, # data 16 Load Data direct bit to
Pointer with a Carry 2 2
16-bit constant 3 2 ORL C/bit OR direct bit to
MOVCA,@A+ DPTR Move Code byte Carry flag 2 2
relative to DPTR ORL C,/bit OR complement
to A 2 of direct bit to
MOVCA,@A+PC Move Code byte Carry 2 2
relative to PC to MOV C,/bit Move direct bit
A 2 to Carry flag 2
MOVXA,@Ri Move External MOV bit,C Move Carry flag
RAM (8-bit addr) to direct bit 2 2
toA 2
MOVXA,@DPTR Move External PROGRAM AND MACHINE CONTROL
RAM (16-bit ACALL addr11 Absolute
addr) to A 2 Subroutine Call 2 2
MOVX@Ri,A Move A to LCALL addr16 Long Subroutine
External RAM Call 3 2
(8-bit addr) 2 RET Return from
MOVX @DPTR,A Move A to subroutine 2
External RAM RETI Return from
(16-bit) addr 2 interrupt 1 2
PUSH direct Push direct byte Absolute Jump 2 2
AJMP addr11
onto stack 2 2
LJMP addr16 Long Jump 3 2
POP direct Pop direct byte
SJMP rei Short Jump
from stack 2 2
(relative addr) 2 2
XCH A,Rn Exchange
JMP @A + DPTR Jump indirect
register with
relative to the
Accumulator
DPTR 2
XCH A,direct Exchange direct
JZ rei Jump if
byte with
Accumulator is
Accumulator 2 Zero 2 2
XCH A,@Ri Exchange
Jump if
JNZ rei
indirect RAM Accumulator is
with A Not Zero 2 2
XCHD A,@Ri Exchange low- Jump if Carry
JC rei
order Digit ind 2
flag is set 2
RAMwA
JNC rei Jump if No Carry
flag 2 2
. BOOLEAN VARIABLE MANIPULATION Jump if direct Bit
JB bit,rel
CLR C Clear Carry flag 1. set 3 2
CLR bit Clear direct bit 2 JNB bit, rei Jump if direct Bit
SETB C Set Carry Flag 1 Not set 3 2
SETB bit Set direct Bit 2 JBC bit,rel Jump if direct Bit
CPL C Complement is set & Clear bit 3 2
Carry Flag CJNE A,direct,rel Compare direct
CPL bit Complement to A &Jump if
direct bit 2 Not Equal 3 2
ANL C,bit AND direct bit to CJNE A,#data,rel Comp, immed,
Carry flag 2 2 to A & Jump if
Not Equal 3 2
13-137
intJ 8044AH/8344AH/8744H
Table 2. MCS®-S1 Instruction Set Description (Continued)
Mnemonic Description Byte Cyc Notes on data addressing modes:
PROGRAM AND MACHINE CONTROL (Continued)
(Continued) #data - 8-bit constant included in instruction
CJNE Rn,#data,rel Comp, fmmed, #data16 - 16-bit constant included as bytes 2
to reg & Jump if & 3 of instruction
Not Equal 3 2 bit - 128 software flags, any liD pin, con-
CJNE @Ri,#data, rei Comp, immed, troll or status bit
to indo & Jump if
Not Equal 3 2 Notes on program addressing modes:
DJNZ Rn,rel Decrement addr16 - Destination address for LCALL &
register & Jump LJMP may be anywhere within the
if Not Zero 2 2 64-K program memory address
DJNZ direct,rel Decrement space
direct & Jump if Addr11 - Destination address for ACALL &
Not Zero 3 2 AJMP will be within the same 2-K
NOP No operation 1 page of program memory as the first
byte of the following instruction
Notes on data addressing modes: rei - SJMP and all conditional jumps in-
Rn - Working register RO-R7 clude an 8-bit offset byte, Range is
direct -128 internal RAM locations, any I/O '1- 127 . 128 bytes relative to first
port, control or status register byte of tho following instruction
@Ri -Indirect internal RAM location ad· All mnemoniC copyrightod@ Intel Corporation 1979
dressed by register RO or R1
Timer/Counters Serial Interface Unit (SIU)
The 8044 contains two 16-bit counters which can be The Serial Interface Unit is used for HDLC/SDLC
used for measuring time intervals, measuring pulse communications. It handles Zero Bit Insertion/Dele-
widths, counting events, generating precise periodic tion, Flags automatic access recognization, and a
interrupt requests, and clocking the serial communi- 16-bit cyclic redundancy check. In addition it imple-
cations. Internally the Timers are clocked at 1112 of ments in hardware a subset of the SDLC protocol
the crystal frequency, which is the instruction cycle certain applications it is advantageous to have the
time. Externally the counters can run up to 500 KHz. CPU control the reception or transmission of every
single frame. For this reason the SIU has two modes
of operation: "AUTO" and "FLEXIBLE" (or "NON-
Interrupt System AUTO"). It is in the AUTO mode that the SIU re-
sponds to SDLC frames without CPU intervention;
External events and the real-time driven on-chip pe- whereas, in the FLEXIBLE mode the reception or
ripherals require service by the CPU asynchronous transmission of every single frame will be under CPU
to the execution of any particular section of code. To control.
tie the asynchronous activities of these functions to
normal program execLition, a sophisticated multiple- There.are three control registers and eight parame-
source, two priority level, nested interrupt system is ter registers that are used to operate the serial inter-
provided. Interrupt response latency ranges from 3 face. These registers are shown in Figure 5 and Fig-
JLsec to 7 JLsec when using a 12 MHz clock. ure 6. The control register set the modes of opera-
tion and provide status information. Theeightpa-
All five interrupt sources can be mapped into one of rameter registers buffer the station address, receive
the two priority levels. Each interrupt source can be and transmit control bytes, and point to the on-Chip
enabled or disabled individually or the entire inter- transmit and receive buffers.
rupt system can be enabled or disabled. The five
interrupt sources are: Serial Interface Unit, Timer 1, Data to be received or transmitted by the SIU must
Timer 2, and two external interrupts. The external be buffered anywhere within the 192 bytes of on-
interrupts can be either level or edge triggered. chip RAM. Transmit and receive buffers are not al-
lowed to "wrap around" in RAM; a "buffer end" is
generated after address 191 is reached.
13-138
8044AH/8344AH/8744H
SYMBOLIC BYTE
REGISTER NAMES ADDRESS BIT ADDRESS ADDRESS
~
B REGISTER B 247 through 240 240 (FOH)
ACCUMULATOR ACC 231 t rou 224 224 (EOH)
·THREE BYTE FIFO FIFO 223 (DFH)
FIFO 222 (DEH)
FIFO 221 (DOH)
TRANSMIT BUFFER START TBS 220 (DCH)
TRANSMIT BUFFER lENGTH TBl 219 (DBH)
TRANSMIT CONTROL BYTE TCB 216 (DAH)
• SIU STATE COUNTER SIUST 217 (D9H)
SEND COUNT RECEIVE COUNT NSNR 223 t rou 216 216 (D6H)
PROGRAM STATUS WORD PSW 215 t rou 208 206 (DOH)
°DMA COUNT DMA CNT 207 (CFH)
STATION ADDRESS STAD 206 (CEH)
RECEIVE FIELD lENGTH RFl 205 (CDH)
RECEIVE BUFFER START RBS 204 (CCH)
RECEIVE BUFFER lENGTH RBl 203 (CBH) SFR's CONTAINING
RECEIVE CONTROL BYTE RCB 202 (CAH) DIRECT ADDRESSABLE BITS
SERIAL MODE SMD 201 (C9H)
STATUS REGISTER STS 20i--tlirougn 200 200 (C6H)
INTERRUPT PRIORITY CONTROL IP 1-9-1--through 164 164 (D6H)
t83~---th,~n 176 176 (BOH)
PORT 3 P3
INTERRUPT ENABLE CONTROL IE 175 tnfough 168 166 (A6H)
PORT 2 P2 167 Ihrough- 160 160 (AOH)
PORT 1 P1 151 I IQugl! 144 144 (90H)
TIMER HIGH 1 TH1 141 (6DH)
TIMER HIGH 0 THO 140 (6CH)
TIMER lOW 1 Tll 139 (6BH)
TIMER lOW 0 TlO 136 (6AH)
TIMER MODE TMOD 137 (69H)
TCON 143 t rou h~- 136 136 (eaH)
TIMER CONTROL
DATA POINTER HIGH DPH 131 (63H)
DATA POINTER lOW DPl 130 (B2H)
STACK POINTER SP 129 (61H)
PORT 0 PO 135 throu ·h 126 126 (BOH)
231663-6
NOTE:
'ICE Support Hardware registers. Under. normal operating comlilioll!: lilare is no nood for the CPU to access these
registers.
Figure 5. Mapping of Special Function Registers
SERIAL MODE REGISTER ISMD) SCM2 SCM1 SCMO NRZI lOOP PFS NB NFCS
L...--. NO FRAME CHECK SEQUENCE
I
I I NON·BUFFERED
PRE·FRAME nNC
lOOP
NON RETURN TO ZERO INVERTED
SELECT CLOCK MODE
STATUS REGISTER (STS) TBF RBE RTS SI BOV OPB AM RBP
L - - RECEIVE BUFFER PROTECT
I
I I
AUTO MODEl ADDRESSED MODE
OPTIONAL POll BIT
RECEIVE INFORMATION BUFFER OVERRUN
SERIAL INTERFACE UNIT INTERRUPT
REQUEST TO SEND
RECEIVE BUFFER EMPTY
TRANSMIT BUFFER FULL
SEND COUNT RECEIVE
COUNT REGISTER (NSNR) r-:=,..,.....,......=:;;-,,;F.;:-r-;;;;;;;;-. .Uii. . .;;;;;:T"';;;-J
SEQUENCE ERROR RECEIVED
L-_~_ _' -_ _ _ _ RECEIVE SeQUENCE COUNTER
SEQUENCE ERROR SEND
SEND SEQUENCE COUNTER
231663-7
Figure 6. Serial Interface Unit Control Registers
, 13-139
8044AH/8344AH/8744H
With the addition of only a few bytes of code, the lowing responses without CPU intervention: I (Infor-
8044's frame size is not limited to the size of its mation), RR (Receive Ready), and RNR (Receive
internal RAM (192 bytes), but rather by the size of Not Ready).
external buffer with no degradation of the RUPl's
features (e.g. NRZI, zero bit insertion/deletion, ad- When the Receive Buffer Empty bit (RBE) indicates
dress recognition, cyclic redundancy check). There that the Receive Buffer is empty, the receiver is en-
is a special function register called SIUST whose abled, and when the RBE bit indicates that the Re-
contents dictates the operation of the SIU. At low ceive Buffer is full, the receiver is disabled. Assum-
data rates, one section of the SIU (the Byte Proces- ing that the Receiver Buffer is empty, the SIU will
sor) performs no function during known intervals. respond to a poll with an I frame if the Transmit Buff-
For a given data rate, these intervals (stand-by er is full. If the Transmit Buffer is empty, the SIU will
mode) are fixed. The above characteristics make it respond to a poll with a RR command if the Receive
possible to program the CPU to move data to/from Buffer Protect bit (RBP) is cleared, or an RNR com-
external RAM and to force the SIU to perform some mand if RBP is set.
desired hardware tasks while transmission or recep-
tion is taking place. With these modifications, exter-
nal RAM can be utilized as a transmit and received FLEXIBLE (or NON-AUTO) Mode
buffer instead of the internal RAM.
In the FLEXIBLE mode all communications are un-
der control of the CPU. It is the CPU's task to en-
AUTO Mode code and decode control fields, manage acknowl-
edgements, and iidhere to the requirements of the
In the AUTO mode the SIU implements in hardware HOLC/SOLC protocols. The 8044 can be used as a
a subset of the SOLC protocol such that it responds primary or a secondary station in this mode.
to many SOLC frames without CPU intervention. 1\11
AUTO mode responses to the primary station will To receive a frame in the FLEXIBLE mode, the CPU
comform to IBM's SOLC definition. The advantag()~; must load the Receive Buffer Start register, the Re-
of the AUTO mode are that less software is required ceive Buffer Length register, clear the Receive Buff-
to implement a secondary station, and the hardwaru er Protect bit, and set the Receive Buffer Empty bit.
generated response to polls is much faster than do· If a valid opening flag is received and the address
ing it in software. However, the Auto mode can not field matches the byte in the Station Address regis-
be used at a primary station. ter or the address field contains a broadcast ad-
dress, the 8044 loads the control field in the receive
To transmit in the AUTO mode the CPU must load control byte register, and loads the I field in the re-
the Transmit Information Buffer, Transmit Buffer ceive buffer. If there is no CRC error, the SIU inter-
Start register, Transmit Buffer Length register, and rupts the CPU, indicating a frame has just been re-
set the Transmit Buffer Full bit. The SIU automatical- ceived. If there is a CRC error, no interrupt occurs.
ly responds to a poll by transmitting an information The Receive Field Length register provides the num-
frame with the P/F bit in the control field set. When ber of bytes that were received in the information
the SIU receives a positive acknowledgement from field.
the primary station, it automatically increments the
Ns field in the NSNR register and interrupts the To transmit a frame, the CPU must load the transmit
CPU. A negative acknowledgement would cause the information buffer, the Transmit Buffer Start register,
SIU to retransmit the frame. the Transmit Buffer Length register, the Transmit
Control Byte, and set the TBF and the RTS bit. The
To receive in the AUTO mode, the CPU loads the SIU, unsolicited by an HOLC/SOLC frame, will trans-
Receive Buffer Start register, the Receive Buffer mit the entire information frame, and interrupt the
Length register, clears the Receive Buffer Protect CPU, indicating the completion of transmission. For
bit, and sets the Receive Buffer Empty bit. If the SIU supervisory frames or unnumbered frames, the
is polled in this state, and the TBF bit indicates that transmit buffer length would be o.
the Transmit Buffer is empty, an automatic RR re-
sponse will be generated. When a valid information
frame is received the SIU will automatically incre- CRC
ment Nr in the NSNR register and interrupt the CPU.
The FCS register is initially set to all 1's prior to cal-
While in the AUTO mode the SIU can recognize and culating the FCS field. The SIU will not interrupt the
respond to the following commands without CPU in- CPU if a CRC error occurs (in both AUTO and FLEX-
tervention: I (Information), RR (Receive Ready), IBLE modes). The CRC error is cleared upon receiv-
RNR (Receive Not Ready), REJ (Reject). and UP ing of an opening flag.
(Unnumbered Poll). The SIU can generate the fol-
13-140
inter 8044AH/8344AH/8744H
Frame Format Options be stored in the Transmit and Receive buffers. For
example, in the non-buffered mode the third byte is
In addition to the standard SOLC frame format, the treated as the beginning of the information field. In
8044 will support the frames displayed in Figure 7. the non-addressed mode, the information field be-
The standard SOLC frame is shown at the top of this gins after the opening flag. The mode bits to set the
figure. For the remaining frames the information field frame format options are found in the Serial Mode
will incorporate the control or address bytes and the register and the Status register.
frame check sequences; therefore these fields will
FRAME OPTION NFCS NB AM1 FRAME FORMAT
Standard SOLC
NON-AUTO Mode
0 0 0 [F I AI C I I
I FCS I F I
Standard SOLC
AUTO Mode
0 0 1 [F IA IC I I I FCS I F I
Non"Buffered Mode
NON-AUTO Mode
0 1 1
~J A
I I
I FCS I F I
Non-Addressed Mode
NON-AUTO Mode
0 1 0
~I -
I I FCS I F
I
No FCS Field
NON-AUTO Mode
1 0 0
ITI . " I I C I
I F I
No FCS Field
AUTO Mode
1 0 1
I F I AI C I I
~- .. I F I
No FCS Field
Non-Buffered Mode
1 1 1
I F IA I I I Fl
NON-AUTO Mode
No FCS Field
Non-Addressed Mode
1 1 0 IF I I I F I I
NON-AUTO Mode
Mode Bits:
AM - "AUTO" Model Addressed Mode
NB - Non-Buffered Mode
NFCS - No FCS Field Mode
Key to Abbreviations:
F= Flag (01111110) I = Information Field
A= Address Field FCS= Frame Check Sequence
C= Control Field
Note 1:
The AM bit function is controlled by the NB bit. When NB = 0, AM becomes AUTO mode select, when NB = 1, AM
becomes Address mode select.
Figure 7. Frame Format Options
13-141
8044AH/8344AH/8744H
transmit and receive data in this mode at rates up to
Extended Addressing
2.4 Mbps.
To realize an extended control field or an extended
address field using the HDLC protocol, the FLEX- This self clocked mode allows data transfer without
IBLE mode must be used. For an extended control a common system data clock. An on-chip Digital
field, the SIU is programmed to be in the non-buff- Phase Locked Loop is employed to recover the data
ered mode. The extended control field will be the clock which is encoded in the data stream. The
first and second bytes in the Receive and Transmit DPLL will converge to the nominal bit center within
Buffers. For extended addressing the SIU is placed eight bit transitions, worst case. The DPLL requires a
in the non-addressed mode. In this mode the CPU reference clock of either 16 times (16x) or 32 times
must implement the address recognition for received (32x) the data rate. This reference clock may be ex-
frames. The addressing field will be the initial bytes ternally applied or internally generated. When inter-
in the Transmit and Receive buffers followed by the nally generated either the 8044's internal logic clock
control field. (crystal frequency divided by two) or the timer 1
overflow is used as the reference clock. Using the
TheSIU can transmit and receive only frames which internal timer 1 clock the data rates can vary from
are multiples of 8 bits. For frames received with oth- 244 to 62.5 Kbps. Using the internal logic clock at a
er than 8-bit multiples, a CRC error will cause 11)(' 16x sampling rate, receive data can either be 187.5
SIU to reject the frame. Kbps, or 375 Kbps. When tile reference clock for the
DPLL is externally applied the data rates can vary
from 0 to 375 Kbps at a 16x sampling rate.
SDLC Loop Networks
To aid in a Phase Locll()d Loop capture, the SIU has
The SIU can be used in an SDLC loop as a secclIld- a NRZI (Non Return to Zero Inverted) data encoding
ary or primary station. When the SIU is placed ill tiw and decoding option. Additionally the SIU has apre-
Loop mode it receives the data on pin 10 and trallS- frame sync option that transmits two bytes of alter-
mits the data one bit time delayed on pin 11. It C,ifl nating 1's and O's to ensure that the receive station
also recognize the Go ahead signal and chan(jl! it DPLL will be synchronized with the data by the time
illto a flag when it is ready to transmit. As a secolld- it receives the opening flag.
ary station the SIU can be used in the AUTO or
FI.EXIBLE modes. As a primary station the FI.D~
lill_E mode is used; however, additional hardwiU'· is Control and Status Registers
r,)quired for generating the Go Ahead bit pattern. In
the Loop mode the maximum data rate is 1 MlJps There are three SIU Control and Status Registers:
clocked or 375 Kpbs self-clocked. Serial Mode Register (SMD)
Status/Comm,md Register (STS)
SOLC Multidrop Networks Send/Receive Count Register (NSNR)
The SIU can be used in a SDLC non-loop configura- The SMD, STS, and NSNR, registers are all cleared
tion as a secondary or primary station. When the SIU by system reset. This assures that the SIU will power
is placed in the non-loop mode, data is received and up in an idle state (neither receiving nor transmit-
transmitted on· pin 11, and pin 10 drives a tri-state ting).
buffer. In non-loop mode, modem interface pins,
RTS and CTS, become available. These registers and their bit assignments are de-
scribed below.
Data Clocking Options
SMD: Serial Mode Register (byte-addressable)
The 8044's serial port can operate in an externally Bit 7: 6 5 4 3 2 1 0
clocked or self clocked system. A clocked system
provides to the 8044 a clock synchronization to the ISCM2!SCM1!SCMO! NRZI! LOOP! PFS! NB! NFCsl
data. A self-clocked system uses the 8044's on-chip
Digital Phase Locked Loop (DPLL) to recover the The Serial Mode Register (Address C9H) selects the
clock from the data, and clock this data into the Seri- operational modes of the SIU. The 8044 CPU can
al Receive Shift Register. both read and write SMD. The SIU can read SMD
but cannot write to it. To prevent conflict between
In this mode,a clock synchronized with the data is CPU and SIU access to SMD, the CPU should write
externally fed into the 8044. This clock may be gen- SMD only when the Request To Send (RTS) and
erated from an External Phase Locked Loop, or pos-
sibly supplied along with the data. The 8044 can
13-142
inter 8044AH/8344AH/8744H
Receive Buffer Empty (RBE) bits (in the STS regis- CPU, and enables the SIU to post status information
ter) are both false (0). Normally, SMD is accessed for the CPU's access. The SIU can read STS, and
only during initialization. can alter certain bits, as indicated below. The CPU
can both read and write STS asynchronously. How-
The individual bits of the Serial Mode Register areas ever, 2-cycle instructions that access STS during
follows: both cycles ('JBC/B, REL' and 'MOV /B, C.') should
not be used, since the SIU may write to STS be-
Bit# Name Description tween the two CPU accesses.
SMD.O NFCS No FCS field in the SDLC frame. The individual bits of the Status/Command Register
SMD.1 NB Non-Buffered mode. No control are as follows:
field in the SDLC frame.
---
SMD.2 PFS Pre-Frame Sync modo. In this Bit# Name Description
mode, the 8044 transmits two STS.O RBP Receive Buffer Protect. Inhibits
bytes before the first flag of a writing of data into the receive
frame, for DPLL synchronization. buffer. In AUTO mode, RBP
If NRZI is enabled, OOH is sent; forces an RNR response instead
otherwise, 55H is sent. In either of an RR.
case, 16 preframe transitions are
guaranteed. STS.1 AM AUTO Model Addressed Mode.
Selects AUTO mode where
SMD.3 LOOP Loop configuration. AUTO mode is allowed. If NB is
SMDo4 NRZI NRZI coding option. If bit = 1, true, (= 1), the AM bit selects the
NRZI coding is used. If bit = 0, addressed mode. AM may be
then it is straight binary (NRZ). cleared by the SIU.
SMD.5 SCMO Select Clock Mode-Bit 0 STS.2 OPB Optional Poll Bit. Determines
SMD.6 SCM1 Select Clock Mode-Bit 1
SMD.7 SCM2 Select Clock Mode-Bit 2
The SCM bits decode as follows: STS.3 BOV
whether the SIU will generate an
AUTO response to an optional
poll (UP with P = 0). OPM may
be set or cleared by the SIU.
Receive Buffer Overrun. BOV
II
may be set or cleared by the SIU.
SCM Data Rate STSo4 SI SIU Interrupt. This is one of the
2 1 0 Clock Mode (Bits/sec)' five interrupt sources to the CPU.
0 0 0 Externally clocked 0-204M'' The vector location' = 23H. SI
may be set by the SIU. It should
0 0 1 Reserved be cleared by the CPU before
0 1 0 Self clocked, timer overflow 244-62.5K returning from an interrupt
0 1 1 Reserved routine.
1 0 0 Self clocked, external 16x 0-375K STS.5 RTS Request To Send. Indicates that
the 8044 is ready to transmit or is
1 0 1 Self clocked, external 32x 0-187.5K transmitting. RTS may be read or
1 1 0 Self clocked, internal fixed 375K written by the CPU. RTS may be
1 1 1 Self clocked, internal fixed 187.5K read by the SIU, and in AUTO
mode may be written .by the SI U.
NOTES: STS.6 RBE Receive Buffer Empty. RBE can
• Based on a 12 Mhz crystal frequency be thought of as Receive Enable.
"0-1 M bps in loop configuration, RBE is set to one by the CPU
when it is ready to receive a
STS: Status/Command Register (bit- frame, or has just read the buffer,
addressable) and to zero by the SIU when a
Bit: 7 6 5 4 3 2 1 0 frame has been received.
ITBF IRBE IRTS ISI IBOV IOPB IAM IRBP I STS.7 TBF Transmit Buffer Full. Written by
the CPU to indicate that it has
filled the transmit buffer. TBF may
The Status/Command Register (Address C8H) pro- be cleared by the SIU.
vides operational control of the SIU by the 8044
13-143
8044AH/8344AH/8744H
NSNR: Send/Receive Count Register (bit- TBS: Transmit Buffer Start Address Register
addressable) (byte-addressable)
Bit: 7 6 5 4 3 2 1 0
The Transmit Buffer Start address register (Address
INS21NS11NsoisESINR21NR11NROIsERI DC H) points tQ the location in on-chip RAM for the
beginning of the I-field of the frame to be transmit-
The Send/Receive Count Register (Address D8H) ted. The CPU should access TBS only when the SIU
contains the transmit and receive sequence num- is not transmitting a frame (when TBF = 0).
bers, plus tally error indications. The SIU can both
read and write NSNR. The 8044 CPU can both read TBl: Transmit Buffer length Register
and write NSNR asynchronously. However, 2-cycle (byte = addressable)
instructions that access NSNR during both cycles
('JBC /B, REL,' and 'MOV /B,C') should not be The Transmit Buffer Length register (Address DBH)
used, since the SIU may write to. NSMR between the contains the length (in bytes) of the I-field to be
two 8044 CPU accesses. transmitted. A blank I-field (TBL = 0) is valid. The
CPU should access TBL only when the SIU is not
The individual bits of the Send/Receive Count Reg- transmitting a frame (when TBF = 0).
ister are as follows:
NOTE:
Bit# Name Description
The transmit and receivo buffers are not allowed to
NSNR.O SER Receive Sequence Error: "wrap around" in the on-chip RAM. A "buffer end"
NS (P) "1= NR (S) is automatically generatod if address 191 (BFH) is
reached.
NSNR.1 NRO Receive Sequence Counter-Bit 0
NSNR.2 NR1 Receive Sequence Counter-Bit 1
TCB: Transmit Control Byte Register
NSNR.3 NR2 Receive Sequence Counter-Bit 2 (byte-addressable)
NSNR.4 SES Send Sequence Error: The Transmit Control Byte register (Address DAH)
NR (P) ",. NS (S) and contains the byte which is to be placed in the control
NR (P) '" NS (S) + 1 field of the transmitted frame, during NON-AUTO
mode transmission. The CPU should access TCB
NSNR.5 NSO Send Sequence Counter-Bit 0 only when the SIU is not transmitting a frame (when
.-
NSNR.6 NS1 Send Sequence Counter-Bit 1 TBF = 0). The Nsand NR counters are not used in
the NON-AUTO mode.
NSNR.7 NS2 Send Sequence Counter-Bit 2
RBS: Receive Buffer Start Address Register
(byte-addressable)
Parameter Registers
The Receive Buffer Start address register (Address
There are eight parameter registers that are used in CCH) points to the location in on-chip RAM where
connection with SIU operation. All eight registers the beginning of the I-field of the frame being re-
may be read or written by the 8044 CPU. RFL and ceived is to be stored. The CPU should write RBS
RCB are normally loaded by the SIU. only when the SIU is not receiving a frame (when
RBE = 0).
The eight parameter registers are as follows:
RBl: Receive Buffer length Register
STAD: Station Address Register (byte-addressable)
(byte-addressable)
The Receive Buffer Length register (Address CBH)
The Station Address register (Address CEH) con- contains the length (in bytes) of the area in on-chip
tains the station address. To prevent acess conflict, RAM allocated for the received I-field. RBL = 0 is
the CPU should access STAD only when the SIU is valid. The CPU should write RBL only when RBE = O.
idle (RTS = 0 and RBE = 0). Normally, STAD is
accessed only during initialization.
13-144
8044AH18344AH/8744H
RFL: Receive Field Length Register The emulator operates with Intel's Inteliec™ devel-
(byte-addressable) opment system. The development system interfaces
with the user's 8044 system through an in-cable
The Receive Field Length register (Address CDH) buffer box. The cable terminates in a 8044 pin-com-
contains the length (in bytes) of the received I-field patible plug, which fits into the 8044 socket in the
that has just been loaded into on-chip RAM. RFL is user's system. With the emulator plug in place, the
loaded by the SIU. RFL = 0 is valid. RFL should be user can excercise his system in real time while col-
accessed by the CPU only when RBE = O. lecting up to 255 instruction cycles of real-time data.
In addition, he can single-step the program.
RCB: Receive Control Byte Register Static RAM is available (in the in-cable buffer box) to
(byte-addressable) emulate the 8044 internal and external program
memory and external data memory. The designer
The Received Control Byte register (Address CNI)
can display and alter the contents of the replace-
contains the control field of the frame that has just
ment memory in the buffer box, the internal data
been received. RCB is loaded by the SIU. The CPU
memory, and the internal 8044 registers, including
can only read RCB, and should only access RCB
the SFR's.
when RBE = O.
SIUST: SIU State Counter (byte-addressable)
ICE Support
The SIU State Counter (Address D9H) reflects the
The 8044 In-Circuit Emulator (ICE-44) allows the state of the internal logic which is under SIU control.
user to exercise the 8044 application system and Therefore, care must be taken not to write into this
monitor the execution of instructions in real time. register. This register provides a useful means for
debugging 8044 receiver problem.
13-145
8044AH/8344AH/8744H
ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. The specifi-
Ambient Temperature Under Bias ...... O'C to 70'C cations are subject to change without notice.
Storage Temperature ........... - 65'C to - 150'C 'WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
Voltage on EA, VPP Pin to VSS ... -0.5V to -21.5V These are stress ratings only. Operation beyond the
Voltage on Any Other Pin to VSS .... - 0.5V to -7V "Operating Conditions" is not recommended and ex-
Power Dissipation ........................... 2W tended exposure beyond the "Operating Conditions"
may affect device reliability.
D.C. CHARACTERISTICS TA = 0'Ct070'C, vcc = 5V = 10%, VSS = OV
Symbol Parameter Min Max Unit Test Conditions
VIL Input Low Voltage (Except EA Pin of 8744H) -0.5 0.8 V
VILl Input Low Voltage to EA Pin of 8744H 0 0.8 V
VIH Input High Voltage (Except XTAL2, RST) 2.0 vcc + 0.5 V
VIHl Input High Voltage to XTAL2, RST 2.5 VCC + 0.5 V XTALl = VSS
---
VOL Output Low Voltage (Ports 1,2,3)' 0.45 V IOL = 1.6mA
VOLl Output Low Voltage (Port O,ALE,PSEN)'
0.60 V IOL = 3.2mA
8744H
0.45 V IOL = 2.4 mA
8044AH/8344AH 0.45 V IOL = 3.2 mA
VOH Output High Voltage (Ports 1, 2, 3) 2.4 V IOH = -80 fLA
VOHl Output High Voltage (Port 0 in External 2.4 V IOH = -400 fLA
Bus Mode, ALE, PSEN)
ilL Logical 0 Input Current (Ports 1,2, 3) - 500 fLA Vin = 0.45V
ilL 1 Logical 0 Input Current to EA Pin
15 mA
of 8744H only
IIL2 Logical 0 Input Current (XTAL2) -- 3.6 mA Vin = 0.45V
III Input Leakage Current (Port 0)
8744H :': 100 fLA 0.45 < Vin < VCC
8044AH/8344AH ±10 fLA 0.45 < Vin < VCC
IIH Logical 1 Input Current to EA Pin of 8744H 500 fLA
IIHl Input Current to RST to Activate Reset 500 fLA Vin < (VCC - 1 .5V)
ICC Power Supply Current: All Outputs Discon-
8744H 285 mA nected: EA = VCC
8044AH/8344AH 170 mA
CIO Pin Capacitance 10 pF Test Freq. = 1 MHz(l)
'NOTES:
1. Sampled not 100% tested. TA = 25'C.
2. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports
1 and 3. The noise is due to external bus capacitance discharging into the Port a and Port 2 pin when these pins make I-to-
O transitions during bus operations. In the worst cases (capacitive loading> 100 pF), the noise pulse on the ALE line may
exceed 0.8V. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt
Trigger STROBE input.
13-146
8044AH/8344AH/8744H
A.C. CHARACTERISTICS
TA = O°C to + 70°C, VCC = 5V ± 10%, VSS = OV, Load Capacitance for Port 0, ALE, and PSEN = 100 pF.
Load Capacitance for All Other Outputs = 80 pF
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
Variable Clock
12 MHzOsc
Symbol Parameter 1/TCLCL = 3.5 MHz to 12 MHz Unit
Min Max Min Max
TLHLL ALE Pulse Width 127 2TCLCL-40 ns
------
TAVLL Address Valid to ALE Low <13 TCLCL-40 ns
-----
TLLAX1 Address Hold After ALE Low <10 TCLCL-35 ns
"- "
TLlIV ALE Low to Valid Instr in ns
8744H 183 4TCLCL-150
8044AH/8344AH 2:33 4TCLCL-l00
TLLPL ALE Low to PSEN Low 58 TCLCL-25 ns
,. ,
TPLPH PSEN Pulse Width
8744H 190 3TCLCL-60 ns
8044AH/8344AH 215 3TCLCL-35 ns
TPLIV PSEN Low to Valid Instr in
8744H 100 3TCLCL-150 ns
8044AH/8344AH 125 3TCLCL-125 ns
TPXIX Input Instr Hold After PSEN 0 0 ns
TPXIZ2 Input Instr Float After PSEN 63 TCLCL-20 ns
TPXAV2 PSEN to Address Valid 75 TCLCL-8 ns
TAVIV Address to Valid Instr in
8744H 267 5TCLCL-150 ns
8044AH/8344AH 302 5TCLCL-115 ns
TAZPL Address Float to PSEN -25 -25 ns
NOTES:
1. TLLAX for access to program memory is different from TLLAX for data memory.
2. Interfacing RUPI-44 devices with float times up to 75ns is permissible. This limited bus contention will not cause any
damage to Port a drivers.
13-147
inter 8044AH/8344AH/8744H
EXTERNAL DATA MEMORY CHARACTERISTICS
"
Variable Clock
12 MHz Osc
Symbol Parameter 1/TCLCL = 3.5 MHz to 12 MHz Unit
Min Max Min Max
TRLRH RD Pulse Width 400 6TCLCL-100 ns
TWLWH WR Pulse Width 400 6TCLCL-100 ns
TLLAX Address Hold after ALE 48 TCLCL-35 ns
TRLDV RD Low to Valid Data in 252 5TCLCL-165 ns
TRHDX Data Hold After RD 0 0 ns
TRHDZ Data Float After RD 97 2TCLCL-70 ns
TLLDV ALE Low to Valid Data In 517 8TCLCL-150 ns
TAVDV Address to Valid Data In 585 9TCLCL-165 ns
TLLWL ALE Low to RD or WR Low 200 300 3TCLCL·50 3TLCLCL+50 ·ns
TAVWL Address to RD or WR Low 203 4TCLCL-130 ns
TOVWX Data Valid to WR Transition
8744H 13 TCLCL-70 ns
8044AH/8344AH 23 TCLCL-60 ns
TOVWH Data Setup Before WR High 433 7TCLCL-150 ns
TWHOX Data Held After WR 33 TCLCL-50 ns
TRLAZ AD Low to Address Float 25 25 ns
TWHLH AD or WR High to ALE High
8744H 33 133 TCLCL·50 TCLCL+50 ns
8044AH/8344AH 43 123 TCLCL-40 TCLCL+50 ns
NOTE:
1. TLLAX for access to program memory is different from TLLAX for access data memory.
Serial Interface Characteristics
Symbol Parameter Min Max Unit
TDCY Data Clock 420 ns
TDCL Data Clock Low 180 ns
TDCH Data Clock High 100 ns
tTD Transmit Data Delay 140 ns
tOSS Data Setup Time 40 ns
tDHS Data Hold Time 40 ns
13·148
8044AH/8344AH/8744H
WAVEFORMS
Memory Access
PROGRAM MEMORY READ CYCLE
~-------------------------------TCY------------------------~-';
ALE
PSEN
INSTRIN
PORTO
ADDRESS A15-AB
PORT2
231663-8
DATA MEMORY READ CYCLE
TWHlH
~---"" 1-_---------TlLDV-- ------1
ALE
------------------~----------~ ~-----~TRlRHI------------~,_-----
TRlDV
TRHDX
PORTO DATA IN
TRlAZ
ADDRESS
PORT2 DR SFR-P2
231663-9
DATA MEMORY WRITE CYCLE
TWHlH
ALE
----------------~----------_4 14-----------TWlWH----------~r_-----
TOVWH TWHQX
PORTO DATA OUT
PORT 2 ADDRESS A1S-AB DR SFR-P2
231663-10
13-149
infef 8044AH/8344AH/8744H
SERIAL 1/0 WAVEFORMS
SYNCHRONOUS DATA TRANSMISSION
1--------TDCy----,---~
- - - - - " ' \ . f . o - - - T O C L - - - J r------~
SCLK
'-------~ t-----'TDCH---,----~ ' - - - - - - -
DATA
TTD
231663-11
SYNCHRONOUS DATA RECEPTION
-TOCY-------1
I----TDCL - -
SCLK
I----TDCH-
DATA
TOSS 1------TOHS------1
231663-12
13-150
8044AH/8344AH/8744H
AC TESTING INPUT, OUTPUT, FLOAT WAVEFORMS
2 .•
0.45
=X
INPUTIOUTPUT
20
TEST POINTS
...:0"'.8_ _ _ _ _--'0=.8
2.oX=
~F~LO~A~T~-----------------------------'
2.4
j >-------FLOAT------t
2.0
_ _ __ 2 . 0 2.4
231663-13
0.45 0.8 0.8 0.45
AC testing inputs are driv~n at 2.4V for a Logic "1" and OASV for
a Logic "0" Timing measuromonts are made at 2.0V for a Logic 231663-14
"1" and O.SV for a Logic "0".
EXTERNAL CLOCK DRIVE XTAL2
TCHCl
1------------- TCLCL - - - - - - - 1
231663-15
Symbol Parameter
.-
Freq
Min
Variable Clock
3.5 MHz to 12 MHz
-
Max
Unit
II
TCLCL Oscillator Period 83.3 285.7 ns
-
TCHCX High ~imo 20 TCLCL-TCLCX ns
TCLCX Low Timo
.- 20 TCLCL-TCHCX ns
TCLCH Rise Time 20 ns
TCHCL Fall Timo 20 ns
13-151
inter 8044AH/8344AH/8744H
CLOCK WAVEFORMS
INTERNAL
CLOCK I STATE 4
PI I P2
I STATE 5
PI I P2
I S"ATE 6
PI I P2
STATE 1
PI I P2
STATE 2
PI I P2
STATE 3
PI 1 P2
STATE 4
PI I P2
STATE 5
PI I P2
XTAL 2 ..flJ1..-flnILf
ALE
EXTERNAL PROGRAM MEMORY FETCH
PSEN
'----=-_-'1
::2 I I
THESE SIGNALS ARE NOT
ACTIVATED DURING THE
I
EXECUTION OF A MOVX INSTRUCTION
I'" !
~I ____
L
PO
P2(EXT) _ _ _ _--'!INDICATES ADDRESS TRANSIONSIL._ _ _ _ _ _ _ _ _ _- - '
READ CYCLE
RD
OOH IS EMITTED PCL OUT (IF PROGRAM
DUlliNG THIS PERIOD MEMORY IS EXTERNAL)
PO
DPL OR Ri L Y /DATAl. n~
OUT
I- 4J= FLOAT SAMPj,ED i
P2 INDICATES DPH OR P2 SFR TO PCH TRANSITIONS
WRITE CYCLE
WR L !
PCl OUT(EVEN IF PROGRAM
. - - - - - - - - -.... MEMORY IS INTERNAL)
DPl OR Ri 1 d=:,· ·L
PO OUT
t-- --DATA OUT----· .... ~
PCl OUT (IF PROGRAM
P2 -------Ir---I-N-D-IC-A-T-ES-D-PH-0-R-P-2-S-F-R-T-0-P-C-H-T-R-A-N-S-IT-IO-N-S------.1 MEMORY IS EXTERNAL)
PORT OPERATION
MOV PORT, SRC OLD DATil! NEW DATA
,-::-:~-:-:-~-=:_ _ _ _ _ _-,-_ _ _ _ _ _ _ _--,----~PO PINS SAMPLED
MOV DEST. PO ~_- f-4t
MOV DEST. PORT (Pl. P2. P3) PO PINS SAMPLED
(INCLUDES INTO, INTI. TO, TI) ~~---------,------------,F\L
Pl. P2. P3 PINS SAMPLED Pl. P2. P3
SERIAL PORT SHIFT CLOCK PINS SAMPLED
r~gDE O)---------'~XD SAMPLED ~----q:r
RXD SAMPLED
231663-16
This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the
pins, however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as tempera-
ture and pin loading. Propagation also varies from output to output and component to component Typically
though, (TA = 25°C, fully loaded) RD and WR propagation delays are approximately 50 ns. The other signals
are typically 85 ns. Propagation delays are incorporated in the AC specifications.
13-152
8044AH/8344AH/8744H
8744H EPROM CHARACTERISTICS ure 8. Detailed timing specifications are provided in
the EPROM Programming and Verification Charac-
teristics section of this data sheet.
Erasure Characteristics
Erasure of the 8744H Program Memory begins to Program Memory Security
occur when the chip is exposed to light with wave-
lengths shorter than approximately 4,000 Ang- The program memory security feature is developed
stroms. Since sunlight and fluorescent lighting have around a "security bit" in the 8744H EPROM array.
wavelengths in this range, constant exposure to Once this "hidden bit" is programmed, electrical ac-
these light sources over an extended period of time cess to the contents of the entire program memory
(about 1 week in sunlight, or 3 years in room-level array becomes impossible. Activation of this feature
fluorescent lighting) could cause unintentional era- is accomplished by programming the 8744H as de-
sure. If an application subjects the 8744H to this scribed in "Programming the EPROM" with ttie ex-
type of exposure, it is suggested that an opaque la- ception that P2.6 is held at a TTL high rather than a
bel be placed over the window. TTL low. In addition, Port 1 and P2.0-P2.3 may be in
any state. Figure 9 illustrates the security bit pro-
The recommended erasure procedure is exposure qramming configuration. Deactivating the security
to ultraviolet light (at 2537 Angstroms) to an integrat- feature, which again allows programmability of the
ed dose of at least 15 W-sec/cm 2 rating for 20 to 30 I:PROM, is accomplished by exposing the EPROM
minutes, at a distance of about 1 inch, should be to ultraviolet light. This exposure, as described in
sufficient. "Erasure Characteristics," erases the entire EPROM
array. Therefore, attempted retrieval of "protected
Erasure leaves the array in an all 1s state. code" results in its destruction.
Programming the EPROM
To be programmed, the 8744H must be running with
a 4 to 6 MHz oscillator. (The reason the oscillator
needs to be running is that the internal bus is being
Program Verification
Program Memory may be read only when the "secu-
rity featllru" has not tJuen activated. Refer to Figure
10 for Program Verification setup. To read the Pro-
II
used to transfer address and program data to appro- gram Memory, the following procedure can be used.
priate registers.) The address of an EPROM location The unit must be rlllllling with a 4 to 6 MHz oscilla-
to be programmed is applied to Port 1 and pins P2.0- tor. The address 01 it Program Memory location to
P2.3 of Port 2, while the data byte is applied to Port be read is applied to Port 1 and pins P2.0-P2.3 of
O. Pins P2.4-P2.6 and PSEN should be held low, and Port 2. Pins P2.t\-P2.6 and PSEN are held at TTL
P2.7 and RST high. (These are all TTL levels except low, while the ALE/P-ROG, RST, and EAIVPP pins
RST, which requires 2.5V for high.) EAIVPP is held are held at TTL high. (These are all TTL levels ex-
normally high, and is pulsed to +21V. While EAI cept RST, which requires 2.5V for high.) Port 0 will
VPP is at 21 V, the ALE/PROG pin, which is normally be the data output lines. P2.7 can be used as a read
being held high, is pulsed low for 50 msec. Then strobe. While P2.7 is held high, the Port 0 pins float.
EAIVPP is returned to high. This is illustrated in Fig- When P2.7 is strobed low, the contents of the ad-
dressed location will appear at Port O. External pull-
ups (e.g., 10K) are required on Port 0 during program
verification.
13-153
8044AH/8344AH/8744H
.+5V
ADDR. --7:"-":-'\1 Vee
PI
ooooH- 1744H
OFFFH
P2.0- PD PGM DATA
P2.3
P2.4
P2.5 ALE - - ALE PiiOG
P2.6
P2.7
XTAl2 EA --lAiVPP
XTAll RST Vl1-l1
VSS ;;m;
- 231663-17
Figure 8. Programming Configuration
+5V
Vee
NC PI
1744H
P2.0- PO Ne
NC P2.3
P2.4
P2.5 ALE _._ _ ALEIPROG 50 ml PULSE TO GND
P2.6
TTL HIGH P2.7
XTAL2 EA --E"A/VPP '21V PULSE
XTAL1 RST V1H1
VSS PSEN
231663-18
Figure 9. Security Bit Programming Configuration
13-154
8044AH/8344AH/8744H
+5V
ADDR. ---.-::--.-::-'\1 PI
Vee
OOOOH-
OFFFH 8744H
1-----'\ PGM DATA
P2.0- PO (USE 10K PULLUPS)
P2.3
P2.4
P2.5
P2.6
ALE --r- TTL HIGH
P2.7 EA -1
-1.- XTAL2 RST VIHI
4' 6MHl O
XTALI
VSS
231663-19
Figure 10. Program Verification Configuration
EPROM PROGRAMMING, SECURITY BIT PROGRAMMING
AND VERIFICATION CHARACTERISTICS
TA = 21°C to 2rc. Vee = 4.5V to 5.5V. Vss = ov
Symbol Parameter Min Max Units
Vpp Programming Supply Voltage 20.5 21.5 V
IPP Programming Current 30 mA
1/TCLCL Oscillator Frequency 4 6 MHz
TAVGL Address Setup to PROG 48TCLCL
TGHAX Address Hold after PROG 48TCLCL
TDVGL . Data Setup to PROG 48TCLCL
TGHDX Data Hold after PROG 48TCLCL
TEHSH ENABLE High to Vpp 48TCLCL
TSHGL Vpp Setup to PROG 10 p,sec
TGHSL Vpp Hold after PROG 10 p,sec
TGLGH PROGWidth 45 55 msec
TAVQV Address to Data Valid 48TCLCL
TELQV ENABLE to Data Valid 48TCLCL
TEHQZ Data Float after ENABLE 0 48TCLCL
13-155
inter 8044AH/8344AH/8744H
EPROM PROGRAMMING, SECURITY BIT PROGRAMMING
AND VERIFICATION WAVEFORMS
PROGRAMMING VERIFICATION
Pl.D-Pl.7
P2.D-P2.3 ADDRESS ADDRESS
--
TAVOV
PORTO DATA IN DATA OUT
---
TDVGL -
TGHDX
TAVGL --
TGHAX
\
~
ALEPROG
TSHGL TGHSL
TGUiH
21V ..SV
\
~
T TTL HIGH TTL HIGH TTL HIGH
EAVPP
/
'~J )--~--------....J)~
TEHSH
-- _ TELOV _ TEHOZ
231663-20
13-156
RUPITM Development 14
Support Tools
III
ICETM·fHOG/044 IN-CIRCUIT EMULATOR
280816-1
IN-CIRCUIT EMULATOR FOR THE RUP[TM-44 FAMILY OF
PERIPHERALS
The ICETM-5100/044 In-Circuit Emulator is a complete hardware/software debug
environment for developing embedded control applications based on the Intel RUPITM-44
family of peripherals, including the S044-based BITBUSTM board products. With high-
performance 12 MHz emulation, symbolic debugging, and flexible memory mapping, the
ICE-5100/044 emulator expedites all stages of development: hardware development,
software development, system integration, and system test; shortening your project's
time to market.
FEATURES
• Full speed to 12 MHz. • Source code display.
o 64KB of emulation mapped memory. o ASM-51 and PLlM-51 language support.
.. 254 frames of execution trace. o Pop-up help .
o Symbolic debug. o DOS shell escape.
• Serial link to an IBM PC XT, AT, 100% • On-line tutorial.
compatible. • Built-in CRT based editor.
• Four address breakpoints with in-range, • System self-test diagnostics .
out-of-range, and page breaks. o Worldwide service and support .
• On-line disassembler and single line
assembler.
November 1990
14-1 Order Number: 280818-001
FEATURES
ONE TOOL FOR ENTIRE SYMBOLIC DEBUGGING FOR
DEVELOPMENT CYCLE FAST DEVELOPMENT
The ICE-51001044 emulator speeds target Design team productivity is enhanced by the
system development by allowing hardware and use of symbolic debug references to program
software design to proceed simultaneously. line, high-level statements, and module and
You can develop software even before variable names. The terms used to develop
prototype hardware is finished. And because programs are the same used for system
the ICE-.51001044 emulator precisely matches debugging.
the component's electrical and timing
characteristics, it's a valuable tool for PATCH CODE WITHOUT
hardware development and debug. Thus, the RECOMPILING
ICE-5100/044 emulator can debug a prototype
Code-patching is easy with the ICE-51001044
or production system at any stage in its
development, ·without introd ucing extraneous emulator's single-line assembler. Machine code
can be disassembled to mnemonics for
hardware or software test tools.
significantly easier debugging and project
development. .
HIGH-SPEED, REAL-TIME
EMULATION EASY TO LEARN AND USE
The ICE-51001044 emulator provides full- The ICE-5100/044 is accompanied by a full
speed, real- time emulation up to 12 MHz. tutorial that explains all Hystem functions and
Because the emulator is fully transparent t.o provides many examples. Additional features
the target system, you have complete control such as on-line help, a built-in CRT-based
over hardware and softwan~ debug and syst Pill editor, and DOS shell CHcape make the
integration. emulator .fast and easy to use for both novice
64KB of zero wait-state emulation memorv is and experienced users. You can develop your
available to replace target system code . own test suites or save frequently-used debug
memory, allowing software debug to begin routines as debug procedures (PROCs) that can
even before prototype
. hardware is .
fmished. be invoked with a single command.
FLEXIBLE BREAKPOINTING WORLDWIDE SERVICE AND
FOR QUICK PROBLEM SUPPORT .
ISOLATION The ICE-51001044 emulator is supported by
The ICE-51001044 emulator supports three Intel's worldwide service and support
different types of break specifications: specific organization. In addition to an extended
address· breaks on up to 64,000 possible warranty, you can choose from hotline support,
addresses; range breaks; both within and on-site system engineering assistance, and a
outside a user-defined range; and page breaks, variety of hands-on training workshops.
up to 256 pages on 256-byte boundaries. 254
frames of execution trace memory provide
ample debug information, with each frame
divided into 16 bits of program execution
address and 8 bits of external event
information. A maximum of four tracepoints
allows qualified trace for a variety of debug
conditions.
14-2
inter
SPECIFICATIONS
ELECTRICAL DESIGN CONSIDERATIONS
CONSIDERATIONS Execution of user programs that contain
The emulation processor's user-pin timings interrupt routines causes incorrect data to be
and loadings are identical to the 8044 stored in the trace buffer. When an interrupt
component except as follows. occurs, the next instruction to be executed is
• Up to 25 pf of additional pin capacitance is placed into the trace buffer before it is actually
contributed by the processor module and executed. Following completion ofthe
target adaptor assemblies. interrupt routine, the instruction is executed
• Pin 31, EA, has approximately 32 pf of and again placed into the trace buffer.
additional capacitance loading due to sensing
circuitry.
• Pins 18 and 19, X'l'ALI and XTAL2,
respectively, have approximately 15 to 16 pf
of additional capacitance when configured
for crystal operation.
PROCESSOR MODULE DIMENSIONS
TOP VIEW
~,,~o,,'" "00 """~
PROCESSOR MODULE'\. \ PIN 1
I
1 + .- - - - - - - - -
CABLE BODY
39"
(99cmJ
280618-2
Figure 1. Processor Module Dimensions
Host Requirements Physical Characteristics
IBM PC-XT, AT or compatible The ICE-5100/044 emulator consists ofthe
PC-DOS 3.0 or later following components:
512KRAM
Width Height Length
One floppy drive and hard disk Unit
Inch em Inch em Inch em
Controller Pod 8.25 21.0 1.5 3.8 13.5 34.3
User Cable 39.0 99.0
Processor 3.8 9.7 1.5 3.8 4.0 10.2
Module*
Power Supply 7.6 18.1 4.0 10.2 11.0 28.0
Serial Cable 144.0 360.0
*with supplied lur,:t·t udaptor.
14-3
SPECIFICATIONS
Electrical Characteristics Environmental Characteristics
Power supply Operating temperature: + 10'C to + 40'C
100-120Vor 220-240V selectable (50'F to 104'F)
50Hz-60Hz Operating humidity: Maximum of 85%
relative humidity,
2 amps (AC max) @ 120V non-condensing
1 amp CAC max) @ 240V
ORDERING INFORMAT.RON
Order Code Description
plO44KITAD Kit contains ICE-51001044 uspr
probe assembly, power supply
and cables, serial cables, targpt.
adapter, crystal power'accessory,
emulator controller pod,
emulator software, DOS host.
communication, ASM-51 and
AEDIT text editor (requires
software license).
plO44KITD Kit contains the same
components as pI044KITA]),
excluding ASM-51 and the
AEDIT text editor (requires
software license).
pC044KITD Conversion kit for ICE-5100!152,
ICE-5100/451, or ICE-51001252
running PC-DOS 3.0 or lai('r, to
provide emulation support for
MCS-51 components (requires
software license).
D86ASM51 ASM/RL 51 package for PC-DOS
(requires software license).
D86PLM51 PLiM/RL 51 package for PC-
DOS (requires software license).
D86EDINL AEDIT text editor for PC-DOS.
14-4
MCS®~80/85 Family 15
8080A/8080A-1/8080A-2
8-BIT N-CHANNEL MICROPROCESSOR
• 2TTLI-'-s Drive Capability
• Arithmetic
Decimal, Binary, and Double Precision
• Cycle (-1:1.3 I-'-s, - 2:1.5 I-'-s) Instruction
• Ability to Provide Priority Vectored
• Set
Powerful Problem Solving Instruction Interrupts
• Available
512 Directly Addressed 1/0 Ports
• Accumulator
6 General Purpose Registers and an
• - Standardin Temperature
EXPRESS
Range
• Addressing
16-Bit Program Counter for Directly
up to 64K Bytes of Memory • Packages
Available in 40-Lead Cerdip and Plastic
• Manipulation Instructions for Rapid
16-Bit Stack Pointer and Stack (See Packaging Spec. Order #231369)
Switching of the Program Environment
The Intel® BOBOA is a completeB-bit parallel central processing unit (CPU). It is fabricated on a single LSI chip
. using Intel's n-channel silicon gate MOS process. This offers the user a high performance solution to control
and processing applications.
The BOBOA contains 6 B-bit general purpose working renisters and an accumulator. The 6 general purpose
registers may be addressed individually or in pairs providing both single and double precision operators.
Arithmetic and logical instructions set or reset 4 testable flags. A fifth flag provides decimal arithmetic opera-
tion.
The BOBOA has an external stack feature wherein any portion of memory may be used as a last in/first out
stack to store/retrieve the contents of the accumulator, flags, program counter, and all of the 6 general
purpose registers. The 16-bit stack pointer controls the addrossing of this external stack. This stack gives the
BOBOA the ability to easily handle multiple level priority intorrupts by rapidly storing and restoring processor
status. It also provides almost unlimited subroutine nostin!}.
This microprocessor has been designed to simplify systems design. Separate 16-line address and B-line
bidirectional data busses are used to facilitate easy interface to memory and lID. Signals to control the
interface to memory and I/O are provided directly by the BOBOA. Ultimate control of the address and data
busses resides with the HOLD signal. It provides the ability to suspend processor operation and force the
II
address and data busses into a high impedance state. This permits OR-tying these busses with other control-
ling devices for (DMA) direct memory access or multi-processor operation.
NOTE:
The BOBOA is functionally and electrically compatible with the Intel BOBO.
November 1986
15-1 Order Number: 231453-001
8080Al8080A-1/8080A-2
18 Bill
INTERNAL DATA BUS
II'
'"
til REGISTER
ARRAY
1111
ST ACt( I"OINTER
1161
PROCiRAM COUNTER
1-
TIMING
AND
CONTROL
POWER +12V
SUPPLIES _ -+-SV
_-SV ~~~~~~-r~~~~~~~~~~~~~~
_GND
ACK
231453-1
Figure 1. Block Diagram
A,o 40 A"
GND 39 A,.
D, 38 All
Ds 37
Ds 36
D, 35
D3 34
D, 33
D,O 32 As
Do 0 10 BOBOA 31 As
-5V 11 30
RESET 12 29 A3
HOLD 13 28 +12V
INT 14 27 A,
'2 15
16
26 A,
25 As
.,
17 24 WAIT
WR 18 23 READY
SYNC 19 22
+5V 20 21 HLDA
231453-2
Figure 2. Pin Configuration
15-2
8080Al8080A-1I8080A-2
Table 1 Pin Description
Symbol Type Name and Function
A15- AO 0 ADDRESS BUS: The address bus provides the address to memory (up to 64K 8-bit
words) or denotes the 1/0 device number for up to 256 input and 256 output devices. Ao
is the least significant address bit.
Dy-Do 1/0 DATA BUS: The data bus provides bi-directional communication between the CPU,
memory, and 1/0 devices for instructions and data transfers. Also, during the first clock
cycle of each machine cycle, the 8080A outputs a status word on the data bus that
describes the current machine cycle. Do is the least significant bit.
SYNC 0 SYNCHRONIZING SIGNAL: The SYNC pin provides a signal to indicate the beginning
of each machine cycle.
.-
DBIN 0 DATA BUS IN: The DBIN signal indicates to external circuits that the data bus is in the
input mode. This signal should be u~;od to enable the gating of data onto the 8080A data
bus from memory or 1/0.
READY I READY: The READY signal indicatQ~; to the 8080A that valid memory or input data is
available on the 8080A data bus. Tilis signal is used to synchronize the CPU with slower
memory or 1/0 devices. If after sendill~J an address out the 8080A does not receive a
READY input, the 8080A will enter a WAIT state for as long as the READY line is low.
READY can also be used to single stop the CPU.
WAIT 0 WAIT: The WAIT signal acknowledCjo.s!hat the CPU is in a WAIT state.
WR 0 WRITE: The WR signal is used for momory WRITE or 1/0 output control. The data on
the data bus is stable while the WR si~Jnal is active low (WR = 0).
HOLD I HOLD: The HOLD signal requests tho crJu to enter the HOLD state .. The HOLD state
allows an external device to gain control of the 8080A address and data bus as soon as
the 8080A has completed its use of 1I10!;0 busses for the current machine cycle. It is
recognized under the following conditions:
• the CPU is in the HALT state.
• the CPU is in the T2 or TW state and tilO READY signal is active. As a result of
entering the HOLD state the CPU ADDRESS BUS (A15-AO) and DATA BUS (07-00)
will be in their high impedance state. Tho CPU acknowledges its state with the HOLD
ACKNOWLEDGE (HLDA) pin.
HLDA 0 HOLD ACKNOWLEDGE: The HLDA signal appears in response to the HOLD signal and
indicates that 1110 data and address bus will go to the high impedance state. The HLDA
signal begins at:
• T3 for READ memory or input.
• The Clock Period following T3 for WRITE memory or OUTPUT operation.
In either case, the HLDA signal appears after the rising edge of </>2.
INTE 0 INTERRUPT ENABLE: Indicates the content of the internal interrupt enable flip/flop.
This fliplflop may be set or reset by the Enable and Disable Interrupt instructions and
inhibits interrupts from being accepted by the CPU when it is reset. It is automatically
reset (disabling further interrupts) at time T1 of the instruction fetch cycle (M1) when an
interrupt is accepted and is also reset by the RESET Signal.
INT I INTERRUPT REQUEST: The CPU recognizes an interrupt request on this line at the end
of the current instruction or while halted. If the CPU is in the HOLD state or if the
Interrupt Enable fliplflop is reset it will not honor the request.
RESET' I RESET: While the RESET signal is activated, the content of the program counter is
cleared. After RESET, the program will start at location 0 in memory. The INTE and
HLDA fliplflops are also reset. Note that the flags, accumulator, stack pointer, and
registers are not cleared. •
Vss GROUND: Reference.
Voo POWER: +12 ±5% V.
Vee POWER: + 5 ± 5% V.
VBB POWER: -5 ±5% V.
</>" </>2 CLOCK PHASES: 2 externally supplied clock phases. (non TIL compatible)
NOTE:
1. The RESET signal must be. active for a minimum of 3 clocll cycles.
15-3
8080Al8080A-1/8080A-2
ABSOLUTE MAXIMUM RATiNGS* NOTICE: This is a production data sheet. The specifi-
cations are subject to change without notice.
Temperature Under Bias ............ ooe to + 70 0 e
'WARNING: Stressing the device beyond the "Absolute
Storage Temperature .......... -65°e to + 150 e 0
Maximum Ratings". may calise permanent dama{1e.
All Input or Output Voltages These are stress ratings only. Operation beyond the
with Respect to Vee ........... -0.3V to + 20V "Operating Conditions" is nol recommended and ex-
tended exposure beyond the "Operating Conditions"
Vcc, VDD and Vss may affect device reliability.
with Respect to Vee ........... - 0.3V to + 20V
Power Dissipation .......................... 1.5W
D.C. CHARACTERISTICS
== +12V
TA = 0°Ct070°C, VDD ±5%, Vcc = +5V ±5%, Vee = -5V ±5%, Vss . OV; unless otherwise
noted
Symbol Parameter Min Typ Max Unit Test Condition
VILC Clock Input Low Voltage Vss - I VSS + O.B V
VIHC Clock Input High Voltage 9.0 VDD + 1 V
VIL Input Low Voltage Vss - 1 VSS + O.B V
VIH Input High Voltage 3.3 Vcc + 1 V
..-
VOL Output Low Voltage 0.45 V
} IOL = 1.9 mA on All Outputs,
VOH Output High Voltage 3.7 V IOH = -150 iJ-A.
:~ 1
.100 (AV) Avg. Power Supply Current (VDD) 40 70
Operation
ICC (AV) Avg. Power Supply Current (Vccl 60 BO
Tcy = O.4B iJ-s
Iss (AV) Avg. Power Supply Current (Vee) 0.01 1 mA
IlL Input Leakage ±10 iJ-A Vss s VIN s Vce
ICL Clock Leakage ±10 iJ-A Vss s VCLoeK s VDD
IDL Data Bus Leakage in Input Mode -100 iJ- A Vss s VIN :s; Vss + O.BV
-2.0 mA Vss + O.BV :s; VIN :s; Vec
IFL Address and Data Bus Leakage +10 VADDR/DATA = Vee
/LA
During HOLD -100 VAOOR/DATA = Vss + 0.45V
CAPACITANCE 1.5,----..,.----,-----,
TA = 25°C, Vce = VDD = Vss = OV, Vee = -5V
Symbol Parameter Typ Max Unit Test Condition
C</> Clock 17 25 pF Ic = 1 MHz
Capacitance
CIN Input 6 10 pF Unmeasured Pins
Capacitance O.50~--.::!;25:----.:L50-----!<75
COUT Output 10 20 pF Returned to Vss AMBIENT TEMPERATURE ("C)
Capacitance 231453-3
Typical Supply Current vs
Temperature, Normalized
~I Supply/~TA = -O.45%rC
15-4
SOSOAISOSOA-1/S0SOA-2
A.C. CHARACTERISTICS (SOSOA) TA = O°C to 70°C, VOO = + 12V ± 5%, VCC = + 5V ± 5%,
VSS = - 5V ± 5%, VSS = OV; unless otherwise noted
-'1 -1 -2 -2
Symbol Parameter Unit Test Condition
Min Max Min Max Min Max
tCy(3) Clock Period 0.48 2.0 0.32 2.0 0.38 2.0 /ks
t r, tj Clock Rise and Fall Time 0 50 0 25 0 50 ns
t<l>1 I<1>1 Pulse Width 60 50 60 ns
tp2 L<j>2 Pulse Width 220 145 175 ns
t01 Delay <P1 to <P2 0 0 0 ns
-
t02 Delay <P1 to <P2 70 60 70 ns
t03 Delay <P1 to <P2 Leading Edges 80 60 70 ns
tOA Address Output Delay From <P2 200 150 175 ns
CL = 100 pF
too Data Output Delay From '1'2 200 180 200 ns
toc Signal Output Delay From 'P1 or <P2
120 110 120 ns CL = 50 pF
(SYNC, WR, WAIT, HLDA)
- -
tOF DBIN Delay From 'P2 25 140 25 130 25 140 ns
tOI(1) Delay for Input Bus to Entor Input Mode tOF tOF tOF ns
tOS1 Data Setup Time Durin}] ,/>1 and DBIN 30 10 20 ns
tOS2 Data Setup Time to '1'2 During DBIN 150 120 130 ns
tOH(1) Data Hold Time From '/>:> and DBIN (1 ) (1 ) (1 ) ns
tiE INTE Output Delay From .1'2 200 200 200 ns CL = 50 pF
.-
tRS READY Setup Time DUrlI1g <P2 120 90 ~)O os
tHS HOLD Setup Time Durinq <1>2 140 120 120 ns
tiS INT Setup Time Durin~1 .1.;, 120 100 100 ns
tH Hold Time From <1>2 (RFADY, INT, HOLD) 0 0 0 ns
tFO Delay to Float During Hold
120 120 120 ns
(Address and Data Bus)
tAW Address Stable Prior to WR (5) (5) (5) ns
tow Output Data Stable Prior to WR (6) (6) (6) ns
two Output Data Stable From WR (7) (7) (7) ns
tWA Address Stable From WR (7) (7) (7) ns
tHF HLDA to Float Delay (8) (8) (8) ns
tWF WR to Float Delay (9) (9) (9) ns
tAH Address Hold Time After DBIN During HLDA -20 -20 -20 ns
A.C. TESTING LOAD CIRCUIT
DEVICE
UNDER
TEST
' 1 C L •• ,00PF
-= 231453-4
CL· 100 pF
CL Includes Jig Capacitance
15-5
=e
~ ~
tf\ tf\-------4
l>
<
m
~
::0
l
:s:::
~ C/J
- -:1--t-=1~:~;fTrr-] ,
- - - + -.......' j < - - - - -i
-- X_____l'Olf
J__ - _= o~~~
~
toHI-
~I--I---
'ATA OUT
-I
1 - t 051
-'OS2-
1""- ~towt__
w
o
-I'OC f :ox
CD
o
»
.......
CD
!-!::~- -----'::: ~ __ i!
o
CD
CJ1
OJ
WR
READY
I'HJ1,-.
'OC
I
_----'_ r- :t
II I:i.· I
o
» I
......
.......
CD
o
CD
o
WAIT _____________________________________________________________ ~~~~ __ ~
» I
I\)
HOLD
HLDA
'" -~tiS ............
'H -
INTE
231453-5
NOTE:
Timing measurements are made at the following reference voltages: CLOCK "1" B.OV, "0" 1.0V; INPUTS "1" = 3.3V, "0" = O.BV; OUTPUTS "1" = 2.0V,
"0" = O.BV
8080Al8080A-1/8080A-2
WAVEFORMS (Continued) Typical 6. Output Delay vs 6. Capacitance
,l\ ,F\ +20
7
-
c
'" >- +10
V
<t:
F- oJ
·2 I- "----1 L w
...
0
0
I~
::0 ""-.SPEC
'"...
-
--- 1---
tm
I-- ::J
..,
0 -10
A,soAo I- --
- R tWA
y ~- I--~
~,
-20
-100
V -50 +50 +100
-- -- _ ... - -~
~ CAPACITANCE (pI)
- -- y
°7·°0
SYNC
~
- ~ltWD " (CACTUAl - CSPEC )
231453-7
..I .. tAH
3. The following are relevant when interfacing the
OOBOA to devices having VIH = 3.3V:
OOIN I \ a) Maximum output rise time from O.BV to 3.3V =
100 ns @ CL = SPEC.
~'"'-
b) Output delay when measured to 3.0V = SPEC
WAf- 1-1 --
READY
- t Dc +60 ns @ CL = SPEC.
c) If CL = SPEC, add 0.6 ns/pF if CL > CSPEC,
subtract 0.3 ns/pF (from modified delay) if CL <
!-'H'- CSPEC·
WAIT 4. tAW = 2 tCY -t03 - tr 'i)2 - 140 ns (-1:110
ns, - 2:130 ns).
I- 5. tow = tCY - t03 - t r<l)2 - 170 ns (-1:150 ns,
HOLD
HLDA
- 11-
tnr
- 2:170 ns).
6. If not HLDA, two = tWA = t03 + tr'i)2 + 10 ns.
If HLDA, two = tWA = tWF'
7. tHF = t03 + tr<j>2 -50 ns.
II
I-
INT B. tWF =. t03 + trp2 - 10 ns.
9. Data In must be stable for this period during
DBIN T3· Both tOSl and tOS2 must be satisfied.
INTE
~.
~t:=t- 10. Ready signal must be stable for this period dur-
ing T 20r T W. (Must be externally synchronized.)
11. Hold signal must be stable for this period during
231453-6 T2 or TW when entering hold mode, and during. T3,
T 4, T 5 and T WH when in hold mode. (External syn-
chronization is not required.)
NOTES: 12. Interrupt signal must be stable during this peri-
(Parenthesis gives -1, - 2 specifications, respec-
od of the last clock cycle of any instruction in order
tively.) to be recognized on the following instruction. (Ex-
1. Data input should be enabled with DBIN status.
ternal synchronization is not required.)
No bus conflict can then occur and data hold time 13. This timing diagram shows timing relationships
is assured. only; it does not represent any specific machine cy-
tOH = 50 ns or tOF, whichever is less. cle.
2. tCY = tD3 + t r<j>2 + t.p2 + tfp2 + t02 + tr<j>l :2:
4BO ns (-1 :320 ns, - 2:3BO ns).
15-7
inter SOSOA/SOSOA-1/S0S0A-2
INSTRUCTION SET 8080A. The ability to increment and decrement
memory, the six general registers and the accumula-
The accumulator group instructions include arithme- tor is provided as well as extended increment and
tic and logical operators with direct, indirect, and im- decrement instructions to operate on the register
mediate addressing modes. pairs and stack pointer. Further capability is provid-
ed by the ability to rotate the accumulator left or right
Move, load, and store instruction groups provide the through or around the carry bit.
ability to move either 8 or 16 bits of data between
memory, the six working registers and the accumula- Input and output may be accomplished using memo-
tor using direct, indirect, and immediate addressing ry addresses as 1/0 ports or the directly addressed
modes. I/O provided for in the 8080A instruction set.
The ability to branch to different portions of the pro- The following special instruction group completes
gram is provided with jump, jump conditional, and the 8080A instruction set: the NOP instruction,
computed jumps. Also the ability to call to and return HALT to stop processor exocution and the DAA in-
from subroutines is provided both conditionally and structions provide decimal arithmetic capability. STC
unconditionally. The RESTART (or single byte call allows the carry flag to bo diroctly set, and the CMC
instruction) is useful for interrupt vector operation. instruction allows it to be complemented. CMA com-
plements the contents of the accumulator and
Double precision operators such as stack manipula- XCHG exchanges the contonts of two 16-bit register
tion and double add instructions extend both tho pairs directly.
arithmetic and interrupt handling capability of tho
Data and Instruc~ion Formats
Data in the 8080A is stored in the form of 8-bit binary integers. All data transfors to they system data bus will
be in the same format.
107 06 05 D~ 03 02 01 Dol
DATA WORD
The program instructions may be one, two, or three bytes in length. Multiple by to instructions must be stored in
successive words in program memory. The instruction formats then depend on tl18 particular operation execut-
ed.
One Byte Instructions TYPICI\L INSTRUCTIONS
107 06 05 04 03 02 01 Dol OP CODE Register to register, memory reference,
arithmotic or logical, rotate, return, push,
pop, enable or disable Interrupt
instructions
Two Byte Instructions
10 7 06 05 04 03 02 01 Dol OPCODE
Immediate mode or 1/0 instructions
107 06 D5 D 4 03 02 01 Dol OPERAND
Three Byte Instructions
OPCODE Jump, call or direct load and store
107 D6 D5 D4 03 02 01 Dol
instructions
ID7 D6 05 D4 D3 02 01 Dol LOW ADDRESS OR OPERAND 1
ID7 D6 05 D4 D3 D2 01 Dol HIGH ADDRESS OR OPERAND 2
For the 8080A a logic" 1" is defined as a high level and a logic "0" is defined as a low level.
15-8
8080A/8080A-1/8080A-2
Table 2 Instruction Set Summary
Clock Clock
Instruction Code (1) Operations Instruction Code (1) Operations
Mnemonic' Cycles Mnemonic' Cycles
Il? 0 6 D5 D4 03 D2 D1 0 Description D7DsD5D4D3D2D1Dc Description
(2) (2)
MOVE, LOAD, AND STORE JM 1 1 1 1 1 0 1 o Jump on minus 10
MOVrl,r2 o 1 D DDS S S Move register to 5 JPE 1 1 1 0 1 0 1 o Jump on parity 10
register even
MOVM,r 0 1 1 1 0 S S S Move register to 7 JPO 1 1 1 0 0 0 1 o Jump on parity odd 10
memory PCHL 1 1 1 0 1 0 0 1 H & L to program 5
MOVr,M 0 1 D D D 1 1 o Move memory to 7 counter
register CALL
MVlr 0 0 D D D 1 1 o Move immediate 7
register CALL 1 1 0 0 1 1 0 1 Call unconditional 17
MVIM 0 0 1 1 0 1 1 o Move immediate 10 CC 1 1 0 1 1 1 0 o Call on carry 11/17
memory CNC 1 1 0 1 0 1 0 o Call on no carry 11/17
LXIB 0 0 0 0 0 0 0 1 Load immediate 10 CZ 1 1 0 0 1 1 0 o Call on zero 11/17
rogister Pair B & C CNZ 1 1 0 0 0 1 0 o Call on no zero 11/17
LXID 0 0 0 1 0 0 0 1 Load immediate 10 (;1' 1 1 1 1 0 1 0 o Call on positive 11/17
rogister Pair D & E eM 1 1 1 1 1 1 0 o Call on minus 11/17
LXIH 0 0 1 0 0 0 0 1 Load immediate 10 CI'E 1 1 1 0 1 1 0 o Call on parity even 11/17
register Pair H & L
CI'O 1 1 1 0 0 1 0 o Call on parity odd 11/17
STAXB 0 0 0 0 0 0 1 o Store A indirect 7
STAXD 0 0 0 1 0 0 1 o Store A indirect 7 RETURN
LDAXB 0 0 0 0 1 0 1 o Load A indirect 7 IlET 1 1 0 0 1 0
0 1 Return 10
LDAXD 0 0 0 1 1 0 1 o Load A indirect 7 nc 1 1 0 1 0 o Return on carry
1 0 5/11
STA 0 0 1 1 0 0 1 o Store A direct 13 nNC 1 1 0 1 0 o Return on no carry
0 0 5/11
LDA 0 0 1 1 1 0 1 o Load A direct 13 RZ 1 1 0 0 0 o Return on zero
1 0 5/11
SHLD 0 0 1 0 0 0 1 o Store H & L direct 16 nNZ 1 1 0 0 0 o Return on no zero
0 0 5/11
LHLD 0 0 1 0 1 0 1 o Load H & L direct 16 RP 1 1 ()
1 1 0 o Return on positive
0 5111
XCHG 1 1 1 0 1 0 1 1 Exchange D & E, 4 RM 1 1 11 () 0 o Return on minus
1 5111
H & L Registers RPE 1 1 () 0 0 o Return on parity
1 0 5/11
STACKOPS even
RPO 1 1 1 0 () () 0 o Return on parity 5111
PUSHB 1 1 0 0 0 1 0 1 Push register Pair 11 odd
B & Con stack .. -
PUSHD 1 1 0 1 0 1 0 1 Push register Pair 11 RESTART
D & Eon stack RST 1 1 A A A 1 1 1 Restart 11
PUSHH 1 1 1 0 0 1 0 1 Push register Pair 11
H & Lon stack INCREMENT AND DECREMENT
PUSH 1 1 1 1 0 1 0 1 Push A and Flags 11 INRr 0 0 D D D 1 0 o Increment register 5
PSW on stack
DCRr 0 0 D D D 1 0 1 Decrement register 5
POPB 1 1 0 0 0 0 0 1 Pop register Pair B 10
INRM 0 0 1 1 0 1 0 o Increment memory 10
&Coflstack
DCRM 0 0 1 1 0 1 0 1 Decrement memo!) 10
POPD 1 1 0 1 0 0 0 1 Pop register Pair D 10
& E ofl stack INXB 0 0 0 0 0 0 1 1 Increment B & C 5
registers
POPH 1 1 1 0 0 0 0 1 Pop register Pair H 10
&Loflstack INXD 0 0 0 1 0 0 1 1 Increment D & E 5
registers
POPPSW 1 1 1 1 0 0 0 1 Pop A and Flags 10
oflstack INXH 0 0 1 0 0 0 1 1 Increment H & L 5
registers
XTHL 1 1 1 0 0 0 1 1 Exchange top of 18
stack, H & L DCXB 0 0 0 0 1 0 1 1 Decrement B & C 5
SPHL 1 1 1 1 1 0 0 1 H & Lto stack 5 DCXD 0 0 0 1 1 0 1 1 Decrement D & E 5
pointer DCXH 0 0 1 0 1· 0 1 1 Decrement H & L 5
LXISP 0 0 1 1 0 0 0 1 Load immediate 10 ADD
stack pointer
INXSP 0 0 1 1 0 0 1 1 Increment stack 5 ADDr 1 0 0 0 0 S S S Add register to A 4
pointer ADCr 1 0 0 0 1 S S S Add register to A 4
DCXSP 0 0 1 1 1 0 1 1 Decrement stack 5 with carry
pointer ADDM 1 0 0 0 0 1 1 o Add memory to A 7
ADCM 1 0 0 0 1 1 1 o Add memory to A 7
JUMP
with carry
JMP 1 1 0 0 0 0 1 1 Jump 10 ADI 1 1 0 0 0 1 1 o Add immediate to A 7
unconditional ACI 1 1 0 0 1 1 1 o Add immediate to A 7
JC 1 1 0 1 1 0 1 o Jump on carry 10 with carry
JNC 1 1 0 1 0 0 1 o Jump on no carry 10 DADB 0 0 0 0 1 0 0 1 AddB&CtoH&L 10
JZ 1 1 0 0 1 0 1 o Jump on zero 10 DADD 0 0 0 1 1 0 0 1 AddD&EtoH&L 10
JNZ 1 1 0.0 0 0 1 o Jump on no zero 10 DADH 0 0 1 0 1 0 0 1 AddH&LtoH&L 10
JP 1 1 1 1 0 0 1 o Jump on positive 10 DADSP 0 0 1 1 1 0 0 1 Add stack pointer 10
toH&L
15-9
inter 8080A/8080A-1/8080A-2
Table 2. Instruction Set Summary (Continued)
Clock Clock
Instruction Code (1) Operations Instruction Code (1) Operations
Mnemonic' Cycles Mnemonic' Cycles
07 Os Os 04 03 02 01 Do Description D7DsDsD4D3D2D1Do Description
(2) (2)
SUBTRACT ROTATE
SUB r 1 0 0 1 0 S S S Subtract register 4 RLC 0 0 0 0 0 1 1 1 Rotate A left 4
from A RRC 0 0 0 0 1 1 1 1 Rotate A right 4
SBB r 1 0 0 1 1 S S S Subtract register 4 RAL 0 0 0 1 0 1 1 1 Rotate A left 4
from A with borrow through carry
SUBM 1 0 0 1 0 1 1 o Subtract memory 7 RAR 0 0 0 1 1 1 1 1 Rotate A right 4
from A through carry
SBBM 1 0 0 1 1 1 1 o Subtract memory 7
from A with borrow SPECIALS
SUI 1 1 0 1 0 1 1 o Subtract 7 CMA 0 0 1 0 1 1 1 1 Complement A 4
immediate from A STC 0 0 1 1 0 1 1 1 Set carry 4
SBI 1 1 0 1 1 1 1 o Subtract 7 CMC 0 0 1 1 1 1 1 1 Complement carry 4
immediate from A
DAA 0 0 1 0 0 1 1 1 Decimal adjust A 4
with borrow
--- INPUT/OUTPUT
LOGICAL
IN 1 1 0 1 1 0 1 1 Input 10
ANAr 1 0 1 0 0 S S S And register ~
with A OUT 1 1 0 1 0 0 1 1 Output 10
XRA r 1 0 1 0 1 S S S Exclusive or ~ CONTROL
ragister with A
ORAr 1 0 1 1 0 S S S Or register with A ~
EI 1 1 1 1 1 0 1 1 Enable Interrupts 4
CMPr 1 0 1 1 1 S S S Compare register ~
01 1 t t 1 0 0 1 1 Disable Interrupt 4
with A NOP 0 0 0 0 0 0 0 o No-operation 4
ANAM 1 0 1 0 0 1 1 o Alld memory / HLT 0 1 1 .. 1 0
~
1 1 o Halt 7
with A
XRAM 1 0 1 0 1 1 1 o [xclusive Or i
momory with A
ORA M 1 0 1 1 0 1 1 o Or memory with A ./
CMPM 1 0 1 1 1 1 1 o Compare memory /
with A
ANI 1 1 1 0 0 1 1 o And immediate !
with A
XRI 1 1 1 0 1 1 1 o Exclusive Or 7
immediate with A
ORI 1 1 1 1 0 1 1 o Or immediate 7
with A
CPI 1 1 1 1 1 1 1 o Compare 7
immediate with A
NOTES:
1. DDD or SSS: B = 000, C = DOl, 0 = 010, E = 011, H = 100, L == 101, Memory = 110, A = 111.
2. Two possible cycle times (6/12) indicate instruction cycles dependent on condition flags .
• All mnemonics copyright @ Intel Corporation 1977
15-10
soa5f~G:!J f~Oa5A~~i-2/®Oa5A~c <~
S-BIT HMOS MICROPROCESSORS
[j Single + SV Power Supply with 10% IT] On-Chip System Controller; Advanced
Voltage Margins Cycle Status Information Available for
IfI!I 3 MHz, S MHz and 6 MHz Selections Large System Control
Available [iii four Vectored Interrupt Inputs (One Is
[J 20% lower Power Consumption than Non-Maskable) Plus an 80S0A·
SOSSA Tor 3 MHz and S MHz Compatible Interrupt
[] 1.3 I-1s Instruction Cycle (S08SAH)j O.S Gl Serial In/Serial Out Pori
I-1s (SOSSAH-2)j 0.67 I-1s (SOS5AH-1) III Decimal, Binary and Double Precision
[] 100% Software Compatible with SOSOA Arithmetic
EJ On-Chip Clock Generator (with External
[j Direct Addressing Capability to 64K
Crystal, LC or RC Network) Bytes of Memory
II Available in 40-Lead Cerdip and Plastic
Packages
(SOD Packaging Spuc., Order # 231369)
The Intel 8085AH is a complete 8-bit parallel Central Procossing Unit (CPU) implemented in N-channel,
depletion load, silicon gate technology (HMOS). Its instruction set is 100% software compatible with the
8080A microprocessor, and it is designed to improve the present 8080A's performance by higher system
speed. Its high level of system integration allows a minimum system of three IC's [8085AH (CPU), 8156H
(RAMIIO) and 8755A (EPROM/IO)l while maintaining total system expandability. The S085AH-2 and
8085AH-1 are faster versions of the 8085AH,
The S085AH incorporates all of the features that the 8224 (clock generator) and 8228 (system controller)
provided for the S080A, thereby offering a higher level of system integration,
The S085AH uses a multiplexed data bus. The address is split between the 8-bit address bus and the 8-bit
data bus. The on-chip address latches of S155H/S156H/8755A memory products allow a direct interface with
the 8085AH.
x, Vee
X2 HOLD
RESET OUT HlDA
eLK IOUTI
SID RESET IN
TRAP READY
AST 7.5 101M
RST 6.5 S,
B'.' C "'
Ri5
fllG flEG. INTR WR
J-'
o ,II i <II
IItG. IIIEG INTA ALE
H ,., l '.'
REG. REG "RRAY ADO So
SlACII.POunEA II" AD, A'5
PIIOGRAM COUNTER "'
AD2 A,.
AD3 A'3
INCAEM~::~~~~~:um~1I
AD. A'2
AD5 An
AD6 A10
AD7 A9
"" VSS AS
231718-2
"1,-Aa AD,.An.
ADDRIE$SBUS WO"UIIDA1AIU$
Figure 2. 8085AH Pin
231718-1
Configuration
Figure 1. 8085AH CPU Functional Block Diagram
September 1987
15-11 Ordor Number: 231718-001
8085AH/8085AH-2/8085AH-1
Table 1. Pin Description
Symbol Type Name and Function
As-A15 0 ADDRESS BUS: The most significant 8 bits of memory address or the 8 bits of the
1/0 address, 3-stated during Hold and Halt modes and during RESET.
ADo_7 110 MULTIPLEXED ADDRESSIDATA BUS: Lower 8 bits of the memory address (or
1/0 address) appear on the bus during the first clock cycle (T state) of a machine
cycle. It then becomes the data bus during the second and third clock cycles.
ALE 0 ADDRESS LATCH ENABLE: It occurs during the first clock state of it machine
cycle and enables the address to get latched into the On'Cllip latch of peripherals.
The falling edge of ALE is set to guarantee setup and hold times for the address
information. The falling edge of ALE can also be used to strobe the status
information. ALE is never 3-stated.
--
So, S1 and 101M 0 MACHINE CYCLE STATUS:
101M S1 So Status
0 0 1 Memory write
0 1 0 Memory read
1 0 1 110 write
1 1 0 1/0 read
0 1 1 Opcode fetch
1 1 1 Interrupt Acknowledge
• 0 0 Halt
·· X X Hold
X X Reset
X
· 3-state (high impedance)
unspecified
S1 can be used as an advanced R/W status. 101M, SO and S1 become valid at the
beginning of a machine cycle and remain stable tllroughout the cycle. The falling
edge of ALE may be us(~d to latch the state of these lines.
RD 0 READ CONTROL: A low level on RD indicates the selected memory or 110 device
is to be read and that the Data Bus is available for tho data transfer, 3-stated during
Hold and Halt modes and during RESET. . _.
WR 0 WROTE CONTROL: A low level on WR indicatos the data on the Data Bus is to be
written into the selected memory or 1/0 location. Data is set up at the trailing edge
of WR. 3-stated during Hold and Halt modes and during RESET.
READY I READY: If READY is high during a read or write cycle, it indicates that the memory
or peripheral is ready to send or receive data. If READY is low, the CPU will wait an
integral number of clock cycles for READY to go high before completing the read
or write cycle. READY must conform to specified setup and hold times.
HOLD I HOLD: Indicates that another master is requesting the use of the address and data
buses. The CPU, upon receiving the hold request, will relinquish the use of the bus
as soon as the completion of the current bus transfer. Internal processing can
continue. The processor can regain the bus only after the HOLD is removed. When
the HOLD is acknowledged, the Address, Data RD, WR, and 101M lines are
3-stated;
HLDA 0 HOLD ACKNOWLEDGE: Indicates that the CPU has received the HOLD request
and that it will relinquish the.bus in the next clock cycle. HILDA goes low alter the
Hold request is removed. The CPU takes the bus one half clock cycle alter HLDA
goes low.
INTR I INTERRUPT REQUEST: Is used as a general purpose interrupt. It is sampled only
during the next to the last clock cycle of an instruction and during Hold and Halt
states. If it is active, the Program Counter (PC) will be inhibited from incrementing
and an INTA will be issued. During this cycle a RESTART or CALL instruction can
be inserted to jump to the interrupt service routine. The INTR is enabled and
. disabled by software. It is disabled by Reset and immediately alter an interrupt is
accepted.
15-12
8085AH/8085AH-2/S085AH·1
Table 1. Pin Description (Continued)
Symbol Type Name and Function
INTA 0 INTERRUPT ACKNOWLEDGE: Is used instead of (and has the same timing as)
RD during the Instruction cycle after an INTR is accepted. It can be used to
activate an 8259A Interrupt chip or some other interrupt port.
RST5.5 I RESTART INTERRUPTS: These three inputs have the same timing as INTR
RST6.5 except they cause an internal RESTART to be automatically inserted.
RST7.5 The priority of these interrupt is ordered as shown in Table 2. These interrupts have
a higher priority than INTR. In addition, they may be individually masked out using
the SIM instruction.
TRAP I TRAP: Trap interrupt is a non-maskable REST ART interrupt. It is recognized at the
same time as INTR or RST 5.5-7.5. It is unaffected by any mask or Interrupt
Enable. It has the highest priority of any interrupt. (See Table 2.)
RESET IN I RESET IN: Sets the Program Counter to zero and resets the Interrupt Enable and
HlDA flip-flops. The data and address busos and the control lines are 3-stated
during RESET and because of the asynchronous nature of RESET, the processor's
internal registers and flags may be altured by RESET with unpredictable results.
- RESETTN is.a Schmitt-triggered input, allowing connection to an R-C network for
power· on RESET delay (see Figuro 3). Upon power-up, RESET IN must remain low
for al loast 10 ms after minimum Vee has been reached. For proper reset
operation after the power-up duration, RESET IN Sllould be kept Iowa minimum of
three clock periods. The CPU is hold in the reset condition as long as RESET IN is
appliod.
RESET OUT 0 RESET OUT: Reset Out indicates CPU is being reset. Can be used as a systom
reset. The signal is synchronized 10 the processor clock and lasts an integral
number of clock periods.
X1, X2 I Xl and X2: Are connected to a crystal, lC, or RC network to drive the internal
clock gonerator. X1 can also be an external clock input from a logic gate. The input
frequency is divided by 2 to give the processor's internal operating frequency.
ClK 0 CLOCK: Clock output for use as a system clock. The period of ClK is twice the X1,
II
X2 input period.
SID I SERIAL INPUT DATA LINE: The data on this line is loaded into accumulator bit 7
whenever a RIM instruction is executed.
SOD 0 SERIAL OUTPUT DATA LINE: The output SOD is set or reset as specified by the
SIM instruction.
VCC POWER: + 5 volt supply.
Vss GROUND: Reference.
Table 2. Interrupt Priority, Restart Address and Sensitivity
Address Branched to(1)
Name Priority Type Trigger
When Interrupt Occurs
TRAP 1 24H Rising Edge AND High level until Sampled
RST7.5 2 3CH Rising Edge (latched)
RST6.5 3 34H High level until Sampled
RST5.5 4 2CH High level until Sampled
INTR 5 (Note 2) High level until Sampled
NOTES:
1. The processor pushes the PC on the stack before branching to tho indicatod address.
2. The address branched to depends on the instruction provided to tho CPU when the interrupt is acknowledged.
15-13
intJ 8085AH/8085AH-2/8085AH-1
(SID) and Serial Output Data (SOD) lines for simple
RESET IN serial interface.
In addition t~ these features, the 8085AH has three
:
c,
Il
R,
Vee 0 maskable, vector interrupt pins, one nonmaskable
TRAP interrupt, and a bus vectored interrupt, INTR.
.1 f INTERRUPT AND SERIAL 110
Typical Power-On Aeset AC Values'
231718-3
The 8085AH has 5 interrupt inputs: INTR," RST 5.5,
Al = 75 Kll RST 6.5, RST 7.5, and TRAP. INTR is identical in
C1 = I,.F
'Values May Have to Vary Due to Applied Power Supply Aamp function to the 8080A INT. Each of the three RE-
UpTIme. START inputs, 5.5, 6.5, and 7.5, has a programma-
ble mask. TRAP is also a RESTART interrupt but it is
Figure 3. Power-On Reset Circuit
nonmaskable.
The three maskable interrupt cause the internal exe-
FUNCTIONAL DESCRIPTION cution of RESTART (saving the program counter in
The 8085AH is a complete 8-bit parallel central the stack and branching to the RESTART address) if
processor. It is designed with N-channel, depletion the interrupts are enabled and if the interrupt mask
load, silicon gate technology (HMOS), and requires is not set. The nonmaskable TRAP causes the inter-
a single + 5V supply. Its basic clock speed is 3 MHz nal execution of a RESTART vector independent of
(8085AH), 5 MHz (8085AH-2), or 6 MHz (8085-AH-1), the state of the interrupt enable or masks. (See Ta-
ble 2.)
thus improving on the present 8080A's performance
with higher system speed. Also it is designed to lit
There are two different types of inputs in the restart
into a minimum system of three IC's: The CPU
interrupts. RST 5.5 and RST 6.5 are high level-sensi-
a
(8085AH), RAM/IO (8156H), and an EPROMIIO
tive like INTR (and INT on the 8080) and are recog-
chip (8755A). .
nized with the same timing as INTR. RST 7.5 is rising
edge-sensitive.
The 8085AH has twelve addressable 8-bit registers.
Four of them can function only as two 16-bit register For RST 7.5, only a pulse is required to set an inter-
pairs. Six others can be used interchangeably as nal flip-flop which gonerates the internal interrupt re-
8-bit registers or as 16-bit register pairs. The quest (a normally high level signal with a low going
8085AH register set is as follows: pulse is recommended for highest system noise im-
Mnemonic Register Contents munity). The RST 7.5 request flip-flop remains set
ACC or A Accumulator 8 Bits until the request is serviced, Then it is reset auto-
PC Program Counter 16-Bit Address matically. This flip-flop may also be reset by using
BC, DE, HL General-Purpose 8-Bits x 6 or the SIM instruction or by issuing a RESET IN to the
Registers; data 16 Bits x 3 8085AH. The RST 7.5 internal flip-flop will be set by
pointer (HL) a pulse on the RST 7.5 pin everi when the RST 7.5
SP Stack Pointer 16-Bit Address interrupt is masked out.
Flags or F Flag Register 5 Flags (8-Bit Space) The status ,of the three RST interrupt· masks can
only be affected by the SIM instruction and'
The 8085AH uses a multiplexed Data Bus. The ad- RESET IN. (See SIM, Chapter 5 of the 8080/8085
dress is .split between the higher 8-bit Address Bus User's ManuaL)
and the lower 8-bit Address/Data Bus. During the
first T state (clock cycle) of a machine cycle the low The interrupts are arranged in a fixed priority that
order address is sent out on the Address/Data bus. determines which interrupt is to be recognized if
These lower 8 bits may be latched externally by the more than one is pending as follows: TRAP-high-
Address Latch Enable signal (ALE). During the rest est priority, RST 7_5, RST 6.5, RST 5.5, INTR-Iow-
of the machine cycle the data bus is used for memo- est priority. This priority scheme does not take into
ry or I/O data. account the priority of a routine that was started by a
higher ,priority interrupt. RST 5.5 can interrupt an
The 8085AH provides RD, WR, So, 51, and 10lM RST 7.5 routine if the interrupts are re-enabled be-
signals for bus control. An Interrupt Acknowledge fore the end of the RST 7_5 routine.
signal (INTA) is also provided. HOLD and all Inter-
rupts are synchronized with the processor's internal The TRAP interrupt is useful for catastrophic events
clock. The 8085AH also provides Serial Input Data such as power failure or bus error_ The TRAP input is
recognized just as any other interrupt but has the
15-14
8085AH/8085AH-2/8085AH-1
highest priority. It is not affected by any flag or mask. hence, the 8085AH is operated with a 6 MHz crystal
The TRAP input is both edge and level sensitive. (for 3 MHz clock), the 8085AH-2 operated with a 10
The TRAP input must go high and remain high until it MHz crystal (for 5 MHz clock), and the 8085AH-1
is acknowledged. It will not be recognized again until can be operated with a 12 MHz crystal (for 6 MHz
it goes low, then high again. This avoids any false clock). If a crystal is used, it must have the following
triggering due to noise or logic glitches. Figure 4 il- characteristics:
lustrates the TRAP interrupt request circuitry within
the 80B5AH. Note that the servicing of any interrupt Parallel resonance at twice the clock frequency de-
(TRAP, RST 7.5, RST 6.5, RST 5.5, INTR) disables sired
all future interrupts (except TRAPs) until an EI in- CL (load capacitance) os: 30 pF
struction is executed. Cs (Shunt capacitance) os: 7 pF
Rs (equivalent shunt resistance) os: 75i!
Drive level: 10 mW
Frequency tolerance: ± 0.005% (suggested)
INSIDElHE
ExTERNAL BOaSAH
TRAP
INTERRUPT
Note the use of the 20 pF capacitor between X2 and
REOUEST TRAP ground. This capacitor is required with crystal fre-
quencies below 4 MHz to assure oscillator startup at
the correct frequency. A parallel-resonant LC citcuit
RESET u\i SCHM ITT may be used as the frequency-determining network
TRIGGER
for tile 80B5AI-!, providing that its frequency toler-
RESET
an co of approximately ± 10% is acceptable. The
t5V D eLK components aro chosen from the formula:
o
FIF
To minimize V,III;ltlons in frequency, it is recom-
INTERNAL TRAP F.f
TRAP mended that you t:!ioose a value for Cox! tilat is at
ACKNOWLEDGE least twico that "I (:int, or 30 pF. The uso of an LC
231718-4 circuit is not ruc(lIll1nended for frequencies higher
than approximatuly !i MHz.
Figure 4. TRAP and RESET In Circuit
An RC circuit may be used as the frequency-deter-
The TRAP interrupt is special in that it disables inter- mining notworl( fm the B085AH if maintaining a pre-
rupts, but preserves the previous interrupt enable cise cloci( fruqu()llcy is of no importance. Variations
status. Performing the first RIM instruction following in the on-chip tililing generation can cause a wide
a TRAP interrupt allows you to determine whether variation ill frequullcy when using the RC mode. Its
interrupts were enabled or disabled prior to the advantago is its low component cost. The driving
TRAP. All subsequent RIM instructions provide cur- frequency <)enerated by the circuit shown is approxi-
rent interrupt enable status. Performing a RIM in- mately 3 MHz. It is not recommended that frequen-
struction following INTR, or RST 5.5-7.5 will provide cies greatly higher or lower than this be attempted.
current Interrupt Enable status, revealing that inter-
rupts are disabled. See the description of the RIM Figure 5 shows the recommended clock driver cir-
instruction in the B080/B085 Family User's Manual. cuits. Nato in d and e that pullup resistors are re-
quired to assure that the high level voltage of the
The serial I/O system is also controlled by the RIM input is at least 4V and maximum low level voltage
and SIM instruction. SID is read by RIM, and SIM of O.8V.
sets the SOD data.
For driving frequencies up to and including 6 MHz
you may supply the driving signal to XI and leave X2
DRIVING THE X1 AND X2 INPUTS open-circuited (Figure 5d). If the driving frequency is
from 6 MHz to 12 MHz, stability of the clock genera-
You may drive the clock inputs of the 8085AH,
tor will be improved by driving both XI and X2 with a
8085AH-2, or 8085AH-1 with a crystal, an LC tuned
push-pull source (Figure 5e). To prevent self-oscilla-
circuit, an RC network, or an external clock source.
tion of the BOB5AH, be sure that X2 is not coupled
The crystal frequency must be at least 1 MHz, and
back to XI through the driving circuit.
must be twice the desired internal clock frequency;
15-15
inter 8085AH/8085AH-2/8085AH-1
+5V
Xl
---, I
8085AH
4700
LOW nME > 60 ns
TO
/
I
I CINT lKO
..l... = 15pF
-r-
I
"
I
" I
---~
'20 pF capacitors required for ' -_ _ _ _ _ __
crystal frequency,; 4 MHz only. 231718-5
a. Quartz Crystal Clock Driver
'X2 left floating "
8OB5AH
231718-8
.---.----I.,r-'-
r " - -...,
d. 1-6 MHz Input Frequency
I
ceXT
1 CI~;PF Clock Driver Circuit
T +5V
, I
'--4-----I[::r~'- - _-.l
LOW TIME> 40 n.
47011 / __ _
231718-6 1<>--+----'-----1 x,
b. LC Tuned Circuit Clock Driver
8085AH
r- 470fl
'1 "
'---4----j.,
- 6K
t""' r
2
L-
"
231718-7
e. 1-12 MHz Input Frequency
Extern<11 Clock Driver Circuit
231718-9
c. RC Circuit Clock Driver
Figure 5. Clock Driver Circuits
GENERATING AN 8085AH WAIT As in the 8080, tilo READY line is used to extend the
STATE read and write pulse lengths so that the 8085AH can
be used with slow memory. HOLD causes the CPU
If your system requirements are such that slow to relinquish the bus when it is through with it by
memories or peripheral devices are being used, the floating the Address and Data Buses.
circuit shown in Figure 6 may be used to insert one
WAIT state in each 8085AH machine cycle.
SYSTEM INTERFACE
The D flip-flops should be chosen so that
• ClK is rising edge-triggered The 8085AH family includes memory components,
• CLEAR is low-level active. which are directly compatible to the 8085AH CPU.
For example, a system consisting of the three chips,
8085AH, 8156H and 8755A will have the following
r---------~ features:
CLEAR
ALEO ____ eLK
B065AH • 2K Bytes EPROM
CLK OUTPUT· - - Cl K TO
"0"
II065AH • 256 Bytes RAM
"0" READY
F/F /-'Q'- _ _ _ _ _ _ , D F/F ~~PVT • 1 Timer/Counter
+5V~D
• 4 8-bit I/O Ports
231718-10 • 1 6-bit I/O Port
'ALE and CLK (OUT) should be buffered if CLK input of latch
exceeds 8085AH IOL or IOH. • 4 Interrupt levels
Figure 6. Generation of a • Serial In/Serial Out Ports
Wait State for 8085AH CPU
15-16
infef 8085AH/8085AH-2/8085AH-1
This minimum system, using the standard I/O tech- shows the system configuration of Memory Mapped
nique is as shown in Figure 7. liD using 8085AH.
In addition to the standard liD, the memory mapped The 8085AH CPU can also interface with the stan-
I/O offers an efficient liD addressing technique. dard memory that does not have the multiplexed ad-
With this technique, an area of memory address dress/data bus. It will require a simple 8-bit latch as
space is assigned for liD address, thereby, using shown in Figure 9.
the memory address for liD manipulation. Figure 8
rD~ Tli
-- 'HAP
x, x, RESET IN
HOLD I-
--
1I~;T1.!) HLDA
t-
It :; Hi, ~I r.oD t-
--
II~;J
INTH
!', ~I
808SAH
RESET
SID
S, " _
-
INTA
ADDAI OUT "II - -
AOOR DATA ALE RD WR 101M ROV eLK
Vr,s Vee
IBI IB?
II
•H-- CI POR:~
WII PORT ~
IBI
liD 8156H B
ALL PORT~
C 161
-" DATA!
ADDR
y
" 101M
H(SET
IN
TIMER
OUT
-
I--
lOW
AD
ALE
t+-
~ J-..
CE
A8-10 .
PORT
A
W
r0- Y 8755A
... DATAl
ADaR
['-f y
~
101M PORT
RESET B
p-- * ROY Vee
~ CLK lOR
-'
.t tJ t
Vss Vee VOD PROG
Vee
Vee
Vee
7
231718-11
'NOTE:
Optional Connection
Figure 7. 8085AH Minimum System (Standard 1/0 Technique)
15-17
AS-1S r-- )
cl
<&0-7 )
.('t
:=f~
ALE
----
"T1
.
cC'
c
CD
B085AH RD
WR
IDIM
Vee
Vee
!» r---- - c---
CD
0
elK
r---- I I m
CD RESET OUl I 0
U1 r- m
READY i
s: r---- UI
5' I I
Vee
»
3c I.
I I· ....m
::I:
3 i TIMER
{~~D
I 0
~'v7~~~0~~
101
RESET WR AD ALE ~7 10,':i CE F.1 ALE AD i5W elK RS1RDY m
.. +
VI IN eE
UI
01
.....
'<
III »
::I:
co CD
3 N
....
~ m
0
CD
T~~~R_ m
.
3
0
'< 8156H
UI
»
.
::I:
s:
DI
[RAM, to - COUNTERfTIMERJ 8755A [EPROM + 1/0] ....
'tI
'tI
CD
Il.
::::
.9
231718~12
'NOTE:
Optional Connection
8085AH/8085AH-2/8085AH-1
-- TRAP
RST7
X, X2 RESET IN
HOLD
----
--
HlDA
--
RST6 SOD
8085AH
--- RST5
INTR
INTA
ADDR
ADDRI
DATA ALE Rfj WR
R[SET
101M
OUT 50 -
ROY ClK
SID
5,
Icl~
(8) (81
>-- - 101M (CSI
~ r-- WR
LATCH· f--< R5
j,.
vi'-
I\.
DATA
y
" STANDIIIII)
MEMOflV
,-
-\ ADDR (C~;I
(161
,----
-I
~ ClK
RESEI
-~ 101M ICSI 110 POR TS.
~
OLS
WII
liD
V'
II
" DATA
'" y
-~
STANDARD
ADDR
110
I y
UDI II -'\N'I. Vee
Vee
,AA
",y Vee
231718-13
Figure 9. 8085 System (Using Standard Memories)
15-19
inter SOS5AH/SOS5AH-21S0S5AH-1
the three control signals (RD, WR, and INTA). (8ee
BASIC SYSTEM TIMING Table 3.) The status lines can be used as advanced
The 8085AH has a multiplexed Data Bus. ALE is controls (for device selection, for example), since
used as a strobe to sample the lower 8-bits of ad- they become active at the T 1 state, at the outset of
dress on the Data Bus. Figure 10 shows an instruc- each machine cycle. Control lines RD and WR be-
tion fetch, memory read and 1/0 write cycle (as come active later, at the time when the transfer of
would occur during processing of the OUT instruc- data is to take place, so are used as command lines.
tion). Note that during the 1/0 write and read cycle
that the 1/0 port address is copied on both the up- A machine cycle normally consists of three T states,
per and lower half of the address. with the exception of OPCODE FETCH, which nor-
mally has either four or six T states (unless WAIT or
There are seven possible types of machine cycles. HOLD states are forced by the receipt of READY or
Which of these seven takes place is defined by the HOLD inputs). Any T state must be one of ten possi- .
status of the three status lines (101M, 81, 80) and ble states, shown in Table 4.
Table 3 8085AH Machine Cycle Chart
Status Control
Machine Cycle
101M SI SO RD WR INTA
OPCODE FETCH (OF) 0 1 1 0 1 1
--
MEMORY READ (MR) 0 1 0 0 1 1
MEMORY WRITE (MW) 0 0 1 1 0 1
-
1/0 READ (lOR) 1 1 0 0 1 1
1/0 WRITE (lOW) 1 a 1 1 a 1
ACKNOWLEDGE
OF INTR (INA) 1 1 1 1 1 a
BU81DLE (BI): DAD a 1 0 1 1 1
ACK.OF
R8T,TRAP 1 1 1 1 1 1
HALT T8 0 a T8 T8 1
Table 4 8085AH Machine State Chart
Machine Status & Buses Control
State SI,SO 101M As-A15 ADo-AD7 RD,WR INTA ALE
T1 X X X X 1 1 1*
T2 X X X X X X 0
TWAIT X X X X X X 0
T3 X X X X X X 0
T4 1 at X T8 1 1 0
T5 1 ot X T8 1 .1 0
T6 1 O·r X T8 1 1 0
TRESET X T8 T8 T8 T8 1 0
THALT 0 T8 T8 T8 T8 1 0
THOLD X T8 T8 T8 T8 1 a
o LogiC " 0 " TS High Impedance
1 ~ Logic "1" X ~ Unspocified
'ALE_not generated during 2nd and 3rdmachino cycles of DAD instruction.
tlO/M ~ 1 during T4- Te of INA machino cyclo.
15-20
inter 8085AH/8085AH-2/8085AH-1
PC H (HIGH ORDER ADDRESS)
ADO_1
{X;)-----
(LOW ORDER IJATA FROM
ADDRESS) MEMORY
(INSTRUCTION)
ALE
WR
101M
STATUS S,So (FETCH) 10 (IIEAD) 01 WRITE 11
231718-14
Figure 10. 8085AH Basic System Timing
15-21
8085AH/8085AH-2/8085AH-1
ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. The specifi-
Ambient Temperature under Bias ...... O'C to 70'C cations are subject to change without notice.
Storage Temperature .......... -65'C to + 150'C , WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
Voltage on Any Pin These are stress ratings only. Operation beyond the
with Respect to Ground .......... - 0.5V to + 7V "Operating Conditions" is not recommended and ex-
Power Dissipation .......................... 1.5W tended exposure beyond the "Operating Conditions"
may affect device reliability.
D.C. CHARACTERISTICS
8085AH, 8085AH-2: TA = O'C to 70'C, Vcc = 5Vt 10%, VSS = OV; unless otherwise specified-
8085AH-1: TA = O'C to 70'C, Vcc = 5V ±5%, Vss=
_. OV; unless otherwise specified'
Symbol Parameter Min Max Units Test Conditions
.-
VIL Input low Voltage -0.5 +0.8 V
VIH Input High Voltage 2.0 VCC +0.5 V
VOL Output low Voltage 0.45 V IOL = 2 mA
VOH Output High Voltage 2.4 V IOH = - 400 p.A
-
Icc Power Supply Current 135 rnA 8085AH, 8085AH-2
200 mA 0005AH-1
IlL Input leakage ±10 I'.A 0,,; VIN ,,; Vcc
ILO Output leakage ±10 I~I\
-_ .. 0.45V ,,; VOUT ,,; Vce
VILR Input low level, RESET -0.5 +0.8 V
VIHR Input High level, RESET 2.4 Vcc + 0.5 V
VHY Hysteresis, RESET 0.15 V
.-
A.C. CHARACTERISTICS
8085AH, 8085AH-2: TA = O'C to 70'C, Vcc = 5V t 10%, Vss = OV'
8085AH-1: TA = O'C to 70'C, Vcc = 5V ±5%, Vss = OV
8085AH (2) 8085AH-2 (2) 8085AH-1 (2)
Symbol Parameter Units
Min Max Min Max Min Max
tCYC ClK Cycle Period 320 2000 200 2000 167 2000 ns
tl ClK low Time (Standard ClK loading) 80 40 20 ns
t2 ClK High Time (Standard ClK loading) 120 70 50 ns
t r, tf ClK Rise and Fall Time 30 30 30 ns
tXKR Xl Rising to ClK Rising 20 120 20 100 20 100 ns
tXKF Xl Rising to ClK Falling 20 150 20 110 20 110 ns
tAC AB-15 Valid to leading Edge of Control (1) 270 115 70 ns
tACL AO-7 Valid to leading Edge of Control 240 115 60 ns
tAD AO-15 Valid to Valid Data In 575 350 225 ns
tAFR Address Float after leading Edge of 0 0 0 ns
READ (INTA)
tAL AB-15 Valid before Trailing Edge of ALE (1) 115 50 25 ns
'NOTE:
For Extended Temporature EXPRESS use MB085AH Eloctricals Parameters.
15-22
8085AH/8085AH-2/8085AH-1
A.C. CHARACTERISTICS (Continued)
8085AH (2) 8085AH-2 (2) 8085AH-1(2)
Symbol Parameter Units
Min Max Min Max Min Max
tAll AO-7 Valid before Trailing Edge of ALE 90 50 25 ns
tARY READY Valid from Address Valid 220 100 40 ns
tCA Address (A8-15) Valid after Control 120 60 30 ns
tcc Width of Control low (RD, WR, INTA) 400 230 150 ns
Edge of ALE
tCl Trailing Edge of Control to leading Edge 50 25 0 ns
of ALE
tDW Data Valid to Trialing Edge of WRITE 420 230 140 ns
tHABE HlDA to Bus Enable 210 150 150 ns
tHABF Bus Float after HlDA 210 150 150 ns
tHACK HlDA Valid to Trailing Edge of ClK 110 40 0 ns
tHDH HOLD Hold Time 0 0 0 ns
tHDS HOLD Setup Time to Trailing Edge of ClK 170 120 120 ns
--
tlNH INTR Hold Time 0 0 0 ns
--
tiNS INTR, RST, and TRAP Setup Time to 160 150 150 ns
Falling Edge of ClK
tLA Address Hold Time after ALE 100 50 20 ns
tLC Trailing Edge of ALE to leading Edge 130 60 25 ns
of Control
tLCK ALE low During ClK High 100 50 15 ns
-
tLDR ALE to Valid Data during Read 460 ;'70 175 ns
tLDW ALE to Valid Data during
.
Write 200 140 110 ns
tLl ALE Width 140 80 50·. ns
tlRY ALE to READY Stable 110 30 10 ns
tRAE Trailing Edge of READ to Re-Enabling 150 90 50 ns
of Address
tRD READ (or INTA) to Valid Data 300 150 75 ns
tRV Control Trailing Edge to leading Edge 400 220 160 ns
of Next Control
tRDH Data Hold Time after READ INTA 0 0 0 ns
tRYH READY Hold Time 0 0 5 ns
tRYS READY Setup Time to leading Edge 110 100 100 ns
ofClK
tWD Data Valid after Trailing Edge of WRITE 100 60 30 ns
tWDL lEADING Edge of WRITE to Data Valid 40 20 30 ns
NOTES:
1. Ae-A15 address Specs apply 101M, SO, and S1 except Ae-A15 are undefined during :r4- T6 of OF cycle whereas 101M,
SO, and S1 are stable.
2. Test Conditions: tCyc= 320 ns (8085AH)/200 ns (808;;AH-2);/167 os (8085AH-1); CL = 150 pF.
*
3. For all output timing where C 150 pF use tho following correction factors:
25 pF ,; CL < 150 pF: -0.10 ns/pF
150 pF < CL ,; 300 pF: + 0.30 ns/pF
4. Output timings are measured with purely capacitive load.
5. To calculate timing specifications at other valuos of tCYC use Table 5.
15-23
inter SOS5AH/SOS5AH-2/S0S5AH-1
A.C. TESTING INPUT, OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT
INPUT/OUTPUT
x=
DEVICE
UNDER
'.'=X
TEST
l C ' " 150pF
0.45
2.0
0.8
> TEST POINTS ~
2.0
0.8
-=-
231718-16
231718-15 CL ~ 100 pF
A.C. Testing: Inputs are driven at 2.4V for a Logic "1" and 0.45V CL Includes Jig Capacitance
for a Logic "0". TIming measurements aro made at 2.0V for 0
Logic "I" and 0.8V for a Logic "0".
Table 5. Bus Timing Specification as a Tcyc Dependent
Symbol 8085AH 8085AH-2 808SAH-1
tAL (1/2)T - 45 (1 /2)T- 50 (1/2)T - 58 Minimum
tLA (1/2)T - 60 (1/2)T - 50 (1/2)T - 63 Minimum
tLL (1/2)T - 20 (1/2)T - 20 (1/2)T - 33 Minimum
tLCK (1/2)T - 60 (1/2)T - 50 (1/2)T - 68 Minimum
tLC (1/2)T - 30 (1/2)T - 40 (1/2)T - 58 Minimum
tAD (5/2 + N)T - 225 (5/2 -I N)T - 150 (5/2 -I N)T - 192 Maximum
tRO (3/2 + N)T - 180 (3/2 + N)T - 150 (3/2 I N)T - 175 Maximum
IRAE (1/2)T - 10 (1/2)T - 10 (1/2)T - 33 Minimum
tCA (1/2)T - 40 (1/2)T - 40 (1/2)T - 53 Minimum
tow (3/2 + N)T - 60 (3/2 + N)T - 70 (3/2 I- N)T - 110 Minimum
two (1/2)T - 60 (1/2)T 40 (1/2)T - 53 Minimum
tcc (3/2 + N)T - 80 (3/2 -I- N)T - 70 (3/2 1- N)T - 100 Minimum
tCl (1/2)T - 110 (1/2)T - 75 (1/2)T - 83 Minimum
tARY (3/2)T - 260 (3/2)T - 200 (3/2)T - 210 Maximum
tHACK (1/2)T - 50 (1/2)T - 60 (1/2)T - 83 Minimum
tHABF (1/2)T + 50 (1/2)T + 50 (1/2)T + 67 Maximum
tHABE (1/2)T + 50 (1/2)T + 50 (1/2)T + 67 Maximum
tAC (2/2)T - 50 (2/2)T - 85 (2/2)T - 97 Minimum
t1 (1/2)T - 80 (1/2)T - 60 (1/2)T - 63 Minimum
t2 (1/2)T - 40 (1/2)T - 30 (1/2)T - 33 Minimum
tRV (3/2)T - 80 (3/2)T - 80 (3/2)T - 90 Minimum
tLOR (4/2 + N)T - 180 (4/2)T - 130 (4/2)T - 159 Maximum
NOTE:
N is equal to the total WAIT states. T = tCYC.
15-24
inter 8085AH/8085AH-2/8085AH-1
WAVEFORMS
CLOCK
Xl INPUT
elK
OUTPUT
j-+-------- I, ____
-------,------ teye - - - - - - --------..t
--------.- tXKF-
231718-17
READ
T, I I, T,
eLK \'------'Ir--}'---~l \'--------'/ . \'-----
~tlCK_ t CA - __
5
1 ADDRESS
.
~-- ---- 'fll) . 'HOII
<I·
tRAE
, ) ADDRESS
<1!!! }/$) DATA IN
.1- Ir--
1'--
r ~tlL_ . t lA - - _
ALE
t AFR ··_ -- 'LOR -_. __ .
--. I· 'Cl--y I
...:....I Al - .
~--- '"" ~ I I
RD/INTA
. _---ICC
--------1' I
•
.- tLC--- •
I----tAc-
231718-18
WRITE
T, 1 T, T,
eLK \ , - - - - - - - , / r- tLCK~}'---/ \,------,/ \'----
)! ADDRESS J{
~tLDW- t'cA-1
, ) ADDRESS } DATA OUT
X
1- f--tLl_I...-tLA-~ 'ow -'wD~1
-. I-- tWDL
rJ
'J
ALE
~tjU_
ICC ---
~tLdt AC - - -
___ t cl -
231718-19
15-25
infef 8085AH/8085AH-2/8085AH-1
WAVEFORMS (Continued)
HOLD
elK \
T,
\
TJ T HOLD
1
T HOLD
1 , T,
HOLD
t "\ :~
t HDS " Ltlml tt HACK ....
HlDA t t HABF -
'\
,
'.
BUS (ADDRESS. CONTROLS)
-" :>---ll ' 'ABE,
231718-20
READ OPERATION WITH WAIT CYCLE (TYPICAL)-SAME READY TIMING APPLIES TO WRITE
I T, T, TWAIT I:. T,
\ / \
CLK
AO-A1!)
)
--- tlCK
ADDRESS
J K
_tCA'_
I
-. - . - _IAO- ----- .. tRDH ..
·f'RAE-
-,...
ADo·AD, ) ADDRESS
WL ///IJ) DATA IN
~
1
I--t-tLL - I---'LA-
ALE
I. ' tAFR_
- tLOn .. ~ -'CL-1
.•
~-=-
'AL ~
'RO -~
I ··_--'CC - ,I
Ro/iNTA
1
I------ -'LRY
_llC
tAC_ il
~~~~-I 'RYH'1111111111.
tRYS tRYH
i· 'ARV .
READY
I
231718-21
NOTE:
1. Ready must remain stable during setup and hold times.
15-26
a085Ahl/8085AH 2/8085AN-1
n
WA VEIFORiiIlS (Continued)
INTERRUPT AND HOLD
I T5 I T, T,
A . - V - - - - - -.......---"1I-__________-i
a _1s
A°0-7
--''''''-_--J
II-----~ BUSFLOATlNG* -.-------.;
w,--------------t-----l~----------------~
HOLD
HlDA
---------jl
231718-22
'NOTE:
101M is also floating during this time.
15-27
SOS5AH/SOS5AH-2/S0S5AH-1
Table 6. Instruction Set Summary
M . Instruction Code Operations M . Instruction Code Operations
nemomc 07 06 05 04 03 02 01 Do Description nemomc 07 06 05 04 03 02 01 Do Description
MOVE, LOAD AND STORE STACK OPS (Contiriued)
MOVr1 r2 0 1 D D D S S S Move register POPPSW 1 1 1 1 0 0 0 1 Pop A and Flags
to register off stack
MOVM.r 0 1 1 1 0 S S S Move register XTHL 1 1 1 0 0 0 1 1 Exchange top of
to memory stack, H & L
MOVr.M 0 1 D D D 1 1 0 Move memory SPHL 1 1 1 1 1 0 0 1 H & L to stack
to register pointer
MVlr 0 0 D D D 1 1 0 Move immediate LXISP 0 0 1 1 0 0 0 1 Load immediate
register stack pointer
MVIM 0 0 1 1 0 1 1 0 Move immediate INXSP 0 0 1 1 0 0 1 1 Increment stack
memory pointer
LXIB 0 0 0 0 0 0 0 1 Load immediate DCXSP 0 0 1 1 1 0 1 1 Decrement stack
register Pair B & C pointer
LXID 0 0 0 1 0 0 0 1 Load immediate JUMP
register Pair D & E JMP 1 1 0 0 0 0 1 1 Jump unconditional
LXIH 0 0 1 0 0 0 0 1 Load immediate JC 1 1 0 1 1 0 1 0 Jump on carry
register Pair H & 1_
JNC 1 1 0 1 0 0 1 0 Jump on no carry
STAX B 0 0 0 0 0 0 1 0 Store A indirect
JZ 1 1 0 0 1 0 1 0 Jump on zero
STAX D 0 0 0 1 0 0 1 (J Store A indirect
JNZ 1 1 0 0 0 0 1 0 Jump on no zero
LDAX B 0 0 1 0 1 0 1 0 I_oad A indirect
1---- JP 1 1 1 1 0 0 1 0 Jump on positive
LDAX D 0 0 0 1 1 0 1 0 Load A indirect
f--- JM 1 1 1 1 1 0 1 0 Jump on minus
STA 0 0 1 1 0 0 1 0 Store A direct
JPE 1 1 1 [) 1 0 1 0 Jump on parity even
LDA 0 0 1 1 1 0 1 0 Load A direct
JPO 1 1 1 () 0 0 1 0 Jump on parity odd
SHLD 0 0 1 0 0 0 1 0 Store H & L direct
PCHL 1 1 1 0 1 0 0 1 H & L to program
LHLD 0 0 1 0 1 0 1 0 Load H & L direct counter
XCHG 1 1 1 0 1 0 1 1 Exchange D & E. CALL
H & L Registers -.
CALL 1 1 0 0 1 1 0 1 Call unconditional
STACKOPS
CC 1 1 0 1 1 1 0 0 Call on carry
PUSHB 1 1 0 0 0 1 0 1 Push register Pair
B & Can stack CNC 1 1 0 1 0 1 0 0 Call on no carry
PUSH 0 1 1 0 1 0 1 0 1 Push register Pair CZ 1 1 0 0 1 1 0 0 Call on zero
0& E on stack CNZ 1 1 0 0 0 1 0 0 Call on no zero
PUSH H 1 1 1 0 0 1 0 1 Push register Pair CP 1 1 1 1 0 1 0 0 Call on positive
H & L on stack CM 1 1 1 1 1 1 0 0 Call on minus
PUSH 1 1 1 1 0 1 0 1 Push A and Flags CPE 1 ·1 1 0 1 1 0 0 Cali on parity even
PSW on stack
CPO 1 1 1 0 0 1 0 0 Call on parity odd
POPB 1 1 0 0 0 0 0 1 Pop register Pair
B & C off stack RETURN
POPD 1 1 0 1 0 0 0 1 Pop register Pair RET 1 1 0 0 1 0 0 1 Return
o & E off stack RC 1 1 0 1 1 0 0 0 Return on carry
POPH 1 1 1 0 0 0 0 1 Pop register Pair RNC 1 1 0 1 0 0 0 0 Return on no carry
H & L off stack
RZ 1 1 0 0 1 0 0 0 Return on zero
15-28
inter
.------.----.... --_.._...._..
8085AH/8085AH-2/8085AH~1.
__..__.. _.. _._--- ._-_. __ . __ __ _ - - -
._.. ..
Table 6. Instruction Set Summary (Continued)
-------------,----------,
Mnemonic Instruction COd~'~ Operatl~ns Mnemonic Instruction Code Operations
07 Os 05 04 D~.p.s~ Do Description ~--_LD~7~D~6~D~5~D4D3D2D1Do Description
RETURN (Continued) ADD (Continued)
-
RNZ 1 1 0 0 0 0 0 0 Return on no zero I DAD D I0 !) 0 i 1 0 0 1 Add D & E to H & L
----!---.---------f-'-':c:..:::..::c.c:..c..:..---.::c..::.....-r
RP 1 1 1 1 0 0 0 0 Return on positive DAO H 0 0 1 0 , 0 0 1 Add H & Lto H & L
RM 1 1 1 1 , 0 0 0 Return on minus' DAC SP 0 0 1 1 0 0
1 Add stack pointer
RPE 1 1 1 0 1 0 0 0 Return on toH&L
f-----'-----.-----'--'-......::c....::..-------j
parity even SUBTRACT
- - . - - , . . - . - - - - - - _..- r--------------1
RPO 1 1 1 0 0 0 0 0 Return on SUB r I O 0 i 0 S S S Subtract register
parity odd from A
~---~--. .-----
RESTART SBBr 1 0 0 1 1 S S S Subtract register
RST 1 1 A A A 1 1
.. -1 -
IRestart
-------- ---,--" 1---. .--.----.
SUBM i 0 C , ,,o 0
from A with borrow
Subtract memory
INPUT/OUTPUT
IN 1 1 0 ,, 0 1 I Input --..-1---- .......-----+'-=-'------.,
from A
~~~..o~~1 -_.0 _SlJ.I3_~'..
-,~.-.--.~-.
0 1 i Output 0. u 1 1 1 i u Subtract memory
from A with borrow
INCREMENT AND DECREMENT SLJI , 1 0 1 , 0 Subtract immediate
-
0 C D 0 ~
,
C 0 Increment register
.S.'I.J.I~:;·
INRI' 0
--~-
DCR.-
1--'
0 0 D D D 1 0 D~;::rement register
.u....'.' .._'__ '_'_.0 ;::r:ct immediate
from A with borruw
INRM 0 0 1 1 0 1 0 0 Increment memory - - - .... - . .
.'
LOGICAL
DCRM
INXB
0
0
0
0 0
1 1 0
0 0 0
1 0
1 ,
1 Decrement~
Increment B & C
IINI~·-;-'--r-!'··o., I) 0 S S SAnd registor withA:- =
registers
X..II/I.'_J'.i_D.. _'.u
1 S S S Exclusive OR
. . . . ... register willl A ._
'-.1: ~_.
INXD 0 0 0 1 0 0 I I i,lcrement D & E
registers
.. - :~I 0 S S S ~i~hr~gistor
INXH 0 0 1 0 0 0 1 1 Increment H & L
DCXB 0 0 U 0
-
1 0 1 , registers
Decrement B & C
J
~~_~_ ~_c .. ~.l ISS S ~~~~are register . __
DCXD 0 0 0
-~--
, 1 0 ._--
1 1 Decrement D & E ANA ~ 1 U 1 0 0 , 1 0 And memory with A
DCXH 0 0
--
'1 0 '1 0 1 I ,Decrement f:i.~~
XRAM I', -o-·~·· "-1-;--0 ExclusiveoR~~
f)
--1-:-
~.
ADDr 1 0 0 0 . 0 S S S Add register to A
ORA M
eMF' M
+ I
0
U
:
I •
with A
1 0 , 1 0 OR memory with A
1 1 1 0 Compare
ADCr 1 0 0 r 1 S S S Add register to A memory with A _._
with carry
ANi I I ' 0 0
1 1 0 And Immediate
ADDM I 0 C 0 0 1 1 0 Add memory to A
ADCM ,--_ " _-------
0
......
" 0 1 1 1 0 Add memory to A
1--
XRI
with A _ _ _ _- j
.,---. _ _ _ _-\-':.:.::.c..:.:.::.c..
1 1 '1 0 1 , 1 0 Exclusive OR
with carry Immediate with A
.
ADI
ACI
1
, 1 0
1 0
'-
0 0
0 ,, 1 1 0 Add immediate to A
1 0 Add immediate to A
with carry
DADB 0 0 (} 0 1 0 0 I AddB&CtoH&L
15·29
inter 8085AH/8085AH-2/8085AH-1
Table 6. Instruction Set Summary (Continued)
M . Instruction Code Operations Mnemonic Instruction Code Operations
nemonrc D7 D6 Ds D4 D3 D2 D1 Do Description 07 D6 Os 04 03 02 D1 Do Description
ROTATE CONTROL
RLC 0 0 0 0 0 1 1 1 Rotate A left EI 1 1 1 1 1 0 1 1 Enable Interrupts
RRC 0 0 0 0 1 1 1 1 Rotate A right DI 1 1 1 1 0 0 1 1 Disable Interrupt
RAL 0 0 0 1 0 1 1 1 Rotate A left NOP 0 0 0 0 0 0 0 0 No-operation
through carry HLT 0 1 1 1 0 1 1 0 Halt
RAR 0 0 0 1 1 1 1 1 Rotate A right NEW 8085AH INSTRUCTIONS
through carry
RIM 0 0 1 0 0 0 0 0 Read Interrupt
SPECIALS Mask
CMA 0 0 1 0 1 1 1 1 Complement A SIM 0 0 1 1 0 0 0 0 Set Interrupt Mask
STC 0 0 1 1 0 1 1 1 Set carry
CMC 0 0 1 1 1 1 1 1 Complement carry
DAA 0 0 1 0 0 1 1 1 Decimal adjust A
NOTES:
1. DDS or SSS: B 000, C 001, D 010, E011, H 100, L101, Momory 110, A 111.
2. Two possible cycle times (6/12) indicate instruction cyclos dependent on condition flags .
• All mnemonics copyrighted @)Intel Corporation 1976.
15-30
8155H/8156H/8155H-2/8156H-2
2048-BIT STATIC HMOS RAM
WITH I/O PORTS AND TIMER
• Single + 5V Power Supply with 10%
Voltage Margins • 1 Programmable 6·Bit 1/0 Port
• the
30% Lower Power Consumption than • Programmable 14·Bit Binary Counterl
Timer·
8155 and 8156
• 256 Word x 8 Bits
• Compatible with 8085AH and 8088 CPU
• Completely Static Operation • Multiplexed Address and Data Bus
• Internal Address Latch • Available in EXPRESS
- Standard Temperature Range
- Extended Temperature Range
• 2 Programmable 8·Bit 1/0 Ports
The Intel® 8155H and B156H are RAM and 1/0 chips implemented in N-Channel, depletion load, silicon gate
technology (HMOS), to be used in the 8085AH and B08B microprocessor systems. The RAM portion is
designed with 2048 static cells organized as 256 x 8. They have a maximum access time of 400 ns to permit
use with no wait states in 8085AH CPU. The 8155H-2 and 8156H-2 have maximum access times of 330 ns for
use with the 8085H-2 and the 5 MHz 8088 CPU.
The 1/0 portion consists of three general purpose 1/0 ports. One of the three ports can be programmed to be
status pins, thus allowing the othor two ports to operate in handshake modo.
A 14-bit programmable countor/timer is also included on chip to provide oithor a square wave or terminal
. count pulse for the CPU system do pending on timer mode.
PC, Vee
pc, PC 2
a
101M
TIMER IN PC,
G
PA o ·7
RESET PCo
ADo 7 256 X 8 PC 5 PB,
STATIC TIMER OUT PBs
RAM 101M PB5
* PB,
ALE
RP
G PBo-7 AD
WR
ALE
ADo
PB,
PB 2
PB,
PB o
WR AD, PA,
G
pCo - s AD2 PAs
RESET TIMER AD, PA5
AD. PA.
AD5 PA,
TIMER ClK L vcc (+5VI AD. PA 2
AD, PA,
TIMER OUT vss (OVI
vss PAo
231719-1
'8155H/8155H-2 ~ CE, 8156H/8156H-2 ~ CE 231719-2
Figure 1. Block Diagram Figure 2. Pin Configuration
December 1986
15-31 Order Number: 231719-001
inter 8155H/8156H/8155H-2/8156H-2
Table 1. Pin Description
Symbol Type Name and Function
RESET I RESET: Pulse provided by tile 8085AH to initialize the system (connect to
8085AH RESET OUT). Input high on this line resets the chip and initializes the
three ilO ports to input mode. The width of RESET pulse should typically be
two 8085AH clock cycle times.
ADo-7 1/0 ADDRESS/DATA: 3'state Address/Data lines that interface with the CPU
lower 8-bit Address/Data Bus. The 8-bit address is latched into the address
latch inside the 8155H/56H on the falling edge of ALE. The address c~ be
either for the memory section or the I/O section depending on the 10/M input. ,
The 8-bit data~either written into the chip or read from the chip, depending
on the WR or RD input signal.
CE orCE I CHIP ENABLE: On tho 8155H, this pin is CE and is ACTIVE LOW. On the
8156H, this pin is CE and is ACTIVE HIGH.
RD I READ CONTROL: Input low on this line with the Chip Enable active enables
and 1100-7 buffers. If 101M pin is low, the RAM content will be read out to the
AD bus. Otherwise the content ofthe selected 1/0 port or command/status
renisters will be read to the AD bus.
WR I WRITE CONTROL: Input low on this line with the Chip Enable active causes
the data on the Address/Data bus to be written to the RAM or I/O ports and
commandlstatus register, depending on 10/tv1.
ALE I ADDRESS LATCH ENABLE: This control signal latches both the address on
tho 110 0 _ 7 lines and the state of the Chip Enable and 10/M into the chip at the
f<1lll11g edge of ALE.
101M I I/O MEMORY: Selects memory if low and 1/0 and command/status registers
if Iligh.
--
PAO-7 (8) 110 PORT A: These 8 pins are general purpose 1/0 pins. The in/out direction is
selected by programming the command register.
PBO-7 (8) I/O PORT B: These 8 pins are general purpose 1/0 pins. The in/out direction is
selected by programming the command register.
PCO-5 (6) I/O PORT C: These 6 pins can function as either input port, output port, or as
control signals for PA and PB. Programming is done through the command
register. When PCO-5 are used as control signals, they will provide the
following:
PCo-A INTR (Port A Interrupt)
PC1-ABF (Port A Buffer Full)
PCr-A STB (Port A Strobe)
PC3-B INTR (Port B Interrupt)
PC4-B BF (Port B Buffer Full)
PC5-B STB (Port BStrobe)
TIMER IN I TIMER INPUT: Input to the timer-counter.
TIMER OUT 0 TIMER OUTPUT: This output can be either a square wave or a pulse,
depending on the timer mode.
Vee VOLTAGE: +5V supply.
Vss GROUND: Ground reference.
15-32
8155H/8156H/8155H-2/8156H-2
-------,--------
FUNCTIONAL DESCRIPTION
I I
The 8155H/8156H contains the following: I I
I I
• 2K Bit Static RAM organized as 256 x 8 I I
I I
• Two a-bit 1/0 ports (PA & PB) and one 6-bit 1/0 I I
port (PC) I I
I 4.1...-~----1 I
• 14-bit timer-counter I I
TIMER
I MODE I
I
The 10lM (IO/Memory Select) pin selects either the L ____ _ ' _________ ...3I
five registers (Command, Status, PAo':'?, PBO-7,
PCO-5) or the memory (RAM) portion.
231719-3
The a-bit address on the AddresslData lines, Chip
Figure 3. 8155H/8156H Internal Registers
Enable input CE or CE, and 101M are all latched on-
chip at the falling edge of ALE.
OR
\ V '\
--_.
CE(8158H)
/ f\ /
--
101M
\ II \
X ADDRESS I\.
<IX I J.'\f A VALID
AL E
iiDORWR
NOTE: 231719-4
For detailed timing information, see Figure 12 and A.C. Characteristics. ________ ~ _ _ _ _ _ _ ____l
Figure 4. 8155H/8156H On-Board Memory Read/Write Cycle
15-33
inter 8155H/8156H/8155H-2/8156H-2
PROGRAMMING OF THE COMMAND READING THE STATUS REGISTER
REGISTER The status register consists of seven latches, one
The command register consists of eight latches. for each bit; six (0-5) for the status of the ports and
Four bits (0-3) define the mode of the ports, two bits one (6) for the status of the timer.
(4-5) enable or disable the interrupt from port C
when it acts as control port, and the last two bits The status of the timer and the 1/0 section can be
(6 -7) are for the timer. . polled by reading the Status Register (Address
XXXXXOOO). Status word format is shown in Figure
The command register contents can be altered at 6. Note that you may never write to the status regis-
any time by using the 1/0 address XXXXXOOO during ter since the command register shares the same 1/0
a WRITE operation with the Chip Enable active and address and the command rogister is selected when
101M = 1. The meaning of each bit of the command a write to that address is issued.
byte is defined in Figure 5. The contents of the com-
mand register may never be read.
5 4
T_:
ITM' TM,IIEBI'EAI pc,1 PC,
L-~.,
PB I f'"
_
_
I-
I
DEFINESPA.., }
_.... DEFINES PBo-7
__ DEFINES PC
0'" INPUT
1 " OUTPUT
00' All 1
{ ' 1 ' ALl2
0-5 01~AlT3
10"AlT4
'---____ .. ~N~~BRl~U~RT A 1 ~ (NABLE
_________ r~::RL:u~AT B }
o~ DISABLE
00'" NOP· 00 NOT AFFECT COUNT [II
OPErlATION
01 ~. STOP NOP IF TIMER HAS NOT ~;TARTED'
STOP COUNTING IF THE TIMI f! I!; .
RUNNING
10 STor AFTER TC _ STOP IMMI tllflTll.Y
M
TIMER COMMAND AfHR PRESENT TC IS REACt" 0 (tIOP •
If' TIMER HAS NOT STARH(l1
11· ~T AnT - LOAD MODE AND crn U NGTH
AND STARl" IMMEOIATEL Y fII H n
LOADING (IF TIMER IS NOT I'IH $(NTlV
RUNNINGI. IF TIMER IS RUNNING, START
THE NEW MODE AND CNT l r NG Tft
IMMEDIATELY AFTER PRES(NT Ie
IS REACHED.
231719-5
Figure 5. Command Register Bit Assignment
AD, AO. ADs AD4 AD3 A02 AD, ADo
I:8:E'MFAJ'~EI B~ I'N:RI'N;EI :F I'N;AI
I I I L PORT A INTERRUPT REaUEST
~ paRT A BUFFER FULLIEMPTV
(INPUT/OUTPUT)
PORT A INTERRUPT ENABLE
PORT B INTERRUPT REOUEST
- PORT B BUFFER ,FUll/EMPTY
(INPUT/OUTPUT)
PORT B INTERRUPT ENABLED
TIMER INTERRUPT (THIS BIT
IS LATCHED HIGH WHEN
TERMINAL COUNT IS
REACHED, AND IS RESET TO
lOW UPON READING OF THE
CIS REGISTER AND BY
HARDWARE RESET).
231719-6
Figure 6. Status Register Bit Assignment
15-34
8155H/8156H/8155H-2/8156H-2
INPUT/OUTPUT SECTION ond is an output signal indicating whether the
buffer is full or empty, and the third is an input pin
The 110 section of the 8155H/8156H consists of to accept a strobe for the strobed input mode.
five registers: (see Figure 7.) (See Table 2.)
• Command/Status Register (C/S)-Both regis-
ters are assigned the address XXXXXOOO. The When'the 'C' port is programmed to either ALT3 or
CIS address serves the dual purpose. ALT 4, the control signals for PA and PB are initial-
When the CIS registers are selected during ized as follows:
WRITE operation, a command is written into the
command register. The contents of this register Control Input Mode Output Mode
are not accessible through the pins. BF Low Low
When the CIS (XXXXXOOO) is selected during a INTR Low High
READ operation, the status information of the 1/0 STB Input Control Input Control
ports and the timer becomes available on the
ADo-7 lines.
I/O Addresst
• PA Register-This register can be programmed Selection
to be either input or output ports depending on A7 A6 AS A4 A3 A2 A1 AD
the status of the contents of the CIS Register. X X X X X 0 0 0 Interval CommandlStatus
Also depending on the command, this port can Register
operate in either the basic mode or the strobed X X X X X 0 1 General Purpose 110 Port A
0
mode (see timing diagram). The 1/0 pins as- X X X X X 0 1 0 General Purpose 110 Port B
signed in relation to this register are PAO-7. The X X X X X 0 1 1 Port C-General Purpose
address of this register is XXXXX001. 1/0 or Control
• PB Register-This register functions the same X X X X X 1 0 0 Low-Order 8 bits of Timer
as PA Register. The 1/0 pins assigned are Count
PBO-7. The address of this register is XXXXX01 O. X X X X X 1 0 1 High 6 bits of Timer Count
and 2 bits of Timer Modo
• PC Register-This register has the address X: Don't Care.
XXXXX011 and contains only 6 bits. The 6 bits t: 1/0 Address mw;t bo qualified by CE = 1 (8156H)orct
can be programmed to be either input ports, out- = 0 (8155H) and 101M = 1 in order to select the appropri-
put ports or as control signals for PA and PB by ate register.
properly programming the AD2 and AD3 bits of Figure 7. 1/0 Port and Timer Addressing Scheme
the CIS register.
When PCO-5 is used as a control port, 3 bits are Figure 8 shows how 1/0 PORTS A and Bare struc-
assigned for Port A and 3 for Port B. The first bit
.-_is_a_n_i_n_te_r_ru_p_t_th_a_t_th_e_8_1_5_5_H__
tured within the 8155H and 8156H:
se_n_d_s_O_U_t._T_h_e_s_e_c_-______________________________________ ~ IIJ!III
8155H/8156H One Bit of Port A or Port B
I
STB
231719-7
NOTES: ]
(1 j Output Mode Multiplexer
(2) Simple Input Control (4) = 1 for Output Mode
(3) Strobed Input = 0 for Input Mode
READ Port = (101M = 1). (RD = 0) • (CE Active) • (Port Address Selected)
WRITE Port = (101M = 1) • (WR = 0). (CE Active) • (Port Address Selected)
Figure 8. 8155H/8156H Port Functions
15-35
8155H/8156H/8155H-2/8156H-2
Table 2 Port Control Assignment
Pin ALT1 ALT2 ALT3 ALT4
PCO Input Port Output Port A INTR (Port A Interrupt) A INTR (Port A Interrupt)
PC1 Input Port Output Port A BF (Port A Buffer Full) A BF (Port A Buffer Full)
PC2 Input Port , Output Port A STB (Port A Strobe) A STB (Port A Strobe)
PC3 Input Port Output Port Output Port B INTR (Port B Interrupt)
PC4 Input Port Output Port Output Port B BF (Port B Buffer Full)
PC5 Input Port Outpu~£>ort Output Port B STB (Port B Strobe)
Note in the diagram that when the I/O ports are pro- TIMER SECTION
grammed to be output ports, the contents of the out-
put ports can still be read by a READ operation The time' is a 14-bit down-counter that counts the
when appropriately addressed. TIMER IN pulses and provides pither a square wave
or pulse when terminal count (Tr,) is reached.
The outputs of the 8155H/8156H are "glitch-free"
meaning that you can write a "1" to a bit position The timer has the 110 address XXXXX100 for the
that was previously "1" and the lE've! at the output low order byte of the register and the 1/0 address
pin will not change. XXXXX101 for the high 0rder hyte of the register.
(See Figure 7.)
Note also that the output latch is cleared when tho
port enters the input mode. The output latch cannot To program the timer, the COUNT LENGTH REG is
be loaded by writing to the port if the port is in tho loaded first, one byte at a time, by selecting the tim-
input mode. The result is that ear.h time a port modo er addresses. Bits 0-13 of ttlE' high order count reg-
'is changed from input to output, the output pin will ister will specify the len~th of the next count and bits
go low. When the 8155H/56H is HESET, the output 14-15 of the high order r'"gister will specify the timer
latches are all cleared and all 3 pnrts enter the inpul output mode (see Figura '10). The value loaded into
mode. the count length register can have any value from
2H through 3FFFH il1 Aits 0 ..·13.
When in the ALT 1 or ALT 2 nwoes, the bits of , - - - - - - - - _._---,
PORT C are structured like the diagram above in the
simple input or output mode, respectively. 1 I, " 4 3 2 1 II
Reading from an input port with noliling connectetl
IM,I M,IT"I T"ITIII
L-.. f'
fl.1
_ ..- - - , - - _ _ _
T,I T"I
I
to the pins will provide unpredictable results. TIMER MOIII MSB OF CNT LENGTH
7hlj43210
Figure 9 shows how the 8155H/8156H 1/0 ports
might be configured in a typical MCS®-85 system.
GI
,_.
T" I T, I T, 1 T,I T21 T, 1 Tn 1
• _ _ _ _ ,. _ _ _ _ _ _ _ _ ••.•••• J
lSB OF CNT LENGTH
231719-9
TO 808_ RST INPUT
~PORTA .r Figure 10. Timer Format
--1
PORT A
A INTRtrlGNALS DATA RECEIVEDI
. ., ",. ., . MU " M " }
There are ,four modes to choose from: M2 and M1
A srB (ACKNOWL. DATA RECEIVED, TO/FROM define the timer mode, as shown in Figure 11.
PORTe B STB (L.OADSPORT B LATCH) PERIPHERAL
B BF (SIGNALS BUFFER IS FULLI
B INTR {SIGNALS BUFFER
READV FOR READINGI
.J' INTERFACE
TIMER OUT WAVF.FORMS:
PORT B ~ TO INPUT PORT (OPTIONAL)
MODE
BITS
STAAT
COUNT
TERMINAL
COUNT
(TERMINAL)
COUNT
TO 8085AH RST {NPUT Mz M,
+ + +
~-----------
1. SING1.E
231719-8 ~ saUARE WAVE
Figure 9. Example: 2. CONTINUOUS
Command Register "= 00111001 SOUARE WAVE
3. SINGLE
PULSE ON
TERMINAL COUNT
v------------
4. CONTINUOUS
PULSES ur---v--
231719-10
---._--------
Figure 11. Timer Modes
15-36
inter 8155H/8156H/8155H-2/8156H-2
Bits 6-7 (TM2 and TM1) of command register con- The counter in the 8155H is not initialized to any
tents are used to start and stop the counter. There particular mode or count when hardware RESET oc-
are four commands to choose from: curs, but RESET does stop the counting. Therefore,
TM2 TM1 counting cannot begin following RESET until a
o 0 NOP-Do not affect counter operation. START command is issued via the CIS register.
·0 STOP-Nap if timer has not started; stop
counting if the timer is running. Please note that the timer circuit on the 8155HI
o STOP AFTER TC-Stop immediately after 8156H chip is designed to be a square-wave timer,
present TC is reached (Nap if timer has not not an event counter. To achieve this, it counts
started) down by twos twice in completing one cycle. Thus,
START-Load mode and CNT length and its registers do not contain values directly represent-
start immediately after loading (if timer is not ing the number of TIMER IN pulses received. You
presently running). If timor is running, start cannot load an initial value of 1 into the count regis-
the new mode and CNT length immediately ter and cause the timer to operate, as its terminal
after present TC is reachod. count value is 10 (binary) or 2 (decimal). (For the
detection of single pulses, it is suggested that one of
Note that while the counter is counting, you may the hardware interrupt pins on the 8085AH be used.)
load a new count and mode into the count length After the timer has started counting down, the val-
registers. Before the new count and mode will be ues residing in the count registers can be used to
used by the counter, you must is suo a START com- calculate the actual number of TIMER IN pulses re-
mand to the counter. This applies oven though you quired to complete the timer cycle if desired. To ob-
may only want to change the count and use the pre- tain the remaining count, perform the following oper-
vious mode. . ations in order:
1. Stop the count
In case of an odd-numbered count, the first half-cy- 2. Read in the 16-bit value from the count length
cle of the squarewave output, which is high, is one registers
count longer than the second (Iuw) half-cycle, as
shown in Figure 12. 3. Reset the uppor two mode bits
4. Reset the. carry und rotate right one position all 16
bits through cmry
5. If carry is set, add Y2 of the full original count (%
full count-1 if full count is odd).
NOTE:
If you started with an odd count and you read the
count length register before the third count pulse •
occurs, you will not be able to discern whether one
5 or two counts has occurred. Regardless of this, the
231719-11 8155H/56H always counts out the right number of
pulses in generating the TIMER OUT waveforms.
NOTE:
5 and 4 refer to the number of clocks in that time peri-
od.
Figure 12. Asymmetrical Square-Wave Output
Resulting from Count of 9
15-37
intJ 8155H/8156H/8155H·2/8156H~2
8085AH MINIMUM SYSTEM • 2KBytes EPROM
CONFIGURATION • 381/0 Pins
• 1 Interval Timer
Figure 13a shows a 'minimuin system using three'
chips, containing: • 4 Interrupt Levels
• 256 Bytes RAM
A8-15
..w.
AOO-1
:lE
lID
<
..
.---:.
'---
i'
--
>
WI!
,.-- I--f- ---
101"
elK
r-- l - f--
RESET OUT
READY
-,
'--- I-f-
I-- f- -,-
" -
Vee
TIMrn
RESET IN WRRD ALE
e' ' " ;,-
10iM ~:~~ 7~:~ ff I~f ALE m:iill\'i
P-' RS ROY
--C::J. J~r- A I (;11[5
T~~~R_
£"1- c--~'~l •
11_
CONTROL
-,
C""J'
T
III\M
A7SSA IEPROM + 1101
~~~~
B 88 88 231719-12
Figure 1~a. 8085AH Minimum System Configuration (Memory Mapped 110)
15·38
inter 8155H/8156H/8155H-2/8156H-2
8088 FIVE CHIP SYSTEM • 38 I/O Pins
• 1 Interval Timer
Figure13b shows a five chip system containing:
• 2 Interrupt Levels
• 1.25K Bytes RAM
• 2K Bytes EPROM
Vss Vee
I I
I-r--- CE POR!W
~+---_WR Pc>
Ali PORT 18)
11111102 B
ALE PORTPc>
DATAl C 16)
ADOR
[v-
>-- --- IN_
101M TIMER
RESET
OUT f:-
Aa-A19 ~oiiii
.y' '" lOW
Ali
,-- - - eLK
ADo- AC r l/t AOORIOAT A
f--1',
I\~
~
t-- t-- .
~---
t-- t-- --- ALE
CE
PORT
A
~
8088 II~
t--'-- "
--V
A a· 10
--- READY
MN/MX J--Vcc
CII I DATAl
11755A-2
[V-r- ADDR
rDl R5T@
ALE
Ali
- l-
l-
t-
t- t---
101M PORT
~
I
~- RESET 8
X, X,
ClK WR l- t- Vee
READY
READY I - - 101M l- I - f-- - iOR ..J
RES l- I - t- ..
8284
RESET
~
r--- r---i- -- t--
111 L pROG
•
Vss Vee Voo
ROY1 Vee
WR
.... RD
CD eE,
111s.2
ALE
lI- es.
CE,
15--1-
II-r--- All. Ag
A
ADO. 7
.
I I
Vss Vee
7
231719-13
Figure 13b. 8088 Five Chip System Configuration
15-39
inter 8155H/8156H/8155H-2/8156H-2
ABSOLUTE MAXIMUM RATINGS· NOTICE: This is a production data sheet. The specifi-
cations are subject to change without notice.
Temperature Under Bias ............ O'C to + 70'C
• WARNING: Stressing the device beyond the "Absolute
Storage Temperature .......... -65'C to + 150'C Maximum Ratings" may cause permanent damage.
Voltage on Any Pin These are stress ratings only. Operation beyond the
with Respect to Ground .......... - 0.5V to + 7V "Operating Conditions" is not recommended and ex-
tended exposure beyond the "Operating Conditions"
Power Dissipation .......................... 1.5W may affect device reliability.
D.C. CHARACTERISTICS T A = O'C to 70'C, Vcc = 5V ± 10%
Symbol Parameter Min Max Units Test Conditions
V'l Input Low Voltage -0.5 O.B V
V,H Input High Voltage 2.0 Vcc+ 0.5 V
VOL Output Low Voltage 0.45 V IOl = 2mA
VOH Output High Voltage 2.4 V IOH = -400/LA
I,l Input Leakage ±10 /LA OV s: Y,N s: Vcc
ILO Output Leakage Current ±10 /LA 0.45V s: VOUT s: Vcc
Icc Vcc Supply Curront 125 rnA
I,l (CE) Chip Enable Leakage
B155H +100 /LA OV s: Y,N s: Vcc
8156H -100 /LA
A.C. CHARACTERISTICS TA = 0'Ct070'C, Vcc = 5V ±10%
8155H/8156H 8155H-2~8156H-2
Symbol Parameter· Units
Min Max Min Max
tAL Address to Latch Setup Time 50 30 ns
tLA Addresl1 Hold Time after Latch 80 30 ns
tlC Latch to READ/WRITE Control 100 40 ns
tRO Valid Data Out Delay from READ Control 170 140 ns
tlO Latch to Data Out Valid 350 270 ns J
tAD Address Stable to Data Out Valid 400 330 ns .
tll Latch Enable Width 100 70 ns
tROF Data Bus Float after READ 0 100 0 80 ns
tCl READ/WRITE Control to Latch Enable 20 10 ns
tCll WRITE Control to Latch Enable for CIS Register 125 125 ns
. tcc READ/WRITE Control Width 250 200 ns
tow·. Data In to WRITE Setup Time 150 100 ns
two Data.!n Hold Time after WRITE 25 25 ns
tRV Recovery Time between Controls 300 200 ns
twp WRITE to Port Output 400 300 ns
15-40
inter 8155H/8156H/8155H-2/8156H-2
A.C_ CHARACTERISTICS TA = O·C to 70·C, Vee = 5V ± 10% (Continued)
8155H/8156H 8155H-2/8156H-2
Symbol Parameter Units
Min Max Min Max
tpR Port Input Setup Time 70 50 ns
tRP Port Input Hold Time 50 10 ns
tSBF Strobe to Buffer Full 400 300 ns
tss Strobe Width 200 150 ns
tRBE READ to Buffer Empty 400 300 ns
tSI Strobe to INTR On 400 300 ns
tRDI READ to INTR Off 400 300 ns
tPSS' Port Setup Time to Strobe 50 0 ns
tpHS Port Hold Time After Strobe 120 100 ns
tSBE Strobe to Buffer Empty 400 300 ns
"
tWBF WRITE to Buffer Full 400 300 ns
tWI WRITE to INTR Off 400 300 ns
tTL TIMER·IN to TIMER·OUT Low 400 300 ns
tTH TIMER·IN to TIMER·OUT High 400 300 ns
tRDE Data Bus Enable from READ Control 10 10 ns
I '
t1 TIMER·IN Low Time 80 40 ns
t2 TIMER·IN High Time 120 70 ns
tWT WRITE to TIMER·IN 360 200 ns
(for writes which start counting)
A.C. TESTING INPUT, OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT
. ------------, II
x=
INPUT/OUTPUT
'.'=X
0.45
2.0
0.8
> TEST POINTS < 2.0
0.8
231719-14
DEVICE
UNDER
TEST
i CL = 150pF
A.C. testing: inputs are driven at 2.4V for a logic "I" and 0.45V for
a logic "0". Timing measurements are made at 2.0V for a logic 231719-15
"I" and O.BV for a logic "0". CL ~ 150 pF
CL Includes Jig Capacitance
15·41
8155H/8156H/8155H-2/8156H-2
WAVEFORMS
READ
CE(ll5SK)
~
OR
I'-
CE (l158HI
/ 1\ /
101M \ l( ~
11\11'
). ~
DATA VALID
7
>- _II\L-
ADDRESS
- t LA - - · · ·
L,... -
AL E
J r\ ; V
--'11--- _tRDE'" f-tRDF-
-C>r-.,. - - I R O -
- l ll:-------:-
II
_ - I CI - -
I\-
I - - - - tCC · · - I- ----IRV-
------tLO
231719-16
WRITE
CE(ll &lltl \ ( \
oR
ci! (II SlHI
/ .~I\.
I
i011i
\ I \
A°0_7
~
I - - tAL -
ADDRESS
I--tLA -
K x: _ t ow -
DATA VALID
_ t CL -
K
ALE
/ 1\ _V
J--- t LL - ~tlc~1 ! - two -
W;;
teLL
II f\>-
I t.------- t,ce - j.---ttWT
Rv _
~
TIMER IN
)
231719-17
15-42
inter 8155H/8156H/8155H-2/8156H-2
WAVEFORMS (Continued)
STROBED INPUT
BF
lNTR
INPUT DATA
FROM PORT
--------~~--~~~---------------------------
231719-18
STROBED OUTPUT
BF
INTR
OUTPUT DATA
TO PORT
--------------------------------------------~~--------------------------------
231719-19
BASIC INPUT BASIC OUTPUT
tRe } -I WR
}
k-
AD
i..
INPUT ===>t tpR
OATA BUS·
OUTPUT _ _ _ _ _ _ _ _ _ _ _ _---J~ y,!---
[)ATABUS· ~=====~
231719-20 231719-21
'Data Bus Timing is shown in Figure 7.
15-43
:::!
~
~
III
::D'm
0
C
~
<
."
0
:D
l
c s:
-t (/)
()
0 (')
C 0
~
Z ct.
-t ~
I
LOAD COUNTER FROM CLR
2 I
_I s 4
RELOAD COUNTER FROM CLR
I 2 I -\
CI
~z
i
B
"II
::D CD
0 -.
TIMER IN ~ en
en
en ::z:
.....
-t CD
0 -.
.....
s:
::z:
.....
UI
TIMER OUT
(PULSEI
\
\ (NOTE 11
, I
0;
-.
t '----" en
en
::z:
~
TIMER Om' \ INOTE 11 I
.....
CD
(SQUARE WAVEI \ I -.
'----------' en
CD
::z:
N•
231719-22
NOTE:
1. The timer output is periodic if in an automatic reload mode (M1 Mode bit = 1).
8185/8185-2
1024 x 8-BIT STATIC RAM FOR MCS®-85
• Multiplexed Address and Data Bus
• Low Standby Power Dissipation
• Directly Compatible with 8085AH and
8088 Microprocessors • Single + 5V Supply
• Low Operating Power Dissipation • High Density 18-Pin Package
The Intel 8185 is an 8192-bit static random access memory (RAM) organized as 1024 words by 8-bits using N-
channel Silicon-Gate MOS technology. The multiplexed address and data bus allows the 8185 to interface
directly to the 8085AH and 8088 microprocessors to provido a maximum level of system integration.
The low standby power dissipation minimizes system powor requirements when the 8185 is disabled.
The 8185-2 is a high-speed selected version of the 8185 til at is compatible with the 5 MHz 8085AH-2 and the
5 MHz 8088.
ADO Vee
cs
CEl
. ADl
AD2
RD
WR
CE2
RD R/W AD3 ALE
LOGIC
WR
ALE AD, cs
~
ADs CEl
ADs CE2
AD-r Ag
..l\ DATA
BUS
1K x 8
RAM
DUffeR MEMORY Vss As
IV' ARRAY
231450-2
Figure 2. Pin Configuration
X·YDECODE
;:::.
As,Ag
ALE
L--I\
~
ADDRESS
LATCH
U ADo-AD7
As, Ag
CS
Pin Names
Address/Data Lines
Address Lines
Chip Select
231450-1 CE1 Chip Enable (IO/M)
Figure 1. Block Diagram CE2 Chip Enable
ALE Address Latch Enable
WR Write Enable
November 1989
15-45 Ordor Number: 231450·002
inter 8185/8185-2
FUNCTIONAL DESCRIPTION
The 8185 has been designed to provide for direct Vss Vee
interface to the multiplexed bus structure and bus !!!
timing of the 8085A microprocessor.
- TRAP
X, X, IlESET IN
I--
---
HOLD
RST7,5 HLDA
r-
At the beginning of an 8185 memory access cycle, RST6,5
B085A
SOD
I-
RST5,5 I--
-
SID
the 8-bit address on ADo-7' A8 and Ag, and the INTR
-
S,r-
status of GEl and GE2 are all latched internally in 1m'A
HI !it T
OUT S.I-
ADORI
the 8185 by the falling edge of ALE. If the latched ADO A DATA ALE f,o WA 101M nOyeLK
status of both GEl and GE2 are active, the 8185
powers itself up, but no action occurs until the GS '" 181 T VI'
line goes low and the appropriate RD or WR control Itf-- ~ POR~~
signal input is activated.
The GS input is not latched by the 8185 in order to
WR
RD B156
PORT
B
W '
8)
ALE PORTpv
allow the maximum amount of time for address de- DATAl C
coding in selecting the 8185 chip, Maximum power r~ AODA
IN
consumption savings will occur, however, only when 10/0\1 TIMER I-
GEl and GE2 are activated selectively to power ~ RESET OUT r---
down the 8185 when it is not in use. A possible con-
nection would be to wire the 8085A's 10/M line to lOW
the 8185's GEl input, thereby keeping the 8185 RD
powered down during I/O and interrupt cycles. ALE
Table 1. Truth Table for t-
_l\.
eE
AS_1O
ponr
A
W
Power Down and Function Enable f=
B755A
CEI CE2 CS (CS*)(2) 8185 Status DATAl
ADOR
-
~
1 X X 0 Power Down and 101M ponT
B
Function Disable( 1) ~ t- I- RESET
noy
X 0 X 0 Power Down and .- elK
Function Disable(l)
0 1 1 0 Powered Up and
vs~ )[" V~l(l tROG
Function Disable(l) wn
iID
0 1 0 1 Powered Up and
Enabled CT, 8185
ALE
NOTES: IH- CS, CE 2
X = Don't Care, IH- AS. Ag
1: Function Disable implies Data Bus in high impedance A°0- 7
state and not writing.
2: CS' = (CEl = 0) X (CE2 = 1) x (CS = 0),
CS' = 1 signifies all chip enables and chip select ac- Vss
t vL
tive. Vee
Vee
Table 2. Truth Table for
Control and Data Bus Pin Status 231450-3
ADo_7 During Data Figure 3. 8185 in an MCS®-85 System
(CS*) RD WR 8185 Function
Portion of Cycle
4 Chips:
0 X X Hi-Impedance No Function 2K Bytes EPROM
1.2SK Bytes RAM
1 0 1 Data from Memory Read
38 1/0 Lines
1 1 0 Data to Memory Write 1 CounterlTimer
2 Serial 1/0 Lines
1 1 1 Hi-Impedance Reading, but not S Interrupt Inputs
Driving Data Bus
NOTE:
X = Don't Care,
15-46
8185/8185-2
iAPX 88 FIVE CHIP SYSTEM:
• 1.25K Bytes RAM
• 2K Bytes EPROM
• 38 I/O Pins
• 1 Internal Timer
• 2 Interrupt Levels
/'-.. Vss Vee
I I
~ POR!~
\--
.--+-- - _ .- WR
RD POR~
W (6)
W
8155-2
ALE PORT
v-- DATAl e (6)
rv ~ ---
ADOR
101M TIMER
IN_
RESET
OUT r---
As-A1,)
--
ADOR
,,-
..
lOW
v
- RO
~
W
ADo - AD1 ADOR/DATA t- -- ALE
~ eLK
l"-r I\~ r- t- eE
PORT
A
r- - - - - _... _t.
8088 /;= AS_l0
r - - READY
MNIMX ....-Vcc
r:rLIII--~ I
DATAl
81S5A·2
ADDA
rDl , - RST ®
ALE
AD
r--- -
-
101M PORT
B
W
I
t-- >----- RESET
x, X,
eLK WR t-- Vee
READY
READY r- 101M
r--- ;00 .--J
•
RES - r-
82UA
REseT r---
III L
Vss Vee Voo
pROG
ROV1 Vee
WR
.... Rij
CD GE, 818$-2
ALE
\1- es.
Ifr- eE,
I~r- Ae. Ag
ADO_1
~
I I
Vss Vee
231450-4
Figure 4. iAPX 88 Five Chip System Configuration
15-47
inter 8185/8185-2
ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. The specifi-
cations are subject to change without notice.
Temperature Under Bias ............ O·C to + 70·C
• WARNING: Stressing the device beyond the "Absolute
Storage Temperature .......... - 65·C to + 150·C Maximum Ratings" may cause permanent' damage.
Voltage on Any Pin These are stress ratings only. Operation beyond the
with Respect to Ground .......... - 0.5V to + 7V "Operating Conditions" is not recommended and ex-
Power Dissipation .......................... 1.5W tended exposure beyond the "Operating Conditions"
may affect device reliability.
D.C. CHARACTERISTICS TA = 0·Ct070·C, Vec = 5V ±10%
Symbol Parameter Min Max Units Test Conditions
VIL Input Low Voltage -0.5 0.8 V
VIH Input High Voltage 2.0 Vcc+ 0.5 V
VOL Output Low Voltage 0.45 V IOL = 2mA
VOH Output High Voltago 2.4 IOH = -400 J.tA
IlL Input Leakage ±10 J.tA OV s VIN S Vcc
ILO Output Leakage Current ±10 J.tA 0.45V s VOUT s Vce
..
Icc Vce Supply Current
100 mA
Powered Up
Powered Down 35 mA
A.C. CHARACTERISTICS TA = 0·Ct070"C, Vec = 5V ±10%
8185 8185-2
Symbol Parameter
Min Max Min Max Units
tAL Address to Latch Set Up Time 50 30 ns
tLA Address Hold Time After Latch 80 30 ns
tLC Latch to READ/WRITE Control 100 40 ns
tRO Valid Data Out Delay from READ Control 170 140 ns
tLO ALE to Data Out Valid 300 200 ns
tLL Latch Enable Width 100 70 ns
tROF Data Bus Float After READ 0 100 0 80 ns
tCL READ/WRITE Control to Latch Enable 20 10 ns
tcc READ/WRITE Control Width 250 200 ns
tDW Data In to WRITE Set Up Time 150 150 ns
two Data In Hold Time After WRITE 20 20 ns
tsc Chip Select Set Up to Control Line 10 10 ns
tcs Chip Select Hold Time After Control 10 10 ns
tALCE Chip Enable Set Up to ALE Falling 30 10 ns
tLACE Chip Enable Hold Time After ALE 50 30 ns
15-48
inter 8185/8185·2
A.C. TESTING INPUT, OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT
2.4 =>(20 > <2.0)<=
INPUT/OUTPUT
DEVICE
~"~'~"
UNDER
TEST
0.8 TEST POINTS 0.8
0.45 - -
231450-5 -
AC. Testing: Inputs Are Driven at 2.4V for a Logic "1" and 231450-6
OA5V for a Logic "0." Timing Measuremonts Are Made at
2.0V for a Logic "1" and O.SV for a Logic "0." (;1 .~ 150 pF
(;1 Includes Jig Capacitance
WAVEFORM
tAlCE-
ALE
(CE, =0)-
(CE2'" 11
WR. AD
ADo- AD 7 {READ CYCLE I
(As. A91
ADO·AD7 (WRITE CYClEI
(SELECTED) (DESELECTED)
231450-7
15-49
8224
CLOCK GENERATOR AND DRIVER
FOR 8080A CPU
• Single Chip Clock Generator/Driver for
8080ACPU
• Crystal Controlled for Stable
System Operation
• Power-Up Reset for CPU
• Available
Reduces System Package Count
• Ready Synchronizing Flip-Flop
• - Standardin Temperature
EXPRESS
Range
• Advanced Status Strobe
• Available in 16-Lead Cerdip Package
• Oscillator Output for External System
Timing (See Packaging Spec. Order # 231369)
The Intel 8224 is a single chip clock generator/driver for the 8080A CPU. It is controlled by a crystal, selected
by the designer to meet a variety of system speed requirements.
Also included are circuits to provide power-up reset, advance status strobe, and synchronization of ready.
The 8224 provides the designer with a significant reduction of packages used to generate clocks and timing
for 8080A.
RESET Vee
RESIN XTAl1
RDYIN XTAl "J
@> XTAl1
I--t---·D~--osc @> READY TANK
IE> XTAL2
OSC
lIT> TANK
>---¢, ID> ~2 {TTLI
"
>---·2 !j§>
STSTD
'2
GND voo
1-----·2ITTLI~
231464-2
~ SYNC ----+----L_ RESIN Reset Input
[I> XTAl1
RESIN RESET Reset Output
XTAl2
) forConnections
Crystal
H~~-+----- RESET IT> RDYIN Ready Input
READY Ready Output TANK Used with Overtone XT Al
----+-roQl-----READY~
SYNC Sync Input OSC Osciliator Output
STSTB StatusSTB <1>2 (TTL) <1>2 ClK (TTL level)
231464-1 (Active low) Vee +sv
Figure 1. Block Diagram
~ }" 8080
Clocks
VDD +12V
<1>2 GND OV
Figure 2. Pin Configuration
December 1986
15-50 Order Number: 231464-001
inter 8224
ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. The specifi-
cations are subject to change without notice.
Temperature Under Bias ............ O°C to + 70°C
• WARNING: Stressing the device beyond the "Absolute
Storage Temperature .......... - 65°C to + 150°C Maximum Ratings" may cause permanent damage.
Supply Voltage, Vee ............... - 0.5V to + 7V These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and ex-
Supply Voltage, Voo ............ - 0.5V to + 13.5V tended exposure beyond the "Operating Conditions"
Input Voltage ..................... -1.5V to + 7V may affect device reliability.
Output Current .......................... 100 mA
D.C. CHARACTERISTICS
TA = O°C to + 70°C, Vee = +5.0V ±5%, Voo = + 12V ±5%
limits
Symbol Parameter Units Test Conditions
Min Typ Max
IF Input Current Loading -0.25 mA VF = 0.45V
IR Input Leakage Current 10 p.A VR = 5.2SV
Ve Input Forward Clamp Voltage 1.0 V Ie = -SmA
VIL Input "Low" Voltage 0.8 V Vee = 5.0V
VIH Input "High" Voltage 2.6 V Reset Input
2.0 V All Other Inputs
VIH-VIL . RESIN Input Hysteresis 0.25 V Vee = 5.0V
VOL Output "Low" Voltage 0.45 V «1>1, <1>2), Ready, Reset, STSTB
IOL = 2.5 mA
0.45 V All Other Outputs
IOL = 15 mA
VOH Output "High" Voltage
•
<h </>2 9.4 V IOH = -100 p.A
READY, RESET 3.6 V IOH = -100 p.A
All Other Outputs 2.4 V IOH = -1 mA
lee Power Supply Current 115 mA
100 Power Supply Current 12 mA
NOTE:
1. For crystal frequencies of 18 MHz connect 51 on resistors between the X1 input and ground as well as the X2 input and
ground to prevent oscillation at harmonic frequencies.
Crystal Requirements
Power Dissipation (Min): 4 mW
Tolerance: 0.005% at 0°C-70°C
Resonance: Series (Fundamental)' 'NOTE:
Load Capacitance: 20 pF-35 pF With tank circuit use 3rd overtone mode.
Equivalent Resistance: 750.-200.
15-S1
inter 8224
A.C. CHARACTERISTICS
Limits Test
Symbol Parameter Units
Min Typ Max Conditions
t</>1 <1>1 Pulse Width 2tcy
- - 20ns
9
t</>2 <1>2 Pulse Width 5tcy
- - 35ns
9
t01 <1>1 to <1>2 Delay 0
t02 <1>2 to <1>1 Delay 2tcy ns Cl = 20 pF to 50 pF
- - 14ns
9
t03 <1>1 to <1>2 Delay 2tcy 2tcy
- + 20n5
9 9
tR <1>1 and <1>2 Rise Time 20
--
tF <1>1 and <1>2 Fall Time 20
t04,2 <1>2 to <1>2 (TTL) Delay -5 +15 ns <1>2 TTL, Cl = 30
R1 = 300n
R2 = 600n
toss <1>2 to STSTB Delay 6tcy 6tcy
- - 30ns ns
9 9
tpw STSTB Pulse Width tcy STSTB, Cl = 15 pF
- - 15 ns
9 R1 = 2K
RDYIN Setup Time to 4tcy R2 = 4K
tORS 50 ns - - - ns
Status Strobe 9 -
RDYIN Hold Time 4tcy
tORH afterSTSTB 9
RDYIN or RESIN to 4tcy Ready & Reset
tOR - - 25n5
<1>2 Delay 9 Cl = 10 pF
ns
R1 = 2K
R2 = 4K
telK ClK Period tcy ns
9
Maximum Oscillating 27 MHz
f max
Frequency
Cin Input Capacitance 8 pF Vee = +5.0V
VOO = +12V
VSIAS = 2.5V
f = 1 MHz
NOTE:
These formulas are based on the internal workings of the part and intended for customer convenience. Actual testing of the
part is done at tcy = 488.28 ns.
15-52
8224
A.C. CHARACTERISTICS (Continued)
For tey = 488.28 ns; TA = O°C to 70°C, Vee = + 5V ± 5%, VDO = + 12V ± 5%
Limits
Symbol Parameter Units Test Conditions
Min Typ Max
t<l>1 <1>1 Pulse Width
<1>2 Pulse Width
89
236
ns
ns
- tey = 488.28 ns
t4>2
tD1 Delay <1>1 to <1>2 0 ns
t02 Delay <1>2 to <1>1 95 ns <1>1 & <1>2 Loaded to
129 ns CL = 20 pF to 50 pF
t03 Delay <1>1 to <1>2 Leading Edges 109
tr Output Rise Time 20 ns
~-----
tl Output Fall Time
<1>2 to STSTB Delay 296
20
326
ns
ns
-
toss
t04>2 <1>2 to <1>2 (TIL) Delay -5 +15 ns
tpw Status Strobe Pulse Width 40 ns Ready & Reset Loaded
t02mAl10pF
tORS RDYIN Setup Time to STSTB -167 ns
All measurements
tORH RDYIN Hold Time after STSTB 217 ns referenced to 1.5V
READY or RESET 192 ns unless specified
tOR
to <1>2 Delay otherwise.
fMAX Oscillator Frequency 18.432 MHz
A.C. TESTING, INPUT,
OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT
~.-
u=x ?
.... vcc
R,
0.45
2.0
0.8
TEST POINTS < )C 2.0
0.8
DEVICE
UNDER
TEST
C'i
!> R,
231464-3 ~
A.C. Testing: Inputs are driven at 2.4V for a logic "'1" and 0.45V
-= 231464-4
for a logic ··0". Timing measurements are made at 2.0V for a
logic "'1" and O.BV for a logic "0" (unless otherwise noted). CL Includes Jig Capacitance
15-53
8224
WAVEFORMS
.... ~, -I 1---',
lev
L
., ,/
'-
\ :t
--, r --,
., I----- '0,
,~ r-
'"
~~ '0,
,
- r- tO <,>2 t 04l2 -
+ -t
SYNC
(FROM 8080A ) \
-'", 'OSS '1'W-
----,
-c..J-
--.
1'------'
tORS--t
'01111
--------- r-------------------
;~
--------------if-
RDYINOR R~SIN
I-'O"~
READY OU T
-------------------
r- ------ --------------------
--tOR_
RESET OU T --
231464-5
VOLTAGE MEASUREMENT POINTS: <1>" <1>2 logic "0" 1.0V, logic "1" ~ B.OV. All othor signals measured at 1.5V.
CLOCK HIGH AND LOW TIME (USING X1, X2)
Xl elK
l8MHz 0-r
X2
R, R2
":"
-=- 231464-6
15-54
8228
SYSTEM CONTROLLER AND BUS DRIVER
FOR 8080A CPU
• Single Chip System Control for
MCS®-SO Systems • Vector
User Selected Single Level Interrupt
(RST 7)
• Built-In Bidirectional Bus Driver for
Data Bus Isolation
• - Standard Temperature Range
Available in EXPRESS
• Instructions
Allows the Use of Multiple Byte
(e.g. CALL) for Interrupt • Available in 2S-Lead Cerdip and Plastic
Packages
Acknowledge (See Packaging Spoc, Order. # 231369)
• Reduces System Package Count
. The Intel® 8228 is a single chip system controller and bus driver for MCS''''-BO, It generates all signals required
to directly interface MCS-80 family RAM, ROM, and I/O components. .
A bidirectional bus driver is included to provide high system TTL fan-out. It also provides isolation of the 8080
data bus froni memory and I/O. This allows for the optimization of control signals, enabling the systems
designer to use slower memory and I/O. The isolation of the bus driver also provides for enhanced system
noise immunity.
A user selected single level interrupt vector (RST 7) is provided to simplify real time, interrupt driven, small
system requirements. The 8228 also generates the correct control signals to allow the use of multiple byte
instructions (e.g., CALL) in response to an interrupt acknowledge by the 1l0BOA. This feature permits large,
interrupt driven systems to have an unlimited number of interrupt levels.
The 8228 is designed to support a wide variety of system bus structures and also reduce system package
count for cost effective, reliable design of MCS-80 systems.
NOTE:
The specifications for the 3228 are identical with those for the 8228.
CPU
DATA.
BUS fDO -
0,_
Dz -
0,_
0,_
°4-
0,-
0,_
_OBI
-DBOl
- D B1
:= ~:~
- DB!,!
-oB6
-DB,
SYSTEM DATA BUS
III ~
~LATCH
STATUS
GATING
ARRAV
STSTB ---~-------' 231465-2
DB'N - - - - - - - - - - - - - - 1
WA--------------<1
-1
HLOA _ _ _ _ _ _ _ _ _ _ _ _ _ 07-00 Data Bus (8080 Side) INTA Interrupt Acknowledge
087·DBO Data Bus (System Side) HLCA HLDA (from 8080)
IIOR IICRead WR WR (from B080)
231465-1
IIOW 110 Write .GSEIl Bus Enable Input
Figure 1. Block Diagram ~ Memory Aead STSTIl Status Strobe (from 8224)
MEtlW Memory Write Vee +5V
DBIN OBIN (from 8080) GNO o Veils
Figure 2. Pin Configuration
September 1987
15-55 Ordor Number: 231465-002
8228
ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. The specifi-
cations are subject to change without notice.
Temperature Under Bias ............ O°C to + 70°C
• WARNING: Stressing the device beyond the "Absolute
Storage Temperature .......... - 65°C to + 150°C Maximum Ratings" may cause permanent damage.
Supply Voltage, Vcc ............... -0.5Vto +7V These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and ex-
Input Voltage ...................... -1.5 to + 7V tended exposure beyond the "Operating Conditions"
Output Current .......................... 100 mA may affect device reliability.
D.C. CHARACTERISTICS TA = O°C to + 70°C, Vec = 5V ± 5%
Limits
Symbol Parameter Unit Test Conditions
Min Typ(1) Max
Ve Input Clamp Voltage, 0.75 -1.0 V Vee = 4.75V; Ie = -5mA
All Input
IF Input Load Current STSTB 500 ).LA Vee = 5.25V
02&06 750 ).LA VF = 0.45V
--
00,01,04, 250 ).LA
05&07
All Other Inputs 250 ).LA
IR Input Leakage Current STSTB 100 ).LA Vee = 5.25V
- VR = 5.25V
DBo-OB7 20 ).LA
--
Ali Other Inputs _. 100 ).LA
VTH Input Threshold O.B 2.0 V Vee = 5V
Voltage, All Inputs
Icc Power Supply Current 140 190 mA Vee = 5.25V
VOL Output Low Voltage 00- 0 7 0.45 V Vee = 4.75V; IOL = 2 mA
All Other Outputs 0.45 V IOL=10mA
VOH Output High Voltage 00- 0 7 3.6 3.8 V Vee = 4.75V; 10H = -10).LA
All Other Outputs 2.4 V 10H = -1 mA
los Short Circuit Current, All Outputs - 15 90 mA Vee = 5V
10 (all) Off State Output Current 100 ).LA Vee = 5.25V; Vo = 5.25V
All Control Outputs
-100 ).LA Vo = 0.45V
liNT INTA Current 5 mA (See INTA Test Circuit)
NOTE:
1. Typical values are for TA = 25°C and nominal supply voltages.
15-56
inter 8228
CAPACITANCE VSIAS = 2.5V, Vee = 5.0V, TA = 25DC, f = 1 MHz
1. This parameter is periodically sampled and not 100 % tested.
Limits
Symbol Parameter Unit
Min Typ(1) Max
CIN Input Capacitance 8 12 pF
COUT Output Capacitance 7 15 pF
Control Signals
I/O I/O Capacitance 8 15 pF
(0 or DB)
A.C. CHARACTERISTICS T A = ODC to + 70DC, Vee = 5V ± 5%
Limits
Symbol Parameter Unit Conditions
Min Max
tpw Width of Status Strobe 22 ns
tss Setup Time, Status Inputs 00-07 B ns
tSH Hold Time, Status Inputs 00-07 5 ns
toe Delay from STSTB to any Control Signal 20 60 ns CL = 100 pF
tRR Delay from DBIN to Control Outputs 30 ns CL = 100 pF
tRE Delay from DBIN to Enable/Disable 8080 Bus 45 ns CL = 25pF
tRo Delay from System Bus to 8080 Bus during Read 30 ns CL = 25 pF
tWR Delay from WR to Control Outputs 5 45 ns CL = 100 pF
tWE Delay to Enable System Bus DBo-DB7 after STSTB 30 ns CL = 100 pF
two Delay from 8080 Bus 00-07 to System Bus 5 40 ns CL= 100pF
DBo-DB7 during Write
tE Delay from System Bus Enable to System Bus DBo-DB7 30 ns CL - 100 pF
tHO HLDA to Read Status Outputs 25 ns
tos Setup Time, System Bus Inputs to HLDA 10 ns
tOH Hold Time, System Bus Inputs to HLDA 20 ns CL = 100 pF
AC TESTING LOAD CIRCUIT INTA Test Circuit (for RST 7)
+12V
"""Vcc
lKO±l0"f0
R,
DEVICE
UNDER
TEST
< R,
8228
231465-3
For Do-D7; R1 ~ 4 Kn, R2 ~ con, CL ~ 25 pF.
23
For all other outputs: R1 ~ 500n, R2 ~ 1 Kn, CL ~ 100 pF. INTAP------.....I
231465-4
15-57
8228
WAVEFORMS
.,
STATUS STROBE
~-----'
-
I'-
Ipw"-
lOla DATA BUS )I(
IS~I= '*
-IS;.!
DBIN
INTA. lOR. MEMR
i
I~
\.
--j 'RR r-
IDe-
HLDA
iiii'A. lOR. iiEiiR
DURINGHLDA \
- I_'HD
A'
J:-'DS- -'DH..:j
- - -i-1\D.I- ~ -------------
-------- ---k
SYSTEM BUS DURING READ
-- - -- - -- - - - - - - - - - - - --
8010 BUS DURING READ ------,-- - I- - - - f«"'""'x " --------------
'R'- I=-
\ 1
'WR~ .1- .-;.II-IWR
iowOR MEMW
). 1
--- _.. - - --
--------- ==~
t=
8080 BUS DURING WRITE
SYSTEM BUS DURING WRITE - - - - - - - - - < 'WDj
-'WE-
SYSTEM BUS ENABLE
SYSTEM BUS OUTPUTS
----~----------<
j'~I->--------------
"-
231465-5
VOLTAGE MEASUREMENT POINTS: Do-D7 (when outputs) Logic "0" = O.BV. Logic "1" = 3.0V. Ail other signals mea-
'sured at 1.5V. '
15-58
8755A
16,384-BIT EPROM WITH 1/0
• Single
2048 Words x 8 Bits
• Each
2 General Purpose 8-Bit Ports 1/0
• Directly+Compatible
5V Power Supply (Vce)
• Programmable as Input or Output
Port Line Individually
1/0
• U.V. Erasable and Electrically
• Reprogrammable
with 8085AH
. Multiplexed Address and Data Bus
• 40-Pin DIP
• Internal Address Latch • -Available in EXPRESS
Standard Temperature Range
- Extended Temperature Range
The Intel 8755A is an erasable and electrically reprogrammable ROM (EPROM) and I/O chip to be used in the
8085AH microprocessor systems. The EPROM portion is organized as 204B words by 8 bits. It has a maximum
access time of 450 ns to permit use with no wait statos ill an 8085AH CPU.
The I/O portion consists of 2 general purpose I/O ports. Each I/O port has 8 port lines, and each I/O port line
is individually programmable as input or output.
PROt; liND CE, vee
ClK. CE 2 PB,
ClK PB G
READY RESET PBs
vDO PB 4
ADo_,
READY PB 3
101M PB 2
G
A8-,o lOR PB,
AD PB o
CE2
2K x 8 PA,
EPROM lOW
101M
ALE PA G
ALE
G
ADo PA 5
AD AD, PA 4
lOW
AD2 PA 3
RESET AD3 PA 2
lOR AD4 PA,
ADs PAo
PROG/CE, ~VCC(+5VI· AD. A,o
VOD--~-.J Vss (OVI AD, Ag
231735-1 vss A8
Figure 1. Block Diagram 231735-2
Figure 2. Pin Configuration
November 1986
15-59 Order Number: 231735-002
inter 8755A
Table 1. Pin Description
Symbol Type Name and Function
ALE I ADDRESS LATCH ENABLE: When Address latch Enable goes high, ADo-7'
101M, As-,o, CE2, and CE, enter the address latches. The signals, (AD, 101M,
ADs-,o, CE2, CEll are latched in at the trailing edge of ALE.
ADo_7 I BIDIRECTIONAL ADDRESSIDATA BUS: The lower 8 bits of the PROM or liD
address are applied to the bus lines when ALE is high.
During an liD cycle, Port A or B is selected based on the latched value of ADo.
IF RD or lOR is low when the latched Chip Enables are active, the output
buffers present data on the bus.
ADs_,o I ADDRESS BUS: These are the high order bits of the PROM address. They do
not affect liD operations.
PROG/CE, I CHIP ENABLE INPUTS: CE, is active low and CE2 is active high. The 8755A
CE2 can be accessed only when both Chip Enables are active at the time the ALE
signal latches them up. If either Chip Enable input is not active, the ADo_7' and
READY au puts will be in a high impedance state. GE, is also used as a
programming pin. (See section on programming.)
101M I 1/0 MEMORY: If the latched 101M is high when RD is low, the output data
comes from an liD port. If it is low the output data comes from the PROM.
RD I READ: If the latched Chip Enables are active when RD goes low, the ADo_7
output buffers are enabled and output either the selected PROM location or
110 port. When bothHIJ and lOR are high, the ADo_7 output buffers are 3-
stated.
lOW I I/O WRITE: If the latched Chip Enables are active, a Iowan lOW causes the
output port pointed to by the latched value of ADo to be written with the data on
ADo-7. The state of 101M is ignored.
ClK I CLOCK: The ClK is used to force the READY into its high impedance state
after it has been forced low by CE, low, CE2 high, and ALE high.
READY 0 READY is a 3-state output controlled by CE" CE 2, ALE and ClK. READY is
forced low when the Chip Enables are active during the time ALE is high, and
remains low until the rising edge of the next ClK. (See Figure 6c.)
PAO-7 liD PORT A: These are general purpose 110 pins. Their input/output direction is
determined by the contents of Data Direction Register (DDR). Port A is
selected for write operations when the Chip Enables are active and lOW is low
and a 0 was previously latched from ADo, AD,.
Read Operation is s~ected ~either lOR low and active Chip Enables and ADo
and AD, low, or 101M high, RD low, active Chip Enables, and ADo and AD,
low.
PBO-7 110 PORT B: The general purpose 110 port is identical to Port A except that it is
selected by a 1 latched from ADo and a 0 from AD1.
RESET I RESET: In normal operation, an input high on RESET causes all pins in Ports A
and B to assume input mode (clear DDR register).
lOR I 1/0 READ: When the Chip Enables are active, a Iowan lOR will output the
selected 1/0 port onto the AD bus. lOR low performs the same function as the
combination of 101M high and RD low. When lOR is not used in a system, lOR
should be tied to Vee ("1 ").
Vee POWER: + 5V supply.
Vss GROUND: Reference.
VDD POWER SUPPLY: VDD is a programming voltage, and must be tied to Vee
when the 8755A is being read.
For programming, a high voltage is supplied with VDD = 25V, typical. (See
section on programming.)
15-60
inter 8755A
FUNCTIONAL DESCRIPTION A port can be read out when the latched Chip En-
ables are active and either RD goes low with 10/M
high, or lOR goes low. Both input and output mode
PROM Section bits of a selected port will appear on lines ADo-7.
The 8755A contains an 8-bit address latch which To clarify the function of the I/O Ports and Data Di-
allows it to interface directly to MCS®-48 and rection Registers, the following diagram shows the
MCS®-85 processors wiHlout additional hardware. configuration of one bit of PORT A and DDR A. The
same logic applies to PORT Band DDR B.
The PROM section of tho chip is addressed by the
11-bit address and the Chip Enables. The address,
CE1 and CE2 are latched into the address latches on 8755A ONE BIT OF PORT A AND DDR A
the falling edge of ALE. If tho latched Chip Enables
are active and 10/M is low when RD goes low, the
contents of the PROM location addressed by the
latched address are put out on the ADO_7 lines (pro-
vided that Voo is tied to Vc;e;).
1/0 Section
The I/O section of the chip is addressed by the
latched value of ADo-1. Two B-bit Data Direction WRITE DQR A
Registers (DDR) in 8755A determine the input/out-
put status of each pin in the corrosponding ports. A DO
"0" in a particular bit position of a DDR signifies that ~
the corresponding I/O port bit is in the input mode. A REAO PA
"1" in a particular bit position siDnifies that the corre- 231735-3
WRITE PA = (lOW" 0) • (CHIP ENABLES ACTIVE) • (PORT A
sponding I/O port bit is in the output mode. In this ADDRESS SELECTED)
manner the I/O ports of the B7!i5i\ are bit-by-bit pro- WRITE DDR A = (lOW'" 0)· (CHIP ENABLES ACTIVE) • (DDR
grammable as inputs or outputs. The table summa- A ADDRESS SELECTED)
READ PA = i(lO/M " 1) • (RD = 0) + (lOR cO)} • (CHIP
rizes port and DDR designation. DDR's cannot be ENABLES ACTIVE) • (PORT A ADDRESS SELECTED)
read.
NOTE:
-- Write PA is not qualified by 101M.
AD1 ADo Selection
0
0
0
1
PortA
Port B
Note that hardware RESET or writing a zero to the
DDR latch will cause the output latch's output buffer . .
~
1 0 Port A Data Direction Register (DDR A) . to be disabled, preventing the data in the Output
1 1 Port B Data Direction Register (DDR B) Latch from being passed through to the pin. This is
equivalent to putting the port in the input mode. Note
When lOW goes low and the Chip Enables are ac- also that the data can be written to the Output Latch
tive, the data on the ADO-7 is written into I/O port even though the Output Buffer has been disabled.
selected by the latched value of ADo-1. During this This enables a port to be initialized with a value prior
operation all I/O bits of the selected port are affect- to enabling the output.
ed, regardless of their I/O mode and the state of 10/
M. The actual output level does not change until The diagram also shows that the contents of PORT
lOW returns high. (Glitch free output.) A and PORT B can be read even when the ports are
configured as outputs.
15-61
inter 8755A
ERASURE CHARACTERISTICS SYSTEM APPLICATIONS
The erasure characteristics of the 8755A are such
that erasure begins to occur when' exposed to light System Interface with 8085AH
with wavelengths shorter than approximately 4000
Angstroms (A). It should be noted that sunlight and A system using the 8755A can use either one of the
certain types of fluorescent lamps have wavelengths two 1/0 Interface techniques:
in the 3000-4000A range. Data show that constant • Standard 1/0
exposure to room level fluorescent lighting could • Memory Mapped 110
erase the typical 8755A in approximately 3 years
while it would take approximately 1 week to cause If a standard 1/0 technique is used, the system can
erasure when exposed to direct sunlight. If the use the feature of both CE2 and CE1. By using a
8755A is to be exposed to these types of lighting combination ot' unused address lines A ll - 15 and the
conditions for extended periods of time, opaque la- Chip Enable inputs, the 8085AH system can use up
bels are available from Intel which should be placed to 5 8755A's without requiring a CE decoder. See
over the 8755A window to prevent unintentional era- Figure 4.
sure.
If a memory mapped 110 approach is used the
The recommended erasure procedure for the 8755A 8755A will be selected by the combination of both
is exposure to shortwave ultraviolet light which has a the Chip Enables and 101M using ADs-15 address
wavelength of 2537 Angstroms (A). The integrated lines. See Figure 3.
dose (i.e., UV intensity x exposure time) for erasure
should be a minimum of 15W-sec/cm2. The erasure
time with this dosage is approximately 15 to 20 min- r---
utes using an ultraviolet lamp with a 12000 /J-W/cm?' A
power rating. The 8755A should be placed within A8-15
one illch from the lamp tubes during erasure. Some ; ~
lamps have a filter on their tubes and this filter ADo.,
should be removed before erasure.
8085AH
~lE
.
iili t--
i'ffi t--
PROGRAMMING elK f~~21
t--
READY
t--
Initially, and after each erasure, all bits of the t--
101M
t-- ..1
EPROM portions of the 8755A are in the "1" state.
Information is introduced by selectively program-
ming "0" into the desired bit locations. A pro- ------ VI"
iOn
7"
A/Du_7 A...,D RD elK
I 101M
ALE ilIW READY fE
grammed "0" can only be changed to a "1" by UV
erasure. 8755A
The 8755A can be programmed on the Intel Univer- 231735-4
sal Programmer (iUP), and iUPF8744A programming
module. Figure 3. 8755A In 8085AH System
(Memory-Mapped 110)
The program mode itself consists of programming a
single address at a time, giving a single 50 msec
pulse for every address. Generally, it is desirable to
have a verify cycle after, a program cycle for the
same address as shown in the attached timing dia-
gram. In the verify cycle (i.e., normal memory
read cycle) 'Voo' should be at + 5V.
15-62
cl
"1_15
AU Au I A"
T
Au
:-=t>
'"
." I"
..
AID~J
cO' " r- r- r- r- r-
e: 'I
III ALE
1085 AH
l- I-- I-- t-- I-
~ RO
CO I-- I-- l- I- I--
-...I
U"1
U"1
w-
el.K (~21
I- - I-- l- I-
» I- r- l- t-- I-
5' READY
I- - I-- 1-- I-
~
CO
Q
CO
U"1
101M
I- - l- I- l-
Q)
» ......
U"1
a,
w
:t
en
i i I en
en
'<
i :to
Vl
;
3 ,
)\ "Ie, , ~r .
}> v"
jf
.
7 7 7
~
I»
::s 1_lOR
AID~, A~" ALER.fieLKREADY"!Ji,II "ii,,,
iOii A/1I~, A~" AUR,ilrir' "READY i:R
1.':1-1
A~" ALEROlOw' "REAOY
10MtEl iiiR
""D~J
.~" AlEROiOw"KREADY10"', II I A/1I~,
,0. A~" RO "K 1011', I
.
tEl tIl Cl, AU Illii READY tEz
Co
I» 8155A 8755A B7~5A 8755A 8755A
(2K BYTESI (2K BVTES) :-.:. "l ~ E~ (:1:. SY"'ES: (2K BYTES)
Co
:::::: 231735-6
.9 NOTE:
Use CE 1 for the first 8755A in the system, and CE2 for the other 8755A's. Permits up to 5·8755A's in a system without CE decoder.
inter 8755A
ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. The specifi-
cations are subject to change without notice.
Temperature Under Bias ............ O°C to + 70°C • WARNING: Stressing the device beyond the "Absolute
Storage Temperature .......... -65°C to + 150°C Maximum Ratings" may cause permanent damage.
Voltage on any Pin These are stress ratings only. Operation beyond the
with Respect to Ground .. : ....... - 0.5V to + 7V "Operating Conditions" is not recommended and ex-
tended exposure beyond the "Operating Conditions"
Power Dissipation .......................... 1.5W may affect device reliability. '
D.C. CHARACTERISTICS
TA = O°C to 700C, Vee = Voo = 5V ±5%
Symbol Parameter Min Max Unit Test Conditions
VIL Input Low Voltage -0.5 0.8 V Vee = 5.0V
VIH Input High Voltage 2.0 Vee + 0.5 V Vee =5.0V
VOL Output Low Voltage 0.45 V IOL = 2mA
VOH Output High Voltage 2.4 V IOH = -400,...A
IlL Input Leakage 10 p,A Vss oS: VIN oS: Vee
ILO Output Leakage Current ±10 p,A 0.45V oS: VOUT oS: Vee
lee Vee Supply Curront 180 mA
100 Voo Supply Current 30 mA Voo = Vee
CIN Capacitance of Input Buffer 10 pF fe = 1,...Hz
CliO Capacitance of I/O Buffer 15 pF fe = 1,...Hz
D.C. CHARACTERISTICS-PROGRAMMING
TA= O°C to 70°C, Vee = 5V ±5%, Vss = OV, Voo = 25V ±1V
Symbol Parameter Min Typ Max Unit
Voo Programming Voltage (during Write to EPROM) 24 25 26 V
100 Prog Supply Current 15 30 mA
15-64
inter 8755A
A.C. CHARACTERISTICS
TA = O·C to 70·C, vcc = 5V ±5%
8755A
Symbol Parameter Unit
Min Max
tCYC Clock Cycle Time 320 ns
T1 ClK Pulse Width 80 ns
T2 ClK Pulse Width 120 ns
tt, tr ClK Rise and Fall Time 30 ns
tAL Address to latch Set Up Time 50 ns
tLA Address Hold Time after Lat~h 80 ns
tlC Latch to READ/WRITE Control 100 ns
tRD Valid Data Out Delay from READ Control' 170 ns
tAD Address Stable to Data Out Valid" 450 ns
tll latch Enable Width 100 ns
tRDF Data Bus Float after READ 0 100 ns
tCl READ/WRITE Control to latch Enable 20 ns
tcc READ/WRITE Control Width 250 ns
tow Data in Write Set Up Time 150 ns
-.
two Data in Hold Time after WRITE 30 ns
twp WRITE to Port Output 400 ns
tpR Port Input Set Up Time 50 ns
tRP Port Input Hold Time to Control 50 ns
tRYH READY HOLD Time to Control 0 160 ns
tARY ADDRESS (CE) to READY 160 ns
tRV Recovery Time between Controls 300 ns
tRDE READ Control to Data Bus Enable 10 ns
NOTES:
CLOAD = 150 pF.
'Or TAD - (TAL + T Le), whichever is greater.
"Defines ALE to Data Out Valid in conjunction with TAL.
A.C. CHARACTERISTICS-PROGRAMMING
TA =
= o·c to 70·C, Vcc 5V ±5%, Vss = OV, VDD = 25V ±1V
Symbol Parameter Min Typ Max Unit
tps Data Setup Time 10 ns
tpD Data Hold Time 0 ns
ts Prog Pulse Setup Time 2 IJ.s
tH Prog Pulse Hold Time 2 IJ.s
tpR Prog Pulse Rise Time 0.01 2 IJ.s
tpF Prog Pulse Fall Time 0.01 2 IJ.s
tpRG Prog Pulse Width 45 50 ms
15-65
inter 8755A
A.C. TESTING INPUT, OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT
u=x. >
0.45
2.0
0.8
.
TEST POINTS < . 2.0
0.8
x=231735-7
A.C. Testing: Inputs are driven at 2,4V for a Logic "1" and 0,45V
for a Logic "0". Timing Measurements ara made at 2.0V for a
CL
DEVICE
UNDER
=
TEST
150 pF
!fCl=150 PF
-=
231735-B
CL Includes Jig C[lpncitance
Logic "1" and O.BV for a Logic "0".
WAVEFORMS
CLOCK SPECIFICATION FOR 8755A
"
231735-9
PROM READ, 1/0 READ AND WRITE
A010 ADDRESS
101M
ADO·1 DATA
- - - -<\.__ A_D_DR_E_SS_-..J>-
ALE
eE,
--+l---Iow
231735-10
Please nole Ihal CE1 must remain low for the entire cycle.
15-66
8755A
WAVEFORMS (Continued)
1/0 PORT
~OR ~!'F-------! f.---+-
... tpR
tRP
"" _____ t
INPUT X""---
~________________________
DATA' - - - - - - - ')(
SUS _ _ _ _ _ _ _ ' - -_ _ _ _ _ _ _ _ __
231735-11
A. Input Mode
PORT ------------
\
OUTPUT _ _ _ _ _ _ _ _ _ _ _ _
'wP - is{
- / ow,"
OUTPUT " "
~~~A' =====)(___________X"-____ 231735-12
B. Output Mode
WAIT STATE (READY = 0)
•
231735-13
15-67
8755A
WA VEFORMS (Continued)
8755A PROGRAM MODE
FUNCTION
1.... . . . - - - - - - - - PROGRAM CYCLE ----~- .jl.......------
.... VERIFY CYCLE' ---1_ PROGRAM CYCLE
ALE
DATA TO BE
A/DO·7 PROGRAMMED
IpO
AB·l0
CEO
IpS
'25
Voo
.5-----------------------{
\J--
231735-14
'Verify cycle is a regular Memory Read Cycle (with VOO = + 5V for 8755A).
15·68
DOMESTIC SALES OFFICES
ALABAMA FLORIDA MICHIGAN OHIO VIRGINIA
Intel Corp. tlnlal Corp tlntel Corp. tlntel Corp. *
5015 Bradford Dr., #2 tlntel Corp.
80~ Fnirw:\y Drive 7071 Orchard Lake Road 3401 Park Center Drive
Huntsville 35805 9030 Stony Point Pkwy.
SUllo IGO Suite 100 Suite 220 Suite 360
Tel: (205) 830-4010 Deerliold Uuach 33441 West Bloomfield 48322 Dayton 45414
FAX: (205) 837-2640 Richmond 23235
Tel: (305) 421·0506 Tel: (313) 851-0096 Tel: (513) 890-5350 Tel: (804) 330-9393
FAX: (05)·I:?I·2444 FAX: (313) 851·8770 TWX: 810-450-2528 FAX: (804) 330-3019
ARIZONA FAX: (513) 890-8658
tlntel Corp. tlntol Corp.
MINNESOTA tlnlel Corp.*
410 North 44th Street 5850 T.G. Luo Blvd. WASHINGTON
Suito 3·10 25700 Science Park Dr
Suite 500 tin tel Corp.
Orlando 32822 Suite 100
Phoenix 85008 3500 W. 80th SI tlnlel Corp.
Tel: (·107) 240·8000 Beachwood 44122
Tel: (602) 231-0386 Suite 360 155 lOath Avenue N.E.
FAX: (407) 240·8097 Tel: (216) 464-2736
FAX: (602) 244-0446 Bloomington 55·1:\ I Suite 386
TWX: 810·427-9298
Tel: (612) 835·6,/;,;1 Bellevue 98004
Intel Corp. Intel Corp. FAX: (804) 282-0673
1WX: 910-576-2!HiI Tel: (206) 453-8086
7225 N. Mona Lisa Rd. 11300 4th Stroot North FAX: (612) B3HA'11 TWX: 910-443-3002
Suite 215 Suite 170 OKLAHOMA FAX: (206) 451-9556
Tucson 85741 51. Petersburg 33716
Tel: (602) 544-0227 Tel: (813) 577-2413 MISSOURI Intol Corp.
6801 N. Uroadway Intel Corp.
FAX: (602) 544-0232 FAX: (813) 578-1607 408 N. Mullan Road
tlntel Corp. SUI III It!)
4203 Earth City E~prl!:;:,way Okl,i!HHI\<I City 73162 Suite 102
CALIFORNIA Spokane 99206
GEORGIA Suite 131 Tel: (·lll~J) 1)48-8086
tlntel Corp. Earth City 63045 FAX' (.HEI) 840-9819 Tel: (509) 928-8086
21515 Vanowen Street tlntel Corp. Tel: (314) 291-1990 FAX: (509) 928-9467
Suite 116 20 Technology Parkway FAX: (314) 291-4341 OREGON
Canoga Park 91303 Suite 150
Norcross 30092 WISCONSIN
Tel: (818) 704-8500 NEW JERSEY 11I11t:! Corp.
FAX: (818) 340-1144 Tel: (404) 449-0541 . 1~J:>!.J·I N,W, Greenbrier Pkwy.
FAX: (404) 605-9762 Intel Corp.
tlntel Corp.* l3lJ1ldHIlI U
tlntel Corp. 330 S. Executive Dr.
Lincroft Office Center Uedvortoll g7006
300 N. Continental Blvd. Suite 102
ILLINOIS 125 Half Mile Road To1: (!.JOJ) G45·8051
Suite 100 Brookfield 53005
Red Bank 07701 TWX: 010·467-8741
EI Segundo 90245 Tel: (414) 784·8087
tlntel Corp.* Tel: (908) 747-2233 FAX: (SO:~) 645·8181
Tel: (213) 640-6040 FAX: (414) 796-2115
FAX: (213) 640-7133 Woodfield Corp. Center III FAX: (908) 747-0983
300 N. Martingale Road PENNSYLVANIA
Intel Corp. Suite 400 Intel Corp.
t Sierra Gate Plaza Schaumburg 60173 280 Corporate Center
75 Livingston Avenuo
tlnlel Carp."
925 Harvest Drive
CANADA
Suite 280C Tel: (708) 605-8031
Roseville 95678 First Floor Suite 200
FAX: (708) 706-9762
Tel: (916) 782-8086 Roseland 07068 Blue Bell 19422 BRITISH COLUMBIA
FAX: (916) 782-8153 Tel: (201) 740-0111 Tel: (215) 641-1000
INDIANA FAX: (201) 740-0626 FAX: (215) 641-0785 Intel Somiconductor of
tlntel Corp. Canada, Ltd.
9665 Chesapeake Dr. tlntel Corp. tlntel Corp. *
NEW YORK 400 Penn Center Blvd. 4585 Canada Way
Suite 325 8910 PUrdue Road
Suite 610 Suito 202
San Diego 92123 Suite 350 tntel Corp. * Pittsburgh 15235 Burnaby V5G 4L6
Tel: (619) 292-8086 Indianapolis 46268 850 Crosskeys Office Park Tel (412) 823-4970 Tel: (604) 298-0387
FAX: (619) 292-0628 Tel: (317) 875-0623 Fairport 14450 I AX (412) 829-7578 FAX: (604) 298-8234
FAX: (317) 875-8938 Tel: (716) 425-2750
tlntel Corp.*
400 N. Tustin Avenue TWX: 510-253-7391
FAX: (716) 223-2561 PUUlTO RICO ONTARIO
Suite 450 IOWA
Santa Ana 92705 rlJllql Corp.
Tel: (714) 835-9642 Intel Corp. tlnlel Corp.* tlntel Semiconductor of
:;(Hrtll Industrial Park
TWX: 910-595-1114 1930 SI. Andrews Drive N.E. 2950 Express Dr., South II 0, Bo)( 910 Canada, Ltd.
FAX: (714) 541-9157 2nd Floor Suite 130 2650 Queensview Drive
l;\:"; PI()(jras 00671
Cedar Rapids 52402 Islandia 11722 Suite 250
Tol: (BOg) 733·8616
tlntel Corp. * Tel: (319) 393-5510 Tel: (516) 231-3300 Ottawa K2B 8H6
San Tomas 4 TWX: 510-227-6236 Tel: (613) 829-9714
2700 San Tomas Expressway fAX: (516) 348-7939 TEXAS FAX: (613) 820-5936
2nd Floor KANSAS Intol Corp.
Santa Clara 95051 tlntel Corp. tlntel Semiconductor of
89~ 1 N. Capital of Texas Hwy.
Tel: (408) 986-8086 tlnlel Corp. 300 Westage Business Center Canada, Ltd.
Surte 4230
TWX: 910-338-0255 10985 Cody S1. Suite 230 190 Attwell Drive
Austin 78759
FAX: (408) 727-2620 Suile 140 Fishkill 12524 Suite 500
Overland Park 66210 Tel: (914) 897-3860 Tel: (512) 794-8086
Rexdale M9W 6H8
Tel: (913) 345·2727 FAX: (914) 897-3125 FAX: (512) 338-9335
COLORADO Tel: (416) 675-2105
FAX: (913) 345-2076 tlntel Corp.* FAX: (416) 675-2438
Intel Corp. Intel Corp. 12000 Ford Road
4445 Northpark Drive Seventeen State Street Suite 400
Suite 100 MA.RYLAND 14th Floor aUEBEC
Dallas 75234
Colorado Springs B0907 New York 10004 Tel: (214) 241-8087
Tel: (719) 594-6622 tlntel Corp." Tel: (212) 248-8086 tlntel Semiconductor of
10010 Junction Dr. FAX: (214) 484-1180
FAX: (303) 594-0720 FAX: (212) 248-0888 Canada, Ltd.
Suite 200 tlntel Corp." 1 Rue Holiday
tlntel Corp.* Annapolis Junction 20701 Suite 115.
600 S. Cherry S1. NORTH CAROLINA 7322 S.W. Freeway
Tel: (301) 206-2860 Suite 1490 Tour East
Suite 700 FAX: (301) 206-3677
Denver 80222 tlntel Corp, Houston 77074 Pt. Claire H9R 5N3
(301) 206-3678 . Tel: (713) 988-8086 Tel: (514) 694·9130
Tel: (303) 321-8086 5800 Executive Center Dr.
Suite 105 TWX: 910-881-2490 FAX: 514-694-0064
TWX: 910-931-2289
FAX: (303) 322-8670 MASSACHUSETTS Charlotte 28212 FAX: (713) 988-3660
Tel: (704) 568-8966
CONNECTiCUT tlntel Corp.* FAX: (704) 535-2236 UTAH
Westford Corp. Center
tlntel Corp. 3 Carlisle Road tlntel Corp. tlntel Corp.
301 Lee Farm Corporate Park 2nd Floor 5540 Centerview Dr. 428 East 6400 South
83 Woosler Heights Rd. Westford 01886 Suite 215 Suite 104
Danbury 06810 Tel: (508) 692-0960 Raleigh 27606 Murray 84107
Tel: (203) 748-3130 TWX: 710-343-6333 Tel: (919) 851-9537 Tel: (801) 263-8051
FAX: (203) 794-0339 FAX: (508) 692-7867 FAX: (919) 851-8974 FAX: (801)268·1457
tSales and Service Office
*Field Application Location
DOMESTIC DISTRIBUTORS
ALABAMA tArrow Electronics, fnc. tWyJe Distribution Group tPioneerfTechnologies Group, Inc.
2961 Dow Avenue 17872 Cowan Avenue 337 Northlake Blvd., Suite 1000
Arrow Electronics, Inc. Tustin 92680 Irvine 92714 Alta Monte Springs 32701
10t5 Henderson Road Tel: (714) 838·5422 Tol: (714) 863·9953 Tel: (407) 834·9090
Huntsville 35805 1WX: 910·595·2860 TWX: 910-371-7127 FAX: 407·834·0865
Tel: (205) 837·6955
FAX: 205·751-1581 Hamilton/Avnet Computer tWyle Distribution Group PioneerlTechnologies Group, Inc_
3170 Pullman Street 26677 W. Agoura Rd. 674 S. Military Trail
HamHton/Avnet Computer Costa Mesa 92626 Calabasas 91302 Deerfield Beach 33442
4930 I Corporate Drive Tel: (818) 880·9000 Tel: (305) 428·8877
Huntsville 35805 Hamilton/Avnet Computer TWX: 372·0232 FAX: 305-481-2950
1361 B West 190th Street
Hamilton/Avne! Electronics Gardena 90248
4940 Research Drive
COLORADO
Hamilton/Avnet Computer GEORGIA
Huntsville 35805 Arrow Electronics, Inc.
Tel: (205) 837·7210 4103 Northgate Blvd. 7060 South Tucson Way
Sacramento 95834 Arrow Commercial System Group
FAX: 205·721-0356 Englewood 80112 3400 C. Corporate Way
Hamilton/Avnet Computer. Tel: (303) 790·4444 DeJuth 30139
MTI Systems Sales
4950 Corporate Drive 4545 Viewridge Avenue Hamilton/Avnet Computer Tel: (404) 623·8825
Suite 120 San Diego 92123 9605 Maroon Circle, Ste. 200 FAX: (404) 623·8802
Huntsville 35806 Hamilton/Avnol Computer Engelwood 80112
Tel: (205) 830·9526 tArrow ElectroniCS, Inc.
1175 Bordeaux Drive tHamiiton/Avnet Electronics 4250 E. Rivergreen Parkway
FAX: (205) 830·9557 Sunnyvale 94089 9605 Maroon Circle Deluth 30136
PioneerfTcchnologies Group, Inc. Hamilton/Avnot Electronics Suite 200 Tel: (404) 497·1300
4825 U,niversity Square 21150 Califa Strcet Englewood 80112 rnx: 810·766·0439
Huntsville 35805 Woodland Hill~ \)1367 Tel: (303) 799·0663
Tel: (205) 837·9300 rnx: 910·935·0787 Hamilton/Avne! Computer
FAX: 205·837·9358 tHamUton/Avnf't Electronics 5825 D. Peachtree Corners E.
3170 Pullman Street tWyle Distribution Group Norcross 30092
Costa Mesa D?fi26 451 E. 124th Avonuo
ALASKA
Tel: (714) 6'1-4150 Thornton 80241 tHamilton/Avnet Electronics
Hamitton/Avns! Computer TWX: 910-595·2fi38 Tel: (303) 457·9953 S825 D Peachtree Corners
140D W. Benson Blvd., Suite 400 rnx: 910·936·0770 Norcross 30092
Anchorage 99503 tHamilton/Avnn! Electronics Tel: (404) 447·7500
1175 Borderlux Drive CONNECTICUT lWX: 810·766·0432
ARIZONA Sunnyvale 9400G
Tel: (408) 743·3300 tArrow Electronics, Inc
rloneerfTechnologies Group, Inc.
tArrow Electronics, Inc. rnx: 910·3399332 12 Beaumont Road
Wallingford 06492 3100 F Northwoods Place
4134 E. Wood Street Norcross 30071
Phoenix 85040 tHamiiton/Avnct Electronics Tel: (203) 265·7741
Tel: (602) 437·0750 4545 Ridgeview Avenue rnx: 710476·0162 Tol: (404) 448·1711
FAX: 404·446·8270
rnx: 910·951-1550 San Diego 92123
Tel: (619) 571·7500 Hamilton!Avnet Compll!l!r
Hamilton/Avne! Computer 1WX: 910·595·2638 Commerce Industrial f'.Irk
Commerce Drive ILLtNOIS
30 South McKemy Avenue
Chandler 85226 tHamilton/Avnet Electronics Danbury 06810
21150 Califa St. tArrow ElectroniCS, Inc.
Hamilton/A'met Computer Woodland Hills 91376 tHamilton/Avnet Electronics 1140 W. Thorndale
90 South McKemy Road Tel: (818) 594·0404 Commerce Industrial riHk Itasca 60143
Chandler 85226 FAX: 818·594·8233 Commerce Drive Tel: (708) 250·0500
Danbury 06810 1WX: 708·250·0916
tHamillon/Avnet EIBctronic~, tHamiiton/Avnct [I(~clronics Tel: (203) 797·2800
505 S. Madison Drive 10950 W. Washlrl r l1nn Blvd. 1WX: 710·456·9974 Hamilton/Avnet Computer
Tempe 85281 Culver City 202:lO 1130 Thorndale Avenue
Tel: (602) 231·5140 Tel: (213) 558-?·I~JO tPioneer/Standard Electronics
Bensenville 60106
rnx: 910·950·0077 TWX: 910-340-G:J(),1 112 Main Street
Norwalk 06851
tHamilton/Avnot Eloc1r()rI'C~ tHamllton/Avnet Electronics
Hamilton/Avne! Electronics Tel: (203) 853·1515 1130 Thorndale Avenue
30 South McKemy 1361B West 190th Strll!'! FAX: 203-838·9901
Gardena 90248 Bensenville 60106
Chandler 85226
Tel: (213) 217-6700 Tel: (708) 860·7780
Tel: (602) 961·6669 FLORIDA rnx: 708·860·8530
FAX: 602·961-4073 1WX: 910·340·6364
tArrow ElectroniCS, Inc.
Wyle Distribution Group tHamilton/Avnet Electronl>". 400 Fairway Drive MTI Systems Sales
4141 E. Raymond 4103 Northgate Blvd. Suite 102 1100 W. Thorndale
Phoenix 85040 Sacramento 95834 Deerfield Beach 3344 t Itasca 60143
Tel: (602) 249·2232 Tel: (916) 920·3150 Tel: (305) 429·8200 Tel: (708) 773·2300
1WX: 910·371-2871 PioneerfTechnologies Group, Inc. FAX: 305428·3991
tPioneer/Standard Electronics
134 Rio Robles tArrow ElectroniCS, Inc. 2171 Executive Dr., Suite 200
CAliFORNIA San Jose 95134 37 Skyline Drive Addison 60101
Arrow Commercial System Group Tel: (408) 954·9100 Suite 3101 Tel: (708) 495·9680
1502 Crocker Avenue FAX: 408·954·9113 Lake Marv 32746 FAX: 708·495·9831
Hayward 94544 Wyle Distribution Group Tel: (407) 323·0252
Tel: (415) 489·5371 124 Maryland Street F!IX: 407·323·3189
FAX: (415) 489·9393 EI Segundo 90254 INDIANA
Hamilton/Avnet Computer
Tel: (213) 322·8100 6801 NW. 15th Way
Arrow Commercial System Group fArrow Electronics, Inc.
14242 Chambers Road Wyle Distribution Group Ft. lauderdale 33309 7108 Lakeview Parkway West Drive
Tustin 92680 7431 Chapman Ave. Hamilton/Avnet Computer Indianapolis 46268
Tel: (714) 544·0200 Garden Grove 92641 3247 Spring Forest Road Tel: (317) 299·2071
FAX: (714) 731-8438 Tel: (714) 891·1717 St. Petersburg 33702 FAX: 317-299-0255
FAX: 714·891-1621
tArrow Electronics, Inc. tHamilton/Avnet Electronics Hamilton/Avnet Computer
19748 Dearborn Street tWyle Distribution Group 6801 NW. 15th Way 485 Gradle Drive
Chatsworth 91311 2951 Sunrise Blvd., Suite 175 Ft. Lauderdale 33309 Carmel 46032
Tel: (213) 701-7500 Rancho Cordova 95742 Tel: (305) 971'·2900
1WX: 910493·2086 Tel: (916) 638·5282 FAX: 305·971·5420 Hamilton/Avnet Electronics
tArrow Electronics, Inc. tWyle Distribution Group tHamilton/Avnet Electronics 485 GradJe Drive
9511 Ridgehaven Court 9525 Chesapeake Drive 3197 Tech Drive North Carmel 46032
San Diego 92123 San Diego 92123 St. Petersburg 33702 Tel: (317) 844·9333
Tel: (619) 565·4800 Tel: (619) 565·9171 Tel: (813) 573·3930 FAX: 317·844·5921
FAX: 619·279·8062 rnx: 910·335·1590 FAX: 813·572-4329
tPioneer/Standard Electronics
tArrow Electronics, Inc. tWyle Distribution Group tHamiiton/Avnet Electronics 9350 Priority Way
521 Weddell Drive 3000 Bowers Avenue 6947 University Boulevard West Drive
Sunnyvale 94086 Santa Clara 95051 Winter Park 32792 Indianapolis 46250
Tel: (408) 745·6600 Tel: (408) 727·2500 Tel: (407) 628·3888 Tel: (317) 573·0880
1WX: 910·339·9371 rnx: 408·988·2747 FAX: 407·678·1878 FAX: 317·573·0979
tCertified Technical Distributor
DOMESTIC DISTRIBUTORS (Contd.)
IOWA Hamilton/Avnet computer Hamilton/Avnet Computer tPioneer/Standard Electronics
2215 S.E. A-5 10 Industrial Road 60 Crossway Park West
Hamilton/Avnet Computer Grand Rapids 49508 Fail1ield 07006 Woodbury, Long Island 11797
915 33rd Avenue SW
Tel: (516) 921-8700
Cedar Rapids 52404 Hamilton/Avne! Computer tHamiiton/Avnet Electronics
FAX' 516-921-2143
41650 Garden Rd., Ste. 100 1 Keystono Avo., Bldg. 36
Hamilton/Avnet ElectroniCS Novi 48050 Cherry HIli 08003 tPloneer/Standf.,d Electronics
915 33rd Avenue, S.w. Tel: (609) 424·0t 10 840 Fairport Park
Cedar Rapids 52404 Hamllton/Avnet Electronics FAX: 609·751·2552 Fairport 14450
Tel: (319) 362-4757 2215 29th Street S.E.
Tel. (716) 381-7070
Space A5 tHamliton/Avrll)1 Eloctronlc', FAX: 716·361-5955
KANSAS Grand Rapids 49508 10 Indu~,trldl
Tel: (616) 243-6605 Fairfiold 070(H, NORTH CAROLINA
Arrow Electronics, Inc. FAX: 616-698-1831 Tol: (201) ~)7~·33!JO
8208 Melrose Dr., Suite 210
FAX: 20 I·~ 7S·5839 tAr row Electronics, Inc.
Lenexa 66214 Hamilton/Avne! Electronics 5240 Greensdairy Road
Tel: (913) 541-9542
FAX: 913-541-0328
41650 Garden Brook
Novi 48050
~~t;~~;~~I~~n5 Sales Raloigh 27604
Tel: (919) 876-3132
Tel: (313) 347-4271 Fairfield 07006 TWX: 510-928-1856
Hamilton/A'met Computer FAX: 313-347-4021 Tel: (201) 227-5552
15313 W. 95th Street FAX: 201-575-6336 Hamilton/Avnet Computer
Lenexa 61219 tPioneer/Standard Electronic; 3510 Spring Forest Road
4505 Broadmoor S.E. tPioneer/Standard Elecll('llll.·, Raleigh 27604
tHamllton/Avnet Electronics Grand Rapids 49508 14-A Madison Rd.
15313 W. 95th Tel: (616) 696-1800 tHamilton/Avnet Electronics
Fairfield 07006
Overland Park 66215
Tel: (913) 888-8900
FAX: 616-698-1831 Tel: (201) 575-3510 q
351 Spring Forest Dnve
FAX: 201-575·3454 Ralolgh 27604
FAX: 913-541-7951 tPioneer/Standard Electronics Tel: (919) 878-0819
13485 Stamford TWX: 510-928-1836
Livonia 48150 NEW MEXICO
KENTUCKY
Tel: (313) 525-1800 Attiance Electronics Inc PlonoerfTechnorogies Group, Inc.
Hamilton/Avnet Electronics FAX: 313-427-3720 940t L-Southern Pine Blvd.
805 A. Newtown Circle 10510 Research Avenu1J
Albuquerque 67123 Charlotte 28210
Lexington 40511 MINNESOTA Tal. (919) 527-8188
Tel: (606) 259-1475 Tel: (505) 292-3360
FAX: 505-292-6537 FAX: 704-522·8564
tArrow Electronics, Inc.
MARYLAND 5230 W. 73rd Street Hamilton/Avnet Computlil Pioneer Technologies Group, Inc.
Edina 55435 5659 Jefferson, N.E. SUlt1l'1 II . ; B 2010 Meridian Parkway
tArrow Electronics. Inc. Tel: (612) 830-1800 SUllo 148
8300 Guilford Drivo Albuquerque 87109
TWX: 910-576-3125 Ourh<lm 27713
Suite H, River Centor tHamilton/Avnet Electronic'. Tel: (010) 544-5400
Columbia 21046 Hamilton/Avnet Computer 5659A Jefferson N.E. FAX: 010-544-5885
Tel: (301) 995-6002 12400 Whitewater Drive Albuquerque 67109
FAX: 301-381-3854 Minnetonka 55343 Tel: (505) 765-1500 OHIO
Hamilton/Avne! Computer tHamiiton/Avnet Electronics FAX: 505-243-1395
Arrow Commercial System Group
6622 Oak Hall Lane 12400 Whitewater Drive 264 Cramer Creek Court
Cblumbia 21045 Minnetonka 55434 NEW YORK
Dublin 43017
Tel: (612) 932·0600 Tel: (614) 889-9347
tHamilton/Avnet Electronics tArrow Electronics, Inc.
TWX: 910-576-2720 FAX: (614) 889-9680
6822 Oak Hall Lane 3375 Brighton Henrietta TOWIIIIIIO lid
Columbia 21045 tPioneer/Standard Electronics Rochoster 14623
tArrow Electronics, Inc.
Tel: (301) 995-3500 7625 Golden Triange Dr. Tel: (716) 427-0300
6236 Cochran Road
FAX: 301-995-3593 Suite G TWX: 510-253-4766
Solon 44139
Eden Prairie 55343 Tel: (216) 248-3990
~~i3p!t~~~~~'~cio~~r8r. Tel: (612) 944-3355 Arrow Electronics, Inc.
20 OSOf Avenue TWX: 810·427-9409
FAX: 612-944-3794
Columbia 21046 Hauppauge 11768 Hamilton/Avne! Computer
Tel: (301) 290-8150 MISSOURI Tel: (516) 231-1000 7764 Washington Village Dr.
FAX: 301-290-6474 TWX: 510-227-6623 Dayton 45459
tArrow Electronics, Inc.
tPioneerfTechnologies Group, Inc. 2380 Schuetz Hamllton/Avnet Computer Hamillon/Avnot Computer
9100 Gaither Road SI. Louis 63141 933 Motor Parkway 30325 Bainbridge Rd., Bldg. A
Gaithersburg 20877 Tel: (314) 567-6888 Haupauge 11788 Solon 44139
Tel: (301) 921-0660 FAX: 314-567-1164
FAX: 301-921-4255 Hamilton/Avne! Computer tHamlllon/Avnet Electronics
Hamilton/Avnet Computer 2060 Townline 7760 Washington Village Dr.
MASSACHUSETIS 739 Goddard Avenue Rochester 14623 Dayton 45459
Chestel1ield 63005 tHamilton/Avnet Electromcs Tel: (513) 439-6733
Arrow Electronics, Inc. FAX: 513·439·6711
25 Upton Dr. tHamilton/Avnet Electronics 933 Motor Parkway
Wilmington 01887 741 Goddard Hauppauge 11768 tHamiiton/Avnet Electronics
Tel: (508) 658-0900 Chesterfield 63005 Tel: (516) 231-9800 30325 Bainbridge
TWX: 710-393-6770 Tel: (314) 537-1600 TWX: 510-224·6166 Solon 44139
FAX: 314·537·4248 tHamilton/Avnet Electronics Tel: (216) 349-5100
Hamilton/Avnet Computer TWX: 810-427-9452
10 0 Centennial Drive 2060 Townline Rd.
NEW HAMPSHIRE Rochester 14623
Peabody 01960 Hamilton/Avnet Computer
HamHton!Avnet Computer Tel: (716) 272-2744 777 Brooksedge Blvd.
tHamiiton/Avnet Electronics 2 Executive Park Drive TWX: 510-253-5470 Westerville 43081
100 Centennial Drive Bedford 03102 Tel: (614) 882-7004
Peabody 01960 Hamilton/Avnet Electronics
FAX: 614-882-8650
Tel: (508) 532-9838 Hamilton/Avnet Computer 103 Twin Oaks Drive
FAX: 508-596-7802 444 East Industrial Park Dr. Syracuse 13206 Hamilton/Avne! Electronics
Manchester 03103 Tel: (315) 437-0288 777 Brooksedge Blvd.
tPloneerfStandard Electronics TWX: 710·541-1560 Westerville 43081
44 Hartwell Avenue NEW JERSEY Tel: (614) 882-7004
Lexington 02173
Tel: (617) 861-9200 t Arrow Electronics, Inc. ~~~a~6~~e~~kSDI;;e MTI Systems Sales
FAX: 617-863-1547 4 East Stow Road Port Washington 11050 23400 Commerce Park Road
Unitt1 Tel: (516) 621-6200 Beachwood 44122
WyJe Distribution Group Marlton 06053 FAX: 510-223-0846 Tel: (216) 464-6688
15 Third Avenue Tel: (609) 596-8000
Burlington 01803 Pioneer/Standard Electronics tPloneerJStandard Electronics
FAX: 609-596-9632 68 Corporate Drive 4433 Interpoint Boulevard
Tel: (617) 272-7300
FAX: 617-272-6809 tArrow Electronics Binghamton 13904· Dayton 45424
6 Century Drive Tel: (607) 722-9300 Tel: (513) 236-9900
MICHIGAN Parsipanny 07054 FAX: 607·722·9562 FAX: 513-236-8133
Tel: (201) 538-0900 tPioneer/Standard Electronics
tArrow Electronics, Inc. Pioneer/Standard Electronics
FAX: 201-538-0900
19880 Haggerty Road 40 Osor Avenue 4800 E. 131 st Street
Livonia 48152 Hamilton/Avnet Computer Hauppauge 11767 Cleveland 44105
Tel: (313) 665-4100 1 Keystone Ave., Bldg. 36 Tel: (516) 231-9200 Tel: (216) 587-3600
TWX: 810-223-6020 Cherry Hill 08003 FAX: 510-227-9869 FAX: 216-663-1004
tCertifled Technical Distributor
DOMESTIC DISTRIBUTORS (Contd.)
OKLAHOMA Hamilton/Avnet Computer Hnmilton/Avnet Computer fArrow Electronics, Inc.
1807A West Braker Lane 17761 Northeast 78th Place 1093 Meyerside, Unit 2
Arrow Electronics, Inc. Austin 78758 Rodmond 98052 Mississauga l5T 1M4
4719 South Memorial Dr. Tel: (416) 673-7769
Tulsa 74145 Hamilton/Avnet CompulOr tHnmilton/Avnet Electronics FAX: 416-672-0849
Forum 2 177Gl N.E. 78th Place
tHamilton/Avnet Electronics 4004 Beltline, Suilo 200 nodmond 98052 Hamilton/Avnet Computer
12121 E. 51st St., Suite lO2A Dallas 75244 Tnl: (206) 881-6697 Canada System Engineering
Tulsa 74146 I-AX: 206-867-0159 Group
Tel: (918) 252-7297 Hamilton/Avnet Computer 3688 Nashua Drive
4850 Wright Ad .. Suite 190 Wyle Distribution Group Units 7 & 8
OREGON Stafford 77477 l!.o305 N.E. 90th Street Mississuaga L4V 1M5
nl'drnond 98052
tAlmac Electronics Corp. tHamilton/Avnel [Iectronics T,'I (206) 881-1150 Hamilton/Avnet Computer
1685 NW. 1691h Place 1807 W. Braker Lane rAX: 206-881-1567 3688 Nashua Drive
Beaverton 97005 Austin 78758 Units 9& 10
Tel: (503) 629-8090 Tel: (51~) 837-8'''' WISCONSIN Mississuaga L4V 1M5
FAX: 503-645-0611 TWX: 910-874-1:ll!)
Hamilton/Avnet Computer
Arrow Electronics, Inc.
Hamifton/Avnet Computer tHamiiton/Avnet [11~ctronics 6845 Rexwood Road
200 N. Patrick Blvd., Ste. 100
9409 Southwest Nimbus Ave. 4004 Beltline, SWill 200 Units 7, 8, & 9
Brookfield 53005 Mississuaga L4V 1R2
Beaverton 97005 Dallas 75234 Tel: (414) 792-0150
tHamilton/Avnet Electronics Tel: (214) 308-8' " FAX: 414-792-0156 Hamihon/Avnet Computer
lWX: 910-860-5~1:,q 190 Colonade Road
9409 S.W. Nimbus Ave.
Hamilton/Avnet Computer Nepean K2E 7J5
Beaverton 97005 tHamiJton/Avne! rillctronics 20875 Crossroads Circle
Tel: (503) 627-0201 4850 Wright Rd .. ~;lJIte 190 tHamilton/Avnet Electronics
FAX: 503-641-4012 Suite 400
Stafford 77477 Waukesha 53186 6845 Rexwood Road
Tel: (713) 240·7/:!:1 Units 3-4-5
Wyle
9640 Sunshine Court TWX: 910-881·!/,:'J tHamilton/Avnet Electronics Mississauga L4T 1R2
Bldg. G, Suito 200 28875 Crossroads Circle Tel: (416) 677-7432
tpioneer/Stand.I!lt Electronics Suite 400
Beaverton 97005 FAX: 416-677-0940
1826-0 Kramer Waukesha 53186
Tel: (503) 643-7900 Austin 78758 tHamllton/Avnet Electronics
FAX: 503·646·5466 Tel: (414) 784-4510
Tel: (512) 835 -woo FAX: 414-784-9509 190 Colonnade Road South
FAX: 512-835·!III:'~j Napean K2E 7L5
PENNSYLVANIA Tel: (613) 226-1700
tPioneer/Stand.lrtl Electronics FAX: 613-226-1184
Arrow Electronics, Inc. 13710 Ome~p Ho:Jd CANADA
650 Seco Road Dallas 75244 tZentronics
Monroeville 15146 Tel: (214) 381; ':100 ALBERTA 1355 Meyerside Drive
Tel: (412) 856-7000 FAX: 214-490 1;·119 Mississauga L5T 1C9
Hamilton/Avnet Complilcr Tel: (416) 564-9600
Hamilton/Avnet Computer tPioneer/SI.lrHt.lrd Electronics 2816 21st Street Nortlll'.J~,1 FAX: 416-564-8320
2800 Uberty Ave .. Bldg. E 10$30 Rockloy noad Cal gal}' T2E 622 tZentronics
Pittsburgh 15222 Houston 770~):)
Tel: (713) 4%·4700 Hamilton/Avnet ElcclrIHlrc::; 155 Colonnade Road
Hamilton/Avne1 Electronics Unit 17
FAX: 713·4%·5642 2816 21st Street N.E II~I
2800 Uberty Ave. Nepean K2E 7Kl
Calgary T2E 6Z3
Pittsburgh 15238 tWyle Distribution Group Tel: (613) 226-8840
Tol: (412) 281-4150 Tel: (403) 230-3586
1810 Greonville Avenue FAX: 403-250-1591 FAX: 613-226-6352
Pioneer/Standard Electronics Richardson 75081
Tel: (214) 235-9953 Zentronics aUEBEC
259 Kappa Drive
Pittsburgh 15238 FAX: 214·644-5064 6815 #8 Street N.E. Arrow Electronics Inc.
Tel: (412) 782-2300 Suite 100 1100 St. Regis
FAX: 412-963-8255 UTAH Calgal}' T2E 7H Dorval H9P 2T5
Tel: (403) 295-8818 Tel: (514) 421-7411
tPioneer/Technologies Group, Inc. Hamilton/Avne! Computer FAX: 403-295-8714 FAX: 514-421-7430
Delaware Valley 1585 West 2100 South
261 Gibralter Road Salt Lake City 84119 BRITISH COLUMBIA Arrow ElectroniCS, Inc.
Horsham 19044 500 Boul. SI-Jean-Baptiste
Tel: (215) 674-4000 tHamilton/Avnet Electronics tHamllton/Avnet Electronics Suite 260
FAX: 215-674-3107 1585 West 2100 South 8610 Commerce Ct. Quebec G2E 5R9
Sail Lake City 84119 Burnaby V5A 4N6 Tel: (418) 871-7500
TENNESSEE Tel: (801) 972-2800 Tel: (604) 420-4101 FAX: 418-871-6816
TWX: 910-925-4018 FAX: 604-437-4712
Arrow Commercial System Group Hamilton/Avnet Computer
3635 Knight Road tWyle Distribution Group Zentronics 2795 Rue Halpern
Suite 7 1325 West 2200 South 108-11400 Bridgeport Road St. Laurent H4S 1P8
Memphis 38118 Suite E Richmond V6X 1T2 tHamilton/Avnet Electronics
Tel: (901) 367-0540 West Valley.84119 Tel: (604) 273-5575 2795 Halpern
FAX: (901) 367-2081 Tel: (801) 974-9953 FAX: 604-273-2413 St. Laurent H2E 7Kl
Tel: (514) 335-1000
TEXAS WASHINGTON ONTARIO FAX: 514-335-2481
Arrow Electronics, Inc. tAlmac Electronics Corp. Arrow Electronics, Inc. tZentronics
3220 Commander Drive 14360 S.E. Eastgate Way 36 Antares Dr., Unit 100 520 McCaffrey
Carrollton 75006 Bellevue 98007 Napean K2E 7W5 81. Laurent H4T 1N3
Tel: (214) 380-6464 Tel: (206) 643-9992 Tel: (613) 226-6903 Tel: (514) 737-9700
FAX: (214) 248-7208 FAX: 206-643-9709 FAX: 613-723-2018 FAX: 514-737-5212
tCertified Technical Distributor
EUROPEAN SALES OFFICES
FINlAND ITALY SWEDEN UNITED KINGDOM Intel GmbH
Abraham Lincoln Strasse 16-18
Intel Finland QY In~el Corporation !talia S,pA
Ruasilantie 2 Mllanoflorl PalaZlo E
Intel Sweden A.B. ~~~r~Wa~ration (U.K.) Ltd. 6200 Wiesbaden
Dalvagen 24 Tel: (49) 06121/7605-0
00390 Helsinki 20094 A:;~,3g0
171 36 Solna Swindon, Wiltshire SN3 lRJ TLX: 4-186183
Tel: (358) 0 544644 Milano Tel: (46) 8 734 01 DO Tel: (44) (0793) 696000
TLX: 123332 Tel: (3g) (02) 89200950 TLX: 12261 TLX: 444447/8 Intel GmbH
TLX: 3·11 n16 Zenachring lOA
FRANCE 7000 Stuttgart 80
Intel Corporation SAA.l. NETHERlANDS SWITZERLAND WEST GERMANY Tel: (49) 0711/7287-280
1, Rue Edison-BP 303 TLX: 7-254826
Intel StJflllCOnduclor B.V. Intel Semiconductor A.G. Intel GmbH
78054 St. Quentin-on·Yvolinos
Cedex PoslulJ:; B4130 Zuerichstrasse Oornacher Strasse 1
Tel: (33) (1) 30 57 70 00 3099 CC Hotlordam 8185 Winkel·Rueti bei Zuerich 8016 Foldkirchen bei Muenchen
Tel: PI) 10.407.11.11 Tel: (41) 01/860 62 62 Tel: (49) 089/90992-0
TLX: 699016 TLX: :}:);}03 TLX: 825977 FAX: (49) 089/904/3948
ISRAEL
SPAIN
Intel Semiconductor Ltd.
Atidim Industrial Park· Novo Sh.Jfot Intel aWlr.1 SA
P.O. Box 43202 ZUrb;H.lII. 20
Tel·Aviv 61430 28010 M.ldrid
Tel: (972) 03-498080 Tel: (:.l.\) (I) 308.25.52
TLX: 371215 TLX: ·\1,11110
EUROPEAN DISTRIBUTORS/REPRESENTATIVES
AUSTRIA IRELAtHi NORWAY UNIT[D KINGDOM Rapid Recall, Ltd.
28 High Street
Bacher Electronics G.m.b.H.
~ig~~;I(~·::.\r~e~fRc~t~ark
Nordisk Elektronikk (Norna) AJS Accent I I"f.tronic Components LId. Nantwich
Rotenmuehlgasse 26 Postboks 123 JUbrle'r II, "I:;e, Jubilee Road Cheshire CW5 5AS
1120 Wien Glen·IlI"·lry Smedsvingen 4 Letchwl!!lil. Herts SG6 10H Tel: (0270) 627505
Tel: (43) (0222) 83 56 46 Co. {)lJh~ln 1364 Hvalstad Tel: (4·1) (111Ii2) 670011 FAX: (0270) 629883
TLX: 31532 Tel: (:" I (353) (01) 856288 Tel: (47) (02) 84 62 III FAX: (H) ilJ.\(2) 682467 TWX: 36329
FAX: (:'11 (353) (01) 857364 TLX: 77546 TWX: e:'I.·,II')
BELGIUM TLX: :II:,l34
Bytech L"lllp"rrents Ltd.
Inelco Belgium SA PORTUGAL 12A CCtl.li"·""J(J WEST GER MANY
Av. des Croix de Guerre 94 ISRAEL Chinell~lIll Iltl·.'IH~:;5
Park
1120 Bruxelles ATD Portugal LOA Electronic 2000 AG
Easilorlll:s Ltd. Rua Dos Lusiados, 5 ~;,\I;I B Crockforil 1.11111
?l0~~i~~~~i:~nlaan, 94 11 RU/dllis Street 1300 Lisboa Basingstr ,\.0\ Stahlgruberring 12
8000 Muenchen 82
Hants R(;; '.\ (JWD
Tel: (32) (02) 216 01 60 P.O.G. :1~)300 Tel: (35) (1) 64 80 91 Tel: (49) 089/42001-0
TLX: 61562 Tel: (02~r.) {O/I07
TLX: 64475 or 22090 Tel·Avlv 61392 TLX: 522561
FAX: 02~,t, /(l/IG2
Tel: (n",! 03-475151
TLX: 3~E38 Oitram
DENMARK Conforml)( In Multikomponent GmbH
Avenida Miguel Bombard;l, 133
In-Multikomponent 1000 Lisboa Unit 5 Postfach 1265
ITALY Tel: (35) (1) 5453 13 A1M 8U~III(1~;:; Contre Sahnl10fstrasse 44
Naverland 29
TLX: 14182 Dixons Hill f10~1[J 7141 Moeglingen
2600 Glostrup Intest Welham Groon Tel: (49) 07141/4879
Tel: (45) (D) 2456645 Oivisione In Industries GmbH South Hallreld TLX: 7264472
TLX: 33 355 Viale Milanofiori SPAIN Herts AL9 7JE
Palazzo E/5 Tel: (07072) 73282 Jermyn GmbH
FINlAND ATD Electronica. SA
OY Fintronic AS ¥~~9(~~so~Pa~J~6)1 Plaza Ciudad de Viena, 6
FAX: (07072) 61678 1m Dachsstueck 9
6250 Limburg
Melkonkatu 24A TLX: 311351 28040 Madrid Bytech Systems
Tel: (34) (1) 23440 00 Tel: (49) 06431/508-0
00210 Helsinki 3 The Western Centre
Lasi Elettronica S.p.A. TLX: 42477 TLX: 415257·0
Te(: (358) (0) 6926022 Western Road
V.le Fulvio Testi. 126 BrackneU RG 12 1RW
TLX: 124224 Metrologia Iberica, SA Metrologie GmbH
20092 Cinisello Balsamo (MI) Tel: (44) (0344) 55333
~0~9Ji~~~~~~~~e7~9
Tel: (39) 02/2440012 Ctra. de Fuencarral, n.80 FAX: (44) (0344) 867270
FRANCE 28100 Alcobendas (Madrid)
TLX: 352040 TWX: 849624
Almex Tel: (34) (1) 653 86 11 Tel: (49) 089/78042-0
Zone industrielle d'Antony Teleam S,r.l. Jermyn TLX: 5213189
48, rue de \'Aubepine Via M. C;vitali 75 Vestry Estate
SWEDEN
BP 102 20148 Milano Otford Road Proelectron Vertriebs GmbH
92164 Antony cedex Tel: (39) 02/4049046 Nordisk Elektronik AB Sevenoaks Max Planck Strasse 1-3
Tel: (33) (1)46662112 TLX: 335654 Torshamnsgatan 39 Kent TN14 5EU 6072 Dreieich
TLX: 250067 Box 36 Tel: (44) (0732) 450144 Tel: (49) 06103/30434-3
In Multicomponents 16493 Kista FAX: (44) (0732) 451251 TLX: 417903
Jermyn Viale Milanofiori E/5 Tel: (46) 08-03 46 30 TWX: 95142
60, rue des Gemeaux 20090 Assago (MI) TLX: 10547
Silic 580 Tel: (39) 02/824701 MMD Ltd.
94653 Rungis Cedex TLX: 311351 YUGOSlAVIA
3 Bennet Court
Tel: (33) (1) 49 78 49 78 SWITZERlAND Bennet Road
TLX: 261585 Silverstar Reading H.R. Microelectronics Corp.
Via Dei Gracchi 20 Industrade A.G. Berkshire RG2 OOX 2005 de la Cruz Blvd., Sle. 223
Metrologie 20146 Milano Hertistrasse 31 Santa Clara. CA 95050
Tel: (44) (0734) 313232
Tour d'Asnieres Tel: (39) 02/49961 8304 Wallis ellen U.S.A.
FAX: (44) (0734) 313255
4, avo Laurent-Cely TLX: 332189 Tel: (41) (01) 8328111 Tel: (1) (408) 988-0286
TWX: 846669
92606 Asnieres Cedex TLX: 56788 TLX: 387452
Tel: (33) (1) 47906240 Rapid Recall, Ltd.
TLX: 611448 NETHERlANDS
TURKEY Rapid House Aapido Electronic Components
Tekelec-Airtronic Koning en Hartman Oxford Road S,p.a.
Cite des Bruyeres Elektrotechniek BV. EMPA Electronic High Wycombe Via C. Beccaria, 8
Rue Carle Vernet - BP 2 Energieweg 1 Lindwurmstrasse 9SA Buckinghamshire HP11 2EE 34133 Trieste
92310 Sevres 2627 AP Delft 8000 Muenchen 2 Tel: (44) (0494) 26271 Italia
Tel, (33) (1) 45347535 Tel, (31) (1) 15/609906 Tel: (49) 089/53 80 570 FAX: (44) (0494) 21860 Tel: (39) 040/360555
TLX: 204552 TLX: 38250 TLX: 528573 TWX: 837931 TLX: 460461
INTERNATIONAL SALES OFFICES
AUS'TlIALIA INOlA Intel Japan K.K.· SINGAPORE
Kawa-asa Bldg.
Intel Australia pty.ltd. Intel,Asia Electronics, Inc. 2-11·5 Shin-Yokohama Intel Singapore Technology. Ud.
Untt 13 4/2, Samrah Plaza Kohoku-ku, Yokohama-shi 101 Thomson Road #21-05/06
Allambie Grove Business Park St. Mark's Road Kanagawa, 222 United Squar~
25 Frenchs Forest Road East Bangalore 560001 Tel: 045-474-7661 Singapore 1130
Frenchs Forest, NSW. 2086 Tel: 011-91-812-215065 FAX: 045-471-4394 Tel: 250-7811
Tel: 61-2975-3300 TLX: 953-845-2646 INTL IN TLX: 39921 INTEL
FAX: 61-2975-3375 FAX: 091-812-215067 Intel Japan K.K.. FAX: 250-9256
Ryokuchi-Eki Bldg.
2-4-1 Terauchi
BRAZIL JAPAN Toyonaka-shi. Osaka 560 TAIWAN
Tel: 06-863-1091
Intel Semicondutores do Brazil LTDA Intel Japan K.K. FAX: 06-863-1084 Intel Technology Far East Ltd.
Av. Paulisla, 1159-CJS 404/405 5-6 Tokodai. Tsukuba-shi Intel Japan K.K 8th Floor, No. 205
01311 - Sao Paulo - S.P. (baraki,300-26 Shinmaru Bldg. Bank Tower Bldg.
Tel: 55-11-287-5899 Tel: 0298-47-8511 Tung Hua N. Road
TLX: 39111531461SDB 1-5-1 Marunouchi
TLX: 3656-160 Chiyoda-ku, Tokyo 100 Taipei
FAX: 55-11-287-5119 FAX: 0298-47-8450 Tel: 886-2-716-9660
Tel: 03-201-3621
FAX: 03-201-6850 FAX: 886-2-717-2455
CHINA/HONG KONG ~~~~~r~~~g~i~ld9. Intel Japan K.K.
1-8889 Fuchu-ctlo Green Bldg.
Intel PRC Corporation Fuchu-shi. Tokyo 183 1-16-20 Nishiki
15/F, Office 1, Cilie Bldg. TeJ: 0423-60-7071 Naka-ku. Nagoya-shi
Jian Guo Men Wai Street FAX: 0423-60·0:l15 Aichi 450
Beijing, PAC Tel: 052-204-1261
Tel: (1) 500-4850 Intel Japan K.K • FAX: 052-204-1285
TLX: 22947 INTEL CN Bldg. Kumagay.1
FAX: (1) 500-2953 2-69 Hon-cho KOREA
Kumagaya-shl, ~;,lilama 360
InIal Semiconductor Ltd.'" Tel: 0485-24'fi!l/1 Intel Korea. Ltd.
10/F East Tower FAX: 0485-2·1·/~.18 16th Floor. Life Bldg.
Bond Center 61 Yoido-dong, Youngdeungpo-Ku
Queensway, Central Seoul 150-010
Hong Kong
Tel: (852) 844-4555 m:(~~28iNBjlEE~~6, 6386
FAX: (852) 868-1989 . FAX: (2) 764-8096
INTERNATIONAL DISTRIBUTORS/REPRESENTATIVES
ARGENTINA Micronic DI"~IC:I'~ Okays Koki NEW ZEALAND
No. 516 5UI 'Ioor 2-4-18 Sakse
Dalsys S.R.L. Swastik Cll.'rntmr~ Naka-ku, Nagoya-shi 400
Chacabuco. 90-6 Piso r::maiJ Electronics
Sion, TrorTIl>:IY Road Tel: 052-204-2916 36 Olivo Road
l069-Buenos Aires Chembur FAX: 052-204-2901
Tel: 54-1-334-n26 Penrose. Auckland
Bombay 40() 071 Tel: 011-64-9-591-155
FAX: 54-1-334-1871 TLX: 9531 171447 MDEV Ryoyo Electro Corp
Konwa Bldg_ FAX: 011-64-9-592-661
AUS'TlIALIA Micronic Dovices 1-12-22 Tsukiji
25/8, 1st Floor Chuo-ku, Tokyo 10·1
Email Electronics Tel: 03-546-5011
15·17 Hume Street Bada Bazaar Marg SINGAPORE
Hunlingdale, 3166 Old Rajinder Nagar FAX: 03-546-5044
Tel: 011-61-3-544-8244 New Dolhi 110 060 Electronic Resources Pte, Ltd.
TLX: AA 30895 Tel: 011·91-11-5723509 KOREA
17Harv~Road
FAX: 011-61-3-543-8179 011-91-11-589771 J-Tek Corporalion
TLX: 031-63253 MONO IN #03-01 Sin~apore 1336
Dong Sung Bldg_ 9/F
NSD-Australia
205 Middleborough Rd. Micronic Devices
158-24, Samsung-Dong, Kangnarn·Ku
Seoul 135-090
~\~~~~~8~RS
Box Hill, Victoria 3128 6-3-348/12A Dwarakapuri Colony FAX: (65) 289-5327
Tel: 03 8900970 Tel: (822) 557-8039
Hyderabad 500 482 FAX: (822) 557-8304
FAX: 038990819 Tel: 011-91-842-226748
Samsung Electronics SOUTH AFRICA
BRAZIL 5&5 Corporation Samsung Main Bldg.
Elebra Componentes 1587 Kooser Road 150 Taepyung·Ro-2KA, Chung-Ku
Rua Geraldo Flausina Gomes. 78
7 Andar
San Jose, CA 95118
Tel: (408) 978-6216
Seoul 100-102
C.P.O. Box 8780 i~~~~~~~~i~~roNI~~~~:eyet St.)
TLX: 820281 Tel: (822) 751-3680 Meyerspark, Pretoria, 0184
04575 - Sao Paulo - S.P. Tel: 011-2712-803-7680
Tel: 55-11-534-9641 FAX: (408) 978-8635 TWX: KORSST K 27970
FAX: (822) .753-9065 FAX: 011-2712-803-8294
TLX: 55-11-54593/54591
FAX: 55-11-534-9424 JAPAN MEXICO
CHINA/HONG KONG Asahi Electronics Co. Ltd. SSB Electronics, Inc. TAIWAN
Novel Precision Machinery Co., Ltd. KMM Bldg. 2-14-1 Asono 675 Palomar Street, Bldg. 4, Suite A
Room 728 Trade Square Kokurakita-ku Chula Vista. CA 92011 Micro Eledronlcs Corporation
681 Cheung Sha Wan Road Kitakyushu~shi 802 Tel: (619) 585-3253 12th Floor, Section 3
Kowloon, Hong Kong Tel: 093-511-6471 TLX: 28n51 CBALL UR 285 Nanking East Road
Tel: (852) 360-8999 FAX: 093-551-7861 FAX: (619) 585-8322 Taipei, R.O.C.
TWX: 32032 NVTNL HX Dicopel SA Tel: (886) 2-7198419.
FAX: (852) 725-3695 CTC Components Systems Co .• Ltd. FAX: (886) 2-7197916 .
4-8-1 Dobashr. Miyamae-ku Tochtli 368 Fracc. Ind. San Antonio '
Azcapotzalco -
INOlA Kawasaki-shi, Kanagawa 213 C.P. 02760-Mexico, D.F. Acer Sertek Inc.
Tel: 044-852-5121 Tel: 52-5-561-3211 15th Floor, Section 2
Micronic Devices FAX: 044-877-4268
Arun Complex TLX:I77 3790 Oicome Chien Kuo North Rd.
FAX: 52-5-561-1279 - TaipellB479 R.O.C.
No. 65 D.V.G. Road Dia Semicon Systems. Inc. Tel: 866-2-50HI055 .
Basavanagudi Flower Hill Shinmachi Higashi-kan PHI SA de C.V. TWX: 23756 SERTEK
Sangalore 560 004 1-23-9 Shinmachi, Setagaya-ku Fco. Villa esq. Ajusco sIn FAX: (BB8) 2-5012521
Tel: 011-91-812-600-631 Tokyo 154 Cuernavaca- Morelos
011-91-812-611-365 Tel: 03-439-1600 "Tel: 52-73-13-9412
TLX: 9538458332 MDBG FAX: 03-439-1601 FAX: 52-73-17-5333
·Field Application Location
DOMESTIC SERVICE OFFICES
ALASKA CONNECTICUT MARYLAND NEW YORK PUERTO RICO
Intel Corp. *Inlel Corp **Inlel Corp. *Intel Corp Intel Corp.
c/o TransAlaska Network 301 Leo f'arm ~orporate Park 10010 Junction Dr., Suite 200 2950 Expressway Dr. South South Industrial Park
1515 Lore Rd. 83 Wooster HUIghts Rd. Annapolis Junction 20701 P.O. Box 910
Anchorage 99507 Suite 130
Danbury DGB 11 Tel: (301) 206-2860 Islandia 11722 Las Piedras 00671
Tel: (907) 522-1776 Tel: (203) 7·10·3130 Tel: (516) 231-3300 Tel: (809) 733-8616
Intel Corp. MASSACHUSETIS
c/o TransAlaska Data Systems FLORIDA Intel Corp. TEXAS
c/o Gel Oporatlons **Intel Corp. Westage Business Center
**lntel Corp. Bldg. 300, Route 9 **Inlel Corp.
520 Fifth Ave., SUite 407 800 Fairway Dr .. SUite 160 Westford Corp. Center Westech 360, Suite 4230
Fairbanks 99701 3 Carlisle Rd .. 2nd Floor Fishkill 12524
Deerfield Beach 33441 Tel: (914) 897-3860 8911 Capitol of Texas Hwy.
Tel: (907) 452-6264 Tel: (305) 421-0506 Westford 0188(, Austin 78752-1239
FAX: (305) 421-2144 Tel: (508) 692·00[j0 T01 : (512) 794-8086
Intel Corp.
ARIZONA
*Intel Corp. 5858 Easl Monoy Road **tlntel Corp.
*lnlel Corp. MICHIGAN Syracuse 13211
5850 T.G. Lee Blvd., Sto. 340 12000 ford Rd., SUite 401
410 North 44th Street Orlando 32822 Tel: (315) 454-0576 Dallas 75234
Suite 500 *Intel Carp.
Tel: (407) 240-8000 7071 Orchard Lnku nd., Sle. 100 Tel: (214) 241-8087
Phoenix 85008 NOfHH CAROLINA
Tel: (602) 231-0386 West Bloomfield ·18322 **Inlel Corp.
GEORGIA Tel: (313) 851-8905 7322 SW Freeway, Suite 1490
FAl( (602) 244-0446 *\nhol Corp.
*lntel Corp. 5aoo executive Center Drive Houston 77074
*Inlel Corp. MINNESOTA Tel: (713) 988-8086
20 Technology Park, Suite 150 SUlllll05
500 E. Fry Blvd" Suite M-t5 Norcross 30092
Sierra Vista 85635 Ch.HI()lIo 26212
Tel: (404) 449-0541 *Inlel Corp. UTAH
Tel: (602) 459-5010 Tol. (lO·i) 568-8966
3500 W. 80th St., SUllo 360
Bloomington 55431 Intel Corp.
5523 Theresa Street **1111\'1 Corp.
ARKANSAS Columbus 31907 Tel: (612) 835-6722 428 East 6400 South
55·Hl Cunterview Or., Suite 215 Suite 104
Intel Corp_ Rah'lqh :~7606 Murray 84107
c/o Federal Express HAWAII MISSISSIPPI Tol. ('I\~l) 851-9537 Tel: (801) 263-8051
1500 West Park Drive **Intel Corp. FAX: (801) 268-1457
Little Rock 72204 Intel Corp.
Honolulu 96820 c/o Compu-Care OHIO
Tel: (808) 847-6738 VIRGINIA
CALIFORNIA 2001 Arrport Road, Suite 205F ~·\II\ul Corp.
Jackson 39206 *Intel Corp.
*1nlel Corp. ILLINOIS :\·\01 I"lrk Center Dr., Ste. 220 1504 Santa Rosa Rd., Sle. 106
Tel: (601) 932-6275 Daylon'15414
21515 Vanowen St., Ste. 116 Richmond 23288
Canoga Park 91303 **tlntel Corp. ·T,·I (513) 890-5350 Tel: (804) 282-5668
Tel: (818) 704-8500 Woodfield Corp. Center III MISSOURI
300 N. Martingale Rd., Ste. 400 Corp. WASHINGTON
*Inlel Corp. Schaumburg 60173 *Inlel Corp. :;r.ionce Park Dr., Ste. 100
300 N. Continental Blvd. Tel: (708) 605-8031 4203 Earth City Exp., Slo. 131 1",,,,Ild 44122 **Intel Corp.
Suite 100 Earth City 63045 (.'H,) ·\t;·i.:!736 155 10Bth Avenue N.E., Ste. 386
EI Segundo 90245 INDIANA Tel: (314) 291-1990 Bellevue 98004
Tel: (213)640-6040 Tel: (206) 453-8086
*Intel Corp. Intel Corp.
*Inlel Corp. 8910 Purdue Rd., Ste. 350 Route 2, Box 221
*·'111111 Corp
1900 Prairie City Rd. Indianapolis 46268 Smithville 64089
152~,·1 11 W (;rLJenbrier Parkway
CANADA
Folsom 95630-9597 Tel: (317) 875-0623 Tel: (913) 345-2727
Tel: (916) 351-6143 BUlldlllq II
BeavurlcJlI'II{)05 ONTARIO
-Intel Corp. , KANSAS NEW JERSEY Tel: (50:J) b·i~J e051 **Intel Semiconductor of
%65 Chesapeake Dr., Suite 325 *lntel Corp. Canada, Ltd.
San Diego 92123 **Inle\ Corp. 2650 Queensview Dr., Sto. 2~jO
10985 Cody, Suite 140 300 Sylvan Av.enue PENNSYLVANIA
Tel: (619) 292-8086 Overland Park 66210 Ottawa K2B 8H6
Englewood Cliffs 07632 Tel: (613) 829-9714
··Intel Corp. Tel: (913) 345-2727 *tlntel Corp.
Tel: (201) 567-0821
,100 N. Tustin Avenue 925 Harvest Drrv() **Inlel Semiconductor of
!'uite 450 KENTUCKY *Intel Corp. Suite 200 Canada, Ltd.
!i;\nta Ana 92705 Parkway 109 Office Center Blue Bel119422 190 Attwell Dr., Sle. 102
1,,1: (714) 835-9642 Intel Corp. 328 Newman Springs Road Tel: (215) 641-1000 Rexda\e (Toronto) M9W 6H8
133 Walton Ave., Office lA Red Bank 07701 1-600-468-3546 Tel: (416) 675-2105
"Inlel Corp. Lexington 40508 Tel: (201) 747-2233 FAX: (215) 641-0785
;' 100 San Tomas Exp., 1st floor Tel: (606) 255-2957 QUEBEC
~j,mta Clara 95051 **tlntel Corp.
t,,): (408) 970-1747 Intel Corp. NEW MEXICO 400 Penn Center Blvd., Ste. 610 **Intel Semiconductor of
896 Hillcrest Road, Apt. A Pitlsburgh 15235 Canada, Ltd.
COLORADO Radcliff 40160 (Louisville) Intel Corp. Tel: (412) 823-4970 1 Rue Holiday
Rio Rancho 1 Suite 115
'Inlol Corp. LOUISIANA 4100 Sara Road *Inlel Corp. Tour East
tiOD S. Cherry St., Suite 700 Rio Rancho 87124-1025 1513 Cedar Cliff Dr. Pt. Claire H9R 5N3
[)unvor 80222 Hammond 70401 (near Albuquerque) Camp Hill 17011 Tel: (514) 694-9130
_ Tol: (303) 321-8086 (serviced from Jackson, MS) Tel: (505) 893-7000 Tel: (717) 761-0860 fAX: 514-694-0064
CUSTOMER TRAINING CENTERS
CALIFORNIA MARYLAND
:~'IOO San Tomas Expressway 10010 Junction Dr.
Sdilla Clara 95051 Suite 200
Tel: 1·800-328-0386 Annapolis Junction 20701
Tel: 1-800-328-0386
SYSTEMS ENGINEERING OFFICES
MINNESOTA NEW YORK
3500 W. Both Street 2950 Expressway Dr., Soulh
Suite 360 Islandia 11722
Bloomington 55431 Tel: (506) 231-3300
Tel: (612) 835-6722
*CarrY'ln locations
**Carry·in/mail-in locations
'"
UNITED STATES
Intel Corporation
3065 Bowers Avenue
Santa Clara, CA 95051
JAPAN
Intel Japan KK
5-6 Tokodai, Tsukuba-shi
Ibaraki, 300-26
FRANCE
Intel Corporation S.A.R.L.
1, Rue Edison, BP 303
78054 Saint-Quentin-en-Yvelines Cedex
UNITED KINGDOM
Intel Corporation (U.K) Ltd.
Pipers Way
Swindon
Wiltshire, England SN3 lRJ
GERMANY
Intel GmbH
Dornacher Strasse 1
8016 Feldkirchen bei Muenchen
HONG KONG
Intel Semiconductor Ltd.
10/F East Tower
Bond Center
Queensway, Central
CANADA
Intel Semiconductor of Canada, Ltd.
190 Attwell Drive, Suite 500
Rexdale, Ontario M9W 6H8
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