PlayStation 2 Emotion Engine Serial I/O port information

(by Wisi)

Some of the info is from the PS2SDK.

The added information may be inaccurate - use it at your own risk!

----------- SIO lines locations on PCB ----------

PSTwo SCPH-79004 (GH-061-51)

Chipset (may partialy match SCPH-9000x):

(The following information is not confirmed.)
CXD2976GB = EE + RDRAM + IOP + ..(The way the traces connect and chips are
positioned, suggests the IOP is in this ASIC. Traces from MC, Controller & USB
conectors, go to it.)
CXD2980CGB = GS (It is located close to the Video Encoder and a lot of their traces
connect.)

Note: Earlyer PS3 models may have PS2 EE + .. ASIC and other chips used in
PSTwo ... with the same pinout.

--- SIO points:

a = TX pad; b = RX pad; c = RTS pad; d = CTS pad.

o o o = three small holes; [_] = GND pad.
e, f, g, = other pads
I1 = IC '739 592F'; I2 = Empty pads for IC;
O = One of three metalized holes for bolts, holding the metal heatsink.
. = via

-----------------------------------------------
PCB top:
<- Controller, MC port
______
/ \__
| BATTERY__|
\______/
_
o o o b [_]
_____________________
| EE + RDRAM /|
| + IOP + ... |
| CXD2976GB |
~ ~
-----------------------------------------------
PCB bottom:
__ Controller, MC port->
O __ |I1|
|I2|
|__| o o o
d.
.a f
e .c g

<PCB under CXD2976GB>

-----------------------------------------------
----------- Serial Port Hardware ----------

[out]'->'[in] = signal direction

PS2 SIO input lines have internal pull-up resistors, so sinking is sufficient to
drive them. Low level < 0.7V (inputs). Output high = 1.75V. None of the I/Os are
inverted.

States:
TXD: Tri-State / Open-Drain out, Active low, 1.75V (pulses low on boot-up), with
10kohm load => no detectable drop, can be configured as open-drain output (in
multi-controller mode).
RXD: In, Active low, 1.75V on boot-up, with 10kohm load => drop to ~1V, triggers
with < 5.1k load.
RTS: Out, Tri-State, 0V on boot-up, 10kohm to +1.75V => no change.
CTS: In, Active low, 1.75V on boot-up, 10kohm load => drop to ~1V, triggers with <
5.1k load.

The information above can be used to identify the SIO connection poins.

------------------------------------------------------
RS-232 Transceivers:
MAX3323 (1TX, 1RX) or MAX3322 (2TX, 2RX) can be used. Other manufacturers also
offer suitable ICs. MAX232 can also be used, but additional circuitry is required
between it and the EE SIO. The only downside of using MAX232 & discrete elements,
is that the baud rate is limited to 120 000 bps (tested @ 115 200 bps), but many
Serial ports also don't support higher baud rates.

On the SCPH-79004 (GH-061-51) +5V can be taken from one of the three 78M05G
regulators: there is one near the Ethernet connector, and two more for each USB
port. I used the one for the USB port furthest away from the Controller/MC
connector, as the other one seemed to be used to power something else too.
MAX3322(3) can also be powered from 5V (instead of 3.3V).

When working with the 1.75V logic lines, special care should be taken to prevent
any static electricity from damaging them.
Using 2 paralel wires and connectors for GND lowers the chance of the GND line
getting disconnected, exposing the 1.75V logic lines to higher voltages and
currents.

Make sure the wires are well-secured to the PSTwo's circuit board. I used a wire
soldered to a large ground pad as a strap across a heat-shrink tubing on the lot of
wires. Solder points should not be close to via-s, to prevent damage to them. Near
the SIO pads, the wires can be secured with a little of some weak glue or hot-melt
adhesive, to surfaces of the PCB with no via or thin tracks (to prevent damage to
them in the event of 'un-glueing').

----------- Registers -------------

Similar to the SIO in TMPR4937 and TMPR7901.

[Reg. Name] [REG] [Description]

bit
0 [tested][Name]
[when=0] / [when=1]

tested: [empty] = Yes / 'n' = No / '?' = unknown function

--------
SIO_LCR 0x1000f100 Line Control Register. (TMPR4937 matches)

0 Word_Length
8bit / 7bit

1 Multi_Controller_Enable When set adds TX Wake_Up_Bit (after data bits).

Off / On

2 Stop_Bits
1bit / 2bits

3 Parity_ENable
Off / On

4 Even_Parity
Odd / Even

5 ?(R/O=1)

6:5 ?SIO_Clock_Select
00 = Internal(IMBUSCLK)
01 = Baud_rate_generator_output_that_divided_IMBUSCLK (used by PS2, fixed)
10 = External_clock(SCLK)
11 = Baud_rate_generator_output_that_divided_SCLK

6 .. 7 reserved (R/O=0)

8 Enable_RTS->CTS_Flow_Controll When set and CTS line is high, data for

transmission is stored in TX FIFO. When CTS line is low, the data from the TX FIFO
and any new data gets transmitted.
Off / On

9 .. 12 reserved (R/O=0)

13 Open_Drain_TX (Multi-Controller: when one of many slaves). Has internal pull-

up resistor. When On, RTS goes high (wrong?).
Totem_Pole_Output / Open_Drain_Output

14 n Wake_Up_TX_Bit (Got set to 1 when even parity enabled & Multi-ctrl. -

disabled (undefined behaviour?) Could that be used as a fixed parity bit?
Data_Frame_TX / Address(ID)_Frame_TX

15 n Wake_Up_RX_Bit (Specifies what to receive.)

Data_Frames_RX / Address(ID)_Frames_RX

-----------------
SIO_LSR 0x1000f110 Line Status Register. (R/W) (cleared by
writing 1 (0x0F))

0 n Data_Ready
no/yes

1 Overrun_Error
no/yes

2 Parity_Error
no/yes
3 Framing_Error
no/yes

4 ? RX_Break (RX line low for period of >= one char. transmission.)
no/yes

5..15 ?

--------------
SIO_IER 0x1000f120 Interrupt Enable Register. (3:0 R/W)

0 Enable_Received_Data_Available_Interrupt. Interrupt when RX buffer contains

data.
no/yes

1 n Interrupt when TX buffer is empty.

no/yes

2 Enable_Line_Status_Interrupt Interrupt if an error (LSR.1:4) is present.

no/yes

3 ? Modem Status Interrupt -Interrupt if LSR.0:3 is set.

no/yes

15:4 (R/O =0)

--------------
SIO_ISR 0x1000f130 Interrupt Status Register. (3:0 R/W) (cleared
by writing 1 (0x0F))

0 RX_Data_Available
no/yes

1 TX_Empty
no/yes

2 RX_Error
no/yes

3 ? Modem Status Interrupt -Interrupt if LSR.0:3 is set.

no/yes

11:8 Count of received (unread) bytes.

15:12 Count of bytes for transmit in buffer (0-8).

-----------
SIO_FCR 0x1000f140 FIFO buffer Control Register.

0 FIFO_Reset_Enable

1 RX_FIFO_Reset

2 TX_FIFO_Reset

15:3 (R/O = 0)
-----------
SIO_BGR 0x1000f150 Baud Rate Control Register.
9:0 baudrate = 0 - 0x3FF
Note: The default is 0x1D = 38400, however calculating: 294912000 / (38400 * 256) =
30 = 0x1E ...
15:10 (R/O = 0)
--------------
SIO_TXFIFO 0x1000f180 Transmit FIFO.
--------------
SIO_RXFIFO 0x1000f1c0 Receive FIFO.
-------------