LOADCOMMUTATED

INVERTER BHEL

/||-t lr|TErl .t
\rnAf I En t

DIAGNOSTICAND TROUBLESHOOTING

7.1 SELF TEST

7-1.1 Baslc Structure

The setftest routinesare procdures which may be executedby the HMPG resident
in the LCIcontrolto test individualHruBsand functions.Theseroutinesare executed
upon power-upif the TESTswitch on the NLCB is in the up poisition.The function
oi the self test is to test most of the control panel for the LCl, with great emphasis
placed on the testing of the ntrBs in the SEM/MEM.

Testing of the panel begins by performance tets of the hardware elements within
a neighborhoodof the HMP& microprocessorand continuesto testsof increasingly
remote hardware.All of the tests incorporated within the self test may be classed
into 3 groups:

1. - specifictests
FryVB

2. PairedP\ffEltests

3. Fanel-level
tests

7-1.1.1 PWB - speclflc tests

A great amount of effort has been placed on performing tests that will pinpoint
problems on specific Pv!tss first. lf any easily diagnosed problem exists, it will
be clearly spelled out to the operator.Test such as these comprise the pwb -
Specific test group.

7-1.1.2 Paired PWB Tests

icsrswnrcirdeireiroori lne operattonot severalPWBSare classedwithin the pairexl

PWEIgroup. Diagnosticmessagesfor test failures will indicate a functional problem
and also a list of possible solutions which may be general in nature.

7-1.1.3 Panel-level Tests

Panel-leveltests also require correct operation of several PWBs or modules, how-

ever, these tests are segregated to allow the user to perform either a module-level
test (involvingonly the control SEM/MEM)or a complete panel-leveltest would
include this last category of procedures.

7-1
 BHEL INVERTER
LOADCOMMUTATED

From a practical point of view, the sequence of testing within the control SEM
progresses in the following rnanner:

1. HMPG

2. HLCB

3. HAIA

4. NSFC (source)

5. NSFC (load)

6. NSFE

7. NLCB

8. NLIB (source)

9. NLIB(load)

10. HtsA

11. HRDA
,

12. HTCA(if used)

Furthertestswhich includeHffBs outsidethe SEM/MEM,optionaltest for for series

12, - pulse and tach feedback circuits progress in the following sequence:

1. Cableloadingfrom the SEM.

2, The l/O Module.

3. HLCB.slot 2H

4. SourceslaveNSFC

5. NBIE (series12-pulseonly)

6. HrcA (tachoption)

7. Fieldexcitermodule

8. Door rnodule

7-2
s
*
t

INVERTER
LOADCOMMUTATED BHEL
{
I

7-'|.2 Execudng the Tegts

i
The self routine may be initiated by by resetting the HMPG with the TEST switch
I
(on the NLCB)in the UP position.The entire test is completed in approx 2Oseconds.
At its completion,status infonnation will be printed out at the door-mounted printer.

Upon successfullcompletion of the self test, the drive will operate in the gate
test mode. To returnto normal operation,the NLCBstest switch must be returned
to the normal position and the HMPG must be reset.

cAlrnoN
*lf test et<ercisethe output relalp; thereforethe outputterminal
boards should be disconnected trom the I/O module and/or
source and load breaker should be racked-out drive stopped
before pertorming the test.

7-1.3 DlagnoCnglallures

As mentionedabove,faitureof the setf test procedureswill produce a diagnostic

messages:

DATE ]]ME FAILED AA=TESTNUMBER

(aabb) DURINGTEST OF bb=SUB-TESTNUMBER
description of test

PROBLEM: problem statement

POSSIBLE SOLUTION:

solution 1
solution 2
solution 3

Usually,a failurecan easily be diagnosedby the problem statement.At least one

solution will be suggested in the print out. lt is suggested that troubleshooting
be performed at the F{A/E}level (Fbplace the FlffB not its component}. Although
the diagnostic messagemay indicate specffic failures,itis not recommeded that
F\A/E}components be raplaced or repaired (write or attach the diagnosis to the
card).

7.3
BHEL INVERTEB
LOADCOMMUTATED

The TEST NUMBERand SUB-TESTNUMBERuniquely define a failure within the

(hex) as
seff test procedure. The TEST NUMBER is incremented from 1 to 36
vary
the test progress. For different test numbers, the SUB-TESTparameter will
of
froml up to the number of sub-testswithin that rnaior test. The description
to
lbsts section that follows details the complete self test procedure according
the TESTNUMBERand SUB-TESTNUMBER parameters'

7-1.4 DescrlPdonof Tests.

The tests listedcover the followingstandardelectronicmoduleversions:

1. LCGX-AC E(CTERLCISEM

2 LGJX-DCE(CTERLCISEM

3 MEM
LC[X- SERIE1z-PULSE

Jbst are identicalon all versionsup to test 2D'

The followinglist all tests availablewith sub-testinformation:

Test DescriPtion
Pos-
to F0O0:FFF)'
O. HMPGROMTST Readsallof RAMmemory(FO@:0
siblefailuresare

.0- BusHog error

.1- Read error

1. to 0:3FFF)pcssible
HMPGRAMTST Fteadallof RAM memory (OOO0O:
failuresare:

.0- BusHog error

.2 Read error

.3- Write error

2 HMPGINTFTTST

.1 Verifies control and data lines to HMPGs 8259 interrupt

controller
LOADCOMMUTATED
INVERTER BHEL

3. HMPG-TMR

.1 -Verifies addr lines & daA bit 6 & 7

.2 -Verifies addr lines & data bit 6 & 7

.3 -Verifies addr lines & data bit 6 & 7

.4 -Verifies data bit 5-0 with walking 'l pattern

.5 -Verifies that all outputs are free to toggle

.6 -FOR TMRO;Checks for null count = 1

.7 -FOR TMRO; Load TMR; checks for null count = O

.8 -FOR TMRO;Verify TMR time out

.9 -FOR TMRO;verify TMR reloads

.A -FOR TMRI; Checks for null count = 1

.B -FOR TMRI; Loads TMR; checks for null count = 0

.C -FOR TMRI; Verify TMR time out

.D -FOR TMRl;Verify TMR reloads

.E -FOR TMR2: Checks fo null count = 1

.F -FOR TMR2; Loads TMR; check for null count = O

.10 -FOR TMR2; Verify.TMR time out

.11 -FOR TMR2:VerifiTMR reloads

d Hr.dPG*SfO_patrS

.1 - Check that trans and rec butfers are empty

5 HMPG STALL

.1 - Verify software reset of stall circuit

.2 - Initiate stall timer; checks for no stall after 1O0 ms

.3 - Verify stall asserted after 1.5 seconds

7-5
f'

t'

{'
r BHEL INVERTER
LOADCOMMUTATED
t

6 HMPG-INTR

.1 - Verify operation of bus hog interrupt

'2.Veritythatbushogdoesnotoccurforlegitimateread

.3 - Verify operation of time tic interrupt

7 DMPts

.1 - Checks that write enable switch is not asserted

.2 - Checks for no bus hog during EEPROM reads

.3 -Checks for expected pattern in EEPROM

S HLCB-PRES

.1 - Enable IMOK checks for OIMOK = O

.2 - Disable IMOK checks for OIMOK = 1

9 HLCB-DAK

.1 - Checks for no bus hog during reads of HLCB

A. HLCB-TMR-U2z

.1 - Verify addr lines & data bits 6 & 7

.2 - Verify addr lines & data bits 6 & 7

.3 -Verfi addr lines & data bits 6 & 7

.4 - Verifv data bits 5 - 0 with walking 1 pattern

.5 - Verify that all outputs are free to toggle

.6 -FOR TMRO; Checks for null count = 1

.7 - FOR TMRO; Loads TMR; checks for null count = 0

.8 FORTMRO;VerifYTMR time out

.9 - FORTMR0;VerifYTMR reloads

.A - FORTMRI; Checksfor null count= 1

7,4
?
r
BHEL
INVERTER
LOADCOMMUTATED
x
(
(
count = o
.E - FOR TMRI; LoacisTMR; checksfot null
t:

I
.c - FORTMR1;VerifYTMRtimeout
I

.D - FORTMRI;VerifYTMR reloads
=
.E - FOR TMR2;Checksfor null count 0
count =1
.F - FOR TMR2;LoadsTMR; checksfor null

out
. 1 0 - FORTMR2;VerifYTMR time
reloads
. 1 1 - FORTMR2;VerifYTMR

HLCB-TMR-U23

.1 - Verify addr lines & data bits 6 & 7

.2 -Verify addr lines & data bits 6 & 7

.3 - Verify addr lines & data bits 6 & 7

pattern
'4 - Verify data bits 5-0 with walking 1

.5 -Verfi that all ouputs are free to toggle

=
.6 -FOR TMRO; Checks for null count 1 .
count = O
.7 - FOR TMRO;Loads TMFI checks for null

.8 -FOR TMRO;VerifYTMR time out

.9 - FOR TMRO;VerifYTMR reloads

= 1
.A - FOR TMRI; Checkslor null count

null count = o
.B - FOR TMRI; Loads TMR; checks for

.C - FOR TMRI; VerifYTMR time out

.D - FOR TMRI; VerifYTMR reloads

= 1
.E - FOR TMR2; Checks lor null count

count = 0
.F -FORTMRA LoadsTMR; checksfor null

7-7
 BHEL LOADCOMMUTATED
INVERTER

.10 - FOR TMR2; Verify TMR time

out

.ii - FOR TMR2; Venfy TMR retoads

.12 -FOR TMR2; Intializeto Mode O; verify

status

.13 - FOR TMR2; Load with 10 ms delay;

verify status

.14 - FOR TMR2; After 4 ms verify status

.15 - FOR TMR2; After 15 ms verify time

out

.16 - FOR TMR2; Check that count = O

C HLCB_INTR_PRES

.1 - Vedfy addr and data lines to HLCBs

8259

D HLCB-SIO

.1 - Intializeand check status of HLCBs g251

.2 - Verfi that singre byte of data is

sent by sensing status

.3 - Verifr transfer of data pattern

.
E HAIA-DM

.1 - Checks for no BusHog during

, reads of HAIA

.2 _ Checks for no BusHog during

writes to HAIA

F HAIA-PRES

.1 - Checks that HAfA is present \.-

by reading single bit

10 HAIA.TMR

.1 - Verify addr lines & data bits

6 & Z

.2 - Verify addr lines & data bits

6 & Z

.3 - Verify addr lines & data

bits 6 & 7

.4 - Verifies data bits 5-O with

walking 1 pattern

.5 - Verifies that all outputs are

free to toggle

7-8
 BHEL
INVERTER
LOADCOMMUTATED
=
.6 - FOR TMRO;Checksfor null count 1
count = 0
.7 - FoR TMR0;LoadsTMR; checkslor null

lime out
- FOR TMRO;VerifYTMR
.8

.9 - FORTMRO;VenfYTMR reloads
=1
.A - FOR TMRI; Checksfor null count
count = 0
'B - FOR TMRI; LoadTMR; checksfor null

.C - FORruFil; VerilY TMR time out

.D - FORTtrl|RI;VerrfYTMR reloads
= 1
.E ' FORTMR2;Ghecksfor null count
count d)
.F - FOR TMR2;toads TMR: checksfor null

time out
.10 ' FORTMR2;VerifYTMR
reloads
.11 -.for TMR2;VerifYTMR

11. FIAIA-cot{vEFHoN
=1
.1 ' Start Ay'Dconversion;check that BUSY

2 - Checkthat IDAVAL = 0
that BUSY =
.3 - Wait for conversionto complete;check
o

-4 - Check that IDAVAL = 1

12. HAIA_PSUPPLY

.1 - Check that N15 supply is read correcdy

.2 - Check that P15 supply is read correcdy

13. NSFC_S-PRES

.1 - Set IMOK true; read back IMOK signal'

.2 - Set IMOK False; read back IMOK signal'

+-1
 ?
e
e
( BHEL LOADCOMMUTATED
INVERTER

14. NSF;-S-TMR_PffiS

.l _ Verifies addr lines & data bits 6

& 7

.2 - Verifies addr lines & data bits 6 & 7

3 - Verifies addr lines & data bib 6 & 7

.4 - Verities data bits 5-0 with watking 1 pattern

.5 - Verifies that all outputs are free to toggle

15. NSFC_S_ruODE

.1 - FOR TMRO; Checks for null count = 1

.2 - FOR TMRO;LoadsTMR; checksfor null count = O

.3 - FORTMRO;VerifyTMR time out

it
.4 - FORTMR0;VerifyTMR reloads rs
t"
t
.5 - FOR TMRI; Checksfor nutt count = 1
6

.6 - FOR TMRI; LoadsTMR;checksfor nult count = O f

v
,7 - FORTMRI; VerifyTMR time out
€
.8 - FORTMR1;VerifyTMR reloads

.9 - Performoperationto set pulse train to 0; verify

.A - In TESTMode;writeall on pattern,expectechoof same

.B - In TEST Mode;Watk 1 thru primary& firing latch

.c - In TEST MODE;See if plusetrain is stucktow

.D - In TEST MODE;See if plusetain is stuck high

.E - In TESTMODE;Checkthat plusetain is toggting I

I
l f
7-10
 ?
?
r INVERTER
LoAD coMMUTATED BHEL

'(
16. NSFc L PRES
{
.1 - Set IMOKbue; readbackIMOKsignle
{
1 .2 - Set IMOKfalse;read back IMOKsignal

17.NSFCL ruR PRES

.1 - Verify addr lines & data bits 6 & 7

.2 - Verifyaddr lines & data bits 6 & 7

.3 - Verify addr lines & data bits 6 & 7

.4 - Verfy data bits 5-0 with walking 1 pattern

.5 - Vedfy that all outputsare free to toggle

!

18. NSFCL TMODE

i .1 - FOR TMRO:Checksfor null count = 1

.2 - FOR TMRO;LoadsTMR; checksfor null count = O

1

.3 - FORTMRO;Verfi TMR time out

,
{ .4" - FoR TMRo;vertfYTMR reloads

5 - FOR TMRI; Checlisfor null count = 1

l

!. .6 - FORTMRI; LoadsTMFI checksfor null count = O

! .7 - FoR TMRI; VerE TMR time out

I

.8 - FORTMRI; VerifyTMR reloads

.9 - Performoperationsto set pulsetrain to O; verify

i .

.A - In TEST Mode, write all on pattern, expect echo of same

i .B - In TEST Mode, Wdk 1 thru primary & firing latch

\ .C - In TEST Mode, See if pulse is stuck low

I
.D - In TEST Mode, See if pulse is stuck high
(
( .E - In TEST Mode, Check that pulse train is toggling
(
t

7-11
 BHEL LOADCOMMUTATEDINVERTER

19. NSFE_PRES/NSFF-PRES

.1 - Set IMOKtue; readbackIMOKsignal

.2 - Set IMOKfalse;read back IMOKsignal

1A NSFC-TMR_PRES/NSFF-TMR-PRES

.1 - Verifiesaddr lines & data bits 6 & 7

.2 - Verifiesaddr lines & data bits 6 & 7

.3 - Verifiesaddr lines & data bits 6 & z

.4 - Verifiesdata bits $o with wdking 1 pattern

.5 - Verifiesthat all ouput are free to toggle

1B NSEF-TMODE/NSFF-TMODE

.1 -- FOR TMRO;Checksfor null count = 1

.2 - FOR TMRO;LoadTMR; checksfor null count = O

.3 - FORTMRO;VerifyTMR time out

.4 - FORTMR0;Verfi TMR retoads

.5 - FOR TMRI; Checksfor null count = 1

.6 - FOR TMRI; LoadsTMR: checksfor null count = O

.7 - FORTMRI; Verify TMR time out

.8 - FORTMRI; VerifyTMR retoads

.9 - Performoperationsto set pulse bain to O; verify

.A - In TESTMode,writeallon pattern,expectechoof same

.B - ln TEST Mode,walk I thru primary& firing latch

.C - In TEST Mode,see if pulse is stuoklow

.D - ln TEST Mode,see if putseis stuck high

.E - In TEST Mode,Checkthat pulsetrain is toggling

7-12
 INVERTER
LOADCOMMUTATED BHEL

1C NSFC-S_PLL

. .1 - FOR TMR2: Enables PLL; Checks for null count = 1

'2 - FOR TMR2: Loads TMR2; checks for null count = o

.3 - FOR TMR2: VerifYTMR time out

.4 - FOR TMR2: VerifYTMR reloads

lD NSFC-L-PLL

.1 - FOR TMR2: Enables PLL; Checks for null count = 1

.2 - FOR TMR2: Loads TMR2; checks for null count = 0

.3 - FOR TMR2: VerifYTMR time out

.4 - FOR TMR2: Verufy TMR reloads.

lE NSFE-PLUNSFF-PLL

.1 - FOR TMR2: Enables PLU Checks for null count = 1

.2 - FOR TMR2: Loads TMR2; checks for null count = O

.3 - FOR TMR2: Verify TMR time out

. .4 - FOR TMR2: Verufy TMR reloads

.IF
ROLL-CALL

.1 - Test for ribbon cable connectingHAIA(JA)to SEM(JG)

.2 - Enable NLCB IMOK check for IMOK true

.3 - Disable NLCB IMOK check for IMOK false

.4 - Brable NUBS IMOK check for IMOK true

.5 - Disable NUBS IMOK check for IMOK false

,

.6 - Enable NLIBL IMOK; check for IMOK tue

.7 - Disable NLIBL IMOK; check for IMOK false

7-13
?
C
C
BHEL LOADCOMMUTATED
INVERTER
f
{
20. NLCB-DIFFJMPS
T

t- .1 - Tesi for 0 voits ai REFO

.2 - Test for O volts at TREFO

.3 - Test for 0 volb at 12PREFO

.4 - lnjectcurrentin REFOcircuit;test for changein output

.5 - Injectcurrentin TREFOcircuit testfor changein output

.6 - lnjectcurrentin
l2PREFOcirct.tiBtestforchangeinoutput i

7 - Test for 0 volb at SP (speed)

f

.8 - Reset exitingfaulb; test for 1OSP (overspeed)=O {

t.
21. NSFEjf{ALOq/NSFF_rANAISG
6

.1 - Resetfor El(excitercunent) = 0 volts

*
.2 - Test for no currentimbalance 6
B
.3 - Inject signal in cunent circuit;testfor output change
f

.4 - Again,test for cunent imbalance

6

.5 - Excitercunent circuitW55 Hz input; wdfi current im-

balance is detected f

.6 - Wait 100 ms; verify no cunent imbalancecondition

22. HLCB SQ WAVES

.1 - Test for absenceof SQ wav€swith oscillatoroff

.2 - Test for any activity(gourceor load) with oscillatoron

.3 - Checkfor activityon each of the 3 source channels

,4 - Verifysourceside VA channelactive

.5 - Verrfysourc€side VB channelactive

.6 - Verify sourceside VG channelactive

.7 - Test phasesequenc€of source SQ waws

.8 - Checkfor activityon each of the 3 load channels

7-14
 c
c
C LOADCOMMUTATED
INVERTER BHEL

( .9 - Verify load side VB channel active

(
.A - Verify load side VB channel active
(
( .B - Verify load side VB channel active

' .C -Test phase sequence of source SQ waves

(
23, NUB S ANALOG

r .1 Reset existing faults; verify UV & not OV condition

.2 - Verify not SUPPressioncondition

3 -VerifylUVTO=O
!

.4 - Test C17 tor time delay (Undervoltagecircuit)

.5 - Test C37 tor time delay (Overvolta$e circuit)

{ .6 - Test for 0 volts at IFBS

7 - Test for 0 volts at FLUX BAS

i
.8 - lnject cunent in source current conditioncircuit. Detect
t
change in IFBS.
/ -
.9 - Detect change FLUX BAS
t
( .A - For FLUX BAS: Check for 0 volts dc offset
{
.B - For FLUX BAS: Check level of positive peak

i .C - For FLUX BAS: Check level of negative peak

24. NUB-L.AMLOG
I

.1 - Reset existing faults; verify UV & not OV condition

( - Verity not SUPPressionennditiop

.2
{
.3 - Verify 1UW0 =0

.4 - Test C17 tor time delay (Undervoltagecircuit)

.5 - Test C37 tor time delay (Overvoltagecircuit)

.6 - Test for O volts at IFBL

7-15
 BHEL LOADCOMMUTATEDINVERTER

.7 - Test for 0 volts at FLUX BAL

.8 - Injectcunent in sourcecurrentconditioncircuit. Detect

^L^6^^ i^ tEEc
urrqrr!,g lll ll 9v'

.9 - Detect change FLUX BAL

.A - For FLUX BAL: Check for 0 volts dc offset

.B - For FLUX BAL: Check level of positive peak

.C - For FLUX BAL: Check level of negative peak

.D - For FLUX CBL: Check for O votts dc ofiset

.E - For FLUX CBL: Check level of positive peak

.F - For FLUX CBL: Check level of negative peak \-

.10 - For FLUX ACL' Check for O volts dc offset

.11 - For FLUX ACL: Check level of positive peak

.12 - For FLUX AGL: Check level of negative peak

2s. HLCB_|NA

.1 - Enabletest oscillator;
venfyoccurrence
of sourcezero
crossinginterrupt(slaveintenupt O)

.2 - Verify frequencyof source zero crossingintenupt

.3 - Enabletestoscillator;
verifyoccurenceofloadzerocross-
ing interrupt(slaveinterrupt1)

.4 - Vertfyfrequencyof load zero crossinginterrupt !

.5 - Verifyoccurrehceof sourcefiring interrupt

.6 - Verify occurence of load firing interrupt

.7 - Verifyoccurrenceof field liring interrupt

26. NLCB_SPEED

.1 - Enabletest oscillator;verifyspeedcicuitsreads55 Hz

.2 - Verifyno overspeedcondition.

27. HISA_PRES

.1 - Disable IMOK; verify by reading backbit

.2 - Enable IMOK; verify by readingbackbit

7-16
 INVERTER
LOADCOMMUTATED BHEL

28. CABI-E_CONT

.1 - Testsfor continuityin ribboncablefrom SEM, JA, to

l/6 llazllla
l, v alrvss.e

.2 - Testsfor continuityin ribboncablefrom SEM, JK to

' l/O Module

.3 - Tests for continuityin ribbon cable from SEM, JH, to

l/O Module

.4 - Tests for continuityin ribbon cable from SEM, JB, to

door Module

29. HtSA_lO

1 - Set all inputsfrom UQ Modulehigh; verfi by reading

back input to HISA

.2 -Setall inputsfrom l/O Modulelow; verifyby readingback

input to HISA

?A PIOs-SUPPLY-CHECK

;1 -Checkthat 105 volt dc powersupplyis OK

28 HROA-IA-IO:

In sequence;pick up signalrelayson the HROAin slot 1A of the VO

module.Expectfeedbick signalto indicatechange.

.1 - Forceall HROA(IA)retaysto dropout; verfi byfeedback

.2 - Force 105 Vdc relays to pick-up;venfy by feedback

.3 - Dropout 105Vdc relays,wait 4Oms, verify by feedback

.4 - Pick-upsingle 28 V relay;verify by feedback

.5 - urop-outali lelays,venty by leedback

.6 - Pick-upsingle28 V relay:verifyby feedback

.7 - Dropout all relays;verify feedback

.8 - Pick up single 28 Y relay;verify by feedback

.9 - Drop out all relays;verify feedback

.A - Pick-upsingle28 V relay;verifyby feedback

.B - Drop-outall relays;verify feedback

7-17
 BHEL LOADCOMMUTATED
INVERTER

2C HROA_1B_|O:

In sequencerpick up single relays on the HROA in stot 1A of the l/o

nnodule.Expectfeedbacksignalto indicaiechairge. .

.1 - Forceall HROA(IA) relaysto drop-out;verify byfeedback

.2 - Force 105 Vdc relays to pick-up; verify by feedback

.3 - Drop out 105 Vdc relays,wait 4O ms, verify by feedback

.4 - pick-up single 2g V relay; verify by feedback

.5 - Drop-out all relays; verify by feedback

t
.6 - Pick-upsingle 28 V relay;verify by feedback

.7 - Drop-out all relays; veirify.feedback

F

.8 - Pick-up single 28 V relay; verify by feedback n

:.
.9 - Drop-out all relays; verify by feedback
6
.A - Pick-up single 28 V relay; verify by feedback €

.B - Drop-out all relays; verify feedback

e

2D NLCB_R_DVR
€
.1 - Verify presenceof HROA in slot 18 of VO Module e

.2 - Verifypresenceof HROAin slot 1A of UO Module

:
.3 - Forcerelaydriverson NLCBon; verifyresponsefrom
l/O Modulevia feedback

.4 - Force relays drivers on NLCB on; verify response from

l/O Module via feedback

2gLCG, LGJ HrcA PRES

.1 - Disabte IMOK; verify by reading back bit

.2 - Enabte IMOK; verifr by reading back bit

2FILCG, LC.' HTCA 829 TST

.1 - Check for U1 timer present

.2 - Check for U1 timer 1 ok

.3 - Check for U1 timer 2 ok

.4 - Check for U1 timer 3 ok

7-18
 C
?
?
INVERTER
LOADCOMMUTATED BHEL
(
.5 - Check tor U2 timer present
{
( .5 Chcck tor U2 timei-1 ok
(
.7 - Check tor U2 timer 2 ok
I

.8 - Check Ior U2 timer 3 ok

3O/LCG LGJ HrcA TACH COUNT TST

.1 - Free run counterand verifythat each counterbit toggles

.2 - Sets each bit in the max count register and watches

countermaximum

.3 - Loads2 differentbit patternsinto count registerand looks

to verify that the patterns ere properly loaded

3ULCG LCJ HrcA_PS12-TST

.1 - Check that the +12 Vdc tach power supply is ok

3ALCG LCJ HTCA-CABLE_TST

.1 - Check that the cable is plugged in JA of HTCA card

33/LGJ FLD_E(C_MODiTTEN (DC Field Only)

.1 - Check for presenceof ac on SFG/SFH Module, via the

cell state sensors

.2 - Verify line voltage present bit (HAIA 9OOA:7)is zero

.3 - Verify all cells are not on, via the cell state sensors

.4 - Verify celf 1 turns off, via the cell stale sensors

i
.5 - Verify cell 3 furns off, via the cell state sensors

.6 - Verify cell 5 tums off, via the cell state sensors

.7 - Verify cell 4 turns off, via the cell state sensors

.8 - Verify cell 6 turns off, via the cell state sensors

(
i r .9 - Verify cell 2 turns off, via the cell state sensors

\ .A - Check negativelevel (3.15- 5.64 Vrms) of the ac input

voltage

.B - Check positive level of the ac input voltage

:

7-19
 INVERTER
LOADCOMMUTATED
BHEL
ac input voltage
.C . Check dc offset ol the

.D-Gheckthatexciteroutputvoltage(EV)is<0'5
is < 0'5
'E - Gheck that exciter output voltage
is < 0'5
.F - Check that exciter current (B)
0'5
.10 - Check that exciter current is <
for cells 1'3'5
- While sampling cell state sensor pattems
'11
are operational
verify that cell state sensor
thru cells 1'3' and 5
12. - Verify phase A zero-crossing
cell
A by finding correct second
'13 - Verity phase C follows
data)
state Patterh (in samPled
cell
C by finding colect'third
'14 - Verify phase B tollows
data' (Gomplete phase
tt"iJ p"o*n in sanrpled
reversal check')
pattems for cells 4'6'2
.15 - While sampling cell state sensor
are operational
u"'if in"t'cell state sensors
celb 1'3' and 5
.16 - Verify phase A zero-crossingihru

A by finding correct second

-17 - Verity phase C lollows
Pattern
pattern
C by finding conect third
.18 - Verify phase B follows

3 4 l L c G F L D _ E ( o - M o D A C J T T N ( A C F i e l d o n l y ) v
the SFFJSFFmodule'
.1 - Check for no absence of ac on
via the cell state sensors
the cell state sensors
.2 - Verify presenceof ac phase A' via

the cell state sensors

.3 - Verify presence ol ac phase B' via

the cell state sensors

'4 - Verify presenceof ac phase C' via

.5 - Check level of the ac input voltage

.6 - Check level of the ac input voltage

voltage
.7 - Check dc offset of the ac input

is equal to 0
.8 - Check that exciter output voltage
 INVERTER
LOADCOMMUTATED BHEL

.9 - Check that exciterouput voltageis equal to O

.A - Check that excitercunent is equal to 0

.B - Check that excitercunent is equal to 0

.C - While samplingcell state sensor pattems,vedfy that

cell state sensorsare operational

.D - Venfy correctcell state patternis in sampleddata

.E - Verifyphasesequenceof SFUSFF Moduleinputvoltage

by finding correct seQondcell state pattern in
sampleddata

.F - Venfyphasesequenceof SFEISFFModuleinput
voltageby finding correct third cell state pattem in
sampleddata (Coppletionof phase reversalcheck)

34LC., F|-O-D(C-MOD-1PI{ASE(DC Field Only)

nsingle phaseoperationof SFGISFHmodule,A-B*

.1 - Waitingfor negalivelevel of field excitersync signal

2 - Waiting for positive edge of field exciter sync signal

.3 - After delay, fire conect SCR pair, verify via cell state
sensors then tum-off all cells

.4 - After 5 cycles, veri! that el<citercunent < 0.5 per unit

.5 - Waitingfor positivelevel of field excitersync signal

.6 - Waitingfor negaliveedge of field excitersync signal

.7 - After delay, fire correctSGR pair; verify via cell state

sensorsthen tum-off all cells

.8 - After 5 cycles,verifythat excitercunent < 0.5 per unit

r€ingle phaseoperationof SFG|/SFHmoduleB-Cn

.9 - Waitingfor negativelevel of field excitersync signal

.10 - Waitingfor positiveedge of field exciter sync signal

.11 - After delay, lire correct SCR pair; verify via cell state
sensorsthen turn-offall cells

.12 - After 5 cycles,verifythat excitercurrent< 0.5 per unit

7-21
(-

e
INVERTER
LOADCOMMUTATED
r BHEL
(
signal
.13 - Waiting for positive level of field exciter

exciter signal
.14 - Waiting for neoative edge of field

verify via cell state

'15 - After delay' fire correct SCR pair;
cells
sensors' then turn-off all
current < 0'5 per unit
'16 - After 5 cyclas' verify that exciter

*€ing|ephaseoperationo|SFG/SFHmodulec-A*
sync signal
.17 - Waiting for negative level of field exciter
sync signal
'18 - Waiting for positive edge of field exciter
via cell state
.19 - After delay' fire correct SCR pair; verify
sensors then turn-off all cells
per unit
that exciter Current < O'5
.20 - After 5 cycles' verrty
signal
level of field exciter sync
.21 - Waiting for positive
signal
edge of field exciter sync
'22 - Waiting for negative

.2g-Afterdelay'firecorrectSGRpair;verifyviacellstate
cells
sensors then turn-off all
< O'5 per unit
.24 -After 5 cycles' verify that exciter current

(AC Field Onlv)

35/LCG FLD-E(C-MODAC-IPHASE
A-Bs
**Single phase operation of SFFJSFFmodule'

exciter sync signal

.1 - Waiting for negative level of field

exciter sync signal

.2 - Waiting for positive edge of field

verify via cell state

.3 - After delay' fire correct SGR pair;
sensors
sync signal
.4 - Waiting for positive level of field exciter

exciter sync signal

.5 - Waiting for negative edge of field

.6 .Afterde|ay,firecorrectSCRpair;verifyviace||state
sensors
1

< O'5 per unit

.7 - After 5 cycles,verifythat excitercurrent

*€ingle phaseoperationof SFBSFFmodule'B-Cn

7-22
C
?
f INVERTER
LOADCOMMUTATED BHEL

( - Wailingfor negativelevel of field excitersync slgnal

.8
(
.9 - Waitingfor positiveedge of field excitersync slgnal
{
( .A - After delay, fire correct SCR pair; verify via cell state
sensors

.B - Waitingfor positivelevel of field excitersync signal

.C - Waitingfor negativeedge of field excitersync signal

.D - After delay, fire correct SCR pair; verify via cell state
sensors

.E - After 5 cycles,verifythat excitercurrent< 0.5 per unit

*€ingle phaseoperationol SFE/SFHmodule,C-A*

.F - Waitingfor negativelevel of field excitersync signal

.10 - Waitinglor positiveedge of field excitersync signal

.11 - After delay, fire correct SCR pair; verify via cell state
sensors

.12 - Waitingfor positivelevel of field excitersync signal

.13 - Waitingfor negativeedge of field excitersync signal

.14 - After delay, fire correct SCR pair; verify via cell state
sensors

.15 - After 5 cycles,verifythat excitercurrent< 0.5 per unit

DOOR_MOD-PRES

.1 - Test for CTS asserted

.2 - Test for DSR asserted

2E]LCL HLCB2-PRES

.1 - Enables IMOK checks for 0IMOK = O.

.2 - Disables IMOK checks for OIMOK =1.

aFILCL HLCB2-DM

.'l - Checks for no Bushog during reads of HLCB (2H).

3O|LCL HLCB2_TMR-U22

.1 - Verifies addr lines & data bits 6 & 7

.2 - Verifies addr lines & data bits 6 & 7

7-23
 BHEL LOAD COMMUTATEDINVERTER

.3 - Verifies addr lines & data bib 6 & 7

.4 - Verifies data bits 5-0 with walking 1 pattem

.5 - Verifies that all outputs are free to toggle.

.6 - FOR TMRO: Checks for null count= 1

.7 - FOR TMRO: Loads TMR; checks for null count = 0

.8 - FOR TMRO: Verify TMR time out

.9 - FOR TMRO: Verify TMR.reloads

.A - FOR TMRI: Checks for null count = 1

.B - FOR TMRI: Loads TMR; checks for null count = O

.C - FOR TMRI: Venfy TMR time out

.D - FOR TMRI: Verify TMR reloads

.E - FOR TMR2: Checks for null count = 1

.F - FOR TMR2: Loads TMR: checks for null count = 0

.10 - FOR TMR2: Verify TMR time out

.11 - FOR TMR2: Verify TMR reloads

31/LCL HLCB2-TMR-U23

.1 - Verifies addr lines & data bits 6 & 7

.2 - Verifies addr lines & data bits 6 & 7

.3 - Verifies addr lines & data bits 6 & 7

.4 - Verifiesdata bits 5-0 with walking 1 pattern

.5 - Verifiesthat all ouputs are free to toggle.

.6 - FOR TMRO:Checksfor null count= 1

.7 - FOR TMRO:LoadsTMR; checksfor null count = 0

.8 - FORTMRO:VerifyTMR time out

.9 - FORTMRO:VerifyTMR reloads

7-24
LOADCOMMUTATED
INVERTER BHEL

.A - FOR TMRI: Checksfor null count= 1

.B - FOR TMRI: LoadsTMR; checksfor null count = O

.C - FOR TMRI: Verfi TMR time out

.D - FORTMRI: VerifyTMR retoads

.E - FOR TMR2:Ghecksfor null count = 1

.F - FOR TMR2:LoadsTMR; checksfor null count = O

.10 - FORTMR2:Verifytime out

.11 - FORTMR2:VerifyTMR reloads

.12 - FOR TMR2:Initialiizeto modeO;verfi status

.13 - FOR TMR2:Loadwith 1Oms delay;verifystatus

.14 - FORTMR2:After4 ms, verifystatus

.15 - FORTMR2:After 15 ms, verifytime out

.16 - FOR TMR21:Gheckthat count = O

3?LCL HLCB2_S|O

.1 - Initializeand check status of HLCBs 8251

.2 - Verify that single byte of data is sent, by sensing status

.3 - Vedfy transfer of data pattern

33/LCL NSFC_S-SI.AVE_PRES

.1 - Set IMOK tue; read back IMOK signal

.2 - Set IMOK false; read back IMOK signal

34/LCL NSFC_S-SI-AVE_TMR-PRES

.1 - Verifies addr lines & data bits 6 & 7

.2 - Verifies addr lines & data bits 6 & 7

.3 - Verifies addr lines & data bits 6 & 7

.4 - Verifies data bits 5-O with walking 1 pattem

.5 - Verifies that all outputs are free to toggle

7-25
f:

o
{'
BHEL LOADCOMMUTATED
INVERTER
{

35/LCLNSFCS SI.A\E ruODE AND NSFCS SI-AVEPLL

.1 - FOR TMRO: Checks for null count = 1

.2 - FOR TMRO:loads TMR; checksfor nullcount=O

.3 - FORTMRO:VerifyTMR time out

.4 - FORTMRO:VerifyTMR reloads

.5 - FOR TMRI: Checksfor null count = 1

.6 = FOR TMRI: LoadsTMR: checksfor null count = O

€

7 - FORTMRI: VerifyTMR;time out G

t
.8 - FORTMRI: VerifyTMR;'rdoads
C
.9 - Pedormoperationto set pulse train to O; verfi C

.A - In TESTMode,writeall on pattern,expectecho of same t

c
.B - ln TEST Mode,walk 1 thru primary& firing latch
e
.C - In TEST Mode,see if pulse train is struck low t

- In TEST Mode,chec* that pulse train is struck high €

.D
e
.E In TEST Mode,check that pulse trian is toggling f;

.F FOR TMR2: EnablesPLL Checksfor null count = 1 G

e
.10 - FOR TMR2:LoadsTMR; checksfor null count = O

.11 - FORTMR2:VerifyTMR time out {

.12 FORTMR2:VerifyTMR reloads

{.
36ILCLNB|E_IHJNALOG

.1 - afterreset,verifyno SUPP2or CIB

.2 - forceSUPP2and ClB.fault

.3 - Verifycan clearCIB fault

.4 - Verifycan clearSUPP2fault

3ILCL HTCA-PRES

.1 - Set IMOK true; read back IMOK signal

.2 - Set IMOK false; read back IMOK signal

7.26
C
C
? INVERTER
LOADCOMMUTATED BHEL

f 38/LCL HTCA_8254_TST
(
.1- .11 areforU1
t

( .1 - Verifiesaddr lines & data bib 6 & 7

t .2 - Verifiesaddr lines & data bits 6 & 7

i
.3 - Verifiesaddr lines & data bits 6 & 7

I .4 - Verifiesdata bits 5-0 with walking 1 pattern

,5 - Verifiesthat all outputsare free to toggle

.6 - FOR TMRO:Ghecksfor null count = 1

i

.7 - FOR TMRO:LoadsTMR; checksfor nullcount=o

.8 - FORTMRO:VerrfyTMR time out

|'
{ .9 - FORTMRO:VerifyTMR reloads

.A - FOR TMRI: Ghecks for null count = 1

(
.B - FOR TMRI: Loads TMR; checks for null count = O
(
'
.c - FOR TMRI: Verify TMR; time out

.D - FOR TMR1: VerrfyTMR; reloads

(
.E - FOR TMR2: Checks for null count = 1
(

.F - FOR TMR2: Loads TMR; checks for null cou;tt = O

(
. 1 0 - FOR TMR2: Verify time out

. 1 1 - FOR TMR2: Verify TMR reloads

. 21 - .31 are lor U2

I . 2 1 - Verifies addr lines & data bits 6 & 7

.22 - Verifies addr lines & data bits 6 & 7

{
.23 - Verifies addr lines & data bits 6 & 7

(
.24 - Verifies data bits 5-0 with walking 1 pattern

.25 - Verifies that all outputs are free to toggle.

(
.26 - FOR TMRO: Checks for null count= 1
I

7-27
 BHEL LOADCOMMUTATED
INVERTER

,27 - FOR TMRO: Loads TMR; checks for null count = 0

.28 - FOR TMRO: Verify TMR time out

.29 - FOR TMRO: Verify TMR reloads

.2A - FOR TMRI: Checks for null count = 1

.28 - FOR TMRI: Loads TMR: checks for null count = O

.2C - FOR TMRI: Verify TMR time out

.2D - FOR TMRI: VerifyTMR reloads

.2E - FOR TMR2: Checks for null count = 1

.2F - FOR TMR2: Loads TMR; checks for null count = O

.30 - FOR TMR2: Verify TMR time out

.31 - FOR TMR2: Verify TMR reloads

39/LCL HTCA TACH COUNT TST

.1 - free run counter and verify each counter bit toggles

.2 - set each bit in the max count register watch counter

maximum

.3 load and ver'rtyZdifferentbit patterns into the count register

3A/LCL HrcA_PS12-TST

.1 - check high position count bit 7 for zero (P12 ok)

3B/LCL HrcA-CABLE_TST

.1 - check high positioncount bit 6 for zero (cableconnected

to tab)

3C/LCL FLD_E(C_MODAC_ATTEN(for ac field exciter only)

,1 - check for no absence of ac on the SFESFF module

via the cell statersensors

.2 - Verify presence of ac on phase A via the cell state sensors

{
.3 - Verfy presenceof ac on phase I via the cellstate sensors

i
.4 - Verifypresenceof ac on phase C via the cellstatesensors

7'2e
LOADCOMMUTATED
INVERTER BHEL

.5 - Check level of the ac input voltage

.6 - Check level of the ac input voltage

.7 - Gheec* dc offset of the ac input voltage

.8 - Checkthat exciter output voltageis equal O

.9 - Checkthat exciter output voltageis equal O

.A - Check that excitercurrentis equal to 0

.B -Checkthat excitercurrentis equalto 0

.C - Whilesamplingcellstatesensorpatterns,verifythat cell
statesensorsare operational

.D - Verify correctcell state patternis in sampleddata

.E - Verifyphasesequenceof SFE moduleinputvoltageby

findingconect secondcell state patternin sampleddata

.F - Venfyphasesequenceoisfe moduleinputvoltageby
finding correct third cell state patterni;r sampleddata
(Completionof phase reversalcheck)

3C/LCLFLD-E(C-MOD-ATTiI(for dc field only)

.1 - Checkfor presenceof ac on SFG/SFHModule,via the

cell state sensors

.2 - Verfy line voltage presentbit (HAIA90044 is zero

.3 - Verrfyall cells are not on, via the cell state sensors

.4 - Verify cell 1 tums off, via the cell state sensors

.5 - Verifycell 3 turns off, via the cell statesensors

.L . Verifyc.:ii 5 {.;:;i;.u{i, via the cell statesensors

.7 - Verify cell 4 turns off, via the cell state sensors

.8 - Verify cell 6 turns off, via the cell state sensors

.9 - Verifycell 2 turns off, via the cell statesensors

.A - Checknegativelevel (3.15- 5.64Vrms)of the ac input

voltage

.B - Check positive level of the ac input voltage

7-29
t''

BHEL LOADCOMMUTATED
INVERTER

.C - Check dc offset of the ac input voltage

.D - Check that exciter output voltage (E\4 is < 0.5

.E - Check that exciter output voltage is < 0.5

.F - Check that exciter current (El) is < 0.5

.10 - Check that exciter current is < 0.5

.11 - Whilesmaplingcell state.sensorpattemsfor cells 1,3,5

verify that cell stratesensor are operational

12. - Verfi Phase A zero-crossingthru cells 1,3, and 5

.13 - Verify phase C follows A by finding correct second cell

state pattern in sampled data

.14 - Verify phase B follows C by finding correct third cell

i
state pattern in sampled data. (Complete phase reversal
€
check.)
t

.15 - While sampling cell state sensor pattems for cells 4,6,2
t
verify that cell stiate sensors are operational

.1S - Verify phase A zero-crossingthru cells 1,3, and 5

.17 - Verify phase C following A by finding correct second

paftern

- Verify phase B follows A by finding correct third pattern {

.18

3D/LCL FLD_EG_MODAC_IPHASE (for ac field only)

*€ingle phase operationof SFE/SFFmodule,A-B*

.1 - Waiting for negative level of field exciter sync signal

.2 - Waiting for positive edge of field exciter sync signal

.3 - Afterdelay,fire correctSCR pair;verifyviacelstatesensors

.4 - Waiting for positive level of field exciter sync signal

.5 - Waiting for negative edge of field exciter sync signal

{
.6 - After delay, fire correct SCR pair; verify via cell state
sensors

.7 - After 5 cycles, verify that exciter current < 0.5 per unit

*Single phase operationof SFVSFF module, B-Cn

.8 - Waiting for negative level of field exciter sync signal

7-.30
 C
f
? LOADCOMMUTATED
INVERTER BHEL

( .9 - Waiting for positive edge of field exciter sync signal

{
.A - After delay, fire correct SCR pair; verify
via cell state
sensors
(
.B - Waiting for positive tevel of field exciter
{ sync signal

.C - Waiting for negative edge of field excirer sync

signal

.D - After delay, fire correct SCR pair; verity via

cell state
sensors

.E - After 5 cycles, verify that exciter current < 0.5 per

unit
*Single phase operationof SFEISFF
module,C A#

.F - Waiting for negative level of lield exciter sync signal

.10 - Waiting for positive edge of field exciter sync signal

.11 - After delay, fire correct SCR pair; verify via cefl state
sensors

.12 - Waiting for positive level of field exciter sync signal

.13 - Waiting for negativg edge of field exciter sync signal

.14 - After delay, fire conect SCR pair; verify via cell state
sensors

.15 - After 5 cycles, verify that exciter current < O.5 per unit

3D/LCL FLD_EG_MOD_IPHASE (for dc fietd onty)

* Singlephase operation
of SFG/SFHmodule,A-EIfr

.1 - Waiting for negative level of field exciter sync signal

i r .2 - Waiting for positive edge of field exciter sync signal

.3 - After delay, fire correct SCR pair, verify via cell state
sensors then turn-off all cells

.4 - After 5 cycles, verify that exciter current < O.5 per unit

.5 - Waiting for positive level of field exciter signal

.6 - Waiting for negative edge of field exciter signal

.7 -Afterdelay,firecorrectSCR pair;verifyvia cellstatesensors

then turn-ofi all cells

.8 - After 5 cycles,rrerifythat excitercurrent< 0.5 per unit

*€ingle phaseoperationof SFG/SFHmodule

B-C*

7-31
 BHEL LOADCOMMUTATED
INVERTER

.9 - Waitingfor negativelevel of field excitersync signal

.10 - Waitingfor positiveedge of field exciter sync signal

.11 - After delay,fire correctSCR pair; verifyvia cell state

sensorsthen turn-offall cells

.12 - After 5 cycles,verifythat excitercurrent< 0.5 per unit

.13 - Waitingfor positivelevel of field excitersignal

.14 - Waitingfor negativeedge of field excitersignal

.15 - Afier delay, fire correct SCR pair; verify via cell state
sensorsthen turn-offall cells

.16 - After 5 cycles,verifythat excitercunent < 0.5 per unit

*€ingle phaseoperationof SFG/SFHmoduleC-An

.17 - Waitingfor negativelevel of lield excitersync signal

.18 - Waitingfor positiveedge of field exciter sync signal

.19 - After delay, fire correct SCR pair; verify via cell state
sensorsthen tum-offall cells
z
.2O - After5 cycles,verifythat excitercurrent< 0.5 per unit

.21 - Waitingfor positivelevel of field excitersignal

.22 - Waitingfor negativeedge of field excitersignal

.23 - After delay, fire correct SCR pair; verify via cell state
sensorsthen turn-offall cells

.24 - After 5 cycles,verfi that excitercunent < 0.5 per unit

3E DOOR-MOD_PRES

.1 - Testfor CTS asserted

.2 - Test for DSR asserted

7.2 GATE.TEST.MODE !

\
7-2.1 General

The gate test mode allows off-linetesting of much of the analog signal conditionirq,
i
microprocessor firing control, and gate pulse generation circuitry. In the gd+
test-mode, a local test oscillator supplies 3 phase, approxinmately 60 Hz signds ;
inp|aceoftheattenuatedbussigna|sfromthesourceand|oadbridges..Ihe.-

7-32