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BCD Sumador de 1 Dígito: Library Use All Use All Entity Is Port in Downto in Out Downto Out End Architecture of Is

The document describes a 4-bit BCD adder circuit in VHDL. It contains an entity for a single-digit BCD adder with inputs for two 4-bit BCD numbers, a carry in, and outputs for the sum and carry out. It also contains a top-level entity that uses four of the single-digit adders connected in series to add 16-bit BCD numbers. A testbench entity is provided to test the top-level adder design.

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Cristian Fabian Romero Rojas
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58 views3 pages

BCD Sumador de 1 Dígito: Library Use All Use All Entity Is Port in Downto in Out Downto Out End Architecture of Is

The document describes a 4-bit BCD adder circuit in VHDL. It contains an entity for a single-digit BCD adder with inputs for two 4-bit BCD numbers, a carry in, and outputs for the sum and carry out. It also contains a top-level entity that uses four of the single-digit adders connected in series to add 16-bit BCD numbers. A testbench entity is provided to test the top-level adder design.

Uploaded by

Cristian Fabian Romero Rojas
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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BCD sumador de 1 dígito

library ieee ;
use ieee . std_logic_1164 . all ;
use ieee . numeric_std . all ;

entity bcd_adder is
port (
a , b : in unsigned ( 3 downto 0 ); -- entrada numbers.
carry_in : in std_logic ;
sum : out unsigned ( 3 downto 0 );
carry : out std_logic
);
end bcd_adder ;

architecture arch of bcd_adder is

begin

process ( a , b )
variable sum_temp : unsigned ( 4 downto 0 );
begin
sum_temp := ( '0' & a ) + ( '0' & b ) + ( "0000" & carry_in );
if ( sum_temp > 9 ) then
carry <= '1' ;
sum <= resize (( sum_temp + "00110" ), 4 );
else
carry <= '0' ;
sum <= sum_temp ( 3 downto 0 );
end if ;
end process ;

end arch ;
Entidad superior
library IEEE ;
use IEEE . STD_LOGIC_1164 . ALL ;
use ieee . numeric_std . ALL ;

entity TopAdder is
port (
in1 : in std_logic_vector ( 15 downto 0 );
in2 : in std_logic_vector ( 15 downto 0 );
sum : out std_logic_vector ( 15 downto 0 );
carry : out std_logic );
end TopAdder ;

architecture structural of TopAdder is

component bcd_adder is
port (
a , b : in unsigned ( 3 downto 0 ); -- entrada numbers.
carry_in : in std_logic ;
sum : out unsigned ( 3 downto 0 );
carry : out std_logic
);
end component ;

signal carry1 , carry2 , carry3 : std_logic ;


signal in1_s , in2_s , sum_s : unsigned ( 15 downto 0 );

begin
in1_s <= unsigned ( in1 );
in2_s <= unsigned ( in2 );
sum <= std_logic_vector ( sum_s );

adder1 : bcd_adder
port map ( in1_s ( 3 downto 0 ), in2_s ( 3 downto 0 ), '0' , sum_s ( 3
downto 0 ), carry1 );

adder2 : bcd_adder
port map ( in1_s ( 7 downto 4 ), in2_s ( 7 downto 4 ), carry1 , sum_s
( 7 downto 4 ), carry2 );

adder3 : bcd_adder
port map ( in1_s ( 11 downto 8 ), in2_s ( 11 downto 8 ), carry2 ,
sum_s ( 11 downto 8 ), carry3 );

adder4 : bcd_adder
port map ( in1_s ( 15 downto 12 ), in2_s ( 15 downto 12 ), carry3 ,
sum_s ( 15 downto 12 ), carry );

end structural ;
Banco de Pruebas
LIBRARY ieee ;
USE ieee . std_logic_1164 . ALL ;
USE ieee . numeric_std . ALL ;
ENTITY test1 IS
END test1 ;
ARCHITECTURE behavior OF test1 IS
COMPONENT TopAdder
PORT (
in1 : IN std_logic_vector ( 15 downto 0 );
in2 : IN std_logic_vector ( 15 downto 0 );
sum : OUT std_logic_vector ( 15 downto 0 );
carry : OUT std_logic
);
END COMPONENT ;
signal in1 : std_logic_vector ( 15 downto 0 ) := ( others => '0' );
signal in2 : std_logic_vector ( 15 downto 0 ) := ( others => '0' );
signal sum : std_logic_vector ( 15 downto 0 );
signal carry : std_logic ;

BEGIN
uut : TopAdder PORT MAP (
in1 => in1 ,
in2 => in2 ,
sum => sum ,
carry => carry
);

stim_proc : process
begin
wait for 100 ns ;

in1 <= "0000000000000001" ;


in2 <= "0000000000000010" ;
wait for 100 ns ;

in1 <= "0000000000001001" ;


in2 <= "0000000000000001" ;
wait ;
end process ;
END ;

http://stackoverflow.com/questions/28301543/bcd-adder-of-4-bcd-digit-numbers-in-vhdl

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