Chapter 2 : CMOS technology

Instructor: Dr. Po-Wen Chiu

(EE/NTHU)

Reference:

1. J. D. Plummer, M. M. Deal, and P. B. Griffin, Silicon VLSI

Technology, Prentice Hall, 2000.

2. Michael Quirk and Julian Serda, Semiconductor

Manufacturing Technology, Prentice Hall, 2001.

3. Robert Doering and Yoshio Nishi, Handbook of

Semiconductor Manufacturing Technology, CRC Press 2008.
 2.2 CMOS process flow

2-1
2.2.1 Choosing a substrate
(a) Wafer size and type (N or P)
(b) Resistivity (doping level): moderate resistivity (25-50 Wcm) with doping level of
~1015 cm-3 < well doping level of 1016-1017 cm-3.
(c) Crystal orientation: mainly (100) due to less defects and higher quality of Si/SiO2
interface.

The purpose of the underlying SiO2 is to release the

stress in Si substrate, which generate defects in Si
during long high-temperature oxidation.

2-2
2.2.2 Active region formation
(a) Local oxidation of Si (LOCOS) for electrical isolation from each devices :
Thermal growth of thin SiO2 layer (~40 nm):
Ø 15 min at 900 oC in an H2O atmosphere or 45 min at 1000 oC in pure O2 atmosphere
Ø SiO2 is under compressive stress.
(b) Growth of thin nitride layer (~80 nm) by LPCVD:
Ø 3SiH4 + 4NH3 à Si3N4 + 12H2
Ø The Si3N4 is under tensile stress,
and can be partially compensated
The purpose of the underlying SiO2 is to release
by the underlying SiO2, reducing the stress in Si substrate, which generate defects
in Si during long high-temperature oxidation.
the stress in Si.
(c) Spinning and patterning of photoresist
(d) Dry etching of Si3N4 (using CF4 or
NF3 gas):
Si3N4 + 12F à 3SiF4 + 2N2
(e) Remove the resist by
using O2 plasma or
sulfuric acid: both
of them do not
attack Si3N4 and
SiO2.

(f) LOCOS at 1000 oC for 90 min in H2O to grow ~500 nm of SiO2 on the exposed region
Ø Si3N4 is a very dense material and prevents H2O and O2 from diffusing to the
underlying Si.
Ø The lateral diffusion of oxidant (H2O) from SiO2 cause bird’s beak and reduce the
active region (decrease device density).
(g) Stripping Si3N4 in hot phosphoric acid
Ø The acid is highly selective between Si3N4 and SiO2.
2-3
(h) Alternative to SiO2/Si3N4 stack:
Ø poly SiO2/Si3N4/SiO2 (Poly-buffered LOCOS)
Ø Poly SiO2 (~100 nm) is formed by LPCVD.
Ø Poly SiO2 helps release large stresses which would cause defects in Si during
the LOCOS.
Ø This stack allows us to use a thicker Si3N4 and thinner SiO2, both of which
reduce the lateral diffusion of oxidant and bird’s beak accordingly.
2.2.3 Process option for device isolation –
shallow trench isolation (STI)
In this section we will see a process option which can eliminate bird’s beak.
Resist
Si3N4

SiO2

(a) We start with the same process as LOCOS does: First grow SiO2 and then Si3N4
layer with similar thickness.
(b) Photoresist is then applied, exposed, and developed.
(c) Si3N4 and SiO2 are etched using resist as a mask.
2-4
(d) A Si trench is created by bromine-based plasma etching.
Ø The trench needs to be vertical with a little undercut.
Ø The trench will be filled by depositing SiO2. A sharp trench is important for
avoiding voids in filling with SiO2. A little undercut rounds the corners and
avoid electrical effects associated with sharp corners.
(e) Next step is to thermally
grow a thin (10-20 nm)
“liner”oxide which
enhance the Si/SiO2
interface. Liner oxide (SiO2)

(f) Then fill the trench

with SiO2 by CVD.
(g) Polishing the excess surface SiO2 by chemical mechanical polishing (CMP). In
this process, a high-pH silica slurry is used for polishing and the nitride layer
serves as a polishing stop.

(h) There are three advantages in STI compared with LOCOS:

Ø There is no long high-temperature oxidation, so less defects are generated.
Ø The bird’s beak can be eliminated.
Ø Produce a more compact isolation.

2-5
2.2.4 N and P well formation
The well properties such as doping level are important in terms of MOS transistor
threshold voltage, I-V characteristics, and PN junction capacitance.
(a) Using optical lithography to define the (c) Strip resist chemically or in O2 plasma.
region where P well is to be formed.
(d) Thermal annealing for repairing the
(b) Implantation of boron ions for P well. damaged lattice: 10 sec. at 1000 oC or 30
Ø The energy of the boron ions must be min at 800 oC
large enough to go through “thin” and
“thick” oxide regions, but small
enough not to go through the resist ~ 1 µm
layer.
Ø The energy is in the range of 150 –
200 keV. Thick oxide ~ 0.5 µm Thin oxide
Ø The dose depends on the desired (field oxide)
To avoid parasitic
doping level in the well. For doping inversion problem
level 1017 cm-3, we need dose on the
2-6 order of 1013 cm-2.
(e) Follow similar procedure of optical lithography for the N well formation.
(f) Implantation of phosphorus ions for N well.
Ø The energy of the phosphorus ions must be large enough to go through “thin”
and “thick” oxide regions, but small enough not to go through the resist layer.
Ø The energy is in the range of 300 – 400 keV to reach the same depth in Si
because phosphorus is a heavier atom.

2-7
(g) Removing the resist and anneal at 1000-1100 oC for 4-6 hrs to reach a junction
depth of 2-3 µm (drive-in process).
(h) Phosphorus has a bit smaller diffusion coefficient compared with boron, so the
P and N well are capable of having similar junction depth after the drive-in
annealing.
(i) Other dopants for N well are As and Sb. They are heavier (higher implantation
energy) and have smaller diffusion coefficients.

2-7
2.2.5 Process option-Field implants under LOCOS regions
This option is to ensure that the dopants go through the field oxide. It is very often
that the deepest ions penetrate through the resist when the shallowest ions go far
enough to get through the field oxide.
(a) Do the ion implantation prior to the LOCOS. In this way, a low-energy (~50
keV) boron can be used which is easily masked by the resist/Si3N4/SiO2 stack.
(b) Do the LOCOS for field oxide. Some of the boron diffuse ahead and some are
incorporated in the field oxide.

Field implant

2-8
Buried and epitaxial layer
This option is to shunt the parasitic PNPN structures with low resistance, preventing
the PNPN devices from turning on.
(a) High-dose (1015 cm-2) is used to implant
N+ buried layer. Due to the thin oxide
layer, a low-energy (~50 keV) is
sufficient. We do not want the implanted
atoms diffuse too far away in subsequent
high temperature process, so we use low
diffusion-coefficient As or Sb.
(b) Remove the resist and do the LOCOS at
1000 oC for 2 hrs.
Ø It drives in the N+ layer to a depth of 1~2 µm.
Ø It grows a thick oxide layer on top of N+ N+ for low-resistance shunt
buried layer.
Ø The thick oxide form a mesa which indicates
the location of buried layer and hence acts as
2-9 an alignment marker for later process.
(c) Strip the Si3N4 and then implant P+
buried layer.
Ø Boron is used for the P+ buried layer.
Ø Boron must go through the thin
oxide but be stopped by the thick
oxide, so the energy is ~50 keV.
Ø Lower dose ~1014 cm-2 is used to
keep it from diffusing too far at high
temperature process.

(d) High temperature drive-in process:

Ø Diffuse both boron and arsenic deeper
into the substrate.
Ø No additional oxidation is needed (in
N2 or Ar atmosphere).
Ø Few hours at 1000 oC for having
similar depth.
2-10
(e) Form a lightly doped (1016 – 1017 cm-3) P and N well above each buried layer :
Ø No precise counterdoping available.
(f) Remove the SiO2 by HF solution.
(g) Epitaxy by CVD:
Ø SiH4 or SiH2Cl2 as Si source and
B2H6 or AsH3 for the P- and N-type
The step is inherent from the oxide and can be
doping.
used for alignment.
Ø Epi at 800 – 1000 oC.
(h) Then follow the LOCOS steps.
(i) Form the P and N wells.
Ø In this step, the temperature
treatment must account for the
upward diffusion from the buried
layer, which determines the
temperature and time.
Now we are ready for the fabrication
2-11 of active device.
 2.2.6 Gate formation
In this section we would like to adjust the most important MOS parameter –
threshold voltage, which is about 0.5 – 0.8V for both the NMOS and PMOS.
(a) The threshold voltage is given by
2e S qN A (2f f )
VTH = VFB + 2f f +
COX
VFB : Gate voltage required to compensate for work function
difference between the gate and substrate
f f : Fermi level with respect to the intrinsic level
e S : Permittivity of Si
N A : Doping concentration The only two parameters
COX : Oxide capacitance you can play around for VTH !

Because NA achieved by ion implantation is not constant (nonuniform profile), we

modify the above equation with the first order approximation of the implant dose QI.

2e S qN A (2f f ) qQI
VTH = VFB + 2f f + +
COX COX
2-12 Therefore, the VTH can be obtained by adjusting QI through (b) to (d), and COX through (e) to (f).
(b) Optical lithography is applied to define the areas where NMOS devices are located.
(c) A boron implant is used to
adjust VTH of NMOS, with
dose of 1012 cm-2 at an energy
of 50 keV.
Ø The dose QI is calculated based
on the above equation to achieve
a given VTH.
Ø The energy is chosen to be high
enough to go through the thin
oxide, but low enough to keep
the boron near the surface.

(d) The same process and

conditions for arsenic
implant to PMOS.

2-13
(e) Strip the original thin oxide (10-20 nm) by using HF etching.
Ø This is because the original oxide is too thick to serve as gate oxide.
Ø This is also because the original oxide is damaged by several implants.
Ø The etching should be timed, not to etch field oxide too much.
(f) A gate oxide (< 10 nm) is grown in O2 at 800 oC for 2 hrs or in H2O at 800 oC
for 25 min.
(g) Deposit the polysilicon gate electrode by LPCVD at 600 oC
for 0.3-0.5 µm: SiH4 à Si + 2H2
(h) Obtain a low-resistance polysilicon gate electrode:
“in situ” dope the polysilicon as it is formed in LPCVD.
Or use high dose (1015 cm-2) to implant poly after the LPCVD. The energy must be
low enough not to penetrate through the poly. A post annealing can enhance the
doping uniformity because dopants rapidly redistribute along the grain
2-14
boundary at elevated temperature.
(i) Chlorine- or bromine-based plasma etching of patterned poly. The plasma has
good selectivity to SiO2. The poly lines can be used as “local interconnects”. For
long interconnect, the RC delays associated with long poly is significant.
2.2.7 Tip or extension (LDD) formation
The conventional MOS devices are operated at 5 V. Scaling down the device
dimension causes increased electric field in the channel. However, the supply
voltage cannot be simply scaled down as the dimension does because then new
ICs are not compatible with older parts, system power has to be redesigned and
circuit noise margins becomes inadequate.

Ex. For 5 V applied across 2-µm

channel MOS device, the electric
field is 2.5x104 V/cm.
N-channel
Decreasing the channel length to
0.2 µm without reducing the
supply voltage increases the field
to 2.5x105 V/cm. This field
gives rise to “impact
ionization”.
2-15
When the channel length is short and the field is high, “short channel effect”
shows up. This effect happens when the drain electric field penetrates through
the channel region and begins to affect the potential barrier between the source
and channel regions. The result is that the gate cannot effectively control the
drain current.
To reduce this problem, the technique of “Lightly Doped Drain (LDD)” is used.
Ø N+N–P profile between the drain and channel in NMOS
Ø P+P–N profile between the drain and channel in PMOS
Ø LDD structure are often called “tip” or “extension” region.
Ø This allows the drain voltage to be dropped over a larger distance than would
be the case if an abrupt N+P junction were form. This reduces the peak value
of the electric field in the near drain region.

(a) For NMOS: phosphorus implant

with dose of 5x1013 – 5x1014 cm-2
at low energy is used.
(b) For PMOS: boron implant with
similar conditions is used.

2-16
(c) Next step is to form a conformal spacer dielectric layer (SiO2 or Si3N4) by LPCVD.
SiH4 + O2 à SiO2 + 2H2 at 400 oC or
SiH2Cl2 + N2O à SiO2 + 2N2 + 2HCl at 900 oC
(d) Anisotropic etching (only vertically but not horizontally) leaves sidewall spacers
along the edges of the polysilicon.
2.2.8 Source/Drain formation
(a) Formation of screen oxide (~10 nm)
In previous step we have stripped the oxide layers which are above the drain and
source region. We need this oxide layer to prevent from “impurity” and
“channeling”. The thin amorphous oxide can randomize the direction of
implanted ions and hence minimize channeling.

(b) For NMOS: Arsenic implant with

higher dose of 2 – 4x1015 cm-2
at an energy of 75 keV
If we use anisotropic etching and etch only
(c) For PMOS: Boron implant with a fixed depth, the thicker spacer oxide will
have a part left. (no mask is required in this step)
higher dose of 1 – 3x1015 cm-2 at
an energy of 5 – 10 keV

2-17
It should be noted that the polysilicon gate regions which is initially N-doped
receive several high-dose implants, including N+ and P+. We normally use N-
type gate in both the PMOS and NMOS. In this case, we must keep the P+ dose
in the current step smaller than that of N+.

(d) Annealing to repair the implant

damage and drive the
junctions to their final depth:
900 oC for 30 min or 1000 oC
for 1 min.
2.2.9 Contact and local interconnect formation
The first level interconnect is often called “local interconnect”
(a) Fist remove the oxide on top of the drain, source, and gate region by short dip in
a buffered HF. Because the oxide is thin, the etching will not much reduce the
thickness of oxide elsewhere.
(b) Sputter a thin layer of Ti, with thickness of 50 – 100 nm.

Annealing drives in the P+ or N+ to the desired depth.

The spacer is important for providing graded

N+N- or P+P- drain junctions.

2-18
(c) Annealing in an N2 ambient at 600 – 700 oC :

Ø On the side where Ti contacts with Si a layer of TiSi2 is formed. It gives low-
resistance contacts to N+ and P+ silicon or polysilicon.
Ø On the side where Ti exposes to N2 a layer of TiN is formed. It is also
conductive, but not as high as normal metals. It can be used for local
interconnect, but not for long-distant interconnect in which significant RC
delays occur.

Ti film
(d) Optical lithography to define the pattern where we want to remain TiN on the
wafer.
(e) The remaining TiN is etched in NH4OH:H2O2:H2O (1:1:5).
(f) Annealing in an Ar ambient at ~800 oC for 1 min to reduce the resistivity of the
TiN and TiSi2 to the final value.

TiN forms a continuous film on top

TiSi2 is only formed in the area contacted with “Si”. The spacer also serves the function of separating
the TiSi2 on the poly gates from contacting the Si
doped regions.

2-19
2.2.10 Multilevel metal formation
Till now, the surface is full of hills and valleys which make the subsequent metal
interconnects discontinuous. We need to flatten the surface topography.
(a) The fist method is to grow a fairly thick SiO2 layer by CVD. The SiO2 layer (~1
µm) is thicker than the largest steps. This SiO2 layer is often doped with
phosphorus and sometimes with boron as well, known as PSG (phosphosilicate
glass) and BPSG (borophosphosilicate glass), respectively.

Ø Phosphorus provides some protection

against mobile ions like Na+ which causes
instabilities in MOS devices. (chap. 4)
Ø Boron reduces the temperature at which
the glass “flows”.
Ø Spinning a layer of photoresist to make the
whole wafer flat because resist is a liquid
and can fill up the valleys well.
Ø Plasma etching with a recipe which has 1:1
etching rate for the resist and SiO2 until the
2-20 underlying SiO2 is etched everywhere.
(b) The second method which is widely
used today is chemical mechanical
polishing (CMP).

(d) Optical lithography to define the pattern

where we want to
make contacts.

(e) SiO2 is then etched by plasma.

(f) Strip the resist.

 (g) Blanket deposition of a thin TiN or
Ti/TiN layer (tens of nm) by CVD.
It provides good adhesion to the
SiO2 and also acts as an effective
diffusion barrier.

(h) Blanket deposition of W layer by

CVD:WF6 + 3H2 à W + 6HF

(i) Use CMP to planarize the wafer. It

removes the W and TiN everywhere
except in the contact holes.

2-21
(j) Al with a small percentage of Si and Cu is deposited and then etched, as shown in
Fig. 2-43. The containing Si is to prevent the absorption of Si from underlying Si-
rich layers. The Cu is added to prevent from electromigration in Al.
(k) Repeating the same procedures multilevel of interconnects can be built.
(l) At the end, the top layer is covered with SiO2 or Si3N4 for protection.

2-22