Maj2-202-T102 - Key
Maj2-202-T102 - Key
Notes:
Do not open the exam book until instructed
Calculators are not allowed (basic, advanced, cell phones, etc.)
Answer all questions
All steps must be shown
Any assumptions made must be clearly stated
(A). For the following Boolean function F(A, B, C, D)=m(0, 1, 2, 5, 6, 7, 8, 9, 10, 12, 13)
(i) Identify all the prime implicants and the essential prime implicants of F. (7+2=9 points)
(ii) Simplify the Boolean function F into a minimal sum-of-products expression. (5 points)
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(B) Consider the following Boolean function F together with the don`t care conditions d
F(A, B, C, D)=m(0, 2, 5, 8, 10), d(A, B, C, D)=m(1, 4, 7, 9, 11, 12, 14, 15)
(i) Simplify the Boolean function F together with the don`t care conditions d, into minimal sum-
of-products expression. (4 points)
(ii) Starting with the sum-of-products expression, implement the function using only NAND gates
and Inverters. (4 points)
(iii) Starting with the sum-of-products expression, implement the function using only NOR gates
and Inverters. (4 points)
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Question 2. (16 Points)
Design a 3-bit decrementer using only basic gates (AND, OR, and NOT). The circuit takes a 3-bit
unsigned number I=I2I1I0 as input and generates a 3-bit output number Z = Z2Z1Z0 and a Valid output
V. Whenever I > 0 the output Z = I-1 and V=1. If I=0, the output is invalid which is indicated by an
output V=0. Derive the simplified Boolean expressions of all outputs.
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Question 3. (12 Points)
driver
WX Y Z
It is required to design a 7-segment display driver whose input is a Hexadecimal digit such that the
resulting 7-seg display is as shown above (Note that HEX digits larger than 9 are displayed as A A,
B b, C C, D d, E E, F F). The driver circuit should generate the 7-segment control
signals (a to g).
If a single decoder and number of OR gates are used to build this driver circuit;
a. What is the minimum size of the decoder? (3 points)
b. What is the minimum a number of OR gates required to build the 7-segment display driver
circuit (3 points)
c. Draw the block diagram of the circuit showing in details how the control signals g and c are
generated. (6 points)
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ii. Represent the decimal value (- 21) in binary using a total of 7 bits in the following notations:
iii. Perform the following signed-2’s complement arithmetic operations in binary using 5 bits. All
numbers given are represented in the signed-2’s complement notation. Indicate clearly the carry values
from the last two stages. For each of the three operations, check and indicate whether overflow
occurred or not.
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i. Implement F using one (1) 3-to-8 decoder, and one (1) NOR gate. Properly label all input and output
lines.
ii. Implement F using two (2) 2-to-4 decoders with enable, one (1) inverter, and one (1) OR gate.
Properly label all input and output lines.
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i. Implement F using an 8-to-1 MUX. Properly label all input and output lines.
ii. Implement F using a 4-to-1 MUX. Show how you obtained your solution, and properly label all
input and output lines.
OR